TBD_TaxiBoard.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000002cc 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000229f4 080002d0 080002d0 000102d0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00004224 08022cc4 08022cc4 00032cc4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 08026ee8 08026ee8 00036ee8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 08026ef0 08026ef0 00036ef0 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .fini_array 00000004 08026ef4 08026ef4 00036ef4 2**2 CONTENTS, ALLOC, LOAD, DATA 6 .data 000000a4 24000000 08026ef8 00040000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 0001a68c 240000a4 08026f9c 000400a4 2**2 ALLOC 8 ._user_heap_stack 00006000 2401a730 08026f9c 0004a730 2**0 ALLOC 9 .lwip_sec 00000160 30000000 30000000 00050000 2**2 ALLOC 10 .ARM.attributes 0000002e 00000000 00000000 000400a4 2**0 CONTENTS, READONLY 11 .comment 00000043 00000000 00000000 000400d2 2**0 CONTENTS, READONLY 12 .debug_info 00046c14 00000000 00000000 00040115 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00009da5 00000000 00000000 00086d29 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00003268 00000000 00000000 00090ad0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 000027cc 00000000 00000000 00093d38 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0004a444 00000000 00000000 00096504 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000516b3 00000000 00000000 000e0948 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00183e93 00000000 00000000 00131ffb 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_frame 0000de4c 00000000 00000000 002b5e90 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .debug_line_str 0000004e 00000000 00000000 002c3cdc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002d0 <__do_global_dtors_aux>: 80002d0: b510 push {r4, lr} 80002d2: 4c05 ldr r4, [pc, #20] ; (80002e8 <__do_global_dtors_aux+0x18>) 80002d4: 7823 ldrb r3, [r4, #0] 80002d6: b933 cbnz r3, 80002e6 <__do_global_dtors_aux+0x16> 80002d8: 4b04 ldr r3, [pc, #16] ; (80002ec <__do_global_dtors_aux+0x1c>) 80002da: b113 cbz r3, 80002e2 <__do_global_dtors_aux+0x12> 80002dc: 4804 ldr r0, [pc, #16] ; (80002f0 <__do_global_dtors_aux+0x20>) 80002de: f3af 8000 nop.w 80002e2: 2301 movs r3, #1 80002e4: 7023 strb r3, [r4, #0] 80002e6: bd10 pop {r4, pc} 80002e8: 240000a4 .word 0x240000a4 80002ec: 00000000 .word 0x00000000 80002f0: 08022cac .word 0x08022cac 080002f4 : 80002f4: b508 push {r3, lr} 80002f6: 4b03 ldr r3, [pc, #12] ; (8000304 ) 80002f8: b11b cbz r3, 8000302 80002fa: 4903 ldr r1, [pc, #12] ; (8000308 ) 80002fc: 4803 ldr r0, [pc, #12] ; (800030c ) 80002fe: f3af 8000 nop.w 8000302: bd08 pop {r3, pc} 8000304: 00000000 .word 0x00000000 8000308: 240000a8 .word 0x240000a8 800030c: 08022cac .word 0x08022cac 08000310 : 8000310: f810 2b01 ldrb.w r2, [r0], #1 8000314: f811 3b01 ldrb.w r3, [r1], #1 8000318: 2a01 cmp r2, #1 800031a: bf28 it cs 800031c: 429a cmpcs r2, r3 800031e: d0f7 beq.n 8000310 8000320: 1ad0 subs r0, r2, r3 8000322: 4770 bx lr 08000324 : 8000324: 4603 mov r3, r0 8000326: f813 2b01 ldrb.w r2, [r3], #1 800032a: 2a00 cmp r2, #0 800032c: d1fb bne.n 8000326 800032e: 1a18 subs r0, r3, r0 8000330: 3801 subs r0, #1 8000332: 4770 bx lr ... 08000340 : 8000340: f001 01ff and.w r1, r1, #255 ; 0xff 8000344: 2a10 cmp r2, #16 8000346: db2b blt.n 80003a0 8000348: f010 0f07 tst.w r0, #7 800034c: d008 beq.n 8000360 800034e: f810 3b01 ldrb.w r3, [r0], #1 8000352: 3a01 subs r2, #1 8000354: 428b cmp r3, r1 8000356: d02d beq.n 80003b4 8000358: f010 0f07 tst.w r0, #7 800035c: b342 cbz r2, 80003b0 800035e: d1f6 bne.n 800034e 8000360: b4f0 push {r4, r5, r6, r7} 8000362: ea41 2101 orr.w r1, r1, r1, lsl #8 8000366: ea41 4101 orr.w r1, r1, r1, lsl #16 800036a: f022 0407 bic.w r4, r2, #7 800036e: f07f 0700 mvns.w r7, #0 8000372: 2300 movs r3, #0 8000374: e8f0 5602 ldrd r5, r6, [r0], #8 8000378: 3c08 subs r4, #8 800037a: ea85 0501 eor.w r5, r5, r1 800037e: ea86 0601 eor.w r6, r6, r1 8000382: fa85 f547 uadd8 r5, r5, r7 8000386: faa3 f587 sel r5, r3, r7 800038a: fa86 f647 uadd8 r6, r6, r7 800038e: faa5 f687 sel r6, r5, r7 8000392: b98e cbnz r6, 80003b8 8000394: d1ee bne.n 8000374 8000396: bcf0 pop {r4, r5, r6, r7} 8000398: f001 01ff and.w r1, r1, #255 ; 0xff 800039c: f002 0207 and.w r2, r2, #7 80003a0: b132 cbz r2, 80003b0 80003a2: f810 3b01 ldrb.w r3, [r0], #1 80003a6: 3a01 subs r2, #1 80003a8: ea83 0301 eor.w r3, r3, r1 80003ac: b113 cbz r3, 80003b4 80003ae: d1f8 bne.n 80003a2 80003b0: 2000 movs r0, #0 80003b2: 4770 bx lr 80003b4: 3801 subs r0, #1 80003b6: 4770 bx lr 80003b8: 2d00 cmp r5, #0 80003ba: bf06 itte eq 80003bc: 4635 moveq r5, r6 80003be: 3803 subeq r0, #3 80003c0: 3807 subne r0, #7 80003c2: f015 0f01 tst.w r5, #1 80003c6: d107 bne.n 80003d8 80003c8: 3001 adds r0, #1 80003ca: f415 7f80 tst.w r5, #256 ; 0x100 80003ce: bf02 ittt eq 80003d0: 3001 addeq r0, #1 80003d2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 80003d6: 3001 addeq r0, #1 80003d8: bcf0 pop {r4, r5, r6, r7} 80003da: 3801 subs r0, #1 80003dc: 4770 bx lr 80003de: bf00 nop 080003e0 <__aeabi_uldivmod>: 80003e0: b953 cbnz r3, 80003f8 <__aeabi_uldivmod+0x18> 80003e2: b94a cbnz r2, 80003f8 <__aeabi_uldivmod+0x18> 80003e4: 2900 cmp r1, #0 80003e6: bf08 it eq 80003e8: 2800 cmpeq r0, #0 80003ea: bf1c itt ne 80003ec: f04f 31ff movne.w r1, #4294967295 80003f0: f04f 30ff movne.w r0, #4294967295 80003f4: f000 b970 b.w 80006d8 <__aeabi_idiv0> 80003f8: f1ad 0c08 sub.w ip, sp, #8 80003fc: e96d ce04 strd ip, lr, [sp, #-16]! 8000400: f000 f806 bl 8000410 <__udivmoddi4> 8000404: f8dd e004 ldr.w lr, [sp, #4] 8000408: e9dd 2302 ldrd r2, r3, [sp, #8] 800040c: b004 add sp, #16 800040e: 4770 bx lr 08000410 <__udivmoddi4>: 8000410: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000414: 9e08 ldr r6, [sp, #32] 8000416: 460d mov r5, r1 8000418: 4604 mov r4, r0 800041a: 460f mov r7, r1 800041c: 2b00 cmp r3, #0 800041e: d14a bne.n 80004b6 <__udivmoddi4+0xa6> 8000420: 428a cmp r2, r1 8000422: 4694 mov ip, r2 8000424: d965 bls.n 80004f2 <__udivmoddi4+0xe2> 8000426: fab2 f382 clz r3, r2 800042a: b143 cbz r3, 800043e <__udivmoddi4+0x2e> 800042c: fa02 fc03 lsl.w ip, r2, r3 8000430: f1c3 0220 rsb r2, r3, #32 8000434: 409f lsls r7, r3 8000436: fa20 f202 lsr.w r2, r0, r2 800043a: 4317 orrs r7, r2 800043c: 409c lsls r4, r3 800043e: ea4f 4e1c mov.w lr, ip, lsr #16 8000442: fa1f f58c uxth.w r5, ip 8000446: fbb7 f1fe udiv r1, r7, lr 800044a: 0c22 lsrs r2, r4, #16 800044c: fb0e 7711 mls r7, lr, r1, r7 8000450: ea42 4207 orr.w r2, r2, r7, lsl #16 8000454: fb01 f005 mul.w r0, r1, r5 8000458: 4290 cmp r0, r2 800045a: d90a bls.n 8000472 <__udivmoddi4+0x62> 800045c: eb1c 0202 adds.w r2, ip, r2 8000460: f101 37ff add.w r7, r1, #4294967295 8000464: f080 811c bcs.w 80006a0 <__udivmoddi4+0x290> 8000468: 4290 cmp r0, r2 800046a: f240 8119 bls.w 80006a0 <__udivmoddi4+0x290> 800046e: 3902 subs r1, #2 8000470: 4462 add r2, ip 8000472: 1a12 subs r2, r2, r0 8000474: b2a4 uxth r4, r4 8000476: fbb2 f0fe udiv r0, r2, lr 800047a: fb0e 2210 mls r2, lr, r0, r2 800047e: ea44 4402 orr.w r4, r4, r2, lsl #16 8000482: fb00 f505 mul.w r5, r0, r5 8000486: 42a5 cmp r5, r4 8000488: d90a bls.n 80004a0 <__udivmoddi4+0x90> 800048a: eb1c 0404 adds.w r4, ip, r4 800048e: f100 32ff add.w r2, r0, #4294967295 8000492: f080 8107 bcs.w 80006a4 <__udivmoddi4+0x294> 8000496: 42a5 cmp r5, r4 8000498: f240 8104 bls.w 80006a4 <__udivmoddi4+0x294> 800049c: 4464 add r4, ip 800049e: 3802 subs r0, #2 80004a0: ea40 4001 orr.w r0, r0, r1, lsl #16 80004a4: 1b64 subs r4, r4, r5 80004a6: 2100 movs r1, #0 80004a8: b11e cbz r6, 80004b2 <__udivmoddi4+0xa2> 80004aa: 40dc lsrs r4, r3 80004ac: 2300 movs r3, #0 80004ae: e9c6 4300 strd r4, r3, [r6] 80004b2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80004b6: 428b cmp r3, r1 80004b8: d908 bls.n 80004cc <__udivmoddi4+0xbc> 80004ba: 2e00 cmp r6, #0 80004bc: f000 80ed beq.w 800069a <__udivmoddi4+0x28a> 80004c0: 2100 movs r1, #0 80004c2: e9c6 0500 strd r0, r5, [r6] 80004c6: 4608 mov r0, r1 80004c8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80004cc: fab3 f183 clz r1, r3 80004d0: 2900 cmp r1, #0 80004d2: d149 bne.n 8000568 <__udivmoddi4+0x158> 80004d4: 42ab cmp r3, r5 80004d6: d302 bcc.n 80004de <__udivmoddi4+0xce> 80004d8: 4282 cmp r2, r0 80004da: f200 80f8 bhi.w 80006ce <__udivmoddi4+0x2be> 80004de: 1a84 subs r4, r0, r2 80004e0: eb65 0203 sbc.w r2, r5, r3 80004e4: 2001 movs r0, #1 80004e6: 4617 mov r7, r2 80004e8: 2e00 cmp r6, #0 80004ea: d0e2 beq.n 80004b2 <__udivmoddi4+0xa2> 80004ec: e9c6 4700 strd r4, r7, [r6] 80004f0: e7df b.n 80004b2 <__udivmoddi4+0xa2> 80004f2: b902 cbnz r2, 80004f6 <__udivmoddi4+0xe6> 80004f4: deff udf #255 ; 0xff 80004f6: fab2 f382 clz r3, r2 80004fa: 2b00 cmp r3, #0 80004fc: f040 8090 bne.w 8000620 <__udivmoddi4+0x210> 8000500: 1a8a subs r2, r1, r2 8000502: ea4f 471c mov.w r7, ip, lsr #16 8000506: fa1f fe8c uxth.w lr, ip 800050a: 2101 movs r1, #1 800050c: fbb2 f5f7 udiv r5, r2, r7 8000510: fb07 2015 mls r0, r7, r5, r2 8000514: 0c22 lsrs r2, r4, #16 8000516: ea42 4200 orr.w r2, r2, r0, lsl #16 800051a: fb0e f005 mul.w r0, lr, r5 800051e: 4290 cmp r0, r2 8000520: d908 bls.n 8000534 <__udivmoddi4+0x124> 8000522: eb1c 0202 adds.w r2, ip, r2 8000526: f105 38ff add.w r8, r5, #4294967295 800052a: d202 bcs.n 8000532 <__udivmoddi4+0x122> 800052c: 4290 cmp r0, r2 800052e: f200 80cb bhi.w 80006c8 <__udivmoddi4+0x2b8> 8000532: 4645 mov r5, r8 8000534: 1a12 subs r2, r2, r0 8000536: b2a4 uxth r4, r4 8000538: fbb2 f0f7 udiv r0, r2, r7 800053c: fb07 2210 mls r2, r7, r0, r2 8000540: ea44 4402 orr.w r4, r4, r2, lsl #16 8000544: fb0e fe00 mul.w lr, lr, r0 8000548: 45a6 cmp lr, r4 800054a: d908 bls.n 800055e <__udivmoddi4+0x14e> 800054c: eb1c 0404 adds.w r4, ip, r4 8000550: f100 32ff add.w r2, r0, #4294967295 8000554: d202 bcs.n 800055c <__udivmoddi4+0x14c> 8000556: 45a6 cmp lr, r4 8000558: f200 80bb bhi.w 80006d2 <__udivmoddi4+0x2c2> 800055c: 4610 mov r0, r2 800055e: eba4 040e sub.w r4, r4, lr 8000562: ea40 4005 orr.w r0, r0, r5, lsl #16 8000566: e79f b.n 80004a8 <__udivmoddi4+0x98> 8000568: f1c1 0720 rsb r7, r1, #32 800056c: 408b lsls r3, r1 800056e: fa22 fc07 lsr.w ip, r2, r7 8000572: ea4c 0c03 orr.w ip, ip, r3 8000576: fa05 f401 lsl.w r4, r5, r1 800057a: fa20 f307 lsr.w r3, r0, r7 800057e: 40fd lsrs r5, r7 8000580: ea4f 491c mov.w r9, ip, lsr #16 8000584: 4323 orrs r3, r4 8000586: fbb5 f8f9 udiv r8, r5, r9 800058a: fa1f fe8c uxth.w lr, ip 800058e: fb09 5518 mls r5, r9, r8, r5 8000592: 0c1c lsrs r4, r3, #16 8000594: ea44 4405 orr.w r4, r4, r5, lsl #16 8000598: fb08 f50e mul.w r5, r8, lr 800059c: 42a5 cmp r5, r4 800059e: fa02 f201 lsl.w r2, r2, r1 80005a2: fa00 f001 lsl.w r0, r0, r1 80005a6: d90b bls.n 80005c0 <__udivmoddi4+0x1b0> 80005a8: eb1c 0404 adds.w r4, ip, r4 80005ac: f108 3aff add.w sl, r8, #4294967295 80005b0: f080 8088 bcs.w 80006c4 <__udivmoddi4+0x2b4> 80005b4: 42a5 cmp r5, r4 80005b6: f240 8085 bls.w 80006c4 <__udivmoddi4+0x2b4> 80005ba: f1a8 0802 sub.w r8, r8, #2 80005be: 4464 add r4, ip 80005c0: 1b64 subs r4, r4, r5 80005c2: b29d uxth r5, r3 80005c4: fbb4 f3f9 udiv r3, r4, r9 80005c8: fb09 4413 mls r4, r9, r3, r4 80005cc: ea45 4404 orr.w r4, r5, r4, lsl #16 80005d0: fb03 fe0e mul.w lr, r3, lr 80005d4: 45a6 cmp lr, r4 80005d6: d908 bls.n 80005ea <__udivmoddi4+0x1da> 80005d8: eb1c 0404 adds.w r4, ip, r4 80005dc: f103 35ff add.w r5, r3, #4294967295 80005e0: d26c bcs.n 80006bc <__udivmoddi4+0x2ac> 80005e2: 45a6 cmp lr, r4 80005e4: d96a bls.n 80006bc <__udivmoddi4+0x2ac> 80005e6: 3b02 subs r3, #2 80005e8: 4464 add r4, ip 80005ea: ea43 4308 orr.w r3, r3, r8, lsl #16 80005ee: fba3 9502 umull r9, r5, r3, r2 80005f2: eba4 040e sub.w r4, r4, lr 80005f6: 42ac cmp r4, r5 80005f8: 46c8 mov r8, r9 80005fa: 46ae mov lr, r5 80005fc: d356 bcc.n 80006ac <__udivmoddi4+0x29c> 80005fe: d053 beq.n 80006a8 <__udivmoddi4+0x298> 8000600: b156 cbz r6, 8000618 <__udivmoddi4+0x208> 8000602: ebb0 0208 subs.w r2, r0, r8 8000606: eb64 040e sbc.w r4, r4, lr 800060a: fa04 f707 lsl.w r7, r4, r7 800060e: 40ca lsrs r2, r1 8000610: 40cc lsrs r4, r1 8000612: 4317 orrs r7, r2 8000614: e9c6 7400 strd r7, r4, [r6] 8000618: 4618 mov r0, r3 800061a: 2100 movs r1, #0 800061c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8000620: f1c3 0120 rsb r1, r3, #32 8000624: fa02 fc03 lsl.w ip, r2, r3 8000628: fa20 f201 lsr.w r2, r0, r1 800062c: fa25 f101 lsr.w r1, r5, r1 8000630: 409d lsls r5, r3 8000632: 432a orrs r2, r5 8000634: ea4f 471c mov.w r7, ip, lsr #16 8000638: fa1f fe8c uxth.w lr, ip 800063c: fbb1 f0f7 udiv r0, r1, r7 8000640: fb07 1510 mls r5, r7, r0, r1 8000644: 0c11 lsrs r1, r2, #16 8000646: ea41 4105 orr.w r1, r1, r5, lsl #16 800064a: fb00 f50e mul.w r5, r0, lr 800064e: 428d cmp r5, r1 8000650: fa04 f403 lsl.w r4, r4, r3 8000654: d908 bls.n 8000668 <__udivmoddi4+0x258> 8000656: eb1c 0101 adds.w r1, ip, r1 800065a: f100 38ff add.w r8, r0, #4294967295 800065e: d22f bcs.n 80006c0 <__udivmoddi4+0x2b0> 8000660: 428d cmp r5, r1 8000662: d92d bls.n 80006c0 <__udivmoddi4+0x2b0> 8000664: 3802 subs r0, #2 8000666: 4461 add r1, ip 8000668: 1b49 subs r1, r1, r5 800066a: b292 uxth r2, r2 800066c: fbb1 f5f7 udiv r5, r1, r7 8000670: fb07 1115 mls r1, r7, r5, r1 8000674: ea42 4201 orr.w r2, r2, r1, lsl #16 8000678: fb05 f10e mul.w r1, r5, lr 800067c: 4291 cmp r1, r2 800067e: d908 bls.n 8000692 <__udivmoddi4+0x282> 8000680: eb1c 0202 adds.w r2, ip, r2 8000684: f105 38ff add.w r8, r5, #4294967295 8000688: d216 bcs.n 80006b8 <__udivmoddi4+0x2a8> 800068a: 4291 cmp r1, r2 800068c: d914 bls.n 80006b8 <__udivmoddi4+0x2a8> 800068e: 3d02 subs r5, #2 8000690: 4462 add r2, ip 8000692: 1a52 subs r2, r2, r1 8000694: ea45 4100 orr.w r1, r5, r0, lsl #16 8000698: e738 b.n 800050c <__udivmoddi4+0xfc> 800069a: 4631 mov r1, r6 800069c: 4630 mov r0, r6 800069e: e708 b.n 80004b2 <__udivmoddi4+0xa2> 80006a0: 4639 mov r1, r7 80006a2: e6e6 b.n 8000472 <__udivmoddi4+0x62> 80006a4: 4610 mov r0, r2 80006a6: e6fb b.n 80004a0 <__udivmoddi4+0x90> 80006a8: 4548 cmp r0, r9 80006aa: d2a9 bcs.n 8000600 <__udivmoddi4+0x1f0> 80006ac: ebb9 0802 subs.w r8, r9, r2 80006b0: eb65 0e0c sbc.w lr, r5, ip 80006b4: 3b01 subs r3, #1 80006b6: e7a3 b.n 8000600 <__udivmoddi4+0x1f0> 80006b8: 4645 mov r5, r8 80006ba: e7ea b.n 8000692 <__udivmoddi4+0x282> 80006bc: 462b mov r3, r5 80006be: e794 b.n 80005ea <__udivmoddi4+0x1da> 80006c0: 4640 mov r0, r8 80006c2: e7d1 b.n 8000668 <__udivmoddi4+0x258> 80006c4: 46d0 mov r8, sl 80006c6: e77b b.n 80005c0 <__udivmoddi4+0x1b0> 80006c8: 3d02 subs r5, #2 80006ca: 4462 add r2, ip 80006cc: e732 b.n 8000534 <__udivmoddi4+0x124> 80006ce: 4608 mov r0, r1 80006d0: e70a b.n 80004e8 <__udivmoddi4+0xd8> 80006d2: 4464 add r4, ip 80006d4: 3802 subs r0, #2 80006d6: e742 b.n 800055e <__udivmoddi4+0x14e> 080006d8 <__aeabi_idiv0>: 80006d8: 4770 bx lr 80006da: bf00 nop 080006dc : /* Hook prototypes */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); /* USER CODE BEGIN 4 */ __weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 80006dc: b480 push {r7} 80006de: b083 sub sp, #12 80006e0: af00 add r7, sp, #0 80006e2: 6078 str r0, [r7, #4] 80006e4: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 80006e6: bf00 nop 80006e8: 370c adds r7, #12 80006ea: 46bd mov sp, r7 80006ec: f85d 7b04 ldr.w r7, [sp], #4 80006f0: 4770 bx lr ... 080006f4 : /* USER CODE BEGIN GET_IDLE_TASK_MEMORY */ static StaticTask_t xIdleTaskTCBBuffer; static StackType_t xIdleStack[configMINIMAL_STACK_SIZE]; void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) { 80006f4: b480 push {r7} 80006f6: b085 sub sp, #20 80006f8: af00 add r7, sp, #0 80006fa: 60f8 str r0, [r7, #12] 80006fc: 60b9 str r1, [r7, #8] 80006fe: 607a str r2, [r7, #4] *ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer; 8000700: 68fb ldr r3, [r7, #12] 8000702: 4a07 ldr r2, [pc, #28] ; (8000720 ) 8000704: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &xIdleStack[0]; 8000706: 68bb ldr r3, [r7, #8] 8000708: 4a06 ldr r2, [pc, #24] ; (8000724 ) 800070a: 601a str r2, [r3, #0] *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; 800070c: 687b ldr r3, [r7, #4] 800070e: f44f 7280 mov.w r2, #256 ; 0x100 8000712: 601a str r2, [r3, #0] /* place for user code */ } 8000714: bf00 nop 8000716: 3714 adds r7, #20 8000718: 46bd mov sp, r7 800071a: f85d 7b04 ldr.w r7, [sp], #4 800071e: 4770 bx lr 8000720: 240000c0 .word 0x240000c0 8000724: 24000114 .word 0x24000114 08000728 : /* USER CODE BEGIN GET_TIMER_TASK_MEMORY */ static StaticTask_t xTimerTaskTCBBuffer; static StackType_t xTimerStack[configTIMER_TASK_STACK_DEPTH]; void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) { 8000728: b480 push {r7} 800072a: b085 sub sp, #20 800072c: af00 add r7, sp, #0 800072e: 60f8 str r0, [r7, #12] 8000730: 60b9 str r1, [r7, #8] 8000732: 607a str r2, [r7, #4] *ppxTimerTaskTCBBuffer = &xTimerTaskTCBBuffer; 8000734: 68fb ldr r3, [r7, #12] 8000736: 4a07 ldr r2, [pc, #28] ; (8000754 ) 8000738: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &xTimerStack[0]; 800073a: 68bb ldr r3, [r7, #8] 800073c: 4a06 ldr r2, [pc, #24] ; (8000758 ) 800073e: 601a str r2, [r3, #0] *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; 8000740: 687b ldr r3, [r7, #4] 8000742: f44f 7200 mov.w r2, #512 ; 0x200 8000746: 601a str r2, [r3, #0] /* place for user code */ } 8000748: bf00 nop 800074a: 3714 adds r7, #20 800074c: 46bd mov sp, r7 800074e: f85d 7b04 ldr.w r7, [sp], #4 8000752: 4770 bx lr 8000754: 24000514 .word 0x24000514 8000758: 24000568 .word 0x24000568 0800075c : \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { 800075c: b480 push {r7} 800075e: b083 sub sp, #12 8000760: af00 add r7, sp, #0 8000762: 6078 str r0, [r7, #4] if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 8000764: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000 8000768: f8d3 3e80 ldr.w r3, [r3, #3712] ; 0xe80 800076c: f003 0301 and.w r3, r3, #1 8000770: 2b00 cmp r3, #0 8000772: d013 beq.n 800079c ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 8000774: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000 8000778: f8d3 3e00 ldr.w r3, [r3, #3584] ; 0xe00 800077c: f003 0301 and.w r3, r3, #1 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 8000780: 2b00 cmp r3, #0 8000782: d00b beq.n 800079c { while (ITM->PORT[0U].u32 == 0UL) 8000784: e000 b.n 8000788 { __NOP(); 8000786: bf00 nop while (ITM->PORT[0U].u32 == 0UL) 8000788: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000 800078c: 681b ldr r3, [r3, #0] 800078e: 2b00 cmp r3, #0 8000790: d0f9 beq.n 8000786 } ITM->PORT[0U].u8 = (uint8_t)ch; 8000792: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000 8000796: 687a ldr r2, [r7, #4] 8000798: b2d2 uxtb r2, r2 800079a: 701a strb r2, [r3, #0] } return (ch); 800079c: 687b ldr r3, [r7, #4] } 800079e: 4618 mov r0, r3 80007a0: 370c adds r7, #12 80007a2: 46bd mov sp, r7 80007a4: f85d 7b04 ldr.w r7, [sp], #4 80007a8: 4770 bx lr 080007aa <_write>: /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ int _write(int32_t file, uint8_t *ptr, int32_t len) { 80007aa: b580 push {r7, lr} 80007ac: b086 sub sp, #24 80007ae: af00 add r7, sp, #0 80007b0: 60f8 str r0, [r7, #12] 80007b2: 60b9 str r1, [r7, #8] 80007b4: 607a str r2, [r7, #4] for (int32_t i = 0; i < len; ++i) 80007b6: 2300 movs r3, #0 80007b8: 617b str r3, [r7, #20] 80007ba: e009 b.n 80007d0 <_write+0x26> ITM_SendChar(*ptr++); 80007bc: 68bb ldr r3, [r7, #8] 80007be: 1c5a adds r2, r3, #1 80007c0: 60ba str r2, [r7, #8] 80007c2: 781b ldrb r3, [r3, #0] 80007c4: 4618 mov r0, r3 80007c6: f7ff ffc9 bl 800075c for (int32_t i = 0; i < len; ++i) 80007ca: 697b ldr r3, [r7, #20] 80007cc: 3301 adds r3, #1 80007ce: 617b str r3, [r7, #20] 80007d0: 697a ldr r2, [r7, #20] 80007d2: 687b ldr r3, [r7, #4] 80007d4: 429a cmp r2, r3 80007d6: dbf1 blt.n 80007bc <_write+0x12> return len; 80007d8: 687b ldr r3, [r7, #4] } 80007da: 4618 mov r0, r3 80007dc: 3718 adds r7, #24 80007de: 46bd mov sp, r7 80007e0: bd80 pop {r7, pc} ... 080007e4
: /** * @brief The application entry point. * @retval int */ int main(void) { 80007e4: b5b0 push {r4, r5, r7, lr} 80007e6: b092 sub sp, #72 ; 0x48 80007e8: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); 80007ea: f000 fe13 bl 8001414 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80007ee: 4b55 ldr r3, [pc, #340] ; (8000944 ) 80007f0: 695b ldr r3, [r3, #20] 80007f2: f403 3300 and.w r3, r3, #131072 ; 0x20000 80007f6: 2b00 cmp r3, #0 80007f8: d11b bne.n 8000832 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 80007fa: f3bf 8f4f dsb sy } 80007fe: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000800: f3bf 8f6f isb sy } 8000804: bf00 nop SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 8000806: 4b4f ldr r3, [pc, #316] ; (8000944 ) 8000808: 2200 movs r2, #0 800080a: f8c3 2250 str.w r2, [r3, #592] ; 0x250 __ASM volatile ("dsb 0xF":::"memory"); 800080e: f3bf 8f4f dsb sy } 8000812: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000814: f3bf 8f6f isb sy } 8000818: bf00 nop SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 800081a: 4b4a ldr r3, [pc, #296] ; (8000944 ) 800081c: 695b ldr r3, [r3, #20] 800081e: 4a49 ldr r2, [pc, #292] ; (8000944 ) 8000820: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000824: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000826: f3bf 8f4f dsb sy } 800082a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800082c: f3bf 8f6f isb sy } 8000830: e000 b.n 8000834 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 8000832: bf00 nop if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000834: 4b43 ldr r3, [pc, #268] ; (8000944 ) 8000836: 695b ldr r3, [r3, #20] 8000838: f403 3380 and.w r3, r3, #65536 ; 0x10000 800083c: 2b00 cmp r3, #0 800083e: d138 bne.n 80008b2 SCB->CSSELR = 0U; /* select Level 1 data cache */ 8000840: 4b40 ldr r3, [pc, #256] ; (8000944 ) 8000842: 2200 movs r2, #0 8000844: f8c3 2084 str.w r2, [r3, #132] ; 0x84 __ASM volatile ("dsb 0xF":::"memory"); 8000848: f3bf 8f4f dsb sy } 800084c: bf00 nop ccsidr = SCB->CCSIDR; 800084e: 4b3d ldr r3, [pc, #244] ; (8000944 ) 8000850: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8000854: 647b str r3, [r7, #68] ; 0x44 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 8000856: 6c7b ldr r3, [r7, #68] ; 0x44 8000858: 0b5b lsrs r3, r3, #13 800085a: f3c3 030e ubfx r3, r3, #0, #15 800085e: 643b str r3, [r7, #64] ; 0x40 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 8000860: 6c7b ldr r3, [r7, #68] ; 0x44 8000862: 08db lsrs r3, r3, #3 8000864: f3c3 0309 ubfx r3, r3, #0, #10 8000868: 63fb str r3, [r7, #60] ; 0x3c SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 800086a: 6c3b ldr r3, [r7, #64] ; 0x40 800086c: 015a lsls r2, r3, #5 800086e: f643 73e0 movw r3, #16352 ; 0x3fe0 8000872: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 8000874: 6bfa ldr r2, [r7, #60] ; 0x3c 8000876: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 8000878: 4932 ldr r1, [pc, #200] ; (8000944 ) 800087a: 4313 orrs r3, r2 800087c: f8c1 3260 str.w r3, [r1, #608] ; 0x260 } while (ways-- != 0U); 8000880: 6bfb ldr r3, [r7, #60] ; 0x3c 8000882: 1e5a subs r2, r3, #1 8000884: 63fa str r2, [r7, #60] ; 0x3c 8000886: 2b00 cmp r3, #0 8000888: d1ef bne.n 800086a } while(sets-- != 0U); 800088a: 6c3b ldr r3, [r7, #64] ; 0x40 800088c: 1e5a subs r2, r3, #1 800088e: 643a str r2, [r7, #64] ; 0x40 8000890: 2b00 cmp r3, #0 8000892: d1e5 bne.n 8000860 __ASM volatile ("dsb 0xF":::"memory"); 8000894: f3bf 8f4f dsb sy } 8000898: bf00 nop SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 800089a: 4b2a ldr r3, [pc, #168] ; (8000944 ) 800089c: 695b ldr r3, [r3, #20] 800089e: 4a29 ldr r2, [pc, #164] ; (8000944 ) 80008a0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80008a4: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 80008a6: f3bf 8f4f dsb sy } 80008aa: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80008ac: f3bf 8f6f isb sy } 80008b0: e000 b.n 80008b4 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80008b2: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80008b4: f001 fd06 bl 80022c4 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80008b8: f000 f84e bl 8000958 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80008bc: f000 fbc2 bl 8001044 MX_DMA_Init(); 80008c0: f000 fb3c bl 8000f3c MX_MDMA_Init(); 80008c4: f000 fb5a bl 8000f7c MX_FDCAN3_Init(); 80008c8: f000 f980 bl 8000bcc MX_SDMMC1_SD_Init(); 80008cc: f000 f9e4 bl 8000c98 MX_TIM3_Init(); 80008d0: f000 fa02 bl 8000cd8 MX_UART4_Init(); 80008d4: f000 fa4e bl 8000d74 MX_UART7_Init(); 80008d8: f000 fa98 bl 8000e0c MX_FDCAN1_Init(); 80008dc: f000 f8aa bl 8000a34 MX_FDCAN2_Init(); 80008e0: f000 f90e bl 8000b00 MX_FATFS_Init(); 80008e4: f00e f8b4 bl 800ea50 MX_UART8_Init(); 80008e8: f000 fadc bl 8000ea4 /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* definition and creation of defaultTask */ osThreadStaticDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 4096, defaultTaskBuffer, &defaultTaskControlBlock); 80008ec: 4b16 ldr r3, [pc, #88] ; (8000948 ) 80008ee: f107 0420 add.w r4, r7, #32 80008f2: 461d mov r5, r3 80008f4: cd0f ldmia r5!, {r0, r1, r2, r3} 80008f6: c40f stmia r4!, {r0, r1, r2, r3} 80008f8: e895 0007 ldmia.w r5, {r0, r1, r2} 80008fc: e884 0007 stmia.w r4, {r0, r1, r2} defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL); 8000900: f107 0320 add.w r3, r7, #32 8000904: 2100 movs r1, #0 8000906: 4618 mov r0, r3 8000908: f00f fcee bl 80102e8 800090c: 4603 mov r3, r0 800090e: 4a0f ldr r2, [pc, #60] ; (800094c ) 8000910: 6013 str r3, [r2, #0] /* definition and creation of debugTask */ osThreadStaticDef(debugTask, StartDebugTask, osPriorityNormal, 0, 2048, debugTaskBuffer, &debugTaskControlBlock); 8000912: 4b0f ldr r3, [pc, #60] ; (8000950 ) 8000914: 1d3c adds r4, r7, #4 8000916: 461d mov r5, r3 8000918: cd0f ldmia r5!, {r0, r1, r2, r3} 800091a: c40f stmia r4!, {r0, r1, r2, r3} 800091c: e895 0007 ldmia.w r5, {r0, r1, r2} 8000920: e884 0007 stmia.w r4, {r0, r1, r2} debugTaskHandle = osThreadCreate(osThread(debugTask), NULL); 8000924: 1d3b adds r3, r7, #4 8000926: 2100 movs r1, #0 8000928: 4618 mov r0, r3 800092a: f00f fcdd bl 80102e8 800092e: 4603 mov r3, r0 8000930: 4a08 ldr r2, [pc, #32] ; (8000954 ) 8000932: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ /* USER CODE END RTOS_THREADS */ /* Start scheduler */ osKernelStart(); 8000934: f00f fcb5 bl 80102a2 8000938: 2300 movs r3, #0 /* USER CODE BEGIN 3 */ } #endif /* USER CODE END 3 */ } 800093a: 4618 mov r0, r3 800093c: 3748 adds r7, #72 ; 0x48 800093e: 46bd mov sp, r7 8000940: bdb0 pop {r4, r5, r7, pc} 8000942: bf00 nop 8000944: e000ed00 .word 0xe000ed00 8000948: 08022cf0 .word 0x08022cf0 800094c: 240012b0 .word 0x240012b0 8000950: 08022d18 .word 0x08022d18 8000954: 24005308 .word 0x24005308 08000958 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000958: b580 push {r7, lr} 800095a: b09c sub sp, #112 ; 0x70 800095c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800095e: f107 0324 add.w r3, r7, #36 ; 0x24 8000962: 224c movs r2, #76 ; 0x4c 8000964: 2100 movs r1, #0 8000966: 4618 mov r0, r3 8000968: f021 f9ba bl 8021ce0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800096c: 1d3b adds r3, r7, #4 800096e: 2220 movs r2, #32 8000970: 2100 movs r1, #0 8000972: 4618 mov r0, r3 8000974: f021 f9b4 bl 8021ce0 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000978: 2002 movs r0, #2 800097a: f006 fb7d bl 8007078 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); 800097e: 2300 movs r3, #0 8000980: 603b str r3, [r7, #0] 8000982: 4b2b ldr r3, [pc, #172] ; (8000a30 ) 8000984: 699b ldr r3, [r3, #24] 8000986: 4a2a ldr r2, [pc, #168] ; (8000a30 ) 8000988: f423 4340 bic.w r3, r3, #49152 ; 0xc000 800098c: 6193 str r3, [r2, #24] 800098e: 4b28 ldr r3, [pc, #160] ; (8000a30 ) 8000990: 699b ldr r3, [r3, #24] 8000992: f403 4340 and.w r3, r3, #49152 ; 0xc000 8000996: 603b str r3, [r7, #0] 8000998: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 800099a: bf00 nop 800099c: 4b24 ldr r3, [pc, #144] ; (8000a30 ) 800099e: 699b ldr r3, [r3, #24] 80009a0: f403 5300 and.w r3, r3, #8192 ; 0x2000 80009a4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80009a8: d1f8 bne.n 800099c /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 80009aa: 2301 movs r3, #1 80009ac: 627b str r3, [r7, #36] ; 0x24 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80009ae: f44f 3380 mov.w r3, #65536 ; 0x10000 80009b2: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80009b4: 2302 movs r3, #2 80009b6: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80009b8: 2302 movs r3, #2 80009ba: 64fb str r3, [r7, #76] ; 0x4c RCC_OscInitStruct.PLL.PLLM = 5; 80009bc: 2305 movs r3, #5 80009be: 653b str r3, [r7, #80] ; 0x50 RCC_OscInitStruct.PLL.PLLN = 96; 80009c0: 2360 movs r3, #96 ; 0x60 80009c2: 657b str r3, [r7, #84] ; 0x54 RCC_OscInitStruct.PLL.PLLP = 1; 80009c4: 2301 movs r3, #1 80009c6: 65bb str r3, [r7, #88] ; 0x58 RCC_OscInitStruct.PLL.PLLQ = 4; 80009c8: 2304 movs r3, #4 80009ca: 65fb str r3, [r7, #92] ; 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 80009cc: 2302 movs r3, #2 80009ce: 663b str r3, [r7, #96] ; 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 80009d0: 2308 movs r3, #8 80009d2: 667b str r3, [r7, #100] ; 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 80009d4: 2300 movs r3, #0 80009d6: 66bb str r3, [r7, #104] ; 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 80009d8: 2300 movs r3, #0 80009da: 66fb str r3, [r7, #108] ; 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80009dc: f107 0324 add.w r3, r7, #36 ; 0x24 80009e0: 4618 mov r0, r3 80009e2: f006 fb83 bl 80070ec 80009e6: 4603 mov r3, r0 80009e8: 2b00 cmp r3, #0 80009ea: d001 beq.n 80009f0 { Error_Handler(); 80009ec: f000 fd82 bl 80014f4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80009f0: 233f movs r3, #63 ; 0x3f 80009f2: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80009f4: 2303 movs r3, #3 80009f6: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 80009f8: 2300 movs r3, #0 80009fa: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 80009fc: 2308 movs r3, #8 80009fe: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 8000a00: 2340 movs r3, #64 ; 0x40 8000a02: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 8000a04: 2340 movs r3, #64 ; 0x40 8000a06: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000a08: f44f 6380 mov.w r3, #1024 ; 0x400 8000a0c: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000a0e: 2340 movs r3, #64 ; 0x40 8000a10: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) 8000a12: 1d3b adds r3, r7, #4 8000a14: 2103 movs r1, #3 8000a16: 4618 mov r0, r3 8000a18: f006 ff42 bl 80078a0 8000a1c: 4603 mov r3, r0 8000a1e: 2b00 cmp r3, #0 8000a20: d001 beq.n 8000a26 { Error_Handler(); 8000a22: f000 fd67 bl 80014f4 } } 8000a26: bf00 nop 8000a28: 3770 adds r7, #112 ; 0x70 8000a2a: 46bd mov sp, r7 8000a2c: bd80 pop {r7, pc} 8000a2e: bf00 nop 8000a30: 58024800 .word 0x58024800 08000a34 : * @brief FDCAN1 Initialization Function * @param None * @retval None */ static void MX_FDCAN1_Init(void) { 8000a34: b580 push {r7, lr} 8000a36: af00 add r7, sp, #0 /* USER CODE END FDCAN1_Init 0 */ /* USER CODE BEGIN FDCAN1_Init 1 */ /* USER CODE END FDCAN1_Init 1 */ hfdcan1.Instance = FDCAN1; 8000a38: 4b2f ldr r3, [pc, #188] ; (8000af8 ) 8000a3a: 4a30 ldr r2, [pc, #192] ; (8000afc ) 8000a3c: 601a str r2, [r3, #0] hfdcan1.Init.FrameFormat = FDCAN_FRAME_FD_BRS; 8000a3e: 4b2e ldr r3, [pc, #184] ; (8000af8 ) 8000a40: f44f 7240 mov.w r2, #768 ; 0x300 8000a44: 609a str r2, [r3, #8] hfdcan1.Init.Mode = FDCAN_MODE_NORMAL; 8000a46: 4b2c ldr r3, [pc, #176] ; (8000af8 ) 8000a48: 2200 movs r2, #0 8000a4a: 60da str r2, [r3, #12] hfdcan1.Init.AutoRetransmission = DISABLE; 8000a4c: 4b2a ldr r3, [pc, #168] ; (8000af8 ) 8000a4e: 2200 movs r2, #0 8000a50: 741a strb r2, [r3, #16] hfdcan1.Init.TransmitPause = DISABLE; 8000a52: 4b29 ldr r3, [pc, #164] ; (8000af8 ) 8000a54: 2200 movs r2, #0 8000a56: 745a strb r2, [r3, #17] hfdcan1.Init.ProtocolException = DISABLE; 8000a58: 4b27 ldr r3, [pc, #156] ; (8000af8 ) 8000a5a: 2200 movs r2, #0 8000a5c: 749a strb r2, [r3, #18] hfdcan1.Init.NominalPrescaler = 6; 8000a5e: 4b26 ldr r3, [pc, #152] ; (8000af8 ) 8000a60: 2206 movs r2, #6 8000a62: 615a str r2, [r3, #20] hfdcan1.Init.NominalSyncJumpWidth = 4; 8000a64: 4b24 ldr r3, [pc, #144] ; (8000af8 ) 8000a66: 2204 movs r2, #4 8000a68: 619a str r2, [r3, #24] hfdcan1.Init.NominalTimeSeg1 = 29; 8000a6a: 4b23 ldr r3, [pc, #140] ; (8000af8 ) 8000a6c: 221d movs r2, #29 8000a6e: 61da str r2, [r3, #28] hfdcan1.Init.NominalTimeSeg2 = 10; 8000a70: 4b21 ldr r3, [pc, #132] ; (8000af8 ) 8000a72: 220a movs r2, #10 8000a74: 621a str r2, [r3, #32] hfdcan1.Init.DataPrescaler = 4; 8000a76: 4b20 ldr r3, [pc, #128] ; (8000af8 ) 8000a78: 2204 movs r2, #4 8000a7a: 625a str r2, [r3, #36] ; 0x24 hfdcan1.Init.DataSyncJumpWidth = 4; 8000a7c: 4b1e ldr r3, [pc, #120] ; (8000af8 ) 8000a7e: 2204 movs r2, #4 8000a80: 629a str r2, [r3, #40] ; 0x28 hfdcan1.Init.DataTimeSeg1 = 11; 8000a82: 4b1d ldr r3, [pc, #116] ; (8000af8 ) 8000a84: 220b movs r2, #11 8000a86: 62da str r2, [r3, #44] ; 0x2c hfdcan1.Init.DataTimeSeg2 = 3; 8000a88: 4b1b ldr r3, [pc, #108] ; (8000af8 ) 8000a8a: 2203 movs r2, #3 8000a8c: 631a str r2, [r3, #48] ; 0x30 hfdcan1.Init.MessageRAMOffset = 0; 8000a8e: 4b1a ldr r3, [pc, #104] ; (8000af8 ) 8000a90: 2200 movs r2, #0 8000a92: 635a str r2, [r3, #52] ; 0x34 hfdcan1.Init.StdFiltersNbr = 0; 8000a94: 4b18 ldr r3, [pc, #96] ; (8000af8 ) 8000a96: 2200 movs r2, #0 8000a98: 639a str r2, [r3, #56] ; 0x38 hfdcan1.Init.ExtFiltersNbr = 0; 8000a9a: 4b17 ldr r3, [pc, #92] ; (8000af8 ) 8000a9c: 2200 movs r2, #0 8000a9e: 63da str r2, [r3, #60] ; 0x3c hfdcan1.Init.RxFifo0ElmtsNbr = 8; 8000aa0: 4b15 ldr r3, [pc, #84] ; (8000af8 ) 8000aa2: 2208 movs r2, #8 8000aa4: 641a str r2, [r3, #64] ; 0x40 hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64; 8000aa6: 4b14 ldr r3, [pc, #80] ; (8000af8 ) 8000aa8: 2212 movs r2, #18 8000aaa: 645a str r2, [r3, #68] ; 0x44 hfdcan1.Init.RxFifo1ElmtsNbr = 0; 8000aac: 4b12 ldr r3, [pc, #72] ; (8000af8 ) 8000aae: 2200 movs r2, #0 8000ab0: 649a str r2, [r3, #72] ; 0x48 hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64; 8000ab2: 4b11 ldr r3, [pc, #68] ; (8000af8 ) 8000ab4: 2212 movs r2, #18 8000ab6: 64da str r2, [r3, #76] ; 0x4c hfdcan1.Init.RxBuffersNbr = 0; 8000ab8: 4b0f ldr r3, [pc, #60] ; (8000af8 ) 8000aba: 2200 movs r2, #0 8000abc: 651a str r2, [r3, #80] ; 0x50 hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_64; 8000abe: 4b0e ldr r3, [pc, #56] ; (8000af8 ) 8000ac0: 2212 movs r2, #18 8000ac2: 655a str r2, [r3, #84] ; 0x54 hfdcan1.Init.TxEventsNbr = 8; 8000ac4: 4b0c ldr r3, [pc, #48] ; (8000af8 ) 8000ac6: 2208 movs r2, #8 8000ac8: 659a str r2, [r3, #88] ; 0x58 hfdcan1.Init.TxBuffersNbr = 0; 8000aca: 4b0b ldr r3, [pc, #44] ; (8000af8 ) 8000acc: 2200 movs r2, #0 8000ace: 65da str r2, [r3, #92] ; 0x5c hfdcan1.Init.TxFifoQueueElmtsNbr = 8; 8000ad0: 4b09 ldr r3, [pc, #36] ; (8000af8 ) 8000ad2: 2208 movs r2, #8 8000ad4: 661a str r2, [r3, #96] ; 0x60 hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; 8000ad6: 4b08 ldr r3, [pc, #32] ; (8000af8 ) 8000ad8: 2200 movs r2, #0 8000ada: 665a str r2, [r3, #100] ; 0x64 hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_64; 8000adc: 4b06 ldr r3, [pc, #24] ; (8000af8 ) 8000ade: 2212 movs r2, #18 8000ae0: 669a str r2, [r3, #104] ; 0x68 if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) 8000ae2: 4805 ldr r0, [pc, #20] ; (8000af8 ) 8000ae4: f004 fffe bl 8005ae4 8000ae8: 4603 mov r3, r0 8000aea: 2b00 cmp r3, #0 8000aec: d001 beq.n 8000af2 { Error_Handler(); 8000aee: f000 fd01 bl 80014f4 } /* USER CODE BEGIN FDCAN1_Init 2 */ /* USER CODE END FDCAN1_Init 2 */ } 8000af2: bf00 nop 8000af4: bd80 pop {r7, pc} 8000af6: bf00 nop 8000af8: 24000d68 .word 0x24000d68 8000afc: 4000a000 .word 0x4000a000 08000b00 : * @brief FDCAN2 Initialization Function * @param None * @retval None */ static void MX_FDCAN2_Init(void) { 8000b00: b580 push {r7, lr} 8000b02: af00 add r7, sp, #0 /* USER CODE END FDCAN2_Init 0 */ /* USER CODE BEGIN FDCAN2_Init 1 */ /* USER CODE END FDCAN2_Init 1 */ hfdcan2.Instance = FDCAN2; 8000b04: 4b2f ldr r3, [pc, #188] ; (8000bc4 ) 8000b06: 4a30 ldr r2, [pc, #192] ; (8000bc8 ) 8000b08: 601a str r2, [r3, #0] hfdcan2.Init.FrameFormat = FDCAN_FRAME_FD_BRS; 8000b0a: 4b2e ldr r3, [pc, #184] ; (8000bc4 ) 8000b0c: f44f 7240 mov.w r2, #768 ; 0x300 8000b10: 609a str r2, [r3, #8] hfdcan2.Init.Mode = FDCAN_MODE_NORMAL; 8000b12: 4b2c ldr r3, [pc, #176] ; (8000bc4 ) 8000b14: 2200 movs r2, #0 8000b16: 60da str r2, [r3, #12] hfdcan2.Init.AutoRetransmission = DISABLE; 8000b18: 4b2a ldr r3, [pc, #168] ; (8000bc4 ) 8000b1a: 2200 movs r2, #0 8000b1c: 741a strb r2, [r3, #16] hfdcan2.Init.TransmitPause = DISABLE; 8000b1e: 4b29 ldr r3, [pc, #164] ; (8000bc4 ) 8000b20: 2200 movs r2, #0 8000b22: 745a strb r2, [r3, #17] hfdcan2.Init.ProtocolException = DISABLE; 8000b24: 4b27 ldr r3, [pc, #156] ; (8000bc4 ) 8000b26: 2200 movs r2, #0 8000b28: 749a strb r2, [r3, #18] hfdcan2.Init.NominalPrescaler = 6; 8000b2a: 4b26 ldr r3, [pc, #152] ; (8000bc4 ) 8000b2c: 2206 movs r2, #6 8000b2e: 615a str r2, [r3, #20] hfdcan2.Init.NominalSyncJumpWidth = 4; 8000b30: 4b24 ldr r3, [pc, #144] ; (8000bc4 ) 8000b32: 2204 movs r2, #4 8000b34: 619a str r2, [r3, #24] hfdcan2.Init.NominalTimeSeg1 = 29; 8000b36: 4b23 ldr r3, [pc, #140] ; (8000bc4 ) 8000b38: 221d movs r2, #29 8000b3a: 61da str r2, [r3, #28] hfdcan2.Init.NominalTimeSeg2 = 10; 8000b3c: 4b21 ldr r3, [pc, #132] ; (8000bc4 ) 8000b3e: 220a movs r2, #10 8000b40: 621a str r2, [r3, #32] hfdcan2.Init.DataPrescaler = 4; 8000b42: 4b20 ldr r3, [pc, #128] ; (8000bc4 ) 8000b44: 2204 movs r2, #4 8000b46: 625a str r2, [r3, #36] ; 0x24 hfdcan2.Init.DataSyncJumpWidth = 4; 8000b48: 4b1e ldr r3, [pc, #120] ; (8000bc4 ) 8000b4a: 2204 movs r2, #4 8000b4c: 629a str r2, [r3, #40] ; 0x28 hfdcan2.Init.DataTimeSeg1 = 11; 8000b4e: 4b1d ldr r3, [pc, #116] ; (8000bc4 ) 8000b50: 220b movs r2, #11 8000b52: 62da str r2, [r3, #44] ; 0x2c hfdcan2.Init.DataTimeSeg2 = 3; 8000b54: 4b1b ldr r3, [pc, #108] ; (8000bc4 ) 8000b56: 2203 movs r2, #3 8000b58: 631a str r2, [r3, #48] ; 0x30 hfdcan2.Init.MessageRAMOffset = 512; 8000b5a: 4b1a ldr r3, [pc, #104] ; (8000bc4 ) 8000b5c: f44f 7200 mov.w r2, #512 ; 0x200 8000b60: 635a str r2, [r3, #52] ; 0x34 hfdcan2.Init.StdFiltersNbr = 0; 8000b62: 4b18 ldr r3, [pc, #96] ; (8000bc4 ) 8000b64: 2200 movs r2, #0 8000b66: 639a str r2, [r3, #56] ; 0x38 hfdcan2.Init.ExtFiltersNbr = 0; 8000b68: 4b16 ldr r3, [pc, #88] ; (8000bc4 ) 8000b6a: 2200 movs r2, #0 8000b6c: 63da str r2, [r3, #60] ; 0x3c hfdcan2.Init.RxFifo0ElmtsNbr = 8; 8000b6e: 4b15 ldr r3, [pc, #84] ; (8000bc4 ) 8000b70: 2208 movs r2, #8 8000b72: 641a str r2, [r3, #64] ; 0x40 hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64; 8000b74: 4b13 ldr r3, [pc, #76] ; (8000bc4 ) 8000b76: 2212 movs r2, #18 8000b78: 645a str r2, [r3, #68] ; 0x44 hfdcan2.Init.RxFifo1ElmtsNbr = 0; 8000b7a: 4b12 ldr r3, [pc, #72] ; (8000bc4 ) 8000b7c: 2200 movs r2, #0 8000b7e: 649a str r2, [r3, #72] ; 0x48 hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64; 8000b80: 4b10 ldr r3, [pc, #64] ; (8000bc4 ) 8000b82: 2212 movs r2, #18 8000b84: 64da str r2, [r3, #76] ; 0x4c hfdcan2.Init.RxBuffersNbr = 0; 8000b86: 4b0f ldr r3, [pc, #60] ; (8000bc4 ) 8000b88: 2200 movs r2, #0 8000b8a: 651a str r2, [r3, #80] ; 0x50 hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_64; 8000b8c: 4b0d ldr r3, [pc, #52] ; (8000bc4 ) 8000b8e: 2212 movs r2, #18 8000b90: 655a str r2, [r3, #84] ; 0x54 hfdcan2.Init.TxEventsNbr = 8; 8000b92: 4b0c ldr r3, [pc, #48] ; (8000bc4 ) 8000b94: 2208 movs r2, #8 8000b96: 659a str r2, [r3, #88] ; 0x58 hfdcan2.Init.TxBuffersNbr = 0; 8000b98: 4b0a ldr r3, [pc, #40] ; (8000bc4 ) 8000b9a: 2200 movs r2, #0 8000b9c: 65da str r2, [r3, #92] ; 0x5c hfdcan2.Init.TxFifoQueueElmtsNbr = 8; 8000b9e: 4b09 ldr r3, [pc, #36] ; (8000bc4 ) 8000ba0: 2208 movs r2, #8 8000ba2: 661a str r2, [r3, #96] ; 0x60 hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; 8000ba4: 4b07 ldr r3, [pc, #28] ; (8000bc4 ) 8000ba6: 2200 movs r2, #0 8000ba8: 665a str r2, [r3, #100] ; 0x64 hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_64; 8000baa: 4b06 ldr r3, [pc, #24] ; (8000bc4 ) 8000bac: 2212 movs r2, #18 8000bae: 669a str r2, [r3, #104] ; 0x68 if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) 8000bb0: 4804 ldr r0, [pc, #16] ; (8000bc4 ) 8000bb2: f004 ff97 bl 8005ae4 8000bb6: 4603 mov r3, r0 8000bb8: 2b00 cmp r3, #0 8000bba: d001 beq.n 8000bc0 { Error_Handler(); 8000bbc: f000 fc9a bl 80014f4 } /* USER CODE BEGIN FDCAN2_Init 2 */ /* USER CODE END FDCAN2_Init 2 */ } 8000bc0: bf00 nop 8000bc2: bd80 pop {r7, pc} 8000bc4: 24000e08 .word 0x24000e08 8000bc8: 4000a400 .word 0x4000a400 08000bcc : * @brief FDCAN3 Initialization Function * @param None * @retval None */ static void MX_FDCAN3_Init(void) { 8000bcc: b580 push {r7, lr} 8000bce: af00 add r7, sp, #0 /* USER CODE END FDCAN3_Init 0 */ /* USER CODE BEGIN FDCAN3_Init 1 */ /* USER CODE END FDCAN3_Init 1 */ hfdcan3.Instance = FDCAN3; 8000bd0: 4b2f ldr r3, [pc, #188] ; (8000c90 ) 8000bd2: 4a30 ldr r2, [pc, #192] ; (8000c94 ) 8000bd4: 601a str r2, [r3, #0] hfdcan3.Init.FrameFormat = FDCAN_FRAME_FD_BRS; 8000bd6: 4b2e ldr r3, [pc, #184] ; (8000c90 ) 8000bd8: f44f 7240 mov.w r2, #768 ; 0x300 8000bdc: 609a str r2, [r3, #8] hfdcan3.Init.Mode = FDCAN_MODE_NORMAL; 8000bde: 4b2c ldr r3, [pc, #176] ; (8000c90 ) 8000be0: 2200 movs r2, #0 8000be2: 60da str r2, [r3, #12] hfdcan3.Init.AutoRetransmission = DISABLE; 8000be4: 4b2a ldr r3, [pc, #168] ; (8000c90 ) 8000be6: 2200 movs r2, #0 8000be8: 741a strb r2, [r3, #16] hfdcan3.Init.TransmitPause = DISABLE; 8000bea: 4b29 ldr r3, [pc, #164] ; (8000c90 ) 8000bec: 2200 movs r2, #0 8000bee: 745a strb r2, [r3, #17] hfdcan3.Init.ProtocolException = DISABLE; 8000bf0: 4b27 ldr r3, [pc, #156] ; (8000c90 ) 8000bf2: 2200 movs r2, #0 8000bf4: 749a strb r2, [r3, #18] hfdcan3.Init.NominalPrescaler = 6; 8000bf6: 4b26 ldr r3, [pc, #152] ; (8000c90 ) 8000bf8: 2206 movs r2, #6 8000bfa: 615a str r2, [r3, #20] hfdcan3.Init.NominalSyncJumpWidth = 4; 8000bfc: 4b24 ldr r3, [pc, #144] ; (8000c90 ) 8000bfe: 2204 movs r2, #4 8000c00: 619a str r2, [r3, #24] hfdcan3.Init.NominalTimeSeg1 = 29; 8000c02: 4b23 ldr r3, [pc, #140] ; (8000c90 ) 8000c04: 221d movs r2, #29 8000c06: 61da str r2, [r3, #28] hfdcan3.Init.NominalTimeSeg2 = 10; 8000c08: 4b21 ldr r3, [pc, #132] ; (8000c90 ) 8000c0a: 220a movs r2, #10 8000c0c: 621a str r2, [r3, #32] hfdcan3.Init.DataPrescaler = 4; 8000c0e: 4b20 ldr r3, [pc, #128] ; (8000c90 ) 8000c10: 2204 movs r2, #4 8000c12: 625a str r2, [r3, #36] ; 0x24 hfdcan3.Init.DataSyncJumpWidth = 4; 8000c14: 4b1e ldr r3, [pc, #120] ; (8000c90 ) 8000c16: 2204 movs r2, #4 8000c18: 629a str r2, [r3, #40] ; 0x28 hfdcan3.Init.DataTimeSeg1 = 11; 8000c1a: 4b1d ldr r3, [pc, #116] ; (8000c90 ) 8000c1c: 220b movs r2, #11 8000c1e: 62da str r2, [r3, #44] ; 0x2c hfdcan3.Init.DataTimeSeg2 = 3; 8000c20: 4b1b ldr r3, [pc, #108] ; (8000c90 ) 8000c22: 2203 movs r2, #3 8000c24: 631a str r2, [r3, #48] ; 0x30 hfdcan3.Init.MessageRAMOffset = 1024; 8000c26: 4b1a ldr r3, [pc, #104] ; (8000c90 ) 8000c28: f44f 6280 mov.w r2, #1024 ; 0x400 8000c2c: 635a str r2, [r3, #52] ; 0x34 hfdcan3.Init.StdFiltersNbr = 0; 8000c2e: 4b18 ldr r3, [pc, #96] ; (8000c90 ) 8000c30: 2200 movs r2, #0 8000c32: 639a str r2, [r3, #56] ; 0x38 hfdcan3.Init.ExtFiltersNbr = 0; 8000c34: 4b16 ldr r3, [pc, #88] ; (8000c90 ) 8000c36: 2200 movs r2, #0 8000c38: 63da str r2, [r3, #60] ; 0x3c hfdcan3.Init.RxFifo0ElmtsNbr = 8; 8000c3a: 4b15 ldr r3, [pc, #84] ; (8000c90 ) 8000c3c: 2208 movs r2, #8 8000c3e: 641a str r2, [r3, #64] ; 0x40 hfdcan3.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64; 8000c40: 4b13 ldr r3, [pc, #76] ; (8000c90 ) 8000c42: 2212 movs r2, #18 8000c44: 645a str r2, [r3, #68] ; 0x44 hfdcan3.Init.RxFifo1ElmtsNbr = 0; 8000c46: 4b12 ldr r3, [pc, #72] ; (8000c90 ) 8000c48: 2200 movs r2, #0 8000c4a: 649a str r2, [r3, #72] ; 0x48 hfdcan3.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64; 8000c4c: 4b10 ldr r3, [pc, #64] ; (8000c90 ) 8000c4e: 2212 movs r2, #18 8000c50: 64da str r2, [r3, #76] ; 0x4c hfdcan3.Init.RxBuffersNbr = 0; 8000c52: 4b0f ldr r3, [pc, #60] ; (8000c90 ) 8000c54: 2200 movs r2, #0 8000c56: 651a str r2, [r3, #80] ; 0x50 hfdcan3.Init.RxBufferSize = FDCAN_DATA_BYTES_64; 8000c58: 4b0d ldr r3, [pc, #52] ; (8000c90 ) 8000c5a: 2212 movs r2, #18 8000c5c: 655a str r2, [r3, #84] ; 0x54 hfdcan3.Init.TxEventsNbr = 8; 8000c5e: 4b0c ldr r3, [pc, #48] ; (8000c90 ) 8000c60: 2208 movs r2, #8 8000c62: 659a str r2, [r3, #88] ; 0x58 hfdcan3.Init.TxBuffersNbr = 0; 8000c64: 4b0a ldr r3, [pc, #40] ; (8000c90 ) 8000c66: 2200 movs r2, #0 8000c68: 65da str r2, [r3, #92] ; 0x5c hfdcan3.Init.TxFifoQueueElmtsNbr = 8; 8000c6a: 4b09 ldr r3, [pc, #36] ; (8000c90 ) 8000c6c: 2208 movs r2, #8 8000c6e: 661a str r2, [r3, #96] ; 0x60 hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; 8000c70: 4b07 ldr r3, [pc, #28] ; (8000c90 ) 8000c72: 2200 movs r2, #0 8000c74: 665a str r2, [r3, #100] ; 0x64 hfdcan3.Init.TxElmtSize = FDCAN_DATA_BYTES_64; 8000c76: 4b06 ldr r3, [pc, #24] ; (8000c90 ) 8000c78: 2212 movs r2, #18 8000c7a: 669a str r2, [r3, #104] ; 0x68 if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK) 8000c7c: 4804 ldr r0, [pc, #16] ; (8000c90 ) 8000c7e: f004 ff31 bl 8005ae4 8000c82: 4603 mov r3, r0 8000c84: 2b00 cmp r3, #0 8000c86: d001 beq.n 8000c8c { Error_Handler(); 8000c88: f000 fc34 bl 80014f4 } /* USER CODE BEGIN FDCAN3_Init 2 */ /* USER CODE END FDCAN3_Init 2 */ } 8000c8c: bf00 nop 8000c8e: bd80 pop {r7, pc} 8000c90: 24000ea8 .word 0x24000ea8 8000c94: 4000d400 .word 0x4000d400 08000c98 : * @brief SDMMC1 Initialization Function * @param None * @retval None */ static void MX_SDMMC1_SD_Init(void) { 8000c98: b480 push {r7} 8000c9a: af00 add r7, sp, #0 /* USER CODE END SDMMC1_Init 0 */ /* USER CODE BEGIN SDMMC1_Init 1 */ /* USER CODE END SDMMC1_Init 1 */ hsd1.Instance = SDMMC1; 8000c9c: 4b0c ldr r3, [pc, #48] ; (8000cd0 ) 8000c9e: 4a0d ldr r2, [pc, #52] ; (8000cd4 ) 8000ca0: 601a str r2, [r3, #0] hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; 8000ca2: 4b0b ldr r3, [pc, #44] ; (8000cd0 ) 8000ca4: 2200 movs r2, #0 8000ca6: 605a str r2, [r3, #4] hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; 8000ca8: 4b09 ldr r3, [pc, #36] ; (8000cd0 ) 8000caa: 2200 movs r2, #0 8000cac: 609a str r2, [r3, #8] hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B; 8000cae: 4b08 ldr r3, [pc, #32] ; (8000cd0 ) 8000cb0: f44f 4280 mov.w r2, #16384 ; 0x4000 8000cb4: 60da str r2, [r3, #12] hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE; 8000cb6: 4b06 ldr r3, [pc, #24] ; (8000cd0 ) 8000cb8: f44f 3200 mov.w r2, #131072 ; 0x20000 8000cbc: 611a str r2, [r3, #16] hsd1.Init.ClockDiv = 1; 8000cbe: 4b04 ldr r3, [pc, #16] ; (8000cd0 ) 8000cc0: 2201 movs r2, #1 8000cc2: 615a str r2, [r3, #20] /* USER CODE BEGIN SDMMC1_Init 2 */ /* USER CODE END SDMMC1_Init 2 */ } 8000cc4: bf00 nop 8000cc6: 46bd mov sp, r7 8000cc8: f85d 7b04 ldr.w r7, [sp], #4 8000ccc: 4770 bx lr 8000cce: bf00 nop 8000cd0: 24000f48 .word 0x24000f48 8000cd4: 52007000 .word 0x52007000 08000cd8 : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 8000cd8: b580 push {r7, lr} 8000cda: b088 sub sp, #32 8000cdc: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8000cde: f107 0310 add.w r3, r7, #16 8000ce2: 2200 movs r2, #0 8000ce4: 601a str r2, [r3, #0] 8000ce6: 605a str r2, [r3, #4] 8000ce8: 609a str r2, [r3, #8] 8000cea: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000cec: 1d3b adds r3, r7, #4 8000cee: 2200 movs r2, #0 8000cf0: 601a str r2, [r3, #0] 8000cf2: 605a str r2, [r3, #4] 8000cf4: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8000cf6: 4b1d ldr r3, [pc, #116] ; (8000d6c ) 8000cf8: 4a1d ldr r2, [pc, #116] ; (8000d70 ) 8000cfa: 601a str r2, [r3, #0] htim3.Init.Prescaler = 119; 8000cfc: 4b1b ldr r3, [pc, #108] ; (8000d6c ) 8000cfe: 2277 movs r2, #119 ; 0x77 8000d00: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8000d02: 4b1a ldr r3, [pc, #104] ; (8000d6c ) 8000d04: 2200 movs r2, #0 8000d06: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 8000d08: 4b18 ldr r3, [pc, #96] ; (8000d6c ) 8000d0a: f64f 72ff movw r2, #65535 ; 0xffff 8000d0e: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000d10: 4b16 ldr r3, [pc, #88] ; (8000d6c ) 8000d12: 2200 movs r2, #0 8000d14: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000d16: 4b15 ldr r3, [pc, #84] ; (8000d6c ) 8000d18: 2200 movs r2, #0 8000d1a: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 8000d1c: 4813 ldr r0, [pc, #76] ; (8000d6c ) 8000d1e: f00b f9d7 bl 800c0d0 8000d22: 4603 mov r3, r0 8000d24: 2b00 cmp r3, #0 8000d26: d001 beq.n 8000d2c { Error_Handler(); 8000d28: f000 fbe4 bl 80014f4 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000d2c: f44f 5380 mov.w r3, #4096 ; 0x1000 8000d30: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 8000d32: f107 0310 add.w r3, r7, #16 8000d36: 4619 mov r1, r3 8000d38: 480c ldr r0, [pc, #48] ; (8000d6c ) 8000d3a: f00b fbc7 bl 800c4cc 8000d3e: 4603 mov r3, r0 8000d40: 2b00 cmp r3, #0 8000d42: d001 beq.n 8000d48 { Error_Handler(); 8000d44: f000 fbd6 bl 80014f4 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000d48: 2300 movs r3, #0 8000d4a: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000d4c: 2300 movs r3, #0 8000d4e: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8000d50: 1d3b adds r3, r7, #4 8000d52: 4619 mov r1, r3 8000d54: 4805 ldr r0, [pc, #20] ; (8000d6c ) 8000d56: f00b fe1d bl 800c994 8000d5a: 4603 mov r3, r0 8000d5c: 2b00 cmp r3, #0 8000d5e: d001 beq.n 8000d64 { Error_Handler(); 8000d60: f000 fbc8 bl 80014f4 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8000d64: bf00 nop 8000d66: 3720 adds r7, #32 8000d68: 46bd mov sp, r7 8000d6a: bd80 pop {r7, pc} 8000d6c: 24000fc4 .word 0x24000fc4 8000d70: 40000400 .word 0x40000400 08000d74 : * @brief UART4 Initialization Function * @param None * @retval None */ static void MX_UART4_Init(void) { 8000d74: b580 push {r7, lr} 8000d76: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 8000d78: 4b22 ldr r3, [pc, #136] ; (8000e04 ) 8000d7a: 4a23 ldr r2, [pc, #140] ; (8000e08 ) 8000d7c: 601a str r2, [r3, #0] huart4.Init.BaudRate = 9600; 8000d7e: 4b21 ldr r3, [pc, #132] ; (8000e04 ) 8000d80: f44f 5216 mov.w r2, #9600 ; 0x2580 8000d84: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 8000d86: 4b1f ldr r3, [pc, #124] ; (8000e04 ) 8000d88: 2200 movs r2, #0 8000d8a: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 8000d8c: 4b1d ldr r3, [pc, #116] ; (8000e04 ) 8000d8e: 2200 movs r2, #0 8000d90: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 8000d92: 4b1c ldr r3, [pc, #112] ; (8000e04 ) 8000d94: 2200 movs r2, #0 8000d96: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 8000d98: 4b1a ldr r3, [pc, #104] ; (8000e04 ) 8000d9a: 220c movs r2, #12 8000d9c: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000d9e: 4b19 ldr r3, [pc, #100] ; (8000e04 ) 8000da0: 2200 movs r2, #0 8000da2: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 8000da4: 4b17 ldr r3, [pc, #92] ; (8000e04 ) 8000da6: 2200 movs r2, #0 8000da8: 61da str r2, [r3, #28] huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000daa: 4b16 ldr r3, [pc, #88] ; (8000e04 ) 8000dac: 2200 movs r2, #0 8000dae: 621a str r2, [r3, #32] huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000db0: 4b14 ldr r3, [pc, #80] ; (8000e04 ) 8000db2: 2200 movs r2, #0 8000db4: 625a str r2, [r3, #36] ; 0x24 huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000db6: 4b13 ldr r3, [pc, #76] ; (8000e04 ) 8000db8: 2200 movs r2, #0 8000dba: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart4) != HAL_OK) 8000dbc: 4811 ldr r0, [pc, #68] ; (8000e04 ) 8000dbe: f00b fea3 bl 800cb08 8000dc2: 4603 mov r3, r0 8000dc4: 2b00 cmp r3, #0 8000dc6: d001 beq.n 8000dcc { Error_Handler(); 8000dc8: f000 fb94 bl 80014f4 } if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000dcc: 2100 movs r1, #0 8000dce: 480d ldr r0, [pc, #52] ; (8000e04 ) 8000dd0: f00c ffa9 bl 800dd26 8000dd4: 4603 mov r3, r0 8000dd6: 2b00 cmp r3, #0 8000dd8: d001 beq.n 8000dde { Error_Handler(); 8000dda: f000 fb8b bl 80014f4 } if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000dde: 2100 movs r1, #0 8000de0: 4808 ldr r0, [pc, #32] ; (8000e04 ) 8000de2: f00c ffde bl 800dda2 8000de6: 4603 mov r3, r0 8000de8: 2b00 cmp r3, #0 8000dea: d001 beq.n 8000df0 { Error_Handler(); 8000dec: f000 fb82 bl 80014f4 } if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK) 8000df0: 4804 ldr r0, [pc, #16] ; (8000e04 ) 8000df2: f00c ff5f bl 800dcb4 8000df6: 4603 mov r3, r0 8000df8: 2b00 cmp r3, #0 8000dfa: d001 beq.n 8000e00 { Error_Handler(); 8000dfc: f000 fb7a bl 80014f4 } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 8000e00: bf00 nop 8000e02: bd80 pop {r7, pc} 8000e04: 24001010 .word 0x24001010 8000e08: 40004c00 .word 0x40004c00 08000e0c : * @brief UART7 Initialization Function * @param None * @retval None */ static void MX_UART7_Init(void) { 8000e0c: b580 push {r7, lr} 8000e0e: af00 add r7, sp, #0 /* USER CODE END UART7_Init 0 */ /* USER CODE BEGIN UART7_Init 1 */ /* USER CODE END UART7_Init 1 */ huart7.Instance = UART7; 8000e10: 4b22 ldr r3, [pc, #136] ; (8000e9c ) 8000e12: 4a23 ldr r2, [pc, #140] ; (8000ea0 ) 8000e14: 601a str r2, [r3, #0] huart7.Init.BaudRate = 115200; 8000e16: 4b21 ldr r3, [pc, #132] ; (8000e9c ) 8000e18: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000e1c: 605a str r2, [r3, #4] huart7.Init.WordLength = UART_WORDLENGTH_8B; 8000e1e: 4b1f ldr r3, [pc, #124] ; (8000e9c ) 8000e20: 2200 movs r2, #0 8000e22: 609a str r2, [r3, #8] huart7.Init.StopBits = UART_STOPBITS_1; 8000e24: 4b1d ldr r3, [pc, #116] ; (8000e9c ) 8000e26: 2200 movs r2, #0 8000e28: 60da str r2, [r3, #12] huart7.Init.Parity = UART_PARITY_NONE; 8000e2a: 4b1c ldr r3, [pc, #112] ; (8000e9c ) 8000e2c: 2200 movs r2, #0 8000e2e: 611a str r2, [r3, #16] huart7.Init.Mode = UART_MODE_TX_RX; 8000e30: 4b1a ldr r3, [pc, #104] ; (8000e9c ) 8000e32: 220c movs r2, #12 8000e34: 615a str r2, [r3, #20] huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000e36: 4b19 ldr r3, [pc, #100] ; (8000e9c ) 8000e38: 2200 movs r2, #0 8000e3a: 619a str r2, [r3, #24] huart7.Init.OverSampling = UART_OVERSAMPLING_16; 8000e3c: 4b17 ldr r3, [pc, #92] ; (8000e9c ) 8000e3e: 2200 movs r2, #0 8000e40: 61da str r2, [r3, #28] huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000e42: 4b16 ldr r3, [pc, #88] ; (8000e9c ) 8000e44: 2200 movs r2, #0 8000e46: 621a str r2, [r3, #32] huart7.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000e48: 4b14 ldr r3, [pc, #80] ; (8000e9c ) 8000e4a: 2200 movs r2, #0 8000e4c: 625a str r2, [r3, #36] ; 0x24 huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000e4e: 4b13 ldr r3, [pc, #76] ; (8000e9c ) 8000e50: 2200 movs r2, #0 8000e52: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart7) != HAL_OK) 8000e54: 4811 ldr r0, [pc, #68] ; (8000e9c ) 8000e56: f00b fe57 bl 800cb08 8000e5a: 4603 mov r3, r0 8000e5c: 2b00 cmp r3, #0 8000e5e: d001 beq.n 8000e64 { Error_Handler(); 8000e60: f000 fb48 bl 80014f4 } if (HAL_UARTEx_SetTxFifoThreshold(&huart7, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000e64: 2100 movs r1, #0 8000e66: 480d ldr r0, [pc, #52] ; (8000e9c ) 8000e68: f00c ff5d bl 800dd26 8000e6c: 4603 mov r3, r0 8000e6e: 2b00 cmp r3, #0 8000e70: d001 beq.n 8000e76 { Error_Handler(); 8000e72: f000 fb3f bl 80014f4 } if (HAL_UARTEx_SetRxFifoThreshold(&huart7, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000e76: 2100 movs r1, #0 8000e78: 4808 ldr r0, [pc, #32] ; (8000e9c ) 8000e7a: f00c ff92 bl 800dda2 8000e7e: 4603 mov r3, r0 8000e80: 2b00 cmp r3, #0 8000e82: d001 beq.n 8000e88 { Error_Handler(); 8000e84: f000 fb36 bl 80014f4 } if (HAL_UARTEx_DisableFifoMode(&huart7) != HAL_OK) 8000e88: 4804 ldr r0, [pc, #16] ; (8000e9c ) 8000e8a: f00c ff13 bl 800dcb4 8000e8e: 4603 mov r3, r0 8000e90: 2b00 cmp r3, #0 8000e92: d001 beq.n 8000e98 { Error_Handler(); 8000e94: f000 fb2e bl 80014f4 } /* USER CODE BEGIN UART7_Init 2 */ /* USER CODE END UART7_Init 2 */ } 8000e98: bf00 nop 8000e9a: bd80 pop {r7, pc} 8000e9c: 240010a4 .word 0x240010a4 8000ea0: 40007800 .word 0x40007800 08000ea4 : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 8000ea4: b580 push {r7, lr} 8000ea6: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 8000ea8: 4b22 ldr r3, [pc, #136] ; (8000f34 ) 8000eaa: 4a23 ldr r2, [pc, #140] ; (8000f38 ) 8000eac: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 8000eae: 4b21 ldr r3, [pc, #132] ; (8000f34 ) 8000eb0: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000eb4: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 8000eb6: 4b1f ldr r3, [pc, #124] ; (8000f34 ) 8000eb8: 2200 movs r2, #0 8000eba: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 8000ebc: 4b1d ldr r3, [pc, #116] ; (8000f34 ) 8000ebe: 2200 movs r2, #0 8000ec0: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 8000ec2: 4b1c ldr r3, [pc, #112] ; (8000f34 ) 8000ec4: 2200 movs r2, #0 8000ec6: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 8000ec8: 4b1a ldr r3, [pc, #104] ; (8000f34 ) 8000eca: 220c movs r2, #12 8000ecc: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000ece: 4b19 ldr r3, [pc, #100] ; (8000f34 ) 8000ed0: 2200 movs r2, #0 8000ed2: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 8000ed4: 4b17 ldr r3, [pc, #92] ; (8000f34 ) 8000ed6: 2200 movs r2, #0 8000ed8: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000eda: 4b16 ldr r3, [pc, #88] ; (8000f34 ) 8000edc: 2200 movs r2, #0 8000ede: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000ee0: 4b14 ldr r3, [pc, #80] ; (8000f34 ) 8000ee2: 2200 movs r2, #0 8000ee4: 625a str r2, [r3, #36] ; 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000ee6: 4b13 ldr r3, [pc, #76] ; (8000f34 ) 8000ee8: 2200 movs r2, #0 8000eea: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 8000eec: 4811 ldr r0, [pc, #68] ; (8000f34 ) 8000eee: f00b fe0b bl 800cb08 8000ef2: 4603 mov r3, r0 8000ef4: 2b00 cmp r3, #0 8000ef6: d001 beq.n 8000efc { Error_Handler(); 8000ef8: f000 fafc bl 80014f4 } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000efc: 2100 movs r1, #0 8000efe: 480d ldr r0, [pc, #52] ; (8000f34 ) 8000f00: f00c ff11 bl 800dd26 8000f04: 4603 mov r3, r0 8000f06: 2b00 cmp r3, #0 8000f08: d001 beq.n 8000f0e { Error_Handler(); 8000f0a: f000 faf3 bl 80014f4 } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000f0e: 2100 movs r1, #0 8000f10: 4808 ldr r0, [pc, #32] ; (8000f34 ) 8000f12: f00c ff46 bl 800dda2 8000f16: 4603 mov r3, r0 8000f18: 2b00 cmp r3, #0 8000f1a: d001 beq.n 8000f20 { Error_Handler(); 8000f1c: f000 faea bl 80014f4 } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 8000f20: 4804 ldr r0, [pc, #16] ; (8000f34 ) 8000f22: f00c fec7 bl 800dcb4 8000f26: 4603 mov r3, r0 8000f28: 2b00 cmp r3, #0 8000f2a: d001 beq.n 8000f30 { Error_Handler(); 8000f2c: f000 fae2 bl 80014f4 } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 8000f30: bf00 nop 8000f32: bd80 pop {r7, pc} 8000f34: 24001138 .word 0x24001138 8000f38: 40007c00 .word 0x40007c00 08000f3c : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8000f3c: b580 push {r7, lr} 8000f3e: b082 sub sp, #8 8000f40: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8000f42: 4b0d ldr r3, [pc, #52] ; (8000f78 ) 8000f44: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 8000f48: 4a0b ldr r2, [pc, #44] ; (8000f78 ) 8000f4a: f043 0301 orr.w r3, r3, #1 8000f4e: f8c2 30d8 str.w r3, [r2, #216] ; 0xd8 8000f52: 4b09 ldr r3, [pc, #36] ; (8000f78 ) 8000f54: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 8000f58: f003 0301 and.w r3, r3, #1 8000f5c: 607b str r3, [r7, #4] 8000f5e: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 8000f60: 2200 movs r2, #0 8000f62: 2105 movs r1, #5 8000f64: 200b movs r0, #11 8000f66: f001 faf9 bl 800255c HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000f6a: 200b movs r0, #11 8000f6c: f001 fb10 bl 8002590 } 8000f70: bf00 nop 8000f72: 3708 adds r7, #8 8000f74: 46bd mov sp, r7 8000f76: bd80 pop {r7, pc} 8000f78: 58024400 .word 0x58024400 08000f7c : * Enable MDMA controller clock * Configure MDMA for global transfers * hmdma_mdma_channel0_sdmmc1_end_data_0 */ static void MX_MDMA_Init(void) { 8000f7c: b580 push {r7, lr} 8000f7e: b082 sub sp, #8 8000f80: af00 add r7, sp, #0 /* MDMA controller clock enable */ __HAL_RCC_MDMA_CLK_ENABLE(); 8000f82: 4b2d ldr r3, [pc, #180] ; (8001038 ) 8000f84: f8d3 30d4 ldr.w r3, [r3, #212] ; 0xd4 8000f88: 4a2b ldr r2, [pc, #172] ; (8001038 ) 8000f8a: f043 0301 orr.w r3, r3, #1 8000f8e: f8c2 30d4 str.w r3, [r2, #212] ; 0xd4 8000f92: 4b29 ldr r3, [pc, #164] ; (8001038 ) 8000f94: f8d3 30d4 ldr.w r3, [r3, #212] ; 0xd4 8000f98: f003 0301 and.w r3, r3, #1 8000f9c: 607b str r3, [r7, #4] 8000f9e: 687b ldr r3, [r7, #4] /* Local variables */ /* Configure MDMA channel MDMA_Channel0 */ /* Configure MDMA request hmdma_mdma_channel0_sdmmc1_end_data_0 on MDMA_Channel0 */ hmdma_mdma_channel0_sdmmc1_end_data_0.Instance = MDMA_Channel0; 8000fa0: 4b26 ldr r3, [pc, #152] ; (800103c ) 8000fa2: 4a27 ldr r2, [pc, #156] ; (8001040 ) 8000fa4: 601a str r2, [r3, #0] hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Request = MDMA_REQUEST_SDMMC1_END_DATA; 8000fa6: 4b25 ldr r3, [pc, #148] ; (800103c ) 8000fa8: 221d movs r2, #29 8000faa: 605a str r2, [r3, #4] hmdma_mdma_channel0_sdmmc1_end_data_0.Init.TransferTriggerMode = MDMA_BUFFER_TRANSFER; 8000fac: 4b23 ldr r3, [pc, #140] ; (800103c ) 8000fae: 2200 movs r2, #0 8000fb0: 609a str r2, [r3, #8] hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Priority = MDMA_PRIORITY_LOW; 8000fb2: 4b22 ldr r3, [pc, #136] ; (800103c ) 8000fb4: 2200 movs r2, #0 8000fb6: 60da str r2, [r3, #12] hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Endianness = MDMA_LITTLE_ENDIANNESS_PRESERVE; 8000fb8: 4b20 ldr r3, [pc, #128] ; (800103c ) 8000fba: 2200 movs r2, #0 8000fbc: 611a str r2, [r3, #16] hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceInc = MDMA_SRC_INC_BYTE; 8000fbe: 4b1f ldr r3, [pc, #124] ; (800103c ) 8000fc0: 2202 movs r2, #2 8000fc2: 615a str r2, [r3, #20] hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestinationInc = MDMA_DEST_INC_BYTE; 8000fc4: 4b1d ldr r3, [pc, #116] ; (800103c ) 8000fc6: 2208 movs r2, #8 8000fc8: 619a str r2, [r3, #24] hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceDataSize = MDMA_SRC_DATASIZE_BYTE; 8000fca: 4b1c ldr r3, [pc, #112] ; (800103c ) 8000fcc: 2200 movs r2, #0 8000fce: 61da str r2, [r3, #28] hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestDataSize = MDMA_DEST_DATASIZE_BYTE; 8000fd0: 4b1a ldr r3, [pc, #104] ; (800103c ) 8000fd2: 2200 movs r2, #0 8000fd4: 621a str r2, [r3, #32] hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DataAlignment = MDMA_DATAALIGN_PACKENABLE; 8000fd6: 4b19 ldr r3, [pc, #100] ; (800103c ) 8000fd8: f04f 7200 mov.w r2, #33554432 ; 0x2000000 8000fdc: 625a str r2, [r3, #36] ; 0x24 hmdma_mdma_channel0_sdmmc1_end_data_0.Init.BufferTransferLength = 1; 8000fde: 4b17 ldr r3, [pc, #92] ; (800103c ) 8000fe0: 2201 movs r2, #1 8000fe2: 629a str r2, [r3, #40] ; 0x28 hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceBurst = MDMA_SOURCE_BURST_SINGLE; 8000fe4: 4b15 ldr r3, [pc, #84] ; (800103c ) 8000fe6: 2200 movs r2, #0 8000fe8: 62da str r2, [r3, #44] ; 0x2c hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestBurst = MDMA_DEST_BURST_SINGLE; 8000fea: 4b14 ldr r3, [pc, #80] ; (800103c ) 8000fec: 2200 movs r2, #0 8000fee: 631a str r2, [r3, #48] ; 0x30 hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceBlockAddressOffset = 0; 8000ff0: 4b12 ldr r3, [pc, #72] ; (800103c ) 8000ff2: 2200 movs r2, #0 8000ff4: 635a str r2, [r3, #52] ; 0x34 hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestBlockAddressOffset = 0; 8000ff6: 4b11 ldr r3, [pc, #68] ; (800103c ) 8000ff8: 2200 movs r2, #0 8000ffa: 639a str r2, [r3, #56] ; 0x38 if (HAL_MDMA_Init(&hmdma_mdma_channel0_sdmmc1_end_data_0) != HAL_OK) 8000ffc: 480f ldr r0, [pc, #60] ; (800103c ) 8000ffe: f005 fdb0 bl 8006b62 8001002: 4603 mov r3, r0 8001004: 2b00 cmp r3, #0 8001006: d001 beq.n 800100c { Error_Handler(); 8001008: f000 fa74 bl 80014f4 } /* Configure post request address and data masks */ if (HAL_MDMA_ConfigPostRequestMask(&hmdma_mdma_channel0_sdmmc1_end_data_0, 0, 0) != HAL_OK) 800100c: 2200 movs r2, #0 800100e: 2100 movs r1, #0 8001010: 480a ldr r0, [pc, #40] ; (800103c ) 8001012: f005 fdf2 bl 8006bfa 8001016: 4603 mov r3, r0 8001018: 2b00 cmp r3, #0 800101a: d001 beq.n 8001020 { Error_Handler(); 800101c: f000 fa6a bl 80014f4 } /* MDMA interrupt initialization */ /* MDMA_IRQn interrupt configuration */ HAL_NVIC_SetPriority(MDMA_IRQn, 5, 0); 8001020: 2200 movs r2, #0 8001022: 2105 movs r1, #5 8001024: 207a movs r0, #122 ; 0x7a 8001026: f001 fa99 bl 800255c HAL_NVIC_EnableIRQ(MDMA_IRQn); 800102a: 207a movs r0, #122 ; 0x7a 800102c: f001 fab0 bl 8002590 } 8001030: bf00 nop 8001032: 3708 adds r7, #8 8001034: 46bd mov sp, r7 8001036: bd80 pop {r7, pc} 8001038: 58024400 .word 0x58024400 800103c: 24001244 .word 0x24001244 8001040: 52000040 .word 0x52000040 08001044 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8001044: b580 push {r7, lr} 8001046: b08c sub sp, #48 ; 0x30 8001048: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800104a: f107 031c add.w r3, r7, #28 800104e: 2200 movs r2, #0 8001050: 601a str r2, [r3, #0] 8001052: 605a str r2, [r3, #4] 8001054: 609a str r2, [r3, #8] 8001056: 60da str r2, [r3, #12] 8001058: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOB_CLK_ENABLE(); 800105a: 4b51 ldr r3, [pc, #324] ; (80011a0 ) 800105c: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001060: 4a4f ldr r2, [pc, #316] ; (80011a0 ) 8001062: f043 0302 orr.w r3, r3, #2 8001066: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 800106a: 4b4d ldr r3, [pc, #308] ; (80011a0 ) 800106c: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001070: f003 0302 and.w r3, r3, #2 8001074: 61bb str r3, [r7, #24] 8001076: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001078: 4b49 ldr r3, [pc, #292] ; (80011a0 ) 800107a: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 800107e: 4a48 ldr r2, [pc, #288] ; (80011a0 ) 8001080: f043 0301 orr.w r3, r3, #1 8001084: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8001088: 4b45 ldr r3, [pc, #276] ; (80011a0 ) 800108a: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 800108e: f003 0301 and.w r3, r3, #1 8001092: 617b str r3, [r7, #20] 8001094: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001096: 4b42 ldr r3, [pc, #264] ; (80011a0 ) 8001098: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 800109c: 4a40 ldr r2, [pc, #256] ; (80011a0 ) 800109e: f043 0308 orr.w r3, r3, #8 80010a2: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 80010a6: 4b3e ldr r3, [pc, #248] ; (80011a0 ) 80010a8: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80010ac: f003 0308 and.w r3, r3, #8 80010b0: 613b str r3, [r7, #16] 80010b2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 80010b4: 4b3a ldr r3, [pc, #232] ; (80011a0 ) 80010b6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80010ba: 4a39 ldr r2, [pc, #228] ; (80011a0 ) 80010bc: f043 0304 orr.w r3, r3, #4 80010c0: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 80010c4: 4b36 ldr r3, [pc, #216] ; (80011a0 ) 80010c6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80010ca: f003 0304 and.w r3, r3, #4 80010ce: 60fb str r3, [r7, #12] 80010d0: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOH_CLK_ENABLE(); 80010d2: 4b33 ldr r3, [pc, #204] ; (80011a0 ) 80010d4: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80010d8: 4a31 ldr r2, [pc, #196] ; (80011a0 ) 80010da: f043 0380 orr.w r3, r3, #128 ; 0x80 80010de: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 80010e2: 4b2f ldr r3, [pc, #188] ; (80011a0 ) 80010e4: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80010e8: f003 0380 and.w r3, r3, #128 ; 0x80 80010ec: 60bb str r3, [r7, #8] 80010ee: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 80010f0: 4b2b ldr r3, [pc, #172] ; (80011a0 ) 80010f2: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80010f6: 4a2a ldr r2, [pc, #168] ; (80011a0 ) 80010f8: f043 0310 orr.w r3, r3, #16 80010fc: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8001100: 4b27 ldr r3, [pc, #156] ; (80011a0 ) 8001102: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001106: f003 0310 and.w r3, r3, #16 800110a: 607b str r3, [r7, #4] 800110c: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(mLED_GPIO_Port, mLED_Pin, GPIO_PIN_RESET); 800110e: 2200 movs r2, #0 8001110: f44f 4100 mov.w r1, #32768 ; 0x8000 8001114: 4823 ldr r0, [pc, #140] ; (80011a4 ) 8001116: f005 fd0b bl 8006b30 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, SD_LED_Pin|VIN_ON_Pin|PICO_EN_Pin, GPIO_PIN_RESET); 800111a: 2200 movs r2, #0 800111c: f44f 51b0 mov.w r1, #5632 ; 0x1600 8001120: 4821 ldr r0, [pc, #132] ; (80011a8 ) 8001122: f005 fd05 bl 8006b30 /*Configure GPIO pin : mLED_Pin */ GPIO_InitStruct.Pin = mLED_Pin; 8001126: f44f 4300 mov.w r3, #32768 ; 0x8000 800112a: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800112c: 2301 movs r3, #1 800112e: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001130: 2300 movs r3, #0 8001132: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001134: 2300 movs r3, #0 8001136: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(mLED_GPIO_Port, &GPIO_InitStruct); 8001138: f107 031c add.w r3, r7, #28 800113c: 4619 mov r1, r3 800113e: 4819 ldr r0, [pc, #100] ; (80011a4 ) 8001140: f005 fb36 bl 80067b0 /*Configure GPIO pins : SD_LED_Pin VIN_ON_Pin PICO_EN_Pin */ GPIO_InitStruct.Pin = SD_LED_Pin|VIN_ON_Pin|PICO_EN_Pin; 8001144: f44f 53b0 mov.w r3, #5632 ; 0x1600 8001148: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800114a: 2301 movs r3, #1 800114c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800114e: 2300 movs r3, #0 8001150: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001152: 2300 movs r3, #0 8001154: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8001156: f107 031c add.w r3, r7, #28 800115a: 4619 mov r1, r3 800115c: 4812 ldr r0, [pc, #72] ; (80011a8 ) 800115e: f005 fb27 bl 80067b0 /*Configure GPIO pin : sdDetect_Pin */ GPIO_InitStruct.Pin = sdDetect_Pin; 8001162: f44f 4300 mov.w r3, #32768 ; 0x8000 8001166: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001168: 2300 movs r3, #0 800116a: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800116c: 2300 movs r3, #0 800116e: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(sdDetect_GPIO_Port, &GPIO_InitStruct); 8001170: f107 031c add.w r3, r7, #28 8001174: 4619 mov r1, r3 8001176: 480d ldr r0, [pc, #52] ; (80011ac ) 8001178: f005 fb1a bl 80067b0 /*Configure GPIO pins : VIN_IG_Pin VIN_1_4_Pin */ GPIO_InitStruct.Pin = VIN_IG_Pin|VIN_1_4_Pin; 800117c: f44f 5320 mov.w r3, #10240 ; 0x2800 8001180: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001182: 2300 movs r3, #0 8001184: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001186: 2300 movs r3, #0 8001188: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800118a: f107 031c add.w r3, r7, #28 800118e: 4619 mov r1, r3 8001190: 4805 ldr r0, [pc, #20] ; (80011a8 ) 8001192: f005 fb0d bl 80067b0 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8001196: bf00 nop 8001198: 3730 adds r7, #48 ; 0x30 800119a: 46bd mov sp, r7 800119c: bd80 pop {r7, pc} 800119e: bf00 nop 80011a0: 58024400 .word 0x58024400 80011a4: 58020000 .word 0x58020000 80011a8: 58021000 .word 0x58021000 80011ac: 58020400 .word 0x58020400 080011b0 : /* USER CODE BEGIN 4 */ void lwftp_init(void) { 80011b0: b580 push {r7, lr} 80011b2: b082 sub sp, #8 80011b4: af02 add r7, sp, #8 IP4_ADDR(&s.cli_ip, CLI_IP[0], CLI_IP[1], CLI_IP[2], CLI_IP[3]); 80011b6: 4b6e ldr r3, [pc, #440] ; (8001370 ) 80011b8: 781b ldrb r3, [r3, #0] 80011ba: 061a lsls r2, r3, #24 80011bc: 4b6c ldr r3, [pc, #432] ; (8001370 ) 80011be: 785b ldrb r3, [r3, #1] 80011c0: 041b lsls r3, r3, #16 80011c2: 431a orrs r2, r3 80011c4: 4b6a ldr r3, [pc, #424] ; (8001370 ) 80011c6: 789b ldrb r3, [r3, #2] 80011c8: 021b lsls r3, r3, #8 80011ca: 4313 orrs r3, r2 80011cc: 4a68 ldr r2, [pc, #416] ; (8001370 ) 80011ce: 78d2 ldrb r2, [r2, #3] 80011d0: 4313 orrs r3, r2 80011d2: 061a lsls r2, r3, #24 80011d4: 4b66 ldr r3, [pc, #408] ; (8001370 ) 80011d6: 781b ldrb r3, [r3, #0] 80011d8: 0619 lsls r1, r3, #24 80011da: 4b65 ldr r3, [pc, #404] ; (8001370 ) 80011dc: 785b ldrb r3, [r3, #1] 80011de: 041b lsls r3, r3, #16 80011e0: 4319 orrs r1, r3 80011e2: 4b63 ldr r3, [pc, #396] ; (8001370 ) 80011e4: 789b ldrb r3, [r3, #2] 80011e6: 021b lsls r3, r3, #8 80011e8: 430b orrs r3, r1 80011ea: 4961 ldr r1, [pc, #388] ; (8001370 ) 80011ec: 78c9 ldrb r1, [r1, #3] 80011ee: 430b orrs r3, r1 80011f0: 021b lsls r3, r3, #8 80011f2: f403 037f and.w r3, r3, #16711680 ; 0xff0000 80011f6: 431a orrs r2, r3 80011f8: 4b5d ldr r3, [pc, #372] ; (8001370 ) 80011fa: 781b ldrb r3, [r3, #0] 80011fc: 0619 lsls r1, r3, #24 80011fe: 4b5c ldr r3, [pc, #368] ; (8001370 ) 8001200: 785b ldrb r3, [r3, #1] 8001202: 041b lsls r3, r3, #16 8001204: 4319 orrs r1, r3 8001206: 4b5a ldr r3, [pc, #360] ; (8001370 ) 8001208: 789b ldrb r3, [r3, #2] 800120a: 021b lsls r3, r3, #8 800120c: 430b orrs r3, r1 800120e: 4958 ldr r1, [pc, #352] ; (8001370 ) 8001210: 78c9 ldrb r1, [r1, #3] 8001212: 430b orrs r3, r1 8001214: 0a1b lsrs r3, r3, #8 8001216: f403 437f and.w r3, r3, #65280 ; 0xff00 800121a: 431a orrs r2, r3 800121c: 4b54 ldr r3, [pc, #336] ; (8001370 ) 800121e: 781b ldrb r3, [r3, #0] 8001220: 0619 lsls r1, r3, #24 8001222: 4b53 ldr r3, [pc, #332] ; (8001370 ) 8001224: 785b ldrb r3, [r3, #1] 8001226: 041b lsls r3, r3, #16 8001228: 4319 orrs r1, r3 800122a: 4b51 ldr r3, [pc, #324] ; (8001370 ) 800122c: 789b ldrb r3, [r3, #2] 800122e: 021b lsls r3, r3, #8 8001230: 430b orrs r3, r1 8001232: 494f ldr r1, [pc, #316] ; (8001370 ) 8001234: 78c9 ldrb r1, [r1, #3] 8001236: 430b orrs r3, r1 8001238: 0e1b lsrs r3, r3, #24 800123a: 4313 orrs r3, r2 800123c: 4a4d ldr r2, [pc, #308] ; (8001374 ) 800123e: 6013 str r3, [r2, #0] IP4_ADDR(&s.svr_ip, SVR_IP[0], SVR_IP[1], SVR_IP[2], SVR_IP[3]); 8001240: 4b4d ldr r3, [pc, #308] ; (8001378 ) 8001242: 781b ldrb r3, [r3, #0] 8001244: 061a lsls r2, r3, #24 8001246: 4b4c ldr r3, [pc, #304] ; (8001378 ) 8001248: 785b ldrb r3, [r3, #1] 800124a: 041b lsls r3, r3, #16 800124c: 431a orrs r2, r3 800124e: 4b4a ldr r3, [pc, #296] ; (8001378 ) 8001250: 789b ldrb r3, [r3, #2] 8001252: 021b lsls r3, r3, #8 8001254: 4313 orrs r3, r2 8001256: 4a48 ldr r2, [pc, #288] ; (8001378 ) 8001258: 78d2 ldrb r2, [r2, #3] 800125a: 4313 orrs r3, r2 800125c: 061a lsls r2, r3, #24 800125e: 4b46 ldr r3, [pc, #280] ; (8001378 ) 8001260: 781b ldrb r3, [r3, #0] 8001262: 0619 lsls r1, r3, #24 8001264: 4b44 ldr r3, [pc, #272] ; (8001378 ) 8001266: 785b ldrb r3, [r3, #1] 8001268: 041b lsls r3, r3, #16 800126a: 4319 orrs r1, r3 800126c: 4b42 ldr r3, [pc, #264] ; (8001378 ) 800126e: 789b ldrb r3, [r3, #2] 8001270: 021b lsls r3, r3, #8 8001272: 430b orrs r3, r1 8001274: 4940 ldr r1, [pc, #256] ; (8001378 ) 8001276: 78c9 ldrb r1, [r1, #3] 8001278: 430b orrs r3, r1 800127a: 021b lsls r3, r3, #8 800127c: f403 037f and.w r3, r3, #16711680 ; 0xff0000 8001280: 431a orrs r2, r3 8001282: 4b3d ldr r3, [pc, #244] ; (8001378 ) 8001284: 781b ldrb r3, [r3, #0] 8001286: 0619 lsls r1, r3, #24 8001288: 4b3b ldr r3, [pc, #236] ; (8001378 ) 800128a: 785b ldrb r3, [r3, #1] 800128c: 041b lsls r3, r3, #16 800128e: 4319 orrs r1, r3 8001290: 4b39 ldr r3, [pc, #228] ; (8001378 ) 8001292: 789b ldrb r3, [r3, #2] 8001294: 021b lsls r3, r3, #8 8001296: 430b orrs r3, r1 8001298: 4937 ldr r1, [pc, #220] ; (8001378 ) 800129a: 78c9 ldrb r1, [r1, #3] 800129c: 430b orrs r3, r1 800129e: 0a1b lsrs r3, r3, #8 80012a0: f403 437f and.w r3, r3, #65280 ; 0xff00 80012a4: 431a orrs r2, r3 80012a6: 4b34 ldr r3, [pc, #208] ; (8001378 ) 80012a8: 781b ldrb r3, [r3, #0] 80012aa: 0619 lsls r1, r3, #24 80012ac: 4b32 ldr r3, [pc, #200] ; (8001378 ) 80012ae: 785b ldrb r3, [r3, #1] 80012b0: 041b lsls r3, r3, #16 80012b2: 4319 orrs r1, r3 80012b4: 4b30 ldr r3, [pc, #192] ; (8001378 ) 80012b6: 789b ldrb r3, [r3, #2] 80012b8: 021b lsls r3, r3, #8 80012ba: 430b orrs r3, r1 80012bc: 492e ldr r1, [pc, #184] ; (8001378 ) 80012be: 78c9 ldrb r1, [r1, #3] 80012c0: 430b orrs r3, r1 80012c2: 0e1b lsrs r3, r3, #24 80012c4: 4313 orrs r3, r2 80012c6: 4a2b ldr r2, [pc, #172] ; (8001374 ) 80012c8: 6053 str r3, [r2, #4] s.svr_port = SVR_PORT; 80012ca: 4b2c ldr r3, [pc, #176] ; (800137c ) 80012cc: 881a ldrh r2, [r3, #0] 80012ce: 4b29 ldr r3, [pc, #164] ; (8001374 ) 80012d0: 811a strh r2, [r3, #8] s.user = USER; 80012d2: 4b2b ldr r3, [pc, #172] ; (8001380 ) 80012d4: 681b ldr r3, [r3, #0] 80012d6: 4a27 ldr r2, [pc, #156] ; (8001374 ) 80012d8: 60d3 str r3, [r2, #12] s.pass = PASS; 80012da: 4b2a ldr r3, [pc, #168] ; (8001384 ) 80012dc: 681b ldr r3, [r3, #0] 80012de: 4a25 ldr r2, [pc, #148] ; (8001374 ) 80012e0: 6113 str r3, [r2, #16] printf("\n>> lwftp: cli ip: %d.%d.%d.%d\r\n", CLI_IP[0], CLI_IP[1], CLI_IP[2], CLI_IP[3]); 80012e2: 4b23 ldr r3, [pc, #140] ; (8001370 ) 80012e4: 781b ldrb r3, [r3, #0] 80012e6: 4619 mov r1, r3 80012e8: 4b21 ldr r3, [pc, #132] ; (8001370 ) 80012ea: 785b ldrb r3, [r3, #1] 80012ec: 461a mov r2, r3 80012ee: 4b20 ldr r3, [pc, #128] ; (8001370 ) 80012f0: 789b ldrb r3, [r3, #2] 80012f2: 4618 mov r0, r3 80012f4: 4b1e ldr r3, [pc, #120] ; (8001370 ) 80012f6: 78db ldrb r3, [r3, #3] 80012f8: 9300 str r3, [sp, #0] 80012fa: 4603 mov r3, r0 80012fc: 4822 ldr r0, [pc, #136] ; (8001388 ) 80012fe: f020 fb43 bl 8021988 printf(">> lwftp: svr ip: %d.%d.%d.%d\r\n", SVR_IP[0], SVR_IP[1], SVR_IP[2], SVR_IP[3]); 8001302: 4b1d ldr r3, [pc, #116] ; (8001378 ) 8001304: 781b ldrb r3, [r3, #0] 8001306: 4619 mov r1, r3 8001308: 4b1b ldr r3, [pc, #108] ; (8001378 ) 800130a: 785b ldrb r3, [r3, #1] 800130c: 461a mov r2, r3 800130e: 4b1a ldr r3, [pc, #104] ; (8001378 ) 8001310: 789b ldrb r3, [r3, #2] 8001312: 4618 mov r0, r3 8001314: 4b18 ldr r3, [pc, #96] ; (8001378 ) 8001316: 78db ldrb r3, [r3, #3] 8001318: 9300 str r3, [sp, #0] 800131a: 4603 mov r3, r0 800131c: 481b ldr r0, [pc, #108] ; (800138c ) 800131e: f020 fb33 bl 8021988 printf(">> lwftp: svr port: %d\r\n", s.svr_port); 8001322: 4b14 ldr r3, [pc, #80] ; (8001374 ) 8001324: 891b ldrh r3, [r3, #8] 8001326: 4619 mov r1, r3 8001328: 4819 ldr r0, [pc, #100] ; (8001390 ) 800132a: f020 fb2d bl 8021988 printf(">> lwftp: username: %s\r\n", s.user); 800132e: 4b11 ldr r3, [pc, #68] ; (8001374 ) 8001330: 68db ldr r3, [r3, #12] 8001332: 4619 mov r1, r3 8001334: 4817 ldr r0, [pc, #92] ; (8001394 ) 8001336: f020 fb27 bl 8021988 printf(">> lwftp: password: %s\r\n\n", s.pass); 800133a: 4b0e ldr r3, [pc, #56] ; (8001374 ) 800133c: 691b ldr r3, [r3, #16] 800133e: 4619 mov r1, r3 8001340: 4815 ldr r0, [pc, #84] ; (8001398 ) 8001342: f020 fb21 bl 8021988 #if FTPSemaphore sys_sem_new(&ftpsem, 0); // the semaphore would prevent simultaneous access to lwftp_send #endif /* Thread for Control connection*/ sys_thread_new("lwftp_ctrl_thread", lwftp_ctrl_thread, (void*) &s, 8001346: 2300 movs r3, #0 8001348: 9300 str r3, [sp, #0] 800134a: f44f 6300 mov.w r3, #2048 ; 0x800 800134e: 4a09 ldr r2, [pc, #36] ; (8001374 ) 8001350: 4912 ldr r1, [pc, #72] ; (800139c ) 8001352: 4813 ldr r0, [pc, #76] ; (80013a0 ) 8001354: f020 f958 bl 8021608 DEFAULT_THREAD_STACKSIZE, osPriorityNormal); /* Thread for Data connection*/ sys_thread_new("lwftp_data_thread", lwftp_data_thread, (void*) &s, 8001358: 2300 movs r3, #0 800135a: 9300 str r3, [sp, #0] 800135c: f44f 6300 mov.w r3, #2048 ; 0x800 8001360: 4a04 ldr r2, [pc, #16] ; (8001374 ) 8001362: 4910 ldr r1, [pc, #64] ; (80013a4 ) 8001364: 4810 ldr r0, [pc, #64] ; (80013a8 ) 8001366: f020 f94f bl 8021608 DEFAULT_THREAD_STACKSIZE, osPriorityNormal); } 800136a: bf00 nop 800136c: 46bd mov sp, r7 800136e: bd80 pop {r7, pc} 8001370: 24000000 .word 0x24000000 8001374: 24007360 .word 0x24007360 8001378: 24000004 .word 0x24000004 800137c: 24000008 .word 0x24000008 8001380: 2400000c .word 0x2400000c 8001384: 24000010 .word 0x24000010 8001388: 08022d34 .word 0x08022d34 800138c: 08022d58 .word 0x08022d58 8001390: 08022d78 .word 0x08022d78 8001394: 08022d94 .word 0x08022d94 8001398: 08022db0 .word 0x08022db0 800139c: 0800f251 .word 0x0800f251 80013a0: 08022dcc .word 0x08022dcc 80013a4: 0800f1c9 .word 0x0800f1c9 80013a8: 08022de0 .word 0x08022de0 080013ac : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void const * argument) { 80013ac: b580 push {r7, lr} 80013ae: b084 sub sp, #16 80013b0: af00 add r7, sp, #0 80013b2: 6078 str r0, [r7, #4] /* init code for LWIP */ MX_LWIP_Init(); 80013b4: f00e f8c4 bl 800f540 /* USER CODE BEGIN 5 */ printf("[INFO] Remaining stack size of task: %ld\r\n", 80013b8: 2000 movs r0, #0 80013ba: f011 f939 bl 8012630 80013be: 4603 mov r3, r0 80013c0: 4619 mov r1, r3 80013c2: 480c ldr r0, [pc, #48] ; (80013f4 ) 80013c4: f020 fae0 bl 8021988 uxTaskGetStackHighWaterMark(NULL)); lwftp_init(); 80013c8: f7ff fef2 bl 80011b0 osDelay(5000); // run code aft 5s 80013cc: f241 3088 movw r0, #5000 ; 0x1388 80013d0: f00e ffd6 bl 8010380 err_t err; // err = lwftp_list(&s); // err = lwftp_store(&s, "foobar.txt", "TESTTESTTESTTESTTESTTESTTEST\r\n"); err = lwftp_retrieve(&s, "ftp_test_1.txt"); 80013d4: 4908 ldr r1, [pc, #32] ; (80013f8 ) 80013d6: 4809 ldr r0, [pc, #36] ; (80013fc ) 80013d8: f00d fe9e bl 800f118 80013dc: 4603 mov r3, r0 80013de: 73fb strb r3, [r7, #15] printf("%d\r\n",err); 80013e0: f997 300f ldrsb.w r3, [r7, #15] 80013e4: 4619 mov r1, r3 80013e6: 4806 ldr r0, [pc, #24] ; (8001400 ) 80013e8: f020 face bl 8021988 /* Infinite loop */ for (;;) { osDelay(1); 80013ec: 2001 movs r0, #1 80013ee: f00e ffc7 bl 8010380 80013f2: e7fb b.n 80013ec 80013f4: 08022df4 .word 0x08022df4 80013f8: 08022e20 .word 0x08022e20 80013fc: 24007360 .word 0x24007360 8001400: 08022e30 .word 0x08022e30 08001404 : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDebugTask */ void StartDebugTask(void const * argument) { 8001404: b580 push {r7, lr} 8001406: b082 sub sp, #8 8001408: af00 add r7, sp, #0 800140a: 6078 str r0, [r7, #4] /* USER CODE BEGIN StartDebugTask */ /* Infinite loop */ for(;;) { osDelay(1); 800140c: 2001 movs r0, #1 800140e: f00e ffb7 bl 8010380 8001412: e7fb b.n 800140c 08001414 : } /* MPU Configuration */ void MPU_Config(void) { 8001414: b580 push {r7, lr} 8001416: b084 sub sp, #16 8001418: af00 add r7, sp, #0 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 800141a: 463b mov r3, r7 800141c: 2200 movs r2, #0 800141e: 601a str r2, [r3, #0] 8001420: 605a str r2, [r3, #4] 8001422: 609a str r2, [r3, #8] 8001424: 60da str r2, [r3, #12] /* Disables the MPU */ HAL_MPU_Disable(); 8001426: f001 f8c1 bl 80025ac /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 800142a: 2301 movs r3, #1 800142c: 703b strb r3, [r7, #0] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 800142e: 2300 movs r3, #0 8001430: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x0; 8001432: 2300 movs r3, #0 8001434: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8001436: 231f movs r3, #31 8001438: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x87; 800143a: 2387 movs r3, #135 ; 0x87 800143c: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 800143e: 2300 movs r3, #0 8001440: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 8001442: 2300 movs r3, #0 8001444: 72fb strb r3, [r7, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 8001446: 2301 movs r3, #1 8001448: 733b strb r3, [r7, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 800144a: 2301 movs r3, #1 800144c: 737b strb r3, [r7, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 800144e: 2300 movs r3, #0 8001450: 73bb strb r3, [r7, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 8001452: 2300 movs r3, #0 8001454: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001456: 463b mov r3, r7 8001458: 4618 mov r0, r3 800145a: f001 f8df bl 800261c /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER1; 800145e: 2301 movs r3, #1 8001460: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x30000000; 8001462: f04f 5340 mov.w r3, #805306368 ; 0x30000000 8001466: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_32KB; 8001468: 230e movs r3, #14 800146a: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x0; 800146c: 2300 movs r3, #0 800146e: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 8001470: 2301 movs r3, #1 8001472: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; 8001474: 2303 movs r3, #3 8001476: 72fb strb r3, [r7, #11] MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 8001478: 2300 movs r3, #0 800147a: 737b strb r3, [r7, #13] HAL_MPU_ConfigRegion(&MPU_InitStruct); 800147c: 463b mov r3, r7 800147e: 4618 mov r0, r3 8001480: f001 f8cc bl 800261c /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8001484: 2302 movs r3, #2 8001486: 707b strb r3, [r7, #1] MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8001488: 2308 movs r3, #8 800148a: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 800148c: 2300 movs r3, #0 800148e: 72bb strb r3, [r7, #10] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001490: 2301 movs r3, #1 8001492: 737b strb r3, [r7, #13] MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 8001494: 2301 movs r3, #1 8001496: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001498: 463b mov r3, r7 800149a: 4618 mov r0, r3 800149c: f001 f8be bl 800261c /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER3; 80014a0: 2303 movs r3, #3 80014a2: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24000000; 80014a4: f04f 5310 mov.w r3, #603979776 ; 0x24000000 80014a8: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 80014aa: 2310 movs r3, #16 80014ac: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 80014ae: 2301 movs r3, #1 80014b0: 72bb strb r3, [r7, #10] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; 80014b2: 2300 movs r3, #0 80014b4: 733b strb r3, [r7, #12] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 80014b6: 2300 movs r3, #0 80014b8: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 80014ba: 463b mov r3, r7 80014bc: 4618 mov r0, r3 80014be: f001 f8ad bl 800261c /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 80014c2: 2004 movs r0, #4 80014c4: f001 f88a bl 80025dc } 80014c8: bf00 nop 80014ca: 3710 adds r7, #16 80014cc: 46bd mov sp, r7 80014ce: bd80 pop {r7, pc} 080014d0 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 80014d0: b580 push {r7, lr} 80014d2: b082 sub sp, #8 80014d4: af00 add r7, sp, #0 80014d6: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 80014d8: 687b ldr r3, [r7, #4] 80014da: 681b ldr r3, [r3, #0] 80014dc: 4a04 ldr r2, [pc, #16] ; (80014f0 ) 80014de: 4293 cmp r3, r2 80014e0: d101 bne.n 80014e6 HAL_IncTick(); 80014e2: f000 ff2b bl 800233c } /* USER CODE BEGIN Callback 1 */ /* USER CODE END Callback 1 */ } 80014e6: bf00 nop 80014e8: 3708 adds r7, #8 80014ea: 46bd mov sp, r7 80014ec: bd80 pop {r7, pc} 80014ee: bf00 nop 80014f0: 40001000 .word 0x40001000 080014f4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80014f4: b480 push {r7} 80014f6: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 80014f8: b672 cpsid i } 80014fa: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 80014fc: e7fe b.n 80014fc ... 08001500 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001500: b580 push {r7, lr} 8001502: b082 sub sp, #8 8001504: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001506: 4b0c ldr r3, [pc, #48] ; (8001538 ) 8001508: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 800150c: 4a0a ldr r2, [pc, #40] ; (8001538 ) 800150e: f043 0302 orr.w r3, r3, #2 8001512: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 8001516: 4b08 ldr r3, [pc, #32] ; (8001538 ) 8001518: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 800151c: f003 0302 and.w r3, r3, #2 8001520: 607b str r3, [r7, #4] 8001522: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8001524: 2200 movs r2, #0 8001526: 210f movs r1, #15 8001528: f06f 0001 mvn.w r0, #1 800152c: f001 f816 bl 800255c /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001530: bf00 nop 8001532: 3708 adds r7, #8 8001534: 46bd mov sp, r7 8001536: bd80 pop {r7, pc} 8001538: 58024400 .word 0x58024400 0800153c : * This function configures the hardware resources used in this example * @param hfdcan: FDCAN handle pointer * @retval None */ void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan) { 800153c: b580 push {r7, lr} 800153e: b0bc sub sp, #240 ; 0xf0 8001540: af00 add r7, sp, #0 8001542: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001544: f107 03dc add.w r3, r7, #220 ; 0xdc 8001548: 2200 movs r2, #0 800154a: 601a str r2, [r3, #0] 800154c: 605a str r2, [r3, #4] 800154e: 609a str r2, [r3, #8] 8001550: 60da str r2, [r3, #12] 8001552: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8001554: f107 0320 add.w r3, r7, #32 8001558: 22b8 movs r2, #184 ; 0xb8 800155a: 2100 movs r1, #0 800155c: 4618 mov r0, r3 800155e: f020 fbbf bl 8021ce0 if(hfdcan->Instance==FDCAN1) 8001562: 687b ldr r3, [r7, #4] 8001564: 681b ldr r3, [r3, #0] 8001566: 4a8e ldr r2, [pc, #568] ; (80017a0 ) 8001568: 4293 cmp r3, r2 800156a: d159 bne.n 8001620 /* USER CODE END FDCAN1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; 800156c: f44f 4200 mov.w r2, #32768 ; 0x8000 8001570: f04f 0300 mov.w r3, #0 8001574: e9c7 2308 strd r2, r3, [r7, #32] PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; 8001578: f04f 5380 mov.w r3, #268435456 ; 0x10000000 800157c: f8c7 308c str.w r3, [r7, #140] ; 0x8c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001580: f107 0320 add.w r3, r7, #32 8001584: 4618 mov r0, r3 8001586: f006 fd59 bl 800803c 800158a: 4603 mov r3, r0 800158c: 2b00 cmp r3, #0 800158e: d001 beq.n 8001594 { Error_Handler(); 8001590: f7ff ffb0 bl 80014f4 } /* Peripheral clock enable */ HAL_RCC_FDCAN_CLK_ENABLED++; 8001594: 4b83 ldr r3, [pc, #524] ; (80017a4 ) 8001596: 681b ldr r3, [r3, #0] 8001598: 3301 adds r3, #1 800159a: 4a82 ldr r2, [pc, #520] ; (80017a4 ) 800159c: 6013 str r3, [r2, #0] if(HAL_RCC_FDCAN_CLK_ENABLED==1){ 800159e: 4b81 ldr r3, [pc, #516] ; (80017a4 ) 80015a0: 681b ldr r3, [r3, #0] 80015a2: 2b01 cmp r3, #1 80015a4: d10e bne.n 80015c4 __HAL_RCC_FDCAN_CLK_ENABLE(); 80015a6: 4b80 ldr r3, [pc, #512] ; (80017a8 ) 80015a8: f8d3 30ec ldr.w r3, [r3, #236] ; 0xec 80015ac: 4a7e ldr r2, [pc, #504] ; (80017a8 ) 80015ae: f443 7380 orr.w r3, r3, #256 ; 0x100 80015b2: f8c2 30ec str.w r3, [r2, #236] ; 0xec 80015b6: 4b7c ldr r3, [pc, #496] ; (80017a8 ) 80015b8: f8d3 30ec ldr.w r3, [r3, #236] ; 0xec 80015bc: f403 7380 and.w r3, r3, #256 ; 0x100 80015c0: 61fb str r3, [r7, #28] 80015c2: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOB_CLK_ENABLE(); 80015c4: 4b78 ldr r3, [pc, #480] ; (80017a8 ) 80015c6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80015ca: 4a77 ldr r2, [pc, #476] ; (80017a8 ) 80015cc: f043 0302 orr.w r3, r3, #2 80015d0: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 80015d4: 4b74 ldr r3, [pc, #464] ; (80017a8 ) 80015d6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80015da: f003 0302 and.w r3, r3, #2 80015de: 61bb str r3, [r7, #24] 80015e0: 69bb ldr r3, [r7, #24] /**FDCAN1 GPIO Configuration PB9 ------> FDCAN1_TX PB8 ------> FDCAN1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8; 80015e2: f44f 7340 mov.w r3, #768 ; 0x300 80015e6: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80015ea: 2302 movs r3, #2 80015ec: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 80015f0: 2300 movs r3, #0 80015f2: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80015f6: 2300 movs r3, #0 80015f8: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; 80015fc: 2309 movs r3, #9 80015fe: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001602: f107 03dc add.w r3, r7, #220 ; 0xdc 8001606: 4619 mov r1, r3 8001608: 4868 ldr r0, [pc, #416] ; (80017ac ) 800160a: f005 f8d1 bl 80067b0 /* FDCAN1 interrupt Init */ HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0); 800160e: 2200 movs r2, #0 8001610: 2105 movs r1, #5 8001612: 2013 movs r0, #19 8001614: f000 ffa2 bl 800255c HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); 8001618: 2013 movs r0, #19 800161a: f000 ffb9 bl 8002590 /* USER CODE BEGIN FDCAN3_MspInit 1 */ /* USER CODE END FDCAN3_MspInit 1 */ } } 800161e: e0bb b.n 8001798 else if(hfdcan->Instance==FDCAN2) 8001620: 687b ldr r3, [r7, #4] 8001622: 681b ldr r3, [r3, #0] 8001624: 4a62 ldr r2, [pc, #392] ; (80017b0 ) 8001626: 4293 cmp r3, r2 8001628: d158 bne.n 80016dc PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; 800162a: f44f 4200 mov.w r2, #32768 ; 0x8000 800162e: f04f 0300 mov.w r3, #0 8001632: e9c7 2308 strd r2, r3, [r7, #32] PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; 8001636: f04f 5380 mov.w r3, #268435456 ; 0x10000000 800163a: f8c7 308c str.w r3, [r7, #140] ; 0x8c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800163e: f107 0320 add.w r3, r7, #32 8001642: 4618 mov r0, r3 8001644: f006 fcfa bl 800803c 8001648: 4603 mov r3, r0 800164a: 2b00 cmp r3, #0 800164c: d001 beq.n 8001652 Error_Handler(); 800164e: f7ff ff51 bl 80014f4 HAL_RCC_FDCAN_CLK_ENABLED++; 8001652: 4b54 ldr r3, [pc, #336] ; (80017a4 ) 8001654: 681b ldr r3, [r3, #0] 8001656: 3301 adds r3, #1 8001658: 4a52 ldr r2, [pc, #328] ; (80017a4 ) 800165a: 6013 str r3, [r2, #0] if(HAL_RCC_FDCAN_CLK_ENABLED==1){ 800165c: 4b51 ldr r3, [pc, #324] ; (80017a4 ) 800165e: 681b ldr r3, [r3, #0] 8001660: 2b01 cmp r3, #1 8001662: d10e bne.n 8001682 __HAL_RCC_FDCAN_CLK_ENABLE(); 8001664: 4b50 ldr r3, [pc, #320] ; (80017a8 ) 8001666: f8d3 30ec ldr.w r3, [r3, #236] ; 0xec 800166a: 4a4f ldr r2, [pc, #316] ; (80017a8 ) 800166c: f443 7380 orr.w r3, r3, #256 ; 0x100 8001670: f8c2 30ec str.w r3, [r2, #236] ; 0xec 8001674: 4b4c ldr r3, [pc, #304] ; (80017a8 ) 8001676: f8d3 30ec ldr.w r3, [r3, #236] ; 0xec 800167a: f403 7380 and.w r3, r3, #256 ; 0x100 800167e: 617b str r3, [r7, #20] 8001680: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001682: 4b49 ldr r3, [pc, #292] ; (80017a8 ) 8001684: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001688: 4a47 ldr r2, [pc, #284] ; (80017a8 ) 800168a: f043 0302 orr.w r3, r3, #2 800168e: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8001692: 4b45 ldr r3, [pc, #276] ; (80017a8 ) 8001694: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001698: f003 0302 and.w r3, r3, #2 800169c: 613b str r3, [r7, #16] 800169e: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_5; 80016a0: 2360 movs r3, #96 ; 0x60 80016a2: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80016a6: 2302 movs r3, #2 80016a8: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 80016ac: 2300 movs r3, #0 80016ae: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80016b2: 2300 movs r3, #0 80016b4: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; 80016b8: 2309 movs r3, #9 80016ba: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80016be: f107 03dc add.w r3, r7, #220 ; 0xdc 80016c2: 4619 mov r1, r3 80016c4: 4839 ldr r0, [pc, #228] ; (80017ac ) 80016c6: f005 f873 bl 80067b0 HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 5, 0); 80016ca: 2200 movs r2, #0 80016cc: 2105 movs r1, #5 80016ce: 2014 movs r0, #20 80016d0: f000 ff44 bl 800255c HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); 80016d4: 2014 movs r0, #20 80016d6: f000 ff5b bl 8002590 } 80016da: e05d b.n 8001798 else if(hfdcan->Instance==FDCAN3) 80016dc: 687b ldr r3, [r7, #4] 80016de: 681b ldr r3, [r3, #0] 80016e0: 4a34 ldr r2, [pc, #208] ; (80017b4 ) 80016e2: 4293 cmp r3, r2 80016e4: d158 bne.n 8001798 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; 80016e6: f44f 4200 mov.w r2, #32768 ; 0x8000 80016ea: f04f 0300 mov.w r3, #0 80016ee: e9c7 2308 strd r2, r3, [r7, #32] PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; 80016f2: f04f 5380 mov.w r3, #268435456 ; 0x10000000 80016f6: f8c7 308c str.w r3, [r7, #140] ; 0x8c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80016fa: f107 0320 add.w r3, r7, #32 80016fe: 4618 mov r0, r3 8001700: f006 fc9c bl 800803c 8001704: 4603 mov r3, r0 8001706: 2b00 cmp r3, #0 8001708: d001 beq.n 800170e Error_Handler(); 800170a: f7ff fef3 bl 80014f4 HAL_RCC_FDCAN_CLK_ENABLED++; 800170e: 4b25 ldr r3, [pc, #148] ; (80017a4 ) 8001710: 681b ldr r3, [r3, #0] 8001712: 3301 adds r3, #1 8001714: 4a23 ldr r2, [pc, #140] ; (80017a4 ) 8001716: 6013 str r3, [r2, #0] if(HAL_RCC_FDCAN_CLK_ENABLED==1){ 8001718: 4b22 ldr r3, [pc, #136] ; (80017a4 ) 800171a: 681b ldr r3, [r3, #0] 800171c: 2b01 cmp r3, #1 800171e: d10e bne.n 800173e __HAL_RCC_FDCAN_CLK_ENABLE(); 8001720: 4b21 ldr r3, [pc, #132] ; (80017a8 ) 8001722: f8d3 30ec ldr.w r3, [r3, #236] ; 0xec 8001726: 4a20 ldr r2, [pc, #128] ; (80017a8 ) 8001728: f443 7380 orr.w r3, r3, #256 ; 0x100 800172c: f8c2 30ec str.w r3, [r2, #236] ; 0xec 8001730: 4b1d ldr r3, [pc, #116] ; (80017a8 ) 8001732: f8d3 30ec ldr.w r3, [r3, #236] ; 0xec 8001736: f403 7380 and.w r3, r3, #256 ; 0x100 800173a: 60fb str r3, [r7, #12] 800173c: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 800173e: 4b1a ldr r3, [pc, #104] ; (80017a8 ) 8001740: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001744: 4a18 ldr r2, [pc, #96] ; (80017a8 ) 8001746: f043 0308 orr.w r3, r3, #8 800174a: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 800174e: 4b16 ldr r3, [pc, #88] ; (80017a8 ) 8001750: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001754: f003 0308 and.w r3, r3, #8 8001758: 60bb str r3, [r7, #8] 800175a: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_12; 800175c: f44f 5340 mov.w r3, #12288 ; 0x3000 8001760: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001764: 2302 movs r3, #2 8001766: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 800176a: 2300 movs r3, #0 800176c: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001770: 2300 movs r3, #0 8001772: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF5_FDCAN3; 8001776: 2305 movs r3, #5 8001778: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800177c: f107 03dc add.w r3, r7, #220 ; 0xdc 8001780: 4619 mov r1, r3 8001782: 480d ldr r0, [pc, #52] ; (80017b8 ) 8001784: f005 f814 bl 80067b0 HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 5, 0); 8001788: 2200 movs r2, #0 800178a: 2105 movs r1, #5 800178c: 209f movs r0, #159 ; 0x9f 800178e: f000 fee5 bl 800255c HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn); 8001792: 209f movs r0, #159 ; 0x9f 8001794: f000 fefc bl 8002590 } 8001798: bf00 nop 800179a: 37f0 adds r7, #240 ; 0xf0 800179c: 46bd mov sp, r7 800179e: bd80 pop {r7, pc} 80017a0: 4000a000 .word 0x4000a000 80017a4: 24007380 .word 0x24007380 80017a8: 58024400 .word 0x58024400 80017ac: 58020400 .word 0x58020400 80017b0: 4000a400 .word 0x4000a400 80017b4: 4000d400 .word 0x4000d400 80017b8: 58020c00 .word 0x58020c00 080017bc : * This function configures the hardware resources used in this example * @param hsd: SD handle pointer * @retval None */ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) { 80017bc: b580 push {r7, lr} 80017be: b0ba sub sp, #232 ; 0xe8 80017c0: af00 add r7, sp, #0 80017c2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80017c4: f107 03d4 add.w r3, r7, #212 ; 0xd4 80017c8: 2200 movs r2, #0 80017ca: 601a str r2, [r3, #0] 80017cc: 605a str r2, [r3, #4] 80017ce: 609a str r2, [r3, #8] 80017d0: 60da str r2, [r3, #12] 80017d2: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80017d4: f107 0318 add.w r3, r7, #24 80017d8: 22b8 movs r2, #184 ; 0xb8 80017da: 2100 movs r1, #0 80017dc: 4618 mov r0, r3 80017de: f020 fa7f bl 8021ce0 if(hsd->Instance==SDMMC1) 80017e2: 687b ldr r3, [r7, #4] 80017e4: 681b ldr r3, [r3, #0] 80017e6: 4a3c ldr r2, [pc, #240] ; (80018d8 ) 80017e8: 4293 cmp r3, r2 80017ea: d171 bne.n 80018d0 /* USER CODE END SDMMC1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC; 80017ec: f44f 3280 mov.w r2, #65536 ; 0x10000 80017f0: f04f 0300 mov.w r3, #0 80017f4: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; 80017f8: 2300 movs r3, #0 80017fa: 66bb str r3, [r7, #104] ; 0x68 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80017fc: f107 0318 add.w r3, r7, #24 8001800: 4618 mov r0, r3 8001802: f006 fc1b bl 800803c 8001806: 4603 mov r3, r0 8001808: 2b00 cmp r3, #0 800180a: d001 beq.n 8001810 { Error_Handler(); 800180c: f7ff fe72 bl 80014f4 } /* Peripheral clock enable */ __HAL_RCC_SDMMC1_CLK_ENABLE(); 8001810: 4b32 ldr r3, [pc, #200] ; (80018dc ) 8001812: f8d3 30d4 ldr.w r3, [r3, #212] ; 0xd4 8001816: 4a31 ldr r2, [pc, #196] ; (80018dc ) 8001818: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800181c: f8c2 30d4 str.w r3, [r2, #212] ; 0xd4 8001820: 4b2e ldr r3, [pc, #184] ; (80018dc ) 8001822: f8d3 30d4 ldr.w r3, [r3, #212] ; 0xd4 8001826: f403 3380 and.w r3, r3, #65536 ; 0x10000 800182a: 617b str r3, [r7, #20] 800182c: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOD_CLK_ENABLE(); 800182e: 4b2b ldr r3, [pc, #172] ; (80018dc ) 8001830: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001834: 4a29 ldr r2, [pc, #164] ; (80018dc ) 8001836: f043 0308 orr.w r3, r3, #8 800183a: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 800183e: 4b27 ldr r3, [pc, #156] ; (80018dc ) 8001840: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001844: f003 0308 and.w r3, r3, #8 8001848: 613b str r3, [r7, #16] 800184a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800184c: 4b23 ldr r3, [pc, #140] ; (80018dc ) 800184e: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001852: 4a22 ldr r2, [pc, #136] ; (80018dc ) 8001854: f043 0304 orr.w r3, r3, #4 8001858: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 800185c: 4b1f ldr r3, [pc, #124] ; (80018dc ) 800185e: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001862: f003 0304 and.w r3, r3, #4 8001866: 60fb str r3, [r7, #12] 8001868: 68fb ldr r3, [r7, #12] PC10 ------> SDMMC1_D2 PC12 ------> SDMMC1_CK PC9 ------> SDMMC1_D1 PC8 ------> SDMMC1_D0 */ GPIO_InitStruct.Pin = GPIO_PIN_2; 800186a: 2304 movs r3, #4 800186c: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001870: 2302 movs r3, #2 8001872: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001876: 2300 movs r3, #0 8001878: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800187c: 2303 movs r3, #3 800187e: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; 8001882: 230c movs r3, #12 8001884: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001888: f107 03d4 add.w r3, r7, #212 ; 0xd4 800188c: 4619 mov r1, r3 800188e: 4814 ldr r0, [pc, #80] ; (80018e0 ) 8001890: f004 ff8e bl 80067b0 GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_9 8001894: f44f 53f8 mov.w r3, #7936 ; 0x1f00 8001898: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 |GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800189c: 2302 movs r3, #2 800189e: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 80018a2: 2300 movs r3, #0 80018a4: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80018a8: 2303 movs r3, #3 80018aa: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; 80018ae: 230c movs r3, #12 80018b0: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80018b4: f107 03d4 add.w r3, r7, #212 ; 0xd4 80018b8: 4619 mov r1, r3 80018ba: 480a ldr r0, [pc, #40] ; (80018e4 ) 80018bc: f004 ff78 bl 80067b0 /* SDMMC1 interrupt Init */ HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0); 80018c0: 2200 movs r2, #0 80018c2: 2105 movs r1, #5 80018c4: 2031 movs r0, #49 ; 0x31 80018c6: f000 fe49 bl 800255c HAL_NVIC_EnableIRQ(SDMMC1_IRQn); 80018ca: 2031 movs r0, #49 ; 0x31 80018cc: f000 fe60 bl 8002590 /* USER CODE BEGIN SDMMC1_MspInit 1 */ /* USER CODE END SDMMC1_MspInit 1 */ } } 80018d0: bf00 nop 80018d2: 37e8 adds r7, #232 ; 0xe8 80018d4: 46bd mov sp, r7 80018d6: bd80 pop {r7, pc} 80018d8: 52007000 .word 0x52007000 80018dc: 58024400 .word 0x58024400 80018e0: 58020c00 .word 0x58020c00 80018e4: 58020800 .word 0x58020800 080018e8 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 80018e8: b480 push {r7} 80018ea: b085 sub sp, #20 80018ec: af00 add r7, sp, #0 80018ee: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM3) 80018f0: 687b ldr r3, [r7, #4] 80018f2: 681b ldr r3, [r3, #0] 80018f4: 4a0b ldr r2, [pc, #44] ; (8001924 ) 80018f6: 4293 cmp r3, r2 80018f8: d10e bne.n 8001918 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 80018fa: 4b0b ldr r3, [pc, #44] ; (8001928 ) 80018fc: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001900: 4a09 ldr r2, [pc, #36] ; (8001928 ) 8001902: f043 0302 orr.w r3, r3, #2 8001906: f8c2 30e8 str.w r3, [r2, #232] ; 0xe8 800190a: 4b07 ldr r3, [pc, #28] ; (8001928 ) 800190c: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001910: f003 0302 and.w r3, r3, #2 8001914: 60fb str r3, [r7, #12] 8001916: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8001918: bf00 nop 800191a: 3714 adds r7, #20 800191c: 46bd mov sp, r7 800191e: f85d 7b04 ldr.w r7, [sp], #4 8001922: 4770 bx lr 8001924: 40000400 .word 0x40000400 8001928: 58024400 .word 0x58024400 0800192c : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 800192c: b580 push {r7, lr} 800192e: b0bc sub sp, #240 ; 0xf0 8001930: af00 add r7, sp, #0 8001932: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001934: f107 03dc add.w r3, r7, #220 ; 0xdc 8001938: 2200 movs r2, #0 800193a: 601a str r2, [r3, #0] 800193c: 605a str r2, [r3, #4] 800193e: 609a str r2, [r3, #8] 8001940: 60da str r2, [r3, #12] 8001942: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8001944: f107 0320 add.w r3, r7, #32 8001948: 22b8 movs r2, #184 ; 0xb8 800194a: 2100 movs r1, #0 800194c: 4618 mov r0, r3 800194e: f020 f9c7 bl 8021ce0 if(huart->Instance==UART4) 8001952: 687b ldr r3, [r7, #4] 8001954: 681b ldr r3, [r3, #0] 8001956: 4a8a ldr r2, [pc, #552] ; (8001b80 ) 8001958: 4293 cmp r3, r2 800195a: d146 bne.n 80019ea /* USER CODE END UART4_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4; 800195c: f04f 0202 mov.w r2, #2 8001960: f04f 0300 mov.w r3, #0 8001964: e9c7 2308 strd r2, r3, [r7, #32] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8001968: 2300 movs r3, #0 800196a: f8c7 3094 str.w r3, [r7, #148] ; 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800196e: f107 0320 add.w r3, r7, #32 8001972: 4618 mov r0, r3 8001974: f006 fb62 bl 800803c 8001978: 4603 mov r3, r0 800197a: 2b00 cmp r3, #0 800197c: d001 beq.n 8001982 { Error_Handler(); 800197e: f7ff fdb9 bl 80014f4 } /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 8001982: 4b80 ldr r3, [pc, #512] ; (8001b84 ) 8001984: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001988: 4a7e ldr r2, [pc, #504] ; (8001b84 ) 800198a: f443 2300 orr.w r3, r3, #524288 ; 0x80000 800198e: f8c2 30e8 str.w r3, [r2, #232] ; 0xe8 8001992: 4b7c ldr r3, [pc, #496] ; (8001b84 ) 8001994: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001998: f403 2300 and.w r3, r3, #524288 ; 0x80000 800199c: 61fb str r3, [r7, #28] 800199e: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOD_CLK_ENABLE(); 80019a0: 4b78 ldr r3, [pc, #480] ; (8001b84 ) 80019a2: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80019a6: 4a77 ldr r2, [pc, #476] ; (8001b84 ) 80019a8: f043 0308 orr.w r3, r3, #8 80019ac: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 80019b0: 4b74 ldr r3, [pc, #464] ; (8001b84 ) 80019b2: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80019b6: f003 0308 and.w r3, r3, #8 80019ba: 61bb str r3, [r7, #24] 80019bc: 69bb ldr r3, [r7, #24] /**UART4 GPIO Configuration PD0 ------> UART4_RX PD1 ------> UART4_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 80019be: 2303 movs r3, #3 80019c0: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80019c4: 2302 movs r3, #2 80019c6: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 80019ca: 2300 movs r3, #0 80019cc: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80019d0: 2300 movs r3, #0 80019d2: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 80019d6: 2308 movs r3, #8 80019d8: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80019dc: f107 03dc add.w r3, r7, #220 ; 0xdc 80019e0: 4619 mov r1, r3 80019e2: 4869 ldr r0, [pc, #420] ; (8001b88 ) 80019e4: f004 fee4 bl 80067b0 /* USER CODE BEGIN UART8_MspInit 1 */ /* USER CODE END UART8_MspInit 1 */ } } 80019e8: e0c6 b.n 8001b78 else if(huart->Instance==UART7) 80019ea: 687b ldr r3, [r7, #4] 80019ec: 681b ldr r3, [r3, #0] 80019ee: 4a67 ldr r2, [pc, #412] ; (8001b8c ) 80019f0: 4293 cmp r3, r2 80019f2: d147 bne.n 8001a84 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART7; 80019f4: f04f 0202 mov.w r2, #2 80019f8: f04f 0300 mov.w r3, #0 80019fc: e9c7 2308 strd r2, r3, [r7, #32] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8001a00: 2300 movs r3, #0 8001a02: f8c7 3094 str.w r3, [r7, #148] ; 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001a06: f107 0320 add.w r3, r7, #32 8001a0a: 4618 mov r0, r3 8001a0c: f006 fb16 bl 800803c 8001a10: 4603 mov r3, r0 8001a12: 2b00 cmp r3, #0 8001a14: d001 beq.n 8001a1a Error_Handler(); 8001a16: f7ff fd6d bl 80014f4 __HAL_RCC_UART7_CLK_ENABLE(); 8001a1a: 4b5a ldr r3, [pc, #360] ; (8001b84 ) 8001a1c: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001a20: 4a58 ldr r2, [pc, #352] ; (8001b84 ) 8001a22: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 8001a26: f8c2 30e8 str.w r3, [r2, #232] ; 0xe8 8001a2a: 4b56 ldr r3, [pc, #344] ; (8001b84 ) 8001a2c: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001a30: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8001a34: 617b str r3, [r7, #20] 8001a36: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 8001a38: 4b52 ldr r3, [pc, #328] ; (8001b84 ) 8001a3a: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001a3e: 4a51 ldr r2, [pc, #324] ; (8001b84 ) 8001a40: f043 0310 orr.w r3, r3, #16 8001a44: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8001a48: 4b4e ldr r3, [pc, #312] ; (8001b84 ) 8001a4a: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001a4e: f003 0310 and.w r3, r3, #16 8001a52: 613b str r3, [r7, #16] 8001a54: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8; 8001a56: f44f 73c0 mov.w r3, #384 ; 0x180 8001a5a: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001a5e: 2302 movs r3, #2 8001a60: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001a64: 2300 movs r3, #0 8001a66: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001a6a: 2300 movs r3, #0 8001a6c: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF7_UART7; 8001a70: 2307 movs r3, #7 8001a72: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8001a76: f107 03dc add.w r3, r7, #220 ; 0xdc 8001a7a: 4619 mov r1, r3 8001a7c: 4844 ldr r0, [pc, #272] ; (8001b90 ) 8001a7e: f004 fe97 bl 80067b0 } 8001a82: e079 b.n 8001b78 else if(huart->Instance==UART8) 8001a84: 687b ldr r3, [r7, #4] 8001a86: 681b ldr r3, [r3, #0] 8001a88: 4a42 ldr r2, [pc, #264] ; (8001b94 ) 8001a8a: 4293 cmp r3, r2 8001a8c: d174 bne.n 8001b78 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 8001a8e: f04f 0202 mov.w r2, #2 8001a92: f04f 0300 mov.w r3, #0 8001a96: e9c7 2308 strd r2, r3, [r7, #32] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8001a9a: 2300 movs r3, #0 8001a9c: f8c7 3094 str.w r3, [r7, #148] ; 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001aa0: f107 0320 add.w r3, r7, #32 8001aa4: 4618 mov r0, r3 8001aa6: f006 fac9 bl 800803c 8001aaa: 4603 mov r3, r0 8001aac: 2b00 cmp r3, #0 8001aae: d001 beq.n 8001ab4 Error_Handler(); 8001ab0: f7ff fd20 bl 80014f4 __HAL_RCC_UART8_CLK_ENABLE(); 8001ab4: 4b33 ldr r3, [pc, #204] ; (8001b84 ) 8001ab6: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001aba: 4a32 ldr r2, [pc, #200] ; (8001b84 ) 8001abc: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8001ac0: f8c2 30e8 str.w r3, [r2, #232] ; 0xe8 8001ac4: 4b2f ldr r3, [pc, #188] ; (8001b84 ) 8001ac6: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001aca: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8001ace: 60fb str r3, [r7, #12] 8001ad0: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8001ad2: 4b2c ldr r3, [pc, #176] ; (8001b84 ) 8001ad4: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001ad8: 4a2a ldr r2, [pc, #168] ; (8001b84 ) 8001ada: f043 0310 orr.w r3, r3, #16 8001ade: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8001ae2: 4b28 ldr r3, [pc, #160] ; (8001b84 ) 8001ae4: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001ae8: f003 0310 and.w r3, r3, #16 8001aec: 60bb str r3, [r7, #8] 8001aee: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0; 8001af0: 2303 movs r3, #3 8001af2: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001af6: 2302 movs r3, #2 8001af8: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001afc: 2300 movs r3, #0 8001afe: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001b02: 2300 movs r3, #0 8001b04: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 8001b08: 2308 movs r3, #8 8001b0a: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8001b0e: f107 03dc add.w r3, r7, #220 ; 0xdc 8001b12: 4619 mov r1, r3 8001b14: 481e ldr r0, [pc, #120] ; (8001b90 ) 8001b16: f004 fe4b bl 80067b0 hdma_uart8_rx.Instance = DMA1_Stream0; 8001b1a: 4b1f ldr r3, [pc, #124] ; (8001b98 ) 8001b1c: 4a1f ldr r2, [pc, #124] ; (8001b9c ) 8001b1e: 601a str r2, [r3, #0] hdma_uart8_rx.Init.Request = DMA_REQUEST_UART8_RX; 8001b20: 4b1d ldr r3, [pc, #116] ; (8001b98 ) 8001b22: 2251 movs r2, #81 ; 0x51 8001b24: 605a str r2, [r3, #4] hdma_uart8_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001b26: 4b1c ldr r3, [pc, #112] ; (8001b98 ) 8001b28: 2200 movs r2, #0 8001b2a: 609a str r2, [r3, #8] hdma_uart8_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001b2c: 4b1a ldr r3, [pc, #104] ; (8001b98 ) 8001b2e: 2200 movs r2, #0 8001b30: 60da str r2, [r3, #12] hdma_uart8_rx.Init.MemInc = DMA_MINC_ENABLE; 8001b32: 4b19 ldr r3, [pc, #100] ; (8001b98 ) 8001b34: f44f 6280 mov.w r2, #1024 ; 0x400 8001b38: 611a str r2, [r3, #16] hdma_uart8_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001b3a: 4b17 ldr r3, [pc, #92] ; (8001b98 ) 8001b3c: 2200 movs r2, #0 8001b3e: 615a str r2, [r3, #20] hdma_uart8_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001b40: 4b15 ldr r3, [pc, #84] ; (8001b98 ) 8001b42: 2200 movs r2, #0 8001b44: 619a str r2, [r3, #24] hdma_uart8_rx.Init.Mode = DMA_CIRCULAR; 8001b46: 4b14 ldr r3, [pc, #80] ; (8001b98 ) 8001b48: f44f 7280 mov.w r2, #256 ; 0x100 8001b4c: 61da str r2, [r3, #28] hdma_uart8_rx.Init.Priority = DMA_PRIORITY_LOW; 8001b4e: 4b12 ldr r3, [pc, #72] ; (8001b98 ) 8001b50: 2200 movs r2, #0 8001b52: 621a str r2, [r3, #32] hdma_uart8_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001b54: 4b10 ldr r3, [pc, #64] ; (8001b98 ) 8001b56: 2200 movs r2, #0 8001b58: 625a str r2, [r3, #36] ; 0x24 if (HAL_DMA_Init(&hdma_uart8_rx) != HAL_OK) 8001b5a: 480f ldr r0, [pc, #60] ; (8001b98 ) 8001b5c: f000 fda2 bl 80026a4 8001b60: 4603 mov r3, r0 8001b62: 2b00 cmp r3, #0 8001b64: d001 beq.n 8001b6a Error_Handler(); 8001b66: f7ff fcc5 bl 80014f4 __HAL_LINKDMA(huart,hdmarx,hdma_uart8_rx); 8001b6a: 687b ldr r3, [r7, #4] 8001b6c: 4a0a ldr r2, [pc, #40] ; (8001b98 ) 8001b6e: f8c3 2080 str.w r2, [r3, #128] ; 0x80 8001b72: 4a09 ldr r2, [pc, #36] ; (8001b98 ) 8001b74: 687b ldr r3, [r7, #4] 8001b76: 6393 str r3, [r2, #56] ; 0x38 } 8001b78: bf00 nop 8001b7a: 37f0 adds r7, #240 ; 0xf0 8001b7c: 46bd mov sp, r7 8001b7e: bd80 pop {r7, pc} 8001b80: 40004c00 .word 0x40004c00 8001b84: 58024400 .word 0x58024400 8001b88: 58020c00 .word 0x58020c00 8001b8c: 40007800 .word 0x40007800 8001b90: 58021000 .word 0x58021000 8001b94: 40007c00 .word 0x40007c00 8001b98: 240011cc .word 0x240011cc 8001b9c: 40020010 .word 0x40020010 08001ba0 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001ba0: b580 push {r7, lr} 8001ba2: b090 sub sp, #64 ; 0x40 8001ba4: af00 add r7, sp, #0 8001ba6: 6078 str r0, [r7, #4] uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001ba8: 687b ldr r3, [r7, #4] 8001baa: 2b0f cmp r3, #15 8001bac: d827 bhi.n 8001bfe { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 8001bae: 2200 movs r2, #0 8001bb0: 6879 ldr r1, [r7, #4] 8001bb2: 2036 movs r0, #54 ; 0x36 8001bb4: f000 fcd2 bl 800255c /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8001bb8: 2036 movs r0, #54 ; 0x36 8001bba: f000 fce9 bl 8002590 uwTickPrio = TickPriority; 8001bbe: 4a29 ldr r2, [pc, #164] ; (8001c64 ) 8001bc0: 687b ldr r3, [r7, #4] 8001bc2: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 8001bc4: 4b28 ldr r3, [pc, #160] ; (8001c68 ) 8001bc6: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001bca: 4a27 ldr r2, [pc, #156] ; (8001c68 ) 8001bcc: f043 0310 orr.w r3, r3, #16 8001bd0: f8c2 30e8 str.w r3, [r2, #232] ; 0xe8 8001bd4: 4b24 ldr r3, [pc, #144] ; (8001c68 ) 8001bd6: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001bda: f003 0310 and.w r3, r3, #16 8001bde: 60fb str r3, [r7, #12] 8001be0: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8001be2: f107 0210 add.w r2, r7, #16 8001be6: f107 0314 add.w r3, r7, #20 8001bea: 4611 mov r1, r2 8001bec: 4618 mov r0, r3 8001bee: f006 f9e3 bl 8007fb8 /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 8001bf2: 6abb ldr r3, [r7, #40] ; 0x28 8001bf4: 63bb str r3, [r7, #56] ; 0x38 /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 8001bf6: 6bbb ldr r3, [r7, #56] ; 0x38 8001bf8: 2b00 cmp r3, #0 8001bfa: d106 bne.n 8001c0a 8001bfc: e001 b.n 8001c02 return HAL_ERROR; 8001bfe: 2301 movs r3, #1 8001c00: e02b b.n 8001c5a { uwTimclock = HAL_RCC_GetPCLK1Freq(); 8001c02: f006 f9ad bl 8007f60 8001c06: 63f8 str r0, [r7, #60] ; 0x3c 8001c08: e004 b.n 8001c14 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 8001c0a: f006 f9a9 bl 8007f60 8001c0e: 4603 mov r3, r0 8001c10: 005b lsls r3, r3, #1 8001c12: 63fb str r3, [r7, #60] ; 0x3c } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8001c14: 6bfb ldr r3, [r7, #60] ; 0x3c 8001c16: 4a15 ldr r2, [pc, #84] ; (8001c6c ) 8001c18: fba2 2303 umull r2, r3, r2, r3 8001c1c: 0c9b lsrs r3, r3, #18 8001c1e: 3b01 subs r3, #1 8001c20: 637b str r3, [r7, #52] ; 0x34 /* Initialize TIM6 */ htim6.Instance = TIM6; 8001c22: 4b13 ldr r3, [pc, #76] ; (8001c70 ) 8001c24: 4a13 ldr r2, [pc, #76] ; (8001c74 ) 8001c26: 601a str r2, [r3, #0] + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 8001c28: 4b11 ldr r3, [pc, #68] ; (8001c70 ) 8001c2a: f240 32e7 movw r2, #999 ; 0x3e7 8001c2e: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 8001c30: 4a0f ldr r2, [pc, #60] ; (8001c70 ) 8001c32: 6b7b ldr r3, [r7, #52] ; 0x34 8001c34: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 8001c36: 4b0e ldr r3, [pc, #56] ; (8001c70 ) 8001c38: 2200 movs r2, #0 8001c3a: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8001c3c: 4b0c ldr r3, [pc, #48] ; (8001c70 ) 8001c3e: 2200 movs r2, #0 8001c40: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 8001c42: 480b ldr r0, [pc, #44] ; (8001c70 ) 8001c44: f00a fa44 bl 800c0d0 8001c48: 4603 mov r3, r0 8001c4a: 2b00 cmp r3, #0 8001c4c: d104 bne.n 8001c58 { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim6); 8001c4e: 4808 ldr r0, [pc, #32] ; (8001c70 ) 8001c50: f00a fa96 bl 800c180 8001c54: 4603 mov r3, r0 8001c56: e000 b.n 8001c5a } /* Return function status */ return HAL_ERROR; 8001c58: 2301 movs r3, #1 } 8001c5a: 4618 mov r0, r3 8001c5c: 3740 adds r7, #64 ; 0x40 8001c5e: 46bd mov sp, r7 8001c60: bd80 pop {r7, pc} 8001c62: bf00 nop 8001c64: 2400001c .word 0x2400001c 8001c68: 58024400 .word 0x58024400 8001c6c: 431bde83 .word 0x431bde83 8001c70: 24007384 .word 0x24007384 8001c74: 40001000 .word 0x40001000 08001c78 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001c78: b480 push {r7} 8001c7a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8001c7c: e7fe b.n 8001c7c 08001c7e : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8001c7e: b480 push {r7} 8001c80: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8001c82: e7fe b.n 8001c82 08001c84 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001c84: b480 push {r7} 8001c86: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001c88: e7fe b.n 8001c88 08001c8a : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8001c8a: b480 push {r7} 8001c8c: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8001c8e: e7fe b.n 8001c8e 08001c90 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001c90: b480 push {r7} 8001c92: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001c94: e7fe b.n 8001c94 08001c96 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8001c96: b480 push {r7} 8001c98: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8001c9a: bf00 nop 8001c9c: 46bd mov sp, r7 8001c9e: f85d 7b04 ldr.w r7, [sp], #4 8001ca2: 4770 bx lr 08001ca4 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8001ca4: b580 push {r7, lr} 8001ca6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart8_rx); 8001ca8: 4802 ldr r0, [pc, #8] ; (8001cb4 ) 8001caa: f001 f853 bl 8002d54 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 8001cae: bf00 nop 8001cb0: bd80 pop {r7, pc} 8001cb2: bf00 nop 8001cb4: 240011cc .word 0x240011cc 08001cb8 : /** * @brief This function handles FDCAN1 interrupt 0. */ void FDCAN1_IT0_IRQHandler(void) { 8001cb8: b580 push {r7, lr} 8001cba: af00 add r7, sp, #0 /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ /* USER CODE END FDCAN1_IT0_IRQn 0 */ HAL_FDCAN_IRQHandler(&hfdcan1); 8001cbc: 4802 ldr r0, [pc, #8] ; (8001cc8 ) 8001cbe: f004 f8ef bl 8005ea0 /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */ /* USER CODE END FDCAN1_IT0_IRQn 1 */ } 8001cc2: bf00 nop 8001cc4: bd80 pop {r7, pc} 8001cc6: bf00 nop 8001cc8: 24000d68 .word 0x24000d68 08001ccc : /** * @brief This function handles FDCAN2 interrupt 0. */ void FDCAN2_IT0_IRQHandler(void) { 8001ccc: b580 push {r7, lr} 8001cce: af00 add r7, sp, #0 /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ /* USER CODE END FDCAN2_IT0_IRQn 0 */ HAL_FDCAN_IRQHandler(&hfdcan2); 8001cd0: 4802 ldr r0, [pc, #8] ; (8001cdc ) 8001cd2: f004 f8e5 bl 8005ea0 /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ /* USER CODE END FDCAN2_IT0_IRQn 1 */ } 8001cd6: bf00 nop 8001cd8: bd80 pop {r7, pc} 8001cda: bf00 nop 8001cdc: 24000e08 .word 0x24000e08 08001ce0 : /** * @brief This function handles SDMMC1 global interrupt. */ void SDMMC1_IRQHandler(void) { 8001ce0: b580 push {r7, lr} 8001ce2: af00 add r7, sp, #0 /* USER CODE BEGIN SDMMC1_IRQn 0 */ /* USER CODE END SDMMC1_IRQn 0 */ HAL_SD_IRQHandler(&hsd1); 8001ce4: 4802 ldr r0, [pc, #8] ; (8001cf0 ) 8001ce6: f008 ffff bl 800ace8 /* USER CODE BEGIN SDMMC1_IRQn 1 */ /* USER CODE END SDMMC1_IRQn 1 */ } 8001cea: bf00 nop 8001cec: bd80 pop {r7, pc} 8001cee: bf00 nop 8001cf0: 24000f48 .word 0x24000f48 08001cf4 : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8001cf4: b580 push {r7, lr} 8001cf6: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 8001cf8: 4802 ldr r0, [pc, #8] ; (8001d04 ) 8001cfa: f00a fac7 bl 800c28c /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 8001cfe: bf00 nop 8001d00: bd80 pop {r7, pc} 8001d02: bf00 nop 8001d04: 24007384 .word 0x24007384 08001d08 : /** * @brief This function handles Ethernet global interrupt. */ void ETH_IRQHandler(void) { 8001d08: b580 push {r7, lr} 8001d0a: af00 add r7, sp, #0 /* USER CODE BEGIN ETH_IRQn 0 */ /* USER CODE END ETH_IRQn 0 */ HAL_ETH_IRQHandler(&heth); 8001d0c: 4802 ldr r0, [pc, #8] ; (8001d18 ) 8001d0e: f002 fd4b bl 80047a8 /* USER CODE BEGIN ETH_IRQn 1 */ /* USER CODE END ETH_IRQn 1 */ } 8001d12: bf00 nop 8001d14: bd80 pop {r7, pc} 8001d16: bf00 nop 8001d18: 2400bdcc .word 0x2400bdcc 08001d1c : /** * @brief This function handles MDMA global interrupt. */ void MDMA_IRQHandler(void) { 8001d1c: b580 push {r7, lr} 8001d1e: af00 add r7, sp, #0 /* USER CODE BEGIN MDMA_IRQn 0 */ /* USER CODE END MDMA_IRQn 0 */ HAL_MDMA_IRQHandler(&hmdma_mdma_channel0_sdmmc1_end_data_0); 8001d20: 4802 ldr r0, [pc, #8] ; (8001d2c ) 8001d22: f004 ffbd bl 8006ca0 /* USER CODE BEGIN MDMA_IRQn 1 */ /* USER CODE END MDMA_IRQn 1 */ } 8001d26: bf00 nop 8001d28: bd80 pop {r7, pc} 8001d2a: bf00 nop 8001d2c: 24001244 .word 0x24001244 08001d30 : /** * @brief This function handles FDCAN3 interrupt 0. */ void FDCAN3_IT0_IRQHandler(void) { 8001d30: b580 push {r7, lr} 8001d32: af00 add r7, sp, #0 /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */ /* USER CODE END FDCAN3_IT0_IRQn 0 */ HAL_FDCAN_IRQHandler(&hfdcan3); 8001d34: 4802 ldr r0, [pc, #8] ; (8001d40 ) 8001d36: f004 f8b3 bl 8005ea0 /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */ /* USER CODE END FDCAN3_IT0_IRQn 1 */ } 8001d3a: bf00 nop 8001d3c: bd80 pop {r7, pc} 8001d3e: bf00 nop 8001d40: 24000ea8 .word 0x24000ea8 08001d44 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 8001d44: b480 push {r7} 8001d46: af00 add r7, sp, #0 return 1; 8001d48: 2301 movs r3, #1 } 8001d4a: 4618 mov r0, r3 8001d4c: 46bd mov sp, r7 8001d4e: f85d 7b04 ldr.w r7, [sp], #4 8001d52: 4770 bx lr 08001d54 <_kill>: int _kill(int pid, int sig) { 8001d54: b480 push {r7} 8001d56: b083 sub sp, #12 8001d58: af00 add r7, sp, #0 8001d5a: 6078 str r0, [r7, #4] 8001d5c: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 8001d5e: 4b05 ldr r3, [pc, #20] ; (8001d74 <_kill+0x20>) 8001d60: 2216 movs r2, #22 8001d62: 601a str r2, [r3, #0] return -1; 8001d64: f04f 33ff mov.w r3, #4294967295 } 8001d68: 4618 mov r0, r3 8001d6a: 370c adds r7, #12 8001d6c: 46bd mov sp, r7 8001d6e: f85d 7b04 ldr.w r7, [sp], #4 8001d72: 4770 bx lr 8001d74: 2401a5e0 .word 0x2401a5e0 08001d78 <_exit>: void _exit (int status) { 8001d78: b580 push {r7, lr} 8001d7a: b082 sub sp, #8 8001d7c: af00 add r7, sp, #0 8001d7e: 6078 str r0, [r7, #4] _kill(status, -1); 8001d80: f04f 31ff mov.w r1, #4294967295 8001d84: 6878 ldr r0, [r7, #4] 8001d86: f7ff ffe5 bl 8001d54 <_kill> while (1) {} /* Make sure we hang here */ 8001d8a: e7fe b.n 8001d8a <_exit+0x12> 08001d8c <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8001d8c: b580 push {r7, lr} 8001d8e: b086 sub sp, #24 8001d90: af00 add r7, sp, #0 8001d92: 60f8 str r0, [r7, #12] 8001d94: 60b9 str r1, [r7, #8] 8001d96: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8001d98: 2300 movs r3, #0 8001d9a: 617b str r3, [r7, #20] 8001d9c: e00a b.n 8001db4 <_read+0x28> { *ptr++ = __io_getchar(); 8001d9e: f3af 8000 nop.w 8001da2: 4601 mov r1, r0 8001da4: 68bb ldr r3, [r7, #8] 8001da6: 1c5a adds r2, r3, #1 8001da8: 60ba str r2, [r7, #8] 8001daa: b2ca uxtb r2, r1 8001dac: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8001dae: 697b ldr r3, [r7, #20] 8001db0: 3301 adds r3, #1 8001db2: 617b str r3, [r7, #20] 8001db4: 697a ldr r2, [r7, #20] 8001db6: 687b ldr r3, [r7, #4] 8001db8: 429a cmp r2, r3 8001dba: dbf0 blt.n 8001d9e <_read+0x12> } return len; 8001dbc: 687b ldr r3, [r7, #4] } 8001dbe: 4618 mov r0, r3 8001dc0: 3718 adds r7, #24 8001dc2: 46bd mov sp, r7 8001dc4: bd80 pop {r7, pc} 08001dc6 <_close>: } return len; } int _close(int file) { 8001dc6: b480 push {r7} 8001dc8: b083 sub sp, #12 8001dca: af00 add r7, sp, #0 8001dcc: 6078 str r0, [r7, #4] (void)file; return -1; 8001dce: f04f 33ff mov.w r3, #4294967295 } 8001dd2: 4618 mov r0, r3 8001dd4: 370c adds r7, #12 8001dd6: 46bd mov sp, r7 8001dd8: f85d 7b04 ldr.w r7, [sp], #4 8001ddc: 4770 bx lr 08001dde <_fstat>: int _fstat(int file, struct stat *st) { 8001dde: b480 push {r7} 8001de0: b083 sub sp, #12 8001de2: af00 add r7, sp, #0 8001de4: 6078 str r0, [r7, #4] 8001de6: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 8001de8: 683b ldr r3, [r7, #0] 8001dea: f44f 5200 mov.w r2, #8192 ; 0x2000 8001dee: 605a str r2, [r3, #4] return 0; 8001df0: 2300 movs r3, #0 } 8001df2: 4618 mov r0, r3 8001df4: 370c adds r7, #12 8001df6: 46bd mov sp, r7 8001df8: f85d 7b04 ldr.w r7, [sp], #4 8001dfc: 4770 bx lr 08001dfe <_isatty>: int _isatty(int file) { 8001dfe: b480 push {r7} 8001e00: b083 sub sp, #12 8001e02: af00 add r7, sp, #0 8001e04: 6078 str r0, [r7, #4] (void)file; return 1; 8001e06: 2301 movs r3, #1 } 8001e08: 4618 mov r0, r3 8001e0a: 370c adds r7, #12 8001e0c: 46bd mov sp, r7 8001e0e: f85d 7b04 ldr.w r7, [sp], #4 8001e12: 4770 bx lr 08001e14 <_lseek>: int _lseek(int file, int ptr, int dir) { 8001e14: b480 push {r7} 8001e16: b085 sub sp, #20 8001e18: af00 add r7, sp, #0 8001e1a: 60f8 str r0, [r7, #12] 8001e1c: 60b9 str r1, [r7, #8] 8001e1e: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 8001e20: 2300 movs r3, #0 } 8001e22: 4618 mov r0, r3 8001e24: 3714 adds r7, #20 8001e26: 46bd mov sp, r7 8001e28: f85d 7b04 ldr.w r7, [sp], #4 8001e2c: 4770 bx lr ... 08001e30 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8001e30: b480 push {r7} 8001e32: b087 sub sp, #28 8001e34: af00 add r7, sp, #0 8001e36: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8001e38: 4a14 ldr r2, [pc, #80] ; (8001e8c <_sbrk+0x5c>) 8001e3a: 4b15 ldr r3, [pc, #84] ; (8001e90 <_sbrk+0x60>) 8001e3c: 1ad3 subs r3, r2, r3 8001e3e: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8001e40: 697b ldr r3, [r7, #20] 8001e42: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8001e44: 4b13 ldr r3, [pc, #76] ; (8001e94 <_sbrk+0x64>) 8001e46: 681b ldr r3, [r3, #0] 8001e48: 2b00 cmp r3, #0 8001e4a: d102 bne.n 8001e52 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8001e4c: 4b11 ldr r3, [pc, #68] ; (8001e94 <_sbrk+0x64>) 8001e4e: 4a12 ldr r2, [pc, #72] ; (8001e98 <_sbrk+0x68>) 8001e50: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8001e52: 4b10 ldr r3, [pc, #64] ; (8001e94 <_sbrk+0x64>) 8001e54: 681a ldr r2, [r3, #0] 8001e56: 687b ldr r3, [r7, #4] 8001e58: 4413 add r3, r2 8001e5a: 693a ldr r2, [r7, #16] 8001e5c: 429a cmp r2, r3 8001e5e: d205 bcs.n 8001e6c <_sbrk+0x3c> { errno = ENOMEM; 8001e60: 4b0e ldr r3, [pc, #56] ; (8001e9c <_sbrk+0x6c>) 8001e62: 220c movs r2, #12 8001e64: 601a str r2, [r3, #0] return (void *)-1; 8001e66: f04f 33ff mov.w r3, #4294967295 8001e6a: e009 b.n 8001e80 <_sbrk+0x50> } prev_heap_end = __sbrk_heap_end; 8001e6c: 4b09 ldr r3, [pc, #36] ; (8001e94 <_sbrk+0x64>) 8001e6e: 681b ldr r3, [r3, #0] 8001e70: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8001e72: 4b08 ldr r3, [pc, #32] ; (8001e94 <_sbrk+0x64>) 8001e74: 681a ldr r2, [r3, #0] 8001e76: 687b ldr r3, [r7, #4] 8001e78: 4413 add r3, r2 8001e7a: 4a06 ldr r2, [pc, #24] ; (8001e94 <_sbrk+0x64>) 8001e7c: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8001e7e: 68fb ldr r3, [r7, #12] } 8001e80: 4618 mov r0, r3 8001e82: 371c adds r7, #28 8001e84: 46bd mov sp, r7 8001e86: f85d 7b04 ldr.w r7, [sp], #4 8001e8a: 4770 bx lr 8001e8c: 24050000 .word 0x24050000 8001e90: 00004000 .word 0x00004000 8001e94: 240073d0 .word 0x240073d0 8001e98: 2401a730 .word 0x2401a730 8001e9c: 2401a5e0 .word 0x2401a5e0 08001ea0 : * configuration. * @param None * @retval None */ void SystemInit (void) { 8001ea0: b480 push {r7} 8001ea2: b083 sub sp, #12 8001ea4: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8001ea6: 4b3a ldr r3, [pc, #232] ; (8001f90 ) 8001ea8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001eac: 4a38 ldr r2, [pc, #224] ; (8001f90 ) 8001eae: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8001eb2: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8001eb6: 4b37 ldr r3, [pc, #220] ; (8001f94 ) 8001eb8: 681b ldr r3, [r3, #0] 8001eba: f003 030f and.w r3, r3, #15 8001ebe: 2b06 cmp r3, #6 8001ec0: d807 bhi.n 8001ed2 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8001ec2: 4b34 ldr r3, [pc, #208] ; (8001f94 ) 8001ec4: 681b ldr r3, [r3, #0] 8001ec6: f023 030f bic.w r3, r3, #15 8001eca: 4a32 ldr r2, [pc, #200] ; (8001f94 ) 8001ecc: f043 0307 orr.w r3, r3, #7 8001ed0: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 8001ed2: 4b31 ldr r3, [pc, #196] ; (8001f98 ) 8001ed4: 681b ldr r3, [r3, #0] 8001ed6: 4a30 ldr r2, [pc, #192] ; (8001f98 ) 8001ed8: f043 0301 orr.w r3, r3, #1 8001edc: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8001ede: 4b2e ldr r3, [pc, #184] ; (8001f98 ) 8001ee0: 2200 movs r2, #0 8001ee2: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 8001ee4: 4b2c ldr r3, [pc, #176] ; (8001f98 ) 8001ee6: 681a ldr r2, [r3, #0] 8001ee8: 492b ldr r1, [pc, #172] ; (8001f98 ) 8001eea: 4b2c ldr r3, [pc, #176] ; (8001f9c ) 8001eec: 4013 ands r3, r2 8001eee: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8001ef0: 4b28 ldr r3, [pc, #160] ; (8001f94 ) 8001ef2: 681b ldr r3, [r3, #0] 8001ef4: f003 0308 and.w r3, r3, #8 8001ef8: 2b00 cmp r3, #0 8001efa: d007 beq.n 8001f0c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8001efc: 4b25 ldr r3, [pc, #148] ; (8001f94 ) 8001efe: 681b ldr r3, [r3, #0] 8001f00: f023 030f bic.w r3, r3, #15 8001f04: 4a23 ldr r2, [pc, #140] ; (8001f94 ) 8001f06: f043 0307 orr.w r3, r3, #7 8001f0a: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 8001f0c: 4b22 ldr r3, [pc, #136] ; (8001f98 ) 8001f0e: 2200 movs r2, #0 8001f10: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 8001f12: 4b21 ldr r3, [pc, #132] ; (8001f98 ) 8001f14: 2200 movs r2, #0 8001f16: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 8001f18: 4b1f ldr r3, [pc, #124] ; (8001f98 ) 8001f1a: 2200 movs r2, #0 8001f1c: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 8001f1e: 4b1e ldr r3, [pc, #120] ; (8001f98 ) 8001f20: 4a1f ldr r2, [pc, #124] ; (8001fa0 ) 8001f22: 629a str r2, [r3, #40] ; 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 8001f24: 4b1c ldr r3, [pc, #112] ; (8001f98 ) 8001f26: 4a1f ldr r2, [pc, #124] ; (8001fa4 ) 8001f28: 62da str r2, [r3, #44] ; 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 8001f2a: 4b1b ldr r3, [pc, #108] ; (8001f98 ) 8001f2c: 4a1e ldr r2, [pc, #120] ; (8001fa8 ) 8001f2e: 631a str r2, [r3, #48] ; 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 8001f30: 4b19 ldr r3, [pc, #100] ; (8001f98 ) 8001f32: 2200 movs r2, #0 8001f34: 635a str r2, [r3, #52] ; 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8001f36: 4b18 ldr r3, [pc, #96] ; (8001f98 ) 8001f38: 4a1b ldr r2, [pc, #108] ; (8001fa8 ) 8001f3a: 639a str r2, [r3, #56] ; 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 8001f3c: 4b16 ldr r3, [pc, #88] ; (8001f98 ) 8001f3e: 2200 movs r2, #0 8001f40: 63da str r2, [r3, #60] ; 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 8001f42: 4b15 ldr r3, [pc, #84] ; (8001f98 ) 8001f44: 4a18 ldr r2, [pc, #96] ; (8001fa8 ) 8001f46: 641a str r2, [r3, #64] ; 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 8001f48: 4b13 ldr r3, [pc, #76] ; (8001f98 ) 8001f4a: 2200 movs r2, #0 8001f4c: 645a str r2, [r3, #68] ; 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8001f4e: 4b12 ldr r3, [pc, #72] ; (8001f98 ) 8001f50: 681b ldr r3, [r3, #0] 8001f52: 4a11 ldr r2, [pc, #68] ; (8001f98 ) 8001f54: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8001f58: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8001f5a: 4b0f ldr r3, [pc, #60] ; (8001f98 ) 8001f5c: 2200 movs r2, #0 8001f5e: 661a str r2, [r3, #96] ; 0x60 #if defined(DATA_IN_D2_SRAM) /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */ #if defined(RCC_AHB2ENR_D2SRAM3EN) RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); #elif defined(RCC_AHB2ENR_D2SRAM2EN) RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); 8001f60: 4b0d ldr r3, [pc, #52] ; (8001f98 ) 8001f62: f8d3 30dc ldr.w r3, [r3, #220] ; 0xdc 8001f66: 4a0c ldr r2, [pc, #48] ; (8001f98 ) 8001f68: f043 43c0 orr.w r3, r3, #1610612736 ; 0x60000000 8001f6c: f8c2 30dc str.w r3, [r2, #220] ; 0xdc #else RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); #endif /* RCC_AHB2ENR_D2SRAM3EN */ tmpreg = RCC->AHB2ENR; 8001f70: 4b09 ldr r3, [pc, #36] ; (8001f98 ) 8001f72: f8d3 30dc ldr.w r3, [r3, #220] ; 0xdc 8001f76: 607b str r3, [r7, #4] (void) tmpreg; 8001f78: 687b ldr r3, [r7, #4] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 8001f7a: 4b0c ldr r3, [pc, #48] ; (8001fac ) 8001f7c: f243 02d2 movw r2, #12498 ; 0x30d2 8001f80: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 8001f82: bf00 nop 8001f84: 370c adds r7, #12 8001f86: 46bd mov sp, r7 8001f88: f85d 7b04 ldr.w r7, [sp], #4 8001f8c: 4770 bx lr 8001f8e: bf00 nop 8001f90: e000ed00 .word 0xe000ed00 8001f94: 52002000 .word 0x52002000 8001f98: 58024400 .word 0x58024400 8001f9c: eaf6ed7f .word 0xeaf6ed7f 8001fa0: 02020200 .word 0x02020200 8001fa4: 01ff0000 .word 0x01ff0000 8001fa8: 01010280 .word 0x01010280 8001fac: 52004000 .word 0x52004000 08001fb0 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001fb0: f8df d034 ldr.w sp, [pc, #52] ; 8001fe8 /* Call the clock system initialization function.*/ bl SystemInit 8001fb4: f7ff ff74 bl 8001ea0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001fb8: 480c ldr r0, [pc, #48] ; (8001fec ) ldr r1, =_edata 8001fba: 490d ldr r1, [pc, #52] ; (8001ff0 ) ldr r2, =_sidata 8001fbc: 4a0d ldr r2, [pc, #52] ; (8001ff4 ) movs r3, #0 8001fbe: 2300 movs r3, #0 b LoopCopyDataInit 8001fc0: e002 b.n 8001fc8 08001fc2 : CopyDataInit: ldr r4, [r2, r3] 8001fc2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001fc4: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001fc6: 3304 adds r3, #4 08001fc8 : LoopCopyDataInit: adds r4, r0, r3 8001fc8: 18c4 adds r4, r0, r3 cmp r4, r1 8001fca: 428c cmp r4, r1 bcc CopyDataInit 8001fcc: d3f9 bcc.n 8001fc2 /* Zero fill the bss segment. */ ldr r2, =_sbss 8001fce: 4a0a ldr r2, [pc, #40] ; (8001ff8 ) ldr r4, =_ebss 8001fd0: 4c0a ldr r4, [pc, #40] ; (8001ffc ) movs r3, #0 8001fd2: 2300 movs r3, #0 b LoopFillZerobss 8001fd4: e001 b.n 8001fda 08001fd6 : FillZerobss: str r3, [r2] 8001fd6: 6013 str r3, [r2, #0] adds r2, r2, #4 8001fd8: 3204 adds r2, #4 08001fda : LoopFillZerobss: cmp r2, r4 8001fda: 42a2 cmp r2, r4 bcc FillZerobss 8001fdc: d3fb bcc.n 8001fd6 /* Call static constructors */ bl __libc_init_array 8001fde: f01f fedb bl 8021d98 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001fe2: f7fe fbff bl 80007e4
bx lr 8001fe6: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001fe8: 24050000 .word 0x24050000 ldr r0, =_sdata 8001fec: 24000000 .word 0x24000000 ldr r1, =_edata 8001ff0: 240000a4 .word 0x240000a4 ldr r2, =_sidata 8001ff4: 08026ef8 .word 0x08026ef8 ldr r2, =_sbss 8001ff8: 240000a4 .word 0x240000a4 ldr r4, =_ebss 8001ffc: 2401a730 .word 0x2401a730 08002000 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8002000: e7fe b.n 8002000 08002002 : * @param ioctx: holds device IO functions. * @retval LAN8742_STATUS_OK if OK * LAN8742_STATUS_ERROR if missing mandatory function */ int32_t LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx) { 8002002: b480 push {r7} 8002004: b083 sub sp, #12 8002006: af00 add r7, sp, #0 8002008: 6078 str r0, [r7, #4] 800200a: 6039 str r1, [r7, #0] if(!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick) 800200c: 687b ldr r3, [r7, #4] 800200e: 2b00 cmp r3, #0 8002010: d00b beq.n 800202a 8002012: 683b ldr r3, [r7, #0] 8002014: 68db ldr r3, [r3, #12] 8002016: 2b00 cmp r3, #0 8002018: d007 beq.n 800202a 800201a: 683b ldr r3, [r7, #0] 800201c: 689b ldr r3, [r3, #8] 800201e: 2b00 cmp r3, #0 8002020: d003 beq.n 800202a 8002022: 683b ldr r3, [r7, #0] 8002024: 691b ldr r3, [r3, #16] 8002026: 2b00 cmp r3, #0 8002028: d102 bne.n 8002030 { return LAN8742_STATUS_ERROR; 800202a: f04f 33ff mov.w r3, #4294967295 800202e: e014 b.n 800205a } pObj->IO.Init = ioctx->Init; 8002030: 683b ldr r3, [r7, #0] 8002032: 681a ldr r2, [r3, #0] 8002034: 687b ldr r3, [r7, #4] 8002036: 609a str r2, [r3, #8] pObj->IO.DeInit = ioctx->DeInit; 8002038: 683b ldr r3, [r7, #0] 800203a: 685a ldr r2, [r3, #4] 800203c: 687b ldr r3, [r7, #4] 800203e: 60da str r2, [r3, #12] pObj->IO.ReadReg = ioctx->ReadReg; 8002040: 683b ldr r3, [r7, #0] 8002042: 68da ldr r2, [r3, #12] 8002044: 687b ldr r3, [r7, #4] 8002046: 615a str r2, [r3, #20] pObj->IO.WriteReg = ioctx->WriteReg; 8002048: 683b ldr r3, [r7, #0] 800204a: 689a ldr r2, [r3, #8] 800204c: 687b ldr r3, [r7, #4] 800204e: 611a str r2, [r3, #16] pObj->IO.GetTick = ioctx->GetTick; 8002050: 683b ldr r3, [r7, #0] 8002052: 691a ldr r2, [r3, #16] 8002054: 687b ldr r3, [r7, #4] 8002056: 619a str r2, [r3, #24] return LAN8742_STATUS_OK; 8002058: 2300 movs r3, #0 } 800205a: 4618 mov r0, r3 800205c: 370c adds r7, #12 800205e: 46bd mov sp, r7 8002060: f85d 7b04 ldr.w r7, [sp], #4 8002064: 4770 bx lr 08002066 : * LAN8742_STATUS_READ_ERROR if connot read register * LAN8742_STATUS_WRITE_ERROR if connot write to register * LAN8742_STATUS_RESET_TIMEOUT if cannot perform a software reset */ int32_t LAN8742_Init(lan8742_Object_t *pObj) { 8002066: b580 push {r7, lr} 8002068: b086 sub sp, #24 800206a: af00 add r7, sp, #0 800206c: 6078 str r0, [r7, #4] uint32_t tickstart = 0, regvalue = 0, addr = 0; 800206e: 2300 movs r3, #0 8002070: 60fb str r3, [r7, #12] 8002072: 2300 movs r3, #0 8002074: 60bb str r3, [r7, #8] 8002076: 2300 movs r3, #0 8002078: 617b str r3, [r7, #20] int32_t status = LAN8742_STATUS_OK; 800207a: 2300 movs r3, #0 800207c: 613b str r3, [r7, #16] if(pObj->Is_Initialized == 0) 800207e: 687b ldr r3, [r7, #4] 8002080: 685b ldr r3, [r3, #4] 8002082: 2b00 cmp r3, #0 8002084: d17c bne.n 8002180 { if(pObj->IO.Init != 0) 8002086: 687b ldr r3, [r7, #4] 8002088: 689b ldr r3, [r3, #8] 800208a: 2b00 cmp r3, #0 800208c: d002 beq.n 8002094 { /* GPIO and Clocks initialization */ pObj->IO.Init(); 800208e: 687b ldr r3, [r7, #4] 8002090: 689b ldr r3, [r3, #8] 8002092: 4798 blx r3 } /* for later check */ pObj->DevAddr = LAN8742_MAX_DEV_ADDR + 1; 8002094: 687b ldr r3, [r7, #4] 8002096: 2220 movs r2, #32 8002098: 601a str r2, [r3, #0] /* Get the device address from special mode register */ for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++) 800209a: 2300 movs r3, #0 800209c: 617b str r3, [r7, #20] 800209e: e01c b.n 80020da { if(pObj->IO.ReadReg(addr, LAN8742_SMR, ®value) < 0) 80020a0: 687b ldr r3, [r7, #4] 80020a2: 695b ldr r3, [r3, #20] 80020a4: f107 0208 add.w r2, r7, #8 80020a8: 2112 movs r1, #18 80020aa: 6978 ldr r0, [r7, #20] 80020ac: 4798 blx r3 80020ae: 4603 mov r3, r0 80020b0: 2b00 cmp r3, #0 80020b2: da03 bge.n 80020bc { status = LAN8742_STATUS_READ_ERROR; 80020b4: f06f 0304 mvn.w r3, #4 80020b8: 613b str r3, [r7, #16] /* Can't read from this device address continue with next address */ continue; 80020ba: e00b b.n 80020d4 } if((regvalue & LAN8742_SMR_PHY_ADDR) == addr) 80020bc: 68bb ldr r3, [r7, #8] 80020be: f003 031f and.w r3, r3, #31 80020c2: 697a ldr r2, [r7, #20] 80020c4: 429a cmp r2, r3 80020c6: d105 bne.n 80020d4 { pObj->DevAddr = addr; 80020c8: 687b ldr r3, [r7, #4] 80020ca: 697a ldr r2, [r7, #20] 80020cc: 601a str r2, [r3, #0] status = LAN8742_STATUS_OK; 80020ce: 2300 movs r3, #0 80020d0: 613b str r3, [r7, #16] break; 80020d2: e005 b.n 80020e0 for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++) 80020d4: 697b ldr r3, [r7, #20] 80020d6: 3301 adds r3, #1 80020d8: 617b str r3, [r7, #20] 80020da: 697b ldr r3, [r7, #20] 80020dc: 2b1f cmp r3, #31 80020de: d9df bls.n 80020a0 } } if(pObj->DevAddr > LAN8742_MAX_DEV_ADDR) 80020e0: 687b ldr r3, [r7, #4] 80020e2: 681b ldr r3, [r3, #0] 80020e4: 2b1f cmp r3, #31 80020e6: d902 bls.n 80020ee { status = LAN8742_STATUS_ADDRESS_ERROR; 80020e8: f06f 0302 mvn.w r3, #2 80020ec: 613b str r3, [r7, #16] } /* if device address is matched */ if(status == LAN8742_STATUS_OK) 80020ee: 693b ldr r3, [r7, #16] 80020f0: 2b00 cmp r3, #0 80020f2: d145 bne.n 8002180 { /* set a software reset */ if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, LAN8742_BCR_SOFT_RESET) >= 0) 80020f4: 687b ldr r3, [r7, #4] 80020f6: 691b ldr r3, [r3, #16] 80020f8: 687a ldr r2, [r7, #4] 80020fa: 6810 ldr r0, [r2, #0] 80020fc: f44f 4200 mov.w r2, #32768 ; 0x8000 8002100: 2100 movs r1, #0 8002102: 4798 blx r3 8002104: 4603 mov r3, r0 8002106: 2b00 cmp r3, #0 8002108: db37 blt.n 800217a { /* get software reset status */ if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) >= 0) 800210a: 687b ldr r3, [r7, #4] 800210c: 695b ldr r3, [r3, #20] 800210e: 687a ldr r2, [r7, #4] 8002110: 6810 ldr r0, [r2, #0] 8002112: f107 0208 add.w r2, r7, #8 8002116: 2100 movs r1, #0 8002118: 4798 blx r3 800211a: 4603 mov r3, r0 800211c: 2b00 cmp r3, #0 800211e: db28 blt.n 8002172 { tickstart = pObj->IO.GetTick(); 8002120: 687b ldr r3, [r7, #4] 8002122: 699b ldr r3, [r3, #24] 8002124: 4798 blx r3 8002126: 4603 mov r3, r0 8002128: 60fb str r3, [r7, #12] /* wait until software reset is done or timeout occured */ while(regvalue & LAN8742_BCR_SOFT_RESET) 800212a: e01c b.n 8002166 { if((pObj->IO.GetTick() - tickstart) <= LAN8742_SW_RESET_TO) 800212c: 687b ldr r3, [r7, #4] 800212e: 699b ldr r3, [r3, #24] 8002130: 4798 blx r3 8002132: 4603 mov r3, r0 8002134: 461a mov r2, r3 8002136: 68fb ldr r3, [r7, #12] 8002138: 1ad3 subs r3, r2, r3 800213a: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 800213e: d80e bhi.n 800215e { if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) < 0) 8002140: 687b ldr r3, [r7, #4] 8002142: 695b ldr r3, [r3, #20] 8002144: 687a ldr r2, [r7, #4] 8002146: 6810 ldr r0, [r2, #0] 8002148: f107 0208 add.w r2, r7, #8 800214c: 2100 movs r1, #0 800214e: 4798 blx r3 8002150: 4603 mov r3, r0 8002152: 2b00 cmp r3, #0 8002154: da07 bge.n 8002166 { status = LAN8742_STATUS_READ_ERROR; 8002156: f06f 0304 mvn.w r3, #4 800215a: 613b str r3, [r7, #16] break; 800215c: e010 b.n 8002180 } } else { status = LAN8742_STATUS_RESET_TIMEOUT; 800215e: f06f 0301 mvn.w r3, #1 8002162: 613b str r3, [r7, #16] break; 8002164: e00c b.n 8002180 while(regvalue & LAN8742_BCR_SOFT_RESET) 8002166: 68bb ldr r3, [r7, #8] 8002168: f403 4300 and.w r3, r3, #32768 ; 0x8000 800216c: 2b00 cmp r3, #0 800216e: d1dd bne.n 800212c 8002170: e006 b.n 8002180 } } } else { status = LAN8742_STATUS_READ_ERROR; 8002172: f06f 0304 mvn.w r3, #4 8002176: 613b str r3, [r7, #16] 8002178: e002 b.n 8002180 } } else { status = LAN8742_STATUS_WRITE_ERROR; 800217a: f06f 0303 mvn.w r3, #3 800217e: 613b str r3, [r7, #16] } } } if(status == LAN8742_STATUS_OK) 8002180: 693b ldr r3, [r7, #16] 8002182: 2b00 cmp r3, #0 8002184: d112 bne.n 80021ac { tickstart = pObj->IO.GetTick(); 8002186: 687b ldr r3, [r7, #4] 8002188: 699b ldr r3, [r3, #24] 800218a: 4798 blx r3 800218c: 4603 mov r3, r0 800218e: 60fb str r3, [r7, #12] /* Wait for 2s to perform initialization */ while((pObj->IO.GetTick() - tickstart) <= LAN8742_INIT_TO) 8002190: bf00 nop 8002192: 687b ldr r3, [r7, #4] 8002194: 699b ldr r3, [r3, #24] 8002196: 4798 blx r3 8002198: 4603 mov r3, r0 800219a: 461a mov r2, r3 800219c: 68fb ldr r3, [r7, #12] 800219e: 1ad3 subs r3, r2, r3 80021a0: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0 80021a4: d9f5 bls.n 8002192 { } pObj->Is_Initialized = 1; 80021a6: 687b ldr r3, [r7, #4] 80021a8: 2201 movs r2, #1 80021aa: 605a str r2, [r3, #4] } return status; 80021ac: 693b ldr r3, [r7, #16] } 80021ae: 4618 mov r0, r3 80021b0: 3718 adds r7, #24 80021b2: 46bd mov sp, r7 80021b4: bd80 pop {r7, pc} 080021b6 : * LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD * LAN8742_STATUS_READ_ERROR if connot read register * LAN8742_STATUS_WRITE_ERROR if connot write to register */ int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj) { 80021b6: b580 push {r7, lr} 80021b8: b084 sub sp, #16 80021ba: af00 add r7, sp, #0 80021bc: 6078 str r0, [r7, #4] uint32_t readval = 0; 80021be: 2300 movs r3, #0 80021c0: 60fb str r3, [r7, #12] /* Read Status register */ if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0) 80021c2: 687b ldr r3, [r7, #4] 80021c4: 695b ldr r3, [r3, #20] 80021c6: 687a ldr r2, [r7, #4] 80021c8: 6810 ldr r0, [r2, #0] 80021ca: f107 020c add.w r2, r7, #12 80021ce: 2101 movs r1, #1 80021d0: 4798 blx r3 80021d2: 4603 mov r3, r0 80021d4: 2b00 cmp r3, #0 80021d6: da02 bge.n 80021de { return LAN8742_STATUS_READ_ERROR; 80021d8: f06f 0304 mvn.w r3, #4 80021dc: e06e b.n 80022bc } /* Read Status register again */ if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0) 80021de: 687b ldr r3, [r7, #4] 80021e0: 695b ldr r3, [r3, #20] 80021e2: 687a ldr r2, [r7, #4] 80021e4: 6810 ldr r0, [r2, #0] 80021e6: f107 020c add.w r2, r7, #12 80021ea: 2101 movs r1, #1 80021ec: 4798 blx r3 80021ee: 4603 mov r3, r0 80021f0: 2b00 cmp r3, #0 80021f2: da02 bge.n 80021fa { return LAN8742_STATUS_READ_ERROR; 80021f4: f06f 0304 mvn.w r3, #4 80021f8: e060 b.n 80022bc } if((readval & LAN8742_BSR_LINK_STATUS) == 0) 80021fa: 68fb ldr r3, [r7, #12] 80021fc: f003 0304 and.w r3, r3, #4 8002200: 2b00 cmp r3, #0 8002202: d101 bne.n 8002208 { /* Return Link Down status */ return LAN8742_STATUS_LINK_DOWN; 8002204: 2301 movs r3, #1 8002206: e059 b.n 80022bc } /* Check Auto negotiaition */ if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) < 0) 8002208: 687b ldr r3, [r7, #4] 800220a: 695b ldr r3, [r3, #20] 800220c: 687a ldr r2, [r7, #4] 800220e: 6810 ldr r0, [r2, #0] 8002210: f107 020c add.w r2, r7, #12 8002214: 2100 movs r1, #0 8002216: 4798 blx r3 8002218: 4603 mov r3, r0 800221a: 2b00 cmp r3, #0 800221c: da02 bge.n 8002224 { return LAN8742_STATUS_READ_ERROR; 800221e: f06f 0304 mvn.w r3, #4 8002222: e04b b.n 80022bc } if((readval & LAN8742_BCR_AUTONEGO_EN) != LAN8742_BCR_AUTONEGO_EN) 8002224: 68fb ldr r3, [r7, #12] 8002226: f403 5380 and.w r3, r3, #4096 ; 0x1000 800222a: 2b00 cmp r3, #0 800222c: d11b bne.n 8002266 { if(((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) && ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)) 800222e: 68fb ldr r3, [r7, #12] 8002230: f403 5300 and.w r3, r3, #8192 ; 0x2000 8002234: 2b00 cmp r3, #0 8002236: d006 beq.n 8002246 8002238: 68fb ldr r3, [r7, #12] 800223a: f403 7380 and.w r3, r3, #256 ; 0x100 800223e: 2b00 cmp r3, #0 8002240: d001 beq.n 8002246 { return LAN8742_STATUS_100MBITS_FULLDUPLEX; 8002242: 2302 movs r3, #2 8002244: e03a b.n 80022bc } else if ((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) 8002246: 68fb ldr r3, [r7, #12] 8002248: f403 5300 and.w r3, r3, #8192 ; 0x2000 800224c: 2b00 cmp r3, #0 800224e: d001 beq.n 8002254 { return LAN8742_STATUS_100MBITS_HALFDUPLEX; 8002250: 2303 movs r3, #3 8002252: e033 b.n 80022bc } else if ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE) 8002254: 68fb ldr r3, [r7, #12] 8002256: f403 7380 and.w r3, r3, #256 ; 0x100 800225a: 2b00 cmp r3, #0 800225c: d001 beq.n 8002262 { return LAN8742_STATUS_10MBITS_FULLDUPLEX; 800225e: 2304 movs r3, #4 8002260: e02c b.n 80022bc } else { return LAN8742_STATUS_10MBITS_HALFDUPLEX; 8002262: 2305 movs r3, #5 8002264: e02a b.n 80022bc } } else /* Auto Nego enabled */ { if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_PHYSCSR, &readval) < 0) 8002266: 687b ldr r3, [r7, #4] 8002268: 695b ldr r3, [r3, #20] 800226a: 687a ldr r2, [r7, #4] 800226c: 6810 ldr r0, [r2, #0] 800226e: f107 020c add.w r2, r7, #12 8002272: 211f movs r1, #31 8002274: 4798 blx r3 8002276: 4603 mov r3, r0 8002278: 2b00 cmp r3, #0 800227a: da02 bge.n 8002282 { return LAN8742_STATUS_READ_ERROR; 800227c: f06f 0304 mvn.w r3, #4 8002280: e01c b.n 80022bc } /* Check if auto nego not done */ if((readval & LAN8742_PHYSCSR_AUTONEGO_DONE) == 0) 8002282: 68fb ldr r3, [r7, #12] 8002284: f403 5380 and.w r3, r3, #4096 ; 0x1000 8002288: 2b00 cmp r3, #0 800228a: d101 bne.n 8002290 { return LAN8742_STATUS_AUTONEGO_NOTDONE; 800228c: 2306 movs r3, #6 800228e: e015 b.n 80022bc } if((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_FD) 8002290: 68fb ldr r3, [r7, #12] 8002292: f003 031c and.w r3, r3, #28 8002296: 2b18 cmp r3, #24 8002298: d101 bne.n 800229e { return LAN8742_STATUS_100MBITS_FULLDUPLEX; 800229a: 2302 movs r3, #2 800229c: e00e b.n 80022bc } else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_HD) 800229e: 68fb ldr r3, [r7, #12] 80022a0: f003 031c and.w r3, r3, #28 80022a4: 2b08 cmp r3, #8 80022a6: d101 bne.n 80022ac { return LAN8742_STATUS_100MBITS_HALFDUPLEX; 80022a8: 2303 movs r3, #3 80022aa: e007 b.n 80022bc } else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_10BT_FD) 80022ac: 68fb ldr r3, [r7, #12] 80022ae: f003 031c and.w r3, r3, #28 80022b2: 2b14 cmp r3, #20 80022b4: d101 bne.n 80022ba { return LAN8742_STATUS_10MBITS_FULLDUPLEX; 80022b6: 2304 movs r3, #4 80022b8: e000 b.n 80022bc } else { return LAN8742_STATUS_10MBITS_HALFDUPLEX; 80022ba: 2305 movs r3, #5 } } } 80022bc: 4618 mov r0, r3 80022be: 3710 adds r7, #16 80022c0: 46bd mov sp, r7 80022c2: bd80 pop {r7, pc} 080022c4 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80022c4: b580 push {r7, lr} 80022c6: b082 sub sp, #8 80022c8: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80022ca: 2003 movs r0, #3 80022cc: f000 f93b bl 8002546 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 80022d0: f005 fc9c bl 8007c0c 80022d4: 4602 mov r2, r0 80022d6: 4b15 ldr r3, [pc, #84] ; (800232c ) 80022d8: 699b ldr r3, [r3, #24] 80022da: 0a1b lsrs r3, r3, #8 80022dc: f003 030f and.w r3, r3, #15 80022e0: 4913 ldr r1, [pc, #76] ; (8002330 ) 80022e2: 5ccb ldrb r3, [r1, r3] 80022e4: f003 031f and.w r3, r3, #31 80022e8: fa22 f303 lsr.w r3, r2, r3 80022ec: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 80022ee: 4b0f ldr r3, [pc, #60] ; (800232c ) 80022f0: 699b ldr r3, [r3, #24] 80022f2: f003 030f and.w r3, r3, #15 80022f6: 4a0e ldr r2, [pc, #56] ; (8002330 ) 80022f8: 5cd3 ldrb r3, [r2, r3] 80022fa: f003 031f and.w r3, r3, #31 80022fe: 687a ldr r2, [r7, #4] 8002300: fa22 f303 lsr.w r3, r2, r3 8002304: 4a0b ldr r2, [pc, #44] ; (8002334 ) 8002306: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8002308: 4a0b ldr r2, [pc, #44] ; (8002338 ) 800230a: 687b ldr r3, [r7, #4] 800230c: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 800230e: 200f movs r0, #15 8002310: f7ff fc46 bl 8001ba0 8002314: 4603 mov r3, r0 8002316: 2b00 cmp r3, #0 8002318: d001 beq.n 800231e { return HAL_ERROR; 800231a: 2301 movs r3, #1 800231c: e002 b.n 8002324 } /* Init the low level hardware */ HAL_MspInit(); 800231e: f7ff f8ef bl 8001500 /* Return function status */ return HAL_OK; 8002322: 2300 movs r3, #0 } 8002324: 4618 mov r0, r3 8002326: 3708 adds r7, #8 8002328: 46bd mov sp, r7 800232a: bd80 pop {r7, pc} 800232c: 58024400 .word 0x58024400 8002330: 08026b40 .word 0x08026b40 8002334: 24000018 .word 0x24000018 8002338: 24000014 .word 0x24000014 0800233c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800233c: b480 push {r7} 800233e: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8002340: 4b06 ldr r3, [pc, #24] ; (800235c ) 8002342: 781b ldrb r3, [r3, #0] 8002344: 461a mov r2, r3 8002346: 4b06 ldr r3, [pc, #24] ; (8002360 ) 8002348: 681b ldr r3, [r3, #0] 800234a: 4413 add r3, r2 800234c: 4a04 ldr r2, [pc, #16] ; (8002360 ) 800234e: 6013 str r3, [r2, #0] } 8002350: bf00 nop 8002352: 46bd mov sp, r7 8002354: f85d 7b04 ldr.w r7, [sp], #4 8002358: 4770 bx lr 800235a: bf00 nop 800235c: 24000020 .word 0x24000020 8002360: 240073d4 .word 0x240073d4 08002364 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8002364: b480 push {r7} 8002366: af00 add r7, sp, #0 return uwTick; 8002368: 4b03 ldr r3, [pc, #12] ; (8002378 ) 800236a: 681b ldr r3, [r3, #0] } 800236c: 4618 mov r0, r3 800236e: 46bd mov sp, r7 8002370: f85d 7b04 ldr.w r7, [sp], #4 8002374: 4770 bx lr 8002376: bf00 nop 8002378: 240073d4 .word 0x240073d4 0800237c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800237c: b580 push {r7, lr} 800237e: b084 sub sp, #16 8002380: af00 add r7, sp, #0 8002382: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8002384: f7ff ffee bl 8002364 8002388: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800238a: 687b ldr r3, [r7, #4] 800238c: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800238e: 68fb ldr r3, [r7, #12] 8002390: f1b3 3fff cmp.w r3, #4294967295 8002394: d005 beq.n 80023a2 { wait += (uint32_t)(uwTickFreq); 8002396: 4b0a ldr r3, [pc, #40] ; (80023c0 ) 8002398: 781b ldrb r3, [r3, #0] 800239a: 461a mov r2, r3 800239c: 68fb ldr r3, [r7, #12] 800239e: 4413 add r3, r2 80023a0: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80023a2: bf00 nop 80023a4: f7ff ffde bl 8002364 80023a8: 4602 mov r2, r0 80023aa: 68bb ldr r3, [r7, #8] 80023ac: 1ad3 subs r3, r2, r3 80023ae: 68fa ldr r2, [r7, #12] 80023b0: 429a cmp r2, r3 80023b2: d8f7 bhi.n 80023a4 { } } 80023b4: bf00 nop 80023b6: bf00 nop 80023b8: 3710 adds r7, #16 80023ba: 46bd mov sp, r7 80023bc: bd80 pop {r7, pc} 80023be: bf00 nop 80023c0: 24000020 .word 0x24000020 080023c4 : * @arg SYSCFG_ETH_MII : Select the Media Independent Interface * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface * @retval None */ void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface) { 80023c4: b480 push {r7} 80023c6: b083 sub sp, #12 80023c8: af00 add r7, sp, #0 80023ca: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface)); MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface)); 80023cc: 4b06 ldr r3, [pc, #24] ; (80023e8 ) 80023ce: 685b ldr r3, [r3, #4] 80023d0: f423 0260 bic.w r2, r3, #14680064 ; 0xe00000 80023d4: 4904 ldr r1, [pc, #16] ; (80023e8 ) 80023d6: 687b ldr r3, [r7, #4] 80023d8: 4313 orrs r3, r2 80023da: 604b str r3, [r1, #4] } 80023dc: bf00 nop 80023de: 370c adds r7, #12 80023e0: 46bd mov sp, r7 80023e2: f85d 7b04 ldr.w r7, [sp], #4 80023e6: 4770 bx lr 80023e8: 58000400 .word 0x58000400 080023ec <__NVIC_SetPriorityGrouping>: { 80023ec: b480 push {r7} 80023ee: b085 sub sp, #20 80023f0: af00 add r7, sp, #0 80023f2: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80023f4: 687b ldr r3, [r7, #4] 80023f6: f003 0307 and.w r3, r3, #7 80023fa: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80023fc: 4b0b ldr r3, [pc, #44] ; (800242c <__NVIC_SetPriorityGrouping+0x40>) 80023fe: 68db ldr r3, [r3, #12] 8002400: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8002402: 68ba ldr r2, [r7, #8] 8002404: f64f 03ff movw r3, #63743 ; 0xf8ff 8002408: 4013 ands r3, r2 800240a: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800240c: 68fb ldr r3, [r7, #12] 800240e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8002410: 68bb ldr r3, [r7, #8] 8002412: 431a orrs r2, r3 reg_value = (reg_value | 8002414: 4b06 ldr r3, [pc, #24] ; (8002430 <__NVIC_SetPriorityGrouping+0x44>) 8002416: 4313 orrs r3, r2 8002418: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800241a: 4a04 ldr r2, [pc, #16] ; (800242c <__NVIC_SetPriorityGrouping+0x40>) 800241c: 68bb ldr r3, [r7, #8] 800241e: 60d3 str r3, [r2, #12] } 8002420: bf00 nop 8002422: 3714 adds r7, #20 8002424: 46bd mov sp, r7 8002426: f85d 7b04 ldr.w r7, [sp], #4 800242a: 4770 bx lr 800242c: e000ed00 .word 0xe000ed00 8002430: 05fa0000 .word 0x05fa0000 08002434 <__NVIC_GetPriorityGrouping>: { 8002434: b480 push {r7} 8002436: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8002438: 4b04 ldr r3, [pc, #16] ; (800244c <__NVIC_GetPriorityGrouping+0x18>) 800243a: 68db ldr r3, [r3, #12] 800243c: 0a1b lsrs r3, r3, #8 800243e: f003 0307 and.w r3, r3, #7 } 8002442: 4618 mov r0, r3 8002444: 46bd mov sp, r7 8002446: f85d 7b04 ldr.w r7, [sp], #4 800244a: 4770 bx lr 800244c: e000ed00 .word 0xe000ed00 08002450 <__NVIC_EnableIRQ>: { 8002450: b480 push {r7} 8002452: b083 sub sp, #12 8002454: af00 add r7, sp, #0 8002456: 4603 mov r3, r0 8002458: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 800245a: f9b7 3006 ldrsh.w r3, [r7, #6] 800245e: 2b00 cmp r3, #0 8002460: db0b blt.n 800247a <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8002462: 88fb ldrh r3, [r7, #6] 8002464: f003 021f and.w r2, r3, #31 8002468: 4907 ldr r1, [pc, #28] ; (8002488 <__NVIC_EnableIRQ+0x38>) 800246a: f9b7 3006 ldrsh.w r3, [r7, #6] 800246e: 095b lsrs r3, r3, #5 8002470: 2001 movs r0, #1 8002472: fa00 f202 lsl.w r2, r0, r2 8002476: f841 2023 str.w r2, [r1, r3, lsl #2] } 800247a: bf00 nop 800247c: 370c adds r7, #12 800247e: 46bd mov sp, r7 8002480: f85d 7b04 ldr.w r7, [sp], #4 8002484: 4770 bx lr 8002486: bf00 nop 8002488: e000e100 .word 0xe000e100 0800248c <__NVIC_SetPriority>: { 800248c: b480 push {r7} 800248e: b083 sub sp, #12 8002490: af00 add r7, sp, #0 8002492: 4603 mov r3, r0 8002494: 6039 str r1, [r7, #0] 8002496: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8002498: f9b7 3006 ldrsh.w r3, [r7, #6] 800249c: 2b00 cmp r3, #0 800249e: db0a blt.n 80024b6 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80024a0: 683b ldr r3, [r7, #0] 80024a2: b2da uxtb r2, r3 80024a4: 490c ldr r1, [pc, #48] ; (80024d8 <__NVIC_SetPriority+0x4c>) 80024a6: f9b7 3006 ldrsh.w r3, [r7, #6] 80024aa: 0112 lsls r2, r2, #4 80024ac: b2d2 uxtb r2, r2 80024ae: 440b add r3, r1 80024b0: f883 2300 strb.w r2, [r3, #768] ; 0x300 } 80024b4: e00a b.n 80024cc <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80024b6: 683b ldr r3, [r7, #0] 80024b8: b2da uxtb r2, r3 80024ba: 4908 ldr r1, [pc, #32] ; (80024dc <__NVIC_SetPriority+0x50>) 80024bc: 88fb ldrh r3, [r7, #6] 80024be: f003 030f and.w r3, r3, #15 80024c2: 3b04 subs r3, #4 80024c4: 0112 lsls r2, r2, #4 80024c6: b2d2 uxtb r2, r2 80024c8: 440b add r3, r1 80024ca: 761a strb r2, [r3, #24] } 80024cc: bf00 nop 80024ce: 370c adds r7, #12 80024d0: 46bd mov sp, r7 80024d2: f85d 7b04 ldr.w r7, [sp], #4 80024d6: 4770 bx lr 80024d8: e000e100 .word 0xe000e100 80024dc: e000ed00 .word 0xe000ed00 080024e0 : { 80024e0: b480 push {r7} 80024e2: b089 sub sp, #36 ; 0x24 80024e4: af00 add r7, sp, #0 80024e6: 60f8 str r0, [r7, #12] 80024e8: 60b9 str r1, [r7, #8] 80024ea: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80024ec: 68fb ldr r3, [r7, #12] 80024ee: f003 0307 and.w r3, r3, #7 80024f2: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80024f4: 69fb ldr r3, [r7, #28] 80024f6: f1c3 0307 rsb r3, r3, #7 80024fa: 2b04 cmp r3, #4 80024fc: bf28 it cs 80024fe: 2304 movcs r3, #4 8002500: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8002502: 69fb ldr r3, [r7, #28] 8002504: 3304 adds r3, #4 8002506: 2b06 cmp r3, #6 8002508: d902 bls.n 8002510 800250a: 69fb ldr r3, [r7, #28] 800250c: 3b03 subs r3, #3 800250e: e000 b.n 8002512 8002510: 2300 movs r3, #0 8002512: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002514: f04f 32ff mov.w r2, #4294967295 8002518: 69bb ldr r3, [r7, #24] 800251a: fa02 f303 lsl.w r3, r2, r3 800251e: 43da mvns r2, r3 8002520: 68bb ldr r3, [r7, #8] 8002522: 401a ands r2, r3 8002524: 697b ldr r3, [r7, #20] 8002526: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8002528: f04f 31ff mov.w r1, #4294967295 800252c: 697b ldr r3, [r7, #20] 800252e: fa01 f303 lsl.w r3, r1, r3 8002532: 43d9 mvns r1, r3 8002534: 687b ldr r3, [r7, #4] 8002536: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002538: 4313 orrs r3, r2 } 800253a: 4618 mov r0, r3 800253c: 3724 adds r7, #36 ; 0x24 800253e: 46bd mov sp, r7 8002540: f85d 7b04 ldr.w r7, [sp], #4 8002544: 4770 bx lr 08002546 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002546: b580 push {r7, lr} 8002548: b082 sub sp, #8 800254a: af00 add r7, sp, #0 800254c: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800254e: 6878 ldr r0, [r7, #4] 8002550: f7ff ff4c bl 80023ec <__NVIC_SetPriorityGrouping> } 8002554: bf00 nop 8002556: 3708 adds r7, #8 8002558: 46bd mov sp, r7 800255a: bd80 pop {r7, pc} 0800255c : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800255c: b580 push {r7, lr} 800255e: b086 sub sp, #24 8002560: af00 add r7, sp, #0 8002562: 4603 mov r3, r0 8002564: 60b9 str r1, [r7, #8] 8002566: 607a str r2, [r7, #4] 8002568: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800256a: f7ff ff63 bl 8002434 <__NVIC_GetPriorityGrouping> 800256e: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8002570: 687a ldr r2, [r7, #4] 8002572: 68b9 ldr r1, [r7, #8] 8002574: 6978 ldr r0, [r7, #20] 8002576: f7ff ffb3 bl 80024e0 800257a: 4602 mov r2, r0 800257c: f9b7 300e ldrsh.w r3, [r7, #14] 8002580: 4611 mov r1, r2 8002582: 4618 mov r0, r3 8002584: f7ff ff82 bl 800248c <__NVIC_SetPriority> } 8002588: bf00 nop 800258a: 3718 adds r7, #24 800258c: 46bd mov sp, r7 800258e: bd80 pop {r7, pc} 08002590 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002590: b580 push {r7, lr} 8002592: b082 sub sp, #8 8002594: af00 add r7, sp, #0 8002596: 4603 mov r3, r0 8002598: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800259a: f9b7 3006 ldrsh.w r3, [r7, #6] 800259e: 4618 mov r0, r3 80025a0: f7ff ff56 bl 8002450 <__NVIC_EnableIRQ> } 80025a4: bf00 nop 80025a6: 3708 adds r7, #8 80025a8: 46bd mov sp, r7 80025aa: bd80 pop {r7, pc} 080025ac : /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { 80025ac: b480 push {r7} 80025ae: af00 add r7, sp, #0 \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); 80025b0: f3bf 8f5f dmb sy } 80025b4: bf00 nop /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 80025b6: 4b07 ldr r3, [pc, #28] ; (80025d4 ) 80025b8: 6a5b ldr r3, [r3, #36] ; 0x24 80025ba: 4a06 ldr r2, [pc, #24] ; (80025d4 ) 80025bc: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80025c0: 6253 str r3, [r2, #36] ; 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 80025c2: 4b05 ldr r3, [pc, #20] ; (80025d8 ) 80025c4: 2200 movs r2, #0 80025c6: 605a str r2, [r3, #4] } 80025c8: bf00 nop 80025ca: 46bd mov sp, r7 80025cc: f85d 7b04 ldr.w r7, [sp], #4 80025d0: 4770 bx lr 80025d2: bf00 nop 80025d4: e000ed00 .word 0xe000ed00 80025d8: e000ed90 .word 0xe000ed90 080025dc : * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { 80025dc: b480 push {r7} 80025de: b083 sub sp, #12 80025e0: af00 add r7, sp, #0 80025e2: 6078 str r0, [r7, #4] /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 80025e4: 4a0b ldr r2, [pc, #44] ; (8002614 ) 80025e6: 687b ldr r3, [r7, #4] 80025e8: f043 0301 orr.w r3, r3, #1 80025ec: 6053 str r3, [r2, #4] /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 80025ee: 4b0a ldr r3, [pc, #40] ; (8002618 ) 80025f0: 6a5b ldr r3, [r3, #36] ; 0x24 80025f2: 4a09 ldr r2, [pc, #36] ; (8002618 ) 80025f4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80025f8: 6253 str r3, [r2, #36] ; 0x24 __ASM volatile ("dsb 0xF":::"memory"); 80025fa: f3bf 8f4f dsb sy } 80025fe: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8002600: f3bf 8f6f isb sy } 8002604: bf00 nop /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 8002606: bf00 nop 8002608: 370c adds r7, #12 800260a: 46bd mov sp, r7 800260c: f85d 7b04 ldr.w r7, [sp], #4 8002610: 4770 bx lr 8002612: bf00 nop 8002614: e000ed90 .word 0xe000ed90 8002618: e000ed00 .word 0xe000ed00 0800261c : * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { 800261c: b480 push {r7} 800261e: b083 sub sp, #12 8002620: af00 add r7, sp, #0 8002622: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 8002624: 687b ldr r3, [r7, #4] 8002626: 785a ldrb r2, [r3, #1] 8002628: 4b1d ldr r3, [pc, #116] ; (80026a0 ) 800262a: 609a str r2, [r3, #8] if ((MPU_Init->Enable) != 0UL) 800262c: 687b ldr r3, [r7, #4] 800262e: 781b ldrb r3, [r3, #0] 8002630: 2b00 cmp r3, #0 8002632: d029 beq.n 8002688 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); MPU->RBAR = MPU_Init->BaseAddress; 8002634: 4a1a ldr r2, [pc, #104] ; (80026a0 ) 8002636: 687b ldr r3, [r7, #4] 8002638: 685b ldr r3, [r3, #4] 800263a: 60d3 str r3, [r2, #12] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 800263c: 687b ldr r3, [r7, #4] 800263e: 7b1b ldrb r3, [r3, #12] 8002640: 071a lsls r2, r3, #28 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8002642: 687b ldr r3, [r7, #4] 8002644: 7adb ldrb r3, [r3, #11] 8002646: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8002648: 431a orrs r2, r3 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 800264a: 687b ldr r3, [r7, #4] 800264c: 7a9b ldrb r3, [r3, #10] 800264e: 04db lsls r3, r3, #19 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8002650: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8002652: 687b ldr r3, [r7, #4] 8002654: 7b5b ldrb r3, [r3, #13] 8002656: 049b lsls r3, r3, #18 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8002658: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 800265a: 687b ldr r3, [r7, #4] 800265c: 7b9b ldrb r3, [r3, #14] 800265e: 045b lsls r3, r3, #17 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8002660: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8002662: 687b ldr r3, [r7, #4] 8002664: 7bdb ldrb r3, [r3, #15] 8002666: 041b lsls r3, r3, #16 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8002668: 431a orrs r2, r3 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 800266a: 687b ldr r3, [r7, #4] 800266c: 7a5b ldrb r3, [r3, #9] 800266e: 021b lsls r3, r3, #8 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8002670: 431a orrs r2, r3 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8002672: 687b ldr r3, [r7, #4] 8002674: 7a1b ldrb r3, [r3, #8] 8002676: 005b lsls r3, r3, #1 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8002678: 4313 orrs r3, r2 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 800267a: 687a ldr r2, [r7, #4] 800267c: 7812 ldrb r2, [r2, #0] 800267e: 4611 mov r1, r2 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8002680: 4a07 ldr r2, [pc, #28] ; (80026a0 ) ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8002682: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8002684: 6113 str r3, [r2, #16] else { MPU->RBAR = 0x00; MPU->RASR = 0x00; } } 8002686: e005 b.n 8002694 MPU->RBAR = 0x00; 8002688: 4b05 ldr r3, [pc, #20] ; (80026a0 ) 800268a: 2200 movs r2, #0 800268c: 60da str r2, [r3, #12] MPU->RASR = 0x00; 800268e: 4b04 ldr r3, [pc, #16] ; (80026a0 ) 8002690: 2200 movs r2, #0 8002692: 611a str r2, [r3, #16] } 8002694: bf00 nop 8002696: 370c adds r7, #12 8002698: 46bd mov sp, r7 800269a: f85d 7b04 ldr.w r7, [sp], #4 800269e: 4770 bx lr 80026a0: e000ed90 .word 0xe000ed90 080026a4 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 80026a4: b580 push {r7, lr} 80026a6: b086 sub sp, #24 80026a8: af00 add r7, sp, #0 80026aa: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 80026ac: f7ff fe5a bl 8002364 80026b0: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 80026b2: 687b ldr r3, [r7, #4] 80026b4: 2b00 cmp r3, #0 80026b6: d101 bne.n 80026bc { return HAL_ERROR; 80026b8: 2301 movs r3, #1 80026ba: e312 b.n 8002ce2 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80026bc: 687b ldr r3, [r7, #4] 80026be: 681b ldr r3, [r3, #0] 80026c0: 4a66 ldr r2, [pc, #408] ; (800285c ) 80026c2: 4293 cmp r3, r2 80026c4: d04a beq.n 800275c 80026c6: 687b ldr r3, [r7, #4] 80026c8: 681b ldr r3, [r3, #0] 80026ca: 4a65 ldr r2, [pc, #404] ; (8002860 ) 80026cc: 4293 cmp r3, r2 80026ce: d045 beq.n 800275c 80026d0: 687b ldr r3, [r7, #4] 80026d2: 681b ldr r3, [r3, #0] 80026d4: 4a63 ldr r2, [pc, #396] ; (8002864 ) 80026d6: 4293 cmp r3, r2 80026d8: d040 beq.n 800275c 80026da: 687b ldr r3, [r7, #4] 80026dc: 681b ldr r3, [r3, #0] 80026de: 4a62 ldr r2, [pc, #392] ; (8002868 ) 80026e0: 4293 cmp r3, r2 80026e2: d03b beq.n 800275c 80026e4: 687b ldr r3, [r7, #4] 80026e6: 681b ldr r3, [r3, #0] 80026e8: 4a60 ldr r2, [pc, #384] ; (800286c ) 80026ea: 4293 cmp r3, r2 80026ec: d036 beq.n 800275c 80026ee: 687b ldr r3, [r7, #4] 80026f0: 681b ldr r3, [r3, #0] 80026f2: 4a5f ldr r2, [pc, #380] ; (8002870 ) 80026f4: 4293 cmp r3, r2 80026f6: d031 beq.n 800275c 80026f8: 687b ldr r3, [r7, #4] 80026fa: 681b ldr r3, [r3, #0] 80026fc: 4a5d ldr r2, [pc, #372] ; (8002874 ) 80026fe: 4293 cmp r3, r2 8002700: d02c beq.n 800275c 8002702: 687b ldr r3, [r7, #4] 8002704: 681b ldr r3, [r3, #0] 8002706: 4a5c ldr r2, [pc, #368] ; (8002878 ) 8002708: 4293 cmp r3, r2 800270a: d027 beq.n 800275c 800270c: 687b ldr r3, [r7, #4] 800270e: 681b ldr r3, [r3, #0] 8002710: 4a5a ldr r2, [pc, #360] ; (800287c ) 8002712: 4293 cmp r3, r2 8002714: d022 beq.n 800275c 8002716: 687b ldr r3, [r7, #4] 8002718: 681b ldr r3, [r3, #0] 800271a: 4a59 ldr r2, [pc, #356] ; (8002880 ) 800271c: 4293 cmp r3, r2 800271e: d01d beq.n 800275c 8002720: 687b ldr r3, [r7, #4] 8002722: 681b ldr r3, [r3, #0] 8002724: 4a57 ldr r2, [pc, #348] ; (8002884 ) 8002726: 4293 cmp r3, r2 8002728: d018 beq.n 800275c 800272a: 687b ldr r3, [r7, #4] 800272c: 681b ldr r3, [r3, #0] 800272e: 4a56 ldr r2, [pc, #344] ; (8002888 ) 8002730: 4293 cmp r3, r2 8002732: d013 beq.n 800275c 8002734: 687b ldr r3, [r7, #4] 8002736: 681b ldr r3, [r3, #0] 8002738: 4a54 ldr r2, [pc, #336] ; (800288c ) 800273a: 4293 cmp r3, r2 800273c: d00e beq.n 800275c 800273e: 687b ldr r3, [r7, #4] 8002740: 681b ldr r3, [r3, #0] 8002742: 4a53 ldr r2, [pc, #332] ; (8002890 ) 8002744: 4293 cmp r3, r2 8002746: d009 beq.n 800275c 8002748: 687b ldr r3, [r7, #4] 800274a: 681b ldr r3, [r3, #0] 800274c: 4a51 ldr r2, [pc, #324] ; (8002894 ) 800274e: 4293 cmp r3, r2 8002750: d004 beq.n 800275c 8002752: 687b ldr r3, [r7, #4] 8002754: 681b ldr r3, [r3, #0] 8002756: 4a50 ldr r2, [pc, #320] ; (8002898 ) 8002758: 4293 cmp r3, r2 800275a: d101 bne.n 8002760 800275c: 2301 movs r3, #1 800275e: e000 b.n 8002762 8002760: 2300 movs r3, #0 8002762: 2b00 cmp r3, #0 8002764: f000 813c beq.w 80029e0 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002768: 687b ldr r3, [r7, #4] 800276a: 2202 movs r2, #2 800276c: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8002770: 687b ldr r3, [r7, #4] 8002772: 2200 movs r2, #0 8002774: f883 2034 strb.w r2, [r3, #52] ; 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8002778: 687b ldr r3, [r7, #4] 800277a: 681b ldr r3, [r3, #0] 800277c: 4a37 ldr r2, [pc, #220] ; (800285c ) 800277e: 4293 cmp r3, r2 8002780: d04a beq.n 8002818 8002782: 687b ldr r3, [r7, #4] 8002784: 681b ldr r3, [r3, #0] 8002786: 4a36 ldr r2, [pc, #216] ; (8002860 ) 8002788: 4293 cmp r3, r2 800278a: d045 beq.n 8002818 800278c: 687b ldr r3, [r7, #4] 800278e: 681b ldr r3, [r3, #0] 8002790: 4a34 ldr r2, [pc, #208] ; (8002864 ) 8002792: 4293 cmp r3, r2 8002794: d040 beq.n 8002818 8002796: 687b ldr r3, [r7, #4] 8002798: 681b ldr r3, [r3, #0] 800279a: 4a33 ldr r2, [pc, #204] ; (8002868 ) 800279c: 4293 cmp r3, r2 800279e: d03b beq.n 8002818 80027a0: 687b ldr r3, [r7, #4] 80027a2: 681b ldr r3, [r3, #0] 80027a4: 4a31 ldr r2, [pc, #196] ; (800286c ) 80027a6: 4293 cmp r3, r2 80027a8: d036 beq.n 8002818 80027aa: 687b ldr r3, [r7, #4] 80027ac: 681b ldr r3, [r3, #0] 80027ae: 4a30 ldr r2, [pc, #192] ; (8002870 ) 80027b0: 4293 cmp r3, r2 80027b2: d031 beq.n 8002818 80027b4: 687b ldr r3, [r7, #4] 80027b6: 681b ldr r3, [r3, #0] 80027b8: 4a2e ldr r2, [pc, #184] ; (8002874 ) 80027ba: 4293 cmp r3, r2 80027bc: d02c beq.n 8002818 80027be: 687b ldr r3, [r7, #4] 80027c0: 681b ldr r3, [r3, #0] 80027c2: 4a2d ldr r2, [pc, #180] ; (8002878 ) 80027c4: 4293 cmp r3, r2 80027c6: d027 beq.n 8002818 80027c8: 687b ldr r3, [r7, #4] 80027ca: 681b ldr r3, [r3, #0] 80027cc: 4a2b ldr r2, [pc, #172] ; (800287c ) 80027ce: 4293 cmp r3, r2 80027d0: d022 beq.n 8002818 80027d2: 687b ldr r3, [r7, #4] 80027d4: 681b ldr r3, [r3, #0] 80027d6: 4a2a ldr r2, [pc, #168] ; (8002880 ) 80027d8: 4293 cmp r3, r2 80027da: d01d beq.n 8002818 80027dc: 687b ldr r3, [r7, #4] 80027de: 681b ldr r3, [r3, #0] 80027e0: 4a28 ldr r2, [pc, #160] ; (8002884 ) 80027e2: 4293 cmp r3, r2 80027e4: d018 beq.n 8002818 80027e6: 687b ldr r3, [r7, #4] 80027e8: 681b ldr r3, [r3, #0] 80027ea: 4a27 ldr r2, [pc, #156] ; (8002888 ) 80027ec: 4293 cmp r3, r2 80027ee: d013 beq.n 8002818 80027f0: 687b ldr r3, [r7, #4] 80027f2: 681b ldr r3, [r3, #0] 80027f4: 4a25 ldr r2, [pc, #148] ; (800288c ) 80027f6: 4293 cmp r3, r2 80027f8: d00e beq.n 8002818 80027fa: 687b ldr r3, [r7, #4] 80027fc: 681b ldr r3, [r3, #0] 80027fe: 4a24 ldr r2, [pc, #144] ; (8002890 ) 8002800: 4293 cmp r3, r2 8002802: d009 beq.n 8002818 8002804: 687b ldr r3, [r7, #4] 8002806: 681b ldr r3, [r3, #0] 8002808: 4a22 ldr r2, [pc, #136] ; (8002894 ) 800280a: 4293 cmp r3, r2 800280c: d004 beq.n 8002818 800280e: 687b ldr r3, [r7, #4] 8002810: 681b ldr r3, [r3, #0] 8002812: 4a21 ldr r2, [pc, #132] ; (8002898 ) 8002814: 4293 cmp r3, r2 8002816: d108 bne.n 800282a 8002818: 687b ldr r3, [r7, #4] 800281a: 681b ldr r3, [r3, #0] 800281c: 681a ldr r2, [r3, #0] 800281e: 687b ldr r3, [r7, #4] 8002820: 681b ldr r3, [r3, #0] 8002822: f022 0201 bic.w r2, r2, #1 8002826: 601a str r2, [r3, #0] 8002828: e007 b.n 800283a 800282a: 687b ldr r3, [r7, #4] 800282c: 681b ldr r3, [r3, #0] 800282e: 681a ldr r2, [r3, #0] 8002830: 687b ldr r3, [r7, #4] 8002832: 681b ldr r3, [r3, #0] 8002834: f022 0201 bic.w r2, r2, #1 8002838: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800283a: e02f b.n 800289c { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 800283c: f7ff fd92 bl 8002364 8002840: 4602 mov r2, r0 8002842: 693b ldr r3, [r7, #16] 8002844: 1ad3 subs r3, r2, r3 8002846: 2b05 cmp r3, #5 8002848: d928 bls.n 800289c { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800284a: 687b ldr r3, [r7, #4] 800284c: 2220 movs r2, #32 800284e: 655a str r2, [r3, #84] ; 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8002850: 687b ldr r3, [r7, #4] 8002852: 2203 movs r2, #3 8002854: f883 2035 strb.w r2, [r3, #53] ; 0x35 return HAL_ERROR; 8002858: 2301 movs r3, #1 800285a: e242 b.n 8002ce2 800285c: 40020010 .word 0x40020010 8002860: 40020028 .word 0x40020028 8002864: 40020040 .word 0x40020040 8002868: 40020058 .word 0x40020058 800286c: 40020070 .word 0x40020070 8002870: 40020088 .word 0x40020088 8002874: 400200a0 .word 0x400200a0 8002878: 400200b8 .word 0x400200b8 800287c: 40020410 .word 0x40020410 8002880: 40020428 .word 0x40020428 8002884: 40020440 .word 0x40020440 8002888: 40020458 .word 0x40020458 800288c: 40020470 .word 0x40020470 8002890: 40020488 .word 0x40020488 8002894: 400204a0 .word 0x400204a0 8002898: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800289c: 687b ldr r3, [r7, #4] 800289e: 681b ldr r3, [r3, #0] 80028a0: 681b ldr r3, [r3, #0] 80028a2: f003 0301 and.w r3, r3, #1 80028a6: 2b00 cmp r3, #0 80028a8: d1c8 bne.n 800283c } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 80028aa: 687b ldr r3, [r7, #4] 80028ac: 681b ldr r3, [r3, #0] 80028ae: 681b ldr r3, [r3, #0] 80028b0: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 80028b2: 697a ldr r2, [r7, #20] 80028b4: 4b83 ldr r3, [pc, #524] ; (8002ac4 ) 80028b6: 4013 ands r3, r2 80028b8: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 80028ba: 687b ldr r3, [r7, #4] 80028bc: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 80028be: 687b ldr r3, [r7, #4] 80028c0: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 80028c2: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 80028c4: 687b ldr r3, [r7, #4] 80028c6: 691b ldr r3, [r3, #16] 80028c8: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80028ca: 687b ldr r3, [r7, #4] 80028cc: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 80028ce: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80028d0: 687b ldr r3, [r7, #4] 80028d2: 699b ldr r3, [r3, #24] 80028d4: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80028d6: 687b ldr r3, [r7, #4] 80028d8: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80028da: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80028dc: 687b ldr r3, [r7, #4] 80028de: 6a1b ldr r3, [r3, #32] 80028e0: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 80028e2: 697a ldr r2, [r7, #20] 80028e4: 4313 orrs r3, r2 80028e6: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80028e8: 687b ldr r3, [r7, #4] 80028ea: 6a5b ldr r3, [r3, #36] ; 0x24 80028ec: 2b04 cmp r3, #4 80028ee: d107 bne.n 8002900 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 80028f0: 687b ldr r3, [r7, #4] 80028f2: 6ada ldr r2, [r3, #44] ; 0x2c 80028f4: 687b ldr r3, [r7, #4] 80028f6: 6b1b ldr r3, [r3, #48] ; 0x30 80028f8: 4313 orrs r3, r2 80028fa: 697a ldr r2, [r7, #20] 80028fc: 4313 orrs r3, r2 80028fe: 617b str r3, [r7, #20] lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 8002900: 687b ldr r3, [r7, #4] 8002902: 685b ldr r3, [r3, #4] 8002904: 2b28 cmp r3, #40 ; 0x28 8002906: d903 bls.n 8002910 8002908: 687b ldr r3, [r7, #4] 800290a: 685b ldr r3, [r3, #4] 800290c: 2b2e cmp r3, #46 ; 0x2e 800290e: d91f bls.n 8002950 8002910: 687b ldr r3, [r7, #4] 8002912: 685b ldr r3, [r3, #4] 8002914: 2b3e cmp r3, #62 ; 0x3e 8002916: d903 bls.n 8002920 8002918: 687b ldr r3, [r7, #4] 800291a: 685b ldr r3, [r3, #4] 800291c: 2b42 cmp r3, #66 ; 0x42 800291e: d917 bls.n 8002950 8002920: 687b ldr r3, [r7, #4] 8002922: 685b ldr r3, [r3, #4] 8002924: 2b46 cmp r3, #70 ; 0x46 8002926: d903 bls.n 8002930 8002928: 687b ldr r3, [r7, #4] 800292a: 685b ldr r3, [r3, #4] 800292c: 2b48 cmp r3, #72 ; 0x48 800292e: d90f bls.n 8002950 8002930: 687b ldr r3, [r7, #4] 8002932: 685b ldr r3, [r3, #4] 8002934: 2b4e cmp r3, #78 ; 0x4e 8002936: d903 bls.n 8002940 8002938: 687b ldr r3, [r7, #4] 800293a: 685b ldr r3, [r3, #4] 800293c: 2b52 cmp r3, #82 ; 0x52 800293e: d907 bls.n 8002950 8002940: 687b ldr r3, [r7, #4] 8002942: 685b ldr r3, [r3, #4] 8002944: 2b73 cmp r3, #115 ; 0x73 8002946: d905 bls.n 8002954 8002948: 687b ldr r3, [r7, #4] 800294a: 685b ldr r3, [r3, #4] 800294c: 2b77 cmp r3, #119 ; 0x77 800294e: d801 bhi.n 8002954 8002950: 2301 movs r3, #1 8002952: e000 b.n 8002956 8002954: 2300 movs r3, #0 8002956: 2b00 cmp r3, #0 8002958: d003 beq.n 8002962 { registerValue |= DMA_SxCR_TRBUFF; 800295a: 697b ldr r3, [r7, #20] 800295c: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8002960: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8002962: 687b ldr r3, [r7, #4] 8002964: 681b ldr r3, [r3, #0] 8002966: 697a ldr r2, [r7, #20] 8002968: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 800296a: 687b ldr r3, [r7, #4] 800296c: 681b ldr r3, [r3, #0] 800296e: 695b ldr r3, [r3, #20] 8002970: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8002972: 697b ldr r3, [r7, #20] 8002974: f023 0307 bic.w r3, r3, #7 8002978: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 800297a: 687b ldr r3, [r7, #4] 800297c: 6a5b ldr r3, [r3, #36] ; 0x24 800297e: 697a ldr r2, [r7, #20] 8002980: 4313 orrs r3, r2 8002982: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8002984: 687b ldr r3, [r7, #4] 8002986: 6a5b ldr r3, [r3, #36] ; 0x24 8002988: 2b04 cmp r3, #4 800298a: d117 bne.n 80029bc { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 800298c: 687b ldr r3, [r7, #4] 800298e: 6a9b ldr r3, [r3, #40] ; 0x28 8002990: 697a ldr r2, [r7, #20] 8002992: 4313 orrs r3, r2 8002994: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8002996: 687b ldr r3, [r7, #4] 8002998: 6adb ldr r3, [r3, #44] ; 0x2c 800299a: 2b00 cmp r3, #0 800299c: d00e beq.n 80029bc { if (DMA_CheckFifoParam(hdma) != HAL_OK) 800299e: 6878 ldr r0, [r7, #4] 80029a0: f001 f9b4 bl 8003d0c 80029a4: 4603 mov r3, r0 80029a6: 2b00 cmp r3, #0 80029a8: d008 beq.n 80029bc { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 80029aa: 687b ldr r3, [r7, #4] 80029ac: 2240 movs r2, #64 ; 0x40 80029ae: 655a str r2, [r3, #84] ; 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80029b0: 687b ldr r3, [r7, #4] 80029b2: 2201 movs r2, #1 80029b4: f883 2035 strb.w r2, [r3, #53] ; 0x35 return HAL_ERROR; 80029b8: 2301 movs r3, #1 80029ba: e192 b.n 8002ce2 } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 80029bc: 687b ldr r3, [r7, #4] 80029be: 681b ldr r3, [r3, #0] 80029c0: 697a ldr r2, [r7, #20] 80029c2: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 80029c4: 6878 ldr r0, [r7, #4] 80029c6: f001 f8ef bl 8003ba8 80029ca: 4603 mov r3, r0 80029cc: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80029ce: 687b ldr r3, [r7, #4] 80029d0: 6ddb ldr r3, [r3, #92] ; 0x5c 80029d2: f003 031f and.w r3, r3, #31 80029d6: 223f movs r2, #63 ; 0x3f 80029d8: 409a lsls r2, r3 80029da: 68bb ldr r3, [r7, #8] 80029dc: 609a str r2, [r3, #8] 80029de: e0c8 b.n 8002b72 } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 80029e0: 687b ldr r3, [r7, #4] 80029e2: 681b ldr r3, [r3, #0] 80029e4: 4a38 ldr r2, [pc, #224] ; (8002ac8 ) 80029e6: 4293 cmp r3, r2 80029e8: d022 beq.n 8002a30 80029ea: 687b ldr r3, [r7, #4] 80029ec: 681b ldr r3, [r3, #0] 80029ee: 4a37 ldr r2, [pc, #220] ; (8002acc ) 80029f0: 4293 cmp r3, r2 80029f2: d01d beq.n 8002a30 80029f4: 687b ldr r3, [r7, #4] 80029f6: 681b ldr r3, [r3, #0] 80029f8: 4a35 ldr r2, [pc, #212] ; (8002ad0 ) 80029fa: 4293 cmp r3, r2 80029fc: d018 beq.n 8002a30 80029fe: 687b ldr r3, [r7, #4] 8002a00: 681b ldr r3, [r3, #0] 8002a02: 4a34 ldr r2, [pc, #208] ; (8002ad4 ) 8002a04: 4293 cmp r3, r2 8002a06: d013 beq.n 8002a30 8002a08: 687b ldr r3, [r7, #4] 8002a0a: 681b ldr r3, [r3, #0] 8002a0c: 4a32 ldr r2, [pc, #200] ; (8002ad8 ) 8002a0e: 4293 cmp r3, r2 8002a10: d00e beq.n 8002a30 8002a12: 687b ldr r3, [r7, #4] 8002a14: 681b ldr r3, [r3, #0] 8002a16: 4a31 ldr r2, [pc, #196] ; (8002adc ) 8002a18: 4293 cmp r3, r2 8002a1a: d009 beq.n 8002a30 8002a1c: 687b ldr r3, [r7, #4] 8002a1e: 681b ldr r3, [r3, #0] 8002a20: 4a2f ldr r2, [pc, #188] ; (8002ae0 ) 8002a22: 4293 cmp r3, r2 8002a24: d004 beq.n 8002a30 8002a26: 687b ldr r3, [r7, #4] 8002a28: 681b ldr r3, [r3, #0] 8002a2a: 4a2e ldr r2, [pc, #184] ; (8002ae4 ) 8002a2c: 4293 cmp r3, r2 8002a2e: d101 bne.n 8002a34 8002a30: 2301 movs r3, #1 8002a32: e000 b.n 8002a36 8002a34: 2300 movs r3, #0 8002a36: 2b00 cmp r3, #0 8002a38: f000 8092 beq.w 8002b60 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8002a3c: 687b ldr r3, [r7, #4] 8002a3e: 681b ldr r3, [r3, #0] 8002a40: 4a21 ldr r2, [pc, #132] ; (8002ac8 ) 8002a42: 4293 cmp r3, r2 8002a44: d021 beq.n 8002a8a 8002a46: 687b ldr r3, [r7, #4] 8002a48: 681b ldr r3, [r3, #0] 8002a4a: 4a20 ldr r2, [pc, #128] ; (8002acc ) 8002a4c: 4293 cmp r3, r2 8002a4e: d01c beq.n 8002a8a 8002a50: 687b ldr r3, [r7, #4] 8002a52: 681b ldr r3, [r3, #0] 8002a54: 4a1e ldr r2, [pc, #120] ; (8002ad0 ) 8002a56: 4293 cmp r3, r2 8002a58: d017 beq.n 8002a8a 8002a5a: 687b ldr r3, [r7, #4] 8002a5c: 681b ldr r3, [r3, #0] 8002a5e: 4a1d ldr r2, [pc, #116] ; (8002ad4 ) 8002a60: 4293 cmp r3, r2 8002a62: d012 beq.n 8002a8a 8002a64: 687b ldr r3, [r7, #4] 8002a66: 681b ldr r3, [r3, #0] 8002a68: 4a1b ldr r2, [pc, #108] ; (8002ad8 ) 8002a6a: 4293 cmp r3, r2 8002a6c: d00d beq.n 8002a8a 8002a6e: 687b ldr r3, [r7, #4] 8002a70: 681b ldr r3, [r3, #0] 8002a72: 4a1a ldr r2, [pc, #104] ; (8002adc ) 8002a74: 4293 cmp r3, r2 8002a76: d008 beq.n 8002a8a 8002a78: 687b ldr r3, [r7, #4] 8002a7a: 681b ldr r3, [r3, #0] 8002a7c: 4a18 ldr r2, [pc, #96] ; (8002ae0 ) 8002a7e: 4293 cmp r3, r2 8002a80: d003 beq.n 8002a8a 8002a82: 687b ldr r3, [r7, #4] 8002a84: 681b ldr r3, [r3, #0] 8002a86: 4a17 ldr r2, [pc, #92] ; (8002ae4 ) 8002a88: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002a8a: 687b ldr r3, [r7, #4] 8002a8c: 2202 movs r2, #2 8002a8e: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8002a92: 687b ldr r3, [r7, #4] 8002a94: 2200 movs r2, #0 8002a96: f883 2034 strb.w r2, [r3, #52] ; 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 8002a9a: 687b ldr r3, [r7, #4] 8002a9c: 681b ldr r3, [r3, #0] 8002a9e: 681b ldr r3, [r3, #0] 8002aa0: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 8002aa2: 697a ldr r2, [r7, #20] 8002aa4: 4b10 ldr r3, [pc, #64] ; (8002ae8 ) 8002aa6: 4013 ands r3, r2 8002aa8: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8002aaa: 687b ldr r3, [r7, #4] 8002aac: 689b ldr r3, [r3, #8] 8002aae: 2b40 cmp r3, #64 ; 0x40 8002ab0: d01c beq.n 8002aec 8002ab2: 687b ldr r3, [r7, #4] 8002ab4: 689b ldr r3, [r3, #8] 8002ab6: 2b80 cmp r3, #128 ; 0x80 8002ab8: d102 bne.n 8002ac0 8002aba: f44f 4380 mov.w r3, #16384 ; 0x4000 8002abe: e016 b.n 8002aee 8002ac0: 2300 movs r3, #0 8002ac2: e014 b.n 8002aee 8002ac4: fe10803f .word 0xfe10803f 8002ac8: 58025408 .word 0x58025408 8002acc: 5802541c .word 0x5802541c 8002ad0: 58025430 .word 0x58025430 8002ad4: 58025444 .word 0x58025444 8002ad8: 58025458 .word 0x58025458 8002adc: 5802546c .word 0x5802546c 8002ae0: 58025480 .word 0x58025480 8002ae4: 58025494 .word 0x58025494 8002ae8: fffe000f .word 0xfffe000f 8002aec: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8002aee: 687a ldr r2, [r7, #4] 8002af0: 68d2 ldr r2, [r2, #12] 8002af2: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8002af4: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8002af6: 687b ldr r3, [r7, #4] 8002af8: 691b ldr r3, [r3, #16] 8002afa: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8002afc: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8002afe: 687b ldr r3, [r7, #4] 8002b00: 695b ldr r3, [r3, #20] 8002b02: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8002b04: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8002b06: 687b ldr r3, [r7, #4] 8002b08: 699b ldr r3, [r3, #24] 8002b0a: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8002b0c: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8002b0e: 687b ldr r3, [r7, #4] 8002b10: 69db ldr r3, [r3, #28] 8002b12: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8002b14: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 8002b16: 687b ldr r3, [r7, #4] 8002b18: 6a1b ldr r3, [r3, #32] 8002b1a: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8002b1c: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8002b1e: 697a ldr r2, [r7, #20] 8002b20: 4313 orrs r3, r2 8002b22: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 8002b24: 687b ldr r3, [r7, #4] 8002b26: 681b ldr r3, [r3, #0] 8002b28: 697a ldr r2, [r7, #20] 8002b2a: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 8002b2c: 687b ldr r3, [r7, #4] 8002b2e: 681b ldr r3, [r3, #0] 8002b30: 461a mov r2, r3 8002b32: 4b6e ldr r3, [pc, #440] ; (8002cec ) 8002b34: 4413 add r3, r2 8002b36: 4a6e ldr r2, [pc, #440] ; (8002cf0 ) 8002b38: fba2 2303 umull r2, r3, r2, r3 8002b3c: 091b lsrs r3, r3, #4 8002b3e: 009a lsls r2, r3, #2 8002b40: 687b ldr r3, [r7, #4] 8002b42: 65da str r2, [r3, #92] ; 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8002b44: 6878 ldr r0, [r7, #4] 8002b46: f001 f82f bl 8003ba8 8002b4a: 4603 mov r3, r0 8002b4c: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8002b4e: 687b ldr r3, [r7, #4] 8002b50: 6ddb ldr r3, [r3, #92] ; 0x5c 8002b52: f003 031f and.w r3, r3, #31 8002b56: 2201 movs r2, #1 8002b58: 409a lsls r2, r3 8002b5a: 68fb ldr r3, [r7, #12] 8002b5c: 605a str r2, [r3, #4] 8002b5e: e008 b.n 8002b72 } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8002b60: 687b ldr r3, [r7, #4] 8002b62: 2240 movs r2, #64 ; 0x40 8002b64: 655a str r2, [r3, #84] ; 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8002b66: 687b ldr r3, [r7, #4] 8002b68: 2203 movs r2, #3 8002b6a: f883 2035 strb.w r2, [r3, #53] ; 0x35 return HAL_ERROR; 8002b6e: 2301 movs r3, #1 8002b70: e0b7 b.n 8002ce2 } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8002b72: 687b ldr r3, [r7, #4] 8002b74: 681b ldr r3, [r3, #0] 8002b76: 4a5f ldr r2, [pc, #380] ; (8002cf4 ) 8002b78: 4293 cmp r3, r2 8002b7a: d072 beq.n 8002c62 8002b7c: 687b ldr r3, [r7, #4] 8002b7e: 681b ldr r3, [r3, #0] 8002b80: 4a5d ldr r2, [pc, #372] ; (8002cf8 ) 8002b82: 4293 cmp r3, r2 8002b84: d06d beq.n 8002c62 8002b86: 687b ldr r3, [r7, #4] 8002b88: 681b ldr r3, [r3, #0] 8002b8a: 4a5c ldr r2, [pc, #368] ; (8002cfc ) 8002b8c: 4293 cmp r3, r2 8002b8e: d068 beq.n 8002c62 8002b90: 687b ldr r3, [r7, #4] 8002b92: 681b ldr r3, [r3, #0] 8002b94: 4a5a ldr r2, [pc, #360] ; (8002d00 ) 8002b96: 4293 cmp r3, r2 8002b98: d063 beq.n 8002c62 8002b9a: 687b ldr r3, [r7, #4] 8002b9c: 681b ldr r3, [r3, #0] 8002b9e: 4a59 ldr r2, [pc, #356] ; (8002d04 ) 8002ba0: 4293 cmp r3, r2 8002ba2: d05e beq.n 8002c62 8002ba4: 687b ldr r3, [r7, #4] 8002ba6: 681b ldr r3, [r3, #0] 8002ba8: 4a57 ldr r2, [pc, #348] ; (8002d08 ) 8002baa: 4293 cmp r3, r2 8002bac: d059 beq.n 8002c62 8002bae: 687b ldr r3, [r7, #4] 8002bb0: 681b ldr r3, [r3, #0] 8002bb2: 4a56 ldr r2, [pc, #344] ; (8002d0c ) 8002bb4: 4293 cmp r3, r2 8002bb6: d054 beq.n 8002c62 8002bb8: 687b ldr r3, [r7, #4] 8002bba: 681b ldr r3, [r3, #0] 8002bbc: 4a54 ldr r2, [pc, #336] ; (8002d10 ) 8002bbe: 4293 cmp r3, r2 8002bc0: d04f beq.n 8002c62 8002bc2: 687b ldr r3, [r7, #4] 8002bc4: 681b ldr r3, [r3, #0] 8002bc6: 4a53 ldr r2, [pc, #332] ; (8002d14 ) 8002bc8: 4293 cmp r3, r2 8002bca: d04a beq.n 8002c62 8002bcc: 687b ldr r3, [r7, #4] 8002bce: 681b ldr r3, [r3, #0] 8002bd0: 4a51 ldr r2, [pc, #324] ; (8002d18 ) 8002bd2: 4293 cmp r3, r2 8002bd4: d045 beq.n 8002c62 8002bd6: 687b ldr r3, [r7, #4] 8002bd8: 681b ldr r3, [r3, #0] 8002bda: 4a50 ldr r2, [pc, #320] ; (8002d1c ) 8002bdc: 4293 cmp r3, r2 8002bde: d040 beq.n 8002c62 8002be0: 687b ldr r3, [r7, #4] 8002be2: 681b ldr r3, [r3, #0] 8002be4: 4a4e ldr r2, [pc, #312] ; (8002d20 ) 8002be6: 4293 cmp r3, r2 8002be8: d03b beq.n 8002c62 8002bea: 687b ldr r3, [r7, #4] 8002bec: 681b ldr r3, [r3, #0] 8002bee: 4a4d ldr r2, [pc, #308] ; (8002d24 ) 8002bf0: 4293 cmp r3, r2 8002bf2: d036 beq.n 8002c62 8002bf4: 687b ldr r3, [r7, #4] 8002bf6: 681b ldr r3, [r3, #0] 8002bf8: 4a4b ldr r2, [pc, #300] ; (8002d28 ) 8002bfa: 4293 cmp r3, r2 8002bfc: d031 beq.n 8002c62 8002bfe: 687b ldr r3, [r7, #4] 8002c00: 681b ldr r3, [r3, #0] 8002c02: 4a4a ldr r2, [pc, #296] ; (8002d2c ) 8002c04: 4293 cmp r3, r2 8002c06: d02c beq.n 8002c62 8002c08: 687b ldr r3, [r7, #4] 8002c0a: 681b ldr r3, [r3, #0] 8002c0c: 4a48 ldr r2, [pc, #288] ; (8002d30 ) 8002c0e: 4293 cmp r3, r2 8002c10: d027 beq.n 8002c62 8002c12: 687b ldr r3, [r7, #4] 8002c14: 681b ldr r3, [r3, #0] 8002c16: 4a47 ldr r2, [pc, #284] ; (8002d34 ) 8002c18: 4293 cmp r3, r2 8002c1a: d022 beq.n 8002c62 8002c1c: 687b ldr r3, [r7, #4] 8002c1e: 681b ldr r3, [r3, #0] 8002c20: 4a45 ldr r2, [pc, #276] ; (8002d38 ) 8002c22: 4293 cmp r3, r2 8002c24: d01d beq.n 8002c62 8002c26: 687b ldr r3, [r7, #4] 8002c28: 681b ldr r3, [r3, #0] 8002c2a: 4a44 ldr r2, [pc, #272] ; (8002d3c ) 8002c2c: 4293 cmp r3, r2 8002c2e: d018 beq.n 8002c62 8002c30: 687b ldr r3, [r7, #4] 8002c32: 681b ldr r3, [r3, #0] 8002c34: 4a42 ldr r2, [pc, #264] ; (8002d40 ) 8002c36: 4293 cmp r3, r2 8002c38: d013 beq.n 8002c62 8002c3a: 687b ldr r3, [r7, #4] 8002c3c: 681b ldr r3, [r3, #0] 8002c3e: 4a41 ldr r2, [pc, #260] ; (8002d44 ) 8002c40: 4293 cmp r3, r2 8002c42: d00e beq.n 8002c62 8002c44: 687b ldr r3, [r7, #4] 8002c46: 681b ldr r3, [r3, #0] 8002c48: 4a3f ldr r2, [pc, #252] ; (8002d48 ) 8002c4a: 4293 cmp r3, r2 8002c4c: d009 beq.n 8002c62 8002c4e: 687b ldr r3, [r7, #4] 8002c50: 681b ldr r3, [r3, #0] 8002c52: 4a3e ldr r2, [pc, #248] ; (8002d4c ) 8002c54: 4293 cmp r3, r2 8002c56: d004 beq.n 8002c62 8002c58: 687b ldr r3, [r7, #4] 8002c5a: 681b ldr r3, [r3, #0] 8002c5c: 4a3c ldr r2, [pc, #240] ; (8002d50 ) 8002c5e: 4293 cmp r3, r2 8002c60: d101 bne.n 8002c66 8002c62: 2301 movs r3, #1 8002c64: e000 b.n 8002c68 8002c66: 2300 movs r3, #0 8002c68: 2b00 cmp r3, #0 8002c6a: d032 beq.n 8002cd2 { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8002c6c: 6878 ldr r0, [r7, #4] 8002c6e: f001 f8c9 bl 8003e04 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8002c72: 687b ldr r3, [r7, #4] 8002c74: 689b ldr r3, [r3, #8] 8002c76: 2b80 cmp r3, #128 ; 0x80 8002c78: d102 bne.n 8002c80 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8002c7a: 687b ldr r3, [r7, #4] 8002c7c: 2200 movs r2, #0 8002c7e: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8002c80: 687b ldr r3, [r7, #4] 8002c82: 685a ldr r2, [r3, #4] 8002c84: 687b ldr r3, [r7, #4] 8002c86: 6e1b ldr r3, [r3, #96] ; 0x60 8002c88: b2d2 uxtb r2, r2 8002c8a: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8002c8c: 687b ldr r3, [r7, #4] 8002c8e: 6e5b ldr r3, [r3, #100] ; 0x64 8002c90: 687a ldr r2, [r7, #4] 8002c92: 6e92 ldr r2, [r2, #104] ; 0x68 8002c94: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8002c96: 687b ldr r3, [r7, #4] 8002c98: 685b ldr r3, [r3, #4] 8002c9a: 2b00 cmp r3, #0 8002c9c: d010 beq.n 8002cc0 8002c9e: 687b ldr r3, [r7, #4] 8002ca0: 685b ldr r3, [r3, #4] 8002ca2: 2b08 cmp r3, #8 8002ca4: d80c bhi.n 8002cc0 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8002ca6: 6878 ldr r0, [r7, #4] 8002ca8: f001 f946 bl 8003f38 /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 8002cac: 687b ldr r3, [r7, #4] 8002cae: 6edb ldr r3, [r3, #108] ; 0x6c 8002cb0: 2200 movs r2, #0 8002cb2: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8002cb4: 687b ldr r3, [r7, #4] 8002cb6: 6f1b ldr r3, [r3, #112] ; 0x70 8002cb8: 687a ldr r2, [r7, #4] 8002cba: 6f52 ldr r2, [r2, #116] ; 0x74 8002cbc: 605a str r2, [r3, #4] 8002cbe: e008 b.n 8002cd2 } else { hdma->DMAmuxRequestGen = 0U; 8002cc0: 687b ldr r3, [r7, #4] 8002cc2: 2200 movs r2, #0 8002cc4: 66da str r2, [r3, #108] ; 0x6c hdma->DMAmuxRequestGenStatus = 0U; 8002cc6: 687b ldr r3, [r7, #4] 8002cc8: 2200 movs r2, #0 8002cca: 671a str r2, [r3, #112] ; 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 8002ccc: 687b ldr r3, [r7, #4] 8002cce: 2200 movs r2, #0 8002cd0: 675a str r2, [r3, #116] ; 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002cd2: 687b ldr r3, [r7, #4] 8002cd4: 2200 movs r2, #0 8002cd6: 655a str r2, [r3, #84] ; 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002cd8: 687b ldr r3, [r7, #4] 8002cda: 2201 movs r2, #1 8002cdc: f883 2035 strb.w r2, [r3, #53] ; 0x35 return HAL_OK; 8002ce0: 2300 movs r3, #0 } 8002ce2: 4618 mov r0, r3 8002ce4: 3718 adds r7, #24 8002ce6: 46bd mov sp, r7 8002ce8: bd80 pop {r7, pc} 8002cea: bf00 nop 8002cec: a7fdabf8 .word 0xa7fdabf8 8002cf0: cccccccd .word 0xcccccccd 8002cf4: 40020010 .word 0x40020010 8002cf8: 40020028 .word 0x40020028 8002cfc: 40020040 .word 0x40020040 8002d00: 40020058 .word 0x40020058 8002d04: 40020070 .word 0x40020070 8002d08: 40020088 .word 0x40020088 8002d0c: 400200a0 .word 0x400200a0 8002d10: 400200b8 .word 0x400200b8 8002d14: 40020410 .word 0x40020410 8002d18: 40020428 .word 0x40020428 8002d1c: 40020440 .word 0x40020440 8002d20: 40020458 .word 0x40020458 8002d24: 40020470 .word 0x40020470 8002d28: 40020488 .word 0x40020488 8002d2c: 400204a0 .word 0x400204a0 8002d30: 400204b8 .word 0x400204b8 8002d34: 58025408 .word 0x58025408 8002d38: 5802541c .word 0x5802541c 8002d3c: 58025430 .word 0x58025430 8002d40: 58025444 .word 0x58025444 8002d44: 58025458 .word 0x58025458 8002d48: 5802546c .word 0x5802546c 8002d4c: 58025480 .word 0x58025480 8002d50: 58025494 .word 0x58025494 08002d54 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8002d54: b580 push {r7, lr} 8002d56: b08a sub sp, #40 ; 0x28 8002d58: af00 add r7, sp, #0 8002d5a: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 8002d5c: 2300 movs r3, #0 8002d5e: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 8002d60: 4b67 ldr r3, [pc, #412] ; (8002f00 ) 8002d62: 681b ldr r3, [r3, #0] 8002d64: 4a67 ldr r2, [pc, #412] ; (8002f04 ) 8002d66: fba2 2303 umull r2, r3, r2, r3 8002d6a: 0a9b lsrs r3, r3, #10 8002d6c: 627b str r3, [r7, #36] ; 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8002d6e: 687b ldr r3, [r7, #4] 8002d70: 6d9b ldr r3, [r3, #88] ; 0x58 8002d72: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8002d74: 687b ldr r3, [r7, #4] 8002d76: 6d9b ldr r3, [r3, #88] ; 0x58 8002d78: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 8002d7a: 6a3b ldr r3, [r7, #32] 8002d7c: 681b ldr r3, [r3, #0] 8002d7e: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 8002d80: 69fb ldr r3, [r7, #28] 8002d82: 681b ldr r3, [r3, #0] 8002d84: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8002d86: 687b ldr r3, [r7, #4] 8002d88: 681b ldr r3, [r3, #0] 8002d8a: 4a5f ldr r2, [pc, #380] ; (8002f08 ) 8002d8c: 4293 cmp r3, r2 8002d8e: d04a beq.n 8002e26 8002d90: 687b ldr r3, [r7, #4] 8002d92: 681b ldr r3, [r3, #0] 8002d94: 4a5d ldr r2, [pc, #372] ; (8002f0c ) 8002d96: 4293 cmp r3, r2 8002d98: d045 beq.n 8002e26 8002d9a: 687b ldr r3, [r7, #4] 8002d9c: 681b ldr r3, [r3, #0] 8002d9e: 4a5c ldr r2, [pc, #368] ; (8002f10 ) 8002da0: 4293 cmp r3, r2 8002da2: d040 beq.n 8002e26 8002da4: 687b ldr r3, [r7, #4] 8002da6: 681b ldr r3, [r3, #0] 8002da8: 4a5a ldr r2, [pc, #360] ; (8002f14 ) 8002daa: 4293 cmp r3, r2 8002dac: d03b beq.n 8002e26 8002dae: 687b ldr r3, [r7, #4] 8002db0: 681b ldr r3, [r3, #0] 8002db2: 4a59 ldr r2, [pc, #356] ; (8002f18 ) 8002db4: 4293 cmp r3, r2 8002db6: d036 beq.n 8002e26 8002db8: 687b ldr r3, [r7, #4] 8002dba: 681b ldr r3, [r3, #0] 8002dbc: 4a57 ldr r2, [pc, #348] ; (8002f1c ) 8002dbe: 4293 cmp r3, r2 8002dc0: d031 beq.n 8002e26 8002dc2: 687b ldr r3, [r7, #4] 8002dc4: 681b ldr r3, [r3, #0] 8002dc6: 4a56 ldr r2, [pc, #344] ; (8002f20 ) 8002dc8: 4293 cmp r3, r2 8002dca: d02c beq.n 8002e26 8002dcc: 687b ldr r3, [r7, #4] 8002dce: 681b ldr r3, [r3, #0] 8002dd0: 4a54 ldr r2, [pc, #336] ; (8002f24 ) 8002dd2: 4293 cmp r3, r2 8002dd4: d027 beq.n 8002e26 8002dd6: 687b ldr r3, [r7, #4] 8002dd8: 681b ldr r3, [r3, #0] 8002dda: 4a53 ldr r2, [pc, #332] ; (8002f28 ) 8002ddc: 4293 cmp r3, r2 8002dde: d022 beq.n 8002e26 8002de0: 687b ldr r3, [r7, #4] 8002de2: 681b ldr r3, [r3, #0] 8002de4: 4a51 ldr r2, [pc, #324] ; (8002f2c ) 8002de6: 4293 cmp r3, r2 8002de8: d01d beq.n 8002e26 8002dea: 687b ldr r3, [r7, #4] 8002dec: 681b ldr r3, [r3, #0] 8002dee: 4a50 ldr r2, [pc, #320] ; (8002f30 ) 8002df0: 4293 cmp r3, r2 8002df2: d018 beq.n 8002e26 8002df4: 687b ldr r3, [r7, #4] 8002df6: 681b ldr r3, [r3, #0] 8002df8: 4a4e ldr r2, [pc, #312] ; (8002f34 ) 8002dfa: 4293 cmp r3, r2 8002dfc: d013 beq.n 8002e26 8002dfe: 687b ldr r3, [r7, #4] 8002e00: 681b ldr r3, [r3, #0] 8002e02: 4a4d ldr r2, [pc, #308] ; (8002f38 ) 8002e04: 4293 cmp r3, r2 8002e06: d00e beq.n 8002e26 8002e08: 687b ldr r3, [r7, #4] 8002e0a: 681b ldr r3, [r3, #0] 8002e0c: 4a4b ldr r2, [pc, #300] ; (8002f3c ) 8002e0e: 4293 cmp r3, r2 8002e10: d009 beq.n 8002e26 8002e12: 687b ldr r3, [r7, #4] 8002e14: 681b ldr r3, [r3, #0] 8002e16: 4a4a ldr r2, [pc, #296] ; (8002f40 ) 8002e18: 4293 cmp r3, r2 8002e1a: d004 beq.n 8002e26 8002e1c: 687b ldr r3, [r7, #4] 8002e1e: 681b ldr r3, [r3, #0] 8002e20: 4a48 ldr r2, [pc, #288] ; (8002f44 ) 8002e22: 4293 cmp r3, r2 8002e24: d101 bne.n 8002e2a 8002e26: 2301 movs r3, #1 8002e28: e000 b.n 8002e2c 8002e2a: 2300 movs r3, #0 8002e2c: 2b00 cmp r3, #0 8002e2e: f000 842b beq.w 8003688 { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8002e32: 687b ldr r3, [r7, #4] 8002e34: 6ddb ldr r3, [r3, #92] ; 0x5c 8002e36: f003 031f and.w r3, r3, #31 8002e3a: 2208 movs r2, #8 8002e3c: 409a lsls r2, r3 8002e3e: 69bb ldr r3, [r7, #24] 8002e40: 4013 ands r3, r2 8002e42: 2b00 cmp r3, #0 8002e44: f000 80a2 beq.w 8002f8c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8002e48: 687b ldr r3, [r7, #4] 8002e4a: 681b ldr r3, [r3, #0] 8002e4c: 4a2e ldr r2, [pc, #184] ; (8002f08 ) 8002e4e: 4293 cmp r3, r2 8002e50: d04a beq.n 8002ee8 8002e52: 687b ldr r3, [r7, #4] 8002e54: 681b ldr r3, [r3, #0] 8002e56: 4a2d ldr r2, [pc, #180] ; (8002f0c ) 8002e58: 4293 cmp r3, r2 8002e5a: d045 beq.n 8002ee8 8002e5c: 687b ldr r3, [r7, #4] 8002e5e: 681b ldr r3, [r3, #0] 8002e60: 4a2b ldr r2, [pc, #172] ; (8002f10 ) 8002e62: 4293 cmp r3, r2 8002e64: d040 beq.n 8002ee8 8002e66: 687b ldr r3, [r7, #4] 8002e68: 681b ldr r3, [r3, #0] 8002e6a: 4a2a ldr r2, [pc, #168] ; (8002f14 ) 8002e6c: 4293 cmp r3, r2 8002e6e: d03b beq.n 8002ee8 8002e70: 687b ldr r3, [r7, #4] 8002e72: 681b ldr r3, [r3, #0] 8002e74: 4a28 ldr r2, [pc, #160] ; (8002f18 ) 8002e76: 4293 cmp r3, r2 8002e78: d036 beq.n 8002ee8 8002e7a: 687b ldr r3, [r7, #4] 8002e7c: 681b ldr r3, [r3, #0] 8002e7e: 4a27 ldr r2, [pc, #156] ; (8002f1c ) 8002e80: 4293 cmp r3, r2 8002e82: d031 beq.n 8002ee8 8002e84: 687b ldr r3, [r7, #4] 8002e86: 681b ldr r3, [r3, #0] 8002e88: 4a25 ldr r2, [pc, #148] ; (8002f20 ) 8002e8a: 4293 cmp r3, r2 8002e8c: d02c beq.n 8002ee8 8002e8e: 687b ldr r3, [r7, #4] 8002e90: 681b ldr r3, [r3, #0] 8002e92: 4a24 ldr r2, [pc, #144] ; (8002f24 ) 8002e94: 4293 cmp r3, r2 8002e96: d027 beq.n 8002ee8 8002e98: 687b ldr r3, [r7, #4] 8002e9a: 681b ldr r3, [r3, #0] 8002e9c: 4a22 ldr r2, [pc, #136] ; (8002f28 ) 8002e9e: 4293 cmp r3, r2 8002ea0: d022 beq.n 8002ee8 8002ea2: 687b ldr r3, [r7, #4] 8002ea4: 681b ldr r3, [r3, #0] 8002ea6: 4a21 ldr r2, [pc, #132] ; (8002f2c ) 8002ea8: 4293 cmp r3, r2 8002eaa: d01d beq.n 8002ee8 8002eac: 687b ldr r3, [r7, #4] 8002eae: 681b ldr r3, [r3, #0] 8002eb0: 4a1f ldr r2, [pc, #124] ; (8002f30 ) 8002eb2: 4293 cmp r3, r2 8002eb4: d018 beq.n 8002ee8 8002eb6: 687b ldr r3, [r7, #4] 8002eb8: 681b ldr r3, [r3, #0] 8002eba: 4a1e ldr r2, [pc, #120] ; (8002f34 ) 8002ebc: 4293 cmp r3, r2 8002ebe: d013 beq.n 8002ee8 8002ec0: 687b ldr r3, [r7, #4] 8002ec2: 681b ldr r3, [r3, #0] 8002ec4: 4a1c ldr r2, [pc, #112] ; (8002f38 ) 8002ec6: 4293 cmp r3, r2 8002ec8: d00e beq.n 8002ee8 8002eca: 687b ldr r3, [r7, #4] 8002ecc: 681b ldr r3, [r3, #0] 8002ece: 4a1b ldr r2, [pc, #108] ; (8002f3c ) 8002ed0: 4293 cmp r3, r2 8002ed2: d009 beq.n 8002ee8 8002ed4: 687b ldr r3, [r7, #4] 8002ed6: 681b ldr r3, [r3, #0] 8002ed8: 4a19 ldr r2, [pc, #100] ; (8002f40 ) 8002eda: 4293 cmp r3, r2 8002edc: d004 beq.n 8002ee8 8002ede: 687b ldr r3, [r7, #4] 8002ee0: 681b ldr r3, [r3, #0] 8002ee2: 4a18 ldr r2, [pc, #96] ; (8002f44 ) 8002ee4: 4293 cmp r3, r2 8002ee6: d12f bne.n 8002f48 8002ee8: 687b ldr r3, [r7, #4] 8002eea: 681b ldr r3, [r3, #0] 8002eec: 681b ldr r3, [r3, #0] 8002eee: f003 0304 and.w r3, r3, #4 8002ef2: 2b00 cmp r3, #0 8002ef4: bf14 ite ne 8002ef6: 2301 movne r3, #1 8002ef8: 2300 moveq r3, #0 8002efa: b2db uxtb r3, r3 8002efc: e02e b.n 8002f5c 8002efe: bf00 nop 8002f00: 24000014 .word 0x24000014 8002f04: 1b4e81b5 .word 0x1b4e81b5 8002f08: 40020010 .word 0x40020010 8002f0c: 40020028 .word 0x40020028 8002f10: 40020040 .word 0x40020040 8002f14: 40020058 .word 0x40020058 8002f18: 40020070 .word 0x40020070 8002f1c: 40020088 .word 0x40020088 8002f20: 400200a0 .word 0x400200a0 8002f24: 400200b8 .word 0x400200b8 8002f28: 40020410 .word 0x40020410 8002f2c: 40020428 .word 0x40020428 8002f30: 40020440 .word 0x40020440 8002f34: 40020458 .word 0x40020458 8002f38: 40020470 .word 0x40020470 8002f3c: 40020488 .word 0x40020488 8002f40: 400204a0 .word 0x400204a0 8002f44: 400204b8 .word 0x400204b8 8002f48: 687b ldr r3, [r7, #4] 8002f4a: 681b ldr r3, [r3, #0] 8002f4c: 681b ldr r3, [r3, #0] 8002f4e: f003 0308 and.w r3, r3, #8 8002f52: 2b00 cmp r3, #0 8002f54: bf14 ite ne 8002f56: 2301 movne r3, #1 8002f58: 2300 moveq r3, #0 8002f5a: b2db uxtb r3, r3 8002f5c: 2b00 cmp r3, #0 8002f5e: d015 beq.n 8002f8c { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8002f60: 687b ldr r3, [r7, #4] 8002f62: 681b ldr r3, [r3, #0] 8002f64: 681a ldr r2, [r3, #0] 8002f66: 687b ldr r3, [r7, #4] 8002f68: 681b ldr r3, [r3, #0] 8002f6a: f022 0204 bic.w r2, r2, #4 8002f6e: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8002f70: 687b ldr r3, [r7, #4] 8002f72: 6ddb ldr r3, [r3, #92] ; 0x5c 8002f74: f003 031f and.w r3, r3, #31 8002f78: 2208 movs r2, #8 8002f7a: 409a lsls r2, r3 8002f7c: 6a3b ldr r3, [r7, #32] 8002f7e: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8002f80: 687b ldr r3, [r7, #4] 8002f82: 6d5b ldr r3, [r3, #84] ; 0x54 8002f84: f043 0201 orr.w r2, r3, #1 8002f88: 687b ldr r3, [r7, #4] 8002f8a: 655a str r2, [r3, #84] ; 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8002f8c: 687b ldr r3, [r7, #4] 8002f8e: 6ddb ldr r3, [r3, #92] ; 0x5c 8002f90: f003 031f and.w r3, r3, #31 8002f94: 69ba ldr r2, [r7, #24] 8002f96: fa22 f303 lsr.w r3, r2, r3 8002f9a: f003 0301 and.w r3, r3, #1 8002f9e: 2b00 cmp r3, #0 8002fa0: d06e beq.n 8003080 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8002fa2: 687b ldr r3, [r7, #4] 8002fa4: 681b ldr r3, [r3, #0] 8002fa6: 4a69 ldr r2, [pc, #420] ; (800314c ) 8002fa8: 4293 cmp r3, r2 8002faa: d04a beq.n 8003042 8002fac: 687b ldr r3, [r7, #4] 8002fae: 681b ldr r3, [r3, #0] 8002fb0: 4a67 ldr r2, [pc, #412] ; (8003150 ) 8002fb2: 4293 cmp r3, r2 8002fb4: d045 beq.n 8003042 8002fb6: 687b ldr r3, [r7, #4] 8002fb8: 681b ldr r3, [r3, #0] 8002fba: 4a66 ldr r2, [pc, #408] ; (8003154 ) 8002fbc: 4293 cmp r3, r2 8002fbe: d040 beq.n 8003042 8002fc0: 687b ldr r3, [r7, #4] 8002fc2: 681b ldr r3, [r3, #0] 8002fc4: 4a64 ldr r2, [pc, #400] ; (8003158 ) 8002fc6: 4293 cmp r3, r2 8002fc8: d03b beq.n 8003042 8002fca: 687b ldr r3, [r7, #4] 8002fcc: 681b ldr r3, [r3, #0] 8002fce: 4a63 ldr r2, [pc, #396] ; (800315c ) 8002fd0: 4293 cmp r3, r2 8002fd2: d036 beq.n 8003042 8002fd4: 687b ldr r3, [r7, #4] 8002fd6: 681b ldr r3, [r3, #0] 8002fd8: 4a61 ldr r2, [pc, #388] ; (8003160 ) 8002fda: 4293 cmp r3, r2 8002fdc: d031 beq.n 8003042 8002fde: 687b ldr r3, [r7, #4] 8002fe0: 681b ldr r3, [r3, #0] 8002fe2: 4a60 ldr r2, [pc, #384] ; (8003164 ) 8002fe4: 4293 cmp r3, r2 8002fe6: d02c beq.n 8003042 8002fe8: 687b ldr r3, [r7, #4] 8002fea: 681b ldr r3, [r3, #0] 8002fec: 4a5e ldr r2, [pc, #376] ; (8003168 ) 8002fee: 4293 cmp r3, r2 8002ff0: d027 beq.n 8003042 8002ff2: 687b ldr r3, [r7, #4] 8002ff4: 681b ldr r3, [r3, #0] 8002ff6: 4a5d ldr r2, [pc, #372] ; (800316c ) 8002ff8: 4293 cmp r3, r2 8002ffa: d022 beq.n 8003042 8002ffc: 687b ldr r3, [r7, #4] 8002ffe: 681b ldr r3, [r3, #0] 8003000: 4a5b ldr r2, [pc, #364] ; (8003170 ) 8003002: 4293 cmp r3, r2 8003004: d01d beq.n 8003042 8003006: 687b ldr r3, [r7, #4] 8003008: 681b ldr r3, [r3, #0] 800300a: 4a5a ldr r2, [pc, #360] ; (8003174 ) 800300c: 4293 cmp r3, r2 800300e: d018 beq.n 8003042 8003010: 687b ldr r3, [r7, #4] 8003012: 681b ldr r3, [r3, #0] 8003014: 4a58 ldr r2, [pc, #352] ; (8003178 ) 8003016: 4293 cmp r3, r2 8003018: d013 beq.n 8003042 800301a: 687b ldr r3, [r7, #4] 800301c: 681b ldr r3, [r3, #0] 800301e: 4a57 ldr r2, [pc, #348] ; (800317c ) 8003020: 4293 cmp r3, r2 8003022: d00e beq.n 8003042 8003024: 687b ldr r3, [r7, #4] 8003026: 681b ldr r3, [r3, #0] 8003028: 4a55 ldr r2, [pc, #340] ; (8003180 ) 800302a: 4293 cmp r3, r2 800302c: d009 beq.n 8003042 800302e: 687b ldr r3, [r7, #4] 8003030: 681b ldr r3, [r3, #0] 8003032: 4a54 ldr r2, [pc, #336] ; (8003184 ) 8003034: 4293 cmp r3, r2 8003036: d004 beq.n 8003042 8003038: 687b ldr r3, [r7, #4] 800303a: 681b ldr r3, [r3, #0] 800303c: 4a52 ldr r2, [pc, #328] ; (8003188 ) 800303e: 4293 cmp r3, r2 8003040: d10a bne.n 8003058 8003042: 687b ldr r3, [r7, #4] 8003044: 681b ldr r3, [r3, #0] 8003046: 695b ldr r3, [r3, #20] 8003048: f003 0380 and.w r3, r3, #128 ; 0x80 800304c: 2b00 cmp r3, #0 800304e: bf14 ite ne 8003050: 2301 movne r3, #1 8003052: 2300 moveq r3, #0 8003054: b2db uxtb r3, r3 8003056: e003 b.n 8003060 8003058: 687b ldr r3, [r7, #4] 800305a: 681b ldr r3, [r3, #0] 800305c: 681b ldr r3, [r3, #0] 800305e: 2300 movs r3, #0 8003060: 2b00 cmp r3, #0 8003062: d00d beq.n 8003080 { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8003064: 687b ldr r3, [r7, #4] 8003066: 6ddb ldr r3, [r3, #92] ; 0x5c 8003068: f003 031f and.w r3, r3, #31 800306c: 2201 movs r2, #1 800306e: 409a lsls r2, r3 8003070: 6a3b ldr r3, [r7, #32] 8003072: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8003074: 687b ldr r3, [r7, #4] 8003076: 6d5b ldr r3, [r3, #84] ; 0x54 8003078: f043 0202 orr.w r2, r3, #2 800307c: 687b ldr r3, [r7, #4] 800307e: 655a str r2, [r3, #84] ; 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003080: 687b ldr r3, [r7, #4] 8003082: 6ddb ldr r3, [r3, #92] ; 0x5c 8003084: f003 031f and.w r3, r3, #31 8003088: 2204 movs r2, #4 800308a: 409a lsls r2, r3 800308c: 69bb ldr r3, [r7, #24] 800308e: 4013 ands r3, r2 8003090: 2b00 cmp r3, #0 8003092: f000 808f beq.w 80031b4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8003096: 687b ldr r3, [r7, #4] 8003098: 681b ldr r3, [r3, #0] 800309a: 4a2c ldr r2, [pc, #176] ; (800314c ) 800309c: 4293 cmp r3, r2 800309e: d04a beq.n 8003136 80030a0: 687b ldr r3, [r7, #4] 80030a2: 681b ldr r3, [r3, #0] 80030a4: 4a2a ldr r2, [pc, #168] ; (8003150 ) 80030a6: 4293 cmp r3, r2 80030a8: d045 beq.n 8003136 80030aa: 687b ldr r3, [r7, #4] 80030ac: 681b ldr r3, [r3, #0] 80030ae: 4a29 ldr r2, [pc, #164] ; (8003154 ) 80030b0: 4293 cmp r3, r2 80030b2: d040 beq.n 8003136 80030b4: 687b ldr r3, [r7, #4] 80030b6: 681b ldr r3, [r3, #0] 80030b8: 4a27 ldr r2, [pc, #156] ; (8003158 ) 80030ba: 4293 cmp r3, r2 80030bc: d03b beq.n 8003136 80030be: 687b ldr r3, [r7, #4] 80030c0: 681b ldr r3, [r3, #0] 80030c2: 4a26 ldr r2, [pc, #152] ; (800315c ) 80030c4: 4293 cmp r3, r2 80030c6: d036 beq.n 8003136 80030c8: 687b ldr r3, [r7, #4] 80030ca: 681b ldr r3, [r3, #0] 80030cc: 4a24 ldr r2, [pc, #144] ; (8003160 ) 80030ce: 4293 cmp r3, r2 80030d0: d031 beq.n 8003136 80030d2: 687b ldr r3, [r7, #4] 80030d4: 681b ldr r3, [r3, #0] 80030d6: 4a23 ldr r2, [pc, #140] ; (8003164 ) 80030d8: 4293 cmp r3, r2 80030da: d02c beq.n 8003136 80030dc: 687b ldr r3, [r7, #4] 80030de: 681b ldr r3, [r3, #0] 80030e0: 4a21 ldr r2, [pc, #132] ; (8003168 ) 80030e2: 4293 cmp r3, r2 80030e4: d027 beq.n 8003136 80030e6: 687b ldr r3, [r7, #4] 80030e8: 681b ldr r3, [r3, #0] 80030ea: 4a20 ldr r2, [pc, #128] ; (800316c ) 80030ec: 4293 cmp r3, r2 80030ee: d022 beq.n 8003136 80030f0: 687b ldr r3, [r7, #4] 80030f2: 681b ldr r3, [r3, #0] 80030f4: 4a1e ldr r2, [pc, #120] ; (8003170 ) 80030f6: 4293 cmp r3, r2 80030f8: d01d beq.n 8003136 80030fa: 687b ldr r3, [r7, #4] 80030fc: 681b ldr r3, [r3, #0] 80030fe: 4a1d ldr r2, [pc, #116] ; (8003174 ) 8003100: 4293 cmp r3, r2 8003102: d018 beq.n 8003136 8003104: 687b ldr r3, [r7, #4] 8003106: 681b ldr r3, [r3, #0] 8003108: 4a1b ldr r2, [pc, #108] ; (8003178 ) 800310a: 4293 cmp r3, r2 800310c: d013 beq.n 8003136 800310e: 687b ldr r3, [r7, #4] 8003110: 681b ldr r3, [r3, #0] 8003112: 4a1a ldr r2, [pc, #104] ; (800317c ) 8003114: 4293 cmp r3, r2 8003116: d00e beq.n 8003136 8003118: 687b ldr r3, [r7, #4] 800311a: 681b ldr r3, [r3, #0] 800311c: 4a18 ldr r2, [pc, #96] ; (8003180 ) 800311e: 4293 cmp r3, r2 8003120: d009 beq.n 8003136 8003122: 687b ldr r3, [r7, #4] 8003124: 681b ldr r3, [r3, #0] 8003126: 4a17 ldr r2, [pc, #92] ; (8003184 ) 8003128: 4293 cmp r3, r2 800312a: d004 beq.n 8003136 800312c: 687b ldr r3, [r7, #4] 800312e: 681b ldr r3, [r3, #0] 8003130: 4a15 ldr r2, [pc, #84] ; (8003188 ) 8003132: 4293 cmp r3, r2 8003134: d12a bne.n 800318c 8003136: 687b ldr r3, [r7, #4] 8003138: 681b ldr r3, [r3, #0] 800313a: 681b ldr r3, [r3, #0] 800313c: f003 0302 and.w r3, r3, #2 8003140: 2b00 cmp r3, #0 8003142: bf14 ite ne 8003144: 2301 movne r3, #1 8003146: 2300 moveq r3, #0 8003148: b2db uxtb r3, r3 800314a: e023 b.n 8003194 800314c: 40020010 .word 0x40020010 8003150: 40020028 .word 0x40020028 8003154: 40020040 .word 0x40020040 8003158: 40020058 .word 0x40020058 800315c: 40020070 .word 0x40020070 8003160: 40020088 .word 0x40020088 8003164: 400200a0 .word 0x400200a0 8003168: 400200b8 .word 0x400200b8 800316c: 40020410 .word 0x40020410 8003170: 40020428 .word 0x40020428 8003174: 40020440 .word 0x40020440 8003178: 40020458 .word 0x40020458 800317c: 40020470 .word 0x40020470 8003180: 40020488 .word 0x40020488 8003184: 400204a0 .word 0x400204a0 8003188: 400204b8 .word 0x400204b8 800318c: 687b ldr r3, [r7, #4] 800318e: 681b ldr r3, [r3, #0] 8003190: 681b ldr r3, [r3, #0] 8003192: 2300 movs r3, #0 8003194: 2b00 cmp r3, #0 8003196: d00d beq.n 80031b4 { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8003198: 687b ldr r3, [r7, #4] 800319a: 6ddb ldr r3, [r3, #92] ; 0x5c 800319c: f003 031f and.w r3, r3, #31 80031a0: 2204 movs r2, #4 80031a2: 409a lsls r2, r3 80031a4: 6a3b ldr r3, [r7, #32] 80031a6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 80031a8: 687b ldr r3, [r7, #4] 80031aa: 6d5b ldr r3, [r3, #84] ; 0x54 80031ac: f043 0204 orr.w r2, r3, #4 80031b0: 687b ldr r3, [r7, #4] 80031b2: 655a str r2, [r3, #84] ; 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 80031b4: 687b ldr r3, [r7, #4] 80031b6: 6ddb ldr r3, [r3, #92] ; 0x5c 80031b8: f003 031f and.w r3, r3, #31 80031bc: 2210 movs r2, #16 80031be: 409a lsls r2, r3 80031c0: 69bb ldr r3, [r7, #24] 80031c2: 4013 ands r3, r2 80031c4: 2b00 cmp r3, #0 80031c6: f000 80a6 beq.w 8003316 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 80031ca: 687b ldr r3, [r7, #4] 80031cc: 681b ldr r3, [r3, #0] 80031ce: 4a85 ldr r2, [pc, #532] ; (80033e4 ) 80031d0: 4293 cmp r3, r2 80031d2: d04a beq.n 800326a 80031d4: 687b ldr r3, [r7, #4] 80031d6: 681b ldr r3, [r3, #0] 80031d8: 4a83 ldr r2, [pc, #524] ; (80033e8 ) 80031da: 4293 cmp r3, r2 80031dc: d045 beq.n 800326a 80031de: 687b ldr r3, [r7, #4] 80031e0: 681b ldr r3, [r3, #0] 80031e2: 4a82 ldr r2, [pc, #520] ; (80033ec ) 80031e4: 4293 cmp r3, r2 80031e6: d040 beq.n 800326a 80031e8: 687b ldr r3, [r7, #4] 80031ea: 681b ldr r3, [r3, #0] 80031ec: 4a80 ldr r2, [pc, #512] ; (80033f0 ) 80031ee: 4293 cmp r3, r2 80031f0: d03b beq.n 800326a 80031f2: 687b ldr r3, [r7, #4] 80031f4: 681b ldr r3, [r3, #0] 80031f6: 4a7f ldr r2, [pc, #508] ; (80033f4 ) 80031f8: 4293 cmp r3, r2 80031fa: d036 beq.n 800326a 80031fc: 687b ldr r3, [r7, #4] 80031fe: 681b ldr r3, [r3, #0] 8003200: 4a7d ldr r2, [pc, #500] ; (80033f8 ) 8003202: 4293 cmp r3, r2 8003204: d031 beq.n 800326a 8003206: 687b ldr r3, [r7, #4] 8003208: 681b ldr r3, [r3, #0] 800320a: 4a7c ldr r2, [pc, #496] ; (80033fc ) 800320c: 4293 cmp r3, r2 800320e: d02c beq.n 800326a 8003210: 687b ldr r3, [r7, #4] 8003212: 681b ldr r3, [r3, #0] 8003214: 4a7a ldr r2, [pc, #488] ; (8003400 ) 8003216: 4293 cmp r3, r2 8003218: d027 beq.n 800326a 800321a: 687b ldr r3, [r7, #4] 800321c: 681b ldr r3, [r3, #0] 800321e: 4a79 ldr r2, [pc, #484] ; (8003404 ) 8003220: 4293 cmp r3, r2 8003222: d022 beq.n 800326a 8003224: 687b ldr r3, [r7, #4] 8003226: 681b ldr r3, [r3, #0] 8003228: 4a77 ldr r2, [pc, #476] ; (8003408 ) 800322a: 4293 cmp r3, r2 800322c: d01d beq.n 800326a 800322e: 687b ldr r3, [r7, #4] 8003230: 681b ldr r3, [r3, #0] 8003232: 4a76 ldr r2, [pc, #472] ; (800340c ) 8003234: 4293 cmp r3, r2 8003236: d018 beq.n 800326a 8003238: 687b ldr r3, [r7, #4] 800323a: 681b ldr r3, [r3, #0] 800323c: 4a74 ldr r2, [pc, #464] ; (8003410 ) 800323e: 4293 cmp r3, r2 8003240: d013 beq.n 800326a 8003242: 687b ldr r3, [r7, #4] 8003244: 681b ldr r3, [r3, #0] 8003246: 4a73 ldr r2, [pc, #460] ; (8003414 ) 8003248: 4293 cmp r3, r2 800324a: d00e beq.n 800326a 800324c: 687b ldr r3, [r7, #4] 800324e: 681b ldr r3, [r3, #0] 8003250: 4a71 ldr r2, [pc, #452] ; (8003418 ) 8003252: 4293 cmp r3, r2 8003254: d009 beq.n 800326a 8003256: 687b ldr r3, [r7, #4] 8003258: 681b ldr r3, [r3, #0] 800325a: 4a70 ldr r2, [pc, #448] ; (800341c ) 800325c: 4293 cmp r3, r2 800325e: d004 beq.n 800326a 8003260: 687b ldr r3, [r7, #4] 8003262: 681b ldr r3, [r3, #0] 8003264: 4a6e ldr r2, [pc, #440] ; (8003420 ) 8003266: 4293 cmp r3, r2 8003268: d10a bne.n 8003280 800326a: 687b ldr r3, [r7, #4] 800326c: 681b ldr r3, [r3, #0] 800326e: 681b ldr r3, [r3, #0] 8003270: f003 0308 and.w r3, r3, #8 8003274: 2b00 cmp r3, #0 8003276: bf14 ite ne 8003278: 2301 movne r3, #1 800327a: 2300 moveq r3, #0 800327c: b2db uxtb r3, r3 800327e: e009 b.n 8003294 8003280: 687b ldr r3, [r7, #4] 8003282: 681b ldr r3, [r3, #0] 8003284: 681b ldr r3, [r3, #0] 8003286: f003 0304 and.w r3, r3, #4 800328a: 2b00 cmp r3, #0 800328c: bf14 ite ne 800328e: 2301 movne r3, #1 8003290: 2300 moveq r3, #0 8003292: b2db uxtb r3, r3 8003294: 2b00 cmp r3, #0 8003296: d03e beq.n 8003316 { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 8003298: 687b ldr r3, [r7, #4] 800329a: 6ddb ldr r3, [r3, #92] ; 0x5c 800329c: f003 031f and.w r3, r3, #31 80032a0: 2210 movs r2, #16 80032a2: 409a lsls r2, r3 80032a4: 6a3b ldr r3, [r7, #32] 80032a6: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 80032a8: 687b ldr r3, [r7, #4] 80032aa: 681b ldr r3, [r3, #0] 80032ac: 681b ldr r3, [r3, #0] 80032ae: f403 2380 and.w r3, r3, #262144 ; 0x40000 80032b2: 2b00 cmp r3, #0 80032b4: d018 beq.n 80032e8 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 80032b6: 687b ldr r3, [r7, #4] 80032b8: 681b ldr r3, [r3, #0] 80032ba: 681b ldr r3, [r3, #0] 80032bc: f403 2300 and.w r3, r3, #524288 ; 0x80000 80032c0: 2b00 cmp r3, #0 80032c2: d108 bne.n 80032d6 { if(hdma->XferHalfCpltCallback != NULL) 80032c4: 687b ldr r3, [r7, #4] 80032c6: 6c1b ldr r3, [r3, #64] ; 0x40 80032c8: 2b00 cmp r3, #0 80032ca: d024 beq.n 8003316 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 80032cc: 687b ldr r3, [r7, #4] 80032ce: 6c1b ldr r3, [r3, #64] ; 0x40 80032d0: 6878 ldr r0, [r7, #4] 80032d2: 4798 blx r3 80032d4: e01f b.n 8003316 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 80032d6: 687b ldr r3, [r7, #4] 80032d8: 6c9b ldr r3, [r3, #72] ; 0x48 80032da: 2b00 cmp r3, #0 80032dc: d01b beq.n 8003316 { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 80032de: 687b ldr r3, [r7, #4] 80032e0: 6c9b ldr r3, [r3, #72] ; 0x48 80032e2: 6878 ldr r0, [r7, #4] 80032e4: 4798 blx r3 80032e6: e016 b.n 8003316 } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 80032e8: 687b ldr r3, [r7, #4] 80032ea: 681b ldr r3, [r3, #0] 80032ec: 681b ldr r3, [r3, #0] 80032ee: f403 7380 and.w r3, r3, #256 ; 0x100 80032f2: 2b00 cmp r3, #0 80032f4: d107 bne.n 8003306 { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 80032f6: 687b ldr r3, [r7, #4] 80032f8: 681b ldr r3, [r3, #0] 80032fa: 681a ldr r2, [r3, #0] 80032fc: 687b ldr r3, [r7, #4] 80032fe: 681b ldr r3, [r3, #0] 8003300: f022 0208 bic.w r2, r2, #8 8003304: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 8003306: 687b ldr r3, [r7, #4] 8003308: 6c1b ldr r3, [r3, #64] ; 0x40 800330a: 2b00 cmp r3, #0 800330c: d003 beq.n 8003316 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800330e: 687b ldr r3, [r7, #4] 8003310: 6c1b ldr r3, [r3, #64] ; 0x40 8003312: 6878 ldr r0, [r7, #4] 8003314: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003316: 687b ldr r3, [r7, #4] 8003318: 6ddb ldr r3, [r3, #92] ; 0x5c 800331a: f003 031f and.w r3, r3, #31 800331e: 2220 movs r2, #32 8003320: 409a lsls r2, r3 8003322: 69bb ldr r3, [r7, #24] 8003324: 4013 ands r3, r2 8003326: 2b00 cmp r3, #0 8003328: f000 8110 beq.w 800354c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 800332c: 687b ldr r3, [r7, #4] 800332e: 681b ldr r3, [r3, #0] 8003330: 4a2c ldr r2, [pc, #176] ; (80033e4 ) 8003332: 4293 cmp r3, r2 8003334: d04a beq.n 80033cc 8003336: 687b ldr r3, [r7, #4] 8003338: 681b ldr r3, [r3, #0] 800333a: 4a2b ldr r2, [pc, #172] ; (80033e8 ) 800333c: 4293 cmp r3, r2 800333e: d045 beq.n 80033cc 8003340: 687b ldr r3, [r7, #4] 8003342: 681b ldr r3, [r3, #0] 8003344: 4a29 ldr r2, [pc, #164] ; (80033ec ) 8003346: 4293 cmp r3, r2 8003348: d040 beq.n 80033cc 800334a: 687b ldr r3, [r7, #4] 800334c: 681b ldr r3, [r3, #0] 800334e: 4a28 ldr r2, [pc, #160] ; (80033f0 ) 8003350: 4293 cmp r3, r2 8003352: d03b beq.n 80033cc 8003354: 687b ldr r3, [r7, #4] 8003356: 681b ldr r3, [r3, #0] 8003358: 4a26 ldr r2, [pc, #152] ; (80033f4 ) 800335a: 4293 cmp r3, r2 800335c: d036 beq.n 80033cc 800335e: 687b ldr r3, [r7, #4] 8003360: 681b ldr r3, [r3, #0] 8003362: 4a25 ldr r2, [pc, #148] ; (80033f8 ) 8003364: 4293 cmp r3, r2 8003366: d031 beq.n 80033cc 8003368: 687b ldr r3, [r7, #4] 800336a: 681b ldr r3, [r3, #0] 800336c: 4a23 ldr r2, [pc, #140] ; (80033fc ) 800336e: 4293 cmp r3, r2 8003370: d02c beq.n 80033cc 8003372: 687b ldr r3, [r7, #4] 8003374: 681b ldr r3, [r3, #0] 8003376: 4a22 ldr r2, [pc, #136] ; (8003400 ) 8003378: 4293 cmp r3, r2 800337a: d027 beq.n 80033cc 800337c: 687b ldr r3, [r7, #4] 800337e: 681b ldr r3, [r3, #0] 8003380: 4a20 ldr r2, [pc, #128] ; (8003404 ) 8003382: 4293 cmp r3, r2 8003384: d022 beq.n 80033cc 8003386: 687b ldr r3, [r7, #4] 8003388: 681b ldr r3, [r3, #0] 800338a: 4a1f ldr r2, [pc, #124] ; (8003408 ) 800338c: 4293 cmp r3, r2 800338e: d01d beq.n 80033cc 8003390: 687b ldr r3, [r7, #4] 8003392: 681b ldr r3, [r3, #0] 8003394: 4a1d ldr r2, [pc, #116] ; (800340c ) 8003396: 4293 cmp r3, r2 8003398: d018 beq.n 80033cc 800339a: 687b ldr r3, [r7, #4] 800339c: 681b ldr r3, [r3, #0] 800339e: 4a1c ldr r2, [pc, #112] ; (8003410 ) 80033a0: 4293 cmp r3, r2 80033a2: d013 beq.n 80033cc 80033a4: 687b ldr r3, [r7, #4] 80033a6: 681b ldr r3, [r3, #0] 80033a8: 4a1a ldr r2, [pc, #104] ; (8003414 ) 80033aa: 4293 cmp r3, r2 80033ac: d00e beq.n 80033cc 80033ae: 687b ldr r3, [r7, #4] 80033b0: 681b ldr r3, [r3, #0] 80033b2: 4a19 ldr r2, [pc, #100] ; (8003418 ) 80033b4: 4293 cmp r3, r2 80033b6: d009 beq.n 80033cc 80033b8: 687b ldr r3, [r7, #4] 80033ba: 681b ldr r3, [r3, #0] 80033bc: 4a17 ldr r2, [pc, #92] ; (800341c ) 80033be: 4293 cmp r3, r2 80033c0: d004 beq.n 80033cc 80033c2: 687b ldr r3, [r7, #4] 80033c4: 681b ldr r3, [r3, #0] 80033c6: 4a16 ldr r2, [pc, #88] ; (8003420 ) 80033c8: 4293 cmp r3, r2 80033ca: d12b bne.n 8003424 80033cc: 687b ldr r3, [r7, #4] 80033ce: 681b ldr r3, [r3, #0] 80033d0: 681b ldr r3, [r3, #0] 80033d2: f003 0310 and.w r3, r3, #16 80033d6: 2b00 cmp r3, #0 80033d8: bf14 ite ne 80033da: 2301 movne r3, #1 80033dc: 2300 moveq r3, #0 80033de: b2db uxtb r3, r3 80033e0: e02a b.n 8003438 80033e2: bf00 nop 80033e4: 40020010 .word 0x40020010 80033e8: 40020028 .word 0x40020028 80033ec: 40020040 .word 0x40020040 80033f0: 40020058 .word 0x40020058 80033f4: 40020070 .word 0x40020070 80033f8: 40020088 .word 0x40020088 80033fc: 400200a0 .word 0x400200a0 8003400: 400200b8 .word 0x400200b8 8003404: 40020410 .word 0x40020410 8003408: 40020428 .word 0x40020428 800340c: 40020440 .word 0x40020440 8003410: 40020458 .word 0x40020458 8003414: 40020470 .word 0x40020470 8003418: 40020488 .word 0x40020488 800341c: 400204a0 .word 0x400204a0 8003420: 400204b8 .word 0x400204b8 8003424: 687b ldr r3, [r7, #4] 8003426: 681b ldr r3, [r3, #0] 8003428: 681b ldr r3, [r3, #0] 800342a: f003 0302 and.w r3, r3, #2 800342e: 2b00 cmp r3, #0 8003430: bf14 ite ne 8003432: 2301 movne r3, #1 8003434: 2300 moveq r3, #0 8003436: b2db uxtb r3, r3 8003438: 2b00 cmp r3, #0 800343a: f000 8087 beq.w 800354c { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 800343e: 687b ldr r3, [r7, #4] 8003440: 6ddb ldr r3, [r3, #92] ; 0x5c 8003442: f003 031f and.w r3, r3, #31 8003446: 2220 movs r2, #32 8003448: 409a lsls r2, r3 800344a: 6a3b ldr r3, [r7, #32] 800344c: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 800344e: 687b ldr r3, [r7, #4] 8003450: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 8003454: b2db uxtb r3, r3 8003456: 2b04 cmp r3, #4 8003458: d139 bne.n 80034ce { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800345a: 687b ldr r3, [r7, #4] 800345c: 681b ldr r3, [r3, #0] 800345e: 681a ldr r2, [r3, #0] 8003460: 687b ldr r3, [r7, #4] 8003462: 681b ldr r3, [r3, #0] 8003464: f022 0216 bic.w r2, r2, #22 8003468: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800346a: 687b ldr r3, [r7, #4] 800346c: 681b ldr r3, [r3, #0] 800346e: 695a ldr r2, [r3, #20] 8003470: 687b ldr r3, [r7, #4] 8003472: 681b ldr r3, [r3, #0] 8003474: f022 0280 bic.w r2, r2, #128 ; 0x80 8003478: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800347a: 687b ldr r3, [r7, #4] 800347c: 6c1b ldr r3, [r3, #64] ; 0x40 800347e: 2b00 cmp r3, #0 8003480: d103 bne.n 800348a 8003482: 687b ldr r3, [r7, #4] 8003484: 6c9b ldr r3, [r3, #72] ; 0x48 8003486: 2b00 cmp r3, #0 8003488: d007 beq.n 800349a { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800348a: 687b ldr r3, [r7, #4] 800348c: 681b ldr r3, [r3, #0] 800348e: 681a ldr r2, [r3, #0] 8003490: 687b ldr r3, [r7, #4] 8003492: 681b ldr r3, [r3, #0] 8003494: f022 0208 bic.w r2, r2, #8 8003498: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800349a: 687b ldr r3, [r7, #4] 800349c: 6ddb ldr r3, [r3, #92] ; 0x5c 800349e: f003 031f and.w r3, r3, #31 80034a2: 223f movs r2, #63 ; 0x3f 80034a4: 409a lsls r2, r3 80034a6: 6a3b ldr r3, [r7, #32] 80034a8: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80034aa: 687b ldr r3, [r7, #4] 80034ac: 2201 movs r2, #1 80034ae: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80034b2: 687b ldr r3, [r7, #4] 80034b4: 2200 movs r2, #0 80034b6: f883 2034 strb.w r2, [r3, #52] ; 0x34 if(hdma->XferAbortCallback != NULL) 80034ba: 687b ldr r3, [r7, #4] 80034bc: 6d1b ldr r3, [r3, #80] ; 0x50 80034be: 2b00 cmp r3, #0 80034c0: f000 834a beq.w 8003b58 { hdma->XferAbortCallback(hdma); 80034c4: 687b ldr r3, [r7, #4] 80034c6: 6d1b ldr r3, [r3, #80] ; 0x50 80034c8: 6878 ldr r0, [r7, #4] 80034ca: 4798 blx r3 } return; 80034cc: e344 b.n 8003b58 } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 80034ce: 687b ldr r3, [r7, #4] 80034d0: 681b ldr r3, [r3, #0] 80034d2: 681b ldr r3, [r3, #0] 80034d4: f403 2380 and.w r3, r3, #262144 ; 0x40000 80034d8: 2b00 cmp r3, #0 80034da: d018 beq.n 800350e { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 80034dc: 687b ldr r3, [r7, #4] 80034de: 681b ldr r3, [r3, #0] 80034e0: 681b ldr r3, [r3, #0] 80034e2: f403 2300 and.w r3, r3, #524288 ; 0x80000 80034e6: 2b00 cmp r3, #0 80034e8: d108 bne.n 80034fc { if(hdma->XferM1CpltCallback != NULL) 80034ea: 687b ldr r3, [r7, #4] 80034ec: 6c5b ldr r3, [r3, #68] ; 0x44 80034ee: 2b00 cmp r3, #0 80034f0: d02c beq.n 800354c { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 80034f2: 687b ldr r3, [r7, #4] 80034f4: 6c5b ldr r3, [r3, #68] ; 0x44 80034f6: 6878 ldr r0, [r7, #4] 80034f8: 4798 blx r3 80034fa: e027 b.n 800354c } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 80034fc: 687b ldr r3, [r7, #4] 80034fe: 6bdb ldr r3, [r3, #60] ; 0x3c 8003500: 2b00 cmp r3, #0 8003502: d023 beq.n 800354c { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8003504: 687b ldr r3, [r7, #4] 8003506: 6bdb ldr r3, [r3, #60] ; 0x3c 8003508: 6878 ldr r0, [r7, #4] 800350a: 4798 blx r3 800350c: e01e b.n 800354c } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800350e: 687b ldr r3, [r7, #4] 8003510: 681b ldr r3, [r3, #0] 8003512: 681b ldr r3, [r3, #0] 8003514: f403 7380 and.w r3, r3, #256 ; 0x100 8003518: 2b00 cmp r3, #0 800351a: d10f bne.n 800353c { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 800351c: 687b ldr r3, [r7, #4] 800351e: 681b ldr r3, [r3, #0] 8003520: 681a ldr r2, [r3, #0] 8003522: 687b ldr r3, [r7, #4] 8003524: 681b ldr r3, [r3, #0] 8003526: f022 0210 bic.w r2, r2, #16 800352a: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800352c: 687b ldr r3, [r7, #4] 800352e: 2201 movs r2, #1 8003530: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003534: 687b ldr r3, [r7, #4] 8003536: 2200 movs r2, #0 8003538: f883 2034 strb.w r2, [r3, #52] ; 0x34 } if(hdma->XferCpltCallback != NULL) 800353c: 687b ldr r3, [r7, #4] 800353e: 6bdb ldr r3, [r3, #60] ; 0x3c 8003540: 2b00 cmp r3, #0 8003542: d003 beq.n 800354c { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8003544: 687b ldr r3, [r7, #4] 8003546: 6bdb ldr r3, [r3, #60] ; 0x3c 8003548: 6878 ldr r0, [r7, #4] 800354a: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800354c: 687b ldr r3, [r7, #4] 800354e: 6d5b ldr r3, [r3, #84] ; 0x54 8003550: 2b00 cmp r3, #0 8003552: f000 8306 beq.w 8003b62 { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 8003556: 687b ldr r3, [r7, #4] 8003558: 6d5b ldr r3, [r3, #84] ; 0x54 800355a: f003 0301 and.w r3, r3, #1 800355e: 2b00 cmp r3, #0 8003560: f000 8088 beq.w 8003674 { hdma->State = HAL_DMA_STATE_ABORT; 8003564: 687b ldr r3, [r7, #4] 8003566: 2204 movs r2, #4 8003568: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800356c: 687b ldr r3, [r7, #4] 800356e: 681b ldr r3, [r3, #0] 8003570: 4a7a ldr r2, [pc, #488] ; (800375c ) 8003572: 4293 cmp r3, r2 8003574: d04a beq.n 800360c 8003576: 687b ldr r3, [r7, #4] 8003578: 681b ldr r3, [r3, #0] 800357a: 4a79 ldr r2, [pc, #484] ; (8003760 ) 800357c: 4293 cmp r3, r2 800357e: d045 beq.n 800360c 8003580: 687b ldr r3, [r7, #4] 8003582: 681b ldr r3, [r3, #0] 8003584: 4a77 ldr r2, [pc, #476] ; (8003764 ) 8003586: 4293 cmp r3, r2 8003588: d040 beq.n 800360c 800358a: 687b ldr r3, [r7, #4] 800358c: 681b ldr r3, [r3, #0] 800358e: 4a76 ldr r2, [pc, #472] ; (8003768 ) 8003590: 4293 cmp r3, r2 8003592: d03b beq.n 800360c 8003594: 687b ldr r3, [r7, #4] 8003596: 681b ldr r3, [r3, #0] 8003598: 4a74 ldr r2, [pc, #464] ; (800376c ) 800359a: 4293 cmp r3, r2 800359c: d036 beq.n 800360c 800359e: 687b ldr r3, [r7, #4] 80035a0: 681b ldr r3, [r3, #0] 80035a2: 4a73 ldr r2, [pc, #460] ; (8003770 ) 80035a4: 4293 cmp r3, r2 80035a6: d031 beq.n 800360c 80035a8: 687b ldr r3, [r7, #4] 80035aa: 681b ldr r3, [r3, #0] 80035ac: 4a71 ldr r2, [pc, #452] ; (8003774 ) 80035ae: 4293 cmp r3, r2 80035b0: d02c beq.n 800360c 80035b2: 687b ldr r3, [r7, #4] 80035b4: 681b ldr r3, [r3, #0] 80035b6: 4a70 ldr r2, [pc, #448] ; (8003778 ) 80035b8: 4293 cmp r3, r2 80035ba: d027 beq.n 800360c 80035bc: 687b ldr r3, [r7, #4] 80035be: 681b ldr r3, [r3, #0] 80035c0: 4a6e ldr r2, [pc, #440] ; (800377c ) 80035c2: 4293 cmp r3, r2 80035c4: d022 beq.n 800360c 80035c6: 687b ldr r3, [r7, #4] 80035c8: 681b ldr r3, [r3, #0] 80035ca: 4a6d ldr r2, [pc, #436] ; (8003780 ) 80035cc: 4293 cmp r3, r2 80035ce: d01d beq.n 800360c 80035d0: 687b ldr r3, [r7, #4] 80035d2: 681b ldr r3, [r3, #0] 80035d4: 4a6b ldr r2, [pc, #428] ; (8003784 ) 80035d6: 4293 cmp r3, r2 80035d8: d018 beq.n 800360c 80035da: 687b ldr r3, [r7, #4] 80035dc: 681b ldr r3, [r3, #0] 80035de: 4a6a ldr r2, [pc, #424] ; (8003788 ) 80035e0: 4293 cmp r3, r2 80035e2: d013 beq.n 800360c 80035e4: 687b ldr r3, [r7, #4] 80035e6: 681b ldr r3, [r3, #0] 80035e8: 4a68 ldr r2, [pc, #416] ; (800378c ) 80035ea: 4293 cmp r3, r2 80035ec: d00e beq.n 800360c 80035ee: 687b ldr r3, [r7, #4] 80035f0: 681b ldr r3, [r3, #0] 80035f2: 4a67 ldr r2, [pc, #412] ; (8003790 ) 80035f4: 4293 cmp r3, r2 80035f6: d009 beq.n 800360c 80035f8: 687b ldr r3, [r7, #4] 80035fa: 681b ldr r3, [r3, #0] 80035fc: 4a65 ldr r2, [pc, #404] ; (8003794 ) 80035fe: 4293 cmp r3, r2 8003600: d004 beq.n 800360c 8003602: 687b ldr r3, [r7, #4] 8003604: 681b ldr r3, [r3, #0] 8003606: 4a64 ldr r2, [pc, #400] ; (8003798 ) 8003608: 4293 cmp r3, r2 800360a: d108 bne.n 800361e 800360c: 687b ldr r3, [r7, #4] 800360e: 681b ldr r3, [r3, #0] 8003610: 681a ldr r2, [r3, #0] 8003612: 687b ldr r3, [r7, #4] 8003614: 681b ldr r3, [r3, #0] 8003616: f022 0201 bic.w r2, r2, #1 800361a: 601a str r2, [r3, #0] 800361c: e007 b.n 800362e 800361e: 687b ldr r3, [r7, #4] 8003620: 681b ldr r3, [r3, #0] 8003622: 681a ldr r2, [r3, #0] 8003624: 687b ldr r3, [r7, #4] 8003626: 681b ldr r3, [r3, #0] 8003628: f022 0201 bic.w r2, r2, #1 800362c: 601a str r2, [r3, #0] do { if (++count > timeout) 800362e: 68fb ldr r3, [r7, #12] 8003630: 3301 adds r3, #1 8003632: 60fb str r3, [r7, #12] 8003634: 6a7a ldr r2, [r7, #36] ; 0x24 8003636: 429a cmp r2, r3 8003638: d307 bcc.n 800364a { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 800363a: 687b ldr r3, [r7, #4] 800363c: 681b ldr r3, [r3, #0] 800363e: 681b ldr r3, [r3, #0] 8003640: f003 0301 and.w r3, r3, #1 8003644: 2b00 cmp r3, #0 8003646: d1f2 bne.n 800362e 8003648: e000 b.n 800364c break; 800364a: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800364c: 687b ldr r3, [r7, #4] 800364e: 681b ldr r3, [r3, #0] 8003650: 681b ldr r3, [r3, #0] 8003652: f003 0301 and.w r3, r3, #1 8003656: 2b00 cmp r3, #0 8003658: d004 beq.n 8003664 { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 800365a: 687b ldr r3, [r7, #4] 800365c: 2203 movs r2, #3 800365e: f883 2035 strb.w r2, [r3, #53] ; 0x35 8003662: e003 b.n 800366c } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 8003664: 687b ldr r3, [r7, #4] 8003666: 2201 movs r2, #1 8003668: f883 2035 strb.w r2, [r3, #53] ; 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 800366c: 687b ldr r3, [r7, #4] 800366e: 2200 movs r2, #0 8003670: f883 2034 strb.w r2, [r3, #52] ; 0x34 } if(hdma->XferErrorCallback != NULL) 8003674: 687b ldr r3, [r7, #4] 8003676: 6cdb ldr r3, [r3, #76] ; 0x4c 8003678: 2b00 cmp r3, #0 800367a: f000 8272 beq.w 8003b62 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800367e: 687b ldr r3, [r7, #4] 8003680: 6cdb ldr r3, [r3, #76] ; 0x4c 8003682: 6878 ldr r0, [r7, #4] 8003684: 4798 blx r3 8003686: e26c b.n 8003b62 } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8003688: 687b ldr r3, [r7, #4] 800368a: 681b ldr r3, [r3, #0] 800368c: 4a43 ldr r2, [pc, #268] ; (800379c ) 800368e: 4293 cmp r3, r2 8003690: d022 beq.n 80036d8 8003692: 687b ldr r3, [r7, #4] 8003694: 681b ldr r3, [r3, #0] 8003696: 4a42 ldr r2, [pc, #264] ; (80037a0 ) 8003698: 4293 cmp r3, r2 800369a: d01d beq.n 80036d8 800369c: 687b ldr r3, [r7, #4] 800369e: 681b ldr r3, [r3, #0] 80036a0: 4a40 ldr r2, [pc, #256] ; (80037a4 ) 80036a2: 4293 cmp r3, r2 80036a4: d018 beq.n 80036d8 80036a6: 687b ldr r3, [r7, #4] 80036a8: 681b ldr r3, [r3, #0] 80036aa: 4a3f ldr r2, [pc, #252] ; (80037a8 ) 80036ac: 4293 cmp r3, r2 80036ae: d013 beq.n 80036d8 80036b0: 687b ldr r3, [r7, #4] 80036b2: 681b ldr r3, [r3, #0] 80036b4: 4a3d ldr r2, [pc, #244] ; (80037ac ) 80036b6: 4293 cmp r3, r2 80036b8: d00e beq.n 80036d8 80036ba: 687b ldr r3, [r7, #4] 80036bc: 681b ldr r3, [r3, #0] 80036be: 4a3c ldr r2, [pc, #240] ; (80037b0 ) 80036c0: 4293 cmp r3, r2 80036c2: d009 beq.n 80036d8 80036c4: 687b ldr r3, [r7, #4] 80036c6: 681b ldr r3, [r3, #0] 80036c8: 4a3a ldr r2, [pc, #232] ; (80037b4 ) 80036ca: 4293 cmp r3, r2 80036cc: d004 beq.n 80036d8 80036ce: 687b ldr r3, [r7, #4] 80036d0: 681b ldr r3, [r3, #0] 80036d2: 4a39 ldr r2, [pc, #228] ; (80037b8 ) 80036d4: 4293 cmp r3, r2 80036d6: d101 bne.n 80036dc 80036d8: 2301 movs r3, #1 80036da: e000 b.n 80036de 80036dc: 2300 movs r3, #0 80036de: 2b00 cmp r3, #0 80036e0: f000 823f beq.w 8003b62 { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 80036e4: 687b ldr r3, [r7, #4] 80036e6: 681b ldr r3, [r3, #0] 80036e8: 681b ldr r3, [r3, #0] 80036ea: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 80036ec: 687b ldr r3, [r7, #4] 80036ee: 6ddb ldr r3, [r3, #92] ; 0x5c 80036f0: f003 031f and.w r3, r3, #31 80036f4: 2204 movs r2, #4 80036f6: 409a lsls r2, r3 80036f8: 697b ldr r3, [r7, #20] 80036fa: 4013 ands r3, r2 80036fc: 2b00 cmp r3, #0 80036fe: f000 80cd beq.w 800389c 8003702: 693b ldr r3, [r7, #16] 8003704: f003 0304 and.w r3, r3, #4 8003708: 2b00 cmp r3, #0 800370a: f000 80c7 beq.w 800389c { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 800370e: 687b ldr r3, [r7, #4] 8003710: 6ddb ldr r3, [r3, #92] ; 0x5c 8003712: f003 031f and.w r3, r3, #31 8003716: 2204 movs r2, #4 8003718: 409a lsls r2, r3 800371a: 69fb ldr r3, [r7, #28] 800371c: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800371e: 693b ldr r3, [r7, #16] 8003720: f403 4300 and.w r3, r3, #32768 ; 0x8000 8003724: 2b00 cmp r3, #0 8003726: d049 beq.n 80037bc { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 8003728: 693b ldr r3, [r7, #16] 800372a: f403 3380 and.w r3, r3, #65536 ; 0x10000 800372e: 2b00 cmp r3, #0 8003730: d109 bne.n 8003746 { if(hdma->XferM1HalfCpltCallback != NULL) 8003732: 687b ldr r3, [r7, #4] 8003734: 6c9b ldr r3, [r3, #72] ; 0x48 8003736: 2b00 cmp r3, #0 8003738: f000 8210 beq.w 8003b5c { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 800373c: 687b ldr r3, [r7, #4] 800373e: 6c9b ldr r3, [r3, #72] ; 0x48 8003740: 6878 ldr r0, [r7, #4] 8003742: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8003744: e20a b.n 8003b5c } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 8003746: 687b ldr r3, [r7, #4] 8003748: 6c1b ldr r3, [r3, #64] ; 0x40 800374a: 2b00 cmp r3, #0 800374c: f000 8206 beq.w 8003b5c { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 8003750: 687b ldr r3, [r7, #4] 8003752: 6c1b ldr r3, [r3, #64] ; 0x40 8003754: 6878 ldr r0, [r7, #4] 8003756: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8003758: e200 b.n 8003b5c 800375a: bf00 nop 800375c: 40020010 .word 0x40020010 8003760: 40020028 .word 0x40020028 8003764: 40020040 .word 0x40020040 8003768: 40020058 .word 0x40020058 800376c: 40020070 .word 0x40020070 8003770: 40020088 .word 0x40020088 8003774: 400200a0 .word 0x400200a0 8003778: 400200b8 .word 0x400200b8 800377c: 40020410 .word 0x40020410 8003780: 40020428 .word 0x40020428 8003784: 40020440 .word 0x40020440 8003788: 40020458 .word 0x40020458 800378c: 40020470 .word 0x40020470 8003790: 40020488 .word 0x40020488 8003794: 400204a0 .word 0x400204a0 8003798: 400204b8 .word 0x400204b8 800379c: 58025408 .word 0x58025408 80037a0: 5802541c .word 0x5802541c 80037a4: 58025430 .word 0x58025430 80037a8: 58025444 .word 0x58025444 80037ac: 58025458 .word 0x58025458 80037b0: 5802546c .word 0x5802546c 80037b4: 58025480 .word 0x58025480 80037b8: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 80037bc: 693b ldr r3, [r7, #16] 80037be: f003 0320 and.w r3, r3, #32 80037c2: 2b00 cmp r3, #0 80037c4: d160 bne.n 8003888 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 80037c6: 687b ldr r3, [r7, #4] 80037c8: 681b ldr r3, [r3, #0] 80037ca: 4a7f ldr r2, [pc, #508] ; (80039c8 ) 80037cc: 4293 cmp r3, r2 80037ce: d04a beq.n 8003866 80037d0: 687b ldr r3, [r7, #4] 80037d2: 681b ldr r3, [r3, #0] 80037d4: 4a7d ldr r2, [pc, #500] ; (80039cc ) 80037d6: 4293 cmp r3, r2 80037d8: d045 beq.n 8003866 80037da: 687b ldr r3, [r7, #4] 80037dc: 681b ldr r3, [r3, #0] 80037de: 4a7c ldr r2, [pc, #496] ; (80039d0 ) 80037e0: 4293 cmp r3, r2 80037e2: d040 beq.n 8003866 80037e4: 687b ldr r3, [r7, #4] 80037e6: 681b ldr r3, [r3, #0] 80037e8: 4a7a ldr r2, [pc, #488] ; (80039d4 ) 80037ea: 4293 cmp r3, r2 80037ec: d03b beq.n 8003866 80037ee: 687b ldr r3, [r7, #4] 80037f0: 681b ldr r3, [r3, #0] 80037f2: 4a79 ldr r2, [pc, #484] ; (80039d8 ) 80037f4: 4293 cmp r3, r2 80037f6: d036 beq.n 8003866 80037f8: 687b ldr r3, [r7, #4] 80037fa: 681b ldr r3, [r3, #0] 80037fc: 4a77 ldr r2, [pc, #476] ; (80039dc ) 80037fe: 4293 cmp r3, r2 8003800: d031 beq.n 8003866 8003802: 687b ldr r3, [r7, #4] 8003804: 681b ldr r3, [r3, #0] 8003806: 4a76 ldr r2, [pc, #472] ; (80039e0 ) 8003808: 4293 cmp r3, r2 800380a: d02c beq.n 8003866 800380c: 687b ldr r3, [r7, #4] 800380e: 681b ldr r3, [r3, #0] 8003810: 4a74 ldr r2, [pc, #464] ; (80039e4 ) 8003812: 4293 cmp r3, r2 8003814: d027 beq.n 8003866 8003816: 687b ldr r3, [r7, #4] 8003818: 681b ldr r3, [r3, #0] 800381a: 4a73 ldr r2, [pc, #460] ; (80039e8 ) 800381c: 4293 cmp r3, r2 800381e: d022 beq.n 8003866 8003820: 687b ldr r3, [r7, #4] 8003822: 681b ldr r3, [r3, #0] 8003824: 4a71 ldr r2, [pc, #452] ; (80039ec ) 8003826: 4293 cmp r3, r2 8003828: d01d beq.n 8003866 800382a: 687b ldr r3, [r7, #4] 800382c: 681b ldr r3, [r3, #0] 800382e: 4a70 ldr r2, [pc, #448] ; (80039f0 ) 8003830: 4293 cmp r3, r2 8003832: d018 beq.n 8003866 8003834: 687b ldr r3, [r7, #4] 8003836: 681b ldr r3, [r3, #0] 8003838: 4a6e ldr r2, [pc, #440] ; (80039f4 ) 800383a: 4293 cmp r3, r2 800383c: d013 beq.n 8003866 800383e: 687b ldr r3, [r7, #4] 8003840: 681b ldr r3, [r3, #0] 8003842: 4a6d ldr r2, [pc, #436] ; (80039f8 ) 8003844: 4293 cmp r3, r2 8003846: d00e beq.n 8003866 8003848: 687b ldr r3, [r7, #4] 800384a: 681b ldr r3, [r3, #0] 800384c: 4a6b ldr r2, [pc, #428] ; (80039fc ) 800384e: 4293 cmp r3, r2 8003850: d009 beq.n 8003866 8003852: 687b ldr r3, [r7, #4] 8003854: 681b ldr r3, [r3, #0] 8003856: 4a6a ldr r2, [pc, #424] ; (8003a00 ) 8003858: 4293 cmp r3, r2 800385a: d004 beq.n 8003866 800385c: 687b ldr r3, [r7, #4] 800385e: 681b ldr r3, [r3, #0] 8003860: 4a68 ldr r2, [pc, #416] ; (8003a04 ) 8003862: 4293 cmp r3, r2 8003864: d108 bne.n 8003878 8003866: 687b ldr r3, [r7, #4] 8003868: 681b ldr r3, [r3, #0] 800386a: 681a ldr r2, [r3, #0] 800386c: 687b ldr r3, [r7, #4] 800386e: 681b ldr r3, [r3, #0] 8003870: f022 0208 bic.w r2, r2, #8 8003874: 601a str r2, [r3, #0] 8003876: e007 b.n 8003888 8003878: 687b ldr r3, [r7, #4] 800387a: 681b ldr r3, [r3, #0] 800387c: 681a ldr r2, [r3, #0] 800387e: 687b ldr r3, [r7, #4] 8003880: 681b ldr r3, [r3, #0] 8003882: f022 0204 bic.w r2, r2, #4 8003886: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8003888: 687b ldr r3, [r7, #4] 800388a: 6c1b ldr r3, [r3, #64] ; 0x40 800388c: 2b00 cmp r3, #0 800388e: f000 8165 beq.w 8003b5c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8003892: 687b ldr r3, [r7, #4] 8003894: 6c1b ldr r3, [r3, #64] ; 0x40 8003896: 6878 ldr r0, [r7, #4] 8003898: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800389a: e15f b.n 8003b5c } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 800389c: 687b ldr r3, [r7, #4] 800389e: 6ddb ldr r3, [r3, #92] ; 0x5c 80038a0: f003 031f and.w r3, r3, #31 80038a4: 2202 movs r2, #2 80038a6: 409a lsls r2, r3 80038a8: 697b ldr r3, [r7, #20] 80038aa: 4013 ands r3, r2 80038ac: 2b00 cmp r3, #0 80038ae: f000 80c5 beq.w 8003a3c 80038b2: 693b ldr r3, [r7, #16] 80038b4: f003 0302 and.w r3, r3, #2 80038b8: 2b00 cmp r3, #0 80038ba: f000 80bf beq.w 8003a3c { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 80038be: 687b ldr r3, [r7, #4] 80038c0: 6ddb ldr r3, [r3, #92] ; 0x5c 80038c2: f003 031f and.w r3, r3, #31 80038c6: 2202 movs r2, #2 80038c8: 409a lsls r2, r3 80038ca: 69fb ldr r3, [r7, #28] 80038cc: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 80038ce: 693b ldr r3, [r7, #16] 80038d0: f403 4300 and.w r3, r3, #32768 ; 0x8000 80038d4: 2b00 cmp r3, #0 80038d6: d018 beq.n 800390a { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 80038d8: 693b ldr r3, [r7, #16] 80038da: f403 3380 and.w r3, r3, #65536 ; 0x10000 80038de: 2b00 cmp r3, #0 80038e0: d109 bne.n 80038f6 { if(hdma->XferM1CpltCallback != NULL) 80038e2: 687b ldr r3, [r7, #4] 80038e4: 6c5b ldr r3, [r3, #68] ; 0x44 80038e6: 2b00 cmp r3, #0 80038e8: f000 813a beq.w 8003b60 { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 80038ec: 687b ldr r3, [r7, #4] 80038ee: 6c5b ldr r3, [r3, #68] ; 0x44 80038f0: 6878 ldr r0, [r7, #4] 80038f2: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 80038f4: e134 b.n 8003b60 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 80038f6: 687b ldr r3, [r7, #4] 80038f8: 6bdb ldr r3, [r3, #60] ; 0x3c 80038fa: 2b00 cmp r3, #0 80038fc: f000 8130 beq.w 8003b60 { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 8003900: 687b ldr r3, [r7, #4] 8003902: 6bdb ldr r3, [r3, #60] ; 0x3c 8003904: 6878 ldr r0, [r7, #4] 8003906: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8003908: e12a b.n 8003b60 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800390a: 693b ldr r3, [r7, #16] 800390c: f003 0320 and.w r3, r3, #32 8003910: 2b00 cmp r3, #0 8003912: f040 8089 bne.w 8003a28 { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8003916: 687b ldr r3, [r7, #4] 8003918: 681b ldr r3, [r3, #0] 800391a: 4a2b ldr r2, [pc, #172] ; (80039c8 ) 800391c: 4293 cmp r3, r2 800391e: d04a beq.n 80039b6 8003920: 687b ldr r3, [r7, #4] 8003922: 681b ldr r3, [r3, #0] 8003924: 4a29 ldr r2, [pc, #164] ; (80039cc ) 8003926: 4293 cmp r3, r2 8003928: d045 beq.n 80039b6 800392a: 687b ldr r3, [r7, #4] 800392c: 681b ldr r3, [r3, #0] 800392e: 4a28 ldr r2, [pc, #160] ; (80039d0 ) 8003930: 4293 cmp r3, r2 8003932: d040 beq.n 80039b6 8003934: 687b ldr r3, [r7, #4] 8003936: 681b ldr r3, [r3, #0] 8003938: 4a26 ldr r2, [pc, #152] ; (80039d4 ) 800393a: 4293 cmp r3, r2 800393c: d03b beq.n 80039b6 800393e: 687b ldr r3, [r7, #4] 8003940: 681b ldr r3, [r3, #0] 8003942: 4a25 ldr r2, [pc, #148] ; (80039d8 ) 8003944: 4293 cmp r3, r2 8003946: d036 beq.n 80039b6 8003948: 687b ldr r3, [r7, #4] 800394a: 681b ldr r3, [r3, #0] 800394c: 4a23 ldr r2, [pc, #140] ; (80039dc ) 800394e: 4293 cmp r3, r2 8003950: d031 beq.n 80039b6 8003952: 687b ldr r3, [r7, #4] 8003954: 681b ldr r3, [r3, #0] 8003956: 4a22 ldr r2, [pc, #136] ; (80039e0 ) 8003958: 4293 cmp r3, r2 800395a: d02c beq.n 80039b6 800395c: 687b ldr r3, [r7, #4] 800395e: 681b ldr r3, [r3, #0] 8003960: 4a20 ldr r2, [pc, #128] ; (80039e4 ) 8003962: 4293 cmp r3, r2 8003964: d027 beq.n 80039b6 8003966: 687b ldr r3, [r7, #4] 8003968: 681b ldr r3, [r3, #0] 800396a: 4a1f ldr r2, [pc, #124] ; (80039e8 ) 800396c: 4293 cmp r3, r2 800396e: d022 beq.n 80039b6 8003970: 687b ldr r3, [r7, #4] 8003972: 681b ldr r3, [r3, #0] 8003974: 4a1d ldr r2, [pc, #116] ; (80039ec ) 8003976: 4293 cmp r3, r2 8003978: d01d beq.n 80039b6 800397a: 687b ldr r3, [r7, #4] 800397c: 681b ldr r3, [r3, #0] 800397e: 4a1c ldr r2, [pc, #112] ; (80039f0 ) 8003980: 4293 cmp r3, r2 8003982: d018 beq.n 80039b6 8003984: 687b ldr r3, [r7, #4] 8003986: 681b ldr r3, [r3, #0] 8003988: 4a1a ldr r2, [pc, #104] ; (80039f4 ) 800398a: 4293 cmp r3, r2 800398c: d013 beq.n 80039b6 800398e: 687b ldr r3, [r7, #4] 8003990: 681b ldr r3, [r3, #0] 8003992: 4a19 ldr r2, [pc, #100] ; (80039f8 ) 8003994: 4293 cmp r3, r2 8003996: d00e beq.n 80039b6 8003998: 687b ldr r3, [r7, #4] 800399a: 681b ldr r3, [r3, #0] 800399c: 4a17 ldr r2, [pc, #92] ; (80039fc ) 800399e: 4293 cmp r3, r2 80039a0: d009 beq.n 80039b6 80039a2: 687b ldr r3, [r7, #4] 80039a4: 681b ldr r3, [r3, #0] 80039a6: 4a16 ldr r2, [pc, #88] ; (8003a00 ) 80039a8: 4293 cmp r3, r2 80039aa: d004 beq.n 80039b6 80039ac: 687b ldr r3, [r7, #4] 80039ae: 681b ldr r3, [r3, #0] 80039b0: 4a14 ldr r2, [pc, #80] ; (8003a04 ) 80039b2: 4293 cmp r3, r2 80039b4: d128 bne.n 8003a08 80039b6: 687b ldr r3, [r7, #4] 80039b8: 681b ldr r3, [r3, #0] 80039ba: 681a ldr r2, [r3, #0] 80039bc: 687b ldr r3, [r7, #4] 80039be: 681b ldr r3, [r3, #0] 80039c0: f022 0214 bic.w r2, r2, #20 80039c4: 601a str r2, [r3, #0] 80039c6: e027 b.n 8003a18 80039c8: 40020010 .word 0x40020010 80039cc: 40020028 .word 0x40020028 80039d0: 40020040 .word 0x40020040 80039d4: 40020058 .word 0x40020058 80039d8: 40020070 .word 0x40020070 80039dc: 40020088 .word 0x40020088 80039e0: 400200a0 .word 0x400200a0 80039e4: 400200b8 .word 0x400200b8 80039e8: 40020410 .word 0x40020410 80039ec: 40020428 .word 0x40020428 80039f0: 40020440 .word 0x40020440 80039f4: 40020458 .word 0x40020458 80039f8: 40020470 .word 0x40020470 80039fc: 40020488 .word 0x40020488 8003a00: 400204a0 .word 0x400204a0 8003a04: 400204b8 .word 0x400204b8 8003a08: 687b ldr r3, [r7, #4] 8003a0a: 681b ldr r3, [r3, #0] 8003a0c: 681a ldr r2, [r3, #0] 8003a0e: 687b ldr r3, [r7, #4] 8003a10: 681b ldr r3, [r3, #0] 8003a12: f022 020a bic.w r2, r2, #10 8003a16: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003a18: 687b ldr r3, [r7, #4] 8003a1a: 2201 movs r2, #1 8003a1c: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003a20: 687b ldr r3, [r7, #4] 8003a22: 2200 movs r2, #0 8003a24: f883 2034 strb.w r2, [r3, #52] ; 0x34 } if(hdma->XferCpltCallback != NULL) 8003a28: 687b ldr r3, [r7, #4] 8003a2a: 6bdb ldr r3, [r3, #60] ; 0x3c 8003a2c: 2b00 cmp r3, #0 8003a2e: f000 8097 beq.w 8003b60 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8003a32: 687b ldr r3, [r7, #4] 8003a34: 6bdb ldr r3, [r3, #60] ; 0x3c 8003a36: 6878 ldr r0, [r7, #4] 8003a38: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8003a3a: e091 b.n 8003b60 } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 8003a3c: 687b ldr r3, [r7, #4] 8003a3e: 6ddb ldr r3, [r3, #92] ; 0x5c 8003a40: f003 031f and.w r3, r3, #31 8003a44: 2208 movs r2, #8 8003a46: 409a lsls r2, r3 8003a48: 697b ldr r3, [r7, #20] 8003a4a: 4013 ands r3, r2 8003a4c: 2b00 cmp r3, #0 8003a4e: f000 8088 beq.w 8003b62 8003a52: 693b ldr r3, [r7, #16] 8003a54: f003 0308 and.w r3, r3, #8 8003a58: 2b00 cmp r3, #0 8003a5a: f000 8082 beq.w 8003b62 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8003a5e: 687b ldr r3, [r7, #4] 8003a60: 681b ldr r3, [r3, #0] 8003a62: 4a41 ldr r2, [pc, #260] ; (8003b68 ) 8003a64: 4293 cmp r3, r2 8003a66: d04a beq.n 8003afe 8003a68: 687b ldr r3, [r7, #4] 8003a6a: 681b ldr r3, [r3, #0] 8003a6c: 4a3f ldr r2, [pc, #252] ; (8003b6c ) 8003a6e: 4293 cmp r3, r2 8003a70: d045 beq.n 8003afe 8003a72: 687b ldr r3, [r7, #4] 8003a74: 681b ldr r3, [r3, #0] 8003a76: 4a3e ldr r2, [pc, #248] ; (8003b70 ) 8003a78: 4293 cmp r3, r2 8003a7a: d040 beq.n 8003afe 8003a7c: 687b ldr r3, [r7, #4] 8003a7e: 681b ldr r3, [r3, #0] 8003a80: 4a3c ldr r2, [pc, #240] ; (8003b74 ) 8003a82: 4293 cmp r3, r2 8003a84: d03b beq.n 8003afe 8003a86: 687b ldr r3, [r7, #4] 8003a88: 681b ldr r3, [r3, #0] 8003a8a: 4a3b ldr r2, [pc, #236] ; (8003b78 ) 8003a8c: 4293 cmp r3, r2 8003a8e: d036 beq.n 8003afe 8003a90: 687b ldr r3, [r7, #4] 8003a92: 681b ldr r3, [r3, #0] 8003a94: 4a39 ldr r2, [pc, #228] ; (8003b7c ) 8003a96: 4293 cmp r3, r2 8003a98: d031 beq.n 8003afe 8003a9a: 687b ldr r3, [r7, #4] 8003a9c: 681b ldr r3, [r3, #0] 8003a9e: 4a38 ldr r2, [pc, #224] ; (8003b80 ) 8003aa0: 4293 cmp r3, r2 8003aa2: d02c beq.n 8003afe 8003aa4: 687b ldr r3, [r7, #4] 8003aa6: 681b ldr r3, [r3, #0] 8003aa8: 4a36 ldr r2, [pc, #216] ; (8003b84 ) 8003aaa: 4293 cmp r3, r2 8003aac: d027 beq.n 8003afe 8003aae: 687b ldr r3, [r7, #4] 8003ab0: 681b ldr r3, [r3, #0] 8003ab2: 4a35 ldr r2, [pc, #212] ; (8003b88 ) 8003ab4: 4293 cmp r3, r2 8003ab6: d022 beq.n 8003afe 8003ab8: 687b ldr r3, [r7, #4] 8003aba: 681b ldr r3, [r3, #0] 8003abc: 4a33 ldr r2, [pc, #204] ; (8003b8c ) 8003abe: 4293 cmp r3, r2 8003ac0: d01d beq.n 8003afe 8003ac2: 687b ldr r3, [r7, #4] 8003ac4: 681b ldr r3, [r3, #0] 8003ac6: 4a32 ldr r2, [pc, #200] ; (8003b90 ) 8003ac8: 4293 cmp r3, r2 8003aca: d018 beq.n 8003afe 8003acc: 687b ldr r3, [r7, #4] 8003ace: 681b ldr r3, [r3, #0] 8003ad0: 4a30 ldr r2, [pc, #192] ; (8003b94 ) 8003ad2: 4293 cmp r3, r2 8003ad4: d013 beq.n 8003afe 8003ad6: 687b ldr r3, [r7, #4] 8003ad8: 681b ldr r3, [r3, #0] 8003ada: 4a2f ldr r2, [pc, #188] ; (8003b98 ) 8003adc: 4293 cmp r3, r2 8003ade: d00e beq.n 8003afe 8003ae0: 687b ldr r3, [r7, #4] 8003ae2: 681b ldr r3, [r3, #0] 8003ae4: 4a2d ldr r2, [pc, #180] ; (8003b9c ) 8003ae6: 4293 cmp r3, r2 8003ae8: d009 beq.n 8003afe 8003aea: 687b ldr r3, [r7, #4] 8003aec: 681b ldr r3, [r3, #0] 8003aee: 4a2c ldr r2, [pc, #176] ; (8003ba0 ) 8003af0: 4293 cmp r3, r2 8003af2: d004 beq.n 8003afe 8003af4: 687b ldr r3, [r7, #4] 8003af6: 681b ldr r3, [r3, #0] 8003af8: 4a2a ldr r2, [pc, #168] ; (8003ba4 ) 8003afa: 4293 cmp r3, r2 8003afc: d108 bne.n 8003b10 8003afe: 687b ldr r3, [r7, #4] 8003b00: 681b ldr r3, [r3, #0] 8003b02: 681a ldr r2, [r3, #0] 8003b04: 687b ldr r3, [r7, #4] 8003b06: 681b ldr r3, [r3, #0] 8003b08: f022 021c bic.w r2, r2, #28 8003b0c: 601a str r2, [r3, #0] 8003b0e: e007 b.n 8003b20 8003b10: 687b ldr r3, [r7, #4] 8003b12: 681b ldr r3, [r3, #0] 8003b14: 681a ldr r2, [r3, #0] 8003b16: 687b ldr r3, [r7, #4] 8003b18: 681b ldr r3, [r3, #0] 8003b1a: f022 020e bic.w r2, r2, #14 8003b1e: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 8003b20: 687b ldr r3, [r7, #4] 8003b22: 6ddb ldr r3, [r3, #92] ; 0x5c 8003b24: f003 031f and.w r3, r3, #31 8003b28: 2201 movs r2, #1 8003b2a: 409a lsls r2, r3 8003b2c: 69fb ldr r3, [r7, #28] 8003b2e: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8003b30: 687b ldr r3, [r7, #4] 8003b32: 2201 movs r2, #1 8003b34: 655a str r2, [r3, #84] ; 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003b36: 687b ldr r3, [r7, #4] 8003b38: 2201 movs r2, #1 8003b3a: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003b3e: 687b ldr r3, [r7, #4] 8003b40: 2200 movs r2, #0 8003b42: f883 2034 strb.w r2, [r3, #52] ; 0x34 if (hdma->XferErrorCallback != NULL) 8003b46: 687b ldr r3, [r7, #4] 8003b48: 6cdb ldr r3, [r3, #76] ; 0x4c 8003b4a: 2b00 cmp r3, #0 8003b4c: d009 beq.n 8003b62 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8003b4e: 687b ldr r3, [r7, #4] 8003b50: 6cdb ldr r3, [r3, #76] ; 0x4c 8003b52: 6878 ldr r0, [r7, #4] 8003b54: 4798 blx r3 8003b56: e004 b.n 8003b62 return; 8003b58: bf00 nop 8003b5a: e002 b.n 8003b62 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8003b5c: bf00 nop 8003b5e: e000 b.n 8003b62 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8003b60: bf00 nop } else { /* Nothing To Do */ } } 8003b62: 3728 adds r7, #40 ; 0x28 8003b64: 46bd mov sp, r7 8003b66: bd80 pop {r7, pc} 8003b68: 40020010 .word 0x40020010 8003b6c: 40020028 .word 0x40020028 8003b70: 40020040 .word 0x40020040 8003b74: 40020058 .word 0x40020058 8003b78: 40020070 .word 0x40020070 8003b7c: 40020088 .word 0x40020088 8003b80: 400200a0 .word 0x400200a0 8003b84: 400200b8 .word 0x400200b8 8003b88: 40020410 .word 0x40020410 8003b8c: 40020428 .word 0x40020428 8003b90: 40020440 .word 0x40020440 8003b94: 40020458 .word 0x40020458 8003b98: 40020470 .word 0x40020470 8003b9c: 40020488 .word 0x40020488 8003ba0: 400204a0 .word 0x400204a0 8003ba4: 400204b8 .word 0x400204b8 08003ba8 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 8003ba8: b480 push {r7} 8003baa: b085 sub sp, #20 8003bac: af00 add r7, sp, #0 8003bae: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8003bb0: 687b ldr r3, [r7, #4] 8003bb2: 681b ldr r3, [r3, #0] 8003bb4: 4a42 ldr r2, [pc, #264] ; (8003cc0 ) 8003bb6: 4293 cmp r3, r2 8003bb8: d04a beq.n 8003c50 8003bba: 687b ldr r3, [r7, #4] 8003bbc: 681b ldr r3, [r3, #0] 8003bbe: 4a41 ldr r2, [pc, #260] ; (8003cc4 ) 8003bc0: 4293 cmp r3, r2 8003bc2: d045 beq.n 8003c50 8003bc4: 687b ldr r3, [r7, #4] 8003bc6: 681b ldr r3, [r3, #0] 8003bc8: 4a3f ldr r2, [pc, #252] ; (8003cc8 ) 8003bca: 4293 cmp r3, r2 8003bcc: d040 beq.n 8003c50 8003bce: 687b ldr r3, [r7, #4] 8003bd0: 681b ldr r3, [r3, #0] 8003bd2: 4a3e ldr r2, [pc, #248] ; (8003ccc ) 8003bd4: 4293 cmp r3, r2 8003bd6: d03b beq.n 8003c50 8003bd8: 687b ldr r3, [r7, #4] 8003bda: 681b ldr r3, [r3, #0] 8003bdc: 4a3c ldr r2, [pc, #240] ; (8003cd0 ) 8003bde: 4293 cmp r3, r2 8003be0: d036 beq.n 8003c50 8003be2: 687b ldr r3, [r7, #4] 8003be4: 681b ldr r3, [r3, #0] 8003be6: 4a3b ldr r2, [pc, #236] ; (8003cd4 ) 8003be8: 4293 cmp r3, r2 8003bea: d031 beq.n 8003c50 8003bec: 687b ldr r3, [r7, #4] 8003bee: 681b ldr r3, [r3, #0] 8003bf0: 4a39 ldr r2, [pc, #228] ; (8003cd8 ) 8003bf2: 4293 cmp r3, r2 8003bf4: d02c beq.n 8003c50 8003bf6: 687b ldr r3, [r7, #4] 8003bf8: 681b ldr r3, [r3, #0] 8003bfa: 4a38 ldr r2, [pc, #224] ; (8003cdc ) 8003bfc: 4293 cmp r3, r2 8003bfe: d027 beq.n 8003c50 8003c00: 687b ldr r3, [r7, #4] 8003c02: 681b ldr r3, [r3, #0] 8003c04: 4a36 ldr r2, [pc, #216] ; (8003ce0 ) 8003c06: 4293 cmp r3, r2 8003c08: d022 beq.n 8003c50 8003c0a: 687b ldr r3, [r7, #4] 8003c0c: 681b ldr r3, [r3, #0] 8003c0e: 4a35 ldr r2, [pc, #212] ; (8003ce4 ) 8003c10: 4293 cmp r3, r2 8003c12: d01d beq.n 8003c50 8003c14: 687b ldr r3, [r7, #4] 8003c16: 681b ldr r3, [r3, #0] 8003c18: 4a33 ldr r2, [pc, #204] ; (8003ce8 ) 8003c1a: 4293 cmp r3, r2 8003c1c: d018 beq.n 8003c50 8003c1e: 687b ldr r3, [r7, #4] 8003c20: 681b ldr r3, [r3, #0] 8003c22: 4a32 ldr r2, [pc, #200] ; (8003cec ) 8003c24: 4293 cmp r3, r2 8003c26: d013 beq.n 8003c50 8003c28: 687b ldr r3, [r7, #4] 8003c2a: 681b ldr r3, [r3, #0] 8003c2c: 4a30 ldr r2, [pc, #192] ; (8003cf0 ) 8003c2e: 4293 cmp r3, r2 8003c30: d00e beq.n 8003c50 8003c32: 687b ldr r3, [r7, #4] 8003c34: 681b ldr r3, [r3, #0] 8003c36: 4a2f ldr r2, [pc, #188] ; (8003cf4 ) 8003c38: 4293 cmp r3, r2 8003c3a: d009 beq.n 8003c50 8003c3c: 687b ldr r3, [r7, #4] 8003c3e: 681b ldr r3, [r3, #0] 8003c40: 4a2d ldr r2, [pc, #180] ; (8003cf8 ) 8003c42: 4293 cmp r3, r2 8003c44: d004 beq.n 8003c50 8003c46: 687b ldr r3, [r7, #4] 8003c48: 681b ldr r3, [r3, #0] 8003c4a: 4a2c ldr r2, [pc, #176] ; (8003cfc ) 8003c4c: 4293 cmp r3, r2 8003c4e: d101 bne.n 8003c54 8003c50: 2301 movs r3, #1 8003c52: e000 b.n 8003c56 8003c54: 2300 movs r3, #0 8003c56: 2b00 cmp r3, #0 8003c58: d024 beq.n 8003ca4 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8003c5a: 687b ldr r3, [r7, #4] 8003c5c: 681b ldr r3, [r3, #0] 8003c5e: b2db uxtb r3, r3 8003c60: 3b10 subs r3, #16 8003c62: 4a27 ldr r2, [pc, #156] ; (8003d00 ) 8003c64: fba2 2303 umull r2, r3, r2, r3 8003c68: 091b lsrs r3, r3, #4 8003c6a: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 8003c6c: 68fb ldr r3, [r7, #12] 8003c6e: f003 0307 and.w r3, r3, #7 8003c72: 4a24 ldr r2, [pc, #144] ; (8003d04 ) 8003c74: 5cd3 ldrb r3, [r2, r3] 8003c76: 461a mov r2, r3 8003c78: 687b ldr r3, [r7, #4] 8003c7a: 65da str r2, [r3, #92] ; 0x5c if (stream_number > 3U) 8003c7c: 68fb ldr r3, [r7, #12] 8003c7e: 2b03 cmp r3, #3 8003c80: d908 bls.n 8003c94 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 8003c82: 687b ldr r3, [r7, #4] 8003c84: 681b ldr r3, [r3, #0] 8003c86: 461a mov r2, r3 8003c88: 4b1f ldr r3, [pc, #124] ; (8003d08 ) 8003c8a: 4013 ands r3, r2 8003c8c: 1d1a adds r2, r3, #4 8003c8e: 687b ldr r3, [r7, #4] 8003c90: 659a str r2, [r3, #88] ; 0x58 8003c92: e00d b.n 8003cb0 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 8003c94: 687b ldr r3, [r7, #4] 8003c96: 681b ldr r3, [r3, #0] 8003c98: 461a mov r2, r3 8003c9a: 4b1b ldr r3, [pc, #108] ; (8003d08 ) 8003c9c: 4013 ands r3, r2 8003c9e: 687a ldr r2, [r7, #4] 8003ca0: 6593 str r3, [r2, #88] ; 0x58 8003ca2: e005 b.n 8003cb0 } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 8003ca4: 687b ldr r3, [r7, #4] 8003ca6: 681b ldr r3, [r3, #0] 8003ca8: f023 02ff bic.w r2, r3, #255 ; 0xff 8003cac: 687b ldr r3, [r7, #4] 8003cae: 659a str r2, [r3, #88] ; 0x58 } return hdma->StreamBaseAddress; 8003cb0: 687b ldr r3, [r7, #4] 8003cb2: 6d9b ldr r3, [r3, #88] ; 0x58 } 8003cb4: 4618 mov r0, r3 8003cb6: 3714 adds r7, #20 8003cb8: 46bd mov sp, r7 8003cba: f85d 7b04 ldr.w r7, [sp], #4 8003cbe: 4770 bx lr 8003cc0: 40020010 .word 0x40020010 8003cc4: 40020028 .word 0x40020028 8003cc8: 40020040 .word 0x40020040 8003ccc: 40020058 .word 0x40020058 8003cd0: 40020070 .word 0x40020070 8003cd4: 40020088 .word 0x40020088 8003cd8: 400200a0 .word 0x400200a0 8003cdc: 400200b8 .word 0x400200b8 8003ce0: 40020410 .word 0x40020410 8003ce4: 40020428 .word 0x40020428 8003ce8: 40020440 .word 0x40020440 8003cec: 40020458 .word 0x40020458 8003cf0: 40020470 .word 0x40020470 8003cf4: 40020488 .word 0x40020488 8003cf8: 400204a0 .word 0x400204a0 8003cfc: 400204b8 .word 0x400204b8 8003d00: aaaaaaab .word 0xaaaaaaab 8003d04: 08026b50 .word 0x08026b50 8003d08: fffffc00 .word 0xfffffc00 08003d0c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 8003d0c: b480 push {r7} 8003d0e: b085 sub sp, #20 8003d10: af00 add r7, sp, #0 8003d12: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8003d14: 2300 movs r3, #0 8003d16: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 8003d18: 687b ldr r3, [r7, #4] 8003d1a: 699b ldr r3, [r3, #24] 8003d1c: 2b00 cmp r3, #0 8003d1e: d120 bne.n 8003d62 { switch (hdma->Init.FIFOThreshold) 8003d20: 687b ldr r3, [r7, #4] 8003d22: 6a9b ldr r3, [r3, #40] ; 0x28 8003d24: 2b03 cmp r3, #3 8003d26: d858 bhi.n 8003dda 8003d28: a201 add r2, pc, #4 ; (adr r2, 8003d30 ) 8003d2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003d2e: bf00 nop 8003d30: 08003d41 .word 0x08003d41 8003d34: 08003d53 .word 0x08003d53 8003d38: 08003d41 .word 0x08003d41 8003d3c: 08003ddb .word 0x08003ddb { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8003d40: 687b ldr r3, [r7, #4] 8003d42: 6adb ldr r3, [r3, #44] ; 0x2c 8003d44: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8003d48: 2b00 cmp r3, #0 8003d4a: d048 beq.n 8003dde { status = HAL_ERROR; 8003d4c: 2301 movs r3, #1 8003d4e: 73fb strb r3, [r7, #15] } break; 8003d50: e045 b.n 8003dde case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8003d52: 687b ldr r3, [r7, #4] 8003d54: 6adb ldr r3, [r3, #44] ; 0x2c 8003d56: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000 8003d5a: d142 bne.n 8003de2 { status = HAL_ERROR; 8003d5c: 2301 movs r3, #1 8003d5e: 73fb strb r3, [r7, #15] } break; 8003d60: e03f b.n 8003de2 break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8003d62: 687b ldr r3, [r7, #4] 8003d64: 699b ldr r3, [r3, #24] 8003d66: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8003d6a: d123 bne.n 8003db4 { switch (hdma->Init.FIFOThreshold) 8003d6c: 687b ldr r3, [r7, #4] 8003d6e: 6a9b ldr r3, [r3, #40] ; 0x28 8003d70: 2b03 cmp r3, #3 8003d72: d838 bhi.n 8003de6 8003d74: a201 add r2, pc, #4 ; (adr r2, 8003d7c ) 8003d76: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003d7a: bf00 nop 8003d7c: 08003d8d .word 0x08003d8d 8003d80: 08003d93 .word 0x08003d93 8003d84: 08003d8d .word 0x08003d8d 8003d88: 08003da5 .word 0x08003da5 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 8003d8c: 2301 movs r3, #1 8003d8e: 73fb strb r3, [r7, #15] break; 8003d90: e030 b.n 8003df4 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8003d92: 687b ldr r3, [r7, #4] 8003d94: 6adb ldr r3, [r3, #44] ; 0x2c 8003d96: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8003d9a: 2b00 cmp r3, #0 8003d9c: d025 beq.n 8003dea { status = HAL_ERROR; 8003d9e: 2301 movs r3, #1 8003da0: 73fb strb r3, [r7, #15] } break; 8003da2: e022 b.n 8003dea case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8003da4: 687b ldr r3, [r7, #4] 8003da6: 6adb ldr r3, [r3, #44] ; 0x2c 8003da8: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000 8003dac: d11f bne.n 8003dee { status = HAL_ERROR; 8003dae: 2301 movs r3, #1 8003db0: 73fb strb r3, [r7, #15] } break; 8003db2: e01c b.n 8003dee } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 8003db4: 687b ldr r3, [r7, #4] 8003db6: 6a9b ldr r3, [r3, #40] ; 0x28 8003db8: 2b02 cmp r3, #2 8003dba: d902 bls.n 8003dc2 8003dbc: 2b03 cmp r3, #3 8003dbe: d003 beq.n 8003dc8 status = HAL_ERROR; } break; default: break; 8003dc0: e018 b.n 8003df4 status = HAL_ERROR; 8003dc2: 2301 movs r3, #1 8003dc4: 73fb strb r3, [r7, #15] break; 8003dc6: e015 b.n 8003df4 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8003dc8: 687b ldr r3, [r7, #4] 8003dca: 6adb ldr r3, [r3, #44] ; 0x2c 8003dcc: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8003dd0: 2b00 cmp r3, #0 8003dd2: d00e beq.n 8003df2 status = HAL_ERROR; 8003dd4: 2301 movs r3, #1 8003dd6: 73fb strb r3, [r7, #15] break; 8003dd8: e00b b.n 8003df2 break; 8003dda: bf00 nop 8003ddc: e00a b.n 8003df4 break; 8003dde: bf00 nop 8003de0: e008 b.n 8003df4 break; 8003de2: bf00 nop 8003de4: e006 b.n 8003df4 break; 8003de6: bf00 nop 8003de8: e004 b.n 8003df4 break; 8003dea: bf00 nop 8003dec: e002 b.n 8003df4 break; 8003dee: bf00 nop 8003df0: e000 b.n 8003df4 break; 8003df2: bf00 nop } } return status; 8003df4: 7bfb ldrb r3, [r7, #15] } 8003df6: 4618 mov r0, r3 8003df8: 3714 adds r7, #20 8003dfa: 46bd mov sp, r7 8003dfc: f85d 7b04 ldr.w r7, [sp], #4 8003e00: 4770 bx lr 8003e02: bf00 nop 08003e04 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 8003e04: b480 push {r7} 8003e06: b085 sub sp, #20 8003e08: af00 add r7, sp, #0 8003e0a: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 8003e0c: 687b ldr r3, [r7, #4] 8003e0e: 681b ldr r3, [r3, #0] 8003e10: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8003e12: 687b ldr r3, [r7, #4] 8003e14: 681b ldr r3, [r3, #0] 8003e16: 4a38 ldr r2, [pc, #224] ; (8003ef8 ) 8003e18: 4293 cmp r3, r2 8003e1a: d022 beq.n 8003e62 8003e1c: 687b ldr r3, [r7, #4] 8003e1e: 681b ldr r3, [r3, #0] 8003e20: 4a36 ldr r2, [pc, #216] ; (8003efc ) 8003e22: 4293 cmp r3, r2 8003e24: d01d beq.n 8003e62 8003e26: 687b ldr r3, [r7, #4] 8003e28: 681b ldr r3, [r3, #0] 8003e2a: 4a35 ldr r2, [pc, #212] ; (8003f00 ) 8003e2c: 4293 cmp r3, r2 8003e2e: d018 beq.n 8003e62 8003e30: 687b ldr r3, [r7, #4] 8003e32: 681b ldr r3, [r3, #0] 8003e34: 4a33 ldr r2, [pc, #204] ; (8003f04 ) 8003e36: 4293 cmp r3, r2 8003e38: d013 beq.n 8003e62 8003e3a: 687b ldr r3, [r7, #4] 8003e3c: 681b ldr r3, [r3, #0] 8003e3e: 4a32 ldr r2, [pc, #200] ; (8003f08 ) 8003e40: 4293 cmp r3, r2 8003e42: d00e beq.n 8003e62 8003e44: 687b ldr r3, [r7, #4] 8003e46: 681b ldr r3, [r3, #0] 8003e48: 4a30 ldr r2, [pc, #192] ; (8003f0c ) 8003e4a: 4293 cmp r3, r2 8003e4c: d009 beq.n 8003e62 8003e4e: 687b ldr r3, [r7, #4] 8003e50: 681b ldr r3, [r3, #0] 8003e52: 4a2f ldr r2, [pc, #188] ; (8003f10 ) 8003e54: 4293 cmp r3, r2 8003e56: d004 beq.n 8003e62 8003e58: 687b ldr r3, [r7, #4] 8003e5a: 681b ldr r3, [r3, #0] 8003e5c: 4a2d ldr r2, [pc, #180] ; (8003f14 ) 8003e5e: 4293 cmp r3, r2 8003e60: d101 bne.n 8003e66 8003e62: 2301 movs r3, #1 8003e64: e000 b.n 8003e68 8003e66: 2300 movs r3, #0 8003e68: 2b00 cmp r3, #0 8003e6a: d01a beq.n 8003ea2 { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 8003e6c: 687b ldr r3, [r7, #4] 8003e6e: 681b ldr r3, [r3, #0] 8003e70: b2db uxtb r3, r3 8003e72: 3b08 subs r3, #8 8003e74: 4a28 ldr r2, [pc, #160] ; (8003f18 ) 8003e76: fba2 2303 umull r2, r3, r2, r3 8003e7a: 091b lsrs r3, r3, #4 8003e7c: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 8003e7e: 68fa ldr r2, [r7, #12] 8003e80: 4b26 ldr r3, [pc, #152] ; (8003f1c ) 8003e82: 4413 add r3, r2 8003e84: 009b lsls r3, r3, #2 8003e86: 461a mov r2, r3 8003e88: 687b ldr r3, [r7, #4] 8003e8a: 661a str r2, [r3, #96] ; 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 8003e8c: 687b ldr r3, [r7, #4] 8003e8e: 4a24 ldr r2, [pc, #144] ; (8003f20 ) 8003e90: 665a str r2, [r3, #100] ; 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8003e92: 68fb ldr r3, [r7, #12] 8003e94: f003 031f and.w r3, r3, #31 8003e98: 2201 movs r2, #1 8003e9a: 409a lsls r2, r3 8003e9c: 687b ldr r3, [r7, #4] 8003e9e: 669a str r2, [r3, #104] ; 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 8003ea0: e024 b.n 8003eec stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8003ea2: 687b ldr r3, [r7, #4] 8003ea4: 681b ldr r3, [r3, #0] 8003ea6: b2db uxtb r3, r3 8003ea8: 3b10 subs r3, #16 8003eaa: 4a1e ldr r2, [pc, #120] ; (8003f24 ) 8003eac: fba2 2303 umull r2, r3, r2, r3 8003eb0: 091b lsrs r3, r3, #4 8003eb2: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 8003eb4: 68bb ldr r3, [r7, #8] 8003eb6: 4a1c ldr r2, [pc, #112] ; (8003f28 ) 8003eb8: 4293 cmp r3, r2 8003eba: d806 bhi.n 8003eca 8003ebc: 68bb ldr r3, [r7, #8] 8003ebe: 4a1b ldr r2, [pc, #108] ; (8003f2c ) 8003ec0: 4293 cmp r3, r2 8003ec2: d902 bls.n 8003eca stream_number += 8U; 8003ec4: 68fb ldr r3, [r7, #12] 8003ec6: 3308 adds r3, #8 8003ec8: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 8003eca: 68fa ldr r2, [r7, #12] 8003ecc: 4b18 ldr r3, [pc, #96] ; (8003f30 ) 8003ece: 4413 add r3, r2 8003ed0: 009b lsls r3, r3, #2 8003ed2: 461a mov r2, r3 8003ed4: 687b ldr r3, [r7, #4] 8003ed6: 661a str r2, [r3, #96] ; 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 8003ed8: 687b ldr r3, [r7, #4] 8003eda: 4a16 ldr r2, [pc, #88] ; (8003f34 ) 8003edc: 665a str r2, [r3, #100] ; 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8003ede: 68fb ldr r3, [r7, #12] 8003ee0: f003 031f and.w r3, r3, #31 8003ee4: 2201 movs r2, #1 8003ee6: 409a lsls r2, r3 8003ee8: 687b ldr r3, [r7, #4] 8003eea: 669a str r2, [r3, #104] ; 0x68 } 8003eec: bf00 nop 8003eee: 3714 adds r7, #20 8003ef0: 46bd mov sp, r7 8003ef2: f85d 7b04 ldr.w r7, [sp], #4 8003ef6: 4770 bx lr 8003ef8: 58025408 .word 0x58025408 8003efc: 5802541c .word 0x5802541c 8003f00: 58025430 .word 0x58025430 8003f04: 58025444 .word 0x58025444 8003f08: 58025458 .word 0x58025458 8003f0c: 5802546c .word 0x5802546c 8003f10: 58025480 .word 0x58025480 8003f14: 58025494 .word 0x58025494 8003f18: cccccccd .word 0xcccccccd 8003f1c: 16009600 .word 0x16009600 8003f20: 58025880 .word 0x58025880 8003f24: aaaaaaab .word 0xaaaaaaab 8003f28: 400204b8 .word 0x400204b8 8003f2c: 4002040f .word 0x4002040f 8003f30: 10008200 .word 0x10008200 8003f34: 40020880 .word 0x40020880 08003f38 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 8003f38: b480 push {r7} 8003f3a: b085 sub sp, #20 8003f3c: af00 add r7, sp, #0 8003f3e: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 8003f40: 687b ldr r3, [r7, #4] 8003f42: 685b ldr r3, [r3, #4] 8003f44: b2db uxtb r3, r3 8003f46: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 8003f48: 68fb ldr r3, [r7, #12] 8003f4a: 2b00 cmp r3, #0 8003f4c: d04a beq.n 8003fe4 8003f4e: 68fb ldr r3, [r7, #12] 8003f50: 2b08 cmp r3, #8 8003f52: d847 bhi.n 8003fe4 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8003f54: 687b ldr r3, [r7, #4] 8003f56: 681b ldr r3, [r3, #0] 8003f58: 4a25 ldr r2, [pc, #148] ; (8003ff0 ) 8003f5a: 4293 cmp r3, r2 8003f5c: d022 beq.n 8003fa4 8003f5e: 687b ldr r3, [r7, #4] 8003f60: 681b ldr r3, [r3, #0] 8003f62: 4a24 ldr r2, [pc, #144] ; (8003ff4 ) 8003f64: 4293 cmp r3, r2 8003f66: d01d beq.n 8003fa4 8003f68: 687b ldr r3, [r7, #4] 8003f6a: 681b ldr r3, [r3, #0] 8003f6c: 4a22 ldr r2, [pc, #136] ; (8003ff8 ) 8003f6e: 4293 cmp r3, r2 8003f70: d018 beq.n 8003fa4 8003f72: 687b ldr r3, [r7, #4] 8003f74: 681b ldr r3, [r3, #0] 8003f76: 4a21 ldr r2, [pc, #132] ; (8003ffc ) 8003f78: 4293 cmp r3, r2 8003f7a: d013 beq.n 8003fa4 8003f7c: 687b ldr r3, [r7, #4] 8003f7e: 681b ldr r3, [r3, #0] 8003f80: 4a1f ldr r2, [pc, #124] ; (8004000 ) 8003f82: 4293 cmp r3, r2 8003f84: d00e beq.n 8003fa4 8003f86: 687b ldr r3, [r7, #4] 8003f88: 681b ldr r3, [r3, #0] 8003f8a: 4a1e ldr r2, [pc, #120] ; (8004004 ) 8003f8c: 4293 cmp r3, r2 8003f8e: d009 beq.n 8003fa4 8003f90: 687b ldr r3, [r7, #4] 8003f92: 681b ldr r3, [r3, #0] 8003f94: 4a1c ldr r2, [pc, #112] ; (8004008 ) 8003f96: 4293 cmp r3, r2 8003f98: d004 beq.n 8003fa4 8003f9a: 687b ldr r3, [r7, #4] 8003f9c: 681b ldr r3, [r3, #0] 8003f9e: 4a1b ldr r2, [pc, #108] ; (800400c ) 8003fa0: 4293 cmp r3, r2 8003fa2: d101 bne.n 8003fa8 8003fa4: 2301 movs r3, #1 8003fa6: e000 b.n 8003faa 8003fa8: 2300 movs r3, #0 8003faa: 2b00 cmp r3, #0 8003fac: d00a beq.n 8003fc4 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 8003fae: 68fa ldr r2, [r7, #12] 8003fb0: 4b17 ldr r3, [pc, #92] ; (8004010 ) 8003fb2: 4413 add r3, r2 8003fb4: 009b lsls r3, r3, #2 8003fb6: 461a mov r2, r3 8003fb8: 687b ldr r3, [r7, #4] 8003fba: 66da str r2, [r3, #108] ; 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 8003fbc: 687b ldr r3, [r7, #4] 8003fbe: 4a15 ldr r2, [pc, #84] ; (8004014 ) 8003fc0: 671a str r2, [r3, #112] ; 0x70 8003fc2: e009 b.n 8003fd8 } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8003fc4: 68fa ldr r2, [r7, #12] 8003fc6: 4b14 ldr r3, [pc, #80] ; (8004018 ) 8003fc8: 4413 add r3, r2 8003fca: 009b lsls r3, r3, #2 8003fcc: 461a mov r2, r3 8003fce: 687b ldr r3, [r7, #4] 8003fd0: 66da str r2, [r3, #108] ; 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 8003fd2: 687b ldr r3, [r7, #4] 8003fd4: 4a11 ldr r2, [pc, #68] ; (800401c ) 8003fd6: 671a str r2, [r3, #112] ; 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 8003fd8: 68fb ldr r3, [r7, #12] 8003fda: 3b01 subs r3, #1 8003fdc: 2201 movs r2, #1 8003fde: 409a lsls r2, r3 8003fe0: 687b ldr r3, [r7, #4] 8003fe2: 675a str r2, [r3, #116] ; 0x74 } } 8003fe4: bf00 nop 8003fe6: 3714 adds r7, #20 8003fe8: 46bd mov sp, r7 8003fea: f85d 7b04 ldr.w r7, [sp], #4 8003fee: 4770 bx lr 8003ff0: 58025408 .word 0x58025408 8003ff4: 5802541c .word 0x5802541c 8003ff8: 58025430 .word 0x58025430 8003ffc: 58025444 .word 0x58025444 8004000: 58025458 .word 0x58025458 8004004: 5802546c .word 0x5802546c 8004008: 58025480 .word 0x58025480 800400c: 58025494 .word 0x58025494 8004010: 1600963f .word 0x1600963f 8004014: 58025940 .word 0x58025940 8004018: 1000823f .word 0x1000823f 800401c: 40020940 .word 0x40020940 08004020 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { 8004020: b580 push {r7, lr} 8004022: b084 sub sp, #16 8004024: af00 add r7, sp, #0 8004026: 6078 str r0, [r7, #4] uint32_t tickstart; if (heth == NULL) 8004028: 687b ldr r3, [r7, #4] 800402a: 2b00 cmp r3, #0 800402c: d101 bne.n 8004032 { return HAL_ERROR; 800402e: 2301 movs r3, #1 8004030: e0cf b.n 80041d2 } if (heth->gState == HAL_ETH_STATE_RESET) 8004032: 687b ldr r3, [r7, #4] 8004034: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8004038: 2b00 cmp r3, #0 800403a: d106 bne.n 800404a { heth->gState = HAL_ETH_STATE_BUSY; 800403c: 687b ldr r3, [r7, #4] 800403e: 2223 movs r2, #35 ; 0x23 8004040: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Init the low level hardware */ heth->MspInitCallback(heth); #else /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); 8004044: 6878 ldr r0, [r7, #4] 8004046: f00b fe73 bl 800fd30 #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ } __HAL_RCC_SYSCFG_CLK_ENABLE(); 800404a: 4b64 ldr r3, [pc, #400] ; (80041dc ) 800404c: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 8004050: 4a62 ldr r2, [pc, #392] ; (80041dc ) 8004052: f043 0302 orr.w r3, r3, #2 8004056: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 800405a: 4b60 ldr r3, [pc, #384] ; (80041dc ) 800405c: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 8004060: f003 0302 and.w r3, r3, #2 8004064: 60bb str r3, [r7, #8] 8004066: 68bb ldr r3, [r7, #8] if (heth->Init.MediaInterface == HAL_ETH_MII_MODE) 8004068: 687b ldr r3, [r7, #4] 800406a: 7a1b ldrb r3, [r3, #8] 800406c: 2b00 cmp r3, #0 800406e: d103 bne.n 8004078 { HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII); 8004070: 2000 movs r0, #0 8004072: f7fe f9a7 bl 80023c4 8004076: e003 b.n 8004080 } else { HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII); 8004078: f44f 0000 mov.w r0, #8388608 ; 0x800000 800407c: f7fe f9a2 bl 80023c4 } /* Dummy read to sync with ETH */ (void)SYSCFG->PMCR; 8004080: 4b57 ldr r3, [pc, #348] ; (80041e0 ) 8004082: 685b ldr r3, [r3, #4] /* Ethernet Software reset */ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ /* After reset all the registers holds their respective reset values */ SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR); 8004084: 687b ldr r3, [r7, #4] 8004086: 681b ldr r3, [r3, #0] 8004088: f503 5380 add.w r3, r3, #4096 ; 0x1000 800408c: 681b ldr r3, [r3, #0] 800408e: 687a ldr r2, [r7, #4] 8004090: 6812 ldr r2, [r2, #0] 8004092: f043 0301 orr.w r3, r3, #1 8004096: f502 5280 add.w r2, r2, #4096 ; 0x1000 800409a: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 800409c: f7fe f962 bl 8002364 80040a0: 60f8 str r0, [r7, #12] /* Wait for software reset */ while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U) 80040a2: e011 b.n 80040c8 { if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) 80040a4: f7fe f95e bl 8002364 80040a8: 4602 mov r2, r0 80040aa: 68fb ldr r3, [r7, #12] 80040ac: 1ad3 subs r3, r2, r3 80040ae: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 80040b2: d909 bls.n 80040c8 { /* Set Error Code */ heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; 80040b4: 687b ldr r3, [r7, #4] 80040b6: 2204 movs r2, #4 80040b8: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Set State as Error */ heth->gState = HAL_ETH_STATE_ERROR; 80040bc: 687b ldr r3, [r7, #4] 80040be: 22e0 movs r2, #224 ; 0xe0 80040c0: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Return Error */ return HAL_ERROR; 80040c4: 2301 movs r3, #1 80040c6: e084 b.n 80041d2 while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U) 80040c8: 687b ldr r3, [r7, #4] 80040ca: 681b ldr r3, [r3, #0] 80040cc: f503 5380 add.w r3, r3, #4096 ; 0x1000 80040d0: 681b ldr r3, [r3, #0] 80040d2: f003 0301 and.w r3, r3, #1 80040d6: 2b00 cmp r3, #0 80040d8: d1e4 bne.n 80040a4 } } /*------------------ MDIO CSR Clock Range Configuration --------------------*/ HAL_ETH_SetMDIOClockRange(heth); 80040da: 6878 ldr r0, [r7, #4] 80040dc: f000 ff28 bl 8004f30 /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/ WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U)); 80040e0: f003 ff0e bl 8007f00 80040e4: 4603 mov r3, r0 80040e6: 4a3f ldr r2, [pc, #252] ; (80041e4 ) 80040e8: fba2 2303 umull r2, r3, r2, r3 80040ec: 0c9a lsrs r2, r3, #18 80040ee: 687b ldr r3, [r7, #4] 80040f0: 681b ldr r3, [r3, #0] 80040f2: 3a01 subs r2, #1 80040f4: f8c3 20dc str.w r2, [r3, #220] ; 0xdc /*------------------ MAC, MTL and DMA default Configuration ----------------*/ ETH_MACDMAConfig(heth); 80040f8: 6878 ldr r0, [r7, #4] 80040fa: f001 f921 bl 8005340 /* SET DSL to 64 bit */ MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT); 80040fe: 687b ldr r3, [r7, #4] 8004100: 681b ldr r3, [r3, #0] 8004102: f503 5380 add.w r3, r3, #4096 ; 0x1000 8004106: f8d3 3100 ldr.w r3, [r3, #256] ; 0x100 800410a: f423 13e0 bic.w r3, r3, #1835008 ; 0x1c0000 800410e: 687a ldr r2, [r7, #4] 8004110: 6812 ldr r2, [r2, #0] 8004112: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8004116: f502 5280 add.w r2, r2, #4096 ; 0x1000 800411a: f8c2 3100 str.w r3, [r2, #256] ; 0x100 /* Set Receive Buffers Length (must be a multiple of 4) */ if ((heth->Init.RxBuffLen % 0x4U) != 0x0U) 800411e: 687b ldr r3, [r7, #4] 8004120: 695b ldr r3, [r3, #20] 8004122: f003 0303 and.w r3, r3, #3 8004126: 2b00 cmp r3, #0 8004128: d009 beq.n 800413e { /* Set Error Code */ heth->ErrorCode = HAL_ETH_ERROR_PARAM; 800412a: 687b ldr r3, [r7, #4] 800412c: 2201 movs r2, #1 800412e: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Set State as Error */ heth->gState = HAL_ETH_STATE_ERROR; 8004132: 687b ldr r3, [r7, #4] 8004134: 22e0 movs r2, #224 ; 0xe0 8004136: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Return Error */ return HAL_ERROR; 800413a: 2301 movs r3, #1 800413c: e049 b.n 80041d2 } else { MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1)); 800413e: 687b ldr r3, [r7, #4] 8004140: 681b ldr r3, [r3, #0] 8004142: f503 5380 add.w r3, r3, #4096 ; 0x1000 8004146: f8d3 2108 ldr.w r2, [r3, #264] ; 0x108 800414a: 4b27 ldr r3, [pc, #156] ; (80041e8 ) 800414c: 4013 ands r3, r2 800414e: 687a ldr r2, [r7, #4] 8004150: 6952 ldr r2, [r2, #20] 8004152: 0051 lsls r1, r2, #1 8004154: 687a ldr r2, [r7, #4] 8004156: 6812 ldr r2, [r2, #0] 8004158: 430b orrs r3, r1 800415a: f502 5280 add.w r2, r2, #4096 ; 0x1000 800415e: f8c2 3108 str.w r3, [r2, #264] ; 0x108 } /*------------------ DMA Tx Descriptors Configuration ----------------------*/ ETH_DMATxDescListInit(heth); 8004162: 6878 ldr r0, [r7, #4] 8004164: f001 f989 bl 800547a /*------------------ DMA Rx Descriptors Configuration ----------------------*/ ETH_DMARxDescListInit(heth); 8004168: 6878 ldr r0, [r7, #4] 800416a: f001 f9cf bl 800550c /*--------------------- ETHERNET MAC Address Configuration ------------------*/ /* Set MAC addr bits 32 to 47 */ heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]); 800416e: 687b ldr r3, [r7, #4] 8004170: 685b ldr r3, [r3, #4] 8004172: 3305 adds r3, #5 8004174: 781b ldrb r3, [r3, #0] 8004176: 021a lsls r2, r3, #8 8004178: 687b ldr r3, [r7, #4] 800417a: 685b ldr r3, [r3, #4] 800417c: 3304 adds r3, #4 800417e: 781b ldrb r3, [r3, #0] 8004180: 4619 mov r1, r3 8004182: 687b ldr r3, [r7, #4] 8004184: 681b ldr r3, [r3, #0] 8004186: 430a orrs r2, r1 8004188: f8c3 2300 str.w r2, [r3, #768] ; 0x300 /* Set MAC addr bits 0 to 31 */ heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | 800418c: 687b ldr r3, [r7, #4] 800418e: 685b ldr r3, [r3, #4] 8004190: 3303 adds r3, #3 8004192: 781b ldrb r3, [r3, #0] 8004194: 061a lsls r2, r3, #24 8004196: 687b ldr r3, [r7, #4] 8004198: 685b ldr r3, [r3, #4] 800419a: 3302 adds r3, #2 800419c: 781b ldrb r3, [r3, #0] 800419e: 041b lsls r3, r3, #16 80041a0: 431a orrs r2, r3 ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]); 80041a2: 687b ldr r3, [r7, #4] 80041a4: 685b ldr r3, [r3, #4] 80041a6: 3301 adds r3, #1 80041a8: 781b ldrb r3, [r3, #0] 80041aa: 021b lsls r3, r3, #8 heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | 80041ac: 431a orrs r2, r3 ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]); 80041ae: 687b ldr r3, [r7, #4] 80041b0: 685b ldr r3, [r3, #4] 80041b2: 781b ldrb r3, [r3, #0] 80041b4: 4619 mov r1, r3 heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | 80041b6: 687b ldr r3, [r7, #4] 80041b8: 681b ldr r3, [r3, #0] ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]); 80041ba: 430a orrs r2, r1 heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | 80041bc: f8c3 2304 str.w r2, [r3, #772] ; 0x304 heth->ErrorCode = HAL_ETH_ERROR_NONE; 80041c0: 687b ldr r3, [r7, #4] 80041c2: 2200 movs r2, #0 80041c4: f8c3 2088 str.w r2, [r3, #136] ; 0x88 heth->gState = HAL_ETH_STATE_READY; 80041c8: 687b ldr r3, [r7, #4] 80041ca: 2210 movs r2, #16 80041cc: f8c3 2084 str.w r2, [r3, #132] ; 0x84 return HAL_OK; 80041d0: 2300 movs r3, #0 } 80041d2: 4618 mov r0, r3 80041d4: 3710 adds r7, #16 80041d6: 46bd mov sp, r7 80041d8: bd80 pop {r7, pc} 80041da: bf00 nop 80041dc: 58024400 .word 0x58024400 80041e0: 58000400 .word 0x58000400 80041e4: 431bde83 .word 0x431bde83 80041e8: ffff8001 .word 0xffff8001 080041ec : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) { 80041ec: b580 push {r7, lr} 80041ee: b082 sub sp, #8 80041f0: af00 add r7, sp, #0 80041f2: 6078 str r0, [r7, #4] if (heth->gState == HAL_ETH_STATE_READY) 80041f4: 687b ldr r3, [r7, #4] 80041f6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80041fa: 2b10 cmp r3, #16 80041fc: d179 bne.n 80042f2 { heth->gState = HAL_ETH_STATE_BUSY; 80041fe: 687b ldr r3, [r7, #4] 8004200: 2223 movs r2, #35 ; 0x23 8004202: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* save IT mode to ETH Handle */ heth->RxDescList.ItMode = 1U; 8004206: 687b ldr r3, [r7, #4] 8004208: 2201 movs r2, #1 800420a: 659a str r2, [r3, #88] ; 0x58 /* Disable Rx MMC Interrupts */ SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \ 800420c: 687b ldr r3, [r7, #4] 800420e: 681b ldr r3, [r3, #0] 8004210: f8d3 170c ldr.w r1, [r3, #1804] ; 0x70c 8004214: 687b ldr r3, [r7, #4] 8004216: 681a ldr r2, [r3, #0] 8004218: 4b38 ldr r3, [pc, #224] ; (80042fc ) 800421a: 430b orrs r3, r1 800421c: f8c2 370c str.w r3, [r2, #1804] ; 0x70c ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM); /* Disable Tx MMC Interrupts */ SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \ 8004220: 687b ldr r3, [r7, #4] 8004222: 681b ldr r3, [r3, #0] 8004224: f8d3 1710 ldr.w r1, [r3, #1808] ; 0x710 8004228: 687b ldr r3, [r7, #4] 800422a: 681a ldr r2, [r3, #0] 800422c: 4b34 ldr r3, [pc, #208] ; (8004300 ) 800422e: 430b orrs r3, r1 8004230: f8c2 3710 str.w r3, [r2, #1808] ; 0x710 ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM); /* Set nombre of descriptors to build */ heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; 8004234: 687b ldr r3, [r7, #4] 8004236: 2204 movs r2, #4 8004238: 66da str r2, [r3, #108] ; 0x6c /* Build all descriptors */ ETH_UpdateDescriptor(heth); 800423a: 6878 ldr r0, [r7, #4] 800423c: f000 f9eb bl 8004616 /* Enable the MAC transmission */ SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); 8004240: 687b ldr r3, [r7, #4] 8004242: 681b ldr r3, [r3, #0] 8004244: 681a ldr r2, [r3, #0] 8004246: 687b ldr r3, [r7, #4] 8004248: 681b ldr r3, [r3, #0] 800424a: f042 0202 orr.w r2, r2, #2 800424e: 601a str r2, [r3, #0] /* Enable the MAC reception */ SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); 8004250: 687b ldr r3, [r7, #4] 8004252: 681b ldr r3, [r3, #0] 8004254: 681a ldr r2, [r3, #0] 8004256: 687b ldr r3, [r7, #4] 8004258: 681b ldr r3, [r3, #0] 800425a: f042 0201 orr.w r2, r2, #1 800425e: 601a str r2, [r3, #0] /* Set the Flush Transmit FIFO bit */ SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); 8004260: 687b ldr r3, [r7, #4] 8004262: 681b ldr r3, [r3, #0] 8004264: f8d3 2d00 ldr.w r2, [r3, #3328] ; 0xd00 8004268: 687b ldr r3, [r7, #4] 800426a: 681b ldr r3, [r3, #0] 800426c: f042 0201 orr.w r2, r2, #1 8004270: f8c3 2d00 str.w r2, [r3, #3328] ; 0xd00 /* Enable the DMA transmission */ SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); 8004274: 687b ldr r3, [r7, #4] 8004276: 681b ldr r3, [r3, #0] 8004278: f503 5380 add.w r3, r3, #4096 ; 0x1000 800427c: f8d3 3104 ldr.w r3, [r3, #260] ; 0x104 8004280: 687a ldr r2, [r7, #4] 8004282: 6812 ldr r2, [r2, #0] 8004284: f043 0301 orr.w r3, r3, #1 8004288: f502 5280 add.w r2, r2, #4096 ; 0x1000 800428c: f8c2 3104 str.w r3, [r2, #260] ; 0x104 /* Enable the DMA reception */ SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); 8004290: 687b ldr r3, [r7, #4] 8004292: 681b ldr r3, [r3, #0] 8004294: f503 5380 add.w r3, r3, #4096 ; 0x1000 8004298: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 800429c: 687a ldr r2, [r7, #4] 800429e: 6812 ldr r2, [r2, #0] 80042a0: f043 0301 orr.w r3, r3, #1 80042a4: f502 5280 add.w r2, r2, #4096 ; 0x1000 80042a8: f8c2 3108 str.w r3, [r2, #264] ; 0x108 /* Clear Tx and Rx process stopped flags */ heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS); 80042ac: 687b ldr r3, [r7, #4] 80042ae: 681b ldr r3, [r3, #0] 80042b0: f503 5380 add.w r3, r3, #4096 ; 0x1000 80042b4: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 80042b8: 687a ldr r2, [r7, #4] 80042ba: 6812 ldr r2, [r2, #0] 80042bc: f443 7381 orr.w r3, r3, #258 ; 0x102 80042c0: f502 5280 add.w r2, r2, #4096 ; 0x1000 80042c4: f8c2 3160 str.w r3, [r2, #352] ; 0x160 /* Enable ETH DMA interrupts: - Tx complete interrupt - Rx complete interrupt - Fatal bus interrupt */ __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE | 80042c8: 687b ldr r3, [r7, #4] 80042ca: 681b ldr r3, [r3, #0] 80042cc: f503 5380 add.w r3, r3, #4096 ; 0x1000 80042d0: f8d3 1134 ldr.w r1, [r3, #308] ; 0x134 80042d4: 687b ldr r3, [r7, #4] 80042d6: 681a ldr r2, [r3, #0] 80042d8: f24d 03c1 movw r3, #53441 ; 0xd0c1 80042dc: 430b orrs r3, r1 80042de: f502 5280 add.w r2, r2, #4096 ; 0x1000 80042e2: f8c2 3134 str.w r3, [r2, #308] ; 0x134 ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE)); heth->gState = HAL_ETH_STATE_STARTED; 80042e6: 687b ldr r3, [r7, #4] 80042e8: 2223 movs r2, #35 ; 0x23 80042ea: f8c3 2084 str.w r2, [r3, #132] ; 0x84 return HAL_OK; 80042ee: 2300 movs r3, #0 80042f0: e000 b.n 80042f4 } else { return HAL_ERROR; 80042f2: 2301 movs r3, #1 } } 80042f4: 4618 mov r0, r3 80042f6: 3708 adds r7, #8 80042f8: 46bd mov sp, r7 80042fa: bd80 pop {r7, pc} 80042fc: 0c020060 .word 0x0c020060 8004300: 0c20c000 .word 0x0c20c000 08004304 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) { 8004304: b480 push {r7} 8004306: b085 sub sp, #20 8004308: af00 add r7, sp, #0 800430a: 6078 str r0, [r7, #4] ETH_DMADescTypeDef *dmarxdesc; uint32_t descindex; if (heth->gState == HAL_ETH_STATE_STARTED) 800430c: 687b ldr r3, [r7, #4] 800430e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8004312: 2b23 cmp r3, #35 ; 0x23 8004314: d165 bne.n 80043e2 { /* Set the ETH peripheral state to BUSY */ heth->gState = HAL_ETH_STATE_BUSY; 8004316: 687b ldr r3, [r7, #4] 8004318: 2223 movs r2, #35 ; 0x23 800431a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Disable interrupts: - Tx complete interrupt - Rx complete interrupt - Fatal bus interrupt */ __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE | 800431e: 687b ldr r3, [r7, #4] 8004320: 681b ldr r3, [r3, #0] 8004322: f503 5380 add.w r3, r3, #4096 ; 0x1000 8004326: f8d3 1134 ldr.w r1, [r3, #308] ; 0x134 800432a: 687b ldr r3, [r7, #4] 800432c: 681a ldr r2, [r3, #0] 800432e: 4b30 ldr r3, [pc, #192] ; (80043f0 ) 8004330: 400b ands r3, r1 8004332: f502 5280 add.w r2, r2, #4096 ; 0x1000 8004336: f8c2 3134 str.w r3, [r2, #308] ; 0x134 ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE)); /* Disable the DMA transmission */ CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); 800433a: 687b ldr r3, [r7, #4] 800433c: 681b ldr r3, [r3, #0] 800433e: f503 5380 add.w r3, r3, #4096 ; 0x1000 8004342: f8d3 3104 ldr.w r3, [r3, #260] ; 0x104 8004346: 687a ldr r2, [r7, #4] 8004348: 6812 ldr r2, [r2, #0] 800434a: f023 0301 bic.w r3, r3, #1 800434e: f502 5280 add.w r2, r2, #4096 ; 0x1000 8004352: f8c2 3104 str.w r3, [r2, #260] ; 0x104 /* Disable the DMA reception */ CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); 8004356: 687b ldr r3, [r7, #4] 8004358: 681b ldr r3, [r3, #0] 800435a: f503 5380 add.w r3, r3, #4096 ; 0x1000 800435e: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 8004362: 687a ldr r2, [r7, #4] 8004364: 6812 ldr r2, [r2, #0] 8004366: f023 0301 bic.w r3, r3, #1 800436a: f502 5280 add.w r2, r2, #4096 ; 0x1000 800436e: f8c2 3108 str.w r3, [r2, #264] ; 0x108 /* Disable the MAC reception */ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); 8004372: 687b ldr r3, [r7, #4] 8004374: 681b ldr r3, [r3, #0] 8004376: 681a ldr r2, [r3, #0] 8004378: 687b ldr r3, [r7, #4] 800437a: 681b ldr r3, [r3, #0] 800437c: f022 0201 bic.w r2, r2, #1 8004380: 601a str r2, [r3, #0] /* Set the Flush Transmit FIFO bit */ SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); 8004382: 687b ldr r3, [r7, #4] 8004384: 681b ldr r3, [r3, #0] 8004386: f8d3 2d00 ldr.w r2, [r3, #3328] ; 0xd00 800438a: 687b ldr r3, [r7, #4] 800438c: 681b ldr r3, [r3, #0] 800438e: f042 0201 orr.w r2, r2, #1 8004392: f8c3 2d00 str.w r2, [r3, #3328] ; 0xd00 /* Disable the MAC transmission */ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); 8004396: 687b ldr r3, [r7, #4] 8004398: 681b ldr r3, [r3, #0] 800439a: 681a ldr r2, [r3, #0] 800439c: 687b ldr r3, [r7, #4] 800439e: 681b ldr r3, [r3, #0] 80043a0: f022 0202 bic.w r2, r2, #2 80043a4: 601a str r2, [r3, #0] /* Clear IOC bit to all Rx descriptors */ for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) 80043a6: 2300 movs r3, #0 80043a8: 60fb str r3, [r7, #12] 80043aa: e00e b.n 80043ca { dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex]; 80043ac: 687b ldr r3, [r7, #4] 80043ae: 68fa ldr r2, [r7, #12] 80043b0: 3212 adds r2, #18 80043b2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80043b6: 60bb str r3, [r7, #8] CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC); 80043b8: 68bb ldr r3, [r7, #8] 80043ba: 68db ldr r3, [r3, #12] 80043bc: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000 80043c0: 68bb ldr r3, [r7, #8] 80043c2: 60da str r2, [r3, #12] for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) 80043c4: 68fb ldr r3, [r7, #12] 80043c6: 3301 adds r3, #1 80043c8: 60fb str r3, [r7, #12] 80043ca: 68fb ldr r3, [r7, #12] 80043cc: 2b03 cmp r3, #3 80043ce: d9ed bls.n 80043ac } heth->RxDescList.ItMode = 0U; 80043d0: 687b ldr r3, [r7, #4] 80043d2: 2200 movs r2, #0 80043d4: 659a str r2, [r3, #88] ; 0x58 heth->gState = HAL_ETH_STATE_READY; 80043d6: 687b ldr r3, [r7, #4] 80043d8: 2210 movs r2, #16 80043da: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Return function status */ return HAL_OK; 80043de: 2300 movs r3, #0 80043e0: e000 b.n 80043e4 } else { return HAL_ERROR; 80043e2: 2301 movs r3, #1 } } 80043e4: 4618 mov r0, r3 80043e6: 3714 adds r7, #20 80043e8: 46bd mov sp, r7 80043ea: f85d 7b04 ldr.w r7, [sp], #4 80043ee: 4770 bx lr 80043f0: ffff2f3e .word 0xffff2f3e 080043f4 : * the configuration information for ETHERNET module * @param pTxConfig: Hold the configuration of packet to be transmitted * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig) { 80043f4: b580 push {r7, lr} 80043f6: b082 sub sp, #8 80043f8: af00 add r7, sp, #0 80043fa: 6078 str r0, [r7, #4] 80043fc: 6039 str r1, [r7, #0] if (pTxConfig == NULL) 80043fe: 683b ldr r3, [r7, #0] 8004400: 2b00 cmp r3, #0 8004402: d109 bne.n 8004418 { heth->ErrorCode |= HAL_ETH_ERROR_PARAM; 8004404: 687b ldr r3, [r7, #4] 8004406: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 800440a: f043 0201 orr.w r2, r3, #1 800440e: 687b ldr r3, [r7, #4] 8004410: f8c3 2088 str.w r2, [r3, #136] ; 0x88 return HAL_ERROR; 8004414: 2301 movs r3, #1 8004416: e03a b.n 800448e } if (heth->gState == HAL_ETH_STATE_STARTED) 8004418: 687b ldr r3, [r7, #4] 800441a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 800441e: 2b23 cmp r3, #35 ; 0x23 8004420: d134 bne.n 800448c { /* Save the packet pointer to release. */ heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData; 8004422: 683b ldr r3, [r7, #0] 8004424: 6b5a ldr r2, [r3, #52] ; 0x34 8004426: 687b ldr r3, [r7, #4] 8004428: 63da str r2, [r3, #60] ; 0x3c /* Config DMA Tx descriptor by Tx Packet info */ if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE) 800442a: 2201 movs r2, #1 800442c: 6839 ldr r1, [r7, #0] 800442e: 6878 ldr r0, [r7, #4] 8004430: f001 f8ca bl 80055c8 8004434: 4603 mov r3, r0 8004436: 2b00 cmp r3, #0 8004438: d009 beq.n 800444e { heth->ErrorCode |= HAL_ETH_ERROR_BUSY; 800443a: 687b ldr r3, [r7, #4] 800443c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8004440: f043 0202 orr.w r2, r3, #2 8004444: 687b ldr r3, [r7, #4] 8004446: f8c3 2088 str.w r2, [r3, #136] ; 0x88 return HAL_ERROR; 800444a: 2301 movs r3, #1 800444c: e01f b.n 800448e __ASM volatile ("dsb 0xF":::"memory"); 800444e: f3bf 8f4f dsb sy } 8004452: bf00 nop /* Ensure completion of descriptor preparation before transmission start */ __DSB(); /* Incr current tx desc index */ INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); 8004454: 687b ldr r3, [r7, #4] 8004456: 6a9b ldr r3, [r3, #40] ; 0x28 8004458: 1c5a adds r2, r3, #1 800445a: 687b ldr r3, [r7, #4] 800445c: 629a str r2, [r3, #40] ; 0x28 800445e: 687b ldr r3, [r7, #4] 8004460: 6a9b ldr r3, [r3, #40] ; 0x28 8004462: 2b03 cmp r3, #3 8004464: d904 bls.n 8004470 8004466: 687b ldr r3, [r7, #4] 8004468: 6a9b ldr r3, [r3, #40] ; 0x28 800446a: 1f1a subs r2, r3, #4 800446c: 687b ldr r3, [r7, #4] 800446e: 629a str r2, [r3, #40] ; 0x28 /* Start transmission */ /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); 8004470: 687b ldr r3, [r7, #4] 8004472: 6a99 ldr r1, [r3, #40] ; 0x28 8004474: 687b ldr r3, [r7, #4] 8004476: 681a ldr r2, [r3, #0] 8004478: 687b ldr r3, [r7, #4] 800447a: 3106 adds r1, #6 800447c: f853 3021 ldr.w r3, [r3, r1, lsl #2] 8004480: f502 5280 add.w r2, r2, #4096 ; 0x1000 8004484: f8c2 3120 str.w r3, [r2, #288] ; 0x120 return HAL_OK; 8004488: 2300 movs r3, #0 800448a: e000 b.n 800448e } else { return HAL_ERROR; 800448c: 2301 movs r3, #1 } } 800448e: 4618 mov r0, r3 8004490: 3708 adds r7, #8 8004492: 46bd mov sp, r7 8004494: bd80 pop {r7, pc} 08004496 : * the configuration information for ETHERNET module * @param pAppBuff: Pointer to an application buffer to receive the packet. * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) { 8004496: b580 push {r7, lr} 8004498: b088 sub sp, #32 800449a: af00 add r7, sp, #0 800449c: 6078 str r0, [r7, #4] 800449e: 6039 str r1, [r7, #0] uint32_t descidx; ETH_DMADescTypeDef *dmarxdesc; uint32_t desccnt = 0U; 80044a0: 2300 movs r3, #0 80044a2: 617b str r3, [r7, #20] uint32_t desccntmax; uint32_t bufflength; uint8_t rxdataready = 0U; 80044a4: 2300 movs r3, #0 80044a6: 73fb strb r3, [r7, #15] if (pAppBuff == NULL) 80044a8: 683b ldr r3, [r7, #0] 80044aa: 2b00 cmp r3, #0 80044ac: d109 bne.n 80044c2 { heth->ErrorCode |= HAL_ETH_ERROR_PARAM; 80044ae: 687b ldr r3, [r7, #4] 80044b0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80044b4: f043 0201 orr.w r2, r3, #1 80044b8: 687b ldr r3, [r7, #4] 80044ba: f8c3 2088 str.w r2, [r3, #136] ; 0x88 return HAL_ERROR; 80044be: 2301 movs r3, #1 80044c0: e0a5 b.n 800460e } if (heth->gState != HAL_ETH_STATE_STARTED) 80044c2: 687b ldr r3, [r7, #4] 80044c4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80044c8: 2b23 cmp r3, #35 ; 0x23 80044ca: d001 beq.n 80044d0 { return HAL_ERROR; 80044cc: 2301 movs r3, #1 80044ce: e09e b.n 800460e } descidx = heth->RxDescList.RxDescIdx; 80044d0: 687b ldr r3, [r7, #4] 80044d2: 6ddb ldr r3, [r3, #92] ; 0x5c 80044d4: 61fb str r3, [r7, #28] dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; 80044d6: 687b ldr r3, [r7, #4] 80044d8: 69fa ldr r2, [r7, #28] 80044da: 3212 adds r2, #18 80044dc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80044e0: 61bb str r3, [r7, #24] desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt; 80044e2: 687b ldr r3, [r7, #4] 80044e4: 6edb ldr r3, [r3, #108] ; 0x6c 80044e6: f1c3 0304 rsb r3, r3, #4 80044ea: 60bb str r3, [r7, #8] /* Check if descriptor is not owned by DMA */ while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) 80044ec: e067 b.n 80045be && (rxdataready == 0U)) { if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET) 80044ee: 69bb ldr r3, [r7, #24] 80044f0: 68db ldr r3, [r3, #12] 80044f2: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 80044f6: 2b00 cmp r3, #0 80044f8: d007 beq.n 800450a { /* Get timestamp high */ heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1; 80044fa: 69bb ldr r3, [r7, #24] 80044fc: 685a ldr r2, [r3, #4] 80044fe: 687b ldr r3, [r7, #4] 8004500: 679a str r2, [r3, #120] ; 0x78 /* Get timestamp low */ heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC0; 8004502: 69bb ldr r3, [r7, #24] 8004504: 681a ldr r2, [r3, #0] 8004506: 687b ldr r3, [r7, #4] 8004508: 675a str r2, [r3, #116] ; 0x74 } if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) 800450a: 69bb ldr r3, [r7, #24] 800450c: 68db ldr r3, [r3, #12] 800450e: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8004512: 2b00 cmp r3, #0 8004514: d103 bne.n 800451e 8004516: 687b ldr r3, [r7, #4] 8004518: 6fdb ldr r3, [r3, #124] ; 0x7c 800451a: 2b00 cmp r3, #0 800451c: d03d beq.n 800459a { /* Check if first descriptor */ if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) 800451e: 69bb ldr r3, [r7, #24] 8004520: 68db ldr r3, [r3, #12] 8004522: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8004526: 2b00 cmp r3, #0 8004528: d005 beq.n 8004536 { heth->RxDescList.RxDescCnt = 0; 800452a: 687b ldr r3, [r7, #4] 800452c: 2200 movs r2, #0 800452e: 661a str r2, [r3, #96] ; 0x60 heth->RxDescList.RxDataLength = 0; 8004530: 687b ldr r3, [r7, #4] 8004532: 2200 movs r2, #0 8004534: 665a str r2, [r3, #100] ; 0x64 } /* Check if last descriptor */ bufflength = heth->Init.RxBuffLen; 8004536: 687b ldr r3, [r7, #4] 8004538: 695b ldr r3, [r3, #20] 800453a: 613b str r3, [r7, #16] if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET) 800453c: 69bb ldr r3, [r7, #24] 800453e: 68db ldr r3, [r3, #12] 8004540: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8004544: 2b00 cmp r3, #0 8004546: d00d beq.n 8004564 { bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; 8004548: 69bb ldr r3, [r7, #24] 800454a: 68db ldr r3, [r3, #12] 800454c: f3c3 020e ubfx r2, r3, #0, #15 8004550: 687b ldr r3, [r7, #4] 8004552: 6e5b ldr r3, [r3, #100] ; 0x64 8004554: 1ad3 subs r3, r2, r3 8004556: 613b str r3, [r7, #16] /* Save Last descriptor index */ heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3; 8004558: 69bb ldr r3, [r7, #24] 800455a: 68da ldr r2, [r3, #12] 800455c: 687b ldr r3, [r7, #4] 800455e: 671a str r2, [r3, #112] ; 0x70 /* Packet ready */ rxdataready = 1; 8004560: 2301 movs r3, #1 8004562: 73fb strb r3, [r7, #15] /*Call registered Link callback*/ heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, (uint8_t *)dmarxdesc->BackupAddr0, bufflength); #else /* Link callback */ HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, 8004564: 687b ldr r3, [r7, #4] 8004566: f103 007c add.w r0, r3, #124 ; 0x7c 800456a: 687b ldr r3, [r7, #4] 800456c: f103 0180 add.w r1, r3, #128 ; 0x80 (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); 8004570: 69bb ldr r3, [r7, #24] 8004572: 691b ldr r3, [r3, #16] HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, 8004574: 461a mov r2, r3 8004576: 693b ldr r3, [r7, #16] 8004578: b29b uxth r3, r3 800457a: f00b fd99 bl 80100b0 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ heth->RxDescList.RxDescCnt++; 800457e: 687b ldr r3, [r7, #4] 8004580: 6e1b ldr r3, [r3, #96] ; 0x60 8004582: 1c5a adds r2, r3, #1 8004584: 687b ldr r3, [r7, #4] 8004586: 661a str r2, [r3, #96] ; 0x60 heth->RxDescList.RxDataLength += bufflength; 8004588: 687b ldr r3, [r7, #4] 800458a: 6e5a ldr r2, [r3, #100] ; 0x64 800458c: 693b ldr r3, [r7, #16] 800458e: 441a add r2, r3 8004590: 687b ldr r3, [r7, #4] 8004592: 665a str r2, [r3, #100] ; 0x64 /* Clear buffer pointer */ dmarxdesc->BackupAddr0 = 0; 8004594: 69bb ldr r3, [r7, #24] 8004596: 2200 movs r2, #0 8004598: 611a str r2, [r3, #16] } /* Increment current rx descriptor index */ INCR_RX_DESC_INDEX(descidx, 1U); 800459a: 69fb ldr r3, [r7, #28] 800459c: 3301 adds r3, #1 800459e: 61fb str r3, [r7, #28] 80045a0: 69fb ldr r3, [r7, #28] 80045a2: 2b03 cmp r3, #3 80045a4: d902 bls.n 80045ac 80045a6: 69fb ldr r3, [r7, #28] 80045a8: 3b04 subs r3, #4 80045aa: 61fb str r3, [r7, #28] /* Get current descriptor address */ dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; 80045ac: 687b ldr r3, [r7, #4] 80045ae: 69fa ldr r2, [r7, #28] 80045b0: 3212 adds r2, #18 80045b2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80045b6: 61bb str r3, [r7, #24] desccnt++; 80045b8: 697b ldr r3, [r7, #20] 80045ba: 3301 adds r3, #1 80045bc: 617b str r3, [r7, #20] while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) 80045be: 69bb ldr r3, [r7, #24] 80045c0: 68db ldr r3, [r3, #12] && (rxdataready == 0U)) 80045c2: 2b00 cmp r3, #0 80045c4: db06 blt.n 80045d4 while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) 80045c6: 697a ldr r2, [r7, #20] 80045c8: 68bb ldr r3, [r7, #8] 80045ca: 429a cmp r2, r3 80045cc: d202 bcs.n 80045d4 && (rxdataready == 0U)) 80045ce: 7bfb ldrb r3, [r7, #15] 80045d0: 2b00 cmp r3, #0 80045d2: d08c beq.n 80044ee } heth->RxDescList.RxBuildDescCnt += desccnt; 80045d4: 687b ldr r3, [r7, #4] 80045d6: 6eda ldr r2, [r3, #108] ; 0x6c 80045d8: 697b ldr r3, [r7, #20] 80045da: 441a add r2, r3 80045dc: 687b ldr r3, [r7, #4] 80045de: 66da str r2, [r3, #108] ; 0x6c if ((heth->RxDescList.RxBuildDescCnt) != 0U) 80045e0: 687b ldr r3, [r7, #4] 80045e2: 6edb ldr r3, [r3, #108] ; 0x6c 80045e4: 2b00 cmp r3, #0 80045e6: d002 beq.n 80045ee { /* Update Descriptors */ ETH_UpdateDescriptor(heth); 80045e8: 6878 ldr r0, [r7, #4] 80045ea: f000 f814 bl 8004616 } heth->RxDescList.RxDescIdx = descidx; 80045ee: 687b ldr r3, [r7, #4] 80045f0: 69fa ldr r2, [r7, #28] 80045f2: 65da str r2, [r3, #92] ; 0x5c if (rxdataready == 1U) 80045f4: 7bfb ldrb r3, [r7, #15] 80045f6: 2b01 cmp r3, #1 80045f8: d108 bne.n 800460c { /* Return received packet */ *pAppBuff = heth->RxDescList.pRxStart; 80045fa: 687b ldr r3, [r7, #4] 80045fc: 6fda ldr r2, [r3, #124] ; 0x7c 80045fe: 683b ldr r3, [r7, #0] 8004600: 601a str r2, [r3, #0] /* Reset first element */ heth->RxDescList.pRxStart = NULL; 8004602: 687b ldr r3, [r7, #4] 8004604: 2200 movs r2, #0 8004606: 67da str r2, [r3, #124] ; 0x7c return HAL_OK; 8004608: 2300 movs r3, #0 800460a: e000 b.n 800460e } /* Packet not ready */ return HAL_ERROR; 800460c: 2301 movs r3, #1 } 800460e: 4618 mov r0, r3 8004610: 3720 adds r7, #32 8004612: 46bd mov sp, r7 8004614: bd80 pop {r7, pc} 08004616 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) { 8004616: b580 push {r7, lr} 8004618: b088 sub sp, #32 800461a: af00 add r7, sp, #0 800461c: 6078 str r0, [r7, #4] uint32_t descidx; uint32_t desccount; ETH_DMADescTypeDef *dmarxdesc; uint8_t *buff = NULL; 800461e: 2300 movs r3, #0 8004620: 60fb str r3, [r7, #12] uint8_t allocStatus = 1U; 8004622: 2301 movs r3, #1 8004624: 74fb strb r3, [r7, #19] descidx = heth->RxDescList.RxBuildDescIdx; 8004626: 687b ldr r3, [r7, #4] 8004628: 6e9b ldr r3, [r3, #104] ; 0x68 800462a: 61fb str r3, [r7, #28] dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; 800462c: 687b ldr r3, [r7, #4] 800462e: 69fa ldr r2, [r7, #28] 8004630: 3212 adds r2, #18 8004632: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8004636: 617b str r3, [r7, #20] desccount = heth->RxDescList.RxBuildDescCnt; 8004638: 687b ldr r3, [r7, #4] 800463a: 6edb ldr r3, [r3, #108] ; 0x6c 800463c: 61bb str r3, [r7, #24] while ((desccount > 0U) && (allocStatus != 0U)) 800463e: e03b b.n 80046b8 { /* Check if a buffer's attached the descriptor */ if (READ_REG(dmarxdesc->BackupAddr0) == 0U) 8004640: 697b ldr r3, [r7, #20] 8004642: 691b ldr r3, [r3, #16] 8004644: 2b00 cmp r3, #0 8004646: d112 bne.n 800466e #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /*Call registered Allocate callback*/ heth->rxAllocateCallback(&buff); #else /* Allocate callback */ HAL_ETH_RxAllocateCallback(&buff); 8004648: f107 030c add.w r3, r7, #12 800464c: 4618 mov r0, r3 800464e: f00b fcff bl 8010050 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ if (buff == NULL) 8004652: 68fb ldr r3, [r7, #12] 8004654: 2b00 cmp r3, #0 8004656: d102 bne.n 800465e { allocStatus = 0U; 8004658: 2300 movs r3, #0 800465a: 74fb strb r3, [r7, #19] 800465c: e007 b.n 800466e } else { WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff); 800465e: 68fb ldr r3, [r7, #12] 8004660: 461a mov r2, r3 8004662: 697b ldr r3, [r7, #20] 8004664: 611a str r2, [r3, #16] WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff); 8004666: 68fb ldr r3, [r7, #12] 8004668: 461a mov r2, r3 800466a: 697b ldr r3, [r7, #20] 800466c: 601a str r2, [r3, #0] } } if (allocStatus != 0U) 800466e: 7cfb ldrb r3, [r7, #19] 8004670: 2b00 cmp r3, #0 8004672: d021 beq.n 80046b8 __ASM volatile ("dmb 0xF":::"memory"); 8004674: f3bf 8f5f dmb sy } 8004678: bf00 nop { /* Ensure rest of descriptor is written to RAM before the OWN bit */ __DMB(); if (heth->RxDescList.ItMode != 0U) 800467a: 687b ldr r3, [r7, #4] 800467c: 6d9b ldr r3, [r3, #88] ; 0x58 800467e: 2b00 cmp r3, #0 8004680: d004 beq.n 800468c { WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC); 8004682: 697b ldr r3, [r7, #20] 8004684: f04f 4241 mov.w r2, #3238002688 ; 0xc1000000 8004688: 60da str r2, [r3, #12] 800468a: e003 b.n 8004694 } else { WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V); 800468c: 697b ldr r3, [r7, #20] 800468e: f04f 4201 mov.w r2, #2164260864 ; 0x81000000 8004692: 60da str r2, [r3, #12] } /* Increment current rx descriptor index */ INCR_RX_DESC_INDEX(descidx, 1U); 8004694: 69fb ldr r3, [r7, #28] 8004696: 3301 adds r3, #1 8004698: 61fb str r3, [r7, #28] 800469a: 69fb ldr r3, [r7, #28] 800469c: 2b03 cmp r3, #3 800469e: d902 bls.n 80046a6 80046a0: 69fb ldr r3, [r7, #28] 80046a2: 3b04 subs r3, #4 80046a4: 61fb str r3, [r7, #28] /* Get current descriptor address */ dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; 80046a6: 687b ldr r3, [r7, #4] 80046a8: 69fa ldr r2, [r7, #28] 80046aa: 3212 adds r2, #18 80046ac: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80046b0: 617b str r3, [r7, #20] desccount--; 80046b2: 69bb ldr r3, [r7, #24] 80046b4: 3b01 subs r3, #1 80046b6: 61bb str r3, [r7, #24] while ((desccount > 0U) && (allocStatus != 0U)) 80046b8: 69bb ldr r3, [r7, #24] 80046ba: 2b00 cmp r3, #0 80046bc: d002 beq.n 80046c4 80046be: 7cfb ldrb r3, [r7, #19] 80046c0: 2b00 cmp r3, #0 80046c2: d1bd bne.n 8004640 } } if (heth->RxDescList.RxBuildDescCnt != desccount) 80046c4: 687b ldr r3, [r7, #4] 80046c6: 6edb ldr r3, [r3, #108] ; 0x6c 80046c8: 69ba ldr r2, [r7, #24] 80046ca: 429a cmp r2, r3 80046cc: d00d beq.n 80046ea { /* Set the Tail pointer address */ WRITE_REG(heth->Instance->DMACRDTPR, 0); 80046ce: 687b ldr r3, [r7, #4] 80046d0: 681b ldr r3, [r3, #0] 80046d2: f503 5380 add.w r3, r3, #4096 ; 0x1000 80046d6: 461a mov r2, r3 80046d8: 2300 movs r3, #0 80046da: f8c2 3128 str.w r3, [r2, #296] ; 0x128 heth->RxDescList.RxBuildDescIdx = descidx; 80046de: 687b ldr r3, [r7, #4] 80046e0: 69fa ldr r2, [r7, #28] 80046e2: 669a str r2, [r3, #104] ; 0x68 heth->RxDescList.RxBuildDescCnt = desccount; 80046e4: 687b ldr r3, [r7, #4] 80046e6: 69ba ldr r2, [r7, #24] 80046e8: 66da str r2, [r3, #108] ; 0x6c } } 80046ea: bf00 nop 80046ec: 3720 adds r7, #32 80046ee: 46bd mov sp, r7 80046f0: bd80 pop {r7, pc} 080046f2 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) { 80046f2: b580 push {r7, lr} 80046f4: b086 sub sp, #24 80046f6: af00 add r7, sp, #0 80046f8: 6078 str r0, [r7, #4] ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; 80046fa: 687b ldr r3, [r7, #4] 80046fc: 3318 adds r3, #24 80046fe: 60bb str r3, [r7, #8] uint32_t numOfBuf = dmatxdesclist->BuffersInUse; 8004700: 68bb ldr r3, [r7, #8] 8004702: 6a9b ldr r3, [r3, #40] ; 0x28 8004704: 617b str r3, [r7, #20] uint32_t idx = dmatxdesclist->releaseIndex; 8004706: 68bb ldr r3, [r7, #8] 8004708: 6adb ldr r3, [r3, #44] ; 0x2c 800470a: 613b str r3, [r7, #16] uint8_t pktTxStatus = 1U; 800470c: 2301 movs r3, #1 800470e: 73fb strb r3, [r7, #15] #ifdef HAL_ETH_USE_PTP ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp; #endif /* HAL_ETH_USE_PTP */ /* Loop through buffers in use. */ while ((numOfBuf != 0U) && (pktTxStatus != 0U)) 8004710: e03f b.n 8004792 { pktInUse = 1U; 8004712: 2301 movs r3, #1 8004714: 73bb strb r3, [r7, #14] numOfBuf--; 8004716: 697b ldr r3, [r7, #20] 8004718: 3b01 subs r3, #1 800471a: 617b str r3, [r7, #20] /* If no packet, just examine the next packet. */ if (dmatxdesclist->PacketAddress[idx] == NULL) 800471c: 68ba ldr r2, [r7, #8] 800471e: 693b ldr r3, [r7, #16] 8004720: 3304 adds r3, #4 8004722: 009b lsls r3, r3, #2 8004724: 4413 add r3, r2 8004726: 685b ldr r3, [r3, #4] 8004728: 2b00 cmp r3, #0 800472a: d106 bne.n 800473a { /* No packet in use, skip to next. */ idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); 800472c: 693b ldr r3, [r7, #16] 800472e: 3301 adds r3, #1 8004730: f003 0303 and.w r3, r3, #3 8004734: 613b str r3, [r7, #16] pktInUse = 0U; 8004736: 2300 movs r3, #0 8004738: 73bb strb r3, [r7, #14] } if (pktInUse != 0U) 800473a: 7bbb ldrb r3, [r7, #14] 800473c: 2b00 cmp r3, #0 800473e: d028 beq.n 8004792 { /* Determine if the packet has been transmitted. */ if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U) 8004740: 687b ldr r3, [r7, #4] 8004742: 68d9 ldr r1, [r3, #12] 8004744: 693a ldr r2, [r7, #16] 8004746: 4613 mov r3, r2 8004748: 005b lsls r3, r3, #1 800474a: 4413 add r3, r2 800474c: 00db lsls r3, r3, #3 800474e: 440b add r3, r1 8004750: 68db ldr r3, [r3, #12] 8004752: 2b00 cmp r3, #0 8004754: db1b blt.n 800478e #ifdef HAL_ETH_USE_PTP /* Handle Ptp */ HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); #endif /* HAL_ETH_USE_PTP */ /* Release the packet. */ HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); 8004756: 68ba ldr r2, [r7, #8] 8004758: 693b ldr r3, [r7, #16] 800475a: 3304 adds r3, #4 800475c: 009b lsls r3, r3, #2 800475e: 4413 add r3, r2 8004760: 685b ldr r3, [r3, #4] 8004762: 4618 mov r0, r3 8004764: f00b fd0c bl 8010180 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ /* Clear the entry in the in-use array. */ dmatxdesclist->PacketAddress[idx] = NULL; 8004768: 68ba ldr r2, [r7, #8] 800476a: 693b ldr r3, [r7, #16] 800476c: 3304 adds r3, #4 800476e: 009b lsls r3, r3, #2 8004770: 4413 add r3, r2 8004772: 2200 movs r2, #0 8004774: 605a str r2, [r3, #4] /* Update the transmit relesae index and number of buffers in use. */ idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); 8004776: 693b ldr r3, [r7, #16] 8004778: 3301 adds r3, #1 800477a: f003 0303 and.w r3, r3, #3 800477e: 613b str r3, [r7, #16] dmatxdesclist->BuffersInUse = numOfBuf; 8004780: 68bb ldr r3, [r7, #8] 8004782: 697a ldr r2, [r7, #20] 8004784: 629a str r2, [r3, #40] ; 0x28 dmatxdesclist->releaseIndex = idx; 8004786: 68bb ldr r3, [r7, #8] 8004788: 693a ldr r2, [r7, #16] 800478a: 62da str r2, [r3, #44] ; 0x2c 800478c: e001 b.n 8004792 } else { /* Get out of the loop! */ pktTxStatus = 0U; 800478e: 2300 movs r3, #0 8004790: 73fb strb r3, [r7, #15] while ((numOfBuf != 0U) && (pktTxStatus != 0U)) 8004792: 697b ldr r3, [r7, #20] 8004794: 2b00 cmp r3, #0 8004796: d002 beq.n 800479e 8004798: 7bfb ldrb r3, [r7, #15] 800479a: 2b00 cmp r3, #0 800479c: d1b9 bne.n 8004712 } } } return HAL_OK; 800479e: 2300 movs r3, #0 } 80047a0: 4618 mov r0, r3 80047a2: 3718 adds r7, #24 80047a4: 46bd mov sp, r7 80047a6: bd80 pop {r7, pc} 080047a8 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) { 80047a8: b580 push {r7, lr} 80047aa: b084 sub sp, #16 80047ac: af00 add r7, sp, #0 80047ae: 6078 str r0, [r7, #4] uint32_t macirqenable; /* Packet received */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI)) 80047b0: 687b ldr r3, [r7, #4] 80047b2: 681b ldr r3, [r3, #0] 80047b4: f503 5380 add.w r3, r3, #4096 ; 0x1000 80047b8: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 80047bc: f003 0340 and.w r3, r3, #64 ; 0x40 80047c0: 2b40 cmp r3, #64 ; 0x40 80047c2: d115 bne.n 80047f0 { if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE)) 80047c4: 687b ldr r3, [r7, #4] 80047c6: 681b ldr r3, [r3, #0] 80047c8: f503 5380 add.w r3, r3, #4096 ; 0x1000 80047cc: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 80047d0: f003 0340 and.w r3, r3, #64 ; 0x40 80047d4: 2b40 cmp r3, #64 ; 0x40 80047d6: d10b bne.n 80047f0 { /* Clear the Eth DMA Rx IT pending bits */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS); 80047d8: 687b ldr r3, [r7, #4] 80047da: 681b ldr r3, [r3, #0] 80047dc: f503 5380 add.w r3, r3, #4096 ; 0x1000 80047e0: 461a mov r2, r3 80047e2: f248 0340 movw r3, #32832 ; 0x8040 80047e6: f8c2 3160 str.w r3, [r2, #352] ; 0x160 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /*Call registered Receive complete callback*/ heth->RxCpltCallback(heth); #else /* Receive complete callback */ HAL_ETH_RxCpltCallback(heth); 80047ea: 6878 ldr r0, [r7, #4] 80047ec: f00a ffea bl 800f7c4 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ } } /* Packet transmitted */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI)) 80047f0: 687b ldr r3, [r7, #4] 80047f2: 681b ldr r3, [r3, #0] 80047f4: f503 5380 add.w r3, r3, #4096 ; 0x1000 80047f8: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 80047fc: f003 0301 and.w r3, r3, #1 8004800: 2b01 cmp r3, #1 8004802: d115 bne.n 8004830 { if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE)) 8004804: 687b ldr r3, [r7, #4] 8004806: 681b ldr r3, [r3, #0] 8004808: f503 5380 add.w r3, r3, #4096 ; 0x1000 800480c: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8004810: f003 0301 and.w r3, r3, #1 8004814: 2b01 cmp r3, #1 8004816: d10b bne.n 8004830 { /* Clear the Eth DMA Tx IT pending bits */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS); 8004818: 687b ldr r3, [r7, #4] 800481a: 681b ldr r3, [r3, #0] 800481c: f503 5380 add.w r3, r3, #4096 ; 0x1000 8004820: 461a mov r2, r3 8004822: f248 0301 movw r3, #32769 ; 0x8001 8004826: f8c2 3160 str.w r3, [r2, #352] ; 0x160 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /*Call registered Transmit complete callback*/ heth->TxCpltCallback(heth); #else /* Transfer complete callback */ HAL_ETH_TxCpltCallback(heth); 800482a: 6878 ldr r0, [r7, #4] 800482c: f00a ffda bl 800f7e4 } } /* ETH DMA Error */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS)) 8004830: 687b ldr r3, [r7, #4] 8004832: 681b ldr r3, [r3, #0] 8004834: f503 5380 add.w r3, r3, #4096 ; 0x1000 8004838: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 800483c: f403 4380 and.w r3, r3, #16384 ; 0x4000 8004840: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8004844: d153 bne.n 80048ee { if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE)) 8004846: 687b ldr r3, [r7, #4] 8004848: 681b ldr r3, [r3, #0] 800484a: f503 5380 add.w r3, r3, #4096 ; 0x1000 800484e: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8004852: f403 4380 and.w r3, r3, #16384 ; 0x4000 8004856: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 800485a: d148 bne.n 80048ee { heth->ErrorCode |= HAL_ETH_ERROR_DMA; 800485c: 687b ldr r3, [r7, #4] 800485e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8004862: f043 0208 orr.w r2, r3, #8 8004866: 687b ldr r3, [r7, #4] 8004868: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* if fatal bus error occurred */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE)) 800486c: 687b ldr r3, [r7, #4] 800486e: 681b ldr r3, [r3, #0] 8004870: f503 5380 add.w r3, r3, #4096 ; 0x1000 8004874: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 8004878: f403 5380 and.w r3, r3, #4096 ; 0x1000 800487c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004880: d11e bne.n 80048c0 { /* Get DMA error code */ heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS)); 8004882: 687b ldr r3, [r7, #4] 8004884: 681b ldr r3, [r3, #0] 8004886: f503 5380 add.w r3, r3, #4096 ; 0x1000 800488a: f8d3 2160 ldr.w r2, [r3, #352] ; 0x160 800488e: f241 1302 movw r3, #4354 ; 0x1102 8004892: 4013 ands r3, r2 8004894: 687a ldr r2, [r7, #4] 8004896: f8c2 308c str.w r3, [r2, #140] ; 0x8c /* Disable all interrupts */ __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE); 800489a: 687b ldr r3, [r7, #4] 800489c: 681b ldr r3, [r3, #0] 800489e: f503 5380 add.w r3, r3, #4096 ; 0x1000 80048a2: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 80048a6: 687a ldr r2, [r7, #4] 80048a8: 6812 ldr r2, [r2, #0] 80048aa: f423 4340 bic.w r3, r3, #49152 ; 0xc000 80048ae: f502 5280 add.w r2, r2, #4096 ; 0x1000 80048b2: f8c2 3134 str.w r3, [r2, #308] ; 0x134 /* Set HAL state to ERROR */ heth->gState = HAL_ETH_STATE_ERROR; 80048b6: 687b ldr r3, [r7, #4] 80048b8: 22e0 movs r2, #224 ; 0xe0 80048ba: f8c3 2084 str.w r2, [r3, #132] ; 0x84 80048be: e013 b.n 80048e8 } else { /* Get DMA error status */ heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | 80048c0: 687b ldr r3, [r7, #4] 80048c2: 681b ldr r3, [r3, #0] 80048c4: f503 5380 add.w r3, r3, #4096 ; 0x1000 80048c8: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 80048cc: f403 42cd and.w r2, r3, #26240 ; 0x6680 80048d0: 687b ldr r3, [r7, #4] 80048d2: f8c3 208c str.w r2, [r3, #140] ; 0x8c ETH_DMACSR_RBU | ETH_DMACSR_AIS)); /* Clear the interrupt summary flag */ __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | 80048d6: 687b ldr r3, [r7, #4] 80048d8: 681b ldr r3, [r3, #0] 80048da: f503 5380 add.w r3, r3, #4096 ; 0x1000 80048de: 461a mov r2, r3 80048e0: f44f 43cd mov.w r3, #26240 ; 0x6680 80048e4: f8c2 3160 str.w r3, [r2, #352] ; 0x160 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /* Call registered Error callback*/ heth->ErrorCallback(heth); #else /* Ethernet DMA Error callback */ HAL_ETH_ErrorCallback(heth); 80048e8: 6878 ldr r0, [r7, #4] 80048ea: f00a ff8b bl 800f804 } } /* ETH MAC Error IT */ macirqenable = heth->Instance->MACIER; 80048ee: 687b ldr r3, [r7, #4] 80048f0: 681b ldr r3, [r3, #0] 80048f2: f8d3 30b4 ldr.w r3, [r3, #180] ; 0xb4 80048f6: 60fb str r3, [r7, #12] if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \ 80048f8: 68fb ldr r3, [r7, #12] 80048fa: f403 4380 and.w r3, r3, #16384 ; 0x4000 80048fe: 2b00 cmp r3, #0 8004900: d104 bne.n 800490c ((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE)) 8004902: 68fb ldr r3, [r7, #12] 8004904: f403 5300 and.w r3, r3, #8192 ; 0x2000 if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \ 8004908: 2b00 cmp r3, #0 800490a: d019 beq.n 8004940 { heth->ErrorCode |= HAL_ETH_ERROR_MAC; 800490c: 687b ldr r3, [r7, #4] 800490e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8004912: f043 0210 orr.w r2, r3, #16 8004916: 687b ldr r3, [r7, #4] 8004918: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Get MAC Rx Tx status and clear Status register pending bit */ heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR); 800491c: 687b ldr r3, [r7, #4] 800491e: 681b ldr r3, [r3, #0] 8004920: f8d3 20b8 ldr.w r2, [r3, #184] ; 0xb8 8004924: 687b ldr r3, [r7, #4] 8004926: f8c3 2090 str.w r2, [r3, #144] ; 0x90 heth->gState = HAL_ETH_STATE_ERROR; 800492a: 687b ldr r3, [r7, #4] 800492c: 22e0 movs r2, #224 ; 0xe0 800492e: f8c3 2084 str.w r2, [r3, #132] ; 0x84 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /* Call registered Error callback*/ heth->ErrorCallback(heth); #else /* Ethernet Error callback */ HAL_ETH_ErrorCallback(heth); 8004932: 6878 ldr r0, [r7, #4] 8004934: f00a ff66 bl 800f804 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ heth->MACErrorCode = (uint32_t)(0x0U); 8004938: 687b ldr r3, [r7, #4] 800493a: 2200 movs r2, #0 800493c: f8c3 2090 str.w r2, [r3, #144] ; 0x90 } /* ETH PMT IT */ if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT)) 8004940: 687b ldr r3, [r7, #4] 8004942: 681b ldr r3, [r3, #0] 8004944: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8004948: f003 0310 and.w r3, r3, #16 800494c: 2b10 cmp r3, #16 800494e: d10f bne.n 8004970 { /* Get MAC Wake-up source and clear the status register pending bit */ heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD)); 8004950: 687b ldr r3, [r7, #4] 8004952: 681b ldr r3, [r3, #0] 8004954: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0 8004958: f003 0260 and.w r2, r3, #96 ; 0x60 800495c: 687b ldr r3, [r7, #4] 800495e: f8c3 2094 str.w r2, [r3, #148] ; 0x94 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /* Call registered PMT callback*/ heth->PMTCallback(heth); #else /* Ethernet PMT callback */ HAL_ETH_PMTCallback(heth); 8004962: 6878 ldr r0, [r7, #4] 8004964: f000 f830 bl 80049c8 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ heth->MACWakeUpEvent = (uint32_t)(0x0U); 8004968: 687b ldr r3, [r7, #4] 800496a: 2200 movs r2, #0 800496c: f8c3 2094 str.w r2, [r3, #148] ; 0x94 } /* ETH EEE IT */ if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT)) 8004970: 687b ldr r3, [r7, #4] 8004972: 681b ldr r3, [r3, #0] 8004974: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8004978: f003 0320 and.w r3, r3, #32 800497c: 2b20 cmp r3, #32 800497e: d10f bne.n 80049a0 { /* Get MAC LPI interrupt source and clear the status register pending bit */ heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU); 8004980: 687b ldr r3, [r7, #4] 8004982: 681b ldr r3, [r3, #0] 8004984: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0 8004988: f003 020f and.w r2, r3, #15 800498c: 687b ldr r3, [r7, #4] 800498e: f8c3 2098 str.w r2, [r3, #152] ; 0x98 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /* Call registered EEE callback*/ heth->EEECallback(heth); #else /* Ethernet EEE callback */ HAL_ETH_EEECallback(heth); 8004992: 6878 ldr r0, [r7, #4] 8004994: f000 f822 bl 80049dc #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ heth->MACLPIEvent = (uint32_t)(0x0U); 8004998: 687b ldr r3, [r7, #4] 800499a: 2200 movs r2, #0 800499c: f8c3 2098 str.w r2, [r3, #152] ; 0x98 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ } } #else /* USE_HAL_ETH_REGISTER_CALLBACKS */ /* check ETH WAKEUP exti flag */ if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) 80049a0: 4b08 ldr r3, [pc, #32] ; (80049c4 ) 80049a2: 6a9b ldr r3, [r3, #40] ; 0x28 80049a4: f403 0380 and.w r3, r3, #4194304 ; 0x400000 80049a8: 2b00 cmp r3, #0 80049aa: d006 beq.n 80049ba { /* Clear ETH WAKEUP Exti pending bit */ __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); 80049ac: 4b05 ldr r3, [pc, #20] ; (80049c4 ) 80049ae: f44f 0280 mov.w r2, #4194304 ; 0x400000 80049b2: 629a str r2, [r3, #40] ; 0x28 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /* Call registered WakeUp callback*/ heth->WakeUpCallback(heth); #else /* ETH WAKEUP callback */ HAL_ETH_WakeUpCallback(heth); 80049b4: 6878 ldr r0, [r7, #4] 80049b6: f000 f81b bl 80049f0 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ } #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ } 80049ba: bf00 nop 80049bc: 3710 adds r7, #16 80049be: 46bd mov sp, r7 80049c0: bd80 pop {r7, pc} 80049c2: bf00 nop 80049c4: 58000080 .word 0x58000080 080049c8 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ __weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth) { 80049c8: b480 push {r7} 80049ca: b083 sub sp, #12 80049cc: af00 add r7, sp, #0 80049ce: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(heth); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_PMTCallback could be implemented in the user file */ } 80049d0: bf00 nop 80049d2: 370c adds r7, #12 80049d4: 46bd mov sp, r7 80049d6: f85d 7b04 ldr.w r7, [sp], #4 80049da: 4770 bx lr 080049dc : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ __weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth) { 80049dc: b480 push {r7} 80049de: b083 sub sp, #12 80049e0: af00 add r7, sp, #0 80049e2: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(heth); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_EEECallback could be implemented in the user file */ } 80049e4: bf00 nop 80049e6: 370c adds r7, #12 80049e8: 46bd mov sp, r7 80049ea: f85d 7b04 ldr.w r7, [sp], #4 80049ee: 4770 bx lr 080049f0 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ __weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth) { 80049f0: b480 push {r7} 80049f2: b083 sub sp, #12 80049f4: af00 add r7, sp, #0 80049f6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(heth); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_WakeUpCallback could be implemented in the user file */ } 80049f8: bf00 nop 80049fa: 370c adds r7, #12 80049fc: 46bd mov sp, r7 80049fe: f85d 7b04 ldr.w r7, [sp], #4 8004a02: 4770 bx lr 08004a04 : * @param pRegValue: parameter to hold read value * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue) { 8004a04: b580 push {r7, lr} 8004a06: b086 sub sp, #24 8004a08: af00 add r7, sp, #0 8004a0a: 60f8 str r0, [r7, #12] 8004a0c: 60b9 str r1, [r7, #8] 8004a0e: 607a str r2, [r7, #4] 8004a10: 603b str r3, [r7, #0] uint32_t tickstart; uint32_t tmpreg; /* Check for the Busy flag */ if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET) 8004a12: 68fb ldr r3, [r7, #12] 8004a14: 681b ldr r3, [r3, #0] 8004a16: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8004a1a: f003 0301 and.w r3, r3, #1 8004a1e: 2b00 cmp r3, #0 8004a20: d001 beq.n 8004a26 { return HAL_ERROR; 8004a22: 2301 movs r3, #1 8004a24: e03e b.n 8004aa4 } /* Get the MACMDIOAR value */ WRITE_REG(tmpreg, heth->Instance->MACMDIOAR); 8004a26: 68fb ldr r3, [r7, #12] 8004a28: 681b ldr r3, [r3, #0] 8004a2a: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8004a2e: 617b str r3, [r7, #20] - Set the PHY device address - Set the PHY register address - Set the read mode - Set the MII Busy bit */ MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21)); 8004a30: 697b ldr r3, [r7, #20] 8004a32: f023 7278 bic.w r2, r3, #65011712 ; 0x3e00000 8004a36: 68bb ldr r3, [r7, #8] 8004a38: 055b lsls r3, r3, #21 8004a3a: 4313 orrs r3, r2 8004a3c: 617b str r3, [r7, #20] MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16)); 8004a3e: 697b ldr r3, [r7, #20] 8004a40: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 8004a44: 687b ldr r3, [r7, #4] 8004a46: 041b lsls r3, r3, #16 8004a48: 4313 orrs r3, r2 8004a4a: 617b str r3, [r7, #20] MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD); 8004a4c: 697b ldr r3, [r7, #20] 8004a4e: f043 030c orr.w r3, r3, #12 8004a52: 617b str r3, [r7, #20] SET_BIT(tmpreg, ETH_MACMDIOAR_MB); 8004a54: 697b ldr r3, [r7, #20] 8004a56: f043 0301 orr.w r3, r3, #1 8004a5a: 617b str r3, [r7, #20] /* Write the result value into the MDII Address register */ WRITE_REG(heth->Instance->MACMDIOAR, tmpreg); 8004a5c: 68fb ldr r3, [r7, #12] 8004a5e: 681b ldr r3, [r3, #0] 8004a60: 697a ldr r2, [r7, #20] 8004a62: f8c3 2200 str.w r2, [r3, #512] ; 0x200 tickstart = HAL_GetTick(); 8004a66: f7fd fc7d bl 8002364 8004a6a: 6138 str r0, [r7, #16] /* Wait for the Busy flag */ while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) 8004a6c: e009 b.n 8004a82 { if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) 8004a6e: f7fd fc79 bl 8002364 8004a72: 4602 mov r2, r0 8004a74: 693b ldr r3, [r7, #16] 8004a76: 1ad3 subs r3, r2, r3 8004a78: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 8004a7c: d901 bls.n 8004a82 { return HAL_ERROR; 8004a7e: 2301 movs r3, #1 8004a80: e010 b.n 8004aa4 while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) 8004a82: 68fb ldr r3, [r7, #12] 8004a84: 681b ldr r3, [r3, #0] 8004a86: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8004a8a: f003 0301 and.w r3, r3, #1 8004a8e: 2b00 cmp r3, #0 8004a90: d1ed bne.n 8004a6e } } /* Get MACMIIDR value */ WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR); 8004a92: 68fb ldr r3, [r7, #12] 8004a94: 681b ldr r3, [r3, #0] 8004a96: f8d3 3204 ldr.w r3, [r3, #516] ; 0x204 8004a9a: b29b uxth r3, r3 8004a9c: 461a mov r2, r3 8004a9e: 683b ldr r3, [r7, #0] 8004aa0: 601a str r2, [r3, #0] return HAL_OK; 8004aa2: 2300 movs r3, #0 } 8004aa4: 4618 mov r0, r3 8004aa6: 3718 adds r7, #24 8004aa8: 46bd mov sp, r7 8004aaa: bd80 pop {r7, pc} 08004aac : * @param RegValue: the value to write * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue) { 8004aac: b580 push {r7, lr} 8004aae: b086 sub sp, #24 8004ab0: af00 add r7, sp, #0 8004ab2: 60f8 str r0, [r7, #12] 8004ab4: 60b9 str r1, [r7, #8] 8004ab6: 607a str r2, [r7, #4] 8004ab8: 603b str r3, [r7, #0] uint32_t tickstart; uint32_t tmpreg; /* Check for the Busy flag */ if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET) 8004aba: 68fb ldr r3, [r7, #12] 8004abc: 681b ldr r3, [r3, #0] 8004abe: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8004ac2: f003 0301 and.w r3, r3, #1 8004ac6: 2b00 cmp r3, #0 8004ac8: d001 beq.n 8004ace { return HAL_ERROR; 8004aca: 2301 movs r3, #1 8004acc: e03c b.n 8004b48 } /* Get the MACMDIOAR value */ WRITE_REG(tmpreg, heth->Instance->MACMDIOAR); 8004ace: 68fb ldr r3, [r7, #12] 8004ad0: 681b ldr r3, [r3, #0] 8004ad2: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8004ad6: 617b str r3, [r7, #20] - Set the PHY device address - Set the PHY register address - Set the write mode - Set the MII Busy bit */ MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21)); 8004ad8: 697b ldr r3, [r7, #20] 8004ada: f023 7278 bic.w r2, r3, #65011712 ; 0x3e00000 8004ade: 68bb ldr r3, [r7, #8] 8004ae0: 055b lsls r3, r3, #21 8004ae2: 4313 orrs r3, r2 8004ae4: 617b str r3, [r7, #20] MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16)); 8004ae6: 697b ldr r3, [r7, #20] 8004ae8: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 8004aec: 687b ldr r3, [r7, #4] 8004aee: 041b lsls r3, r3, #16 8004af0: 4313 orrs r3, r2 8004af2: 617b str r3, [r7, #20] MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR); 8004af4: 697b ldr r3, [r7, #20] 8004af6: f023 030c bic.w r3, r3, #12 8004afa: f043 0304 orr.w r3, r3, #4 8004afe: 617b str r3, [r7, #20] SET_BIT(tmpreg, ETH_MACMDIOAR_MB); 8004b00: 697b ldr r3, [r7, #20] 8004b02: f043 0301 orr.w r3, r3, #1 8004b06: 617b str r3, [r7, #20] /* Give the value to the MII data register */ WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue); 8004b08: 683b ldr r3, [r7, #0] 8004b0a: b29a uxth r2, r3 8004b0c: 4b10 ldr r3, [pc, #64] ; (8004b50 ) 8004b0e: f8c3 2204 str.w r2, [r3, #516] ; 0x204 /* Write the result value into the MII Address register */ WRITE_REG(ETH->MACMDIOAR, tmpreg); 8004b12: 4a0f ldr r2, [pc, #60] ; (8004b50 ) 8004b14: 697b ldr r3, [r7, #20] 8004b16: f8c2 3200 str.w r3, [r2, #512] ; 0x200 tickstart = HAL_GetTick(); 8004b1a: f7fd fc23 bl 8002364 8004b1e: 6138 str r0, [r7, #16] /* Wait for the Busy flag */ while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) 8004b20: e009 b.n 8004b36 { if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) 8004b22: f7fd fc1f bl 8002364 8004b26: 4602 mov r2, r0 8004b28: 693b ldr r3, [r7, #16] 8004b2a: 1ad3 subs r3, r2, r3 8004b2c: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 8004b30: d901 bls.n 8004b36 { return HAL_ERROR; 8004b32: 2301 movs r3, #1 8004b34: e008 b.n 8004b48 while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) 8004b36: 68fb ldr r3, [r7, #12] 8004b38: 681b ldr r3, [r3, #0] 8004b3a: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8004b3e: f003 0301 and.w r3, r3, #1 8004b42: 2b00 cmp r3, #0 8004b44: d1ed bne.n 8004b22 } } return HAL_OK; 8004b46: 2300 movs r3, #0 } 8004b48: 4618 mov r0, r3 8004b4a: 3718 adds r7, #24 8004b4c: 46bd mov sp, r7 8004b4e: bd80 pop {r7, pc} 8004b50: 40028000 .word 0x40028000 08004b54 : * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold * the configuration of the MAC. * @retval HAL Status */ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) { 8004b54: b480 push {r7} 8004b56: b083 sub sp, #12 8004b58: af00 add r7, sp, #0 8004b5a: 6078 str r0, [r7, #4] 8004b5c: 6039 str r1, [r7, #0] if (macconf == NULL) 8004b5e: 683b ldr r3, [r7, #0] 8004b60: 2b00 cmp r3, #0 8004b62: d101 bne.n 8004b68 { return HAL_ERROR; 8004b64: 2301 movs r3, #1 8004b66: e1c3 b.n 8004ef0 } /* Get MAC parameters */ macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN); 8004b68: 687b ldr r3, [r7, #4] 8004b6a: 681b ldr r3, [r3, #0] 8004b6c: 681b ldr r3, [r3, #0] 8004b6e: f003 020c and.w r2, r3, #12 8004b72: 683b ldr r3, [r7, #0] 8004b74: 62da str r2, [r3, #44] ; 0x2c macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE; 8004b76: 687b ldr r3, [r7, #4] 8004b78: 681b ldr r3, [r3, #0] 8004b7a: 681b ldr r3, [r3, #0] 8004b7c: f003 0310 and.w r3, r3, #16 8004b80: 2b00 cmp r3, #0 8004b82: bf14 ite ne 8004b84: 2301 movne r3, #1 8004b86: 2300 moveq r3, #0 8004b88: b2db uxtb r3, r3 8004b8a: 461a mov r2, r3 8004b8c: 683b ldr r3, [r7, #0] 8004b8e: f883 2028 strb.w r2, [r3, #40] ; 0x28 macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL); 8004b92: 687b ldr r3, [r7, #4] 8004b94: 681b ldr r3, [r3, #0] 8004b96: 681b ldr r3, [r3, #0] 8004b98: f003 0260 and.w r2, r3, #96 ; 0x60 8004b9c: 683b ldr r3, [r7, #0] 8004b9e: 625a str r2, [r3, #36] ; 0x24 macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE; 8004ba0: 687b ldr r3, [r7, #4] 8004ba2: 681b ldr r3, [r3, #0] 8004ba4: 681b ldr r3, [r3, #0] 8004ba6: f403 7380 and.w r3, r3, #256 ; 0x100 8004baa: 2b00 cmp r3, #0 8004bac: bf0c ite eq 8004bae: 2301 moveq r3, #1 8004bb0: 2300 movne r3, #0 8004bb2: b2db uxtb r3, r3 8004bb4: 461a mov r2, r3 8004bb6: 683b ldr r3, [r7, #0] 8004bb8: f883 2020 strb.w r2, [r3, #32] macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) 8004bbc: 687b ldr r3, [r7, #4] 8004bbe: 681b ldr r3, [r3, #0] 8004bc0: 681b ldr r3, [r3, #0] 8004bc2: f403 7300 and.w r3, r3, #512 ; 0x200 ? ENABLE : DISABLE; 8004bc6: 2b00 cmp r3, #0 8004bc8: bf14 ite ne 8004bca: 2301 movne r3, #1 8004bcc: 2300 moveq r3, #0 8004bce: b2db uxtb r3, r3 8004bd0: 461a mov r2, r3 macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) 8004bd2: 683b ldr r3, [r7, #0] 8004bd4: 77da strb r2, [r3, #31] macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE; 8004bd6: 687b ldr r3, [r7, #4] 8004bd8: 681b ldr r3, [r3, #0] 8004bda: 681b ldr r3, [r3, #0] 8004bdc: f403 6380 and.w r3, r3, #1024 ; 0x400 8004be0: 2b00 cmp r3, #0 8004be2: bf0c ite eq 8004be4: 2301 moveq r3, #1 8004be6: 2300 movne r3, #0 8004be8: b2db uxtb r3, r3 8004bea: 461a mov r2, r3 8004bec: 683b ldr r3, [r7, #0] 8004bee: 779a strb r2, [r3, #30] macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, 8004bf0: 687b ldr r3, [r7, #4] 8004bf2: 681b ldr r3, [r3, #0] 8004bf4: 681b ldr r3, [r3, #0] ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE; 8004bf6: f403 6300 and.w r3, r3, #2048 ; 0x800 8004bfa: 2b00 cmp r3, #0 8004bfc: bf14 ite ne 8004bfe: 2301 movne r3, #1 8004c00: 2300 moveq r3, #0 8004c02: b2db uxtb r3, r3 8004c04: 461a mov r2, r3 macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, 8004c06: 683b ldr r3, [r7, #0] 8004c08: 775a strb r2, [r3, #29] macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE; 8004c0a: 687b ldr r3, [r7, #4] 8004c0c: 681b ldr r3, [r3, #0] 8004c0e: 681b ldr r3, [r3, #0] 8004c10: f403 5380 and.w r3, r3, #4096 ; 0x1000 8004c14: 2b00 cmp r3, #0 8004c16: bf14 ite ne 8004c18: 2301 movne r3, #1 8004c1a: 2300 moveq r3, #0 8004c1c: b2db uxtb r3, r3 8004c1e: 461a mov r2, r3 8004c20: 683b ldr r3, [r7, #0] 8004c22: 771a strb r2, [r3, #28] macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM); 8004c24: 687b ldr r3, [r7, #4] 8004c26: 681b ldr r3, [r3, #0] 8004c28: 681b ldr r3, [r3, #0] 8004c2a: f403 5200 and.w r2, r3, #8192 ; 0x2000 8004c2e: 683b ldr r3, [r7, #0] 8004c30: 619a str r2, [r3, #24] macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES); 8004c32: 687b ldr r3, [r7, #4] 8004c34: 681b ldr r3, [r3, #0] 8004c36: 681b ldr r3, [r3, #0] 8004c38: f403 4280 and.w r2, r3, #16384 ; 0x4000 8004c3c: 683b ldr r3, [r7, #0] 8004c3e: 615a str r2, [r3, #20] macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE; 8004c40: 687b ldr r3, [r7, #4] 8004c42: 681b ldr r3, [r3, #0] 8004c44: 681b ldr r3, [r3, #0] 8004c46: f403 3380 and.w r3, r3, #65536 ; 0x10000 8004c4a: 2b00 cmp r3, #0 8004c4c: bf14 ite ne 8004c4e: 2301 movne r3, #1 8004c50: 2300 moveq r3, #0 8004c52: b2db uxtb r3, r3 8004c54: 461a mov r2, r3 8004c56: 683b ldr r3, [r7, #0] 8004c58: 749a strb r2, [r3, #18] macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE; 8004c5a: 687b ldr r3, [r7, #4] 8004c5c: 681b ldr r3, [r3, #0] 8004c5e: 681b ldr r3, [r3, #0] 8004c60: f403 3300 and.w r3, r3, #131072 ; 0x20000 8004c64: 2b00 cmp r3, #0 8004c66: bf0c ite eq 8004c68: 2301 moveq r3, #1 8004c6a: 2300 movne r3, #0 8004c6c: b2db uxtb r3, r3 8004c6e: 461a mov r2, r3 8004c70: 683b ldr r3, [r7, #0] 8004c72: 745a strb r2, [r3, #17] macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE; 8004c74: 687b ldr r3, [r7, #4] 8004c76: 681b ldr r3, [r3, #0] 8004c78: 681b ldr r3, [r3, #0] 8004c7a: f403 2300 and.w r3, r3, #524288 ; 0x80000 8004c7e: 2b00 cmp r3, #0 8004c80: bf0c ite eq 8004c82: 2301 moveq r3, #1 8004c84: 2300 movne r3, #0 8004c86: b2db uxtb r3, r3 8004c88: 461a mov r2, r3 8004c8a: 683b ldr r3, [r7, #0] 8004c8c: 741a strb r2, [r3, #16] macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE; 8004c8e: 687b ldr r3, [r7, #4] 8004c90: 681b ldr r3, [r3, #0] 8004c92: 681b ldr r3, [r3, #0] 8004c94: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8004c98: 2b00 cmp r3, #0 8004c9a: bf14 ite ne 8004c9c: 2301 movne r3, #1 8004c9e: 2300 moveq r3, #0 8004ca0: b2db uxtb r3, r3 8004ca2: 461a mov r2, r3 8004ca4: 683b ldr r3, [r7, #0] 8004ca6: 73da strb r2, [r3, #15] macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE; 8004ca8: 687b ldr r3, [r7, #4] 8004caa: 681b ldr r3, [r3, #0] 8004cac: 681b ldr r3, [r3, #0] 8004cae: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8004cb2: 2b00 cmp r3, #0 8004cb4: bf14 ite ne 8004cb6: 2301 movne r3, #1 8004cb8: 2300 moveq r3, #0 8004cba: b2db uxtb r3, r3 8004cbc: 461a mov r2, r3 8004cbe: 683b ldr r3, [r7, #0] 8004cc0: 739a strb r2, [r3, #14] macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE; 8004cc2: 687b ldr r3, [r7, #4] 8004cc4: 681b ldr r3, [r3, #0] 8004cc6: 681b ldr r3, [r3, #0] 8004cc8: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8004ccc: 2b00 cmp r3, #0 8004cce: bf14 ite ne 8004cd0: 2301 movne r3, #1 8004cd2: 2300 moveq r3, #0 8004cd4: b2db uxtb r3, r3 8004cd6: 461a mov r2, r3 8004cd8: 683b ldr r3, [r7, #0] 8004cda: 735a strb r2, [r3, #13] macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, 8004cdc: 687b ldr r3, [r7, #4] 8004cde: 681b ldr r3, [r3, #0] 8004ce0: 681b ldr r3, [r3, #0] ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE; 8004ce2: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8004ce6: 2b00 cmp r3, #0 8004ce8: bf14 ite ne 8004cea: 2301 movne r3, #1 8004cec: 2300 moveq r3, #0 8004cee: b2db uxtb r3, r3 8004cf0: 461a mov r2, r3 macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, 8004cf2: 683b ldr r3, [r7, #0] 8004cf4: 731a strb r2, [r3, #12] macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG); 8004cf6: 687b ldr r3, [r7, #4] 8004cf8: 681b ldr r3, [r3, #0] 8004cfa: 681b ldr r3, [r3, #0] 8004cfc: f003 62e0 and.w r2, r3, #117440512 ; 0x7000000 8004d00: 683b ldr r3, [r7, #0] 8004d02: 609a str r2, [r3, #8] macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE; 8004d04: 687b ldr r3, [r7, #4] 8004d06: 681b ldr r3, [r3, #0] 8004d08: 681b ldr r3, [r3, #0] 8004d0a: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8004d0e: 2b00 cmp r3, #0 8004d10: bf14 ite ne 8004d12: 2301 movne r3, #1 8004d14: 2300 moveq r3, #0 8004d16: b2db uxtb r3, r3 8004d18: 461a mov r2, r3 8004d1a: 683b ldr r3, [r7, #0] 8004d1c: 711a strb r2, [r3, #4] macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC); 8004d1e: 687b ldr r3, [r7, #4] 8004d20: 681b ldr r3, [r3, #0] 8004d22: 681b ldr r3, [r3, #0] 8004d24: f003 42e0 and.w r2, r3, #1879048192 ; 0x70000000 8004d28: 683b ldr r3, [r7, #0] 8004d2a: 601a str r2, [r3, #0] macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL); 8004d2c: 687b ldr r3, [r7, #4] 8004d2e: 681b ldr r3, [r3, #0] 8004d30: 685b ldr r3, [r3, #4] 8004d32: f3c3 020d ubfx r2, r3, #0, #14 8004d36: 683b ldr r3, [r7, #0] 8004d38: 635a str r2, [r3, #52] ; 0x34 macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE; 8004d3a: 687b ldr r3, [r7, #4] 8004d3c: 681b ldr r3, [r3, #0] 8004d3e: 685b ldr r3, [r3, #4] 8004d40: f403 3380 and.w r3, r3, #65536 ; 0x10000 8004d44: 2b00 cmp r3, #0 8004d46: bf0c ite eq 8004d48: 2301 moveq r3, #1 8004d4a: 2300 movne r3, #0 8004d4c: b2db uxtb r3, r3 8004d4e: 461a mov r2, r3 8004d50: 683b ldr r3, [r7, #0] 8004d52: f883 2032 strb.w r2, [r3, #50] ; 0x32 macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE; 8004d56: 687b ldr r3, [r7, #4] 8004d58: 681b ldr r3, [r3, #0] 8004d5a: 685b ldr r3, [r3, #4] 8004d5c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8004d60: 2b00 cmp r3, #0 8004d62: bf14 ite ne 8004d64: 2301 movne r3, #1 8004d66: 2300 moveq r3, #0 8004d68: b2db uxtb r3, r3 8004d6a: 461a mov r2, r3 8004d6c: 683b ldr r3, [r7, #0] 8004d6e: f883 2031 strb.w r2, [r3, #49] ; 0x31 macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, 8004d72: 687b ldr r3, [r7, #4] 8004d74: 681b ldr r3, [r3, #0] 8004d76: 685b ldr r3, [r3, #4] ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE; 8004d78: f403 2380 and.w r3, r3, #262144 ; 0x40000 8004d7c: 2b00 cmp r3, #0 8004d7e: bf14 ite ne 8004d80: 2301 movne r3, #1 8004d82: 2300 moveq r3, #0 8004d84: b2db uxtb r3, r3 8004d86: 461a mov r2, r3 macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, 8004d88: 683b ldr r3, [r7, #0] 8004d8a: f883 2030 strb.w r2, [r3, #48] ; 0x30 macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) 8004d8e: 687b ldr r3, [r7, #4] 8004d90: 681b ldr r3, [r3, #0] 8004d92: 685b ldr r3, [r3, #4] 8004d94: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 ? ENABLE : DISABLE; 8004d98: 2b00 cmp r3, #0 8004d9a: bf14 ite ne 8004d9c: 2301 movne r3, #1 8004d9e: 2300 moveq r3, #0 8004da0: b2db uxtb r3, r3 8004da2: 461a mov r2, r3 macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) 8004da4: 683b ldr r3, [r7, #0] 8004da6: f883 2038 strb.w r2, [r3, #56] ; 0x38 macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25; 8004daa: 687b ldr r3, [r7, #4] 8004dac: 681b ldr r3, [r3, #0] 8004dae: 685b ldr r3, [r3, #4] 8004db0: 0e5b lsrs r3, r3, #25 8004db2: f003 021f and.w r2, r3, #31 8004db6: 683b ldr r3, [r7, #0] 8004db8: 63da str r2, [r3, #60] ; 0x3c macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE; 8004dba: 687b ldr r3, [r7, #4] 8004dbc: 681b ldr r3, [r3, #0] 8004dbe: 68db ldr r3, [r3, #12] 8004dc0: f403 7380 and.w r3, r3, #256 ; 0x100 8004dc4: 2b00 cmp r3, #0 8004dc6: bf14 ite ne 8004dc8: 2301 movne r3, #1 8004dca: 2300 moveq r3, #0 8004dcc: b2db uxtb r3, r3 8004dce: 461a mov r2, r3 8004dd0: 683b ldr r3, [r7, #0] 8004dd2: f883 2040 strb.w r2, [r3, #64] ; 0x40 macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO); 8004dd6: 687b ldr r3, [r7, #4] 8004dd8: 681b ldr r3, [r3, #0] 8004dda: 68db ldr r3, [r3, #12] 8004ddc: f003 020f and.w r2, r3, #15 8004de0: 683b ldr r3, [r7, #0] 8004de2: 645a str r2, [r3, #68] ; 0x44 macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE; 8004de4: 687b ldr r3, [r7, #4] 8004de6: 681b ldr r3, [r3, #0] 8004de8: 6f1b ldr r3, [r3, #112] ; 0x70 8004dea: f003 0302 and.w r3, r3, #2 8004dee: 2b00 cmp r3, #0 8004df0: bf14 ite ne 8004df2: 2301 movne r3, #1 8004df4: 2300 moveq r3, #0 8004df6: b2db uxtb r3, r3 8004df8: 461a mov r2, r3 8004dfa: 683b ldr r3, [r7, #0] 8004dfc: f883 2054 strb.w r2, [r3, #84] ; 0x54 macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE; 8004e00: 687b ldr r3, [r7, #4] 8004e02: 681b ldr r3, [r3, #0] 8004e04: 6f1b ldr r3, [r3, #112] ; 0x70 8004e06: f003 0380 and.w r3, r3, #128 ; 0x80 8004e0a: 2b00 cmp r3, #0 8004e0c: bf0c ite eq 8004e0e: 2301 moveq r3, #1 8004e10: 2300 movne r3, #0 8004e12: b2db uxtb r3, r3 8004e14: 461a mov r2, r3 8004e16: 683b ldr r3, [r7, #0] 8004e18: f883 204c strb.w r2, [r3, #76] ; 0x4c macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT); 8004e1c: 687b ldr r3, [r7, #4] 8004e1e: 681b ldr r3, [r3, #0] 8004e20: 6f1b ldr r3, [r3, #112] ; 0x70 8004e22: f003 0270 and.w r2, r3, #112 ; 0x70 8004e26: 683b ldr r3, [r7, #0] 8004e28: 651a str r2, [r3, #80] ; 0x50 macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16); 8004e2a: 687b ldr r3, [r7, #4] 8004e2c: 681b ldr r3, [r3, #0] 8004e2e: 6f1b ldr r3, [r3, #112] ; 0x70 8004e30: 0c1b lsrs r3, r3, #16 8004e32: b29a uxth r2, r3 8004e34: 683b ldr r3, [r7, #0] 8004e36: 649a str r2, [r3, #72] ; 0x48 macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE; 8004e38: 687b ldr r3, [r7, #4] 8004e3a: 681b ldr r3, [r3, #0] 8004e3c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8004e40: f003 0301 and.w r3, r3, #1 8004e44: 2b00 cmp r3, #0 8004e46: bf14 ite ne 8004e48: 2301 movne r3, #1 8004e4a: 2300 moveq r3, #0 8004e4c: b2db uxtb r3, r3 8004e4e: 461a mov r2, r3 8004e50: 683b ldr r3, [r7, #0] 8004e52: f883 2056 strb.w r2, [r3, #86] ; 0x56 macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) 8004e56: 687b ldr r3, [r7, #4] 8004e58: 681b ldr r3, [r3, #0] 8004e5a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8004e5e: f003 0302 and.w r3, r3, #2 ? ENABLE : DISABLE; 8004e62: 2b00 cmp r3, #0 8004e64: bf14 ite ne 8004e66: 2301 movne r3, #1 8004e68: 2300 moveq r3, #0 8004e6a: b2db uxtb r3, r3 8004e6c: 461a mov r2, r3 macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) 8004e6e: 683b ldr r3, [r7, #0] 8004e70: f883 2055 strb.w r2, [r3, #85] ; 0x55 macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF)); 8004e74: 687b ldr r3, [r7, #4] 8004e76: 681b ldr r3, [r3, #0] 8004e78: f8d3 3d00 ldr.w r3, [r3, #3328] ; 0xd00 8004e7c: f003 0272 and.w r2, r3, #114 ; 0x72 8004e80: 683b ldr r3, [r7, #0] 8004e82: 659a str r2, [r3, #88] ; 0x58 macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF)); 8004e84: 687b ldr r3, [r7, #4] 8004e86: 681b ldr r3, [r3, #0] 8004e88: f8d3 3d30 ldr.w r3, [r3, #3376] ; 0xd30 8004e8c: f003 0223 and.w r2, r3, #35 ; 0x23 8004e90: 683b ldr r3, [r7, #0] 8004e92: 65da str r2, [r3, #92] ; 0x5c macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, 8004e94: 687b ldr r3, [r7, #4] 8004e96: 681b ldr r3, [r3, #0] 8004e98: f8d3 3d30 ldr.w r3, [r3, #3376] ; 0xd30 ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE; 8004e9c: f003 0308 and.w r3, r3, #8 8004ea0: 2b00 cmp r3, #0 8004ea2: bf14 ite ne 8004ea4: 2301 movne r3, #1 8004ea6: 2300 moveq r3, #0 8004ea8: b2db uxtb r3, r3 8004eaa: 461a mov r2, r3 macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, 8004eac: 683b ldr r3, [r7, #0] 8004eae: f883 2062 strb.w r2, [r3, #98] ; 0x62 macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE; 8004eb2: 687b ldr r3, [r7, #4] 8004eb4: 681b ldr r3, [r3, #0] 8004eb6: f8d3 3d30 ldr.w r3, [r3, #3376] ; 0xd30 8004eba: f003 0310 and.w r3, r3, #16 8004ebe: 2b00 cmp r3, #0 8004ec0: bf14 ite ne 8004ec2: 2301 movne r3, #1 8004ec4: 2300 moveq r3, #0 8004ec6: b2db uxtb r3, r3 8004ec8: 461a mov r2, r3 8004eca: 683b ldr r3, [r7, #0] 8004ecc: f883 2061 strb.w r2, [r3, #97] ; 0x61 macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, 8004ed0: 687b ldr r3, [r7, #4] 8004ed2: 681b ldr r3, [r3, #0] 8004ed4: f8d3 3d30 ldr.w r3, [r3, #3376] ; 0xd30 ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE; 8004ed8: f003 0340 and.w r3, r3, #64 ; 0x40 8004edc: 2b00 cmp r3, #0 8004ede: bf0c ite eq 8004ee0: 2301 moveq r3, #1 8004ee2: 2300 movne r3, #0 8004ee4: b2db uxtb r3, r3 8004ee6: 461a mov r2, r3 macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, 8004ee8: 683b ldr r3, [r7, #0] 8004eea: f883 2060 strb.w r2, [r3, #96] ; 0x60 return HAL_OK; 8004eee: 2300 movs r3, #0 } 8004ef0: 4618 mov r0, r3 8004ef2: 370c adds r7, #12 8004ef4: 46bd mov sp, r7 8004ef6: f85d 7b04 ldr.w r7, [sp], #4 8004efa: 4770 bx lr 08004efc : * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains * the configuration of the MAC. * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) { 8004efc: b580 push {r7, lr} 8004efe: b082 sub sp, #8 8004f00: af00 add r7, sp, #0 8004f02: 6078 str r0, [r7, #4] 8004f04: 6039 str r1, [r7, #0] if (macconf == NULL) 8004f06: 683b ldr r3, [r7, #0] 8004f08: 2b00 cmp r3, #0 8004f0a: d101 bne.n 8004f10 { return HAL_ERROR; 8004f0c: 2301 movs r3, #1 8004f0e: e00b b.n 8004f28 } if (heth->gState == HAL_ETH_STATE_READY) 8004f10: 687b ldr r3, [r7, #4] 8004f12: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8004f16: 2b10 cmp r3, #16 8004f18: d105 bne.n 8004f26 { ETH_SetMACConfig(heth, macconf); 8004f1a: 6839 ldr r1, [r7, #0] 8004f1c: 6878 ldr r0, [r7, #4] 8004f1e: f000 f86d bl 8004ffc return HAL_OK; 8004f22: 2300 movs r3, #0 8004f24: e000 b.n 8004f28 } else { return HAL_ERROR; 8004f26: 2301 movs r3, #1 } } 8004f28: 4618 mov r0, r3 8004f2a: 3708 adds r7, #8 8004f2c: 46bd mov sp, r7 8004f2e: bd80 pop {r7, pc} 08004f30 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) { 8004f30: b580 push {r7, lr} 8004f32: b084 sub sp, #16 8004f34: af00 add r7, sp, #0 8004f36: 6078 str r0, [r7, #4] uint32_t hclk; uint32_t tmpreg; /* Get the ETHERNET MACMDIOAR value */ tmpreg = (heth->Instance)->MACMDIOAR; 8004f38: 687b ldr r3, [r7, #4] 8004f3a: 681b ldr r3, [r3, #0] 8004f3c: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8004f40: 60fb str r3, [r7, #12] /* Clear CSR Clock Range bits */ tmpreg &= ~ETH_MACMDIOAR_CR; 8004f42: 68fb ldr r3, [r7, #12] 8004f44: f423 6370 bic.w r3, r3, #3840 ; 0xf00 8004f48: 60fb str r3, [r7, #12] /* Get hclk frequency value */ hclk = HAL_RCC_GetHCLKFreq(); 8004f4a: f002 ffd9 bl 8007f00 8004f4e: 60b8 str r0, [r7, #8] /* Set CR bits depending on hclk value */ if ((hclk >= 20000000U) && (hclk < 35000000U)) 8004f50: 68bb ldr r3, [r7, #8] 8004f52: 4a1e ldr r2, [pc, #120] ; (8004fcc ) 8004f54: 4293 cmp r3, r2 8004f56: d908 bls.n 8004f6a 8004f58: 68bb ldr r3, [r7, #8] 8004f5a: 4a1d ldr r2, [pc, #116] ; (8004fd0 ) 8004f5c: 4293 cmp r3, r2 8004f5e: d804 bhi.n 8004f6a { /* CSR Clock Range between 20-35 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16; 8004f60: 68fb ldr r3, [r7, #12] 8004f62: f443 7300 orr.w r3, r3, #512 ; 0x200 8004f66: 60fb str r3, [r7, #12] 8004f68: e027 b.n 8004fba } else if ((hclk >= 35000000U) && (hclk < 60000000U)) 8004f6a: 68bb ldr r3, [r7, #8] 8004f6c: 4a18 ldr r2, [pc, #96] ; (8004fd0 ) 8004f6e: 4293 cmp r3, r2 8004f70: d908 bls.n 8004f84 8004f72: 68bb ldr r3, [r7, #8] 8004f74: 4a17 ldr r2, [pc, #92] ; (8004fd4 ) 8004f76: 4293 cmp r3, r2 8004f78: d204 bcs.n 8004f84 { /* CSR Clock Range between 35-60 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26; 8004f7a: 68fb ldr r3, [r7, #12] 8004f7c: f443 7340 orr.w r3, r3, #768 ; 0x300 8004f80: 60fb str r3, [r7, #12] 8004f82: e01a b.n 8004fba } else if ((hclk >= 60000000U) && (hclk < 100000000U)) 8004f84: 68bb ldr r3, [r7, #8] 8004f86: 4a13 ldr r2, [pc, #76] ; (8004fd4 ) 8004f88: 4293 cmp r3, r2 8004f8a: d303 bcc.n 8004f94 8004f8c: 68bb ldr r3, [r7, #8] 8004f8e: 4a12 ldr r2, [pc, #72] ; (8004fd8 ) 8004f90: 4293 cmp r3, r2 8004f92: d911 bls.n 8004fb8 { /* CSR Clock Range between 60-100 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; } else if ((hclk >= 100000000U) && (hclk < 150000000U)) 8004f94: 68bb ldr r3, [r7, #8] 8004f96: 4a10 ldr r2, [pc, #64] ; (8004fd8 ) 8004f98: 4293 cmp r3, r2 8004f9a: d908 bls.n 8004fae 8004f9c: 68bb ldr r3, [r7, #8] 8004f9e: 4a0f ldr r2, [pc, #60] ; (8004fdc ) 8004fa0: 4293 cmp r3, r2 8004fa2: d804 bhi.n 8004fae { /* CSR Clock Range between 100-150 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62; 8004fa4: 68fb ldr r3, [r7, #12] 8004fa6: f443 7380 orr.w r3, r3, #256 ; 0x100 8004faa: 60fb str r3, [r7, #12] 8004fac: e005 b.n 8004fba } else /* (hclk >= 150000000)&&(hclk <= 200000000) */ { /* CSR Clock Range between 150-200 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102; 8004fae: 68fb ldr r3, [r7, #12] 8004fb0: f443 6380 orr.w r3, r3, #1024 ; 0x400 8004fb4: 60fb str r3, [r7, #12] 8004fb6: e000 b.n 8004fba tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; 8004fb8: bf00 nop } /* Configure the CSR Clock Range */ (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg; 8004fba: 687b ldr r3, [r7, #4] 8004fbc: 681b ldr r3, [r3, #0] 8004fbe: 68fa ldr r2, [r7, #12] 8004fc0: f8c3 2200 str.w r2, [r3, #512] ; 0x200 } 8004fc4: bf00 nop 8004fc6: 3710 adds r7, #16 8004fc8: 46bd mov sp, r7 8004fca: bd80 pop {r7, pc} 8004fcc: 01312cff .word 0x01312cff 8004fd0: 02160ebf .word 0x02160ebf 8004fd4: 03938700 .word 0x03938700 8004fd8: 05f5e0ff .word 0x05f5e0ff 8004fdc: 08f0d17f .word 0x08f0d17f 08004fe0 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval ETH DMA Error Code */ uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth) { 8004fe0: b480 push {r7} 8004fe2: b083 sub sp, #12 8004fe4: af00 add r7, sp, #0 8004fe6: 6078 str r0, [r7, #4] return heth->DMAErrorCode; 8004fe8: 687b ldr r3, [r7, #4] 8004fea: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c } 8004fee: 4618 mov r0, r3 8004ff0: 370c adds r7, #12 8004ff2: 46bd mov sp, r7 8004ff4: f85d 7b04 ldr.w r7, [sp], #4 8004ff8: 4770 bx lr ... 08004ffc : * @{ */ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) { 8004ffc: b480 push {r7} 8004ffe: b085 sub sp, #20 8005000: af00 add r7, sp, #0 8005002: 6078 str r0, [r7, #4] 8005004: 6039 str r1, [r7, #0] uint32_t macregval; /*------------------------ MACCR Configuration --------------------*/ macregval = (macconf->InterPacketGapVal | 8005006: 683b ldr r3, [r7, #0] 8005008: 689a ldr r2, [r3, #8] macconf->SourceAddrControl | 800500a: 683b ldr r3, [r7, #0] 800500c: 681b ldr r3, [r3, #0] macregval = (macconf->InterPacketGapVal | 800500e: 431a orrs r2, r3 ((uint32_t)macconf->ChecksumOffload << 27) | 8005010: 683b ldr r3, [r7, #0] 8005012: 791b ldrb r3, [r3, #4] 8005014: 06db lsls r3, r3, #27 macconf->SourceAddrControl | 8005016: 431a orrs r2, r3 ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) | 8005018: 683b ldr r3, [r7, #0] 800501a: 7b1b ldrb r3, [r3, #12] 800501c: 05db lsls r3, r3, #23 ((uint32_t)macconf->ChecksumOffload << 27) | 800501e: 431a orrs r2, r3 ((uint32_t)macconf->Support2KPacket << 22) | 8005020: 683b ldr r3, [r7, #0] 8005022: 7b5b ldrb r3, [r3, #13] 8005024: 059b lsls r3, r3, #22 ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) | 8005026: 431a orrs r2, r3 ((uint32_t)macconf->CRCStripTypePacket << 21) | 8005028: 683b ldr r3, [r7, #0] 800502a: 7b9b ldrb r3, [r3, #14] 800502c: 055b lsls r3, r3, #21 ((uint32_t)macconf->Support2KPacket << 22) | 800502e: 431a orrs r2, r3 ((uint32_t)macconf->AutomaticPadCRCStrip << 20) | 8005030: 683b ldr r3, [r7, #0] 8005032: 7bdb ldrb r3, [r3, #15] 8005034: 051b lsls r3, r3, #20 ((uint32_t)macconf->CRCStripTypePacket << 21) | 8005036: 4313 orrs r3, r2 ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) | 8005038: 683a ldr r2, [r7, #0] 800503a: 7c12 ldrb r2, [r2, #16] 800503c: 2a00 cmp r2, #0 800503e: d102 bne.n 8005046 8005040: f44f 2200 mov.w r2, #524288 ; 0x80000 8005044: e000 b.n 8005048 8005046: 2200 movs r2, #0 ((uint32_t)macconf->AutomaticPadCRCStrip << 20) | 8005048: 4313 orrs r3, r2 ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) | 800504a: 683a ldr r2, [r7, #0] 800504c: 7c52 ldrb r2, [r2, #17] 800504e: 2a00 cmp r2, #0 8005050: d102 bne.n 8005058 8005052: f44f 3200 mov.w r2, #131072 ; 0x20000 8005056: e000 b.n 800505a 8005058: 2200 movs r2, #0 ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) | 800505a: 431a orrs r2, r3 ((uint32_t)macconf->JumboPacket << 16) | 800505c: 683b ldr r3, [r7, #0] 800505e: 7c9b ldrb r3, [r3, #18] 8005060: 041b lsls r3, r3, #16 ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) | 8005062: 431a orrs r2, r3 macconf->Speed | 8005064: 683b ldr r3, [r7, #0] 8005066: 695b ldr r3, [r3, #20] ((uint32_t)macconf->JumboPacket << 16) | 8005068: 431a orrs r2, r3 macconf->DuplexMode | 800506a: 683b ldr r3, [r7, #0] 800506c: 699b ldr r3, [r3, #24] macconf->Speed | 800506e: 431a orrs r2, r3 ((uint32_t)macconf->LoopbackMode << 12) | 8005070: 683b ldr r3, [r7, #0] 8005072: 7f1b ldrb r3, [r3, #28] 8005074: 031b lsls r3, r3, #12 macconf->DuplexMode | 8005076: 431a orrs r2, r3 ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) | 8005078: 683b ldr r3, [r7, #0] 800507a: 7f5b ldrb r3, [r3, #29] 800507c: 02db lsls r3, r3, #11 ((uint32_t)macconf->LoopbackMode << 12) | 800507e: 4313 orrs r3, r2 ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) | 8005080: 683a ldr r2, [r7, #0] 8005082: 7f92 ldrb r2, [r2, #30] 8005084: 2a00 cmp r2, #0 8005086: d102 bne.n 800508e 8005088: f44f 6280 mov.w r2, #1024 ; 0x400 800508c: e000 b.n 8005090 800508e: 2200 movs r2, #0 ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) | 8005090: 431a orrs r2, r3 ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) | 8005092: 683b ldr r3, [r7, #0] 8005094: 7fdb ldrb r3, [r3, #31] 8005096: 025b lsls r3, r3, #9 ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) | 8005098: 4313 orrs r3, r2 ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) | 800509a: 683a ldr r2, [r7, #0] 800509c: f892 2020 ldrb.w r2, [r2, #32] 80050a0: 2a00 cmp r2, #0 80050a2: d102 bne.n 80050aa 80050a4: f44f 7280 mov.w r2, #256 ; 0x100 80050a8: e000 b.n 80050ac 80050aa: 2200 movs r2, #0 ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) | 80050ac: 431a orrs r2, r3 macconf->BackOffLimit | 80050ae: 683b ldr r3, [r7, #0] 80050b0: 6a5b ldr r3, [r3, #36] ; 0x24 ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) | 80050b2: 431a orrs r2, r3 ((uint32_t)macconf->DeferralCheck << 4) | 80050b4: 683b ldr r3, [r7, #0] 80050b6: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 80050ba: 011b lsls r3, r3, #4 macconf->BackOffLimit | 80050bc: 431a orrs r2, r3 macconf->PreambleLength); 80050be: 683b ldr r3, [r7, #0] 80050c0: 6adb ldr r3, [r3, #44] ; 0x2c macregval = (macconf->InterPacketGapVal | 80050c2: 4313 orrs r3, r2 80050c4: 60fb str r3, [r7, #12] /* Write to MACCR */ MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval); 80050c6: 687b ldr r3, [r7, #4] 80050c8: 681b ldr r3, [r3, #0] 80050ca: 681a ldr r2, [r3, #0] 80050cc: 4b56 ldr r3, [pc, #344] ; (8005228 ) 80050ce: 4013 ands r3, r2 80050d0: 687a ldr r2, [r7, #4] 80050d2: 6812 ldr r2, [r2, #0] 80050d4: 68f9 ldr r1, [r7, #12] 80050d6: 430b orrs r3, r1 80050d8: 6013 str r3, [r2, #0] /*------------------------ MACECR Configuration --------------------*/ macregval = ((macconf->ExtendedInterPacketGapVal << 25) | 80050da: 683b ldr r3, [r7, #0] 80050dc: 6bdb ldr r3, [r3, #60] ; 0x3c 80050de: 065a lsls r2, r3, #25 ((uint32_t)macconf->ExtendedInterPacketGap << 24) | 80050e0: 683b ldr r3, [r7, #0] 80050e2: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 80050e6: 061b lsls r3, r3, #24 macregval = ((macconf->ExtendedInterPacketGapVal << 25) | 80050e8: 431a orrs r2, r3 ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) | 80050ea: 683b ldr r3, [r7, #0] 80050ec: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 80050f0: 049b lsls r3, r3, #18 ((uint32_t)macconf->ExtendedInterPacketGap << 24) | 80050f2: 431a orrs r2, r3 ((uint32_t)macconf->SlowProtocolDetect << 17) | 80050f4: 683b ldr r3, [r7, #0] 80050f6: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 80050fa: 045b lsls r3, r3, #17 ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) | 80050fc: 4313 orrs r3, r2 ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) | 80050fe: 683a ldr r2, [r7, #0] 8005100: f892 2032 ldrb.w r2, [r2, #50] ; 0x32 8005104: 2a00 cmp r2, #0 8005106: d102 bne.n 800510e 8005108: f44f 3280 mov.w r2, #65536 ; 0x10000 800510c: e000 b.n 8005110 800510e: 2200 movs r2, #0 ((uint32_t)macconf->SlowProtocolDetect << 17) | 8005110: 431a orrs r2, r3 macconf->GiantPacketSizeLimit); 8005112: 683b ldr r3, [r7, #0] 8005114: 6b5b ldr r3, [r3, #52] ; 0x34 macregval = ((macconf->ExtendedInterPacketGapVal << 25) | 8005116: 4313 orrs r3, r2 8005118: 60fb str r3, [r7, #12] /* Write to MACECR */ MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval); 800511a: 687b ldr r3, [r7, #4] 800511c: 681b ldr r3, [r3, #0] 800511e: 685a ldr r2, [r3, #4] 8005120: 4b42 ldr r3, [pc, #264] ; (800522c ) 8005122: 4013 ands r3, r2 8005124: 687a ldr r2, [r7, #4] 8005126: 6812 ldr r2, [r2, #0] 8005128: 68f9 ldr r1, [r7, #12] 800512a: 430b orrs r3, r1 800512c: 6053 str r3, [r2, #4] /*------------------------ MACWTR Configuration --------------------*/ macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) | 800512e: 683b ldr r3, [r7, #0] 8005130: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 8005134: 021a lsls r2, r3, #8 macconf->WatchdogTimeout); 8005136: 683b ldr r3, [r7, #0] 8005138: 6c5b ldr r3, [r3, #68] ; 0x44 macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) | 800513a: 4313 orrs r3, r2 800513c: 60fb str r3, [r7, #12] /* Write to MACWTR */ MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval); 800513e: 687b ldr r3, [r7, #4] 8005140: 681b ldr r3, [r3, #0] 8005142: 68da ldr r2, [r3, #12] 8005144: 4b3a ldr r3, [pc, #232] ; (8005230 ) 8005146: 4013 ands r3, r2 8005148: 687a ldr r2, [r7, #4] 800514a: 6812 ldr r2, [r2, #0] 800514c: 68f9 ldr r1, [r7, #12] 800514e: 430b orrs r3, r1 8005150: 60d3 str r3, [r2, #12] /*------------------------ MACTFCR Configuration --------------------*/ macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | 8005152: 683b ldr r3, [r7, #0] 8005154: f893 3054 ldrb.w r3, [r3, #84] ; 0x54 8005158: 005a lsls r2, r3, #1 macconf->PauseLowThreshold | 800515a: 683b ldr r3, [r7, #0] 800515c: 6d1b ldr r3, [r3, #80] ; 0x50 macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | 800515e: 4313 orrs r3, r2 ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) | 8005160: 683a ldr r2, [r7, #0] 8005162: f892 204c ldrb.w r2, [r2, #76] ; 0x4c 8005166: 2a00 cmp r2, #0 8005168: d101 bne.n 800516e 800516a: 2280 movs r2, #128 ; 0x80 800516c: e000 b.n 8005170 800516e: 2200 movs r2, #0 macconf->PauseLowThreshold | 8005170: 431a orrs r2, r3 (macconf->PauseTime << 16)); 8005172: 683b ldr r3, [r7, #0] 8005174: 6c9b ldr r3, [r3, #72] ; 0x48 8005176: 041b lsls r3, r3, #16 macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | 8005178: 4313 orrs r3, r2 800517a: 60fb str r3, [r7, #12] /* Write to MACTFCR */ MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval); 800517c: 687b ldr r3, [r7, #4] 800517e: 681b ldr r3, [r3, #0] 8005180: 6f1a ldr r2, [r3, #112] ; 0x70 8005182: f64f 730d movw r3, #65293 ; 0xff0d 8005186: 4013 ands r3, r2 8005188: 687a ldr r2, [r7, #4] 800518a: 6812 ldr r2, [r2, #0] 800518c: 68f9 ldr r1, [r7, #12] 800518e: 430b orrs r3, r1 8005190: 6713 str r3, [r2, #112] ; 0x70 /*------------------------ MACRFCR Configuration --------------------*/ macregval = ((uint32_t)macconf->ReceiveFlowControl | 8005192: 683b ldr r3, [r7, #0] 8005194: f893 3056 ldrb.w r3, [r3, #86] ; 0x56 8005198: 461a mov r2, r3 ((uint32_t)macconf->UnicastPausePacketDetect << 1)); 800519a: 683b ldr r3, [r7, #0] 800519c: f893 3055 ldrb.w r3, [r3, #85] ; 0x55 80051a0: 005b lsls r3, r3, #1 macregval = ((uint32_t)macconf->ReceiveFlowControl | 80051a2: 4313 orrs r3, r2 80051a4: 60fb str r3, [r7, #12] /* Write to MACRFCR */ MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval); 80051a6: 687b ldr r3, [r7, #4] 80051a8: 681b ldr r3, [r3, #0] 80051aa: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 80051ae: f023 0103 bic.w r1, r3, #3 80051b2: 687b ldr r3, [r7, #4] 80051b4: 681b ldr r3, [r3, #0] 80051b6: 68fa ldr r2, [r7, #12] 80051b8: 430a orrs r2, r1 80051ba: f8c3 2090 str.w r2, [r3, #144] ; 0x90 /*------------------------ MTLTQOMR Configuration --------------------*/ /* Write to MTLTQOMR */ MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode); 80051be: 687b ldr r3, [r7, #4] 80051c0: 681b ldr r3, [r3, #0] 80051c2: f8d3 3d00 ldr.w r3, [r3, #3328] ; 0xd00 80051c6: f023 0172 bic.w r1, r3, #114 ; 0x72 80051ca: 683b ldr r3, [r7, #0] 80051cc: 6d9a ldr r2, [r3, #88] ; 0x58 80051ce: 687b ldr r3, [r7, #4] 80051d0: 681b ldr r3, [r3, #0] 80051d2: 430a orrs r2, r1 80051d4: f8c3 2d00 str.w r2, [r3, #3328] ; 0xd00 /*------------------------ MTLRQOMR Configuration --------------------*/ macregval = (macconf->ReceiveQueueMode | 80051d8: 683b ldr r3, [r7, #0] 80051da: 6ddb ldr r3, [r3, #92] ; 0x5c ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) | 80051dc: 683a ldr r2, [r7, #0] 80051de: f892 2060 ldrb.w r2, [r2, #96] ; 0x60 80051e2: 2a00 cmp r2, #0 80051e4: d101 bne.n 80051ea 80051e6: 2240 movs r2, #64 ; 0x40 80051e8: e000 b.n 80051ec 80051ea: 2200 movs r2, #0 macregval = (macconf->ReceiveQueueMode | 80051ec: 431a orrs r2, r3 ((uint32_t)macconf->ForwardRxErrorPacket << 4) | 80051ee: 683b ldr r3, [r7, #0] 80051f0: f893 3061 ldrb.w r3, [r3, #97] ; 0x61 80051f4: 011b lsls r3, r3, #4 ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) | 80051f6: 431a orrs r2, r3 ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3)); 80051f8: 683b ldr r3, [r7, #0] 80051fa: f893 3062 ldrb.w r3, [r3, #98] ; 0x62 80051fe: 00db lsls r3, r3, #3 macregval = (macconf->ReceiveQueueMode | 8005200: 4313 orrs r3, r2 8005202: 60fb str r3, [r7, #12] /* Write to MTLRQOMR */ MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval); 8005204: 687b ldr r3, [r7, #4] 8005206: 681b ldr r3, [r3, #0] 8005208: f8d3 3d30 ldr.w r3, [r3, #3376] ; 0xd30 800520c: f023 017b bic.w r1, r3, #123 ; 0x7b 8005210: 687b ldr r3, [r7, #4] 8005212: 681b ldr r3, [r3, #0] 8005214: 68fa ldr r2, [r7, #12] 8005216: 430a orrs r2, r1 8005218: f8c3 2d30 str.w r2, [r3, #3376] ; 0xd30 } 800521c: bf00 nop 800521e: 3714 adds r7, #20 8005220: 46bd mov sp, r7 8005222: f85d 7b04 ldr.w r7, [sp], #4 8005226: 4770 bx lr 8005228: 00048083 .word 0x00048083 800522c: c0f88000 .word 0xc0f88000 8005230: fffffef0 .word 0xfffffef0 08005234 : static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) { 8005234: b480 push {r7} 8005236: b085 sub sp, #20 8005238: af00 add r7, sp, #0 800523a: 6078 str r0, [r7, #4] 800523c: 6039 str r1, [r7, #0] uint32_t dmaregval; /*------------------------ DMAMR Configuration --------------------*/ MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration); 800523e: 687b ldr r3, [r7, #4] 8005240: 681b ldr r3, [r3, #0] 8005242: f503 5380 add.w r3, r3, #4096 ; 0x1000 8005246: 681a ldr r2, [r3, #0] 8005248: 4b38 ldr r3, [pc, #224] ; (800532c ) 800524a: 4013 ands r3, r2 800524c: 683a ldr r2, [r7, #0] 800524e: 6811 ldr r1, [r2, #0] 8005250: 687a ldr r2, [r7, #4] 8005252: 6812 ldr r2, [r2, #0] 8005254: 430b orrs r3, r1 8005256: f502 5280 add.w r2, r2, #4096 ; 0x1000 800525a: 6013 str r3, [r2, #0] /*------------------------ DMASBMR Configuration --------------------*/ dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) | 800525c: 683b ldr r3, [r7, #0] 800525e: 791b ldrb r3, [r3, #4] 8005260: 031a lsls r2, r3, #12 dmaconf->BurstMode | 8005262: 683b ldr r3, [r7, #0] 8005264: 689b ldr r3, [r3, #8] dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) | 8005266: 431a orrs r2, r3 ((uint32_t)dmaconf->RebuildINCRxBurst << 15)); 8005268: 683b ldr r3, [r7, #0] 800526a: 7b1b ldrb r3, [r3, #12] 800526c: 03db lsls r3, r3, #15 dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) | 800526e: 4313 orrs r3, r2 8005270: 60fb str r3, [r7, #12] MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval); 8005272: 687b ldr r3, [r7, #4] 8005274: 681b ldr r3, [r3, #0] 8005276: f503 5380 add.w r3, r3, #4096 ; 0x1000 800527a: 685a ldr r2, [r3, #4] 800527c: 4b2c ldr r3, [pc, #176] ; (8005330 ) 800527e: 4013 ands r3, r2 8005280: 687a ldr r2, [r7, #4] 8005282: 6812 ldr r2, [r2, #0] 8005284: 68f9 ldr r1, [r7, #12] 8005286: 430b orrs r3, r1 8005288: f502 5280 add.w r2, r2, #4096 ; 0x1000 800528c: 6053 str r3, [r2, #4] /*------------------------ DMACCR Configuration --------------------*/ dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) | 800528e: 683b ldr r3, [r7, #0] 8005290: 7b5b ldrb r3, [r3, #13] 8005292: 041a lsls r2, r3, #16 dmaconf->MaximumSegmentSize); 8005294: 683b ldr r3, [r7, #0] 8005296: 6a1b ldr r3, [r3, #32] dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) | 8005298: 4313 orrs r3, r2 800529a: 60fb str r3, [r7, #12] MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval); 800529c: 687b ldr r3, [r7, #4] 800529e: 681b ldr r3, [r3, #0] 80052a0: f503 5380 add.w r3, r3, #4096 ; 0x1000 80052a4: f8d3 2100 ldr.w r2, [r3, #256] ; 0x100 80052a8: 4b22 ldr r3, [pc, #136] ; (8005334 ) 80052aa: 4013 ands r3, r2 80052ac: 687a ldr r2, [r7, #4] 80052ae: 6812 ldr r2, [r2, #0] 80052b0: 68f9 ldr r1, [r7, #12] 80052b2: 430b orrs r3, r1 80052b4: f502 5280 add.w r2, r2, #4096 ; 0x1000 80052b8: f8c2 3100 str.w r3, [r2, #256] ; 0x100 /*------------------------ DMACTCR Configuration --------------------*/ dmaregval = (dmaconf->TxDMABurstLength | 80052bc: 683b ldr r3, [r7, #0] 80052be: 691a ldr r2, [r3, #16] ((uint32_t)dmaconf->SecondPacketOperate << 4) | 80052c0: 683b ldr r3, [r7, #0] 80052c2: 7d1b ldrb r3, [r3, #20] 80052c4: 011b lsls r3, r3, #4 dmaregval = (dmaconf->TxDMABurstLength | 80052c6: 431a orrs r2, r3 ((uint32_t)dmaconf->TCPSegmentation << 12)); 80052c8: 683b ldr r3, [r7, #0] 80052ca: 7f5b ldrb r3, [r3, #29] 80052cc: 031b lsls r3, r3, #12 dmaregval = (dmaconf->TxDMABurstLength | 80052ce: 4313 orrs r3, r2 80052d0: 60fb str r3, [r7, #12] MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval); 80052d2: 687b ldr r3, [r7, #4] 80052d4: 681b ldr r3, [r3, #0] 80052d6: f503 5380 add.w r3, r3, #4096 ; 0x1000 80052da: f8d3 2104 ldr.w r2, [r3, #260] ; 0x104 80052de: 4b16 ldr r3, [pc, #88] ; (8005338 ) 80052e0: 4013 ands r3, r2 80052e2: 687a ldr r2, [r7, #4] 80052e4: 6812 ldr r2, [r2, #0] 80052e6: 68f9 ldr r1, [r7, #12] 80052e8: 430b orrs r3, r1 80052ea: f502 5280 add.w r2, r2, #4096 ; 0x1000 80052ee: f8c2 3104 str.w r3, [r2, #260] ; 0x104 /*------------------------ DMACRCR Configuration --------------------*/ dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) | 80052f2: 683b ldr r3, [r7, #0] 80052f4: 7f1b ldrb r3, [r3, #28] 80052f6: 07da lsls r2, r3, #31 dmaconf->RxDMABurstLength); 80052f8: 683b ldr r3, [r7, #0] 80052fa: 699b ldr r3, [r3, #24] dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) | 80052fc: 4313 orrs r3, r2 80052fe: 60fb str r3, [r7, #12] /* Write to DMACRCR */ MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval); 8005300: 687b ldr r3, [r7, #4] 8005302: 681b ldr r3, [r3, #0] 8005304: f503 5380 add.w r3, r3, #4096 ; 0x1000 8005308: f8d3 2108 ldr.w r2, [r3, #264] ; 0x108 800530c: 4b0b ldr r3, [pc, #44] ; (800533c ) 800530e: 4013 ands r3, r2 8005310: 687a ldr r2, [r7, #4] 8005312: 6812 ldr r2, [r2, #0] 8005314: 68f9 ldr r1, [r7, #12] 8005316: 430b orrs r3, r1 8005318: f502 5280 add.w r2, r2, #4096 ; 0x1000 800531c: f8c2 3108 str.w r3, [r2, #264] ; 0x108 } 8005320: bf00 nop 8005322: 3714 adds r7, #20 8005324: 46bd mov sp, r7 8005326: f85d 7b04 ldr.w r7, [sp], #4 800532a: 4770 bx lr 800532c: ffff87fd .word 0xffff87fd 8005330: ffff2ffe .word 0xffff2ffe 8005334: fffec000 .word 0xfffec000 8005338: ffc0efef .word 0xffc0efef 800533c: 7fc0ffff .word 0x7fc0ffff 08005340 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) { 8005340: b580 push {r7, lr} 8005342: b0a4 sub sp, #144 ; 0x90 8005344: af00 add r7, sp, #0 8005346: 6078 str r0, [r7, #4] ETH_MACConfigTypeDef macDefaultConf; ETH_DMAConfigTypeDef dmaDefaultConf; /*--------------- ETHERNET MAC registers default Configuration --------------*/ macDefaultConf.AutomaticPadCRCStrip = ENABLE; 8005348: 2301 movs r3, #1 800534a: f887 303b strb.w r3, [r7, #59] ; 0x3b macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; 800534e: 2300 movs r3, #0 8005350: 653b str r3, [r7, #80] ; 0x50 macDefaultConf.CarrierSenseBeforeTransmit = DISABLE; 8005352: 2300 movs r3, #0 8005354: f887 3049 strb.w r3, [r7, #73] ; 0x49 macDefaultConf.CarrierSenseDuringTransmit = DISABLE; 8005358: 2300 movs r3, #0 800535a: f887 304b strb.w r3, [r7, #75] ; 0x4b macDefaultConf.ChecksumOffload = ENABLE; 800535e: 2301 movs r3, #1 8005360: f887 3030 strb.w r3, [r7, #48] ; 0x30 macDefaultConf.CRCCheckingRxPackets = ENABLE; 8005364: 2301 movs r3, #1 8005366: f887 305e strb.w r3, [r7, #94] ; 0x5e macDefaultConf.CRCStripTypePacket = ENABLE; 800536a: 2301 movs r3, #1 800536c: f887 303a strb.w r3, [r7, #58] ; 0x3a macDefaultConf.DeferralCheck = DISABLE; 8005370: 2300 movs r3, #0 8005372: f887 3054 strb.w r3, [r7, #84] ; 0x54 macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE; 8005376: 2301 movs r3, #1 8005378: f887 308c strb.w r3, [r7, #140] ; 0x8c macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; 800537c: f44f 5300 mov.w r3, #8192 ; 0x2000 8005380: 647b str r3, [r7, #68] ; 0x44 macDefaultConf.ExtendedInterPacketGap = DISABLE; 8005382: 2300 movs r3, #0 8005384: f887 3064 strb.w r3, [r7, #100] ; 0x64 macDefaultConf.ExtendedInterPacketGapVal = 0x0; 8005388: 2300 movs r3, #0 800538a: 66bb str r3, [r7, #104] ; 0x68 macDefaultConf.ForwardRxErrorPacket = DISABLE; 800538c: 2300 movs r3, #0 800538e: f887 308d strb.w r3, [r7, #141] ; 0x8d macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE; 8005392: 2300 movs r3, #0 8005394: f887 308e strb.w r3, [r7, #142] ; 0x8e macDefaultConf.GiantPacketSizeLimit = 0x618; 8005398: f44f 63c3 mov.w r3, #1560 ; 0x618 800539c: 663b str r3, [r7, #96] ; 0x60 macDefaultConf.GiantPacketSizeLimitControl = DISABLE; 800539e: 2300 movs r3, #0 80053a0: f887 3038 strb.w r3, [r7, #56] ; 0x38 macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT; 80053a4: 2300 movs r3, #0 80053a6: 637b str r3, [r7, #52] ; 0x34 macDefaultConf.Jabber = ENABLE; 80053a8: 2301 movs r3, #1 80053aa: f887 303d strb.w r3, [r7, #61] ; 0x3d macDefaultConf.JumboPacket = DISABLE; 80053ae: 2300 movs r3, #0 80053b0: f887 303e strb.w r3, [r7, #62] ; 0x3e macDefaultConf.LoopbackMode = DISABLE; 80053b4: 2300 movs r3, #0 80053b6: f887 3048 strb.w r3, [r7, #72] ; 0x48 macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4; 80053ba: 2300 movs r3, #0 80053bc: 67fb str r3, [r7, #124] ; 0x7c macDefaultConf.PauseTime = 0x0; 80053be: 2300 movs r3, #0 80053c0: 677b str r3, [r7, #116] ; 0x74 macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7; 80053c2: 2300 movs r3, #0 80053c4: 65bb str r3, [r7, #88] ; 0x58 macDefaultConf.ProgrammableWatchdog = DISABLE; 80053c6: 2300 movs r3, #0 80053c8: f887 306c strb.w r3, [r7, #108] ; 0x6c macDefaultConf.ReceiveFlowControl = DISABLE; 80053cc: 2300 movs r3, #0 80053ce: f887 3082 strb.w r3, [r7, #130] ; 0x82 macDefaultConf.ReceiveOwn = ENABLE; 80053d2: 2301 movs r3, #1 80053d4: f887 304a strb.w r3, [r7, #74] ; 0x4a macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD; 80053d8: 2320 movs r3, #32 80053da: f8c7 3088 str.w r3, [r7, #136] ; 0x88 macDefaultConf.RetryTransmission = ENABLE; 80053de: 2301 movs r3, #1 80053e0: f887 304c strb.w r3, [r7, #76] ; 0x4c macDefaultConf.SlowProtocolDetect = DISABLE; 80053e4: 2300 movs r3, #0 80053e6: f887 305d strb.w r3, [r7, #93] ; 0x5d macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0; 80053ea: f04f 5340 mov.w r3, #805306368 ; 0x30000000 80053ee: 62fb str r3, [r7, #44] ; 0x2c macDefaultConf.Speed = ETH_SPEED_100M; 80053f0: f44f 4380 mov.w r3, #16384 ; 0x4000 80053f4: 643b str r3, [r7, #64] ; 0x40 macDefaultConf.Support2KPacket = DISABLE; 80053f6: 2300 movs r3, #0 80053f8: f887 3039 strb.w r3, [r7, #57] ; 0x39 macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD; 80053fc: 2302 movs r3, #2 80053fe: f8c7 3084 str.w r3, [r7, #132] ; 0x84 macDefaultConf.TransmitFlowControl = DISABLE; 8005402: 2300 movs r3, #0 8005404: f887 3080 strb.w r3, [r7, #128] ; 0x80 macDefaultConf.UnicastPausePacketDetect = DISABLE; 8005408: 2300 movs r3, #0 800540a: f887 3081 strb.w r3, [r7, #129] ; 0x81 macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE; 800540e: 2300 movs r3, #0 8005410: f887 305c strb.w r3, [r7, #92] ; 0x5c macDefaultConf.Watchdog = ENABLE; 8005414: 2301 movs r3, #1 8005416: f887 303c strb.w r3, [r7, #60] ; 0x3c macDefaultConf.WatchdogTimeout = ETH_MACWTR_WTO_2KB; 800541a: 2300 movs r3, #0 800541c: 673b str r3, [r7, #112] ; 0x70 macDefaultConf.ZeroQuantaPause = ENABLE; 800541e: 2301 movs r3, #1 8005420: f887 3078 strb.w r3, [r7, #120] ; 0x78 /* MAC default configuration */ ETH_SetMACConfig(heth, &macDefaultConf); 8005424: f107 032c add.w r3, r7, #44 ; 0x2c 8005428: 4619 mov r1, r3 800542a: 6878 ldr r0, [r7, #4] 800542c: f7ff fde6 bl 8004ffc /*--------------- ETHERNET DMA registers default Configuration --------------*/ dmaDefaultConf.AddressAlignedBeats = ENABLE; 8005430: 2301 movs r3, #1 8005432: 733b strb r3, [r7, #12] dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; 8005434: 2301 movs r3, #1 8005436: 613b str r3, [r7, #16] dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1; 8005438: 2300 movs r3, #0 800543a: 60bb str r3, [r7, #8] dmaDefaultConf.FlushRxPacket = DISABLE; 800543c: 2300 movs r3, #0 800543e: f887 3024 strb.w r3, [r7, #36] ; 0x24 dmaDefaultConf.PBLx8Mode = DISABLE; 8005442: 2300 movs r3, #0 8005444: 757b strb r3, [r7, #21] dmaDefaultConf.RebuildINCRxBurst = DISABLE; 8005446: 2300 movs r3, #0 8005448: 753b strb r3, [r7, #20] dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; 800544a: f44f 1300 mov.w r3, #2097152 ; 0x200000 800544e: 623b str r3, [r7, #32] dmaDefaultConf.SecondPacketOperate = DISABLE; 8005450: 2300 movs r3, #0 8005452: 773b strb r3, [r7, #28] dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; 8005454: f44f 1300 mov.w r3, #2097152 ; 0x200000 8005458: 61bb str r3, [r7, #24] dmaDefaultConf.TCPSegmentation = DISABLE; 800545a: 2300 movs r3, #0 800545c: f887 3025 strb.w r3, [r7, #37] ; 0x25 dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT; 8005460: f44f 7306 mov.w r3, #536 ; 0x218 8005464: 62bb str r3, [r7, #40] ; 0x28 /* DMA default configuration */ ETH_SetDMAConfig(heth, &dmaDefaultConf); 8005466: f107 0308 add.w r3, r7, #8 800546a: 4619 mov r1, r3 800546c: 6878 ldr r0, [r7, #4] 800546e: f7ff fee1 bl 8005234 } 8005472: bf00 nop 8005474: 3790 adds r7, #144 ; 0x90 8005476: 46bd mov sp, r7 8005478: bd80 pop {r7, pc} 0800547a : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) { 800547a: b480 push {r7} 800547c: b085 sub sp, #20 800547e: af00 add r7, sp, #0 8005480: 6078 str r0, [r7, #4] ETH_DMADescTypeDef *dmatxdesc; uint32_t i; /* Fill each DMATxDesc descriptor with the right values */ for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) 8005482: 2300 movs r3, #0 8005484: 60fb str r3, [r7, #12] 8005486: e01d b.n 80054c4 { dmatxdesc = heth->Init.TxDesc + i; 8005488: 687b ldr r3, [r7, #4] 800548a: 68d9 ldr r1, [r3, #12] 800548c: 68fa ldr r2, [r7, #12] 800548e: 4613 mov r3, r2 8005490: 005b lsls r3, r3, #1 8005492: 4413 add r3, r2 8005494: 00db lsls r3, r3, #3 8005496: 440b add r3, r1 8005498: 60bb str r3, [r7, #8] WRITE_REG(dmatxdesc->DESC0, 0x0); 800549a: 68bb ldr r3, [r7, #8] 800549c: 2200 movs r2, #0 800549e: 601a str r2, [r3, #0] WRITE_REG(dmatxdesc->DESC1, 0x0); 80054a0: 68bb ldr r3, [r7, #8] 80054a2: 2200 movs r2, #0 80054a4: 605a str r2, [r3, #4] WRITE_REG(dmatxdesc->DESC2, 0x0); 80054a6: 68bb ldr r3, [r7, #8] 80054a8: 2200 movs r2, #0 80054aa: 609a str r2, [r3, #8] WRITE_REG(dmatxdesc->DESC3, 0x0); 80054ac: 68bb ldr r3, [r7, #8] 80054ae: 2200 movs r2, #0 80054b0: 60da str r2, [r3, #12] WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); 80054b2: 68b9 ldr r1, [r7, #8] 80054b4: 687b ldr r3, [r7, #4] 80054b6: 68fa ldr r2, [r7, #12] 80054b8: 3206 adds r2, #6 80054ba: f843 1022 str.w r1, [r3, r2, lsl #2] for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) 80054be: 68fb ldr r3, [r7, #12] 80054c0: 3301 adds r3, #1 80054c2: 60fb str r3, [r7, #12] 80054c4: 68fb ldr r3, [r7, #12] 80054c6: 2b03 cmp r3, #3 80054c8: d9de bls.n 8005488 } heth->TxDescList.CurTxDesc = 0; 80054ca: 687b ldr r3, [r7, #4] 80054cc: 2200 movs r2, #0 80054ce: 629a str r2, [r3, #40] ; 0x28 /* Set Transmit Descriptor Ring Length */ WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U)); 80054d0: 687b ldr r3, [r7, #4] 80054d2: 681b ldr r3, [r3, #0] 80054d4: f503 5380 add.w r3, r3, #4096 ; 0x1000 80054d8: 461a mov r2, r3 80054da: 2303 movs r3, #3 80054dc: f8c2 312c str.w r3, [r2, #300] ; 0x12c /* Set Transmit Descriptor List Address */ WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc); 80054e0: 687b ldr r3, [r7, #4] 80054e2: 68da ldr r2, [r3, #12] 80054e4: 687b ldr r3, [r7, #4] 80054e6: 681b ldr r3, [r3, #0] 80054e8: f503 5380 add.w r3, r3, #4096 ; 0x1000 80054ec: f8c3 2114 str.w r2, [r3, #276] ; 0x114 /* Set Transmit Descriptor Tail pointer */ WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc); 80054f0: 687b ldr r3, [r7, #4] 80054f2: 68da ldr r2, [r3, #12] 80054f4: 687b ldr r3, [r7, #4] 80054f6: 681b ldr r3, [r3, #0] 80054f8: f503 5380 add.w r3, r3, #4096 ; 0x1000 80054fc: f8c3 2120 str.w r2, [r3, #288] ; 0x120 } 8005500: bf00 nop 8005502: 3714 adds r7, #20 8005504: 46bd mov sp, r7 8005506: f85d 7b04 ldr.w r7, [sp], #4 800550a: 4770 bx lr 0800550c : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) { 800550c: b480 push {r7} 800550e: b085 sub sp, #20 8005510: af00 add r7, sp, #0 8005512: 6078 str r0, [r7, #4] ETH_DMADescTypeDef *dmarxdesc; uint32_t i; for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) 8005514: 2300 movs r3, #0 8005516: 60fb str r3, [r7, #12] 8005518: e023 b.n 8005562 { dmarxdesc = heth->Init.RxDesc + i; 800551a: 687b ldr r3, [r7, #4] 800551c: 6919 ldr r1, [r3, #16] 800551e: 68fa ldr r2, [r7, #12] 8005520: 4613 mov r3, r2 8005522: 005b lsls r3, r3, #1 8005524: 4413 add r3, r2 8005526: 00db lsls r3, r3, #3 8005528: 440b add r3, r1 800552a: 60bb str r3, [r7, #8] WRITE_REG(dmarxdesc->DESC0, 0x0); 800552c: 68bb ldr r3, [r7, #8] 800552e: 2200 movs r2, #0 8005530: 601a str r2, [r3, #0] WRITE_REG(dmarxdesc->DESC1, 0x0); 8005532: 68bb ldr r3, [r7, #8] 8005534: 2200 movs r2, #0 8005536: 605a str r2, [r3, #4] WRITE_REG(dmarxdesc->DESC2, 0x0); 8005538: 68bb ldr r3, [r7, #8] 800553a: 2200 movs r2, #0 800553c: 609a str r2, [r3, #8] WRITE_REG(dmarxdesc->DESC3, 0x0); 800553e: 68bb ldr r3, [r7, #8] 8005540: 2200 movs r2, #0 8005542: 60da str r2, [r3, #12] WRITE_REG(dmarxdesc->BackupAddr0, 0x0); 8005544: 68bb ldr r3, [r7, #8] 8005546: 2200 movs r2, #0 8005548: 611a str r2, [r3, #16] WRITE_REG(dmarxdesc->BackupAddr1, 0x0); 800554a: 68bb ldr r3, [r7, #8] 800554c: 2200 movs r2, #0 800554e: 615a str r2, [r3, #20] /* Set Rx descritors addresses */ WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); 8005550: 68b9 ldr r1, [r7, #8] 8005552: 687b ldr r3, [r7, #4] 8005554: 68fa ldr r2, [r7, #12] 8005556: 3212 adds r2, #18 8005558: f843 1022 str.w r1, [r3, r2, lsl #2] for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) 800555c: 68fb ldr r3, [r7, #12] 800555e: 3301 adds r3, #1 8005560: 60fb str r3, [r7, #12] 8005562: 68fb ldr r3, [r7, #12] 8005564: 2b03 cmp r3, #3 8005566: d9d8 bls.n 800551a } WRITE_REG(heth->RxDescList.RxDescIdx, 0); 8005568: 687b ldr r3, [r7, #4] 800556a: 2200 movs r2, #0 800556c: 65da str r2, [r3, #92] ; 0x5c WRITE_REG(heth->RxDescList.RxDescCnt, 0); 800556e: 687b ldr r3, [r7, #4] 8005570: 2200 movs r2, #0 8005572: 661a str r2, [r3, #96] ; 0x60 WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0); 8005574: 687b ldr r3, [r7, #4] 8005576: 2200 movs r2, #0 8005578: 669a str r2, [r3, #104] ; 0x68 WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0); 800557a: 687b ldr r3, [r7, #4] 800557c: 2200 movs r2, #0 800557e: 66da str r2, [r3, #108] ; 0x6c WRITE_REG(heth->RxDescList.ItMode, 0); 8005580: 687b ldr r3, [r7, #4] 8005582: 2200 movs r2, #0 8005584: 659a str r2, [r3, #88] ; 0x58 /* Set Receive Descriptor Ring Length */ WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U))); 8005586: 687b ldr r3, [r7, #4] 8005588: 681b ldr r3, [r3, #0] 800558a: f503 5380 add.w r3, r3, #4096 ; 0x1000 800558e: 461a mov r2, r3 8005590: 2303 movs r3, #3 8005592: f8c2 3130 str.w r3, [r2, #304] ; 0x130 /* Set Receive Descriptor List Address */ WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc); 8005596: 687b ldr r3, [r7, #4] 8005598: 691a ldr r2, [r3, #16] 800559a: 687b ldr r3, [r7, #4] 800559c: 681b ldr r3, [r3, #0] 800559e: f503 5380 add.w r3, r3, #4096 ; 0x1000 80055a2: f8c3 211c str.w r2, [r3, #284] ; 0x11c /* Set Receive Descriptor Tail pointer Address */ WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U)))); 80055a6: 687b ldr r3, [r7, #4] 80055a8: 691b ldr r3, [r3, #16] 80055aa: f103 0248 add.w r2, r3, #72 ; 0x48 80055ae: 687b ldr r3, [r7, #4] 80055b0: 681b ldr r3, [r3, #0] 80055b2: f503 5380 add.w r3, r3, #4096 ; 0x1000 80055b6: f8c3 2128 str.w r2, [r3, #296] ; 0x128 } 80055ba: bf00 nop 80055bc: 3714 adds r7, #20 80055be: 46bd mov sp, r7 80055c0: f85d 7b04 ldr.w r7, [sp], #4 80055c4: 4770 bx lr ... 080055c8 : * @param pTxConfig: Tx packet configuration * @param ItMode: Enable or disable Tx EOT interrept * @retval Status */ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode) { 80055c8: b480 push {r7} 80055ca: b08d sub sp, #52 ; 0x34 80055cc: af00 add r7, sp, #0 80055ce: 60f8 str r0, [r7, #12] 80055d0: 60b9 str r1, [r7, #8] 80055d2: 607a str r2, [r7, #4] ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; 80055d4: 68fb ldr r3, [r7, #12] 80055d6: 3318 adds r3, #24 80055d8: 617b str r3, [r7, #20] uint32_t descidx = dmatxdesclist->CurTxDesc; 80055da: 697b ldr r3, [r7, #20] 80055dc: 691b ldr r3, [r3, #16] 80055de: 62fb str r3, [r7, #44] ; 0x2c uint32_t firstdescidx = dmatxdesclist->CurTxDesc; 80055e0: 697b ldr r3, [r7, #20] 80055e2: 691b ldr r3, [r3, #16] 80055e4: 613b str r3, [r7, #16] uint32_t idx; uint32_t descnbr = 0; 80055e6: 2300 movs r3, #0 80055e8: 627b str r3, [r7, #36] ; 0x24 ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; 80055ea: 697b ldr r3, [r7, #20] 80055ec: 6afa ldr r2, [r7, #44] ; 0x2c 80055ee: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80055f2: 623b str r3, [r7, #32] ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; 80055f4: 68bb ldr r3, [r7, #8] 80055f6: 689b ldr r3, [r3, #8] 80055f8: 61fb str r3, [r7, #28] uint32_t bd_count = 0; 80055fa: 2300 movs r3, #0 80055fc: 61bb str r3, [r7, #24] /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) 80055fe: 6a3b ldr r3, [r7, #32] 8005600: 68db ldr r3, [r3, #12] 8005602: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8005606: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 800560a: d007 beq.n 800561c || (dmatxdesclist->PacketAddress[descidx] != NULL)) 800560c: 697a ldr r2, [r7, #20] 800560e: 6afb ldr r3, [r7, #44] ; 0x2c 8005610: 3304 adds r3, #4 8005612: 009b lsls r3, r3, #2 8005614: 4413 add r3, r2 8005616: 685b ldr r3, [r3, #4] 8005618: 2b00 cmp r3, #0 800561a: d001 beq.n 8005620 { return HAL_ETH_ERROR_BUSY; 800561c: 2302 movs r3, #2 800561e: e259 b.n 8005ad4 /***************************************************************************/ /***************** Context descriptor configuration (Optional) **********/ /***************************************************************************/ /* If VLAN tag is enabled for this packet */ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) 8005620: 68bb ldr r3, [r7, #8] 8005622: 681b ldr r3, [r3, #0] 8005624: f003 0304 and.w r3, r3, #4 8005628: 2b00 cmp r3, #0 800562a: d044 beq.n 80056b6 { /* Set vlan tag value */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag); 800562c: 6a3b ldr r3, [r7, #32] 800562e: 68da ldr r2, [r3, #12] 8005630: 4b75 ldr r3, [pc, #468] ; (8005808 ) 8005632: 4013 ands r3, r2 8005634: 68ba ldr r2, [r7, #8] 8005636: 6a52 ldr r2, [r2, #36] ; 0x24 8005638: 431a orrs r2, r3 800563a: 6a3b ldr r3, [r7, #32] 800563c: 60da str r2, [r3, #12] /* Set vlan tag valid bit */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV); 800563e: 6a3b ldr r3, [r7, #32] 8005640: 68db ldr r3, [r3, #12] 8005642: f443 3280 orr.w r2, r3, #65536 ; 0x10000 8005646: 6a3b ldr r3, [r7, #32] 8005648: 60da str r2, [r3, #12] /* Set the descriptor as the vlan input source */ SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI); 800564a: 68fb ldr r3, [r7, #12] 800564c: 681b ldr r3, [r3, #0] 800564e: 6e1a ldr r2, [r3, #96] ; 0x60 8005650: 68fb ldr r3, [r7, #12] 8005652: 681b ldr r3, [r3, #0] 8005654: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8005658: 661a str r2, [r3, #96] ; 0x60 /* if inner VLAN is enabled */ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET) 800565a: 68bb ldr r3, [r7, #8] 800565c: 681b ldr r3, [r3, #0] 800565e: f003 0308 and.w r3, r3, #8 8005662: 2b00 cmp r3, #0 8005664: d027 beq.n 80056b6 { /* Set inner vlan tag value */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16)); 8005666: 6a3b ldr r3, [r7, #32] 8005668: 689b ldr r3, [r3, #8] 800566a: b29a uxth r2, r3 800566c: 68bb ldr r3, [r7, #8] 800566e: 6adb ldr r3, [r3, #44] ; 0x2c 8005670: 041b lsls r3, r3, #16 8005672: 431a orrs r2, r3 8005674: 6a3b ldr r3, [r7, #32] 8005676: 609a str r2, [r3, #8] /* Set inner vlan tag valid bit */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV); 8005678: 6a3b ldr r3, [r7, #32] 800567a: 68db ldr r3, [r3, #12] 800567c: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8005680: 6a3b ldr r3, [r7, #32] 8005682: 60da str r2, [r3, #12] /* Set Vlan Tag control */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl); 8005684: 6a3b ldr r3, [r7, #32] 8005686: 68db ldr r3, [r3, #12] 8005688: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 800568c: 68bb ldr r3, [r7, #8] 800568e: 6b1b ldr r3, [r3, #48] ; 0x30 8005690: 431a orrs r2, r3 8005692: 6a3b ldr r3, [r7, #32] 8005694: 60da str r2, [r3, #12] /* Set the descriptor as the inner vlan input source */ SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI); 8005696: 68fb ldr r3, [r7, #12] 8005698: 681b ldr r3, [r3, #0] 800569a: 6e5a ldr r2, [r3, #100] ; 0x64 800569c: 68fb ldr r3, [r7, #12] 800569e: 681b ldr r3, [r3, #0] 80056a0: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80056a4: 665a str r2, [r3, #100] ; 0x64 /* Enable double VLAN processing */ SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP); 80056a6: 68fb ldr r3, [r7, #12] 80056a8: 681b ldr r3, [r3, #0] 80056aa: 6d1a ldr r2, [r3, #80] ; 0x50 80056ac: 68fb ldr r3, [r7, #12] 80056ae: 681b ldr r3, [r3, #0] 80056b0: f042 6280 orr.w r2, r2, #67108864 ; 0x4000000 80056b4: 651a str r2, [r3, #80] ; 0x50 } } /* if tcp segmentation is enabled for this packet */ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) 80056b6: 68bb ldr r3, [r7, #8] 80056b8: 681b ldr r3, [r3, #0] 80056ba: f003 0310 and.w r3, r3, #16 80056be: 2b00 cmp r3, #0 80056c0: d00e beq.n 80056e0 { /* Set MSS value */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize); 80056c2: 6a3b ldr r3, [r7, #32] 80056c4: 689a ldr r2, [r3, #8] 80056c6: 4b51 ldr r3, [pc, #324] ; (800580c ) 80056c8: 4013 ands r3, r2 80056ca: 68ba ldr r2, [r7, #8] 80056cc: 6992 ldr r2, [r2, #24] 80056ce: 431a orrs r2, r3 80056d0: 6a3b ldr r3, [r7, #32] 80056d2: 609a str r2, [r3, #8] /* Set MSS valid bit */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV); 80056d4: 6a3b ldr r3, [r7, #32] 80056d6: 68db ldr r3, [r3, #12] 80056d8: f043 6280 orr.w r2, r3, #67108864 ; 0x4000000 80056dc: 6a3b ldr r3, [r7, #32] 80056de: 60da str r2, [r3, #12] } if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) 80056e0: 68bb ldr r3, [r7, #8] 80056e2: 681b ldr r3, [r3, #0] 80056e4: f003 0304 and.w r3, r3, #4 80056e8: 2b00 cmp r3, #0 80056ea: d105 bne.n 80056f8 || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)) 80056ec: 68bb ldr r3, [r7, #8] 80056ee: 681b ldr r3, [r3, #0] 80056f0: f003 0310 and.w r3, r3, #16 80056f4: 2b00 cmp r3, #0 80056f6: d036 beq.n 8005766 { /* Set as context descriptor */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT); 80056f8: 6a3b ldr r3, [r7, #32] 80056fa: 68db ldr r3, [r3, #12] 80056fc: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000 8005700: 6a3b ldr r3, [r7, #32] 8005702: 60da str r2, [r3, #12] __ASM volatile ("dmb 0xF":::"memory"); 8005704: f3bf 8f5f dmb sy } 8005708: bf00 nop /* Ensure rest of descriptor is written to RAM before the OWN bit */ __DMB(); /* Set own bit */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN); 800570a: 6a3b ldr r3, [r7, #32] 800570c: 68db ldr r3, [r3, #12] 800570e: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 8005712: 6a3b ldr r3, [r7, #32] 8005714: 60da str r2, [r3, #12] /* Increment current tx descriptor index */ INCR_TX_DESC_INDEX(descidx, 1U); 8005716: 6afb ldr r3, [r7, #44] ; 0x2c 8005718: 3301 adds r3, #1 800571a: 62fb str r3, [r7, #44] ; 0x2c 800571c: 6afb ldr r3, [r7, #44] ; 0x2c 800571e: 2b03 cmp r3, #3 8005720: d902 bls.n 8005728 8005722: 6afb ldr r3, [r7, #44] ; 0x2c 8005724: 3b04 subs r3, #4 8005726: 62fb str r3, [r7, #44] ; 0x2c /* Get current descriptor address */ dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; 8005728: 697b ldr r3, [r7, #20] 800572a: 6afa ldr r2, [r7, #44] ; 0x2c 800572c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8005730: 623b str r3, [r7, #32] descnbr += 1U; 8005732: 6a7b ldr r3, [r7, #36] ; 0x24 8005734: 3301 adds r3, #1 8005736: 627b str r3, [r7, #36] ; 0x24 /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) 8005738: 6a3b ldr r3, [r7, #32] 800573a: 68db ldr r3, [r3, #12] 800573c: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8005740: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8005744: d10f bne.n 8005766 { dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx]; 8005746: 697b ldr r3, [r7, #20] 8005748: 693a ldr r2, [r7, #16] 800574a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800574e: 623b str r3, [r7, #32] __ASM volatile ("dmb 0xF":::"memory"); 8005750: f3bf 8f5f dmb sy } 8005754: bf00 nop /* Ensure rest of descriptor is written to RAM before the OWN bit */ __DMB(); /* Clear own bit */ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN); 8005756: 6a3b ldr r3, [r7, #32] 8005758: 68db ldr r3, [r3, #12] 800575a: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 800575e: 6a3b ldr r3, [r7, #32] 8005760: 60da str r2, [r3, #12] return HAL_ETH_ERROR_BUSY; 8005762: 2302 movs r3, #2 8005764: e1b6 b.n 8005ad4 /***************************************************************************/ /***************** Normal descriptors configuration *****************/ /***************************************************************************/ descnbr += 1U; 8005766: 6a7b ldr r3, [r7, #36] ; 0x24 8005768: 3301 adds r3, #1 800576a: 627b str r3, [r7, #36] ; 0x24 /* Set header or buffer 1 address */ WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer); 800576c: 69fb ldr r3, [r7, #28] 800576e: 681b ldr r3, [r3, #0] 8005770: 461a mov r2, r3 8005772: 6a3b ldr r3, [r7, #32] 8005774: 601a str r2, [r3, #0] /* Set header or buffer 1 Length */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); 8005776: 6a3b ldr r3, [r7, #32] 8005778: 689a ldr r2, [r3, #8] 800577a: 4b24 ldr r3, [pc, #144] ; (800580c ) 800577c: 4013 ands r3, r2 800577e: 69fa ldr r2, [r7, #28] 8005780: 6852 ldr r2, [r2, #4] 8005782: 431a orrs r2, r3 8005784: 6a3b ldr r3, [r7, #32] 8005786: 609a str r2, [r3, #8] if (txbuffer->next != NULL) 8005788: 69fb ldr r3, [r7, #28] 800578a: 689b ldr r3, [r3, #8] 800578c: 2b00 cmp r3, #0 800578e: d012 beq.n 80057b6 { txbuffer = txbuffer->next; 8005790: 69fb ldr r3, [r7, #28] 8005792: 689b ldr r3, [r3, #8] 8005794: 61fb str r3, [r7, #28] /* Set buffer 2 address */ WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer); 8005796: 69fb ldr r3, [r7, #28] 8005798: 681b ldr r3, [r3, #0] 800579a: 461a mov r2, r3 800579c: 6a3b ldr r3, [r7, #32] 800579e: 605a str r2, [r3, #4] /* Set buffer 2 Length */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); 80057a0: 6a3b ldr r3, [r7, #32] 80057a2: 689a ldr r2, [r3, #8] 80057a4: 4b1a ldr r3, [pc, #104] ; (8005810 ) 80057a6: 4013 ands r3, r2 80057a8: 69fa ldr r2, [r7, #28] 80057aa: 6852 ldr r2, [r2, #4] 80057ac: 0412 lsls r2, r2, #16 80057ae: 431a orrs r2, r3 80057b0: 6a3b ldr r3, [r7, #32] 80057b2: 609a str r2, [r3, #8] 80057b4: e008 b.n 80057c8 } else { WRITE_REG(dmatxdesc->DESC1, 0x0); 80057b6: 6a3b ldr r3, [r7, #32] 80057b8: 2200 movs r2, #0 80057ba: 605a str r2, [r3, #4] /* Set buffer 2 Length */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); 80057bc: 6a3b ldr r3, [r7, #32] 80057be: 689a ldr r2, [r3, #8] 80057c0: 4b13 ldr r3, [pc, #76] ; (8005810 ) 80057c2: 4013 ands r3, r2 80057c4: 6a3a ldr r2, [r7, #32] 80057c6: 6093 str r3, [r2, #8] } if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) 80057c8: 68bb ldr r3, [r7, #8] 80057ca: 681b ldr r3, [r3, #0] 80057cc: f003 0310 and.w r3, r3, #16 80057d0: 2b00 cmp r3, #0 80057d2: d021 beq.n 8005818 { /* Set TCP Header length */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19)); 80057d4: 6a3b ldr r3, [r7, #32] 80057d6: 68db ldr r3, [r3, #12] 80057d8: f423 02f0 bic.w r2, r3, #7864320 ; 0x780000 80057dc: 68bb ldr r3, [r7, #8] 80057de: 6a1b ldr r3, [r3, #32] 80057e0: 04db lsls r3, r3, #19 80057e2: 431a orrs r2, r3 80057e4: 6a3b ldr r3, [r7, #32] 80057e6: 60da str r2, [r3, #12] /* Set TCP payload length */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); 80057e8: 6a3b ldr r3, [r7, #32] 80057ea: 68da ldr r2, [r3, #12] 80057ec: 4b09 ldr r3, [pc, #36] ; (8005814 ) 80057ee: 4013 ands r3, r2 80057f0: 68ba ldr r2, [r7, #8] 80057f2: 69d2 ldr r2, [r2, #28] 80057f4: 431a orrs r2, r3 80057f6: 6a3b ldr r3, [r7, #32] 80057f8: 60da str r2, [r3, #12] /* Set TCP Segmentation Enabled bit */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE); 80057fa: 6a3b ldr r3, [r7, #32] 80057fc: 68db ldr r3, [r3, #12] 80057fe: f443 2280 orr.w r2, r3, #262144 ; 0x40000 8005802: 6a3b ldr r3, [r7, #32] 8005804: 60da str r2, [r3, #12] 8005806: e02e b.n 8005866 8005808: ffff0000 .word 0xffff0000 800580c: ffffc000 .word 0xffffc000 8005810: c000ffff .word 0xc000ffff 8005814: fffc0000 .word 0xfffc0000 } else { MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); 8005818: 6a3b ldr r3, [r7, #32] 800581a: 68da ldr r2, [r3, #12] 800581c: 4b7b ldr r3, [pc, #492] ; (8005a0c ) 800581e: 4013 ands r3, r2 8005820: 68ba ldr r2, [r7, #8] 8005822: 6852 ldr r2, [r2, #4] 8005824: 431a orrs r2, r3 8005826: 6a3b ldr r3, [r7, #32] 8005828: 60da str r2, [r3, #12] if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) 800582a: 68bb ldr r3, [r7, #8] 800582c: 681b ldr r3, [r3, #0] 800582e: f003 0301 and.w r3, r3, #1 8005832: 2b00 cmp r3, #0 8005834: d008 beq.n 8005848 { MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); 8005836: 6a3b ldr r3, [r7, #32] 8005838: 68db ldr r3, [r3, #12] 800583a: f423 3240 bic.w r2, r3, #196608 ; 0x30000 800583e: 68bb ldr r3, [r7, #8] 8005840: 695b ldr r3, [r3, #20] 8005842: 431a orrs r2, r3 8005844: 6a3b ldr r3, [r7, #32] 8005846: 60da str r2, [r3, #12] } if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET) 8005848: 68bb ldr r3, [r7, #8] 800584a: 681b ldr r3, [r3, #0] 800584c: f003 0320 and.w r3, r3, #32 8005850: 2b00 cmp r3, #0 8005852: d008 beq.n 8005866 { MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl); 8005854: 6a3b ldr r3, [r7, #32] 8005856: 68db ldr r3, [r3, #12] 8005858: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000 800585c: 68bb ldr r3, [r7, #8] 800585e: 691b ldr r3, [r3, #16] 8005860: 431a orrs r2, r3 8005862: 6a3b ldr r3, [r7, #32] 8005864: 60da str r2, [r3, #12] } } if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) 8005866: 68bb ldr r3, [r7, #8] 8005868: 681b ldr r3, [r3, #0] 800586a: f003 0304 and.w r3, r3, #4 800586e: 2b00 cmp r3, #0 8005870: d008 beq.n 8005884 { /* Set Vlan Tag control */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl); 8005872: 6a3b ldr r3, [r7, #32] 8005874: 689b ldr r3, [r3, #8] 8005876: f423 4240 bic.w r2, r3, #49152 ; 0xc000 800587a: 68bb ldr r3, [r7, #8] 800587c: 6a9b ldr r3, [r3, #40] ; 0x28 800587e: 431a orrs r2, r3 8005880: 6a3b ldr r3, [r7, #32] 8005882: 609a str r2, [r3, #8] } /* Mark it as First Descriptor */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); 8005884: 6a3b ldr r3, [r7, #32] 8005886: 68db ldr r3, [r3, #12] 8005888: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000 800588c: 6a3b ldr r3, [r7, #32] 800588e: 60da str r2, [r3, #12] /* Mark it as NORMAL descriptor */ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); 8005890: 6a3b ldr r3, [r7, #32] 8005892: 68db ldr r3, [r3, #12] 8005894: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000 8005898: 6a3b ldr r3, [r7, #32] 800589a: 60da str r2, [r3, #12] __ASM volatile ("dmb 0xF":::"memory"); 800589c: f3bf 8f5f dmb sy } 80058a0: bf00 nop /* Ensure rest of descriptor is written to RAM before the OWN bit */ __DMB(); /* set OWN bit of FIRST descriptor */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); 80058a2: 6a3b ldr r3, [r7, #32] 80058a4: 68db ldr r3, [r3, #12] 80058a6: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 80058aa: 6a3b ldr r3, [r7, #32] 80058ac: 60da str r2, [r3, #12] /* If source address insertion/replacement is enabled for this packet */ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET) 80058ae: 68bb ldr r3, [r7, #8] 80058b0: 681b ldr r3, [r3, #0] 80058b2: f003 0302 and.w r3, r3, #2 80058b6: 2b00 cmp r3, #0 80058b8: f000 80da beq.w 8005a70 { MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl); 80058bc: 6a3b ldr r3, [r7, #32] 80058be: 68db ldr r3, [r3, #12] 80058c0: f023 7260 bic.w r2, r3, #58720256 ; 0x3800000 80058c4: 68bb ldr r3, [r7, #8] 80058c6: 68db ldr r3, [r3, #12] 80058c8: 431a orrs r2, r3 80058ca: 6a3b ldr r3, [r7, #32] 80058cc: 60da str r2, [r3, #12] } /* only if the packet is split into more than one descriptors > 1 */ while (txbuffer->next != NULL) 80058ce: e0cf b.n 8005a70 { /* Clear the LD bit of previous descriptor */ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); 80058d0: 6a3b ldr r3, [r7, #32] 80058d2: 68db ldr r3, [r3, #12] 80058d4: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 80058d8: 6a3b ldr r3, [r7, #32] 80058da: 60da str r2, [r3, #12] /* Increment current tx descriptor index */ INCR_TX_DESC_INDEX(descidx, 1U); 80058dc: 6afb ldr r3, [r7, #44] ; 0x2c 80058de: 3301 adds r3, #1 80058e0: 62fb str r3, [r7, #44] ; 0x2c 80058e2: 6afb ldr r3, [r7, #44] ; 0x2c 80058e4: 2b03 cmp r3, #3 80058e6: d902 bls.n 80058ee 80058e8: 6afb ldr r3, [r7, #44] ; 0x2c 80058ea: 3b04 subs r3, #4 80058ec: 62fb str r3, [r7, #44] ; 0x2c /* Get current descriptor address */ dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; 80058ee: 697b ldr r3, [r7, #20] 80058f0: 6afa ldr r2, [r7, #44] ; 0x2c 80058f2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80058f6: 623b str r3, [r7, #32] /* Clear the FD bit of new Descriptor */ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); 80058f8: 6a3b ldr r3, [r7, #32] 80058fa: 68db ldr r3, [r3, #12] 80058fc: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 8005900: 6a3b ldr r3, [r7, #32] 8005902: 60da str r2, [r3, #12] /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) 8005904: 6a3b ldr r3, [r7, #32] 8005906: 68db ldr r3, [r3, #12] 8005908: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 800590c: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8005910: d007 beq.n 8005922 || (dmatxdesclist->PacketAddress[descidx] != NULL)) 8005912: 697a ldr r2, [r7, #20] 8005914: 6afb ldr r3, [r7, #44] ; 0x2c 8005916: 3304 adds r3, #4 8005918: 009b lsls r3, r3, #2 800591a: 4413 add r3, r2 800591c: 685b ldr r3, [r3, #4] 800591e: 2b00 cmp r3, #0 8005920: d029 beq.n 8005976 { descidx = firstdescidx; 8005922: 693b ldr r3, [r7, #16] 8005924: 62fb str r3, [r7, #44] ; 0x2c dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; 8005926: 697b ldr r3, [r7, #20] 8005928: 6afa ldr r2, [r7, #44] ; 0x2c 800592a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800592e: 623b str r3, [r7, #32] /* clear previous desc own bit */ for (idx = 0; idx < descnbr; idx ++) 8005930: 2300 movs r3, #0 8005932: 62bb str r3, [r7, #40] ; 0x28 8005934: e019 b.n 800596a __ASM volatile ("dmb 0xF":::"memory"); 8005936: f3bf 8f5f dmb sy } 800593a: bf00 nop { /* Ensure rest of descriptor is written to RAM before the OWN bit */ __DMB(); CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); 800593c: 6a3b ldr r3, [r7, #32] 800593e: 68db ldr r3, [r3, #12] 8005940: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 8005944: 6a3b ldr r3, [r7, #32] 8005946: 60da str r2, [r3, #12] /* Increment current tx descriptor index */ INCR_TX_DESC_INDEX(descidx, 1U); 8005948: 6afb ldr r3, [r7, #44] ; 0x2c 800594a: 3301 adds r3, #1 800594c: 62fb str r3, [r7, #44] ; 0x2c 800594e: 6afb ldr r3, [r7, #44] ; 0x2c 8005950: 2b03 cmp r3, #3 8005952: d902 bls.n 800595a 8005954: 6afb ldr r3, [r7, #44] ; 0x2c 8005956: 3b04 subs r3, #4 8005958: 62fb str r3, [r7, #44] ; 0x2c /* Get current descriptor address */ dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; 800595a: 697b ldr r3, [r7, #20] 800595c: 6afa ldr r2, [r7, #44] ; 0x2c 800595e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8005962: 623b str r3, [r7, #32] for (idx = 0; idx < descnbr; idx ++) 8005964: 6abb ldr r3, [r7, #40] ; 0x28 8005966: 3301 adds r3, #1 8005968: 62bb str r3, [r7, #40] ; 0x28 800596a: 6aba ldr r2, [r7, #40] ; 0x28 800596c: 6a7b ldr r3, [r7, #36] ; 0x24 800596e: 429a cmp r2, r3 8005970: d3e1 bcc.n 8005936 } return HAL_ETH_ERROR_BUSY; 8005972: 2302 movs r3, #2 8005974: e0ae b.n 8005ad4 } descnbr += 1U; 8005976: 6a7b ldr r3, [r7, #36] ; 0x24 8005978: 3301 adds r3, #1 800597a: 627b str r3, [r7, #36] ; 0x24 /* Get the next Tx buffer in the list */ txbuffer = txbuffer->next; 800597c: 69fb ldr r3, [r7, #28] 800597e: 689b ldr r3, [r3, #8] 8005980: 61fb str r3, [r7, #28] /* Set header or buffer 1 address */ WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer); 8005982: 69fb ldr r3, [r7, #28] 8005984: 681b ldr r3, [r3, #0] 8005986: 461a mov r2, r3 8005988: 6a3b ldr r3, [r7, #32] 800598a: 601a str r2, [r3, #0] /* Set header or buffer 1 Length */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); 800598c: 6a3b ldr r3, [r7, #32] 800598e: 689a ldr r2, [r3, #8] 8005990: 4b1f ldr r3, [pc, #124] ; (8005a10 ) 8005992: 4013 ands r3, r2 8005994: 69fa ldr r2, [r7, #28] 8005996: 6852 ldr r2, [r2, #4] 8005998: 431a orrs r2, r3 800599a: 6a3b ldr r3, [r7, #32] 800599c: 609a str r2, [r3, #8] if (txbuffer->next != NULL) 800599e: 69fb ldr r3, [r7, #28] 80059a0: 689b ldr r3, [r3, #8] 80059a2: 2b00 cmp r3, #0 80059a4: d012 beq.n 80059cc { /* Get the next Tx buffer in the list */ txbuffer = txbuffer->next; 80059a6: 69fb ldr r3, [r7, #28] 80059a8: 689b ldr r3, [r3, #8] 80059aa: 61fb str r3, [r7, #28] /* Set buffer 2 address */ WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer); 80059ac: 69fb ldr r3, [r7, #28] 80059ae: 681b ldr r3, [r3, #0] 80059b0: 461a mov r2, r3 80059b2: 6a3b ldr r3, [r7, #32] 80059b4: 605a str r2, [r3, #4] /* Set buffer 2 Length */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); 80059b6: 6a3b ldr r3, [r7, #32] 80059b8: 689a ldr r2, [r3, #8] 80059ba: 4b16 ldr r3, [pc, #88] ; (8005a14 ) 80059bc: 4013 ands r3, r2 80059be: 69fa ldr r2, [r7, #28] 80059c0: 6852 ldr r2, [r2, #4] 80059c2: 0412 lsls r2, r2, #16 80059c4: 431a orrs r2, r3 80059c6: 6a3b ldr r3, [r7, #32] 80059c8: 609a str r2, [r3, #8] 80059ca: e008 b.n 80059de } else { WRITE_REG(dmatxdesc->DESC1, 0x0); 80059cc: 6a3b ldr r3, [r7, #32] 80059ce: 2200 movs r2, #0 80059d0: 605a str r2, [r3, #4] /* Set buffer 2 Length */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); 80059d2: 6a3b ldr r3, [r7, #32] 80059d4: 689a ldr r2, [r3, #8] 80059d6: 4b0f ldr r3, [pc, #60] ; (8005a14 ) 80059d8: 4013 ands r3, r2 80059da: 6a3a ldr r2, [r7, #32] 80059dc: 6093 str r3, [r2, #8] } if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) 80059de: 68bb ldr r3, [r7, #8] 80059e0: 681b ldr r3, [r3, #0] 80059e2: f003 0310 and.w r3, r3, #16 80059e6: 2b00 cmp r3, #0 80059e8: d018 beq.n 8005a1c { /* Set TCP payload length */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); 80059ea: 6a3b ldr r3, [r7, #32] 80059ec: 68da ldr r2, [r3, #12] 80059ee: 4b0a ldr r3, [pc, #40] ; (8005a18 ) 80059f0: 4013 ands r3, r2 80059f2: 68ba ldr r2, [r7, #8] 80059f4: 69d2 ldr r2, [r2, #28] 80059f6: 431a orrs r2, r3 80059f8: 6a3b ldr r3, [r7, #32] 80059fa: 60da str r2, [r3, #12] /* Set TCP Segmentation Enabled bit */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE); 80059fc: 6a3b ldr r3, [r7, #32] 80059fe: 68db ldr r3, [r3, #12] 8005a00: f443 2280 orr.w r2, r3, #262144 ; 0x40000 8005a04: 6a3b ldr r3, [r7, #32] 8005a06: 60da str r2, [r3, #12] 8005a08: e020 b.n 8005a4c 8005a0a: bf00 nop 8005a0c: ffff8000 .word 0xffff8000 8005a10: ffffc000 .word 0xffffc000 8005a14: c000ffff .word 0xc000ffff 8005a18: fffc0000 .word 0xfffc0000 } else { /* Set the packet length */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); 8005a1c: 6a3b ldr r3, [r7, #32] 8005a1e: 68da ldr r2, [r3, #12] 8005a20: 4b2f ldr r3, [pc, #188] ; (8005ae0 ) 8005a22: 4013 ands r3, r2 8005a24: 68ba ldr r2, [r7, #8] 8005a26: 6852 ldr r2, [r2, #4] 8005a28: 431a orrs r2, r3 8005a2a: 6a3b ldr r3, [r7, #32] 8005a2c: 60da str r2, [r3, #12] if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) 8005a2e: 68bb ldr r3, [r7, #8] 8005a30: 681b ldr r3, [r3, #0] 8005a32: f003 0301 and.w r3, r3, #1 8005a36: 2b00 cmp r3, #0 8005a38: d008 beq.n 8005a4c { /* Checksum Insertion Control */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); 8005a3a: 6a3b ldr r3, [r7, #32] 8005a3c: 68db ldr r3, [r3, #12] 8005a3e: f423 3240 bic.w r2, r3, #196608 ; 0x30000 8005a42: 68bb ldr r3, [r7, #8] 8005a44: 695b ldr r3, [r3, #20] 8005a46: 431a orrs r2, r3 8005a48: 6a3b ldr r3, [r7, #32] 8005a4a: 60da str r2, [r3, #12] } } bd_count += 1U; 8005a4c: 69bb ldr r3, [r7, #24] 8005a4e: 3301 adds r3, #1 8005a50: 61bb str r3, [r7, #24] __ASM volatile ("dmb 0xF":::"memory"); 8005a52: f3bf 8f5f dmb sy } 8005a56: bf00 nop /* Ensure rest of descriptor is written to RAM before the OWN bit */ __DMB(); /* Set Own bit */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); 8005a58: 6a3b ldr r3, [r7, #32] 8005a5a: 68db ldr r3, [r3, #12] 8005a5c: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 8005a60: 6a3b ldr r3, [r7, #32] 8005a62: 60da str r2, [r3, #12] /* Mark it as NORMAL descriptor */ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); 8005a64: 6a3b ldr r3, [r7, #32] 8005a66: 68db ldr r3, [r3, #12] 8005a68: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000 8005a6c: 6a3b ldr r3, [r7, #32] 8005a6e: 60da str r2, [r3, #12] while (txbuffer->next != NULL) 8005a70: 69fb ldr r3, [r7, #28] 8005a72: 689b ldr r3, [r3, #8] 8005a74: 2b00 cmp r3, #0 8005a76: f47f af2b bne.w 80058d0 } if (ItMode != ((uint32_t)RESET)) 8005a7a: 687b ldr r3, [r7, #4] 8005a7c: 2b00 cmp r3, #0 8005a7e: d006 beq.n 8005a8e { /* Set Interrupt on completion bit */ SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); 8005a80: 6a3b ldr r3, [r7, #32] 8005a82: 689b ldr r3, [r3, #8] 8005a84: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 8005a88: 6a3b ldr r3, [r7, #32] 8005a8a: 609a str r2, [r3, #8] 8005a8c: e005 b.n 8005a9a } else { /* Clear Interrupt on completion bit */ CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); 8005a8e: 6a3b ldr r3, [r7, #32] 8005a90: 689b ldr r3, [r3, #8] 8005a92: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 8005a96: 6a3b ldr r3, [r7, #32] 8005a98: 609a str r2, [r3, #8] } /* Mark it as LAST descriptor */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); 8005a9a: 6a3b ldr r3, [r7, #32] 8005a9c: 68db ldr r3, [r3, #12] 8005a9e: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 8005aa2: 6a3b ldr r3, [r7, #32] 8005aa4: 60da str r2, [r3, #12] /* Save the current packet address to expose it to the application */ dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; 8005aa6: 697b ldr r3, [r7, #20] 8005aa8: 6a5a ldr r2, [r3, #36] ; 0x24 8005aaa: 6979 ldr r1, [r7, #20] 8005aac: 6afb ldr r3, [r7, #44] ; 0x2c 8005aae: 3304 adds r3, #4 8005ab0: 009b lsls r3, r3, #2 8005ab2: 440b add r3, r1 8005ab4: 605a str r2, [r3, #4] dmatxdesclist->CurTxDesc = descidx; 8005ab6: 697b ldr r3, [r7, #20] 8005ab8: 6afa ldr r2, [r7, #44] ; 0x2c 8005aba: 611a str r2, [r3, #16] __ASM volatile ("cpsid i" : : : "memory"); 8005abc: b672 cpsid i } 8005abe: bf00 nop /* disable the interrupt */ __disable_irq(); dmatxdesclist->BuffersInUse += bd_count + 1U; 8005ac0: 697b ldr r3, [r7, #20] 8005ac2: 6a9a ldr r2, [r3, #40] ; 0x28 8005ac4: 69bb ldr r3, [r7, #24] 8005ac6: 4413 add r3, r2 8005ac8: 1c5a adds r2, r3, #1 8005aca: 697b ldr r3, [r7, #20] 8005acc: 629a str r2, [r3, #40] ; 0x28 __ASM volatile ("cpsie i" : : : "memory"); 8005ace: b662 cpsie i } 8005ad0: bf00 nop /* Enable interrupts back */ __enable_irq(); /* Return function status */ return HAL_ETH_ERROR_NONE; 8005ad2: 2300 movs r3, #0 } 8005ad4: 4618 mov r0, r3 8005ad6: 3734 adds r7, #52 ; 0x34 8005ad8: 46bd mov sp, r7 8005ada: f85d 7b04 ldr.w r7, [sp], #4 8005ade: 4770 bx lr 8005ae0: ffff8000 .word 0xffff8000 08005ae4 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval HAL status */ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) { 8005ae4: b580 push {r7, lr} 8005ae6: b098 sub sp, #96 ; 0x60 8005ae8: af00 add r7, sp, #0 8005aea: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status; const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7}; 8005aec: 4a84 ldr r2, [pc, #528] ; (8005d00 ) 8005aee: f107 030c add.w r3, r7, #12 8005af2: 4611 mov r1, r2 8005af4: 224c movs r2, #76 ; 0x4c 8005af6: 4618 mov r0, r3 8005af8: f01c f975 bl 8021de6 /* Check FDCAN handle */ if (hfdcan == NULL) 8005afc: 687b ldr r3, [r7, #4] 8005afe: 2b00 cmp r3, #0 8005b00: d101 bne.n 8005b06 { return HAL_ERROR; 8005b02: 2301 movs r3, #1 8005b04: e1c6 b.n 8005e94 } /* Check FDCAN instance */ if (hfdcan->Instance == FDCAN1) 8005b06: 687b ldr r3, [r7, #4] 8005b08: 681b ldr r3, [r3, #0] 8005b0a: 4a7e ldr r2, [pc, #504] ; (8005d04 ) 8005b0c: 4293 cmp r3, r2 8005b0e: d106 bne.n 8005b1e { hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U); 8005b10: 687b ldr r3, [r7, #4] 8005b12: 681b ldr r3, [r3, #0] 8005b14: f503 7380 add.w r3, r3, #256 ; 0x100 8005b18: 461a mov r2, r3 8005b1a: 687b ldr r3, [r7, #4] 8005b1c: 605a str r2, [r3, #4] /* Init the low level hardware: CLOCK, NVIC */ hfdcan->MspInitCallback(hfdcan); } #else if (hfdcan->State == HAL_FDCAN_STATE_RESET) 8005b1e: 687b ldr r3, [r7, #4] 8005b20: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 8005b24: b2db uxtb r3, r3 8005b26: 2b00 cmp r3, #0 8005b28: d106 bne.n 8005b38 { /* Allocate lock resource and initialize it */ hfdcan->Lock = HAL_UNLOCKED; 8005b2a: 687b ldr r3, [r7, #4] 8005b2c: 2200 movs r2, #0 8005b2e: f883 2099 strb.w r2, [r3, #153] ; 0x99 /* Init the low level hardware: CLOCK, NVIC */ HAL_FDCAN_MspInit(hfdcan); 8005b32: 6878 ldr r0, [r7, #4] 8005b34: f7fb fd02 bl 800153c } #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ /* Exit from Sleep mode */ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); 8005b38: 687b ldr r3, [r7, #4] 8005b3a: 681b ldr r3, [r3, #0] 8005b3c: 699a ldr r2, [r3, #24] 8005b3e: 687b ldr r3, [r7, #4] 8005b40: 681b ldr r3, [r3, #0] 8005b42: f022 0210 bic.w r2, r2, #16 8005b46: 619a str r2, [r3, #24] /* Get tick */ tickstart = HAL_GetTick(); 8005b48: f7fc fc0c bl 8002364 8005b4c: 65f8 str r0, [r7, #92] ; 0x5c /* Check Sleep mode acknowledge */ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) 8005b4e: e014 b.n 8005b7a { if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) 8005b50: f7fc fc08 bl 8002364 8005b54: 4602 mov r2, r0 8005b56: 6dfb ldr r3, [r7, #92] ; 0x5c 8005b58: 1ad3 subs r3, r2, r3 8005b5a: 2b0a cmp r3, #10 8005b5c: d90d bls.n 8005b7a { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; 8005b5e: 687b ldr r3, [r7, #4] 8005b60: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8005b64: f043 0201 orr.w r2, r3, #1 8005b68: 687b ldr r3, [r7, #4] 8005b6a: f8c3 209c str.w r2, [r3, #156] ; 0x9c /* Change FDCAN state */ hfdcan->State = HAL_FDCAN_STATE_ERROR; 8005b6e: 687b ldr r3, [r7, #4] 8005b70: 2203 movs r2, #3 8005b72: f883 2098 strb.w r2, [r3, #152] ; 0x98 return HAL_ERROR; 8005b76: 2301 movs r3, #1 8005b78: e18c b.n 8005e94 while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) 8005b7a: 687b ldr r3, [r7, #4] 8005b7c: 681b ldr r3, [r3, #0] 8005b7e: 699b ldr r3, [r3, #24] 8005b80: f003 0308 and.w r3, r3, #8 8005b84: 2b08 cmp r3, #8 8005b86: d0e3 beq.n 8005b50 } } /* Request initialisation */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); 8005b88: 687b ldr r3, [r7, #4] 8005b8a: 681b ldr r3, [r3, #0] 8005b8c: 699a ldr r2, [r3, #24] 8005b8e: 687b ldr r3, [r7, #4] 8005b90: 681b ldr r3, [r3, #0] 8005b92: f042 0201 orr.w r2, r2, #1 8005b96: 619a str r2, [r3, #24] /* Get tick */ tickstart = HAL_GetTick(); 8005b98: f7fc fbe4 bl 8002364 8005b9c: 65f8 str r0, [r7, #92] ; 0x5c /* Wait until the INIT bit into CCCR register is set */ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) 8005b9e: e014 b.n 8005bca { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) 8005ba0: f7fc fbe0 bl 8002364 8005ba4: 4602 mov r2, r0 8005ba6: 6dfb ldr r3, [r7, #92] ; 0x5c 8005ba8: 1ad3 subs r3, r2, r3 8005baa: 2b0a cmp r3, #10 8005bac: d90d bls.n 8005bca { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; 8005bae: 687b ldr r3, [r7, #4] 8005bb0: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8005bb4: f043 0201 orr.w r2, r3, #1 8005bb8: 687b ldr r3, [r7, #4] 8005bba: f8c3 209c str.w r2, [r3, #156] ; 0x9c /* Change FDCAN state */ hfdcan->State = HAL_FDCAN_STATE_ERROR; 8005bbe: 687b ldr r3, [r7, #4] 8005bc0: 2203 movs r2, #3 8005bc2: f883 2098 strb.w r2, [r3, #152] ; 0x98 return HAL_ERROR; 8005bc6: 2301 movs r3, #1 8005bc8: e164 b.n 8005e94 while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) 8005bca: 687b ldr r3, [r7, #4] 8005bcc: 681b ldr r3, [r3, #0] 8005bce: 699b ldr r3, [r3, #24] 8005bd0: f003 0301 and.w r3, r3, #1 8005bd4: 2b00 cmp r3, #0 8005bd6: d0e3 beq.n 8005ba0 } } /* Enable configuration change */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); 8005bd8: 687b ldr r3, [r7, #4] 8005bda: 681b ldr r3, [r3, #0] 8005bdc: 699a ldr r2, [r3, #24] 8005bde: 687b ldr r3, [r7, #4] 8005be0: 681b ldr r3, [r3, #0] 8005be2: f042 0202 orr.w r2, r2, #2 8005be6: 619a str r2, [r3, #24] /* Set the no automatic retransmission */ if (hfdcan->Init.AutoRetransmission == ENABLE) 8005be8: 687b ldr r3, [r7, #4] 8005bea: 7c1b ldrb r3, [r3, #16] 8005bec: 2b01 cmp r3, #1 8005bee: d108 bne.n 8005c02 { CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); 8005bf0: 687b ldr r3, [r7, #4] 8005bf2: 681b ldr r3, [r3, #0] 8005bf4: 699a ldr r2, [r3, #24] 8005bf6: 687b ldr r3, [r7, #4] 8005bf8: 681b ldr r3, [r3, #0] 8005bfa: f022 0240 bic.w r2, r2, #64 ; 0x40 8005bfe: 619a str r2, [r3, #24] 8005c00: e007 b.n 8005c12 } else { SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); 8005c02: 687b ldr r3, [r7, #4] 8005c04: 681b ldr r3, [r3, #0] 8005c06: 699a ldr r2, [r3, #24] 8005c08: 687b ldr r3, [r7, #4] 8005c0a: 681b ldr r3, [r3, #0] 8005c0c: f042 0240 orr.w r2, r2, #64 ; 0x40 8005c10: 619a str r2, [r3, #24] } /* Set the transmit pause feature */ if (hfdcan->Init.TransmitPause == ENABLE) 8005c12: 687b ldr r3, [r7, #4] 8005c14: 7c5b ldrb r3, [r3, #17] 8005c16: 2b01 cmp r3, #1 8005c18: d108 bne.n 8005c2c { SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); 8005c1a: 687b ldr r3, [r7, #4] 8005c1c: 681b ldr r3, [r3, #0] 8005c1e: 699a ldr r2, [r3, #24] 8005c20: 687b ldr r3, [r7, #4] 8005c22: 681b ldr r3, [r3, #0] 8005c24: f442 4280 orr.w r2, r2, #16384 ; 0x4000 8005c28: 619a str r2, [r3, #24] 8005c2a: e007 b.n 8005c3c } else { CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); 8005c2c: 687b ldr r3, [r7, #4] 8005c2e: 681b ldr r3, [r3, #0] 8005c30: 699a ldr r2, [r3, #24] 8005c32: 687b ldr r3, [r7, #4] 8005c34: 681b ldr r3, [r3, #0] 8005c36: f422 4280 bic.w r2, r2, #16384 ; 0x4000 8005c3a: 619a str r2, [r3, #24] } /* Set the Protocol Exception Handling */ if (hfdcan->Init.ProtocolException == ENABLE) 8005c3c: 687b ldr r3, [r7, #4] 8005c3e: 7c9b ldrb r3, [r3, #18] 8005c40: 2b01 cmp r3, #1 8005c42: d108 bne.n 8005c56 { CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); 8005c44: 687b ldr r3, [r7, #4] 8005c46: 681b ldr r3, [r3, #0] 8005c48: 699a ldr r2, [r3, #24] 8005c4a: 687b ldr r3, [r7, #4] 8005c4c: 681b ldr r3, [r3, #0] 8005c4e: f422 5280 bic.w r2, r2, #4096 ; 0x1000 8005c52: 619a str r2, [r3, #24] 8005c54: e007 b.n 8005c66 } else { SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); 8005c56: 687b ldr r3, [r7, #4] 8005c58: 681b ldr r3, [r3, #0] 8005c5a: 699a ldr r2, [r3, #24] 8005c5c: 687b ldr r3, [r7, #4] 8005c5e: 681b ldr r3, [r3, #0] 8005c60: f442 5280 orr.w r2, r2, #4096 ; 0x1000 8005c64: 619a str r2, [r3, #24] } /* Set FDCAN Frame Format */ MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat); 8005c66: 687b ldr r3, [r7, #4] 8005c68: 681b ldr r3, [r3, #0] 8005c6a: 699b ldr r3, [r3, #24] 8005c6c: f423 7140 bic.w r1, r3, #768 ; 0x300 8005c70: 687b ldr r3, [r7, #4] 8005c72: 689a ldr r2, [r3, #8] 8005c74: 687b ldr r3, [r7, #4] 8005c76: 681b ldr r3, [r3, #0] 8005c78: 430a orrs r2, r1 8005c7a: 619a str r2, [r3, #24] /* Reset FDCAN Operation Mode */ CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM)); 8005c7c: 687b ldr r3, [r7, #4] 8005c7e: 681b ldr r3, [r3, #0] 8005c80: 699a ldr r2, [r3, #24] 8005c82: 687b ldr r3, [r7, #4] 8005c84: 681b ldr r3, [r3, #0] 8005c86: f022 02a4 bic.w r2, r2, #164 ; 0xa4 8005c8a: 619a str r2, [r3, #24] CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); 8005c8c: 687b ldr r3, [r7, #4] 8005c8e: 681b ldr r3, [r3, #0] 8005c90: 691a ldr r2, [r3, #16] 8005c92: 687b ldr r3, [r7, #4] 8005c94: 681b ldr r3, [r3, #0] 8005c96: f022 0210 bic.w r2, r2, #16 8005c9a: 611a str r2, [r3, #16] CCCR.TEST | 0 | 0 | 0 | 1 | 1 CCCR.MON | 0 | 0 | 1 | 1 | 0 TEST.LBCK | 0 | 0 | 0 | 1 | 1 CCCR.ASM | 0 | 1 | 0 | 0 | 0 */ if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION) 8005c9c: 687b ldr r3, [r7, #4] 8005c9e: 68db ldr r3, [r3, #12] 8005ca0: 2b01 cmp r3, #1 8005ca2: d108 bne.n 8005cb6 { /* Enable Restricted Operation mode */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); 8005ca4: 687b ldr r3, [r7, #4] 8005ca6: 681b ldr r3, [r3, #0] 8005ca8: 699a ldr r2, [r3, #24] 8005caa: 687b ldr r3, [r7, #4] 8005cac: 681b ldr r3, [r3, #0] 8005cae: f042 0204 orr.w r2, r2, #4 8005cb2: 619a str r2, [r3, #24] 8005cb4: e030 b.n 8005d18 } else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL) 8005cb6: 687b ldr r3, [r7, #4] 8005cb8: 68db ldr r3, [r3, #12] 8005cba: 2b00 cmp r3, #0 8005cbc: d02c beq.n 8005d18 { if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING) 8005cbe: 687b ldr r3, [r7, #4] 8005cc0: 68db ldr r3, [r3, #12] 8005cc2: 2b02 cmp r3, #2 8005cc4: d020 beq.n 8005d08 { /* Enable write access to TEST register */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST); 8005cc6: 687b ldr r3, [r7, #4] 8005cc8: 681b ldr r3, [r3, #0] 8005cca: 699a ldr r2, [r3, #24] 8005ccc: 687b ldr r3, [r7, #4] 8005cce: 681b ldr r3, [r3, #0] 8005cd0: f042 0280 orr.w r2, r2, #128 ; 0x80 8005cd4: 619a str r2, [r3, #24] /* Enable LoopBack mode */ SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); 8005cd6: 687b ldr r3, [r7, #4] 8005cd8: 681b ldr r3, [r3, #0] 8005cda: 691a ldr r2, [r3, #16] 8005cdc: 687b ldr r3, [r7, #4] 8005cde: 681b ldr r3, [r3, #0] 8005ce0: f042 0210 orr.w r2, r2, #16 8005ce4: 611a str r2, [r3, #16] if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK) 8005ce6: 687b ldr r3, [r7, #4] 8005ce8: 68db ldr r3, [r3, #12] 8005cea: 2b03 cmp r3, #3 8005cec: d114 bne.n 8005d18 { SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); 8005cee: 687b ldr r3, [r7, #4] 8005cf0: 681b ldr r3, [r3, #0] 8005cf2: 699a ldr r2, [r3, #24] 8005cf4: 687b ldr r3, [r7, #4] 8005cf6: 681b ldr r3, [r3, #0] 8005cf8: f042 0220 orr.w r2, r2, #32 8005cfc: 619a str r2, [r3, #24] 8005cfe: e00b b.n 8005d18 8005d00: 08022e38 .word 0x08022e38 8005d04: 4000a000 .word 0x4000a000 } } else { /* Enable bus monitoring mode */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); 8005d08: 687b ldr r3, [r7, #4] 8005d0a: 681b ldr r3, [r3, #0] 8005d0c: 699a ldr r2, [r3, #24] 8005d0e: 687b ldr r3, [r7, #4] 8005d10: 681b ldr r3, [r3, #0] 8005d12: f042 0220 orr.w r2, r2, #32 8005d16: 619a str r2, [r3, #24] { /* Nothing to do: normal mode */ } /* Set the nominal bit timing register */ hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 8005d18: 687b ldr r3, [r7, #4] 8005d1a: 699b ldr r3, [r3, #24] 8005d1c: 3b01 subs r3, #1 8005d1e: 065a lsls r2, r3, #25 (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \ 8005d20: 687b ldr r3, [r7, #4] 8005d22: 69db ldr r3, [r3, #28] 8005d24: 3b01 subs r3, #1 8005d26: 021b lsls r3, r3, #8 hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 8005d28: 431a orrs r2, r3 (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \ 8005d2a: 687b ldr r3, [r7, #4] 8005d2c: 6a1b ldr r3, [r3, #32] 8005d2e: 3b01 subs r3, #1 (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \ 8005d30: ea42 0103 orr.w r1, r2, r3 (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos)); 8005d34: 687b ldr r3, [r7, #4] 8005d36: 695b ldr r3, [r3, #20] 8005d38: 3b01 subs r3, #1 8005d3a: 041a lsls r2, r3, #16 hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 8005d3c: 687b ldr r3, [r7, #4] 8005d3e: 681b ldr r3, [r3, #0] (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \ 8005d40: 430a orrs r2, r1 hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 8005d42: 61da str r2, [r3, #28] /* If FD operation with BRS is selected, set the data bit timing register */ if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) 8005d44: 687b ldr r3, [r7, #4] 8005d46: 689b ldr r3, [r3, #8] 8005d48: f5b3 7f40 cmp.w r3, #768 ; 0x300 8005d4c: d115 bne.n 8005d7a { hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 8005d4e: 687b ldr r3, [r7, #4] 8005d50: 6a9b ldr r3, [r3, #40] ; 0x28 8005d52: 1e5a subs r2, r3, #1 (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \ 8005d54: 687b ldr r3, [r7, #4] 8005d56: 6adb ldr r3, [r3, #44] ; 0x2c 8005d58: 3b01 subs r3, #1 8005d5a: 021b lsls r3, r3, #8 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 8005d5c: 431a orrs r2, r3 (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \ 8005d5e: 687b ldr r3, [r7, #4] 8005d60: 6b1b ldr r3, [r3, #48] ; 0x30 8005d62: 3b01 subs r3, #1 8005d64: 011b lsls r3, r3, #4 (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \ 8005d66: ea42 0103 orr.w r1, r2, r3 (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos)); 8005d6a: 687b ldr r3, [r7, #4] 8005d6c: 6a5b ldr r3, [r3, #36] ; 0x24 8005d6e: 3b01 subs r3, #1 8005d70: 041a lsls r2, r3, #16 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 8005d72: 687b ldr r3, [r7, #4] 8005d74: 681b ldr r3, [r3, #0] (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \ 8005d76: 430a orrs r2, r1 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 8005d78: 60da str r2, [r3, #12] } if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U) 8005d7a: 687b ldr r3, [r7, #4] 8005d7c: 6e1b ldr r3, [r3, #96] ; 0x60 8005d7e: 2b00 cmp r3, #0 8005d80: d00a beq.n 8005d98 { /* Select between Tx FIFO and Tx Queue operation modes */ SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode); 8005d82: 687b ldr r3, [r7, #4] 8005d84: 681b ldr r3, [r3, #0] 8005d86: f8d3 10c0 ldr.w r1, [r3, #192] ; 0xc0 8005d8a: 687b ldr r3, [r7, #4] 8005d8c: 6e5a ldr r2, [r3, #100] ; 0x64 8005d8e: 687b ldr r3, [r7, #4] 8005d90: 681b ldr r3, [r3, #0] 8005d92: 430a orrs r2, r1 8005d94: f8c3 20c0 str.w r2, [r3, #192] ; 0xc0 } /* Configure Tx element size */ if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U) 8005d98: 687b ldr r3, [r7, #4] 8005d9a: 6dda ldr r2, [r3, #92] ; 0x5c 8005d9c: 687b ldr r3, [r7, #4] 8005d9e: 6e1b ldr r3, [r3, #96] ; 0x60 8005da0: 4413 add r3, r2 8005da2: 2b00 cmp r3, #0 8005da4: d011 beq.n 8005dca { MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]); 8005da6: 687b ldr r3, [r7, #4] 8005da8: 681b ldr r3, [r3, #0] 8005daa: f8d3 30c8 ldr.w r3, [r3, #200] ; 0xc8 8005dae: f023 0107 bic.w r1, r3, #7 8005db2: 687b ldr r3, [r7, #4] 8005db4: 6e9b ldr r3, [r3, #104] ; 0x68 8005db6: 009b lsls r3, r3, #2 8005db8: 3360 adds r3, #96 ; 0x60 8005dba: 443b add r3, r7 8005dbc: f853 2c54 ldr.w r2, [r3, #-84] 8005dc0: 687b ldr r3, [r7, #4] 8005dc2: 681b ldr r3, [r3, #0] 8005dc4: 430a orrs r2, r1 8005dc6: f8c3 20c8 str.w r2, [r3, #200] ; 0xc8 } /* Configure Rx FIFO 0 element size */ if (hfdcan->Init.RxFifo0ElmtsNbr > 0U) 8005dca: 687b ldr r3, [r7, #4] 8005dcc: 6c1b ldr r3, [r3, #64] ; 0x40 8005dce: 2b00 cmp r3, #0 8005dd0: d011 beq.n 8005df6 { MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos)); 8005dd2: 687b ldr r3, [r7, #4] 8005dd4: 681b ldr r3, [r3, #0] 8005dd6: f8d3 30bc ldr.w r3, [r3, #188] ; 0xbc 8005dda: f023 0107 bic.w r1, r3, #7 8005dde: 687b ldr r3, [r7, #4] 8005de0: 6c5b ldr r3, [r3, #68] ; 0x44 8005de2: 009b lsls r3, r3, #2 8005de4: 3360 adds r3, #96 ; 0x60 8005de6: 443b add r3, r7 8005de8: f853 2c54 ldr.w r2, [r3, #-84] 8005dec: 687b ldr r3, [r7, #4] 8005dee: 681b ldr r3, [r3, #0] 8005df0: 430a orrs r2, r1 8005df2: f8c3 20bc str.w r2, [r3, #188] ; 0xbc } /* Configure Rx FIFO 1 element size */ if (hfdcan->Init.RxFifo1ElmtsNbr > 0U) 8005df6: 687b ldr r3, [r7, #4] 8005df8: 6c9b ldr r3, [r3, #72] ; 0x48 8005dfa: 2b00 cmp r3, #0 8005dfc: d012 beq.n 8005e24 { MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos)); 8005dfe: 687b ldr r3, [r7, #4] 8005e00: 681b ldr r3, [r3, #0] 8005e02: f8d3 30bc ldr.w r3, [r3, #188] ; 0xbc 8005e06: f023 0170 bic.w r1, r3, #112 ; 0x70 8005e0a: 687b ldr r3, [r7, #4] 8005e0c: 6cdb ldr r3, [r3, #76] ; 0x4c 8005e0e: 009b lsls r3, r3, #2 8005e10: 3360 adds r3, #96 ; 0x60 8005e12: 443b add r3, r7 8005e14: f853 3c54 ldr.w r3, [r3, #-84] 8005e18: 011a lsls r2, r3, #4 8005e1a: 687b ldr r3, [r7, #4] 8005e1c: 681b ldr r3, [r3, #0] 8005e1e: 430a orrs r2, r1 8005e20: f8c3 20bc str.w r2, [r3, #188] ; 0xbc } /* Configure Rx buffer element size */ if (hfdcan->Init.RxBuffersNbr > 0U) 8005e24: 687b ldr r3, [r7, #4] 8005e26: 6d1b ldr r3, [r3, #80] ; 0x50 8005e28: 2b00 cmp r3, #0 8005e2a: d012 beq.n 8005e52 { MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos)); 8005e2c: 687b ldr r3, [r7, #4] 8005e2e: 681b ldr r3, [r3, #0] 8005e30: f8d3 30bc ldr.w r3, [r3, #188] ; 0xbc 8005e34: f423 61e0 bic.w r1, r3, #1792 ; 0x700 8005e38: 687b ldr r3, [r7, #4] 8005e3a: 6d5b ldr r3, [r3, #84] ; 0x54 8005e3c: 009b lsls r3, r3, #2 8005e3e: 3360 adds r3, #96 ; 0x60 8005e40: 443b add r3, r7 8005e42: f853 3c54 ldr.w r3, [r3, #-84] 8005e46: 021a lsls r2, r3, #8 8005e48: 687b ldr r3, [r7, #4] 8005e4a: 681b ldr r3, [r3, #0] 8005e4c: 430a orrs r2, r1 8005e4e: f8c3 20bc str.w r2, [r3, #188] ; 0xbc } /* By default operation mode is set to Event-driven communication. If Time-triggered communication is needed, user should call the HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */ if (hfdcan->Instance == FDCAN1) 8005e52: 687b ldr r3, [r7, #4] 8005e54: 681b ldr r3, [r3, #0] 8005e56: 4a11 ldr r2, [pc, #68] ; (8005e9c ) 8005e58: 4293 cmp r3, r2 8005e5a: d107 bne.n 8005e6c { CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM); 8005e5c: 687b ldr r3, [r7, #4] 8005e5e: 685b ldr r3, [r3, #4] 8005e60: 689a ldr r2, [r3, #8] 8005e62: 687b ldr r3, [r7, #4] 8005e64: 685b ldr r3, [r3, #4] 8005e66: f022 0203 bic.w r2, r2, #3 8005e6a: 609a str r2, [r3, #8] } /* Initialize the Latest Tx FIFO/Queue request buffer index */ hfdcan->LatestTxFifoQRequest = 0U; 8005e6c: 687b ldr r3, [r7, #4] 8005e6e: 2200 movs r2, #0 8005e70: f8c3 2094 str.w r2, [r3, #148] ; 0x94 /* Initialize the error code */ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; 8005e74: 687b ldr r3, [r7, #4] 8005e76: 2200 movs r2, #0 8005e78: f8c3 209c str.w r2, [r3, #156] ; 0x9c /* Initialize the FDCAN state */ hfdcan->State = HAL_FDCAN_STATE_READY; 8005e7c: 687b ldr r3, [r7, #4] 8005e7e: 2201 movs r2, #1 8005e80: f883 2098 strb.w r2, [r3, #152] ; 0x98 /* Calculate each RAM block address */ status = FDCAN_CalcultateRamBlockAddresses(hfdcan); 8005e84: 6878 ldr r0, [r7, #4] 8005e86: f000 fb0d bl 80064a4 8005e8a: 4603 mov r3, r0 8005e8c: f887 305b strb.w r3, [r7, #91] ; 0x5b /* Return function status */ return status; 8005e90: f897 305b ldrb.w r3, [r7, #91] ; 0x5b } 8005e94: 4618 mov r0, r3 8005e96: 3760 adds r7, #96 ; 0x60 8005e98: 46bd mov sp, r7 8005e9a: bd80 pop {r7, pc} 8005e9c: 4000a000 .word 0x4000a000 08005ea0 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval HAL status */ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) { 8005ea0: b580 push {r7, lr} 8005ea2: b096 sub sp, #88 ; 0x58 8005ea4: af00 add r7, sp, #0 8005ea6: 6078 str r0, [r7, #4] uint32_t itsourceIE; uint32_t itsourceTTIE; uint32_t itflagIR; uint32_t itflagTTIR; ClkCalibrationITs = (FDCAN_CCU->IR << 30); 8005ea8: 4b95 ldr r3, [pc, #596] ; (8006100 ) 8005eaa: 691b ldr r3, [r3, #16] 8005eac: 079b lsls r3, r3, #30 8005eae: 657b str r3, [r7, #84] ; 0x54 ClkCalibrationITs &= (FDCAN_CCU->IE << 30); 8005eb0: 4b93 ldr r3, [pc, #588] ; (8006100 ) 8005eb2: 695b ldr r3, [r3, #20] 8005eb4: 079b lsls r3, r3, #30 8005eb6: 6d7a ldr r2, [r7, #84] ; 0x54 8005eb8: 4013 ands r3, r2 8005eba: 657b str r3, [r7, #84] ; 0x54 TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK; 8005ebc: 687b ldr r3, [r7, #4] 8005ebe: 681b ldr r3, [r3, #0] 8005ec0: 6d1b ldr r3, [r3, #80] ; 0x50 8005ec2: f403 4370 and.w r3, r3, #61440 ; 0xf000 8005ec6: 653b str r3, [r7, #80] ; 0x50 TxEventFifoITs &= hfdcan->Instance->IE; 8005ec8: 687b ldr r3, [r7, #4] 8005eca: 681b ldr r3, [r3, #0] 8005ecc: 6d5b ldr r3, [r3, #84] ; 0x54 8005ece: 6d3a ldr r2, [r7, #80] ; 0x50 8005ed0: 4013 ands r3, r2 8005ed2: 653b str r3, [r7, #80] ; 0x50 RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK; 8005ed4: 687b ldr r3, [r7, #4] 8005ed6: 681b ldr r3, [r3, #0] 8005ed8: 6d1b ldr r3, [r3, #80] ; 0x50 8005eda: f003 030f and.w r3, r3, #15 8005ede: 64fb str r3, [r7, #76] ; 0x4c RxFifo0ITs &= hfdcan->Instance->IE; 8005ee0: 687b ldr r3, [r7, #4] 8005ee2: 681b ldr r3, [r3, #0] 8005ee4: 6d5b ldr r3, [r3, #84] ; 0x54 8005ee6: 6cfa ldr r2, [r7, #76] ; 0x4c 8005ee8: 4013 ands r3, r2 8005eea: 64fb str r3, [r7, #76] ; 0x4c RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK; 8005eec: 687b ldr r3, [r7, #4] 8005eee: 681b ldr r3, [r3, #0] 8005ef0: 6d1b ldr r3, [r3, #80] ; 0x50 8005ef2: f003 03f0 and.w r3, r3, #240 ; 0xf0 8005ef6: 64bb str r3, [r7, #72] ; 0x48 RxFifo1ITs &= hfdcan->Instance->IE; 8005ef8: 687b ldr r3, [r7, #4] 8005efa: 681b ldr r3, [r3, #0] 8005efc: 6d5b ldr r3, [r3, #84] ; 0x54 8005efe: 6cba ldr r2, [r7, #72] ; 0x48 8005f00: 4013 ands r3, r2 8005f02: 64bb str r3, [r7, #72] ; 0x48 Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK; 8005f04: 687b ldr r3, [r7, #4] 8005f06: 681b ldr r3, [r3, #0] 8005f08: 6d1b ldr r3, [r3, #80] ; 0x50 8005f0a: f003 5371 and.w r3, r3, #1010827264 ; 0x3c400000 8005f0e: 647b str r3, [r7, #68] ; 0x44 Errors &= hfdcan->Instance->IE; 8005f10: 687b ldr r3, [r7, #4] 8005f12: 681b ldr r3, [r3, #0] 8005f14: 6d5b ldr r3, [r3, #84] ; 0x54 8005f16: 6c7a ldr r2, [r7, #68] ; 0x44 8005f18: 4013 ands r3, r2 8005f1a: 647b str r3, [r7, #68] ; 0x44 ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK; 8005f1c: 687b ldr r3, [r7, #4] 8005f1e: 681b ldr r3, [r3, #0] 8005f20: 6d1b ldr r3, [r3, #80] ; 0x50 8005f22: f003 7360 and.w r3, r3, #58720256 ; 0x3800000 8005f26: 643b str r3, [r7, #64] ; 0x40 ErrorStatusITs &= hfdcan->Instance->IE; 8005f28: 687b ldr r3, [r7, #4] 8005f2a: 681b ldr r3, [r3, #0] 8005f2c: 6d5b ldr r3, [r3, #84] ; 0x54 8005f2e: 6c3a ldr r2, [r7, #64] ; 0x40 8005f30: 4013 ands r3, r2 8005f32: 643b str r3, [r7, #64] ; 0x40 itsourceIE = hfdcan->Instance->IE; 8005f34: 687b ldr r3, [r7, #4] 8005f36: 681b ldr r3, [r3, #0] 8005f38: 6d5b ldr r3, [r3, #84] ; 0x54 8005f3a: 63fb str r3, [r7, #60] ; 0x3c itflagIR = hfdcan->Instance->IR; 8005f3c: 687b ldr r3, [r7, #4] 8005f3e: 681b ldr r3, [r3, #0] 8005f40: 6d1b ldr r3, [r3, #80] ; 0x50 8005f42: 63bb str r3, [r7, #56] ; 0x38 /* High Priority Message interrupt management *******************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET) 8005f44: 6bfb ldr r3, [r7, #60] ; 0x3c 8005f46: f403 7380 and.w r3, r3, #256 ; 0x100 8005f4a: 2b00 cmp r3, #0 8005f4c: d00f beq.n 8005f6e { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET) 8005f4e: 6bbb ldr r3, [r7, #56] ; 0x38 8005f50: f403 7380 and.w r3, r3, #256 ; 0x100 8005f54: 2b00 cmp r3, #0 8005f56: d00a beq.n 8005f6e { /* Clear the High Priority Message flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG); 8005f58: 687b ldr r3, [r7, #4] 8005f5a: 681b ldr r3, [r3, #0] 8005f5c: f44f 7280 mov.w r2, #256 ; 0x100 8005f60: 651a str r2, [r3, #80] ; 0x50 8005f62: 4b67 ldr r3, [pc, #412] ; (8006100 ) 8005f64: 2200 movs r2, #0 8005f66: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->HighPriorityMessageCallback(hfdcan); #else /* High Priority Message Callback */ HAL_FDCAN_HighPriorityMessageCallback(hfdcan); 8005f68: 6878 ldr r0, [r7, #4] 8005f6a: f000 fa4f bl 800640c #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Transmission Abort interrupt management **********************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET) 8005f6e: 6bfb ldr r3, [r7, #60] ; 0x3c 8005f70: f403 6380 and.w r3, r3, #1024 ; 0x400 8005f74: 2b00 cmp r3, #0 8005f76: d01c beq.n 8005fb2 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET) 8005f78: 6bbb ldr r3, [r7, #56] ; 0x38 8005f7a: f403 6380 and.w r3, r3, #1024 ; 0x400 8005f7e: 2b00 cmp r3, #0 8005f80: d017 beq.n 8005fb2 { /* List of aborted monitored buffers */ AbortedBuffers = hfdcan->Instance->TXBCF; 8005f82: 687b ldr r3, [r7, #4] 8005f84: 681b ldr r3, [r3, #0] 8005f86: f8d3 30dc ldr.w r3, [r3, #220] ; 0xdc 8005f8a: 637b str r3, [r7, #52] ; 0x34 AbortedBuffers &= hfdcan->Instance->TXBCIE; 8005f8c: 687b ldr r3, [r7, #4] 8005f8e: 681b ldr r3, [r3, #0] 8005f90: f8d3 30e4 ldr.w r3, [r3, #228] ; 0xe4 8005f94: 6b7a ldr r2, [r7, #52] ; 0x34 8005f96: 4013 ands r3, r2 8005f98: 637b str r3, [r7, #52] ; 0x34 /* Clear the Transmission Cancellation flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE); 8005f9a: 687b ldr r3, [r7, #4] 8005f9c: 681b ldr r3, [r3, #0] 8005f9e: f44f 6280 mov.w r2, #1024 ; 0x400 8005fa2: 651a str r2, [r3, #80] ; 0x50 8005fa4: 4b56 ldr r3, [pc, #344] ; (8006100 ) 8005fa6: 2200 movs r2, #0 8005fa8: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers); #else /* Transmission Cancellation Callback */ HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers); 8005faa: 6b79 ldr r1, [r7, #52] ; 0x34 8005fac: 6878 ldr r0, [r7, #4] 8005fae: f000 fa04 bl 80063ba #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Clock calibration unit interrupts management *****************************/ if (ClkCalibrationITs != 0U) 8005fb2: 6d7b ldr r3, [r7, #84] ; 0x54 8005fb4: 2b00 cmp r3, #0 8005fb6: d00d beq.n 8005fd4 { /* Clear the Clock Calibration flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs); 8005fb8: 687b ldr r3, [r7, #4] 8005fba: 681a ldr r2, [r3, #0] 8005fbc: 6d79 ldr r1, [r7, #84] ; 0x54 8005fbe: 4b51 ldr r3, [pc, #324] ; (8006104 ) 8005fc0: 400b ands r3, r1 8005fc2: 6513 str r3, [r2, #80] ; 0x50 8005fc4: 4a4e ldr r2, [pc, #312] ; (8006100 ) 8005fc6: 6d7b ldr r3, [r7, #84] ; 0x54 8005fc8: 0f9b lsrs r3, r3, #30 8005fca: 6113 str r3, [r2, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs); #else /* Clock Calibration Callback */ HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs); 8005fcc: 6d79 ldr r1, [r7, #84] ; 0x54 8005fce: 6878 ldr r0, [r7, #4] 8005fd0: f000 f9b2 bl 8006338 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* Tx event FIFO interrupts management **************************************/ if (TxEventFifoITs != 0U) 8005fd4: 6d3b ldr r3, [r7, #80] ; 0x50 8005fd6: 2b00 cmp r3, #0 8005fd8: d00d beq.n 8005ff6 { /* Clear the Tx Event FIFO flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs); 8005fda: 687b ldr r3, [r7, #4] 8005fdc: 681a ldr r2, [r3, #0] 8005fde: 6d39 ldr r1, [r7, #80] ; 0x50 8005fe0: 4b48 ldr r3, [pc, #288] ; (8006104 ) 8005fe2: 400b ands r3, r1 8005fe4: 6513 str r3, [r2, #80] ; 0x50 8005fe6: 4a46 ldr r2, [pc, #280] ; (8006100 ) 8005fe8: 6d3b ldr r3, [r7, #80] ; 0x50 8005fea: 0f9b lsrs r3, r3, #30 8005fec: 6113 str r3, [r2, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs); #else /* Tx Event FIFO Callback */ HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs); 8005fee: 6d39 ldr r1, [r7, #80] ; 0x50 8005ff0: 6878 ldr r0, [r7, #4] 8005ff2: f000 f9ac bl 800634e #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* Rx FIFO 0 interrupts management ******************************************/ if (RxFifo0ITs != 0U) 8005ff6: 6cfb ldr r3, [r7, #76] ; 0x4c 8005ff8: 2b00 cmp r3, #0 8005ffa: d00d beq.n 8006018 { /* Clear the Rx FIFO 0 flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs); 8005ffc: 687b ldr r3, [r7, #4] 8005ffe: 681a ldr r2, [r3, #0] 8006000: 6cf9 ldr r1, [r7, #76] ; 0x4c 8006002: 4b40 ldr r3, [pc, #256] ; (8006104 ) 8006004: 400b ands r3, r1 8006006: 6513 str r3, [r2, #80] ; 0x50 8006008: 4a3d ldr r2, [pc, #244] ; (8006100 ) 800600a: 6cfb ldr r3, [r7, #76] ; 0x4c 800600c: 0f9b lsrs r3, r3, #30 800600e: 6113 str r3, [r2, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs); #else /* Rx FIFO 0 Callback */ HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs); 8006010: 6cf9 ldr r1, [r7, #76] ; 0x4c 8006012: 6878 ldr r0, [r7, #4] 8006014: f000 f9a6 bl 8006364 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* Rx FIFO 1 interrupts management ******************************************/ if (RxFifo1ITs != 0U) 8006018: 6cbb ldr r3, [r7, #72] ; 0x48 800601a: 2b00 cmp r3, #0 800601c: d00d beq.n 800603a { /* Clear the Rx FIFO 1 flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs); 800601e: 687b ldr r3, [r7, #4] 8006020: 681a ldr r2, [r3, #0] 8006022: 6cb9 ldr r1, [r7, #72] ; 0x48 8006024: 4b37 ldr r3, [pc, #220] ; (8006104 ) 8006026: 400b ands r3, r1 8006028: 6513 str r3, [r2, #80] ; 0x50 800602a: 4a35 ldr r2, [pc, #212] ; (8006100 ) 800602c: 6cbb ldr r3, [r7, #72] ; 0x48 800602e: 0f9b lsrs r3, r3, #30 8006030: 6113 str r3, [r2, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs); #else /* Rx FIFO 1 Callback */ HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs); 8006032: 6cb9 ldr r1, [r7, #72] ; 0x48 8006034: 6878 ldr r0, [r7, #4] 8006036: f000 f9a0 bl 800637a #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* Tx FIFO empty interrupt management ***************************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET) 800603a: 6bfb ldr r3, [r7, #60] ; 0x3c 800603c: f403 6300 and.w r3, r3, #2048 ; 0x800 8006040: 2b00 cmp r3, #0 8006042: d00f beq.n 8006064 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET) 8006044: 6bbb ldr r3, [r7, #56] ; 0x38 8006046: f403 6300 and.w r3, r3, #2048 ; 0x800 800604a: 2b00 cmp r3, #0 800604c: d00a beq.n 8006064 { /* Clear the Tx FIFO empty flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY); 800604e: 687b ldr r3, [r7, #4] 8006050: 681b ldr r3, [r3, #0] 8006052: f44f 6200 mov.w r2, #2048 ; 0x800 8006056: 651a str r2, [r3, #80] ; 0x50 8006058: 4b29 ldr r3, [pc, #164] ; (8006100 ) 800605a: 2200 movs r2, #0 800605c: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TxFifoEmptyCallback(hfdcan); #else /* Tx FIFO empty Callback */ HAL_FDCAN_TxFifoEmptyCallback(hfdcan); 800605e: 6878 ldr r0, [r7, #4] 8006060: f000 f996 bl 8006390 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Transmission Complete interrupt management *******************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET) 8006064: 6bfb ldr r3, [r7, #60] ; 0x3c 8006066: f403 7300 and.w r3, r3, #512 ; 0x200 800606a: 2b00 cmp r3, #0 800606c: d01c beq.n 80060a8 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET) 800606e: 6bbb ldr r3, [r7, #56] ; 0x38 8006070: f403 7300 and.w r3, r3, #512 ; 0x200 8006074: 2b00 cmp r3, #0 8006076: d017 beq.n 80060a8 { /* List of transmitted monitored buffers */ TransmittedBuffers = hfdcan->Instance->TXBTO; 8006078: 687b ldr r3, [r7, #4] 800607a: 681b ldr r3, [r3, #0] 800607c: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 8006080: 633b str r3, [r7, #48] ; 0x30 TransmittedBuffers &= hfdcan->Instance->TXBTIE; 8006082: 687b ldr r3, [r7, #4] 8006084: 681b ldr r3, [r3, #0] 8006086: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 800608a: 6b3a ldr r2, [r7, #48] ; 0x30 800608c: 4013 ands r3, r2 800608e: 633b str r3, [r7, #48] ; 0x30 /* Clear the Transmission Complete flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE); 8006090: 687b ldr r3, [r7, #4] 8006092: 681b ldr r3, [r3, #0] 8006094: f44f 7200 mov.w r2, #512 ; 0x200 8006098: 651a str r2, [r3, #80] ; 0x50 800609a: 4b19 ldr r3, [pc, #100] ; (8006100 ) 800609c: 2200 movs r2, #0 800609e: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers); #else /* Transmission Complete Callback */ HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers); 80060a0: 6b39 ldr r1, [r7, #48] ; 0x30 80060a2: 6878 ldr r0, [r7, #4] 80060a4: f000 f97e bl 80063a4 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Rx Buffer New Message interrupt management *******************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET) 80060a8: 6bfb ldr r3, [r7, #60] ; 0x3c 80060aa: f403 2300 and.w r3, r3, #524288 ; 0x80000 80060ae: 2b00 cmp r3, #0 80060b0: d00f beq.n 80060d2 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET) 80060b2: 6bbb ldr r3, [r7, #56] ; 0x38 80060b4: f403 2300 and.w r3, r3, #524288 ; 0x80000 80060b8: 2b00 cmp r3, #0 80060ba: d00a beq.n 80060d2 { /* Clear the Rx Buffer New Message flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE); 80060bc: 687b ldr r3, [r7, #4] 80060be: 681b ldr r3, [r3, #0] 80060c0: f44f 2200 mov.w r2, #524288 ; 0x80000 80060c4: 651a str r2, [r3, #80] ; 0x50 80060c6: 4b0e ldr r3, [pc, #56] ; (8006100 ) 80060c8: 2200 movs r2, #0 80060ca: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->RxBufferNewMessageCallback(hfdcan); #else /* Rx Buffer New Message Callback */ HAL_FDCAN_RxBufferNewMessageCallback(hfdcan); 80060cc: 6878 ldr r0, [r7, #4] 80060ce: f000 f97f bl 80063d0 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Timestamp Wraparound interrupt management ********************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET) 80060d2: 6bfb ldr r3, [r7, #60] ; 0x3c 80060d4: f403 3380 and.w r3, r3, #65536 ; 0x10000 80060d8: 2b00 cmp r3, #0 80060da: d015 beq.n 8006108 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET) 80060dc: 6bbb ldr r3, [r7, #56] ; 0x38 80060de: f403 3380 and.w r3, r3, #65536 ; 0x10000 80060e2: 2b00 cmp r3, #0 80060e4: d010 beq.n 8006108 { /* Clear the Timestamp Wraparound flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND); 80060e6: 687b ldr r3, [r7, #4] 80060e8: 681b ldr r3, [r3, #0] 80060ea: f44f 3280 mov.w r2, #65536 ; 0x10000 80060ee: 651a str r2, [r3, #80] ; 0x50 80060f0: 4b03 ldr r3, [pc, #12] ; (8006100 ) 80060f2: 2200 movs r2, #0 80060f4: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TimestampWraparoundCallback(hfdcan); #else /* Timestamp Wraparound Callback */ HAL_FDCAN_TimestampWraparoundCallback(hfdcan); 80060f6: 6878 ldr r0, [r7, #4] 80060f8: f000 f974 bl 80063e4 80060fc: e004 b.n 8006108 80060fe: bf00 nop 8006100: 4000a800 .word 0x4000a800 8006104: 3fcfffff .word 0x3fcfffff #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Timeout Occurred interrupt management ************************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET) 8006108: 6bfb ldr r3, [r7, #60] ; 0x3c 800610a: f403 2380 and.w r3, r3, #262144 ; 0x40000 800610e: 2b00 cmp r3, #0 8006110: d00f beq.n 8006132 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET) 8006112: 6bbb ldr r3, [r7, #56] ; 0x38 8006114: f403 2380 and.w r3, r3, #262144 ; 0x40000 8006118: 2b00 cmp r3, #0 800611a: d00a beq.n 8006132 { /* Clear the Timeout Occurred flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED); 800611c: 687b ldr r3, [r7, #4] 800611e: 681b ldr r3, [r3, #0] 8006120: f44f 2280 mov.w r2, #262144 ; 0x40000 8006124: 651a str r2, [r3, #80] ; 0x50 8006126: 4b81 ldr r3, [pc, #516] ; (800632c ) 8006128: 2200 movs r2, #0 800612a: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TimeoutOccurredCallback(hfdcan); #else /* Timeout Occurred Callback */ HAL_FDCAN_TimeoutOccurredCallback(hfdcan); 800612c: 6878 ldr r0, [r7, #4] 800612e: f000 f963 bl 80063f8 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Message RAM access failure interrupt management **************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET) 8006132: 6bfb ldr r3, [r7, #60] ; 0x3c 8006134: f403 3300 and.w r3, r3, #131072 ; 0x20000 8006138: 2b00 cmp r3, #0 800613a: d014 beq.n 8006166 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET) 800613c: 6bbb ldr r3, [r7, #56] ; 0x38 800613e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8006142: 2b00 cmp r3, #0 8006144: d00f beq.n 8006166 { /* Clear the Message RAM access failure flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE); 8006146: 687b ldr r3, [r7, #4] 8006148: 681b ldr r3, [r3, #0] 800614a: f44f 3200 mov.w r2, #131072 ; 0x20000 800614e: 651a str r2, [r3, #80] ; 0x50 8006150: 4b76 ldr r3, [pc, #472] ; (800632c ) 8006152: 2200 movs r2, #0 8006154: 611a str r2, [r3, #16] /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS; 8006156: 687b ldr r3, [r7, #4] 8006158: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 800615c: f043 0280 orr.w r2, r3, #128 ; 0x80 8006160: 687b ldr r3, [r7, #4] 8006162: f8c3 209c str.w r2, [r3, #156] ; 0x9c } } /* Error Status interrupts management ***************************************/ if (ErrorStatusITs != 0U) 8006166: 6c3b ldr r3, [r7, #64] ; 0x40 8006168: 2b00 cmp r3, #0 800616a: d00d beq.n 8006188 { /* Clear the Error flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs); 800616c: 687b ldr r3, [r7, #4] 800616e: 681a ldr r2, [r3, #0] 8006170: 6c39 ldr r1, [r7, #64] ; 0x40 8006172: 4b6f ldr r3, [pc, #444] ; (8006330 ) 8006174: 400b ands r3, r1 8006176: 6513 str r3, [r2, #80] ; 0x50 8006178: 4a6c ldr r2, [pc, #432] ; (800632c ) 800617a: 6c3b ldr r3, [r7, #64] ; 0x40 800617c: 0f9b lsrs r3, r3, #30 800617e: 6113 str r3, [r2, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs); #else /* Error Status Callback */ HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs); 8006180: 6c39 ldr r1, [r7, #64] ; 0x40 8006182: 6878 ldr r0, [r7, #4] 8006184: f000 f956 bl 8006434 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* Error interrupts management **********************************************/ if (Errors != 0U) 8006188: 6c7b ldr r3, [r7, #68] ; 0x44 800618a: 2b00 cmp r3, #0 800618c: d011 beq.n 80061b2 { /* Clear the Error flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors); 800618e: 687b ldr r3, [r7, #4] 8006190: 681a ldr r2, [r3, #0] 8006192: 6c79 ldr r1, [r7, #68] ; 0x44 8006194: 4b66 ldr r3, [pc, #408] ; (8006330 ) 8006196: 400b ands r3, r1 8006198: 6513 str r3, [r2, #80] ; 0x50 800619a: 4a64 ldr r2, [pc, #400] ; (800632c ) 800619c: 6c7b ldr r3, [r7, #68] ; 0x44 800619e: 0f9b lsrs r3, r3, #30 80061a0: 6113 str r3, [r2, #16] /* Update error code */ hfdcan->ErrorCode |= Errors; 80061a2: 687b ldr r3, [r7, #4] 80061a4: f8d3 209c ldr.w r2, [r3, #156] ; 0x9c 80061a8: 6c7b ldr r3, [r7, #68] ; 0x44 80061aa: 431a orrs r2, r3 80061ac: 687b ldr r3, [r7, #4] 80061ae: f8c3 209c str.w r2, [r3, #156] ; 0x9c } if (hfdcan->Instance == FDCAN1) 80061b2: 687b ldr r3, [r7, #4] 80061b4: 681b ldr r3, [r3, #0] 80061b6: 4a5f ldr r2, [pc, #380] ; (8006334 ) 80061b8: 4293 cmp r3, r2 80061ba: f040 80aa bne.w 8006312 { if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U) 80061be: 687b ldr r3, [r7, #4] 80061c0: 685b ldr r3, [r3, #4] 80061c2: 689b ldr r3, [r3, #8] 80061c4: f003 0303 and.w r3, r3, #3 80061c8: 2b00 cmp r3, #0 80061ca: f000 80a2 beq.w 8006312 { TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK; 80061ce: 687b ldr r3, [r7, #4] 80061d0: 685b ldr r3, [r3, #4] 80061d2: 6a1b ldr r3, [r3, #32] 80061d4: f003 030f and.w r3, r3, #15 80061d8: 62fb str r3, [r7, #44] ; 0x2c TTSchedSyncITs &= hfdcan->ttcan->TTIE; 80061da: 687b ldr r3, [r7, #4] 80061dc: 685b ldr r3, [r3, #4] 80061de: 6a5b ldr r3, [r3, #36] ; 0x24 80061e0: 6afa ldr r2, [r7, #44] ; 0x2c 80061e2: 4013 ands r3, r2 80061e4: 62fb str r3, [r7, #44] ; 0x2c TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK; 80061e6: 687b ldr r3, [r7, #4] 80061e8: 685b ldr r3, [r3, #4] 80061ea: 6a1b ldr r3, [r3, #32] 80061ec: f003 0330 and.w r3, r3, #48 ; 0x30 80061f0: 62bb str r3, [r7, #40] ; 0x28 TTTimeMarkITs &= hfdcan->ttcan->TTIE; 80061f2: 687b ldr r3, [r7, #4] 80061f4: 685b ldr r3, [r3, #4] 80061f6: 6a5b ldr r3, [r3, #36] ; 0x24 80061f8: 6aba ldr r2, [r7, #40] ; 0x28 80061fa: 4013 ands r3, r2 80061fc: 62bb str r3, [r7, #40] ; 0x28 TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK; 80061fe: 687b ldr r3, [r7, #4] 8006200: 685b ldr r3, [r3, #4] 8006202: 6a1b ldr r3, [r3, #32] 8006204: f403 73c0 and.w r3, r3, #384 ; 0x180 8006208: 627b str r3, [r7, #36] ; 0x24 TTGlobTimeITs &= hfdcan->ttcan->TTIE; 800620a: 687b ldr r3, [r7, #4] 800620c: 685b ldr r3, [r3, #4] 800620e: 6a5b ldr r3, [r3, #36] ; 0x24 8006210: 6a7a ldr r2, [r7, #36] ; 0x24 8006212: 4013 ands r3, r2 8006214: 627b str r3, [r7, #36] ; 0x24 TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK; 8006216: 687b ldr r3, [r7, #4] 8006218: 685b ldr r3, [r3, #4] 800621a: 6a1b ldr r3, [r3, #32] 800621c: f403 43fc and.w r3, r3, #32256 ; 0x7e00 8006220: 623b str r3, [r7, #32] TTDistErrors &= hfdcan->ttcan->TTIE; 8006222: 687b ldr r3, [r7, #4] 8006224: 685b ldr r3, [r3, #4] 8006226: 6a5b ldr r3, [r3, #36] ; 0x24 8006228: 6a3a ldr r2, [r7, #32] 800622a: 4013 ands r3, r2 800622c: 623b str r3, [r7, #32] TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK; 800622e: 687b ldr r3, [r7, #4] 8006230: 685b ldr r3, [r3, #4] 8006232: 6a1b ldr r3, [r3, #32] 8006234: f403 23f0 and.w r3, r3, #491520 ; 0x78000 8006238: 61fb str r3, [r7, #28] TTFatalErrors &= hfdcan->ttcan->TTIE; 800623a: 687b ldr r3, [r7, #4] 800623c: 685b ldr r3, [r3, #4] 800623e: 6a5b ldr r3, [r3, #36] ; 0x24 8006240: 69fa ldr r2, [r7, #28] 8006242: 4013 ands r3, r2 8006244: 61fb str r3, [r7, #28] itsourceTTIE = hfdcan->ttcan->TTIE; 8006246: 687b ldr r3, [r7, #4] 8006248: 685b ldr r3, [r3, #4] 800624a: 6a5b ldr r3, [r3, #36] ; 0x24 800624c: 61bb str r3, [r7, #24] itflagTTIR = hfdcan->ttcan->TTIR; 800624e: 687b ldr r3, [r7, #4] 8006250: 685b ldr r3, [r3, #4] 8006252: 6a1b ldr r3, [r3, #32] 8006254: 617b str r3, [r7, #20] /* TT Schedule Synchronization interrupts management **********************/ if (TTSchedSyncITs != 0U) 8006256: 6afb ldr r3, [r7, #44] ; 0x2c 8006258: 2b00 cmp r3, #0 800625a: d007 beq.n 800626c { /* Clear the TT Schedule Synchronization flags */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs); 800625c: 687b ldr r3, [r7, #4] 800625e: 685b ldr r3, [r3, #4] 8006260: 6afa ldr r2, [r7, #44] ; 0x2c 8006262: 621a str r2, [r3, #32] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs); #else /* TT Schedule Synchronization Callback */ HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs); 8006264: 6af9 ldr r1, [r7, #44] ; 0x2c 8006266: 6878 ldr r0, [r7, #4] 8006268: f000 f8ef bl 800644a #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* TT Time Mark interrupts management *************************************/ if (TTTimeMarkITs != 0U) 800626c: 6abb ldr r3, [r7, #40] ; 0x28 800626e: 2b00 cmp r3, #0 8006270: d007 beq.n 8006282 { /* Clear the TT Time Mark flags */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs); 8006272: 687b ldr r3, [r7, #4] 8006274: 685b ldr r3, [r3, #4] 8006276: 6aba ldr r2, [r7, #40] ; 0x28 8006278: 621a str r2, [r3, #32] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs); #else /* TT Time Mark Callback */ HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs); 800627a: 6ab9 ldr r1, [r7, #40] ; 0x28 800627c: 6878 ldr r0, [r7, #4] 800627e: f000 f8ef bl 8006460 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* TT Stop Watch interrupt management *************************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET) 8006282: 69bb ldr r3, [r7, #24] 8006284: f003 0340 and.w r3, r3, #64 ; 0x40 8006288: 2b00 cmp r3, #0 800628a: d019 beq.n 80062c0 { if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET) 800628c: 697b ldr r3, [r7, #20] 800628e: f003 0340 and.w r3, r3, #64 ; 0x40 8006292: 2b00 cmp r3, #0 8006294: d014 beq.n 80062c0 { /* Retrieve Stop watch Time and Cycle count */ SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos); 8006296: 687b ldr r3, [r7, #4] 8006298: 685b ldr r3, [r3, #4] 800629a: 6bdb ldr r3, [r3, #60] ; 0x3c 800629c: 0c1b lsrs r3, r3, #16 800629e: b29b uxth r3, r3 80062a0: 613b str r3, [r7, #16] SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos); 80062a2: 687b ldr r3, [r7, #4] 80062a4: 685b ldr r3, [r3, #4] 80062a6: 6bdb ldr r3, [r3, #60] ; 0x3c 80062a8: f003 033f and.w r3, r3, #63 ; 0x3f 80062ac: 60fb str r3, [r7, #12] /* Clear the TT Stop Watch flag */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH); 80062ae: 687b ldr r3, [r7, #4] 80062b0: 685b ldr r3, [r3, #4] 80062b2: 2240 movs r2, #64 ; 0x40 80062b4: 621a str r2, [r3, #32] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount); #else /* TT Stop Watch Callback */ HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount); 80062b6: 68fa ldr r2, [r7, #12] 80062b8: 6939 ldr r1, [r7, #16] 80062ba: 6878 ldr r0, [r7, #4] 80062bc: f000 f8db bl 8006476 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* TT Global Time interrupts management ***********************************/ if (TTGlobTimeITs != 0U) 80062c0: 6a7b ldr r3, [r7, #36] ; 0x24 80062c2: 2b00 cmp r3, #0 80062c4: d007 beq.n 80062d6 { /* Clear the TT Global Time flags */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs); 80062c6: 687b ldr r3, [r7, #4] 80062c8: 685b ldr r3, [r3, #4] 80062ca: 6a7a ldr r2, [r7, #36] ; 0x24 80062cc: 621a str r2, [r3, #32] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs); #else /* TT Global Time Callback */ HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs); 80062ce: 6a79 ldr r1, [r7, #36] ; 0x24 80062d0: 6878 ldr r0, [r7, #4] 80062d2: f000 f8dc bl 800648e #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* TT Disturbing Error interrupts management ******************************/ if (TTDistErrors != 0U) 80062d6: 6a3b ldr r3, [r7, #32] 80062d8: 2b00 cmp r3, #0 80062da: d00b beq.n 80062f4 { /* Clear the TT Disturbing Error flags */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors); 80062dc: 687b ldr r3, [r7, #4] 80062de: 685b ldr r3, [r3, #4] 80062e0: 6a3a ldr r2, [r7, #32] 80062e2: 621a str r2, [r3, #32] /* Update error code */ hfdcan->ErrorCode |= TTDistErrors; 80062e4: 687b ldr r3, [r7, #4] 80062e6: f8d3 209c ldr.w r2, [r3, #156] ; 0x9c 80062ea: 6a3b ldr r3, [r7, #32] 80062ec: 431a orrs r2, r3 80062ee: 687b ldr r3, [r7, #4] 80062f0: f8c3 209c str.w r2, [r3, #156] ; 0x9c } /* TT Fatal Error interrupts management ***********************************/ if (TTFatalErrors != 0U) 80062f4: 69fb ldr r3, [r7, #28] 80062f6: 2b00 cmp r3, #0 80062f8: d00b beq.n 8006312 { /* Clear the TT Fatal Error flags */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors); 80062fa: 687b ldr r3, [r7, #4] 80062fc: 685b ldr r3, [r3, #4] 80062fe: 69fa ldr r2, [r7, #28] 8006300: 621a str r2, [r3, #32] /* Update error code */ hfdcan->ErrorCode |= TTFatalErrors; 8006302: 687b ldr r3, [r7, #4] 8006304: f8d3 209c ldr.w r2, [r3, #156] ; 0x9c 8006308: 69fb ldr r3, [r7, #28] 800630a: 431a orrs r2, r3 800630c: 687b ldr r3, [r7, #4] 800630e: f8c3 209c str.w r2, [r3, #156] ; 0x9c } } } if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE) 8006312: 687b ldr r3, [r7, #4] 8006314: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8006318: 2b00 cmp r3, #0 800631a: d002 beq.n 8006322 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->ErrorCallback(hfdcan); #else /* Error Callback */ HAL_FDCAN_ErrorCallback(hfdcan); 800631c: 6878 ldr r0, [r7, #4] 800631e: f000 f87f bl 8006420 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } 8006322: bf00 nop 8006324: 3758 adds r7, #88 ; 0x58 8006326: 46bd mov sp, r7 8006328: bd80 pop {r7, pc} 800632a: bf00 nop 800632c: 4000a800 .word 0x4000a800 8006330: 3fcfffff .word 0x3fcfffff 8006334: 4000a000 .word 0x4000a000 08006338 : * @param ClkCalibrationITs indicates which Clock Calibration interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts. * @retval None */ __weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs) { 8006338: b480 push {r7} 800633a: b083 sub sp, #12 800633c: af00 add r7, sp, #0 800633e: 6078 str r0, [r7, #4] 8006340: 6039 str r1, [r7, #0] UNUSED(ClkCalibrationITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file */ } 8006342: bf00 nop 8006344: 370c adds r7, #12 8006346: 46bd mov sp, r7 8006348: f85d 7b04 ldr.w r7, [sp], #4 800634c: 4770 bx lr 0800634e : * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts. * @retval None */ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs) { 800634e: b480 push {r7} 8006350: b083 sub sp, #12 8006352: af00 add r7, sp, #0 8006354: 6078 str r0, [r7, #4] 8006356: 6039 str r1, [r7, #0] UNUSED(TxEventFifoITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file */ } 8006358: bf00 nop 800635a: 370c adds r7, #12 800635c: 46bd mov sp, r7 800635e: f85d 7b04 ldr.w r7, [sp], #4 8006362: 4770 bx lr 08006364 : * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts. * @retval None */ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs) { 8006364: b480 push {r7} 8006366: b083 sub sp, #12 8006368: af00 add r7, sp, #0 800636a: 6078 str r0, [r7, #4] 800636c: 6039 str r1, [r7, #0] UNUSED(RxFifo0ITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxFifo0Callback could be implemented in the user file */ } 800636e: bf00 nop 8006370: 370c adds r7, #12 8006372: 46bd mov sp, r7 8006374: f85d 7b04 ldr.w r7, [sp], #4 8006378: 4770 bx lr 0800637a : * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts. * @retval None */ __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs) { 800637a: b480 push {r7} 800637c: b083 sub sp, #12 800637e: af00 add r7, sp, #0 8006380: 6078 str r0, [r7, #4] 8006382: 6039 str r1, [r7, #0] UNUSED(RxFifo1ITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxFifo1Callback could be implemented in the user file */ } 8006384: bf00 nop 8006386: 370c adds r7, #12 8006388: 46bd mov sp, r7 800638a: f85d 7b04 ldr.w r7, [sp], #4 800638e: 4770 bx lr 08006390 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) { 8006390: b480 push {r7} 8006392: b083 sub sp, #12 8006394: af00 add r7, sp, #0 8006396: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file */ } 8006398: bf00 nop 800639a: 370c adds r7, #12 800639c: 46bd mov sp, r7 800639e: f85d 7b04 ldr.w r7, [sp], #4 80063a2: 4770 bx lr 080063a4 : * @param BufferIndexes Indexes of the transmitted buffers. * This parameter can be any combination of @arg FDCAN_Tx_location. * @retval None */ __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) { 80063a4: b480 push {r7} 80063a6: b083 sub sp, #12 80063a8: af00 add r7, sp, #0 80063aa: 6078 str r0, [r7, #4] 80063ac: 6039 str r1, [r7, #0] UNUSED(BufferIndexes); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file */ } 80063ae: bf00 nop 80063b0: 370c adds r7, #12 80063b2: 46bd mov sp, r7 80063b4: f85d 7b04 ldr.w r7, [sp], #4 80063b8: 4770 bx lr 080063ba : * @param BufferIndexes Indexes of the aborted buffers. * This parameter can be any combination of @arg FDCAN_Tx_location. * @retval None */ __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) { 80063ba: b480 push {r7} 80063bc: b083 sub sp, #12 80063be: af00 add r7, sp, #0 80063c0: 6078 str r0, [r7, #4] 80063c2: 6039 str r1, [r7, #0] UNUSED(BufferIndexes); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file */ } 80063c4: bf00 nop 80063c6: 370c adds r7, #12 80063c8: 46bd mov sp, r7 80063ca: f85d 7b04 ldr.w r7, [sp], #4 80063ce: 4770 bx lr 080063d0 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan) { 80063d0: b480 push {r7} 80063d2: b083 sub sp, #12 80063d4: af00 add r7, sp, #0 80063d6: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file */ } 80063d8: bf00 nop 80063da: 370c adds r7, #12 80063dc: 46bd mov sp, r7 80063de: f85d 7b04 ldr.w r7, [sp], #4 80063e2: 4770 bx lr 080063e4 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) { 80063e4: b480 push {r7} 80063e6: b083 sub sp, #12 80063e8: af00 add r7, sp, #0 80063ea: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file */ } 80063ec: bf00 nop 80063ee: 370c adds r7, #12 80063f0: 46bd mov sp, r7 80063f2: f85d 7b04 ldr.w r7, [sp], #4 80063f6: 4770 bx lr 080063f8 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) { 80063f8: b480 push {r7} 80063fa: b083 sub sp, #12 80063fc: af00 add r7, sp, #0 80063fe: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file */ } 8006400: bf00 nop 8006402: 370c adds r7, #12 8006404: 46bd mov sp, r7 8006406: f85d 7b04 ldr.w r7, [sp], #4 800640a: 4770 bx lr 0800640c : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) { 800640c: b480 push {r7} 800640e: b083 sub sp, #12 8006410: af00 add r7, sp, #0 8006412: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file */ } 8006414: bf00 nop 8006416: 370c adds r7, #12 8006418: 46bd mov sp, r7 800641a: f85d 7b04 ldr.w r7, [sp], #4 800641e: 4770 bx lr 08006420 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) { 8006420: b480 push {r7} 8006422: b083 sub sp, #12 8006424: af00 add r7, sp, #0 8006426: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_ErrorCallback could be implemented in the user file */ } 8006428: bf00 nop 800642a: 370c adds r7, #12 800642c: 46bd mov sp, r7 800642e: f85d 7b04 ldr.w r7, [sp], #4 8006432: 4770 bx lr 08006434 : * @param ErrorStatusITs indicates which Error Status interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts. * @retval None */ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs) { 8006434: b480 push {r7} 8006436: b083 sub sp, #12 8006438: af00 add r7, sp, #0 800643a: 6078 str r0, [r7, #4] 800643c: 6039 str r1, [r7, #0] UNUSED(ErrorStatusITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file */ } 800643e: bf00 nop 8006440: 370c adds r7, #12 8006442: 46bd mov sp, r7 8006444: f85d 7b04 ldr.w r7, [sp], #4 8006448: 4770 bx lr 0800644a : * @param TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled. * This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts. * @retval None */ __weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs) { 800644a: b480 push {r7} 800644c: b083 sub sp, #12 800644e: af00 add r7, sp, #0 8006450: 6078 str r0, [r7, #4] 8006452: 6039 str r1, [r7, #0] UNUSED(TTSchedSyncITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file */ } 8006454: bf00 nop 8006456: 370c adds r7, #12 8006458: 46bd mov sp, r7 800645a: f85d 7b04 ldr.w r7, [sp], #4 800645e: 4770 bx lr 08006460 : * @param TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled. * This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts. * @retval None */ __weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs) { 8006460: b480 push {r7} 8006462: b083 sub sp, #12 8006464: af00 add r7, sp, #0 8006466: 6078 str r0, [r7, #4] 8006468: 6039 str r1, [r7, #0] UNUSED(TTTimeMarkITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file */ } 800646a: bf00 nop 800646c: 370c adds r7, #12 800646e: 46bd mov sp, r7 8006470: f85d 7b04 ldr.w r7, [sp], #4 8006474: 4770 bx lr 08006476 : * @param SWCycleCount Cycle count value captured together with SWTime. * This parameter is a number between 0 and 0x3F. * @retval None */ __weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount) { 8006476: b480 push {r7} 8006478: b085 sub sp, #20 800647a: af00 add r7, sp, #0 800647c: 60f8 str r0, [r7, #12] 800647e: 60b9 str r1, [r7, #8] 8006480: 607a str r2, [r7, #4] UNUSED(SWCycleCount); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file */ } 8006482: bf00 nop 8006484: 3714 adds r7, #20 8006486: 46bd mov sp, r7 8006488: f85d 7b04 ldr.w r7, [sp], #4 800648c: 4770 bx lr 0800648e : * @param TTGlobTimeITs indicates which TT Global Time interrupts are signaled. * This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts. * @retval None */ __weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs) { 800648e: b480 push {r7} 8006490: b083 sub sp, #12 8006492: af00 add r7, sp, #0 8006494: 6078 str r0, [r7, #4] 8006496: 6039 str r1, [r7, #0] UNUSED(TTGlobTimeITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file */ } 8006498: bf00 nop 800649a: 370c adds r7, #12 800649c: 46bd mov sp, r7 800649e: f85d 7b04 ldr.w r7, [sp], #4 80064a2: 4770 bx lr 080064a4 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval HAL status */ static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) { 80064a4: b480 push {r7} 80064a6: b085 sub sp, #20 80064a8: af00 add r7, sp, #0 80064aa: 6078 str r0, [r7, #4] uint32_t RAMcounter; uint32_t StartAddress; StartAddress = hfdcan->Init.MessageRAMOffset; 80064ac: 687b ldr r3, [r7, #4] 80064ae: 6b5b ldr r3, [r3, #52] ; 0x34 80064b0: 60bb str r3, [r7, #8] /* Standard filter list start address */ MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos)); 80064b2: 687b ldr r3, [r7, #4] 80064b4: 681b ldr r3, [r3, #0] 80064b6: f8d3 2084 ldr.w r2, [r3, #132] ; 0x84 80064ba: 4ba7 ldr r3, [pc, #668] ; (8006758 ) 80064bc: 4013 ands r3, r2 80064be: 68ba ldr r2, [r7, #8] 80064c0: 0091 lsls r1, r2, #2 80064c2: 687a ldr r2, [r7, #4] 80064c4: 6812 ldr r2, [r2, #0] 80064c6: 430b orrs r3, r1 80064c8: f8c2 3084 str.w r3, [r2, #132] ; 0x84 /* Standard filter elements number */ MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos)); 80064cc: 687b ldr r3, [r7, #4] 80064ce: 681b ldr r3, [r3, #0] 80064d0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80064d4: f423 017f bic.w r1, r3, #16711680 ; 0xff0000 80064d8: 687b ldr r3, [r7, #4] 80064da: 6b9b ldr r3, [r3, #56] ; 0x38 80064dc: 041a lsls r2, r3, #16 80064de: 687b ldr r3, [r7, #4] 80064e0: 681b ldr r3, [r3, #0] 80064e2: 430a orrs r2, r1 80064e4: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Extended filter list start address */ StartAddress += hfdcan->Init.StdFiltersNbr; 80064e8: 687b ldr r3, [r7, #4] 80064ea: 6b9b ldr r3, [r3, #56] ; 0x38 80064ec: 68ba ldr r2, [r7, #8] 80064ee: 4413 add r3, r2 80064f0: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos)); 80064f2: 687b ldr r3, [r7, #4] 80064f4: 681b ldr r3, [r3, #0] 80064f6: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 80064fa: 4b97 ldr r3, [pc, #604] ; (8006758 ) 80064fc: 4013 ands r3, r2 80064fe: 68ba ldr r2, [r7, #8] 8006500: 0091 lsls r1, r2, #2 8006502: 687a ldr r2, [r7, #4] 8006504: 6812 ldr r2, [r2, #0] 8006506: 430b orrs r3, r1 8006508: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Extended filter elements number */ MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos)); 800650c: 687b ldr r3, [r7, #4] 800650e: 681b ldr r3, [r3, #0] 8006510: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8006514: f423 01fe bic.w r1, r3, #8323072 ; 0x7f0000 8006518: 687b ldr r3, [r7, #4] 800651a: 6bdb ldr r3, [r3, #60] ; 0x3c 800651c: 041a lsls r2, r3, #16 800651e: 687b ldr r3, [r7, #4] 8006520: 681b ldr r3, [r3, #0] 8006522: 430a orrs r2, r1 8006524: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Rx FIFO 0 start address */ StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U); 8006528: 687b ldr r3, [r7, #4] 800652a: 6bdb ldr r3, [r3, #60] ; 0x3c 800652c: 005b lsls r3, r3, #1 800652e: 68ba ldr r2, [r7, #8] 8006530: 4413 add r3, r2 8006532: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos)); 8006534: 687b ldr r3, [r7, #4] 8006536: 681b ldr r3, [r3, #0] 8006538: f8d3 20a0 ldr.w r2, [r3, #160] ; 0xa0 800653c: 4b86 ldr r3, [pc, #536] ; (8006758 ) 800653e: 4013 ands r3, r2 8006540: 68ba ldr r2, [r7, #8] 8006542: 0091 lsls r1, r2, #2 8006544: 687a ldr r2, [r7, #4] 8006546: 6812 ldr r2, [r2, #0] 8006548: 430b orrs r3, r1 800654a: f8c2 30a0 str.w r3, [r2, #160] ; 0xa0 /* Rx FIFO 0 elements number */ MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos)); 800654e: 687b ldr r3, [r7, #4] 8006550: 681b ldr r3, [r3, #0] 8006552: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 8006556: f423 01fe bic.w r1, r3, #8323072 ; 0x7f0000 800655a: 687b ldr r3, [r7, #4] 800655c: 6c1b ldr r3, [r3, #64] ; 0x40 800655e: 041a lsls r2, r3, #16 8006560: 687b ldr r3, [r7, #4] 8006562: 681b ldr r3, [r3, #0] 8006564: 430a orrs r2, r1 8006566: f8c3 20a0 str.w r2, [r3, #160] ; 0xa0 /* Rx FIFO 1 start address */ StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize); 800656a: 687b ldr r3, [r7, #4] 800656c: 6c1b ldr r3, [r3, #64] ; 0x40 800656e: 687a ldr r2, [r7, #4] 8006570: 6c52 ldr r2, [r2, #68] ; 0x44 8006572: fb02 f303 mul.w r3, r2, r3 8006576: 68ba ldr r2, [r7, #8] 8006578: 4413 add r3, r2 800657a: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos)); 800657c: 687b ldr r3, [r7, #4] 800657e: 681b ldr r3, [r3, #0] 8006580: f8d3 20b0 ldr.w r2, [r3, #176] ; 0xb0 8006584: 4b74 ldr r3, [pc, #464] ; (8006758 ) 8006586: 4013 ands r3, r2 8006588: 68ba ldr r2, [r7, #8] 800658a: 0091 lsls r1, r2, #2 800658c: 687a ldr r2, [r7, #4] 800658e: 6812 ldr r2, [r2, #0] 8006590: 430b orrs r3, r1 8006592: f8c2 30b0 str.w r3, [r2, #176] ; 0xb0 /* Rx FIFO 1 elements number */ MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos)); 8006596: 687b ldr r3, [r7, #4] 8006598: 681b ldr r3, [r3, #0] 800659a: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 800659e: f423 01fe bic.w r1, r3, #8323072 ; 0x7f0000 80065a2: 687b ldr r3, [r7, #4] 80065a4: 6c9b ldr r3, [r3, #72] ; 0x48 80065a6: 041a lsls r2, r3, #16 80065a8: 687b ldr r3, [r7, #4] 80065aa: 681b ldr r3, [r3, #0] 80065ac: 430a orrs r2, r1 80065ae: f8c3 20b0 str.w r2, [r3, #176] ; 0xb0 /* Rx buffer list start address */ StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize); 80065b2: 687b ldr r3, [r7, #4] 80065b4: 6c9b ldr r3, [r3, #72] ; 0x48 80065b6: 687a ldr r2, [r7, #4] 80065b8: 6cd2 ldr r2, [r2, #76] ; 0x4c 80065ba: fb02 f303 mul.w r3, r2, r3 80065be: 68ba ldr r2, [r7, #8] 80065c0: 4413 add r3, r2 80065c2: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos)); 80065c4: 687b ldr r3, [r7, #4] 80065c6: 681b ldr r3, [r3, #0] 80065c8: f8d3 20ac ldr.w r2, [r3, #172] ; 0xac 80065cc: 4b62 ldr r3, [pc, #392] ; (8006758 ) 80065ce: 4013 ands r3, r2 80065d0: 68ba ldr r2, [r7, #8] 80065d2: 0091 lsls r1, r2, #2 80065d4: 687a ldr r2, [r7, #4] 80065d6: 6812 ldr r2, [r2, #0] 80065d8: 430b orrs r3, r1 80065da: f8c2 30ac str.w r3, [r2, #172] ; 0xac /* Tx event FIFO start address */ StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize); 80065de: 687b ldr r3, [r7, #4] 80065e0: 6d1b ldr r3, [r3, #80] ; 0x50 80065e2: 687a ldr r2, [r7, #4] 80065e4: 6d52 ldr r2, [r2, #84] ; 0x54 80065e6: fb02 f303 mul.w r3, r2, r3 80065ea: 68ba ldr r2, [r7, #8] 80065ec: 4413 add r3, r2 80065ee: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos)); 80065f0: 687b ldr r3, [r7, #4] 80065f2: 681b ldr r3, [r3, #0] 80065f4: f8d3 20f0 ldr.w r2, [r3, #240] ; 0xf0 80065f8: 4b57 ldr r3, [pc, #348] ; (8006758 ) 80065fa: 4013 ands r3, r2 80065fc: 68ba ldr r2, [r7, #8] 80065fe: 0091 lsls r1, r2, #2 8006600: 687a ldr r2, [r7, #4] 8006602: 6812 ldr r2, [r2, #0] 8006604: 430b orrs r3, r1 8006606: f8c2 30f0 str.w r3, [r2, #240] ; 0xf0 /* Tx event FIFO elements number */ MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos)); 800660a: 687b ldr r3, [r7, #4] 800660c: 681b ldr r3, [r3, #0] 800660e: f8d3 30f0 ldr.w r3, [r3, #240] ; 0xf0 8006612: f423 117c bic.w r1, r3, #4128768 ; 0x3f0000 8006616: 687b ldr r3, [r7, #4] 8006618: 6d9b ldr r3, [r3, #88] ; 0x58 800661a: 041a lsls r2, r3, #16 800661c: 687b ldr r3, [r7, #4] 800661e: 681b ldr r3, [r3, #0] 8006620: 430a orrs r2, r1 8006622: f8c3 20f0 str.w r2, [r3, #240] ; 0xf0 /* Tx buffer list start address */ StartAddress += (hfdcan->Init.TxEventsNbr * 2U); 8006626: 687b ldr r3, [r7, #4] 8006628: 6d9b ldr r3, [r3, #88] ; 0x58 800662a: 005b lsls r3, r3, #1 800662c: 68ba ldr r2, [r7, #8] 800662e: 4413 add r3, r2 8006630: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos)); 8006632: 687b ldr r3, [r7, #4] 8006634: 681b ldr r3, [r3, #0] 8006636: f8d3 20c0 ldr.w r2, [r3, #192] ; 0xc0 800663a: 4b47 ldr r3, [pc, #284] ; (8006758 ) 800663c: 4013 ands r3, r2 800663e: 68ba ldr r2, [r7, #8] 8006640: 0091 lsls r1, r2, #2 8006642: 687a ldr r2, [r7, #4] 8006644: 6812 ldr r2, [r2, #0] 8006646: 430b orrs r3, r1 8006648: f8c2 30c0 str.w r3, [r2, #192] ; 0xc0 /* Dedicated Tx buffers number */ MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos)); 800664c: 687b ldr r3, [r7, #4] 800664e: 681b ldr r3, [r3, #0] 8006650: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0 8006654: f423 117c bic.w r1, r3, #4128768 ; 0x3f0000 8006658: 687b ldr r3, [r7, #4] 800665a: 6ddb ldr r3, [r3, #92] ; 0x5c 800665c: 041a lsls r2, r3, #16 800665e: 687b ldr r3, [r7, #4] 8006660: 681b ldr r3, [r3, #0] 8006662: 430a orrs r2, r1 8006664: f8c3 20c0 str.w r2, [r3, #192] ; 0xc0 /* Tx FIFO/queue elements number */ MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos)); 8006668: 687b ldr r3, [r7, #4] 800666a: 681b ldr r3, [r3, #0] 800666c: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0 8006670: f023 517c bic.w r1, r3, #1056964608 ; 0x3f000000 8006674: 687b ldr r3, [r7, #4] 8006676: 6e1b ldr r3, [r3, #96] ; 0x60 8006678: 061a lsls r2, r3, #24 800667a: 687b ldr r3, [r7, #4] 800667c: 681b ldr r3, [r3, #0] 800667e: 430a orrs r2, r1 8006680: f8c3 20c0 str.w r2, [r3, #192] ; 0xc0 hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U); 8006684: 687b ldr r3, [r7, #4] 8006686: 6b5a ldr r2, [r3, #52] ; 0x34 8006688: 4b34 ldr r3, [pc, #208] ; (800675c ) 800668a: 4413 add r3, r2 800668c: 009a lsls r2, r3, #2 800668e: 687b ldr r3, [r7, #4] 8006690: 66da str r2, [r3, #108] ; 0x6c hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U); 8006692: 687b ldr r3, [r7, #4] 8006694: 6eda ldr r2, [r3, #108] ; 0x6c 8006696: 687b ldr r3, [r7, #4] 8006698: 6b9b ldr r3, [r3, #56] ; 0x38 800669a: 009b lsls r3, r3, #2 800669c: 441a add r2, r3 800669e: 687b ldr r3, [r7, #4] 80066a0: 671a str r2, [r3, #112] ; 0x70 hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U); 80066a2: 687b ldr r3, [r7, #4] 80066a4: 6f1a ldr r2, [r3, #112] ; 0x70 80066a6: 687b ldr r3, [r7, #4] 80066a8: 6bdb ldr r3, [r3, #60] ; 0x3c 80066aa: 00db lsls r3, r3, #3 80066ac: 441a add r2, r3 80066ae: 687b ldr r3, [r7, #4] 80066b0: 675a str r2, [r3, #116] ; 0x74 hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U); 80066b2: 687b ldr r3, [r7, #4] 80066b4: 6f5a ldr r2, [r3, #116] ; 0x74 80066b6: 687b ldr r3, [r7, #4] 80066b8: 6c1b ldr r3, [r3, #64] ; 0x40 80066ba: 6879 ldr r1, [r7, #4] 80066bc: 6c49 ldr r1, [r1, #68] ; 0x44 80066be: fb01 f303 mul.w r3, r1, r3 80066c2: 009b lsls r3, r3, #2 80066c4: 441a add r2, r3 80066c6: 687b ldr r3, [r7, #4] 80066c8: 679a str r2, [r3, #120] ; 0x78 hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U); 80066ca: 687b ldr r3, [r7, #4] 80066cc: 6f9a ldr r2, [r3, #120] ; 0x78 80066ce: 687b ldr r3, [r7, #4] 80066d0: 6c9b ldr r3, [r3, #72] ; 0x48 80066d2: 6879 ldr r1, [r7, #4] 80066d4: 6cc9 ldr r1, [r1, #76] ; 0x4c 80066d6: fb01 f303 mul.w r3, r1, r3 80066da: 009b lsls r3, r3, #2 80066dc: 441a add r2, r3 80066de: 687b ldr r3, [r7, #4] 80066e0: 67da str r2, [r3, #124] ; 0x7c hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U); 80066e2: 687b ldr r3, [r7, #4] 80066e4: 6fda ldr r2, [r3, #124] ; 0x7c 80066e6: 687b ldr r3, [r7, #4] 80066e8: 6d1b ldr r3, [r3, #80] ; 0x50 80066ea: 6879 ldr r1, [r7, #4] 80066ec: 6d49 ldr r1, [r1, #84] ; 0x54 80066ee: fb01 f303 mul.w r3, r1, r3 80066f2: 009b lsls r3, r3, #2 80066f4: 441a add r2, r3 80066f6: 687b ldr r3, [r7, #4] 80066f8: f8c3 2080 str.w r2, [r3, #128] ; 0x80 hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U); 80066fc: 687b ldr r3, [r7, #4] 80066fe: f8d3 2080 ldr.w r2, [r3, #128] ; 0x80 8006702: 687b ldr r3, [r7, #4] 8006704: 6d9b ldr r3, [r3, #88] ; 0x58 8006706: 00db lsls r3, r3, #3 8006708: 441a add r2, r3 800670a: 687b ldr r3, [r7, #4] 800670c: f8c3 2084 str.w r2, [r3, #132] ; 0x84 hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U); 8006710: 687b ldr r3, [r7, #4] 8006712: f8d3 2084 ldr.w r2, [r3, #132] ; 0x84 8006716: 687b ldr r3, [r7, #4] 8006718: 6ddb ldr r3, [r3, #92] ; 0x5c 800671a: 6879 ldr r1, [r7, #4] 800671c: 6e89 ldr r1, [r1, #104] ; 0x68 800671e: fb01 f303 mul.w r3, r1, r3 8006722: 009b lsls r3, r3, #2 8006724: 441a add r2, r3 8006726: 687b ldr r3, [r7, #4] 8006728: f8c3 2088 str.w r2, [r3, #136] ; 0x88 hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U); 800672c: 687b ldr r3, [r7, #4] 800672e: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 8006732: 687b ldr r3, [r7, #4] 8006734: 6e1b ldr r3, [r3, #96] ; 0x60 8006736: 6879 ldr r1, [r7, #4] 8006738: 6e89 ldr r1, [r1, #104] ; 0x68 800673a: fb01 f303 mul.w r3, r1, r3 800673e: 009b lsls r3, r3, #2 8006740: 441a add r2, r3 8006742: 687b ldr r3, [r7, #4] 8006744: f8c3 2090 str.w r2, [r3, #144] ; 0x90 if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */ 8006748: 687b ldr r3, [r7, #4] 800674a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 800674e: 4a04 ldr r2, [pc, #16] ; (8006760 ) 8006750: 4293 cmp r3, r2 8006752: d915 bls.n 8006780 8006754: e006 b.n 8006764 8006756: bf00 nop 8006758: ffff0003 .word 0xffff0003 800675c: 10002b00 .word 0x10002b00 8006760: 4000d3fc .word 0x4000d3fc { /* Update error code. Message RAM overflow */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; 8006764: 687b ldr r3, [r7, #4] 8006766: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 800676a: f043 0220 orr.w r2, r3, #32 800676e: 687b ldr r3, [r7, #4] 8006770: f8c3 209c str.w r2, [r3, #156] ; 0x9c /* Change FDCAN state */ hfdcan->State = HAL_FDCAN_STATE_ERROR; 8006774: 687b ldr r3, [r7, #4] 8006776: 2203 movs r2, #3 8006778: f883 2098 strb.w r2, [r3, #152] ; 0x98 return HAL_ERROR; 800677c: 2301 movs r3, #1 800677e: e010 b.n 80067a2 } else { /* Flush the allocated Message RAM area */ for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U) 8006780: 687b ldr r3, [r7, #4] 8006782: 6edb ldr r3, [r3, #108] ; 0x6c 8006784: 60fb str r3, [r7, #12] 8006786: e005 b.n 8006794 { *(uint32_t *)(RAMcounter) = 0x00000000; 8006788: 68fb ldr r3, [r7, #12] 800678a: 2200 movs r2, #0 800678c: 601a str r2, [r3, #0] for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U) 800678e: 68fb ldr r3, [r7, #12] 8006790: 3304 adds r3, #4 8006792: 60fb str r3, [r7, #12] 8006794: 687b ldr r3, [r7, #4] 8006796: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 800679a: 68fa ldr r2, [r7, #12] 800679c: 429a cmp r2, r3 800679e: d3f3 bcc.n 8006788 } } /* Return function status */ return HAL_OK; 80067a0: 2300 movs r3, #0 } 80067a2: 4618 mov r0, r3 80067a4: 3714 adds r7, #20 80067a6: 46bd mov sp, r7 80067a8: f85d 7b04 ldr.w r7, [sp], #4 80067ac: 4770 bx lr 80067ae: bf00 nop 080067b0 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80067b0: b480 push {r7} 80067b2: b089 sub sp, #36 ; 0x24 80067b4: af00 add r7, sp, #0 80067b6: 6078 str r0, [r7, #4] 80067b8: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 80067ba: 2300 movs r3, #0 80067bc: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 80067be: 4b86 ldr r3, [pc, #536] ; (80069d8 ) 80067c0: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 80067c2: e18c b.n 8006ade { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 80067c4: 683b ldr r3, [r7, #0] 80067c6: 681a ldr r2, [r3, #0] 80067c8: 2101 movs r1, #1 80067ca: 69fb ldr r3, [r7, #28] 80067cc: fa01 f303 lsl.w r3, r1, r3 80067d0: 4013 ands r3, r2 80067d2: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 80067d4: 693b ldr r3, [r7, #16] 80067d6: 2b00 cmp r3, #0 80067d8: f000 817e beq.w 8006ad8 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 80067dc: 683b ldr r3, [r7, #0] 80067de: 685b ldr r3, [r3, #4] 80067e0: f003 0303 and.w r3, r3, #3 80067e4: 2b01 cmp r3, #1 80067e6: d005 beq.n 80067f4 80067e8: 683b ldr r3, [r7, #0] 80067ea: 685b ldr r3, [r3, #4] 80067ec: f003 0303 and.w r3, r3, #3 80067f0: 2b02 cmp r3, #2 80067f2: d130 bne.n 8006856 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 80067f4: 687b ldr r3, [r7, #4] 80067f6: 689b ldr r3, [r3, #8] 80067f8: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 80067fa: 69fb ldr r3, [r7, #28] 80067fc: 005b lsls r3, r3, #1 80067fe: 2203 movs r2, #3 8006800: fa02 f303 lsl.w r3, r2, r3 8006804: 43db mvns r3, r3 8006806: 69ba ldr r2, [r7, #24] 8006808: 4013 ands r3, r2 800680a: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800680c: 683b ldr r3, [r7, #0] 800680e: 68da ldr r2, [r3, #12] 8006810: 69fb ldr r3, [r7, #28] 8006812: 005b lsls r3, r3, #1 8006814: fa02 f303 lsl.w r3, r2, r3 8006818: 69ba ldr r2, [r7, #24] 800681a: 4313 orrs r3, r2 800681c: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800681e: 687b ldr r3, [r7, #4] 8006820: 69ba ldr r2, [r7, #24] 8006822: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8006824: 687b ldr r3, [r7, #4] 8006826: 685b ldr r3, [r3, #4] 8006828: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 800682a: 2201 movs r2, #1 800682c: 69fb ldr r3, [r7, #28] 800682e: fa02 f303 lsl.w r3, r2, r3 8006832: 43db mvns r3, r3 8006834: 69ba ldr r2, [r7, #24] 8006836: 4013 ands r3, r2 8006838: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800683a: 683b ldr r3, [r7, #0] 800683c: 685b ldr r3, [r3, #4] 800683e: 091b lsrs r3, r3, #4 8006840: f003 0201 and.w r2, r3, #1 8006844: 69fb ldr r3, [r7, #28] 8006846: fa02 f303 lsl.w r3, r2, r3 800684a: 69ba ldr r2, [r7, #24] 800684c: 4313 orrs r3, r2 800684e: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8006850: 687b ldr r3, [r7, #4] 8006852: 69ba ldr r2, [r7, #24] 8006854: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8006856: 683b ldr r3, [r7, #0] 8006858: 685b ldr r3, [r3, #4] 800685a: f003 0303 and.w r3, r3, #3 800685e: 2b03 cmp r3, #3 8006860: d017 beq.n 8006892 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8006862: 687b ldr r3, [r7, #4] 8006864: 68db ldr r3, [r3, #12] 8006866: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8006868: 69fb ldr r3, [r7, #28] 800686a: 005b lsls r3, r3, #1 800686c: 2203 movs r2, #3 800686e: fa02 f303 lsl.w r3, r2, r3 8006872: 43db mvns r3, r3 8006874: 69ba ldr r2, [r7, #24] 8006876: 4013 ands r3, r2 8006878: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 800687a: 683b ldr r3, [r7, #0] 800687c: 689a ldr r2, [r3, #8] 800687e: 69fb ldr r3, [r7, #28] 8006880: 005b lsls r3, r3, #1 8006882: fa02 f303 lsl.w r3, r2, r3 8006886: 69ba ldr r2, [r7, #24] 8006888: 4313 orrs r3, r2 800688a: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 800688c: 687b ldr r3, [r7, #4] 800688e: 69ba ldr r2, [r7, #24] 8006890: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8006892: 683b ldr r3, [r7, #0] 8006894: 685b ldr r3, [r3, #4] 8006896: f003 0303 and.w r3, r3, #3 800689a: 2b02 cmp r3, #2 800689c: d123 bne.n 80068e6 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800689e: 69fb ldr r3, [r7, #28] 80068a0: 08da lsrs r2, r3, #3 80068a2: 687b ldr r3, [r7, #4] 80068a4: 3208 adds r2, #8 80068a6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80068aa: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 80068ac: 69fb ldr r3, [r7, #28] 80068ae: f003 0307 and.w r3, r3, #7 80068b2: 009b lsls r3, r3, #2 80068b4: 220f movs r2, #15 80068b6: fa02 f303 lsl.w r3, r2, r3 80068ba: 43db mvns r3, r3 80068bc: 69ba ldr r2, [r7, #24] 80068be: 4013 ands r3, r2 80068c0: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 80068c2: 683b ldr r3, [r7, #0] 80068c4: 691a ldr r2, [r3, #16] 80068c6: 69fb ldr r3, [r7, #28] 80068c8: f003 0307 and.w r3, r3, #7 80068cc: 009b lsls r3, r3, #2 80068ce: fa02 f303 lsl.w r3, r2, r3 80068d2: 69ba ldr r2, [r7, #24] 80068d4: 4313 orrs r3, r2 80068d6: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 80068d8: 69fb ldr r3, [r7, #28] 80068da: 08da lsrs r2, r3, #3 80068dc: 687b ldr r3, [r7, #4] 80068de: 3208 adds r2, #8 80068e0: 69b9 ldr r1, [r7, #24] 80068e2: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 80068e6: 687b ldr r3, [r7, #4] 80068e8: 681b ldr r3, [r3, #0] 80068ea: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 80068ec: 69fb ldr r3, [r7, #28] 80068ee: 005b lsls r3, r3, #1 80068f0: 2203 movs r2, #3 80068f2: fa02 f303 lsl.w r3, r2, r3 80068f6: 43db mvns r3, r3 80068f8: 69ba ldr r2, [r7, #24] 80068fa: 4013 ands r3, r2 80068fc: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 80068fe: 683b ldr r3, [r7, #0] 8006900: 685b ldr r3, [r3, #4] 8006902: f003 0203 and.w r2, r3, #3 8006906: 69fb ldr r3, [r7, #28] 8006908: 005b lsls r3, r3, #1 800690a: fa02 f303 lsl.w r3, r2, r3 800690e: 69ba ldr r2, [r7, #24] 8006910: 4313 orrs r3, r2 8006912: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8006914: 687b ldr r3, [r7, #4] 8006916: 69ba ldr r2, [r7, #24] 8006918: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800691a: 683b ldr r3, [r7, #0] 800691c: 685b ldr r3, [r3, #4] 800691e: f403 3340 and.w r3, r3, #196608 ; 0x30000 8006922: 2b00 cmp r3, #0 8006924: f000 80d8 beq.w 8006ad8 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8006928: 4b2c ldr r3, [pc, #176] ; (80069dc ) 800692a: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 800692e: 4a2b ldr r2, [pc, #172] ; (80069dc ) 8006930: f043 0302 orr.w r3, r3, #2 8006934: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 8006938: 4b28 ldr r3, [pc, #160] ; (80069dc ) 800693a: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 800693e: f003 0302 and.w r3, r3, #2 8006942: 60fb str r3, [r7, #12] 8006944: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8006946: 4a26 ldr r2, [pc, #152] ; (80069e0 ) 8006948: 69fb ldr r3, [r7, #28] 800694a: 089b lsrs r3, r3, #2 800694c: 3302 adds r3, #2 800694e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8006952: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8006954: 69fb ldr r3, [r7, #28] 8006956: f003 0303 and.w r3, r3, #3 800695a: 009b lsls r3, r3, #2 800695c: 220f movs r2, #15 800695e: fa02 f303 lsl.w r3, r2, r3 8006962: 43db mvns r3, r3 8006964: 69ba ldr r2, [r7, #24] 8006966: 4013 ands r3, r2 8006968: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 800696a: 687b ldr r3, [r7, #4] 800696c: 4a1d ldr r2, [pc, #116] ; (80069e4 ) 800696e: 4293 cmp r3, r2 8006970: d04a beq.n 8006a08 8006972: 687b ldr r3, [r7, #4] 8006974: 4a1c ldr r2, [pc, #112] ; (80069e8 ) 8006976: 4293 cmp r3, r2 8006978: d02b beq.n 80069d2 800697a: 687b ldr r3, [r7, #4] 800697c: 4a1b ldr r2, [pc, #108] ; (80069ec ) 800697e: 4293 cmp r3, r2 8006980: d025 beq.n 80069ce 8006982: 687b ldr r3, [r7, #4] 8006984: 4a1a ldr r2, [pc, #104] ; (80069f0 ) 8006986: 4293 cmp r3, r2 8006988: d01f beq.n 80069ca 800698a: 687b ldr r3, [r7, #4] 800698c: 4a19 ldr r2, [pc, #100] ; (80069f4 ) 800698e: 4293 cmp r3, r2 8006990: d019 beq.n 80069c6 8006992: 687b ldr r3, [r7, #4] 8006994: 4a18 ldr r2, [pc, #96] ; (80069f8 ) 8006996: 4293 cmp r3, r2 8006998: d013 beq.n 80069c2 800699a: 687b ldr r3, [r7, #4] 800699c: 4a17 ldr r2, [pc, #92] ; (80069fc ) 800699e: 4293 cmp r3, r2 80069a0: d00d beq.n 80069be 80069a2: 687b ldr r3, [r7, #4] 80069a4: 4a16 ldr r2, [pc, #88] ; (8006a00 ) 80069a6: 4293 cmp r3, r2 80069a8: d007 beq.n 80069ba 80069aa: 687b ldr r3, [r7, #4] 80069ac: 4a15 ldr r2, [pc, #84] ; (8006a04 ) 80069ae: 4293 cmp r3, r2 80069b0: d101 bne.n 80069b6 80069b2: 2309 movs r3, #9 80069b4: e029 b.n 8006a0a 80069b6: 230a movs r3, #10 80069b8: e027 b.n 8006a0a 80069ba: 2307 movs r3, #7 80069bc: e025 b.n 8006a0a 80069be: 2306 movs r3, #6 80069c0: e023 b.n 8006a0a 80069c2: 2305 movs r3, #5 80069c4: e021 b.n 8006a0a 80069c6: 2304 movs r3, #4 80069c8: e01f b.n 8006a0a 80069ca: 2303 movs r3, #3 80069cc: e01d b.n 8006a0a 80069ce: 2302 movs r3, #2 80069d0: e01b b.n 8006a0a 80069d2: 2301 movs r3, #1 80069d4: e019 b.n 8006a0a 80069d6: bf00 nop 80069d8: 58000080 .word 0x58000080 80069dc: 58024400 .word 0x58024400 80069e0: 58000400 .word 0x58000400 80069e4: 58020000 .word 0x58020000 80069e8: 58020400 .word 0x58020400 80069ec: 58020800 .word 0x58020800 80069f0: 58020c00 .word 0x58020c00 80069f4: 58021000 .word 0x58021000 80069f8: 58021400 .word 0x58021400 80069fc: 58021800 .word 0x58021800 8006a00: 58021c00 .word 0x58021c00 8006a04: 58022400 .word 0x58022400 8006a08: 2300 movs r3, #0 8006a0a: 69fa ldr r2, [r7, #28] 8006a0c: f002 0203 and.w r2, r2, #3 8006a10: 0092 lsls r2, r2, #2 8006a12: 4093 lsls r3, r2 8006a14: 69ba ldr r2, [r7, #24] 8006a16: 4313 orrs r3, r2 8006a18: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8006a1a: 4938 ldr r1, [pc, #224] ; (8006afc ) 8006a1c: 69fb ldr r3, [r7, #28] 8006a1e: 089b lsrs r3, r3, #2 8006a20: 3302 adds r3, #2 8006a22: 69ba ldr r2, [r7, #24] 8006a24: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8006a28: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 8006a2c: 681b ldr r3, [r3, #0] 8006a2e: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8006a30: 693b ldr r3, [r7, #16] 8006a32: 43db mvns r3, r3 8006a34: 69ba ldr r2, [r7, #24] 8006a36: 4013 ands r3, r2 8006a38: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8006a3a: 683b ldr r3, [r7, #0] 8006a3c: 685b ldr r3, [r3, #4] 8006a3e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8006a42: 2b00 cmp r3, #0 8006a44: d003 beq.n 8006a4e { temp |= iocurrent; 8006a46: 69ba ldr r2, [r7, #24] 8006a48: 693b ldr r3, [r7, #16] 8006a4a: 4313 orrs r3, r2 8006a4c: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 8006a4e: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 8006a52: 69bb ldr r3, [r7, #24] 8006a54: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 8006a56: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 8006a5a: 685b ldr r3, [r3, #4] 8006a5c: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8006a5e: 693b ldr r3, [r7, #16] 8006a60: 43db mvns r3, r3 8006a62: 69ba ldr r2, [r7, #24] 8006a64: 4013 ands r3, r2 8006a66: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8006a68: 683b ldr r3, [r7, #0] 8006a6a: 685b ldr r3, [r3, #4] 8006a6c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8006a70: 2b00 cmp r3, #0 8006a72: d003 beq.n 8006a7c { temp |= iocurrent; 8006a74: 69ba ldr r2, [r7, #24] 8006a76: 693b ldr r3, [r7, #16] 8006a78: 4313 orrs r3, r2 8006a7a: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 8006a7c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 8006a80: 69bb ldr r3, [r7, #24] 8006a82: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 8006a84: 697b ldr r3, [r7, #20] 8006a86: 685b ldr r3, [r3, #4] 8006a88: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8006a8a: 693b ldr r3, [r7, #16] 8006a8c: 43db mvns r3, r3 8006a8e: 69ba ldr r2, [r7, #24] 8006a90: 4013 ands r3, r2 8006a92: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8006a94: 683b ldr r3, [r7, #0] 8006a96: 685b ldr r3, [r3, #4] 8006a98: f403 3300 and.w r3, r3, #131072 ; 0x20000 8006a9c: 2b00 cmp r3, #0 8006a9e: d003 beq.n 8006aa8 { temp |= iocurrent; 8006aa0: 69ba ldr r2, [r7, #24] 8006aa2: 693b ldr r3, [r7, #16] 8006aa4: 4313 orrs r3, r2 8006aa6: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 8006aa8: 697b ldr r3, [r7, #20] 8006aaa: 69ba ldr r2, [r7, #24] 8006aac: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 8006aae: 697b ldr r3, [r7, #20] 8006ab0: 681b ldr r3, [r3, #0] 8006ab2: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8006ab4: 693b ldr r3, [r7, #16] 8006ab6: 43db mvns r3, r3 8006ab8: 69ba ldr r2, [r7, #24] 8006aba: 4013 ands r3, r2 8006abc: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8006abe: 683b ldr r3, [r7, #0] 8006ac0: 685b ldr r3, [r3, #4] 8006ac2: f403 3380 and.w r3, r3, #65536 ; 0x10000 8006ac6: 2b00 cmp r3, #0 8006ac8: d003 beq.n 8006ad2 { temp |= iocurrent; 8006aca: 69ba ldr r2, [r7, #24] 8006acc: 693b ldr r3, [r7, #16] 8006ace: 4313 orrs r3, r2 8006ad0: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 8006ad2: 697b ldr r3, [r7, #20] 8006ad4: 69ba ldr r2, [r7, #24] 8006ad6: 601a str r2, [r3, #0] } } position++; 8006ad8: 69fb ldr r3, [r7, #28] 8006ada: 3301 adds r3, #1 8006adc: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 8006ade: 683b ldr r3, [r7, #0] 8006ae0: 681a ldr r2, [r3, #0] 8006ae2: 69fb ldr r3, [r7, #28] 8006ae4: fa22 f303 lsr.w r3, r2, r3 8006ae8: 2b00 cmp r3, #0 8006aea: f47f ae6b bne.w 80067c4 } } 8006aee: bf00 nop 8006af0: bf00 nop 8006af2: 3724 adds r7, #36 ; 0x24 8006af4: 46bd mov sp, r7 8006af6: f85d 7b04 ldr.w r7, [sp], #4 8006afa: 4770 bx lr 8006afc: 58000400 .word 0x58000400 08006b00 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8006b00: b480 push {r7} 8006b02: b085 sub sp, #20 8006b04: af00 add r7, sp, #0 8006b06: 6078 str r0, [r7, #4] 8006b08: 460b mov r3, r1 8006b0a: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 8006b0c: 687b ldr r3, [r7, #4] 8006b0e: 691a ldr r2, [r3, #16] 8006b10: 887b ldrh r3, [r7, #2] 8006b12: 4013 ands r3, r2 8006b14: 2b00 cmp r3, #0 8006b16: d002 beq.n 8006b1e { bitstatus = GPIO_PIN_SET; 8006b18: 2301 movs r3, #1 8006b1a: 73fb strb r3, [r7, #15] 8006b1c: e001 b.n 8006b22 } else { bitstatus = GPIO_PIN_RESET; 8006b1e: 2300 movs r3, #0 8006b20: 73fb strb r3, [r7, #15] } return bitstatus; 8006b22: 7bfb ldrb r3, [r7, #15] } 8006b24: 4618 mov r0, r3 8006b26: 3714 adds r7, #20 8006b28: 46bd mov sp, r7 8006b2a: f85d 7b04 ldr.w r7, [sp], #4 8006b2e: 4770 bx lr 08006b30 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8006b30: b480 push {r7} 8006b32: b083 sub sp, #12 8006b34: af00 add r7, sp, #0 8006b36: 6078 str r0, [r7, #4] 8006b38: 460b mov r3, r1 8006b3a: 807b strh r3, [r7, #2] 8006b3c: 4613 mov r3, r2 8006b3e: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8006b40: 787b ldrb r3, [r7, #1] 8006b42: 2b00 cmp r3, #0 8006b44: d003 beq.n 8006b4e { GPIOx->BSRR = GPIO_Pin; 8006b46: 887a ldrh r2, [r7, #2] 8006b48: 687b ldr r3, [r7, #4] 8006b4a: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 8006b4c: e003 b.n 8006b56 GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 8006b4e: 887b ldrh r3, [r7, #2] 8006b50: 041a lsls r2, r3, #16 8006b52: 687b ldr r3, [r7, #4] 8006b54: 619a str r2, [r3, #24] } 8006b56: bf00 nop 8006b58: 370c adds r7, #12 8006b5a: 46bd mov sp, r7 8006b5c: f85d 7b04 ldr.w r7, [sp], #4 8006b60: 4770 bx lr 08006b62 : * @param hmdma: Pointer to a MDMA_HandleTypeDef structure that contains * the configuration information for the specified MDMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma) { 8006b62: b580 push {r7, lr} 8006b64: b084 sub sp, #16 8006b66: af00 add r7, sp, #0 8006b68: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8006b6a: f7fb fbfb bl 8002364 8006b6e: 60f8 str r0, [r7, #12] /* Check the MDMA peripheral handle */ if(hmdma == NULL) 8006b70: 687b ldr r3, [r7, #4] 8006b72: 2b00 cmp r3, #0 8006b74: d101 bne.n 8006b7a { return HAL_ERROR; 8006b76: 2301 movs r3, #1 8006b78: e03b b.n 8006bf2 assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset)); assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset)); /* Allocate lock resource */ __HAL_UNLOCK(hmdma); 8006b7a: 687b ldr r3, [r7, #4] 8006b7c: 2200 movs r2, #0 8006b7e: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change MDMA peripheral state */ hmdma->State = HAL_MDMA_STATE_BUSY; 8006b82: 687b ldr r3, [r7, #4] 8006b84: 2202 movs r2, #2 8006b86: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the MDMA channel */ __HAL_MDMA_DISABLE(hmdma); 8006b8a: 687b ldr r3, [r7, #4] 8006b8c: 681b ldr r3, [r3, #0] 8006b8e: 68da ldr r2, [r3, #12] 8006b90: 687b ldr r3, [r7, #4] 8006b92: 681b ldr r3, [r3, #0] 8006b94: f022 0201 bic.w r2, r2, #1 8006b98: 60da str r2, [r3, #12] /* Check if the MDMA channel is effectively disabled */ while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) 8006b9a: e00f b.n 8006bbc { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT) 8006b9c: f7fb fbe2 bl 8002364 8006ba0: 4602 mov r2, r0 8006ba2: 68fb ldr r3, [r7, #12] 8006ba4: 1ad3 subs r3, r2, r3 8006ba6: 2b05 cmp r3, #5 8006ba8: d908 bls.n 8006bbc { /* Update error code */ hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT; 8006baa: 687b ldr r3, [r7, #4] 8006bac: 2240 movs r2, #64 ; 0x40 8006bae: 669a str r2, [r3, #104] ; 0x68 /* Change the MDMA state */ hmdma->State = HAL_MDMA_STATE_ERROR; 8006bb0: 687b ldr r3, [r7, #4] 8006bb2: 2203 movs r2, #3 8006bb4: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_ERROR; 8006bb8: 2301 movs r3, #1 8006bba: e01a b.n 8006bf2 while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) 8006bbc: 687b ldr r3, [r7, #4] 8006bbe: 681b ldr r3, [r3, #0] 8006bc0: 68db ldr r3, [r3, #12] 8006bc2: f003 0301 and.w r3, r3, #1 8006bc6: 2b00 cmp r3, #0 8006bc8: d1e8 bne.n 8006b9c } } /* Initialize the MDMA channel registers */ MDMA_Init(hmdma); 8006bca: 6878 ldr r0, [r7, #4] 8006bcc: f000 f9bc bl 8006f48 /* Reset the MDMA first/last linkedlist node addresses and node counter */ hmdma->FirstLinkedListNodeAddress = 0; 8006bd0: 687b ldr r3, [r7, #4] 8006bd2: 2200 movs r2, #0 8006bd4: 65da str r2, [r3, #92] ; 0x5c hmdma->LastLinkedListNodeAddress = 0; 8006bd6: 687b ldr r3, [r7, #4] 8006bd8: 2200 movs r2, #0 8006bda: 661a str r2, [r3, #96] ; 0x60 hmdma->LinkedListNodeCounter = 0; 8006bdc: 687b ldr r3, [r7, #4] 8006bde: 2200 movs r2, #0 8006be0: 665a str r2, [r3, #100] ; 0x64 /* Initialize the error code */ hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; 8006be2: 687b ldr r3, [r7, #4] 8006be4: 2200 movs r2, #0 8006be6: 669a str r2, [r3, #104] ; 0x68 /* Initialize the MDMA state */ hmdma->State = HAL_MDMA_STATE_READY; 8006be8: 687b ldr r3, [r7, #4] 8006bea: 2201 movs r2, #1 8006bec: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8006bf0: 2300 movs r3, #0 } 8006bf2: 4618 mov r0, r3 8006bf4: 3710 adds r7, #16 8006bf6: 46bd mov sp, r7 8006bf8: bd80 pop {r7, pc} 08006bfa : * @param MaskData: specifies the value to be written to MaskAddress after a request is served. * MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served. * @retval HAL status */ HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData) { 8006bfa: b480 push {r7} 8006bfc: b087 sub sp, #28 8006bfe: af00 add r7, sp, #0 8006c00: 60f8 str r0, [r7, #12] 8006c02: 60b9 str r1, [r7, #8] 8006c04: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8006c06: 2300 movs r3, #0 8006c08: 75fb strb r3, [r7, #23] /* Check the MDMA peripheral handle */ if(hmdma == NULL) 8006c0a: 68fb ldr r3, [r7, #12] 8006c0c: 2b00 cmp r3, #0 8006c0e: d101 bne.n 8006c14 { return HAL_ERROR; 8006c10: 2301 movs r3, #1 8006c12: e03e b.n 8006c92 } /* Process locked */ __HAL_LOCK(hmdma); 8006c14: 68fb ldr r3, [r7, #12] 8006c16: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8006c1a: 2b01 cmp r3, #1 8006c1c: d101 bne.n 8006c22 8006c1e: 2302 movs r3, #2 8006c20: e037 b.n 8006c92 8006c22: 68fb ldr r3, [r7, #12] 8006c24: 2201 movs r2, #1 8006c26: f883 203c strb.w r2, [r3, #60] ; 0x3c if(HAL_MDMA_STATE_READY == hmdma->State) 8006c2a: 68fb ldr r3, [r7, #12] 8006c2c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8006c30: b2db uxtb r3, r3 8006c32: 2b01 cmp r3, #1 8006c34: d126 bne.n 8006c84 { /* if HW request set Post Request MaskAddress and MaskData, */ if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U) 8006c36: 68fb ldr r3, [r7, #12] 8006c38: 681b ldr r3, [r3, #0] 8006c3a: 691b ldr r3, [r3, #16] 8006c3c: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8006c40: 2b00 cmp r3, #0 8006c42: d11c bne.n 8006c7e { /* Set the HW request clear Mask and Data */ hmdma->Instance->CMAR = MaskAddress; 8006c44: 68fb ldr r3, [r7, #12] 8006c46: 681b ldr r3, [r3, #0] 8006c48: 68ba ldr r2, [r7, #8] 8006c4a: 631a str r2, [r3, #48] ; 0x30 hmdma->Instance->CMDR = MaskData; 8006c4c: 68fb ldr r3, [r7, #12] 8006c4e: 681b ldr r3, [r3, #0] 8006c50: 687a ldr r2, [r7, #4] 8006c52: 635a str r2, [r3, #52] ; 0x34 -If the request is done by SW : BWM could be set to 1 or 0. -If the request is done by a peripheral : If mask address not set (0) => BWM must be set to 0 If mask address set (different than 0) => BWM could be set to 1 or 0 */ if(MaskAddress == 0U) 8006c54: 68bb ldr r3, [r7, #8] 8006c56: 2b00 cmp r3, #0 8006c58: d108 bne.n 8006c6c { hmdma->Instance->CTCR &= ~MDMA_CTCR_BWM; 8006c5a: 68fb ldr r3, [r7, #12] 8006c5c: 681b ldr r3, [r3, #0] 8006c5e: 691a ldr r2, [r3, #16] 8006c60: 68fb ldr r3, [r7, #12] 8006c62: 681b ldr r3, [r3, #0] 8006c64: f022 4200 bic.w r2, r2, #2147483648 ; 0x80000000 8006c68: 611a str r2, [r3, #16] 8006c6a: e00d b.n 8006c88 } else { hmdma->Instance->CTCR |= MDMA_CTCR_BWM; 8006c6c: 68fb ldr r3, [r7, #12] 8006c6e: 681b ldr r3, [r3, #0] 8006c70: 691a ldr r2, [r3, #16] 8006c72: 68fb ldr r3, [r7, #12] 8006c74: 681b ldr r3, [r3, #0] 8006c76: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000 8006c7a: 611a str r2, [r3, #16] 8006c7c: e004 b.n 8006c88 } } else { /* Return error status */ status = HAL_ERROR; 8006c7e: 2301 movs r3, #1 8006c80: 75fb strb r3, [r7, #23] 8006c82: e001 b.n 8006c88 } } else { /* Return error status */ status = HAL_ERROR; 8006c84: 2301 movs r3, #1 8006c86: 75fb strb r3, [r7, #23] } /* Release Lock */ __HAL_UNLOCK(hmdma); 8006c88: 68fb ldr r3, [r7, #12] 8006c8a: 2200 movs r2, #0 8006c8c: f883 203c strb.w r2, [r3, #60] ; 0x3c return status; 8006c90: 7dfb ldrb r3, [r7, #23] } 8006c92: 4618 mov r0, r3 8006c94: 371c adds r7, #28 8006c96: 46bd mov sp, r7 8006c98: f85d 7b04 ldr.w r7, [sp], #4 8006c9c: 4770 bx lr ... 08006ca0 : * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains * the configuration information for the specified MDMA Channel. * @retval None */ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) { 8006ca0: b580 push {r7, lr} 8006ca2: b086 sub sp, #24 8006ca4: af00 add r7, sp, #0 8006ca6: 6078 str r0, [r7, #4] __IO uint32_t count = 0; 8006ca8: 2300 movs r3, #0 8006caa: 60bb str r3, [r7, #8] uint32_t timeout = SystemCoreClock / 9600U; 8006cac: 4b91 ldr r3, [pc, #580] ; (8006ef4 ) 8006cae: 681b ldr r3, [r3, #0] 8006cb0: 4a91 ldr r2, [pc, #580] ; (8006ef8 ) 8006cb2: fba2 2303 umull r2, r3, r2, r3 8006cb6: 0a9b lsrs r3, r3, #10 8006cb8: 617b str r3, [r7, #20] uint32_t generalIntFlag, errorFlag; /* General Interrupt Flag management ****************************************/ generalIntFlag = 1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU); 8006cba: 687b ldr r3, [r7, #4] 8006cbc: 681b ldr r3, [r3, #0] 8006cbe: 461a mov r2, r3 8006cc0: 4b8e ldr r3, [pc, #568] ; (8006efc ) 8006cc2: 4413 add r3, r2 8006cc4: 099b lsrs r3, r3, #6 8006cc6: f003 031f and.w r3, r3, #31 8006cca: 2201 movs r2, #1 8006ccc: fa02 f303 lsl.w r3, r2, r3 8006cd0: 613b str r3, [r7, #16] if((MDMA->GISR0 & generalIntFlag) == 0U) 8006cd2: f04f 43a4 mov.w r3, #1375731712 ; 0x52000000 8006cd6: 681a ldr r2, [r3, #0] 8006cd8: 693b ldr r3, [r7, #16] 8006cda: 4013 ands r3, r2 8006cdc: 2b00 cmp r3, #0 8006cde: f000 812d beq.w 8006f3c { return; /* the General interrupt flag for the current channel is down , nothing to do */ } /* Transfer Error Interrupt management ***************************************/ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) 8006ce2: 687b ldr r3, [r7, #4] 8006ce4: 681b ldr r3, [r3, #0] 8006ce6: 681b ldr r3, [r3, #0] 8006ce8: f003 0301 and.w r3, r3, #1 8006cec: 2b00 cmp r3, #0 8006cee: d054 beq.n 8006d9a { if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U) 8006cf0: 687b ldr r3, [r7, #4] 8006cf2: 681b ldr r3, [r3, #0] 8006cf4: 68db ldr r3, [r3, #12] 8006cf6: f003 0302 and.w r3, r3, #2 8006cfa: 2b00 cmp r3, #0 8006cfc: d04d beq.n 8006d9a { /* Disable the transfer error interrupt */ __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE); 8006cfe: 687b ldr r3, [r7, #4] 8006d00: 681b ldr r3, [r3, #0] 8006d02: 68da ldr r2, [r3, #12] 8006d04: 687b ldr r3, [r7, #4] 8006d06: 681b ldr r3, [r3, #0] 8006d08: f022 0202 bic.w r2, r2, #2 8006d0c: 60da str r2, [r3, #12] /* Get the transfer error source flag */ errorFlag = hmdma->Instance->CESR; 8006d0e: 687b ldr r3, [r7, #4] 8006d10: 681b ldr r3, [r3, #0] 8006d12: 689b ldr r3, [r3, #8] 8006d14: 60fb str r3, [r7, #12] if((errorFlag & MDMA_CESR_TED) == 0U) 8006d16: 68fb ldr r3, [r7, #12] 8006d18: f003 0380 and.w r3, r3, #128 ; 0x80 8006d1c: 2b00 cmp r3, #0 8006d1e: d106 bne.n 8006d2e { /* Update error code : Read Transfer error */ hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER; 8006d20: 687b ldr r3, [r7, #4] 8006d22: 6e9b ldr r3, [r3, #104] ; 0x68 8006d24: f043 0201 orr.w r2, r3, #1 8006d28: 687b ldr r3, [r7, #4] 8006d2a: 669a str r2, [r3, #104] ; 0x68 8006d2c: e005 b.n 8006d3a } else { /* Update error code : Write Transfer error */ hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; 8006d2e: 687b ldr r3, [r7, #4] 8006d30: 6e9b ldr r3, [r3, #104] ; 0x68 8006d32: f043 0202 orr.w r2, r3, #2 8006d36: 687b ldr r3, [r7, #4] 8006d38: 669a str r2, [r3, #104] ; 0x68 } if((errorFlag & MDMA_CESR_TEMD) != 0U) 8006d3a: 68fb ldr r3, [r7, #12] 8006d3c: f403 7300 and.w r3, r3, #512 ; 0x200 8006d40: 2b00 cmp r3, #0 8006d42: d005 beq.n 8006d50 { /* Update error code : Error Mask Data */ hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; 8006d44: 687b ldr r3, [r7, #4] 8006d46: 6e9b ldr r3, [r3, #104] ; 0x68 8006d48: f043 0204 orr.w r2, r3, #4 8006d4c: 687b ldr r3, [r7, #4] 8006d4e: 669a str r2, [r3, #104] ; 0x68 } if((errorFlag & MDMA_CESR_TELD) != 0U) 8006d50: 68fb ldr r3, [r7, #12] 8006d52: f403 7380 and.w r3, r3, #256 ; 0x100 8006d56: 2b00 cmp r3, #0 8006d58: d005 beq.n 8006d66 { /* Update error code : Error Linked list */ hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; 8006d5a: 687b ldr r3, [r7, #4] 8006d5c: 6e9b ldr r3, [r3, #104] ; 0x68 8006d5e: f043 0208 orr.w r2, r3, #8 8006d62: 687b ldr r3, [r7, #4] 8006d64: 669a str r2, [r3, #104] ; 0x68 } if((errorFlag & MDMA_CESR_ASE) != 0U) 8006d66: 68fb ldr r3, [r7, #12] 8006d68: f403 6380 and.w r3, r3, #1024 ; 0x400 8006d6c: 2b00 cmp r3, #0 8006d6e: d005 beq.n 8006d7c { /* Update error code : Address/Size alignment error */ hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; 8006d70: 687b ldr r3, [r7, #4] 8006d72: 6e9b ldr r3, [r3, #104] ; 0x68 8006d74: f043 0210 orr.w r2, r3, #16 8006d78: 687b ldr r3, [r7, #4] 8006d7a: 669a str r2, [r3, #104] ; 0x68 } if((errorFlag & MDMA_CESR_BSE) != 0U) 8006d7c: 68fb ldr r3, [r7, #12] 8006d7e: f403 6300 and.w r3, r3, #2048 ; 0x800 8006d82: 2b00 cmp r3, #0 8006d84: d005 beq.n 8006d92 { /* Update error code : Block Size error error */ hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; 8006d86: 687b ldr r3, [r7, #4] 8006d88: 6e9b ldr r3, [r3, #104] ; 0x68 8006d8a: f043 0220 orr.w r2, r3, #32 8006d8e: 687b ldr r3, [r7, #4] 8006d90: 669a str r2, [r3, #104] ; 0x68 } /* Clear the transfer error flags */ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE); 8006d92: 687b ldr r3, [r7, #4] 8006d94: 681b ldr r3, [r3, #0] 8006d96: 2201 movs r2, #1 8006d98: 605a str r2, [r3, #4] } } /* Buffer Transfer Complete Interrupt management ******************************/ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U)) 8006d9a: 687b ldr r3, [r7, #4] 8006d9c: 681b ldr r3, [r3, #0] 8006d9e: 681b ldr r3, [r3, #0] 8006da0: f003 0310 and.w r3, r3, #16 8006da4: 2b00 cmp r3, #0 8006da6: d012 beq.n 8006dce { if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U) 8006da8: 687b ldr r3, [r7, #4] 8006daa: 681b ldr r3, [r3, #0] 8006dac: 68db ldr r3, [r3, #12] 8006dae: f003 0320 and.w r3, r3, #32 8006db2: 2b00 cmp r3, #0 8006db4: d00b beq.n 8006dce { /* Clear the buffer transfer complete flag */ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); 8006db6: 687b ldr r3, [r7, #4] 8006db8: 681b ldr r3, [r3, #0] 8006dba: 2210 movs r2, #16 8006dbc: 605a str r2, [r3, #4] if(hmdma->XferBufferCpltCallback != NULL) 8006dbe: 687b ldr r3, [r7, #4] 8006dc0: 6c9b ldr r3, [r3, #72] ; 0x48 8006dc2: 2b00 cmp r3, #0 8006dc4: d003 beq.n 8006dce { /* Buffer transfer callback */ hmdma->XferBufferCpltCallback(hmdma); 8006dc6: 687b ldr r3, [r7, #4] 8006dc8: 6c9b ldr r3, [r3, #72] ; 0x48 8006dca: 6878 ldr r0, [r7, #4] 8006dcc: 4798 blx r3 } } } /* Block Transfer Complete Interrupt management ******************************/ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U)) 8006dce: 687b ldr r3, [r7, #4] 8006dd0: 681b ldr r3, [r3, #0] 8006dd2: 681b ldr r3, [r3, #0] 8006dd4: f003 0308 and.w r3, r3, #8 8006dd8: 2b00 cmp r3, #0 8006dda: d012 beq.n 8006e02 { if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U) 8006ddc: 687b ldr r3, [r7, #4] 8006dde: 681b ldr r3, [r3, #0] 8006de0: 68db ldr r3, [r3, #12] 8006de2: f003 0310 and.w r3, r3, #16 8006de6: 2b00 cmp r3, #0 8006de8: d00b beq.n 8006e02 { /* Clear the block transfer complete flag */ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT); 8006dea: 687b ldr r3, [r7, #4] 8006dec: 681b ldr r3, [r3, #0] 8006dee: 2208 movs r2, #8 8006df0: 605a str r2, [r3, #4] if(hmdma->XferBlockCpltCallback != NULL) 8006df2: 687b ldr r3, [r7, #4] 8006df4: 6cdb ldr r3, [r3, #76] ; 0x4c 8006df6: 2b00 cmp r3, #0 8006df8: d003 beq.n 8006e02 { /* Block transfer callback */ hmdma->XferBlockCpltCallback(hmdma); 8006dfa: 687b ldr r3, [r7, #4] 8006dfc: 6cdb ldr r3, [r3, #76] ; 0x4c 8006dfe: 6878 ldr r0, [r7, #4] 8006e00: 4798 blx r3 } } } /* Repeated Block Transfer Complete Interrupt management ******************************/ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U)) 8006e02: 687b ldr r3, [r7, #4] 8006e04: 681b ldr r3, [r3, #0] 8006e06: 681b ldr r3, [r3, #0] 8006e08: f003 0304 and.w r3, r3, #4 8006e0c: 2b00 cmp r3, #0 8006e0e: d012 beq.n 8006e36 { if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U) 8006e10: 687b ldr r3, [r7, #4] 8006e12: 681b ldr r3, [r3, #0] 8006e14: 68db ldr r3, [r3, #12] 8006e16: f003 0308 and.w r3, r3, #8 8006e1a: 2b00 cmp r3, #0 8006e1c: d00b beq.n 8006e36 { /* Clear the repeat block transfer complete flag */ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT); 8006e1e: 687b ldr r3, [r7, #4] 8006e20: 681b ldr r3, [r3, #0] 8006e22: 2204 movs r2, #4 8006e24: 605a str r2, [r3, #4] if(hmdma->XferRepeatBlockCpltCallback != NULL) 8006e26: 687b ldr r3, [r7, #4] 8006e28: 6d1b ldr r3, [r3, #80] ; 0x50 8006e2a: 2b00 cmp r3, #0 8006e2c: d003 beq.n 8006e36 { /* Repeated Block transfer callback */ hmdma->XferRepeatBlockCpltCallback(hmdma); 8006e2e: 687b ldr r3, [r7, #4] 8006e30: 6d1b ldr r3, [r3, #80] ; 0x50 8006e32: 6878 ldr r0, [r7, #4] 8006e34: 4798 blx r3 } } } /* Channel Transfer Complete Interrupt management ***********************************/ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U)) 8006e36: 687b ldr r3, [r7, #4] 8006e38: 681b ldr r3, [r3, #0] 8006e3a: 681b ldr r3, [r3, #0] 8006e3c: f003 0302 and.w r3, r3, #2 8006e40: 2b00 cmp r3, #0 8006e42: d039 beq.n 8006eb8 { if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U) 8006e44: 687b ldr r3, [r7, #4] 8006e46: 681b ldr r3, [r3, #0] 8006e48: 68db ldr r3, [r3, #12] 8006e4a: f003 0304 and.w r3, r3, #4 8006e4e: 2b00 cmp r3, #0 8006e50: d032 beq.n 8006eb8 { /* Disable all the transfer interrupts */ __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC)); 8006e52: 687b ldr r3, [r7, #4] 8006e54: 681b ldr r3, [r3, #0] 8006e56: 68da ldr r2, [r3, #12] 8006e58: 687b ldr r3, [r7, #4] 8006e5a: 681b ldr r3, [r3, #0] 8006e5c: f022 023e bic.w r2, r2, #62 ; 0x3e 8006e60: 60da str r2, [r3, #12] if(HAL_MDMA_STATE_ABORT == hmdma->State) 8006e62: 687b ldr r3, [r7, #4] 8006e64: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8006e68: b2db uxtb r3, r3 8006e6a: 2b04 cmp r3, #4 8006e6c: d110 bne.n 8006e90 { /* Process Unlocked */ __HAL_UNLOCK(hmdma); 8006e6e: 687b ldr r3, [r7, #4] 8006e70: 2200 movs r2, #0 8006e72: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the DMA state */ hmdma->State = HAL_MDMA_STATE_READY; 8006e76: 687b ldr r3, [r7, #4] 8006e78: 2201 movs r2, #1 8006e7a: f883 203d strb.w r2, [r3, #61] ; 0x3d if(hmdma->XferAbortCallback != NULL) 8006e7e: 687b ldr r3, [r7, #4] 8006e80: 6d9b ldr r3, [r3, #88] ; 0x58 8006e82: 2b00 cmp r3, #0 8006e84: d05c beq.n 8006f40 { hmdma->XferAbortCallback(hmdma); 8006e86: 687b ldr r3, [r7, #4] 8006e88: 6d9b ldr r3, [r3, #88] ; 0x58 8006e8a: 6878 ldr r0, [r7, #4] 8006e8c: 4798 blx r3 } return; 8006e8e: e057 b.n 8006f40 } /* Clear the Channel Transfer Complete flag */ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC); 8006e90: 687b ldr r3, [r7, #4] 8006e92: 681b ldr r3, [r3, #0] 8006e94: 2202 movs r2, #2 8006e96: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hmdma); 8006e98: 687b ldr r3, [r7, #4] 8006e9a: 2200 movs r2, #0 8006e9c: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change MDMA peripheral state */ hmdma->State = HAL_MDMA_STATE_READY; 8006ea0: 687b ldr r3, [r7, #4] 8006ea2: 2201 movs r2, #1 8006ea4: f883 203d strb.w r2, [r3, #61] ; 0x3d if(hmdma->XferCpltCallback != NULL) 8006ea8: 687b ldr r3, [r7, #4] 8006eaa: 6c5b ldr r3, [r3, #68] ; 0x44 8006eac: 2b00 cmp r3, #0 8006eae: d003 beq.n 8006eb8 { /* Channel Transfer Complete callback */ hmdma->XferCpltCallback(hmdma); 8006eb0: 687b ldr r3, [r7, #4] 8006eb2: 6c5b ldr r3, [r3, #68] ; 0x44 8006eb4: 6878 ldr r0, [r7, #4] 8006eb6: 4798 blx r3 } } } /* manage error case */ if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE) 8006eb8: 687b ldr r3, [r7, #4] 8006eba: 6e9b ldr r3, [r3, #104] ; 0x68 8006ebc: 2b00 cmp r3, #0 8006ebe: d040 beq.n 8006f42 { hmdma->State = HAL_MDMA_STATE_ABORT; 8006ec0: 687b ldr r3, [r7, #4] 8006ec2: 2204 movs r2, #4 8006ec4: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the channel */ __HAL_MDMA_DISABLE(hmdma); 8006ec8: 687b ldr r3, [r7, #4] 8006eca: 681b ldr r3, [r3, #0] 8006ecc: 68da ldr r2, [r3, #12] 8006ece: 687b ldr r3, [r7, #4] 8006ed0: 681b ldr r3, [r3, #0] 8006ed2: f022 0201 bic.w r2, r2, #1 8006ed6: 60da str r2, [r3, #12] do { if (++count > timeout) 8006ed8: 68bb ldr r3, [r7, #8] 8006eda: 3301 adds r3, #1 8006edc: 60bb str r3, [r7, #8] 8006ede: 697a ldr r2, [r7, #20] 8006ee0: 429a cmp r2, r3 8006ee2: d30d bcc.n 8006f00 { break; } } while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U); 8006ee4: 687b ldr r3, [r7, #4] 8006ee6: 681b ldr r3, [r3, #0] 8006ee8: 68db ldr r3, [r3, #12] 8006eea: f003 0301 and.w r3, r3, #1 8006eee: 2b00 cmp r3, #0 8006ef0: d1f2 bne.n 8006ed8 8006ef2: e006 b.n 8006f02 8006ef4: 24000014 .word 0x24000014 8006ef8: 1b4e81b5 .word 0x1b4e81b5 8006efc: adffffc0 .word 0xadffffc0 break; 8006f00: bf00 nop /* Process Unlocked */ __HAL_UNLOCK(hmdma); 8006f02: 687b ldr r3, [r7, #4] 8006f04: 2200 movs r2, #0 8006f06: f883 203c strb.w r2, [r3, #60] ; 0x3c if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) 8006f0a: 687b ldr r3, [r7, #4] 8006f0c: 681b ldr r3, [r3, #0] 8006f0e: 68db ldr r3, [r3, #12] 8006f10: f003 0301 and.w r3, r3, #1 8006f14: 2b00 cmp r3, #0 8006f16: d004 beq.n 8006f22 { /* Change the MDMA state to error if MDMA disable fails */ hmdma->State = HAL_MDMA_STATE_ERROR; 8006f18: 687b ldr r3, [r7, #4] 8006f1a: 2203 movs r2, #3 8006f1c: f883 203d strb.w r2, [r3, #61] ; 0x3d 8006f20: e003 b.n 8006f2a } else { /* Change the MDMA state to Ready if MDMA disable success */ hmdma->State = HAL_MDMA_STATE_READY; 8006f22: 687b ldr r3, [r7, #4] 8006f24: 2201 movs r2, #1 8006f26: f883 203d strb.w r2, [r3, #61] ; 0x3d } if (hmdma->XferErrorCallback != NULL) 8006f2a: 687b ldr r3, [r7, #4] 8006f2c: 6d5b ldr r3, [r3, #84] ; 0x54 8006f2e: 2b00 cmp r3, #0 8006f30: d007 beq.n 8006f42 { /* Transfer error callback */ hmdma->XferErrorCallback(hmdma); 8006f32: 687b ldr r3, [r7, #4] 8006f34: 6d5b ldr r3, [r3, #84] ; 0x54 8006f36: 6878 ldr r0, [r7, #4] 8006f38: 4798 blx r3 8006f3a: e002 b.n 8006f42 return; /* the General interrupt flag for the current channel is down , nothing to do */ 8006f3c: bf00 nop 8006f3e: e000 b.n 8006f42 return; 8006f40: bf00 nop } } } 8006f42: 3718 adds r7, #24 8006f44: 46bd mov sp, r7 8006f46: bd80 pop {r7, pc} 08006f48 : * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains * the configuration information for the specified MDMA Channel. * @retval None */ static void MDMA_Init(MDMA_HandleTypeDef *hmdma) { 8006f48: b480 push {r7} 8006f4a: b085 sub sp, #20 8006f4c: af00 add r7, sp, #0 8006f4e: 6078 str r0, [r7, #4] uint32_t blockoffset; /* Prepare the MDMA Channel configuration */ hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.Endianness; 8006f50: 687b ldr r3, [r7, #4] 8006f52: 68d9 ldr r1, [r3, #12] 8006f54: 687b ldr r3, [r7, #4] 8006f56: 691a ldr r2, [r3, #16] 8006f58: 687b ldr r3, [r7, #4] 8006f5a: 681b ldr r3, [r3, #0] 8006f5c: 430a orrs r2, r1 8006f5e: 60da str r2, [r3, #12] /* Write new CTCR Register value */ hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \ 8006f60: 687b ldr r3, [r7, #4] 8006f62: 695a ldr r2, [r3, #20] 8006f64: 687b ldr r3, [r7, #4] 8006f66: 699b ldr r3, [r3, #24] 8006f68: 431a orrs r2, r3 hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ 8006f6a: 687b ldr r3, [r7, #4] 8006f6c: 69db ldr r3, [r3, #28] hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \ 8006f6e: 431a orrs r2, r3 hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ 8006f70: 687b ldr r3, [r7, #4] 8006f72: 6a1b ldr r3, [r3, #32] 8006f74: 431a orrs r2, r3 hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \ 8006f76: 687b ldr r3, [r7, #4] 8006f78: 6a5b ldr r3, [r3, #36] ; 0x24 hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ 8006f7a: 431a orrs r2, r3 hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \ 8006f7c: 687b ldr r3, [r7, #4] 8006f7e: 6adb ldr r3, [r3, #44] ; 0x2c 8006f80: 431a orrs r2, r3 hmdma->Init.DestBurst | \ 8006f82: 687b ldr r3, [r7, #4] 8006f84: 6b1b ldr r3, [r3, #48] ; 0x30 hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \ 8006f86: 431a orrs r2, r3 ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ 8006f88: 687b ldr r3, [r7, #4] 8006f8a: 6a9b ldr r3, [r3, #40] ; 0x28 8006f8c: 3b01 subs r3, #1 8006f8e: 049b lsls r3, r3, #18 hmdma->Init.DestBurst | \ 8006f90: ea42 0103 orr.w r1, r2, r3 hmdma->Init.TransferTriggerMode; 8006f94: 687b ldr r3, [r7, #4] 8006f96: 689a ldr r2, [r3, #8] hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \ 8006f98: 687b ldr r3, [r7, #4] 8006f9a: 681b ldr r3, [r3, #0] ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ 8006f9c: 430a orrs r2, r1 hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \ 8006f9e: 611a str r2, [r3, #16] /* If SW request set the CTCR register to SW Request Mode */ if(hmdma->Init.Request == MDMA_REQUEST_SW) 8006fa0: 687b ldr r3, [r7, #4] 8006fa2: 685b ldr r3, [r3, #4] 8006fa4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8006fa8: d107 bne.n 8006fba -If the request is done by SW : BWM could be set to 1 or 0. -If the request is done by a peripheral : If mask address not set (0) => BWM must be set to 0 If mask address set (different than 0) => BWM could be set to 1 or 0 */ hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM); 8006faa: 687b ldr r3, [r7, #4] 8006fac: 681b ldr r3, [r3, #0] 8006fae: 691a ldr r2, [r3, #16] 8006fb0: 687b ldr r3, [r7, #4] 8006fb2: 681b ldr r3, [r3, #0] 8006fb4: f042 4240 orr.w r2, r2, #3221225472 ; 0xc0000000 8006fb8: 611a str r2, [r3, #16] } /* Reset CBNDTR Register */ hmdma->Instance->CBNDTR = 0; 8006fba: 687b ldr r3, [r7, #4] 8006fbc: 681b ldr r3, [r3, #0] 8006fbe: 2200 movs r2, #0 8006fc0: 615a str r2, [r3, #20] /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */ if(hmdma->Init.SourceBlockAddressOffset < 0) 8006fc2: 687b ldr r3, [r7, #4] 8006fc4: 6b5b ldr r3, [r3, #52] ; 0x34 8006fc6: 2b00 cmp r3, #0 8006fc8: da11 bge.n 8006fee { hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM; 8006fca: 687b ldr r3, [r7, #4] 8006fcc: 681b ldr r3, [r3, #0] 8006fce: 695a ldr r2, [r3, #20] 8006fd0: 687b ldr r3, [r7, #4] 8006fd2: 681b ldr r3, [r3, #0] 8006fd4: f442 2280 orr.w r2, r2, #262144 ; 0x40000 8006fd8: 615a str r2, [r3, #20] /* Write new CBRUR Register value : source repeat block offset */ blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset); 8006fda: 687b ldr r3, [r7, #4] 8006fdc: 6b5b ldr r3, [r3, #52] ; 0x34 8006fde: 425b negs r3, r3 8006fe0: 60fb str r3, [r7, #12] hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU); 8006fe2: 687b ldr r3, [r7, #4] 8006fe4: 681b ldr r3, [r3, #0] 8006fe6: 68fa ldr r2, [r7, #12] 8006fe8: b292 uxth r2, r2 8006fea: 621a str r2, [r3, #32] 8006fec: e006 b.n 8006ffc } else { /* Write new CBRUR Register value : source repeat block offset */ hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU); 8006fee: 687b ldr r3, [r7, #4] 8006ff0: 6b5b ldr r3, [r3, #52] ; 0x34 8006ff2: 461a mov r2, r3 8006ff4: 687b ldr r3, [r7, #4] 8006ff6: 681b ldr r3, [r3, #0] 8006ff8: b292 uxth r2, r2 8006ffa: 621a str r2, [r3, #32] } /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */ if(hmdma->Init.DestBlockAddressOffset < 0) 8006ffc: 687b ldr r3, [r7, #4] 8006ffe: 6b9b ldr r3, [r3, #56] ; 0x38 8007000: 2b00 cmp r3, #0 8007002: da15 bge.n 8007030 { hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM; 8007004: 687b ldr r3, [r7, #4] 8007006: 681b ldr r3, [r3, #0] 8007008: 695a ldr r2, [r3, #20] 800700a: 687b ldr r3, [r7, #4] 800700c: 681b ldr r3, [r3, #0] 800700e: f442 2200 orr.w r2, r2, #524288 ; 0x80000 8007012: 615a str r2, [r3, #20] /* Write new CBRUR Register value : destination repeat block offset */ blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset); 8007014: 687b ldr r3, [r7, #4] 8007016: 6b9b ldr r3, [r3, #56] ; 0x38 8007018: 425b negs r3, r3 800701a: 60fb str r3, [r7, #12] hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); 800701c: 687b ldr r3, [r7, #4] 800701e: 681b ldr r3, [r3, #0] 8007020: 6a19 ldr r1, [r3, #32] 8007022: 68fb ldr r3, [r7, #12] 8007024: 041a lsls r2, r3, #16 8007026: 687b ldr r3, [r7, #4] 8007028: 681b ldr r3, [r3, #0] 800702a: 430a orrs r2, r1 800702c: 621a str r2, [r3, #32] 800702e: e009 b.n 8007044 } else { /*write new CBRUR Register value : destination repeat block offset */ hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); 8007030: 687b ldr r3, [r7, #4] 8007032: 681b ldr r3, [r3, #0] 8007034: 6a19 ldr r1, [r3, #32] 8007036: 687b ldr r3, [r7, #4] 8007038: 6b9b ldr r3, [r3, #56] ; 0x38 800703a: 041a lsls r2, r3, #16 800703c: 687b ldr r3, [r7, #4] 800703e: 681b ldr r3, [r3, #0] 8007040: 430a orrs r2, r1 8007042: 621a str r2, [r3, #32] } /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ if(hmdma->Init.Request != MDMA_REQUEST_SW) 8007044: 687b ldr r3, [r7, #4] 8007046: 685b ldr r3, [r3, #4] 8007048: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800704c: d006 beq.n 800705c { /* Set the HW request in CTRB register */ hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL; 800704e: 687b ldr r3, [r7, #4] 8007050: 685a ldr r2, [r3, #4] 8007052: 687b ldr r3, [r7, #4] 8007054: 681b ldr r3, [r3, #0] 8007056: b2d2 uxtb r2, r2 8007058: 629a str r2, [r3, #40] ; 0x28 800705a: e003 b.n 8007064 } else /* SW request : reset the CTBR register */ { hmdma->Instance->CTBR = 0; 800705c: 687b ldr r3, [r7, #4] 800705e: 681b ldr r3, [r3, #0] 8007060: 2200 movs r2, #0 8007062: 629a str r2, [r3, #40] ; 0x28 } /* Write Link Address Register */ hmdma->Instance->CLAR = 0; 8007064: 687b ldr r3, [r7, #4] 8007066: 681b ldr r3, [r3, #0] 8007068: 2200 movs r2, #0 800706a: 625a str r2, [r3, #36] ; 0x24 } 800706c: bf00 nop 800706e: 3714 adds r7, #20 8007070: 46bd mov sp, r7 8007072: f85d 7b04 ldr.w r7, [sp], #4 8007076: 4770 bx lr 08007078 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 8007078: b580 push {r7, lr} 800707a: b084 sub sp, #16 800707c: af00 add r7, sp, #0 800707e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 8007080: 4b19 ldr r3, [pc, #100] ; (80070e8 ) 8007082: 68db ldr r3, [r3, #12] 8007084: f003 0304 and.w r3, r3, #4 8007088: 2b04 cmp r3, #4 800708a: d00a beq.n 80070a2 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800708c: 4b16 ldr r3, [pc, #88] ; (80070e8 ) 800708e: 68db ldr r3, [r3, #12] 8007090: f003 0307 and.w r3, r3, #7 8007094: 687a ldr r2, [r7, #4] 8007096: 429a cmp r2, r3 8007098: d001 beq.n 800709e { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800709a: 2301 movs r3, #1 800709c: e01f b.n 80070de else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800709e: 2300 movs r3, #0 80070a0: e01d b.n 80070de } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 80070a2: 4b11 ldr r3, [pc, #68] ; (80070e8 ) 80070a4: 68db ldr r3, [r3, #12] 80070a6: f023 0207 bic.w r2, r3, #7 80070aa: 490f ldr r1, [pc, #60] ; (80070e8 ) 80070ac: 687b ldr r3, [r7, #4] 80070ae: 4313 orrs r3, r2 80070b0: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 80070b2: f7fb f957 bl 8002364 80070b6: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 80070b8: e009 b.n 80070ce { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 80070ba: f7fb f953 bl 8002364 80070be: 4602 mov r2, r0 80070c0: 68fb ldr r3, [r7, #12] 80070c2: 1ad3 subs r3, r2, r3 80070c4: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 80070c8: d901 bls.n 80070ce { return HAL_ERROR; 80070ca: 2301 movs r3, #1 80070cc: e007 b.n 80070de while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 80070ce: 4b06 ldr r3, [pc, #24] ; (80070e8 ) 80070d0: 685b ldr r3, [r3, #4] 80070d2: f403 5300 and.w r3, r3, #8192 ; 0x2000 80070d6: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80070da: d1ee bne.n 80070ba } } } #endif /* defined (SMPS) */ return HAL_OK; 80070dc: 2300 movs r3, #0 } 80070de: 4618 mov r0, r3 80070e0: 3710 adds r7, #16 80070e2: 46bd mov sp, r7 80070e4: bd80 pop {r7, pc} 80070e6: bf00 nop 80070e8: 58024800 .word 0x58024800 080070ec : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80070ec: b580 push {r7, lr} 80070ee: b08c sub sp, #48 ; 0x30 80070f0: af00 add r7, sp, #0 80070f2: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 80070f4: 687b ldr r3, [r7, #4] 80070f6: 2b00 cmp r3, #0 80070f8: d101 bne.n 80070fe { return HAL_ERROR; 80070fa: 2301 movs r3, #1 80070fc: e3c8 b.n 8007890 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80070fe: 687b ldr r3, [r7, #4] 8007100: 681b ldr r3, [r3, #0] 8007102: f003 0301 and.w r3, r3, #1 8007106: 2b00 cmp r3, #0 8007108: f000 8087 beq.w 800721a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800710c: 4b88 ldr r3, [pc, #544] ; (8007330 ) 800710e: 691b ldr r3, [r3, #16] 8007110: f003 0338 and.w r3, r3, #56 ; 0x38 8007114: 62fb str r3, [r7, #44] ; 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8007116: 4b86 ldr r3, [pc, #536] ; (8007330 ) 8007118: 6a9b ldr r3, [r3, #40] ; 0x28 800711a: 62bb str r3, [r7, #40] ; 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800711c: 6afb ldr r3, [r7, #44] ; 0x2c 800711e: 2b10 cmp r3, #16 8007120: d007 beq.n 8007132 8007122: 6afb ldr r3, [r7, #44] ; 0x2c 8007124: 2b18 cmp r3, #24 8007126: d110 bne.n 800714a 8007128: 6abb ldr r3, [r7, #40] ; 0x28 800712a: f003 0303 and.w r3, r3, #3 800712e: 2b02 cmp r3, #2 8007130: d10b bne.n 800714a { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8007132: 4b7f ldr r3, [pc, #508] ; (8007330 ) 8007134: 681b ldr r3, [r3, #0] 8007136: f403 3300 and.w r3, r3, #131072 ; 0x20000 800713a: 2b00 cmp r3, #0 800713c: d06c beq.n 8007218 800713e: 687b ldr r3, [r7, #4] 8007140: 685b ldr r3, [r3, #4] 8007142: 2b00 cmp r3, #0 8007144: d168 bne.n 8007218 { return HAL_ERROR; 8007146: 2301 movs r3, #1 8007148: e3a2 b.n 8007890 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800714a: 687b ldr r3, [r7, #4] 800714c: 685b ldr r3, [r3, #4] 800714e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8007152: d106 bne.n 8007162 8007154: 4b76 ldr r3, [pc, #472] ; (8007330 ) 8007156: 681b ldr r3, [r3, #0] 8007158: 4a75 ldr r2, [pc, #468] ; (8007330 ) 800715a: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800715e: 6013 str r3, [r2, #0] 8007160: e02e b.n 80071c0 8007162: 687b ldr r3, [r7, #4] 8007164: 685b ldr r3, [r3, #4] 8007166: 2b00 cmp r3, #0 8007168: d10c bne.n 8007184 800716a: 4b71 ldr r3, [pc, #452] ; (8007330 ) 800716c: 681b ldr r3, [r3, #0] 800716e: 4a70 ldr r2, [pc, #448] ; (8007330 ) 8007170: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8007174: 6013 str r3, [r2, #0] 8007176: 4b6e ldr r3, [pc, #440] ; (8007330 ) 8007178: 681b ldr r3, [r3, #0] 800717a: 4a6d ldr r2, [pc, #436] ; (8007330 ) 800717c: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8007180: 6013 str r3, [r2, #0] 8007182: e01d b.n 80071c0 8007184: 687b ldr r3, [r7, #4] 8007186: 685b ldr r3, [r3, #4] 8007188: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 800718c: d10c bne.n 80071a8 800718e: 4b68 ldr r3, [pc, #416] ; (8007330 ) 8007190: 681b ldr r3, [r3, #0] 8007192: 4a67 ldr r2, [pc, #412] ; (8007330 ) 8007194: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8007198: 6013 str r3, [r2, #0] 800719a: 4b65 ldr r3, [pc, #404] ; (8007330 ) 800719c: 681b ldr r3, [r3, #0] 800719e: 4a64 ldr r2, [pc, #400] ; (8007330 ) 80071a0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80071a4: 6013 str r3, [r2, #0] 80071a6: e00b b.n 80071c0 80071a8: 4b61 ldr r3, [pc, #388] ; (8007330 ) 80071aa: 681b ldr r3, [r3, #0] 80071ac: 4a60 ldr r2, [pc, #384] ; (8007330 ) 80071ae: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80071b2: 6013 str r3, [r2, #0] 80071b4: 4b5e ldr r3, [pc, #376] ; (8007330 ) 80071b6: 681b ldr r3, [r3, #0] 80071b8: 4a5d ldr r2, [pc, #372] ; (8007330 ) 80071ba: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80071be: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80071c0: 687b ldr r3, [r7, #4] 80071c2: 685b ldr r3, [r3, #4] 80071c4: 2b00 cmp r3, #0 80071c6: d013 beq.n 80071f0 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80071c8: f7fb f8cc bl 8002364 80071cc: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80071ce: e008 b.n 80071e2 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80071d0: f7fb f8c8 bl 8002364 80071d4: 4602 mov r2, r0 80071d6: 6a7b ldr r3, [r7, #36] ; 0x24 80071d8: 1ad3 subs r3, r2, r3 80071da: 2b64 cmp r3, #100 ; 0x64 80071dc: d901 bls.n 80071e2 { return HAL_TIMEOUT; 80071de: 2303 movs r3, #3 80071e0: e356 b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80071e2: 4b53 ldr r3, [pc, #332] ; (8007330 ) 80071e4: 681b ldr r3, [r3, #0] 80071e6: f403 3300 and.w r3, r3, #131072 ; 0x20000 80071ea: 2b00 cmp r3, #0 80071ec: d0f0 beq.n 80071d0 80071ee: e014 b.n 800721a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80071f0: f7fb f8b8 bl 8002364 80071f4: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 80071f6: e008 b.n 800720a { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80071f8: f7fb f8b4 bl 8002364 80071fc: 4602 mov r2, r0 80071fe: 6a7b ldr r3, [r7, #36] ; 0x24 8007200: 1ad3 subs r3, r2, r3 8007202: 2b64 cmp r3, #100 ; 0x64 8007204: d901 bls.n 800720a { return HAL_TIMEOUT; 8007206: 2303 movs r3, #3 8007208: e342 b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800720a: 4b49 ldr r3, [pc, #292] ; (8007330 ) 800720c: 681b ldr r3, [r3, #0] 800720e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8007212: 2b00 cmp r3, #0 8007214: d1f0 bne.n 80071f8 8007216: e000 b.n 800721a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8007218: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800721a: 687b ldr r3, [r7, #4] 800721c: 681b ldr r3, [r3, #0] 800721e: f003 0302 and.w r3, r3, #2 8007222: 2b00 cmp r3, #0 8007224: f000 808c beq.w 8007340 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8007228: 4b41 ldr r3, [pc, #260] ; (8007330 ) 800722a: 691b ldr r3, [r3, #16] 800722c: f003 0338 and.w r3, r3, #56 ; 0x38 8007230: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8007232: 4b3f ldr r3, [pc, #252] ; (8007330 ) 8007234: 6a9b ldr r3, [r3, #40] ; 0x28 8007236: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 8007238: 6a3b ldr r3, [r7, #32] 800723a: 2b00 cmp r3, #0 800723c: d007 beq.n 800724e 800723e: 6a3b ldr r3, [r7, #32] 8007240: 2b18 cmp r3, #24 8007242: d137 bne.n 80072b4 8007244: 69fb ldr r3, [r7, #28] 8007246: f003 0303 and.w r3, r3, #3 800724a: 2b00 cmp r3, #0 800724c: d132 bne.n 80072b4 { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800724e: 4b38 ldr r3, [pc, #224] ; (8007330 ) 8007250: 681b ldr r3, [r3, #0] 8007252: f003 0304 and.w r3, r3, #4 8007256: 2b00 cmp r3, #0 8007258: d005 beq.n 8007266 800725a: 687b ldr r3, [r7, #4] 800725c: 68db ldr r3, [r3, #12] 800725e: 2b00 cmp r3, #0 8007260: d101 bne.n 8007266 { return HAL_ERROR; 8007262: 2301 movs r3, #1 8007264: e314 b.n 8007890 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 8007266: 4b32 ldr r3, [pc, #200] ; (8007330 ) 8007268: 681b ldr r3, [r3, #0] 800726a: f023 0219 bic.w r2, r3, #25 800726e: 687b ldr r3, [r7, #4] 8007270: 68db ldr r3, [r3, #12] 8007272: 492f ldr r1, [pc, #188] ; (8007330 ) 8007274: 4313 orrs r3, r2 8007276: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007278: f7fb f874 bl 8002364 800727c: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800727e: e008 b.n 8007292 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8007280: f7fb f870 bl 8002364 8007284: 4602 mov r2, r0 8007286: 6a7b ldr r3, [r7, #36] ; 0x24 8007288: 1ad3 subs r3, r2, r3 800728a: 2b02 cmp r3, #2 800728c: d901 bls.n 8007292 { return HAL_TIMEOUT; 800728e: 2303 movs r3, #3 8007290: e2fe b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8007292: 4b27 ldr r3, [pc, #156] ; (8007330 ) 8007294: 681b ldr r3, [r3, #0] 8007296: f003 0304 and.w r3, r3, #4 800729a: 2b00 cmp r3, #0 800729c: d0f0 beq.n 8007280 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800729e: 4b24 ldr r3, [pc, #144] ; (8007330 ) 80072a0: 685b ldr r3, [r3, #4] 80072a2: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 80072a6: 687b ldr r3, [r7, #4] 80072a8: 691b ldr r3, [r3, #16] 80072aa: 061b lsls r3, r3, #24 80072ac: 4920 ldr r1, [pc, #128] ; (8007330 ) 80072ae: 4313 orrs r3, r2 80072b0: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80072b2: e045 b.n 8007340 } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 80072b4: 687b ldr r3, [r7, #4] 80072b6: 68db ldr r3, [r3, #12] 80072b8: 2b00 cmp r3, #0 80072ba: d026 beq.n 800730a { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 80072bc: 4b1c ldr r3, [pc, #112] ; (8007330 ) 80072be: 681b ldr r3, [r3, #0] 80072c0: f023 0219 bic.w r2, r3, #25 80072c4: 687b ldr r3, [r7, #4] 80072c6: 68db ldr r3, [r3, #12] 80072c8: 4919 ldr r1, [pc, #100] ; (8007330 ) 80072ca: 4313 orrs r3, r2 80072cc: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80072ce: f7fb f849 bl 8002364 80072d2: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80072d4: e008 b.n 80072e8 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80072d6: f7fb f845 bl 8002364 80072da: 4602 mov r2, r0 80072dc: 6a7b ldr r3, [r7, #36] ; 0x24 80072de: 1ad3 subs r3, r2, r3 80072e0: 2b02 cmp r3, #2 80072e2: d901 bls.n 80072e8 { return HAL_TIMEOUT; 80072e4: 2303 movs r3, #3 80072e6: e2d3 b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80072e8: 4b11 ldr r3, [pc, #68] ; (8007330 ) 80072ea: 681b ldr r3, [r3, #0] 80072ec: f003 0304 and.w r3, r3, #4 80072f0: 2b00 cmp r3, #0 80072f2: d0f0 beq.n 80072d6 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80072f4: 4b0e ldr r3, [pc, #56] ; (8007330 ) 80072f6: 685b ldr r3, [r3, #4] 80072f8: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 80072fc: 687b ldr r3, [r7, #4] 80072fe: 691b ldr r3, [r3, #16] 8007300: 061b lsls r3, r3, #24 8007302: 490b ldr r1, [pc, #44] ; (8007330 ) 8007304: 4313 orrs r3, r2 8007306: 604b str r3, [r1, #4] 8007308: e01a b.n 8007340 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800730a: 4b09 ldr r3, [pc, #36] ; (8007330 ) 800730c: 681b ldr r3, [r3, #0] 800730e: 4a08 ldr r2, [pc, #32] ; (8007330 ) 8007310: f023 0301 bic.w r3, r3, #1 8007314: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007316: f7fb f825 bl 8002364 800731a: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800731c: e00a b.n 8007334 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800731e: f7fb f821 bl 8002364 8007322: 4602 mov r2, r0 8007324: 6a7b ldr r3, [r7, #36] ; 0x24 8007326: 1ad3 subs r3, r2, r3 8007328: 2b02 cmp r3, #2 800732a: d903 bls.n 8007334 { return HAL_TIMEOUT; 800732c: 2303 movs r3, #3 800732e: e2af b.n 8007890 8007330: 58024400 .word 0x58024400 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8007334: 4b96 ldr r3, [pc, #600] ; (8007590 ) 8007336: 681b ldr r3, [r3, #0] 8007338: f003 0304 and.w r3, r3, #4 800733c: 2b00 cmp r3, #0 800733e: d1ee bne.n 800731e } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 8007340: 687b ldr r3, [r7, #4] 8007342: 681b ldr r3, [r3, #0] 8007344: f003 0310 and.w r3, r3, #16 8007348: 2b00 cmp r3, #0 800734a: d06a beq.n 8007422 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800734c: 4b90 ldr r3, [pc, #576] ; (8007590 ) 800734e: 691b ldr r3, [r3, #16] 8007350: f003 0338 and.w r3, r3, #56 ; 0x38 8007354: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8007356: 4b8e ldr r3, [pc, #568] ; (8007590 ) 8007358: 6a9b ldr r3, [r3, #40] ; 0x28 800735a: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800735c: 69bb ldr r3, [r7, #24] 800735e: 2b08 cmp r3, #8 8007360: d007 beq.n 8007372 8007362: 69bb ldr r3, [r7, #24] 8007364: 2b18 cmp r3, #24 8007366: d11b bne.n 80073a0 8007368: 697b ldr r3, [r7, #20] 800736a: f003 0303 and.w r3, r3, #3 800736e: 2b01 cmp r3, #1 8007370: d116 bne.n 80073a0 { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 8007372: 4b87 ldr r3, [pc, #540] ; (8007590 ) 8007374: 681b ldr r3, [r3, #0] 8007376: f403 7380 and.w r3, r3, #256 ; 0x100 800737a: 2b00 cmp r3, #0 800737c: d005 beq.n 800738a 800737e: 687b ldr r3, [r7, #4] 8007380: 69db ldr r3, [r3, #28] 8007382: 2b80 cmp r3, #128 ; 0x80 8007384: d001 beq.n 800738a { return HAL_ERROR; 8007386: 2301 movs r3, #1 8007388: e282 b.n 8007890 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800738a: 4b81 ldr r3, [pc, #516] ; (8007590 ) 800738c: 68db ldr r3, [r3, #12] 800738e: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 8007392: 687b ldr r3, [r7, #4] 8007394: 6a1b ldr r3, [r3, #32] 8007396: 061b lsls r3, r3, #24 8007398: 497d ldr r1, [pc, #500] ; (8007590 ) 800739a: 4313 orrs r3, r2 800739c: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800739e: e040 b.n 8007422 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 80073a0: 687b ldr r3, [r7, #4] 80073a2: 69db ldr r3, [r3, #28] 80073a4: 2b00 cmp r3, #0 80073a6: d023 beq.n 80073f0 { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 80073a8: 4b79 ldr r3, [pc, #484] ; (8007590 ) 80073aa: 681b ldr r3, [r3, #0] 80073ac: 4a78 ldr r2, [pc, #480] ; (8007590 ) 80073ae: f043 0380 orr.w r3, r3, #128 ; 0x80 80073b2: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80073b4: f7fa ffd6 bl 8002364 80073b8: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80073ba: e008 b.n 80073ce { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 80073bc: f7fa ffd2 bl 8002364 80073c0: 4602 mov r2, r0 80073c2: 6a7b ldr r3, [r7, #36] ; 0x24 80073c4: 1ad3 subs r3, r2, r3 80073c6: 2b02 cmp r3, #2 80073c8: d901 bls.n 80073ce { return HAL_TIMEOUT; 80073ca: 2303 movs r3, #3 80073cc: e260 b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80073ce: 4b70 ldr r3, [pc, #448] ; (8007590 ) 80073d0: 681b ldr r3, [r3, #0] 80073d2: f403 7380 and.w r3, r3, #256 ; 0x100 80073d6: 2b00 cmp r3, #0 80073d8: d0f0 beq.n 80073bc } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80073da: 4b6d ldr r3, [pc, #436] ; (8007590 ) 80073dc: 68db ldr r3, [r3, #12] 80073de: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 80073e2: 687b ldr r3, [r7, #4] 80073e4: 6a1b ldr r3, [r3, #32] 80073e6: 061b lsls r3, r3, #24 80073e8: 4969 ldr r1, [pc, #420] ; (8007590 ) 80073ea: 4313 orrs r3, r2 80073ec: 60cb str r3, [r1, #12] 80073ee: e018 b.n 8007422 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 80073f0: 4b67 ldr r3, [pc, #412] ; (8007590 ) 80073f2: 681b ldr r3, [r3, #0] 80073f4: 4a66 ldr r2, [pc, #408] ; (8007590 ) 80073f6: f023 0380 bic.w r3, r3, #128 ; 0x80 80073fa: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80073fc: f7fa ffb2 bl 8002364 8007400: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8007402: e008 b.n 8007416 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 8007404: f7fa ffae bl 8002364 8007408: 4602 mov r2, r0 800740a: 6a7b ldr r3, [r7, #36] ; 0x24 800740c: 1ad3 subs r3, r2, r3 800740e: 2b02 cmp r3, #2 8007410: d901 bls.n 8007416 { return HAL_TIMEOUT; 8007412: 2303 movs r3, #3 8007414: e23c b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8007416: 4b5e ldr r3, [pc, #376] ; (8007590 ) 8007418: 681b ldr r3, [r3, #0] 800741a: f403 7380 and.w r3, r3, #256 ; 0x100 800741e: 2b00 cmp r3, #0 8007420: d1f0 bne.n 8007404 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8007422: 687b ldr r3, [r7, #4] 8007424: 681b ldr r3, [r3, #0] 8007426: f003 0308 and.w r3, r3, #8 800742a: 2b00 cmp r3, #0 800742c: d036 beq.n 800749c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800742e: 687b ldr r3, [r7, #4] 8007430: 695b ldr r3, [r3, #20] 8007432: 2b00 cmp r3, #0 8007434: d019 beq.n 800746a { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8007436: 4b56 ldr r3, [pc, #344] ; (8007590 ) 8007438: 6f5b ldr r3, [r3, #116] ; 0x74 800743a: 4a55 ldr r2, [pc, #340] ; (8007590 ) 800743c: f043 0301 orr.w r3, r3, #1 8007440: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007442: f7fa ff8f bl 8002364 8007446: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 8007448: e008 b.n 800745c { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800744a: f7fa ff8b bl 8002364 800744e: 4602 mov r2, r0 8007450: 6a7b ldr r3, [r7, #36] ; 0x24 8007452: 1ad3 subs r3, r2, r3 8007454: 2b02 cmp r3, #2 8007456: d901 bls.n 800745c { return HAL_TIMEOUT; 8007458: 2303 movs r3, #3 800745a: e219 b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800745c: 4b4c ldr r3, [pc, #304] ; (8007590 ) 800745e: 6f5b ldr r3, [r3, #116] ; 0x74 8007460: f003 0302 and.w r3, r3, #2 8007464: 2b00 cmp r3, #0 8007466: d0f0 beq.n 800744a 8007468: e018 b.n 800749c } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800746a: 4b49 ldr r3, [pc, #292] ; (8007590 ) 800746c: 6f5b ldr r3, [r3, #116] ; 0x74 800746e: 4a48 ldr r2, [pc, #288] ; (8007590 ) 8007470: f023 0301 bic.w r3, r3, #1 8007474: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007476: f7fa ff75 bl 8002364 800747a: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800747c: e008 b.n 8007490 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800747e: f7fa ff71 bl 8002364 8007482: 4602 mov r2, r0 8007484: 6a7b ldr r3, [r7, #36] ; 0x24 8007486: 1ad3 subs r3, r2, r3 8007488: 2b02 cmp r3, #2 800748a: d901 bls.n 8007490 { return HAL_TIMEOUT; 800748c: 2303 movs r3, #3 800748e: e1ff b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8007490: 4b3f ldr r3, [pc, #252] ; (8007590 ) 8007492: 6f5b ldr r3, [r3, #116] ; 0x74 8007494: f003 0302 and.w r3, r3, #2 8007498: 2b00 cmp r3, #0 800749a: d1f0 bne.n 800747e } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800749c: 687b ldr r3, [r7, #4] 800749e: 681b ldr r3, [r3, #0] 80074a0: f003 0320 and.w r3, r3, #32 80074a4: 2b00 cmp r3, #0 80074a6: d036 beq.n 8007516 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 80074a8: 687b ldr r3, [r7, #4] 80074aa: 699b ldr r3, [r3, #24] 80074ac: 2b00 cmp r3, #0 80074ae: d019 beq.n 80074e4 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 80074b0: 4b37 ldr r3, [pc, #220] ; (8007590 ) 80074b2: 681b ldr r3, [r3, #0] 80074b4: 4a36 ldr r2, [pc, #216] ; (8007590 ) 80074b6: f443 5380 orr.w r3, r3, #4096 ; 0x1000 80074ba: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 80074bc: f7fa ff52 bl 8002364 80074c0: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 80074c2: e008 b.n 80074d6 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 80074c4: f7fa ff4e bl 8002364 80074c8: 4602 mov r2, r0 80074ca: 6a7b ldr r3, [r7, #36] ; 0x24 80074cc: 1ad3 subs r3, r2, r3 80074ce: 2b02 cmp r3, #2 80074d0: d901 bls.n 80074d6 { return HAL_TIMEOUT; 80074d2: 2303 movs r3, #3 80074d4: e1dc b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 80074d6: 4b2e ldr r3, [pc, #184] ; (8007590 ) 80074d8: 681b ldr r3, [r3, #0] 80074da: f403 5300 and.w r3, r3, #8192 ; 0x2000 80074de: 2b00 cmp r3, #0 80074e0: d0f0 beq.n 80074c4 80074e2: e018 b.n 8007516 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 80074e4: 4b2a ldr r3, [pc, #168] ; (8007590 ) 80074e6: 681b ldr r3, [r3, #0] 80074e8: 4a29 ldr r2, [pc, #164] ; (8007590 ) 80074ea: f423 5380 bic.w r3, r3, #4096 ; 0x1000 80074ee: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 80074f0: f7fa ff38 bl 8002364 80074f4: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 80074f6: e008 b.n 800750a { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 80074f8: f7fa ff34 bl 8002364 80074fc: 4602 mov r2, r0 80074fe: 6a7b ldr r3, [r7, #36] ; 0x24 8007500: 1ad3 subs r3, r2, r3 8007502: 2b02 cmp r3, #2 8007504: d901 bls.n 800750a { return HAL_TIMEOUT; 8007506: 2303 movs r3, #3 8007508: e1c2 b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800750a: 4b21 ldr r3, [pc, #132] ; (8007590 ) 800750c: 681b ldr r3, [r3, #0] 800750e: f403 5300 and.w r3, r3, #8192 ; 0x2000 8007512: 2b00 cmp r3, #0 8007514: d1f0 bne.n 80074f8 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8007516: 687b ldr r3, [r7, #4] 8007518: 681b ldr r3, [r3, #0] 800751a: f003 0304 and.w r3, r3, #4 800751e: 2b00 cmp r3, #0 8007520: f000 8086 beq.w 8007630 { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 8007524: 4b1b ldr r3, [pc, #108] ; (8007594 ) 8007526: 681b ldr r3, [r3, #0] 8007528: 4a1a ldr r2, [pc, #104] ; (8007594 ) 800752a: f443 7380 orr.w r3, r3, #256 ; 0x100 800752e: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8007530: f7fa ff18 bl 8002364 8007534: 6278 str r0, [r7, #36] ; 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8007536: e008 b.n 800754a { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8007538: f7fa ff14 bl 8002364 800753c: 4602 mov r2, r0 800753e: 6a7b ldr r3, [r7, #36] ; 0x24 8007540: 1ad3 subs r3, r2, r3 8007542: 2b64 cmp r3, #100 ; 0x64 8007544: d901 bls.n 800754a { return HAL_TIMEOUT; 8007546: 2303 movs r3, #3 8007548: e1a2 b.n 8007890 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800754a: 4b12 ldr r3, [pc, #72] ; (8007594 ) 800754c: 681b ldr r3, [r3, #0] 800754e: f403 7380 and.w r3, r3, #256 ; 0x100 8007552: 2b00 cmp r3, #0 8007554: d0f0 beq.n 8007538 } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8007556: 687b ldr r3, [r7, #4] 8007558: 689b ldr r3, [r3, #8] 800755a: 2b01 cmp r3, #1 800755c: d106 bne.n 800756c 800755e: 4b0c ldr r3, [pc, #48] ; (8007590 ) 8007560: 6f1b ldr r3, [r3, #112] ; 0x70 8007562: 4a0b ldr r2, [pc, #44] ; (8007590 ) 8007564: f043 0301 orr.w r3, r3, #1 8007568: 6713 str r3, [r2, #112] ; 0x70 800756a: e032 b.n 80075d2 800756c: 687b ldr r3, [r7, #4] 800756e: 689b ldr r3, [r3, #8] 8007570: 2b00 cmp r3, #0 8007572: d111 bne.n 8007598 8007574: 4b06 ldr r3, [pc, #24] ; (8007590 ) 8007576: 6f1b ldr r3, [r3, #112] ; 0x70 8007578: 4a05 ldr r2, [pc, #20] ; (8007590 ) 800757a: f023 0301 bic.w r3, r3, #1 800757e: 6713 str r3, [r2, #112] ; 0x70 8007580: 4b03 ldr r3, [pc, #12] ; (8007590 ) 8007582: 6f1b ldr r3, [r3, #112] ; 0x70 8007584: 4a02 ldr r2, [pc, #8] ; (8007590 ) 8007586: f023 0304 bic.w r3, r3, #4 800758a: 6713 str r3, [r2, #112] ; 0x70 800758c: e021 b.n 80075d2 800758e: bf00 nop 8007590: 58024400 .word 0x58024400 8007594: 58024800 .word 0x58024800 8007598: 687b ldr r3, [r7, #4] 800759a: 689b ldr r3, [r3, #8] 800759c: 2b05 cmp r3, #5 800759e: d10c bne.n 80075ba 80075a0: 4b83 ldr r3, [pc, #524] ; (80077b0 ) 80075a2: 6f1b ldr r3, [r3, #112] ; 0x70 80075a4: 4a82 ldr r2, [pc, #520] ; (80077b0 ) 80075a6: f043 0304 orr.w r3, r3, #4 80075aa: 6713 str r3, [r2, #112] ; 0x70 80075ac: 4b80 ldr r3, [pc, #512] ; (80077b0 ) 80075ae: 6f1b ldr r3, [r3, #112] ; 0x70 80075b0: 4a7f ldr r2, [pc, #508] ; (80077b0 ) 80075b2: f043 0301 orr.w r3, r3, #1 80075b6: 6713 str r3, [r2, #112] ; 0x70 80075b8: e00b b.n 80075d2 80075ba: 4b7d ldr r3, [pc, #500] ; (80077b0 ) 80075bc: 6f1b ldr r3, [r3, #112] ; 0x70 80075be: 4a7c ldr r2, [pc, #496] ; (80077b0 ) 80075c0: f023 0301 bic.w r3, r3, #1 80075c4: 6713 str r3, [r2, #112] ; 0x70 80075c6: 4b7a ldr r3, [pc, #488] ; (80077b0 ) 80075c8: 6f1b ldr r3, [r3, #112] ; 0x70 80075ca: 4a79 ldr r2, [pc, #484] ; (80077b0 ) 80075cc: f023 0304 bic.w r3, r3, #4 80075d0: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 80075d2: 687b ldr r3, [r7, #4] 80075d4: 689b ldr r3, [r3, #8] 80075d6: 2b00 cmp r3, #0 80075d8: d015 beq.n 8007606 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80075da: f7fa fec3 bl 8002364 80075de: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80075e0: e00a b.n 80075f8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80075e2: f7fa febf bl 8002364 80075e6: 4602 mov r2, r0 80075e8: 6a7b ldr r3, [r7, #36] ; 0x24 80075ea: 1ad3 subs r3, r2, r3 80075ec: f241 3288 movw r2, #5000 ; 0x1388 80075f0: 4293 cmp r3, r2 80075f2: d901 bls.n 80075f8 { return HAL_TIMEOUT; 80075f4: 2303 movs r3, #3 80075f6: e14b b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80075f8: 4b6d ldr r3, [pc, #436] ; (80077b0 ) 80075fa: 6f1b ldr r3, [r3, #112] ; 0x70 80075fc: f003 0302 and.w r3, r3, #2 8007600: 2b00 cmp r3, #0 8007602: d0ee beq.n 80075e2 8007604: e014 b.n 8007630 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007606: f7fa fead bl 8002364 800760a: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800760c: e00a b.n 8007624 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800760e: f7fa fea9 bl 8002364 8007612: 4602 mov r2, r0 8007614: 6a7b ldr r3, [r7, #36] ; 0x24 8007616: 1ad3 subs r3, r2, r3 8007618: f241 3288 movw r2, #5000 ; 0x1388 800761c: 4293 cmp r3, r2 800761e: d901 bls.n 8007624 { return HAL_TIMEOUT; 8007620: 2303 movs r3, #3 8007622: e135 b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8007624: 4b62 ldr r3, [pc, #392] ; (80077b0 ) 8007626: 6f1b ldr r3, [r3, #112] ; 0x70 8007628: f003 0302 and.w r3, r3, #2 800762c: 2b00 cmp r3, #0 800762e: d1ee bne.n 800760e } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8007630: 687b ldr r3, [r7, #4] 8007632: 6a5b ldr r3, [r3, #36] ; 0x24 8007634: 2b00 cmp r3, #0 8007636: f000 812a beq.w 800788e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800763a: 4b5d ldr r3, [pc, #372] ; (80077b0 ) 800763c: 691b ldr r3, [r3, #16] 800763e: f003 0338 and.w r3, r3, #56 ; 0x38 8007642: 2b18 cmp r3, #24 8007644: f000 80ba beq.w 80077bc { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8007648: 687b ldr r3, [r7, #4] 800764a: 6a5b ldr r3, [r3, #36] ; 0x24 800764c: 2b02 cmp r3, #2 800764e: f040 8095 bne.w 800777c assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8007652: 4b57 ldr r3, [pc, #348] ; (80077b0 ) 8007654: 681b ldr r3, [r3, #0] 8007656: 4a56 ldr r2, [pc, #344] ; (80077b0 ) 8007658: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 800765c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800765e: f7fa fe81 bl 8002364 8007662: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8007664: e008 b.n 8007678 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8007666: f7fa fe7d bl 8002364 800766a: 4602 mov r2, r0 800766c: 6a7b ldr r3, [r7, #36] ; 0x24 800766e: 1ad3 subs r3, r2, r3 8007670: 2b02 cmp r3, #2 8007672: d901 bls.n 8007678 { return HAL_TIMEOUT; 8007674: 2303 movs r3, #3 8007676: e10b b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8007678: 4b4d ldr r3, [pc, #308] ; (80077b0 ) 800767a: 681b ldr r3, [r3, #0] 800767c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8007680: 2b00 cmp r3, #0 8007682: d1f0 bne.n 8007666 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8007684: 4b4a ldr r3, [pc, #296] ; (80077b0 ) 8007686: 6a9a ldr r2, [r3, #40] ; 0x28 8007688: 4b4a ldr r3, [pc, #296] ; (80077b4 ) 800768a: 4013 ands r3, r2 800768c: 687a ldr r2, [r7, #4] 800768e: 6a91 ldr r1, [r2, #40] ; 0x28 8007690: 687a ldr r2, [r7, #4] 8007692: 6ad2 ldr r2, [r2, #44] ; 0x2c 8007694: 0112 lsls r2, r2, #4 8007696: 430a orrs r2, r1 8007698: 4945 ldr r1, [pc, #276] ; (80077b0 ) 800769a: 4313 orrs r3, r2 800769c: 628b str r3, [r1, #40] ; 0x28 800769e: 687b ldr r3, [r7, #4] 80076a0: 6b1b ldr r3, [r3, #48] ; 0x30 80076a2: 3b01 subs r3, #1 80076a4: f3c3 0208 ubfx r2, r3, #0, #9 80076a8: 687b ldr r3, [r7, #4] 80076aa: 6b5b ldr r3, [r3, #52] ; 0x34 80076ac: 3b01 subs r3, #1 80076ae: 025b lsls r3, r3, #9 80076b0: b29b uxth r3, r3 80076b2: 431a orrs r2, r3 80076b4: 687b ldr r3, [r7, #4] 80076b6: 6b9b ldr r3, [r3, #56] ; 0x38 80076b8: 3b01 subs r3, #1 80076ba: 041b lsls r3, r3, #16 80076bc: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 80076c0: 431a orrs r2, r3 80076c2: 687b ldr r3, [r7, #4] 80076c4: 6bdb ldr r3, [r3, #60] ; 0x3c 80076c6: 3b01 subs r3, #1 80076c8: 061b lsls r3, r3, #24 80076ca: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 80076ce: 4938 ldr r1, [pc, #224] ; (80077b0 ) 80076d0: 4313 orrs r3, r2 80076d2: 630b str r3, [r1, #48] ; 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 80076d4: 4b36 ldr r3, [pc, #216] ; (80077b0 ) 80076d6: 6adb ldr r3, [r3, #44] ; 0x2c 80076d8: 4a35 ldr r2, [pc, #212] ; (80077b0 ) 80076da: f023 0301 bic.w r3, r3, #1 80076de: 62d3 str r3, [r2, #44] ; 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 80076e0: 4b33 ldr r3, [pc, #204] ; (80077b0 ) 80076e2: 6b5a ldr r2, [r3, #52] ; 0x34 80076e4: 4b34 ldr r3, [pc, #208] ; (80077b8 ) 80076e6: 4013 ands r3, r2 80076e8: 687a ldr r2, [r7, #4] 80076ea: 6c92 ldr r2, [r2, #72] ; 0x48 80076ec: 00d2 lsls r2, r2, #3 80076ee: 4930 ldr r1, [pc, #192] ; (80077b0 ) 80076f0: 4313 orrs r3, r2 80076f2: 634b str r3, [r1, #52] ; 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 80076f4: 4b2e ldr r3, [pc, #184] ; (80077b0 ) 80076f6: 6adb ldr r3, [r3, #44] ; 0x2c 80076f8: f023 020c bic.w r2, r3, #12 80076fc: 687b ldr r3, [r7, #4] 80076fe: 6c1b ldr r3, [r3, #64] ; 0x40 8007700: 492b ldr r1, [pc, #172] ; (80077b0 ) 8007702: 4313 orrs r3, r2 8007704: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 8007706: 4b2a ldr r3, [pc, #168] ; (80077b0 ) 8007708: 6adb ldr r3, [r3, #44] ; 0x2c 800770a: f023 0202 bic.w r2, r3, #2 800770e: 687b ldr r3, [r7, #4] 8007710: 6c5b ldr r3, [r3, #68] ; 0x44 8007712: 4927 ldr r1, [pc, #156] ; (80077b0 ) 8007714: 4313 orrs r3, r2 8007716: 62cb str r3, [r1, #44] ; 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 8007718: 4b25 ldr r3, [pc, #148] ; (80077b0 ) 800771a: 6adb ldr r3, [r3, #44] ; 0x2c 800771c: 4a24 ldr r2, [pc, #144] ; (80077b0 ) 800771e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8007722: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8007724: 4b22 ldr r3, [pc, #136] ; (80077b0 ) 8007726: 6adb ldr r3, [r3, #44] ; 0x2c 8007728: 4a21 ldr r2, [pc, #132] ; (80077b0 ) 800772a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800772e: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 8007730: 4b1f ldr r3, [pc, #124] ; (80077b0 ) 8007732: 6adb ldr r3, [r3, #44] ; 0x2c 8007734: 4a1e ldr r2, [pc, #120] ; (80077b0 ) 8007736: f443 2380 orr.w r3, r3, #262144 ; 0x40000 800773a: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 800773c: 4b1c ldr r3, [pc, #112] ; (80077b0 ) 800773e: 6adb ldr r3, [r3, #44] ; 0x2c 8007740: 4a1b ldr r2, [pc, #108] ; (80077b0 ) 8007742: f043 0301 orr.w r3, r3, #1 8007746: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8007748: 4b19 ldr r3, [pc, #100] ; (80077b0 ) 800774a: 681b ldr r3, [r3, #0] 800774c: 4a18 ldr r2, [pc, #96] ; (80077b0 ) 800774e: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8007752: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007754: f7fa fe06 bl 8002364 8007758: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800775a: e008 b.n 800776e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800775c: f7fa fe02 bl 8002364 8007760: 4602 mov r2, r0 8007762: 6a7b ldr r3, [r7, #36] ; 0x24 8007764: 1ad3 subs r3, r2, r3 8007766: 2b02 cmp r3, #2 8007768: d901 bls.n 800776e { return HAL_TIMEOUT; 800776a: 2303 movs r3, #3 800776c: e090 b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800776e: 4b10 ldr r3, [pc, #64] ; (80077b0 ) 8007770: 681b ldr r3, [r3, #0] 8007772: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8007776: 2b00 cmp r3, #0 8007778: d0f0 beq.n 800775c 800777a: e088 b.n 800788e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800777c: 4b0c ldr r3, [pc, #48] ; (80077b0 ) 800777e: 681b ldr r3, [r3, #0] 8007780: 4a0b ldr r2, [pc, #44] ; (80077b0 ) 8007782: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8007786: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007788: f7fa fdec bl 8002364 800778c: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800778e: e008 b.n 80077a2 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8007790: f7fa fde8 bl 8002364 8007794: 4602 mov r2, r0 8007796: 6a7b ldr r3, [r7, #36] ; 0x24 8007798: 1ad3 subs r3, r2, r3 800779a: 2b02 cmp r3, #2 800779c: d901 bls.n 80077a2 { return HAL_TIMEOUT; 800779e: 2303 movs r3, #3 80077a0: e076 b.n 8007890 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80077a2: 4b03 ldr r3, [pc, #12] ; (80077b0 ) 80077a4: 681b ldr r3, [r3, #0] 80077a6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80077aa: 2b00 cmp r3, #0 80077ac: d1f0 bne.n 8007790 80077ae: e06e b.n 800788e 80077b0: 58024400 .word 0x58024400 80077b4: fffffc0c .word 0xfffffc0c 80077b8: ffff0007 .word 0xffff0007 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 80077bc: 4b36 ldr r3, [pc, #216] ; (8007898 ) 80077be: 6a9b ldr r3, [r3, #40] ; 0x28 80077c0: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 80077c2: 4b35 ldr r3, [pc, #212] ; (8007898 ) 80077c4: 6b1b ldr r3, [r3, #48] ; 0x30 80077c6: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80077c8: 687b ldr r3, [r7, #4] 80077ca: 6a5b ldr r3, [r3, #36] ; 0x24 80077cc: 2b01 cmp r3, #1 80077ce: d031 beq.n 8007834 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80077d0: 693b ldr r3, [r7, #16] 80077d2: f003 0203 and.w r2, r3, #3 80077d6: 687b ldr r3, [r7, #4] 80077d8: 6a9b ldr r3, [r3, #40] ; 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80077da: 429a cmp r2, r3 80077dc: d12a bne.n 8007834 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 80077de: 693b ldr r3, [r7, #16] 80077e0: 091b lsrs r3, r3, #4 80077e2: f003 023f and.w r2, r3, #63 ; 0x3f 80077e6: 687b ldr r3, [r7, #4] 80077e8: 6adb ldr r3, [r3, #44] ; 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80077ea: 429a cmp r2, r3 80077ec: d122 bne.n 8007834 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 80077ee: 68fb ldr r3, [r7, #12] 80077f0: f3c3 0208 ubfx r2, r3, #0, #9 80077f4: 687b ldr r3, [r7, #4] 80077f6: 6b1b ldr r3, [r3, #48] ; 0x30 80077f8: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 80077fa: 429a cmp r2, r3 80077fc: d11a bne.n 8007834 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 80077fe: 68fb ldr r3, [r7, #12] 8007800: 0a5b lsrs r3, r3, #9 8007802: f003 027f and.w r2, r3, #127 ; 0x7f 8007806: 687b ldr r3, [r7, #4] 8007808: 6b5b ldr r3, [r3, #52] ; 0x34 800780a: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800780c: 429a cmp r2, r3 800780e: d111 bne.n 8007834 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8007810: 68fb ldr r3, [r7, #12] 8007812: 0c1b lsrs r3, r3, #16 8007814: f003 027f and.w r2, r3, #127 ; 0x7f 8007818: 687b ldr r3, [r7, #4] 800781a: 6b9b ldr r3, [r3, #56] ; 0x38 800781c: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800781e: 429a cmp r2, r3 8007820: d108 bne.n 8007834 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 8007822: 68fb ldr r3, [r7, #12] 8007824: 0e1b lsrs r3, r3, #24 8007826: f003 027f and.w r2, r3, #127 ; 0x7f 800782a: 687b ldr r3, [r7, #4] 800782c: 6bdb ldr r3, [r3, #60] ; 0x3c 800782e: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8007830: 429a cmp r2, r3 8007832: d001 beq.n 8007838 { return HAL_ERROR; 8007834: 2301 movs r3, #1 8007836: e02b b.n 8007890 } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 8007838: 4b17 ldr r3, [pc, #92] ; (8007898 ) 800783a: 6b5b ldr r3, [r3, #52] ; 0x34 800783c: 08db lsrs r3, r3, #3 800783e: f3c3 030c ubfx r3, r3, #0, #13 8007842: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 8007844: 687b ldr r3, [r7, #4] 8007846: 6c9b ldr r3, [r3, #72] ; 0x48 8007848: 693a ldr r2, [r7, #16] 800784a: 429a cmp r2, r3 800784c: d01f beq.n 800788e { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 800784e: 4b12 ldr r3, [pc, #72] ; (8007898 ) 8007850: 6adb ldr r3, [r3, #44] ; 0x2c 8007852: 4a11 ldr r2, [pc, #68] ; (8007898 ) 8007854: f023 0301 bic.w r3, r3, #1 8007858: 62d3 str r3, [r2, #44] ; 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800785a: f7fa fd83 bl 8002364 800785e: 6278 str r0, [r7, #36] ; 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 8007860: bf00 nop 8007862: f7fa fd7f bl 8002364 8007866: 4602 mov r2, r0 8007868: 6a7b ldr r3, [r7, #36] ; 0x24 800786a: 4293 cmp r3, r2 800786c: d0f9 beq.n 8007862 { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800786e: 4b0a ldr r3, [pc, #40] ; (8007898 ) 8007870: 6b5a ldr r2, [r3, #52] ; 0x34 8007872: 4b0a ldr r3, [pc, #40] ; (800789c ) 8007874: 4013 ands r3, r2 8007876: 687a ldr r2, [r7, #4] 8007878: 6c92 ldr r2, [r2, #72] ; 0x48 800787a: 00d2 lsls r2, r2, #3 800787c: 4906 ldr r1, [pc, #24] ; (8007898 ) 800787e: 4313 orrs r3, r2 8007880: 634b str r3, [r1, #52] ; 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 8007882: 4b05 ldr r3, [pc, #20] ; (8007898 ) 8007884: 6adb ldr r3, [r3, #44] ; 0x2c 8007886: 4a04 ldr r2, [pc, #16] ; (8007898 ) 8007888: f043 0301 orr.w r3, r3, #1 800788c: 62d3 str r3, [r2, #44] ; 0x2c } } } } return HAL_OK; 800788e: 2300 movs r3, #0 } 8007890: 4618 mov r0, r3 8007892: 3730 adds r7, #48 ; 0x30 8007894: 46bd mov sp, r7 8007896: bd80 pop {r7, pc} 8007898: 58024400 .word 0x58024400 800789c: ffff0007 .word 0xffff0007 080078a0 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80078a0: b580 push {r7, lr} 80078a2: b086 sub sp, #24 80078a4: af00 add r7, sp, #0 80078a6: 6078 str r0, [r7, #4] 80078a8: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80078aa: 687b ldr r3, [r7, #4] 80078ac: 2b00 cmp r3, #0 80078ae: d101 bne.n 80078b4 { return HAL_ERROR; 80078b0: 2301 movs r3, #1 80078b2: e19c b.n 8007bee /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 80078b4: 4b8a ldr r3, [pc, #552] ; (8007ae0 ) 80078b6: 681b ldr r3, [r3, #0] 80078b8: f003 030f and.w r3, r3, #15 80078bc: 683a ldr r2, [r7, #0] 80078be: 429a cmp r2, r3 80078c0: d910 bls.n 80078e4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80078c2: 4b87 ldr r3, [pc, #540] ; (8007ae0 ) 80078c4: 681b ldr r3, [r3, #0] 80078c6: f023 020f bic.w r2, r3, #15 80078ca: 4985 ldr r1, [pc, #532] ; (8007ae0 ) 80078cc: 683b ldr r3, [r7, #0] 80078ce: 4313 orrs r3, r2 80078d0: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80078d2: 4b83 ldr r3, [pc, #524] ; (8007ae0 ) 80078d4: 681b ldr r3, [r3, #0] 80078d6: f003 030f and.w r3, r3, #15 80078da: 683a ldr r2, [r7, #0] 80078dc: 429a cmp r2, r3 80078de: d001 beq.n 80078e4 { return HAL_ERROR; 80078e0: 2301 movs r3, #1 80078e2: e184 b.n 8007bee } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 80078e4: 687b ldr r3, [r7, #4] 80078e6: 681b ldr r3, [r3, #0] 80078e8: f003 0304 and.w r3, r3, #4 80078ec: 2b00 cmp r3, #0 80078ee: d010 beq.n 8007912 { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 80078f0: 687b ldr r3, [r7, #4] 80078f2: 691a ldr r2, [r3, #16] 80078f4: 4b7b ldr r3, [pc, #492] ; (8007ae4 ) 80078f6: 699b ldr r3, [r3, #24] 80078f8: f003 0370 and.w r3, r3, #112 ; 0x70 80078fc: 429a cmp r2, r3 80078fe: d908 bls.n 8007912 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8007900: 4b78 ldr r3, [pc, #480] ; (8007ae4 ) 8007902: 699b ldr r3, [r3, #24] 8007904: f023 0270 bic.w r2, r3, #112 ; 0x70 8007908: 687b ldr r3, [r7, #4] 800790a: 691b ldr r3, [r3, #16] 800790c: 4975 ldr r1, [pc, #468] ; (8007ae4 ) 800790e: 4313 orrs r3, r2 8007910: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8007912: 687b ldr r3, [r7, #4] 8007914: 681b ldr r3, [r3, #0] 8007916: f003 0308 and.w r3, r3, #8 800791a: 2b00 cmp r3, #0 800791c: d010 beq.n 8007940 { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800791e: 687b ldr r3, [r7, #4] 8007920: 695a ldr r2, [r3, #20] 8007922: 4b70 ldr r3, [pc, #448] ; (8007ae4 ) 8007924: 69db ldr r3, [r3, #28] 8007926: f003 0370 and.w r3, r3, #112 ; 0x70 800792a: 429a cmp r2, r3 800792c: d908 bls.n 8007940 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800792e: 4b6d ldr r3, [pc, #436] ; (8007ae4 ) 8007930: 69db ldr r3, [r3, #28] 8007932: f023 0270 bic.w r2, r3, #112 ; 0x70 8007936: 687b ldr r3, [r7, #4] 8007938: 695b ldr r3, [r3, #20] 800793a: 496a ldr r1, [pc, #424] ; (8007ae4 ) 800793c: 4313 orrs r3, r2 800793e: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8007940: 687b ldr r3, [r7, #4] 8007942: 681b ldr r3, [r3, #0] 8007944: f003 0310 and.w r3, r3, #16 8007948: 2b00 cmp r3, #0 800794a: d010 beq.n 800796e { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800794c: 687b ldr r3, [r7, #4] 800794e: 699a ldr r2, [r3, #24] 8007950: 4b64 ldr r3, [pc, #400] ; (8007ae4 ) 8007952: 69db ldr r3, [r3, #28] 8007954: f403 63e0 and.w r3, r3, #1792 ; 0x700 8007958: 429a cmp r2, r3 800795a: d908 bls.n 800796e { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800795c: 4b61 ldr r3, [pc, #388] ; (8007ae4 ) 800795e: 69db ldr r3, [r3, #28] 8007960: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8007964: 687b ldr r3, [r7, #4] 8007966: 699b ldr r3, [r3, #24] 8007968: 495e ldr r1, [pc, #376] ; (8007ae4 ) 800796a: 4313 orrs r3, r2 800796c: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800796e: 687b ldr r3, [r7, #4] 8007970: 681b ldr r3, [r3, #0] 8007972: f003 0320 and.w r3, r3, #32 8007976: 2b00 cmp r3, #0 8007978: d010 beq.n 800799c { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800797a: 687b ldr r3, [r7, #4] 800797c: 69da ldr r2, [r3, #28] 800797e: 4b59 ldr r3, [pc, #356] ; (8007ae4 ) 8007980: 6a1b ldr r3, [r3, #32] 8007982: f003 0370 and.w r3, r3, #112 ; 0x70 8007986: 429a cmp r2, r3 8007988: d908 bls.n 800799c { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800798a: 4b56 ldr r3, [pc, #344] ; (8007ae4 ) 800798c: 6a1b ldr r3, [r3, #32] 800798e: f023 0270 bic.w r2, r3, #112 ; 0x70 8007992: 687b ldr r3, [r7, #4] 8007994: 69db ldr r3, [r3, #28] 8007996: 4953 ldr r1, [pc, #332] ; (8007ae4 ) 8007998: 4313 orrs r3, r2 800799a: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800799c: 687b ldr r3, [r7, #4] 800799e: 681b ldr r3, [r3, #0] 80079a0: f003 0302 and.w r3, r3, #2 80079a4: 2b00 cmp r3, #0 80079a6: d010 beq.n 80079ca { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 80079a8: 687b ldr r3, [r7, #4] 80079aa: 68da ldr r2, [r3, #12] 80079ac: 4b4d ldr r3, [pc, #308] ; (8007ae4 ) 80079ae: 699b ldr r3, [r3, #24] 80079b0: f003 030f and.w r3, r3, #15 80079b4: 429a cmp r2, r3 80079b6: d908 bls.n 80079ca { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80079b8: 4b4a ldr r3, [pc, #296] ; (8007ae4 ) 80079ba: 699b ldr r3, [r3, #24] 80079bc: f023 020f bic.w r2, r3, #15 80079c0: 687b ldr r3, [r7, #4] 80079c2: 68db ldr r3, [r3, #12] 80079c4: 4947 ldr r1, [pc, #284] ; (8007ae4 ) 80079c6: 4313 orrs r3, r2 80079c8: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80079ca: 687b ldr r3, [r7, #4] 80079cc: 681b ldr r3, [r3, #0] 80079ce: f003 0301 and.w r3, r3, #1 80079d2: 2b00 cmp r3, #0 80079d4: d055 beq.n 8007a82 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 80079d6: 4b43 ldr r3, [pc, #268] ; (8007ae4 ) 80079d8: 699b ldr r3, [r3, #24] 80079da: f423 6270 bic.w r2, r3, #3840 ; 0xf00 80079de: 687b ldr r3, [r7, #4] 80079e0: 689b ldr r3, [r3, #8] 80079e2: 4940 ldr r1, [pc, #256] ; (8007ae4 ) 80079e4: 4313 orrs r3, r2 80079e6: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80079e8: 687b ldr r3, [r7, #4] 80079ea: 685b ldr r3, [r3, #4] 80079ec: 2b02 cmp r3, #2 80079ee: d107 bne.n 8007a00 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80079f0: 4b3c ldr r3, [pc, #240] ; (8007ae4 ) 80079f2: 681b ldr r3, [r3, #0] 80079f4: f403 3300 and.w r3, r3, #131072 ; 0x20000 80079f8: 2b00 cmp r3, #0 80079fa: d121 bne.n 8007a40 { return HAL_ERROR; 80079fc: 2301 movs r3, #1 80079fe: e0f6 b.n 8007bee } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8007a00: 687b ldr r3, [r7, #4] 8007a02: 685b ldr r3, [r3, #4] 8007a04: 2b03 cmp r3, #3 8007a06: d107 bne.n 8007a18 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8007a08: 4b36 ldr r3, [pc, #216] ; (8007ae4 ) 8007a0a: 681b ldr r3, [r3, #0] 8007a0c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8007a10: 2b00 cmp r3, #0 8007a12: d115 bne.n 8007a40 { return HAL_ERROR; 8007a14: 2301 movs r3, #1 8007a16: e0ea b.n 8007bee } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 8007a18: 687b ldr r3, [r7, #4] 8007a1a: 685b ldr r3, [r3, #4] 8007a1c: 2b01 cmp r3, #1 8007a1e: d107 bne.n 8007a30 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8007a20: 4b30 ldr r3, [pc, #192] ; (8007ae4 ) 8007a22: 681b ldr r3, [r3, #0] 8007a24: f403 7380 and.w r3, r3, #256 ; 0x100 8007a28: 2b00 cmp r3, #0 8007a2a: d109 bne.n 8007a40 { return HAL_ERROR; 8007a2c: 2301 movs r3, #1 8007a2e: e0de b.n 8007bee } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8007a30: 4b2c ldr r3, [pc, #176] ; (8007ae4 ) 8007a32: 681b ldr r3, [r3, #0] 8007a34: f003 0304 and.w r3, r3, #4 8007a38: 2b00 cmp r3, #0 8007a3a: d101 bne.n 8007a40 { return HAL_ERROR; 8007a3c: 2301 movs r3, #1 8007a3e: e0d6 b.n 8007bee } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8007a40: 4b28 ldr r3, [pc, #160] ; (8007ae4 ) 8007a42: 691b ldr r3, [r3, #16] 8007a44: f023 0207 bic.w r2, r3, #7 8007a48: 687b ldr r3, [r7, #4] 8007a4a: 685b ldr r3, [r3, #4] 8007a4c: 4925 ldr r1, [pc, #148] ; (8007ae4 ) 8007a4e: 4313 orrs r3, r2 8007a50: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007a52: f7fa fc87 bl 8002364 8007a56: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8007a58: e00a b.n 8007a70 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8007a5a: f7fa fc83 bl 8002364 8007a5e: 4602 mov r2, r0 8007a60: 697b ldr r3, [r7, #20] 8007a62: 1ad3 subs r3, r2, r3 8007a64: f241 3288 movw r2, #5000 ; 0x1388 8007a68: 4293 cmp r3, r2 8007a6a: d901 bls.n 8007a70 { return HAL_TIMEOUT; 8007a6c: 2303 movs r3, #3 8007a6e: e0be b.n 8007bee while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8007a70: 4b1c ldr r3, [pc, #112] ; (8007ae4 ) 8007a72: 691b ldr r3, [r3, #16] 8007a74: f003 0238 and.w r2, r3, #56 ; 0x38 8007a78: 687b ldr r3, [r7, #4] 8007a7a: 685b ldr r3, [r3, #4] 8007a7c: 00db lsls r3, r3, #3 8007a7e: 429a cmp r2, r3 8007a80: d1eb bne.n 8007a5a } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8007a82: 687b ldr r3, [r7, #4] 8007a84: 681b ldr r3, [r3, #0] 8007a86: f003 0302 and.w r3, r3, #2 8007a8a: 2b00 cmp r3, #0 8007a8c: d010 beq.n 8007ab0 { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 8007a8e: 687b ldr r3, [r7, #4] 8007a90: 68da ldr r2, [r3, #12] 8007a92: 4b14 ldr r3, [pc, #80] ; (8007ae4 ) 8007a94: 699b ldr r3, [r3, #24] 8007a96: f003 030f and.w r3, r3, #15 8007a9a: 429a cmp r2, r3 8007a9c: d208 bcs.n 8007ab0 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8007a9e: 4b11 ldr r3, [pc, #68] ; (8007ae4 ) 8007aa0: 699b ldr r3, [r3, #24] 8007aa2: f023 020f bic.w r2, r3, #15 8007aa6: 687b ldr r3, [r7, #4] 8007aa8: 68db ldr r3, [r3, #12] 8007aaa: 490e ldr r1, [pc, #56] ; (8007ae4 ) 8007aac: 4313 orrs r3, r2 8007aae: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8007ab0: 4b0b ldr r3, [pc, #44] ; (8007ae0 ) 8007ab2: 681b ldr r3, [r3, #0] 8007ab4: f003 030f and.w r3, r3, #15 8007ab8: 683a ldr r2, [r7, #0] 8007aba: 429a cmp r2, r3 8007abc: d214 bcs.n 8007ae8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8007abe: 4b08 ldr r3, [pc, #32] ; (8007ae0 ) 8007ac0: 681b ldr r3, [r3, #0] 8007ac2: f023 020f bic.w r2, r3, #15 8007ac6: 4906 ldr r1, [pc, #24] ; (8007ae0 ) 8007ac8: 683b ldr r3, [r7, #0] 8007aca: 4313 orrs r3, r2 8007acc: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8007ace: 4b04 ldr r3, [pc, #16] ; (8007ae0 ) 8007ad0: 681b ldr r3, [r3, #0] 8007ad2: f003 030f and.w r3, r3, #15 8007ad6: 683a ldr r2, [r7, #0] 8007ad8: 429a cmp r2, r3 8007ada: d005 beq.n 8007ae8 { return HAL_ERROR; 8007adc: 2301 movs r3, #1 8007ade: e086 b.n 8007bee 8007ae0: 52002000 .word 0x52002000 8007ae4: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8007ae8: 687b ldr r3, [r7, #4] 8007aea: 681b ldr r3, [r3, #0] 8007aec: f003 0304 and.w r3, r3, #4 8007af0: 2b00 cmp r3, #0 8007af2: d010 beq.n 8007b16 { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8007af4: 687b ldr r3, [r7, #4] 8007af6: 691a ldr r2, [r3, #16] 8007af8: 4b3f ldr r3, [pc, #252] ; (8007bf8 ) 8007afa: 699b ldr r3, [r3, #24] 8007afc: f003 0370 and.w r3, r3, #112 ; 0x70 8007b00: 429a cmp r2, r3 8007b02: d208 bcs.n 8007b16 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8007b04: 4b3c ldr r3, [pc, #240] ; (8007bf8 ) 8007b06: 699b ldr r3, [r3, #24] 8007b08: f023 0270 bic.w r2, r3, #112 ; 0x70 8007b0c: 687b ldr r3, [r7, #4] 8007b0e: 691b ldr r3, [r3, #16] 8007b10: 4939 ldr r1, [pc, #228] ; (8007bf8 ) 8007b12: 4313 orrs r3, r2 8007b14: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8007b16: 687b ldr r3, [r7, #4] 8007b18: 681b ldr r3, [r3, #0] 8007b1a: f003 0308 and.w r3, r3, #8 8007b1e: 2b00 cmp r3, #0 8007b20: d010 beq.n 8007b44 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 8007b22: 687b ldr r3, [r7, #4] 8007b24: 695a ldr r2, [r3, #20] 8007b26: 4b34 ldr r3, [pc, #208] ; (8007bf8 ) 8007b28: 69db ldr r3, [r3, #28] 8007b2a: f003 0370 and.w r3, r3, #112 ; 0x70 8007b2e: 429a cmp r2, r3 8007b30: d208 bcs.n 8007b44 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8007b32: 4b31 ldr r3, [pc, #196] ; (8007bf8 ) 8007b34: 69db ldr r3, [r3, #28] 8007b36: f023 0270 bic.w r2, r3, #112 ; 0x70 8007b3a: 687b ldr r3, [r7, #4] 8007b3c: 695b ldr r3, [r3, #20] 8007b3e: 492e ldr r1, [pc, #184] ; (8007bf8 ) 8007b40: 4313 orrs r3, r2 8007b42: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8007b44: 687b ldr r3, [r7, #4] 8007b46: 681b ldr r3, [r3, #0] 8007b48: f003 0310 and.w r3, r3, #16 8007b4c: 2b00 cmp r3, #0 8007b4e: d010 beq.n 8007b72 { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 8007b50: 687b ldr r3, [r7, #4] 8007b52: 699a ldr r2, [r3, #24] 8007b54: 4b28 ldr r3, [pc, #160] ; (8007bf8 ) 8007b56: 69db ldr r3, [r3, #28] 8007b58: f403 63e0 and.w r3, r3, #1792 ; 0x700 8007b5c: 429a cmp r2, r3 8007b5e: d208 bcs.n 8007b72 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8007b60: 4b25 ldr r3, [pc, #148] ; (8007bf8 ) 8007b62: 69db ldr r3, [r3, #28] 8007b64: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8007b68: 687b ldr r3, [r7, #4] 8007b6a: 699b ldr r3, [r3, #24] 8007b6c: 4922 ldr r1, [pc, #136] ; (8007bf8 ) 8007b6e: 4313 orrs r3, r2 8007b70: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8007b72: 687b ldr r3, [r7, #4] 8007b74: 681b ldr r3, [r3, #0] 8007b76: f003 0320 and.w r3, r3, #32 8007b7a: 2b00 cmp r3, #0 8007b7c: d010 beq.n 8007ba0 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 8007b7e: 687b ldr r3, [r7, #4] 8007b80: 69da ldr r2, [r3, #28] 8007b82: 4b1d ldr r3, [pc, #116] ; (8007bf8 ) 8007b84: 6a1b ldr r3, [r3, #32] 8007b86: f003 0370 and.w r3, r3, #112 ; 0x70 8007b8a: 429a cmp r2, r3 8007b8c: d208 bcs.n 8007ba0 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 8007b8e: 4b1a ldr r3, [pc, #104] ; (8007bf8 ) 8007b90: 6a1b ldr r3, [r3, #32] 8007b92: f023 0270 bic.w r2, r3, #112 ; 0x70 8007b96: 687b ldr r3, [r7, #4] 8007b98: 69db ldr r3, [r3, #28] 8007b9a: 4917 ldr r1, [pc, #92] ; (8007bf8 ) 8007b9c: 4313 orrs r3, r2 8007b9e: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8007ba0: f000 f834 bl 8007c0c 8007ba4: 4602 mov r2, r0 8007ba6: 4b14 ldr r3, [pc, #80] ; (8007bf8 ) 8007ba8: 699b ldr r3, [r3, #24] 8007baa: 0a1b lsrs r3, r3, #8 8007bac: f003 030f and.w r3, r3, #15 8007bb0: 4912 ldr r1, [pc, #72] ; (8007bfc ) 8007bb2: 5ccb ldrb r3, [r1, r3] 8007bb4: f003 031f and.w r3, r3, #31 8007bb8: fa22 f303 lsr.w r3, r2, r3 8007bbc: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007bbe: 4b0e ldr r3, [pc, #56] ; (8007bf8 ) 8007bc0: 699b ldr r3, [r3, #24] 8007bc2: f003 030f and.w r3, r3, #15 8007bc6: 4a0d ldr r2, [pc, #52] ; (8007bfc ) 8007bc8: 5cd3 ldrb r3, [r2, r3] 8007bca: f003 031f and.w r3, r3, #31 8007bce: 693a ldr r2, [r7, #16] 8007bd0: fa22 f303 lsr.w r3, r2, r3 8007bd4: 4a0a ldr r2, [pc, #40] ; (8007c00 ) 8007bd6: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8007bd8: 4a0a ldr r2, [pc, #40] ; (8007c04 ) 8007bda: 693b ldr r3, [r7, #16] 8007bdc: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 8007bde: 4b0a ldr r3, [pc, #40] ; (8007c08 ) 8007be0: 681b ldr r3, [r3, #0] 8007be2: 4618 mov r0, r3 8007be4: f7f9 ffdc bl 8001ba0 8007be8: 4603 mov r3, r0 8007bea: 73fb strb r3, [r7, #15] return halstatus; 8007bec: 7bfb ldrb r3, [r7, #15] } 8007bee: 4618 mov r0, r3 8007bf0: 3718 adds r7, #24 8007bf2: 46bd mov sp, r7 8007bf4: bd80 pop {r7, pc} 8007bf6: bf00 nop 8007bf8: 58024400 .word 0x58024400 8007bfc: 08026b40 .word 0x08026b40 8007c00: 24000018 .word 0x24000018 8007c04: 24000014 .word 0x24000014 8007c08: 2400001c .word 0x2400001c 08007c0c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8007c0c: b480 push {r7} 8007c0e: b089 sub sp, #36 ; 0x24 8007c10: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8007c12: 4bb3 ldr r3, [pc, #716] ; (8007ee0 ) 8007c14: 691b ldr r3, [r3, #16] 8007c16: f003 0338 and.w r3, r3, #56 ; 0x38 8007c1a: 2b18 cmp r3, #24 8007c1c: f200 8155 bhi.w 8007eca 8007c20: a201 add r2, pc, #4 ; (adr r2, 8007c28 ) 8007c22: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007c26: bf00 nop 8007c28: 08007c8d .word 0x08007c8d 8007c2c: 08007ecb .word 0x08007ecb 8007c30: 08007ecb .word 0x08007ecb 8007c34: 08007ecb .word 0x08007ecb 8007c38: 08007ecb .word 0x08007ecb 8007c3c: 08007ecb .word 0x08007ecb 8007c40: 08007ecb .word 0x08007ecb 8007c44: 08007ecb .word 0x08007ecb 8007c48: 08007cb3 .word 0x08007cb3 8007c4c: 08007ecb .word 0x08007ecb 8007c50: 08007ecb .word 0x08007ecb 8007c54: 08007ecb .word 0x08007ecb 8007c58: 08007ecb .word 0x08007ecb 8007c5c: 08007ecb .word 0x08007ecb 8007c60: 08007ecb .word 0x08007ecb 8007c64: 08007ecb .word 0x08007ecb 8007c68: 08007cb9 .word 0x08007cb9 8007c6c: 08007ecb .word 0x08007ecb 8007c70: 08007ecb .word 0x08007ecb 8007c74: 08007ecb .word 0x08007ecb 8007c78: 08007ecb .word 0x08007ecb 8007c7c: 08007ecb .word 0x08007ecb 8007c80: 08007ecb .word 0x08007ecb 8007c84: 08007ecb .word 0x08007ecb 8007c88: 08007cbf .word 0x08007cbf { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007c8c: 4b94 ldr r3, [pc, #592] ; (8007ee0 ) 8007c8e: 681b ldr r3, [r3, #0] 8007c90: f003 0320 and.w r3, r3, #32 8007c94: 2b00 cmp r3, #0 8007c96: d009 beq.n 8007cac { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007c98: 4b91 ldr r3, [pc, #580] ; (8007ee0 ) 8007c9a: 681b ldr r3, [r3, #0] 8007c9c: 08db lsrs r3, r3, #3 8007c9e: f003 0303 and.w r3, r3, #3 8007ca2: 4a90 ldr r2, [pc, #576] ; (8007ee4 ) 8007ca4: fa22 f303 lsr.w r3, r2, r3 8007ca8: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 8007caa: e111 b.n 8007ed0 sysclockfreq = (uint32_t) HSI_VALUE; 8007cac: 4b8d ldr r3, [pc, #564] ; (8007ee4 ) 8007cae: 61bb str r3, [r7, #24] break; 8007cb0: e10e b.n 8007ed0 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 8007cb2: 4b8d ldr r3, [pc, #564] ; (8007ee8 ) 8007cb4: 61bb str r3, [r7, #24] break; 8007cb6: e10b b.n 8007ed0 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8007cb8: 4b8c ldr r3, [pc, #560] ; (8007eec ) 8007cba: 61bb str r3, [r7, #24] break; 8007cbc: e108 b.n 8007ed0 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8007cbe: 4b88 ldr r3, [pc, #544] ; (8007ee0 ) 8007cc0: 6a9b ldr r3, [r3, #40] ; 0x28 8007cc2: f003 0303 and.w r3, r3, #3 8007cc6: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 8007cc8: 4b85 ldr r3, [pc, #532] ; (8007ee0 ) 8007cca: 6a9b ldr r3, [r3, #40] ; 0x28 8007ccc: 091b lsrs r3, r3, #4 8007cce: f003 033f and.w r3, r3, #63 ; 0x3f 8007cd2: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 8007cd4: 4b82 ldr r3, [pc, #520] ; (8007ee0 ) 8007cd6: 6adb ldr r3, [r3, #44] ; 0x2c 8007cd8: f003 0301 and.w r3, r3, #1 8007cdc: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 8007cde: 4b80 ldr r3, [pc, #512] ; (8007ee0 ) 8007ce0: 6b5b ldr r3, [r3, #52] ; 0x34 8007ce2: 08db lsrs r3, r3, #3 8007ce4: f3c3 030c ubfx r3, r3, #0, #13 8007ce8: 68fa ldr r2, [r7, #12] 8007cea: fb02 f303 mul.w r3, r2, r3 8007cee: ee07 3a90 vmov s15, r3 8007cf2: eef8 7a67 vcvt.f32.u32 s15, s15 8007cf6: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 8007cfa: 693b ldr r3, [r7, #16] 8007cfc: 2b00 cmp r3, #0 8007cfe: f000 80e1 beq.w 8007ec4 8007d02: 697b ldr r3, [r7, #20] 8007d04: 2b02 cmp r3, #2 8007d06: f000 8083 beq.w 8007e10 8007d0a: 697b ldr r3, [r7, #20] 8007d0c: 2b02 cmp r3, #2 8007d0e: f200 80a1 bhi.w 8007e54 8007d12: 697b ldr r3, [r7, #20] 8007d14: 2b00 cmp r3, #0 8007d16: d003 beq.n 8007d20 8007d18: 697b ldr r3, [r7, #20] 8007d1a: 2b01 cmp r3, #1 8007d1c: d056 beq.n 8007dcc 8007d1e: e099 b.n 8007e54 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007d20: 4b6f ldr r3, [pc, #444] ; (8007ee0 ) 8007d22: 681b ldr r3, [r3, #0] 8007d24: f003 0320 and.w r3, r3, #32 8007d28: 2b00 cmp r3, #0 8007d2a: d02d beq.n 8007d88 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007d2c: 4b6c ldr r3, [pc, #432] ; (8007ee0 ) 8007d2e: 681b ldr r3, [r3, #0] 8007d30: 08db lsrs r3, r3, #3 8007d32: f003 0303 and.w r3, r3, #3 8007d36: 4a6b ldr r2, [pc, #428] ; (8007ee4 ) 8007d38: fa22 f303 lsr.w r3, r2, r3 8007d3c: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007d3e: 687b ldr r3, [r7, #4] 8007d40: ee07 3a90 vmov s15, r3 8007d44: eef8 6a67 vcvt.f32.u32 s13, s15 8007d48: 693b ldr r3, [r7, #16] 8007d4a: ee07 3a90 vmov s15, r3 8007d4e: eef8 7a67 vcvt.f32.u32 s15, s15 8007d52: ee86 7aa7 vdiv.f32 s14, s13, s15 8007d56: 4b62 ldr r3, [pc, #392] ; (8007ee0 ) 8007d58: 6b1b ldr r3, [r3, #48] ; 0x30 8007d5a: f3c3 0308 ubfx r3, r3, #0, #9 8007d5e: ee07 3a90 vmov s15, r3 8007d62: eef8 6a67 vcvt.f32.u32 s13, s15 8007d66: ed97 6a02 vldr s12, [r7, #8] 8007d6a: eddf 5a61 vldr s11, [pc, #388] ; 8007ef0 8007d6e: eec6 7a25 vdiv.f32 s15, s12, s11 8007d72: ee76 7aa7 vadd.f32 s15, s13, s15 8007d76: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8007d7a: ee77 7aa6 vadd.f32 s15, s15, s13 8007d7e: ee67 7a27 vmul.f32 s15, s14, s15 8007d82: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 8007d86: e087 b.n 8007e98 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007d88: 693b ldr r3, [r7, #16] 8007d8a: ee07 3a90 vmov s15, r3 8007d8e: eef8 7a67 vcvt.f32.u32 s15, s15 8007d92: eddf 6a58 vldr s13, [pc, #352] ; 8007ef4 8007d96: ee86 7aa7 vdiv.f32 s14, s13, s15 8007d9a: 4b51 ldr r3, [pc, #324] ; (8007ee0 ) 8007d9c: 6b1b ldr r3, [r3, #48] ; 0x30 8007d9e: f3c3 0308 ubfx r3, r3, #0, #9 8007da2: ee07 3a90 vmov s15, r3 8007da6: eef8 6a67 vcvt.f32.u32 s13, s15 8007daa: ed97 6a02 vldr s12, [r7, #8] 8007dae: eddf 5a50 vldr s11, [pc, #320] ; 8007ef0 8007db2: eec6 7a25 vdiv.f32 s15, s12, s11 8007db6: ee76 7aa7 vadd.f32 s15, s13, s15 8007dba: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8007dbe: ee77 7aa6 vadd.f32 s15, s15, s13 8007dc2: ee67 7a27 vmul.f32 s15, s14, s15 8007dc6: edc7 7a07 vstr s15, [r7, #28] break; 8007dca: e065 b.n 8007e98 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007dcc: 693b ldr r3, [r7, #16] 8007dce: ee07 3a90 vmov s15, r3 8007dd2: eef8 7a67 vcvt.f32.u32 s15, s15 8007dd6: eddf 6a48 vldr s13, [pc, #288] ; 8007ef8 8007dda: ee86 7aa7 vdiv.f32 s14, s13, s15 8007dde: 4b40 ldr r3, [pc, #256] ; (8007ee0 ) 8007de0: 6b1b ldr r3, [r3, #48] ; 0x30 8007de2: f3c3 0308 ubfx r3, r3, #0, #9 8007de6: ee07 3a90 vmov s15, r3 8007dea: eef8 6a67 vcvt.f32.u32 s13, s15 8007dee: ed97 6a02 vldr s12, [r7, #8] 8007df2: eddf 5a3f vldr s11, [pc, #252] ; 8007ef0 8007df6: eec6 7a25 vdiv.f32 s15, s12, s11 8007dfa: ee76 7aa7 vadd.f32 s15, s13, s15 8007dfe: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8007e02: ee77 7aa6 vadd.f32 s15, s15, s13 8007e06: ee67 7a27 vmul.f32 s15, s14, s15 8007e0a: edc7 7a07 vstr s15, [r7, #28] break; 8007e0e: e043 b.n 8007e98 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007e10: 693b ldr r3, [r7, #16] 8007e12: ee07 3a90 vmov s15, r3 8007e16: eef8 7a67 vcvt.f32.u32 s15, s15 8007e1a: eddf 6a38 vldr s13, [pc, #224] ; 8007efc 8007e1e: ee86 7aa7 vdiv.f32 s14, s13, s15 8007e22: 4b2f ldr r3, [pc, #188] ; (8007ee0 ) 8007e24: 6b1b ldr r3, [r3, #48] ; 0x30 8007e26: f3c3 0308 ubfx r3, r3, #0, #9 8007e2a: ee07 3a90 vmov s15, r3 8007e2e: eef8 6a67 vcvt.f32.u32 s13, s15 8007e32: ed97 6a02 vldr s12, [r7, #8] 8007e36: eddf 5a2e vldr s11, [pc, #184] ; 8007ef0 8007e3a: eec6 7a25 vdiv.f32 s15, s12, s11 8007e3e: ee76 7aa7 vadd.f32 s15, s13, s15 8007e42: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8007e46: ee77 7aa6 vadd.f32 s15, s15, s13 8007e4a: ee67 7a27 vmul.f32 s15, s14, s15 8007e4e: edc7 7a07 vstr s15, [r7, #28] break; 8007e52: e021 b.n 8007e98 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007e54: 693b ldr r3, [r7, #16] 8007e56: ee07 3a90 vmov s15, r3 8007e5a: eef8 7a67 vcvt.f32.u32 s15, s15 8007e5e: eddf 6a26 vldr s13, [pc, #152] ; 8007ef8 8007e62: ee86 7aa7 vdiv.f32 s14, s13, s15 8007e66: 4b1e ldr r3, [pc, #120] ; (8007ee0 ) 8007e68: 6b1b ldr r3, [r3, #48] ; 0x30 8007e6a: f3c3 0308 ubfx r3, r3, #0, #9 8007e6e: ee07 3a90 vmov s15, r3 8007e72: eef8 6a67 vcvt.f32.u32 s13, s15 8007e76: ed97 6a02 vldr s12, [r7, #8] 8007e7a: eddf 5a1d vldr s11, [pc, #116] ; 8007ef0 8007e7e: eec6 7a25 vdiv.f32 s15, s12, s11 8007e82: ee76 7aa7 vadd.f32 s15, s13, s15 8007e86: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8007e8a: ee77 7aa6 vadd.f32 s15, s15, s13 8007e8e: ee67 7a27 vmul.f32 s15, s14, s15 8007e92: edc7 7a07 vstr s15, [r7, #28] break; 8007e96: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 8007e98: 4b11 ldr r3, [pc, #68] ; (8007ee0 ) 8007e9a: 6b1b ldr r3, [r3, #48] ; 0x30 8007e9c: 0a5b lsrs r3, r3, #9 8007e9e: f003 037f and.w r3, r3, #127 ; 0x7f 8007ea2: 3301 adds r3, #1 8007ea4: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 8007ea6: 683b ldr r3, [r7, #0] 8007ea8: ee07 3a90 vmov s15, r3 8007eac: eeb8 7a67 vcvt.f32.u32 s14, s15 8007eb0: edd7 6a07 vldr s13, [r7, #28] 8007eb4: eec6 7a87 vdiv.f32 s15, s13, s14 8007eb8: eefc 7ae7 vcvt.u32.f32 s15, s15 8007ebc: ee17 3a90 vmov r3, s15 8007ec0: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 8007ec2: e005 b.n 8007ed0 sysclockfreq = 0U; 8007ec4: 2300 movs r3, #0 8007ec6: 61bb str r3, [r7, #24] break; 8007ec8: e002 b.n 8007ed0 default: sysclockfreq = CSI_VALUE; 8007eca: 4b07 ldr r3, [pc, #28] ; (8007ee8 ) 8007ecc: 61bb str r3, [r7, #24] break; 8007ece: bf00 nop } return sysclockfreq; 8007ed0: 69bb ldr r3, [r7, #24] } 8007ed2: 4618 mov r0, r3 8007ed4: 3724 adds r7, #36 ; 0x24 8007ed6: 46bd mov sp, r7 8007ed8: f85d 7b04 ldr.w r7, [sp], #4 8007edc: 4770 bx lr 8007ede: bf00 nop 8007ee0: 58024400 .word 0x58024400 8007ee4: 03d09000 .word 0x03d09000 8007ee8: 003d0900 .word 0x003d0900 8007eec: 017d7840 .word 0x017d7840 8007ef0: 46000000 .word 0x46000000 8007ef4: 4c742400 .word 0x4c742400 8007ef8: 4a742400 .word 0x4a742400 8007efc: 4bbebc20 .word 0x4bbebc20 08007f00 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8007f00: b580 push {r7, lr} 8007f02: b082 sub sp, #8 8007f04: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007f06: f7ff fe81 bl 8007c0c 8007f0a: 4602 mov r2, r0 8007f0c: 4b10 ldr r3, [pc, #64] ; (8007f50 ) 8007f0e: 699b ldr r3, [r3, #24] 8007f10: 0a1b lsrs r3, r3, #8 8007f12: f003 030f and.w r3, r3, #15 8007f16: 490f ldr r1, [pc, #60] ; (8007f54 ) 8007f18: 5ccb ldrb r3, [r1, r3] 8007f1a: f003 031f and.w r3, r3, #31 8007f1e: fa22 f303 lsr.w r3, r2, r3 8007f22: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007f24: 4b0a ldr r3, [pc, #40] ; (8007f50 ) 8007f26: 699b ldr r3, [r3, #24] 8007f28: f003 030f and.w r3, r3, #15 8007f2c: 4a09 ldr r2, [pc, #36] ; (8007f54 ) 8007f2e: 5cd3 ldrb r3, [r2, r3] 8007f30: f003 031f and.w r3, r3, #31 8007f34: 687a ldr r2, [r7, #4] 8007f36: fa22 f303 lsr.w r3, r2, r3 8007f3a: 4a07 ldr r2, [pc, #28] ; (8007f58 ) 8007f3c: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8007f3e: 4a07 ldr r2, [pc, #28] ; (8007f5c ) 8007f40: 687b ldr r3, [r7, #4] 8007f42: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 8007f44: 4b04 ldr r3, [pc, #16] ; (8007f58 ) 8007f46: 681b ldr r3, [r3, #0] } 8007f48: 4618 mov r0, r3 8007f4a: 3708 adds r7, #8 8007f4c: 46bd mov sp, r7 8007f4e: bd80 pop {r7, pc} 8007f50: 58024400 .word 0x58024400 8007f54: 08026b40 .word 0x08026b40 8007f58: 24000018 .word 0x24000018 8007f5c: 24000014 .word 0x24000014 08007f60 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8007f60: b580 push {r7, lr} 8007f62: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 8007f64: f7ff ffcc bl 8007f00 8007f68: 4602 mov r2, r0 8007f6a: 4b06 ldr r3, [pc, #24] ; (8007f84 ) 8007f6c: 69db ldr r3, [r3, #28] 8007f6e: 091b lsrs r3, r3, #4 8007f70: f003 0307 and.w r3, r3, #7 8007f74: 4904 ldr r1, [pc, #16] ; (8007f88 ) 8007f76: 5ccb ldrb r3, [r1, r3] 8007f78: f003 031f and.w r3, r3, #31 8007f7c: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 8007f80: 4618 mov r0, r3 8007f82: bd80 pop {r7, pc} 8007f84: 58024400 .word 0x58024400 8007f88: 08026b40 .word 0x08026b40 08007f8c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8007f8c: b580 push {r7, lr} 8007f8e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 8007f90: f7ff ffb6 bl 8007f00 8007f94: 4602 mov r2, r0 8007f96: 4b06 ldr r3, [pc, #24] ; (8007fb0 ) 8007f98: 69db ldr r3, [r3, #28] 8007f9a: 0a1b lsrs r3, r3, #8 8007f9c: f003 0307 and.w r3, r3, #7 8007fa0: 4904 ldr r1, [pc, #16] ; (8007fb4 ) 8007fa2: 5ccb ldrb r3, [r1, r3] 8007fa4: f003 031f and.w r3, r3, #31 8007fa8: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 8007fac: 4618 mov r0, r3 8007fae: bd80 pop {r7, pc} 8007fb0: 58024400 .word 0x58024400 8007fb4: 08026b40 .word 0x08026b40 08007fb8 : * will be configured. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 8007fb8: b480 push {r7} 8007fba: b083 sub sp, #12 8007fbc: af00 add r7, sp, #0 8007fbe: 6078 str r0, [r7, #4] 8007fc0: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 8007fc2: 687b ldr r3, [r7, #4] 8007fc4: 223f movs r2, #63 ; 0x3f 8007fc6: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8007fc8: 4b1a ldr r3, [pc, #104] ; (8008034 ) 8007fca: 691b ldr r3, [r3, #16] 8007fcc: f003 0207 and.w r2, r3, #7 8007fd0: 687b ldr r3, [r7, #4] 8007fd2: 605a str r2, [r3, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 8007fd4: 4b17 ldr r3, [pc, #92] ; (8008034 ) 8007fd6: 699b ldr r3, [r3, #24] 8007fd8: f403 6270 and.w r2, r3, #3840 ; 0xf00 8007fdc: 687b ldr r3, [r7, #4] 8007fde: 609a str r2, [r3, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 8007fe0: 4b14 ldr r3, [pc, #80] ; (8008034 ) 8007fe2: 699b ldr r3, [r3, #24] 8007fe4: f003 020f and.w r2, r3, #15 8007fe8: 687b ldr r3, [r7, #4] 8007fea: 60da str r2, [r3, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 8007fec: 4b11 ldr r3, [pc, #68] ; (8008034 ) 8007fee: 699b ldr r3, [r3, #24] 8007ff0: f003 0270 and.w r2, r3, #112 ; 0x70 8007ff4: 687b ldr r3, [r7, #4] 8007ff6: 611a str r2, [r3, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 8007ff8: 4b0e ldr r3, [pc, #56] ; (8008034 ) 8007ffa: 69db ldr r3, [r3, #28] 8007ffc: f003 0270 and.w r2, r3, #112 ; 0x70 8008000: 687b ldr r3, [r7, #4] 8008002: 615a str r2, [r3, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 8008004: 4b0b ldr r3, [pc, #44] ; (8008034 ) 8008006: 69db ldr r3, [r3, #28] 8008008: f403 62e0 and.w r2, r3, #1792 ; 0x700 800800c: 687b ldr r3, [r7, #4] 800800e: 619a str r2, [r3, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 8008010: 4b08 ldr r3, [pc, #32] ; (8008034 ) 8008012: 6a1b ldr r3, [r3, #32] 8008014: f003 0270 and.w r2, r3, #112 ; 0x70 8008018: 687b ldr r3, [r7, #4] 800801a: 61da str r2, [r3, #28] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 800801c: 4b06 ldr r3, [pc, #24] ; (8008038 ) 800801e: 681b ldr r3, [r3, #0] 8008020: f003 020f and.w r2, r3, #15 8008024: 683b ldr r3, [r7, #0] 8008026: 601a str r2, [r3, #0] } 8008028: bf00 nop 800802a: 370c adds r7, #12 800802c: 46bd mov sp, r7 800802e: f85d 7b04 ldr.w r7, [sp], #4 8008032: 4770 bx lr 8008034: 58024400 .word 0x58024400 8008038: 52002000 .word 0x52002000 0800803c : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800803c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8008040: b0c6 sub sp, #280 ; 0x118 8008042: af00 add r7, sp, #0 8008044: f8c7 0104 str.w r0, [r7, #260] ; 0x104 uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8008048: 2300 movs r3, #0 800804a: f887 3117 strb.w r3, [r7, #279] ; 0x117 HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800804e: 2300 movs r3, #0 8008050: f887 3116 strb.w r3, [r7, #278] ; 0x116 /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8008054: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008058: e9d3 2300 ldrd r2, r3, [r3] 800805c: f002 6400 and.w r4, r2, #134217728 ; 0x8000000 8008060: 2500 movs r5, #0 8008062: ea54 0305 orrs.w r3, r4, r5 8008066: d049 beq.n 80080fc { switch (PeriphClkInit->SpdifrxClockSelection) 8008068: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800806c: 6e5b ldr r3, [r3, #100] ; 0x64 800806e: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8008072: d02f beq.n 80080d4 8008074: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8008078: d828 bhi.n 80080cc 800807a: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 800807e: d01a beq.n 80080b6 8008080: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8008084: d822 bhi.n 80080cc 8008086: 2b00 cmp r3, #0 8008088: d003 beq.n 8008092 800808a: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800808e: d007 beq.n 80080a0 8008090: e01c b.n 80080cc { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008092: 4bab ldr r3, [pc, #684] ; (8008340 ) 8008094: 6adb ldr r3, [r3, #44] ; 0x2c 8008096: 4aaa ldr r2, [pc, #680] ; (8008340 ) 8008098: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800809c: 62d3 str r3, [r2, #44] ; 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800809e: e01a b.n 80080d6 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 80080a0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80080a4: 3308 adds r3, #8 80080a6: 2102 movs r1, #2 80080a8: 4618 mov r0, r3 80080aa: f002 fa49 bl 800a540 80080ae: 4603 mov r3, r0 80080b0: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SPDIFRX clock source configuration done later after clock selection check */ break; 80080b4: e00f b.n 80080d6 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 80080b6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80080ba: 3328 adds r3, #40 ; 0x28 80080bc: 2102 movs r1, #2 80080be: 4618 mov r0, r3 80080c0: f002 faf0 bl 800a6a4 80080c4: 4603 mov r3, r0 80080c6: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SPDIFRX clock source configuration done later after clock selection check */ break; 80080ca: e004 b.n 80080d6 /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80080cc: 2301 movs r3, #1 80080ce: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 80080d2: e000 b.n 80080d6 break; 80080d4: bf00 nop } if (ret == HAL_OK) 80080d6: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80080da: 2b00 cmp r3, #0 80080dc: d10a bne.n 80080f4 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 80080de: 4b98 ldr r3, [pc, #608] ; (8008340 ) 80080e0: 6d1b ldr r3, [r3, #80] ; 0x50 80080e2: f423 1140 bic.w r1, r3, #3145728 ; 0x300000 80080e6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80080ea: 6e5b ldr r3, [r3, #100] ; 0x64 80080ec: 4a94 ldr r2, [pc, #592] ; (8008340 ) 80080ee: 430b orrs r3, r1 80080f0: 6513 str r3, [r2, #80] ; 0x50 80080f2: e003 b.n 80080fc } else { /* set overall return value */ status = ret; 80080f4: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80080f8: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 80080fc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008100: e9d3 2300 ldrd r2, r3, [r3] 8008104: f402 7880 and.w r8, r2, #256 ; 0x100 8008108: f04f 0900 mov.w r9, #0 800810c: ea58 0309 orrs.w r3, r8, r9 8008110: d047 beq.n 80081a2 { switch (PeriphClkInit->Sai1ClockSelection) 8008112: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008116: 6d9b ldr r3, [r3, #88] ; 0x58 8008118: 2b04 cmp r3, #4 800811a: d82a bhi.n 8008172 800811c: a201 add r2, pc, #4 ; (adr r2, 8008124 ) 800811e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008122: bf00 nop 8008124: 08008139 .word 0x08008139 8008128: 08008147 .word 0x08008147 800812c: 0800815d .word 0x0800815d 8008130: 0800817b .word 0x0800817b 8008134: 0800817b .word 0x0800817b { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008138: 4b81 ldr r3, [pc, #516] ; (8008340 ) 800813a: 6adb ldr r3, [r3, #44] ; 0x2c 800813c: 4a80 ldr r2, [pc, #512] ; (8008340 ) 800813e: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8008142: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8008144: e01a b.n 800817c case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8008146: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800814a: 3308 adds r3, #8 800814c: 2100 movs r1, #0 800814e: 4618 mov r0, r3 8008150: f002 f9f6 bl 800a540 8008154: 4603 mov r3, r0 8008156: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SAI1 clock source configuration done later after clock selection check */ break; 800815a: e00f b.n 800817c case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800815c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008160: 3328 adds r3, #40 ; 0x28 8008162: 2100 movs r1, #0 8008164: 4618 mov r0, r3 8008166: f002 fa9d bl 800a6a4 800816a: 4603 mov r3, r0 800816c: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SAI1 clock source configuration done later after clock selection check */ break; 8008170: e004 b.n 800817c /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8008172: 2301 movs r3, #1 8008174: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008178: e000 b.n 800817c break; 800817a: bf00 nop } if (ret == HAL_OK) 800817c: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008180: 2b00 cmp r3, #0 8008182: d10a bne.n 800819a { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8008184: 4b6e ldr r3, [pc, #440] ; (8008340 ) 8008186: 6d1b ldr r3, [r3, #80] ; 0x50 8008188: f023 0107 bic.w r1, r3, #7 800818c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008190: 6d9b ldr r3, [r3, #88] ; 0x58 8008192: 4a6b ldr r2, [pc, #428] ; (8008340 ) 8008194: 430b orrs r3, r1 8008196: 6513 str r3, [r2, #80] ; 0x50 8008198: e003 b.n 80081a2 } else { /* set overall return value */ status = ret; 800819a: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 800819e: f887 3116 strb.w r3, [r7, #278] ; 0x116 } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 80081a2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80081a6: e9d3 2300 ldrd r2, r3, [r3] 80081aa: f402 6a80 and.w sl, r2, #1024 ; 0x400 80081ae: f04f 0b00 mov.w fp, #0 80081b2: ea5a 030b orrs.w r3, sl, fp 80081b6: d05b beq.n 8008270 { switch (PeriphClkInit->Sai4AClockSelection) 80081b8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80081bc: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 80081c0: f5b3 0f20 cmp.w r3, #10485760 ; 0xa00000 80081c4: d03b beq.n 800823e 80081c6: f5b3 0f20 cmp.w r3, #10485760 ; 0xa00000 80081ca: d834 bhi.n 8008236 80081cc: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 80081d0: d037 beq.n 8008242 80081d2: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 80081d6: d82e bhi.n 8008236 80081d8: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000 80081dc: d033 beq.n 8008246 80081de: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000 80081e2: d828 bhi.n 8008236 80081e4: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 80081e8: d01a beq.n 8008220 80081ea: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 80081ee: d822 bhi.n 8008236 80081f0: 2b00 cmp r3, #0 80081f2: d003 beq.n 80081fc 80081f4: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 80081f8: d007 beq.n 800820a 80081fa: e01c b.n 8008236 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80081fc: 4b50 ldr r3, [pc, #320] ; (8008340 ) 80081fe: 6adb ldr r3, [r3, #44] ; 0x2c 8008200: 4a4f ldr r2, [pc, #316] ; (8008340 ) 8008202: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8008206: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8008208: e01e b.n 8008248 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800820a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800820e: 3308 adds r3, #8 8008210: 2100 movs r1, #0 8008212: 4618 mov r0, r3 8008214: f002 f994 bl 800a540 8008218: 4603 mov r3, r0 800821a: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SAI2 clock source configuration done later after clock selection check */ break; 800821e: e013 b.n 8008248 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 8008220: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008224: 3328 adds r3, #40 ; 0x28 8008226: 2100 movs r1, #0 8008228: 4618 mov r0, r3 800822a: f002 fa3b bl 800a6a4 800822e: 4603 mov r3, r0 8008230: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SAI1 clock source configuration done later after clock selection check */ break; 8008234: e008 b.n 8008248 /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 8008236: 2301 movs r3, #1 8008238: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 800823c: e004 b.n 8008248 break; 800823e: bf00 nop 8008240: e002 b.n 8008248 break; 8008242: bf00 nop 8008244: e000 b.n 8008248 break; 8008246: bf00 nop } if (ret == HAL_OK) 8008248: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 800824c: 2b00 cmp r3, #0 800824e: d10b bne.n 8008268 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 8008250: 4b3b ldr r3, [pc, #236] ; (8008340 ) 8008252: 6d9b ldr r3, [r3, #88] ; 0x58 8008254: f423 0160 bic.w r1, r3, #14680064 ; 0xe00000 8008258: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800825c: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 8008260: 4a37 ldr r2, [pc, #220] ; (8008340 ) 8008262: 430b orrs r3, r1 8008264: 6593 str r3, [r2, #88] ; 0x58 8008266: e003 b.n 8008270 } else { /* set overall return value */ status = ret; 8008268: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 800826c: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 8008270: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008274: e9d3 2300 ldrd r2, r3, [r3] 8008278: f402 6300 and.w r3, r2, #2048 ; 0x800 800827c: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 8008280: 2300 movs r3, #0 8008282: f8c7 30fc str.w r3, [r7, #252] ; 0xfc 8008286: e9d7 123e ldrd r1, r2, [r7, #248] ; 0xf8 800828a: 460b mov r3, r1 800828c: 4313 orrs r3, r2 800828e: d05d beq.n 800834c { switch (PeriphClkInit->Sai4BClockSelection) 8008290: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008294: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 8008298: f1b3 6fa0 cmp.w r3, #83886080 ; 0x5000000 800829c: d03b beq.n 8008316 800829e: f1b3 6fa0 cmp.w r3, #83886080 ; 0x5000000 80082a2: d834 bhi.n 800830e 80082a4: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 80082a8: d037 beq.n 800831a 80082aa: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 80082ae: d82e bhi.n 800830e 80082b0: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000 80082b4: d033 beq.n 800831e 80082b6: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000 80082ba: d828 bhi.n 800830e 80082bc: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80082c0: d01a beq.n 80082f8 80082c2: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80082c6: d822 bhi.n 800830e 80082c8: 2b00 cmp r3, #0 80082ca: d003 beq.n 80082d4 80082cc: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 80082d0: d007 beq.n 80082e2 80082d2: e01c b.n 800830e { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80082d4: 4b1a ldr r3, [pc, #104] ; (8008340 ) 80082d6: 6adb ldr r3, [r3, #44] ; 0x2c 80082d8: 4a19 ldr r2, [pc, #100] ; (8008340 ) 80082da: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80082de: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 80082e0: e01e b.n 8008320 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80082e2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80082e6: 3308 adds r3, #8 80082e8: 2100 movs r1, #0 80082ea: 4618 mov r0, r3 80082ec: f002 f928 bl 800a540 80082f0: 4603 mov r3, r0 80082f2: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SAI2 clock source configuration done later after clock selection check */ break; 80082f6: e013 b.n 8008320 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 80082f8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80082fc: 3328 adds r3, #40 ; 0x28 80082fe: 2100 movs r1, #0 8008300: 4618 mov r0, r3 8008302: f002 f9cf bl 800a6a4 8008306: 4603 mov r3, r0 8008308: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SAI1 clock source configuration done later after clock selection check */ break; 800830c: e008 b.n 8008320 /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800830e: 2301 movs r3, #1 8008310: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008314: e004 b.n 8008320 break; 8008316: bf00 nop 8008318: e002 b.n 8008320 break; 800831a: bf00 nop 800831c: e000 b.n 8008320 break; 800831e: bf00 nop } if (ret == HAL_OK) 8008320: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008324: 2b00 cmp r3, #0 8008326: d10d bne.n 8008344 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 8008328: 4b05 ldr r3, [pc, #20] ; (8008340 ) 800832a: 6d9b ldr r3, [r3, #88] ; 0x58 800832c: f023 61e0 bic.w r1, r3, #117440512 ; 0x7000000 8008330: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008334: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 8008338: 4a01 ldr r2, [pc, #4] ; (8008340 ) 800833a: 430b orrs r3, r1 800833c: 6593 str r3, [r2, #88] ; 0x58 800833e: e005 b.n 800834c 8008340: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8008344: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008348: f887 3116 strb.w r3, [r7, #278] ; 0x116 } #endif /*QUADSPI*/ #if defined(OCTOSPI1) || defined(OCTOSPI2) /*---------------------------- OCTOSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) 800834c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008350: e9d3 2300 ldrd r2, r3, [r3] 8008354: f002 7300 and.w r3, r2, #33554432 ; 0x2000000 8008358: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 800835c: 2300 movs r3, #0 800835e: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 8008362: e9d7 123c ldrd r1, r2, [r7, #240] ; 0xf0 8008366: 460b mov r3, r1 8008368: 4313 orrs r3, r2 800836a: d03a beq.n 80083e2 { switch (PeriphClkInit->OspiClockSelection) 800836c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008370: 6cdb ldr r3, [r3, #76] ; 0x4c 8008372: 2b30 cmp r3, #48 ; 0x30 8008374: d01f beq.n 80083b6 8008376: 2b30 cmp r3, #48 ; 0x30 8008378: d819 bhi.n 80083ae 800837a: 2b20 cmp r3, #32 800837c: d00c beq.n 8008398 800837e: 2b20 cmp r3, #32 8008380: d815 bhi.n 80083ae 8008382: 2b00 cmp r3, #0 8008384: d019 beq.n 80083ba 8008386: 2b10 cmp r3, #16 8008388: d111 bne.n 80083ae { case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ /* Enable OSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800838a: 4baa ldr r3, [pc, #680] ; (8008634 ) 800838c: 6adb ldr r3, [r3, #44] ; 0x2c 800838e: 4aa9 ldr r2, [pc, #676] ; (8008634 ) 8008390: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8008394: 62d3 str r3, [r2, #44] ; 0x2c /* OSPI clock source configuration done later after clock selection check */ break; 8008396: e011 b.n 80083bc case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8008398: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800839c: 3308 adds r3, #8 800839e: 2102 movs r1, #2 80083a0: 4618 mov r0, r3 80083a2: f002 f8cd bl 800a540 80083a6: 4603 mov r3, r0 80083a8: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* OSPI clock source configuration done later after clock selection check */ break; 80083ac: e006 b.n 80083bc case RCC_OSPICLKSOURCE_HCLK: /* HCLK clock selected as OSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 80083ae: 2301 movs r3, #1 80083b0: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 80083b4: e002 b.n 80083bc break; 80083b6: bf00 nop 80083b8: e000 b.n 80083bc break; 80083ba: bf00 nop } if (ret == HAL_OK) 80083bc: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80083c0: 2b00 cmp r3, #0 80083c2: d10a bne.n 80083da { /* Set the source of OSPI clock*/ __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); 80083c4: 4b9b ldr r3, [pc, #620] ; (8008634 ) 80083c6: 6cdb ldr r3, [r3, #76] ; 0x4c 80083c8: f023 0130 bic.w r1, r3, #48 ; 0x30 80083cc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80083d0: 6cdb ldr r3, [r3, #76] ; 0x4c 80083d2: 4a98 ldr r2, [pc, #608] ; (8008634 ) 80083d4: 430b orrs r3, r1 80083d6: 64d3 str r3, [r2, #76] ; 0x4c 80083d8: e003 b.n 80083e2 } else { /* set overall return value */ status = ret; 80083da: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80083de: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 80083e2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80083e6: e9d3 2300 ldrd r2, r3, [r3] 80083ea: f402 5380 and.w r3, r2, #4096 ; 0x1000 80083ee: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 80083f2: 2300 movs r3, #0 80083f4: f8c7 30ec str.w r3, [r7, #236] ; 0xec 80083f8: e9d7 123a ldrd r1, r2, [r7, #232] ; 0xe8 80083fc: 460b mov r3, r1 80083fe: 4313 orrs r3, r2 8008400: d051 beq.n 80084a6 { switch (PeriphClkInit->Spi123ClockSelection) 8008402: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008406: 6ddb ldr r3, [r3, #92] ; 0x5c 8008408: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 800840c: d035 beq.n 800847a 800840e: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8008412: d82e bhi.n 8008472 8008414: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 8008418: d031 beq.n 800847e 800841a: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 800841e: d828 bhi.n 8008472 8008420: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8008424: d01a beq.n 800845c 8008426: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800842a: d822 bhi.n 8008472 800842c: 2b00 cmp r3, #0 800842e: d003 beq.n 8008438 8008430: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8008434: d007 beq.n 8008446 8008436: e01c b.n 8008472 { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008438: 4b7e ldr r3, [pc, #504] ; (8008634 ) 800843a: 6adb ldr r3, [r3, #44] ; 0x2c 800843c: 4a7d ldr r2, [pc, #500] ; (8008634 ) 800843e: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8008442: 62d3 str r3, [r2, #44] ; 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8008444: e01c b.n 8008480 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8008446: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800844a: 3308 adds r3, #8 800844c: 2100 movs r1, #0 800844e: 4618 mov r0, r3 8008450: f002 f876 bl 800a540 8008454: 4603 mov r3, r0 8008456: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800845a: e011 b.n 8008480 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800845c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008460: 3328 adds r3, #40 ; 0x28 8008462: 2100 movs r1, #0 8008464: 4618 mov r0, r3 8008466: f002 f91d bl 800a6a4 800846a: 4603 mov r3, r0 800846c: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8008470: e006 b.n 8008480 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8008472: 2301 movs r3, #1 8008474: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008478: e002 b.n 8008480 break; 800847a: bf00 nop 800847c: e000 b.n 8008480 break; 800847e: bf00 nop } if (ret == HAL_OK) 8008480: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008484: 2b00 cmp r3, #0 8008486: d10a bne.n 800849e { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 8008488: 4b6a ldr r3, [pc, #424] ; (8008634 ) 800848a: 6d1b ldr r3, [r3, #80] ; 0x50 800848c: f423 41e0 bic.w r1, r3, #28672 ; 0x7000 8008490: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008494: 6ddb ldr r3, [r3, #92] ; 0x5c 8008496: 4a67 ldr r2, [pc, #412] ; (8008634 ) 8008498: 430b orrs r3, r1 800849a: 6513 str r3, [r2, #80] ; 0x50 800849c: e003 b.n 80084a6 } else { /* set overall return value */ status = ret; 800849e: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80084a2: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 80084a6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80084aa: e9d3 2300 ldrd r2, r3, [r3] 80084ae: f402 5300 and.w r3, r2, #8192 ; 0x2000 80084b2: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 80084b6: 2300 movs r3, #0 80084b8: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 80084bc: e9d7 1238 ldrd r1, r2, [r7, #224] ; 0xe0 80084c0: 460b mov r3, r1 80084c2: 4313 orrs r3, r2 80084c4: d053 beq.n 800856e { switch (PeriphClkInit->Spi45ClockSelection) 80084c6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80084ca: 6e1b ldr r3, [r3, #96] ; 0x60 80084cc: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80084d0: d033 beq.n 800853a 80084d2: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80084d6: d82c bhi.n 8008532 80084d8: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 80084dc: d02f beq.n 800853e 80084de: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 80084e2: d826 bhi.n 8008532 80084e4: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 80084e8: d02b beq.n 8008542 80084ea: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 80084ee: d820 bhi.n 8008532 80084f0: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80084f4: d012 beq.n 800851c 80084f6: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80084fa: d81a bhi.n 8008532 80084fc: 2b00 cmp r3, #0 80084fe: d022 beq.n 8008546 8008500: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8008504: d115 bne.n 8008532 /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8008506: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800850a: 3308 adds r3, #8 800850c: 2101 movs r1, #1 800850e: 4618 mov r0, r3 8008510: f002 f816 bl 800a540 8008514: 4603 mov r3, r0 8008516: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SPI4/5 clock source configuration done later after clock selection check */ break; 800851a: e015 b.n 8008548 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800851c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008520: 3328 adds r3, #40 ; 0x28 8008522: 2101 movs r1, #1 8008524: 4618 mov r0, r3 8008526: f002 f8bd bl 800a6a4 800852a: 4603 mov r3, r0 800852c: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SPI4/5 clock source configuration done later after clock selection check */ break; 8008530: e00a b.n 8008548 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8008532: 2301 movs r3, #1 8008534: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008538: e006 b.n 8008548 break; 800853a: bf00 nop 800853c: e004 b.n 8008548 break; 800853e: bf00 nop 8008540: e002 b.n 8008548 break; 8008542: bf00 nop 8008544: e000 b.n 8008548 break; 8008546: bf00 nop } if (ret == HAL_OK) 8008548: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 800854c: 2b00 cmp r3, #0 800854e: d10a bne.n 8008566 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 8008550: 4b38 ldr r3, [pc, #224] ; (8008634 ) 8008552: 6d1b ldr r3, [r3, #80] ; 0x50 8008554: f423 21e0 bic.w r1, r3, #458752 ; 0x70000 8008558: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800855c: 6e1b ldr r3, [r3, #96] ; 0x60 800855e: 4a35 ldr r2, [pc, #212] ; (8008634 ) 8008560: 430b orrs r3, r1 8008562: 6513 str r3, [r2, #80] ; 0x50 8008564: e003 b.n 800856e } else { /* set overall return value */ status = ret; 8008566: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 800856a: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800856e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008572: e9d3 2300 ldrd r2, r3, [r3] 8008576: f402 4380 and.w r3, r2, #16384 ; 0x4000 800857a: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 800857e: 2300 movs r3, #0 8008580: f8c7 30dc str.w r3, [r7, #220] ; 0xdc 8008584: e9d7 1236 ldrd r1, r2, [r7, #216] ; 0xd8 8008588: 460b mov r3, r1 800858a: 4313 orrs r3, r2 800858c: d058 beq.n 8008640 { switch (PeriphClkInit->Spi6ClockSelection) 800858e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008592: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 8008596: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 800859a: d033 beq.n 8008604 800859c: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 80085a0: d82c bhi.n 80085fc 80085a2: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80085a6: d02f beq.n 8008608 80085a8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80085ac: d826 bhi.n 80085fc 80085ae: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80085b2: d02b beq.n 800860c 80085b4: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80085b8: d820 bhi.n 80085fc 80085ba: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80085be: d012 beq.n 80085e6 80085c0: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80085c4: d81a bhi.n 80085fc 80085c6: 2b00 cmp r3, #0 80085c8: d022 beq.n 8008610 80085ca: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 80085ce: d115 bne.n 80085fc /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 80085d0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80085d4: 3308 adds r3, #8 80085d6: 2101 movs r1, #1 80085d8: 4618 mov r0, r3 80085da: f001 ffb1 bl 800a540 80085de: 4603 mov r3, r0 80085e0: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SPI6 clock source configuration done later after clock selection check */ break; 80085e4: e015 b.n 8008612 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 80085e6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80085ea: 3328 adds r3, #40 ; 0x28 80085ec: 2101 movs r1, #1 80085ee: 4618 mov r0, r3 80085f0: f002 f858 bl 800a6a4 80085f4: 4603 mov r3, r0 80085f6: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SPI6 clock source configuration done later after clock selection check */ break; 80085fa: e00a b.n 8008612 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 80085fc: 2301 movs r3, #1 80085fe: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008602: e006 b.n 8008612 break; 8008604: bf00 nop 8008606: e004 b.n 8008612 break; 8008608: bf00 nop 800860a: e002 b.n 8008612 break; 800860c: bf00 nop 800860e: e000 b.n 8008612 break; 8008610: bf00 nop } if (ret == HAL_OK) 8008612: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008616: 2b00 cmp r3, #0 8008618: d10e bne.n 8008638 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800861a: 4b06 ldr r3, [pc, #24] ; (8008634 ) 800861c: 6d9b ldr r3, [r3, #88] ; 0x58 800861e: f023 41e0 bic.w r1, r3, #1879048192 ; 0x70000000 8008622: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008626: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 800862a: 4a02 ldr r2, [pc, #8] ; (8008634 ) 800862c: 430b orrs r3, r1 800862e: 6593 str r3, [r2, #88] ; 0x58 8008630: e006 b.n 8008640 8008632: bf00 nop 8008634: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8008638: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 800863c: f887 3116 strb.w r3, [r7, #278] ; 0x116 } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 8008640: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008644: e9d3 2300 ldrd r2, r3, [r3] 8008648: f402 4300 and.w r3, r2, #32768 ; 0x8000 800864c: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 8008650: 2300 movs r3, #0 8008652: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 8008656: e9d7 1234 ldrd r1, r2, [r7, #208] ; 0xd0 800865a: 460b mov r3, r1 800865c: 4313 orrs r3, r2 800865e: d037 beq.n 80086d0 { switch (PeriphClkInit->FdcanClockSelection) 8008660: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008664: 6edb ldr r3, [r3, #108] ; 0x6c 8008666: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800866a: d00e beq.n 800868a 800866c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8008670: d816 bhi.n 80086a0 8008672: 2b00 cmp r3, #0 8008674: d018 beq.n 80086a8 8008676: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 800867a: d111 bne.n 80086a0 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800867c: 4bc4 ldr r3, [pc, #784] ; (8008990 ) 800867e: 6adb ldr r3, [r3, #44] ; 0x2c 8008680: 4ac3 ldr r2, [pc, #780] ; (8008990 ) 8008682: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8008686: 62d3 str r3, [r2, #44] ; 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 8008688: e00f b.n 80086aa case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800868a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800868e: 3308 adds r3, #8 8008690: 2101 movs r1, #1 8008692: 4618 mov r0, r3 8008694: f001 ff54 bl 800a540 8008698: 4603 mov r3, r0 800869a: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* FDCAN clock source configuration done later after clock selection check */ break; 800869e: e004 b.n 80086aa /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80086a0: 2301 movs r3, #1 80086a2: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 80086a6: e000 b.n 80086aa break; 80086a8: bf00 nop } if (ret == HAL_OK) 80086aa: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80086ae: 2b00 cmp r3, #0 80086b0: d10a bne.n 80086c8 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 80086b2: 4bb7 ldr r3, [pc, #732] ; (8008990 ) 80086b4: 6d1b ldr r3, [r3, #80] ; 0x50 80086b6: f023 5140 bic.w r1, r3, #805306368 ; 0x30000000 80086ba: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80086be: 6edb ldr r3, [r3, #108] ; 0x6c 80086c0: 4ab3 ldr r2, [pc, #716] ; (8008990 ) 80086c2: 430b orrs r3, r1 80086c4: 6513 str r3, [r2, #80] ; 0x50 80086c6: e003 b.n 80086d0 } else { /* set overall return value */ status = ret; 80086c8: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80086cc: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 80086d0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80086d4: e9d3 2300 ldrd r2, r3, [r3] 80086d8: f002 7380 and.w r3, r2, #16777216 ; 0x1000000 80086dc: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 80086e0: 2300 movs r3, #0 80086e2: f8c7 30cc str.w r3, [r7, #204] ; 0xcc 80086e6: e9d7 1232 ldrd r1, r2, [r7, #200] ; 0xc8 80086ea: 460b mov r3, r1 80086ec: 4313 orrs r3, r2 80086ee: d039 beq.n 8008764 { switch (PeriphClkInit->FmcClockSelection) 80086f0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80086f4: 6c9b ldr r3, [r3, #72] ; 0x48 80086f6: 2b03 cmp r3, #3 80086f8: d81c bhi.n 8008734 80086fa: a201 add r2, pc, #4 ; (adr r2, 8008700 ) 80086fc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008700: 0800873d .word 0x0800873d 8008704: 08008711 .word 0x08008711 8008708: 0800871f .word 0x0800871f 800870c: 0800873d .word 0x0800873d { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008710: 4b9f ldr r3, [pc, #636] ; (8008990 ) 8008712: 6adb ldr r3, [r3, #44] ; 0x2c 8008714: 4a9e ldr r2, [pc, #632] ; (8008990 ) 8008716: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800871a: 62d3 str r3, [r2, #44] ; 0x2c /* FMC clock source configuration done later after clock selection check */ break; 800871c: e00f b.n 800873e case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800871e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008722: 3308 adds r3, #8 8008724: 2102 movs r1, #2 8008726: 4618 mov r0, r3 8008728: f001 ff0a bl 800a540 800872c: 4603 mov r3, r0 800872e: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* FMC clock source configuration done later after clock selection check */ break; 8008732: e004 b.n 800873e case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 8008734: 2301 movs r3, #1 8008736: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 800873a: e000 b.n 800873e break; 800873c: bf00 nop } if (ret == HAL_OK) 800873e: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008742: 2b00 cmp r3, #0 8008744: d10a bne.n 800875c { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 8008746: 4b92 ldr r3, [pc, #584] ; (8008990 ) 8008748: 6cdb ldr r3, [r3, #76] ; 0x4c 800874a: f023 0103 bic.w r1, r3, #3 800874e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008752: 6c9b ldr r3, [r3, #72] ; 0x48 8008754: 4a8e ldr r2, [pc, #568] ; (8008990 ) 8008756: 430b orrs r3, r1 8008758: 64d3 str r3, [r2, #76] ; 0x4c 800875a: e003 b.n 8008764 } else { /* set overall return value */ status = ret; 800875c: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008760: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8008764: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008768: e9d3 2300 ldrd r2, r3, [r3] 800876c: f402 0380 and.w r3, r2, #4194304 ; 0x400000 8008770: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 8008774: 2300 movs r3, #0 8008776: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 800877a: e9d7 1230 ldrd r1, r2, [r7, #192] ; 0xc0 800877e: 460b mov r3, r1 8008780: 4313 orrs r3, r2 8008782: f000 8099 beq.w 80088b8 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8008786: 4b83 ldr r3, [pc, #524] ; (8008994 ) 8008788: 681b ldr r3, [r3, #0] 800878a: 4a82 ldr r2, [pc, #520] ; (8008994 ) 800878c: f443 7380 orr.w r3, r3, #256 ; 0x100 8008790: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8008792: f7f9 fde7 bl 8002364 8008796: f8c7 0110 str.w r0, [r7, #272] ; 0x110 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800879a: e00b b.n 80087b4 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800879c: f7f9 fde2 bl 8002364 80087a0: 4602 mov r2, r0 80087a2: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 80087a6: 1ad3 subs r3, r2, r3 80087a8: 2b64 cmp r3, #100 ; 0x64 80087aa: d903 bls.n 80087b4 { ret = HAL_TIMEOUT; 80087ac: 2303 movs r3, #3 80087ae: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 80087b2: e005 b.n 80087c0 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 80087b4: 4b77 ldr r3, [pc, #476] ; (8008994 ) 80087b6: 681b ldr r3, [r3, #0] 80087b8: f403 7380 and.w r3, r3, #256 ; 0x100 80087bc: 2b00 cmp r3, #0 80087be: d0ed beq.n 800879c } } if (ret == HAL_OK) 80087c0: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80087c4: 2b00 cmp r3, #0 80087c6: d173 bne.n 80088b0 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 80087c8: 4b71 ldr r3, [pc, #452] ; (8008990 ) 80087ca: 6f1a ldr r2, [r3, #112] ; 0x70 80087cc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80087d0: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 80087d4: 4053 eors r3, r2 80087d6: f403 7340 and.w r3, r3, #768 ; 0x300 80087da: 2b00 cmp r3, #0 80087dc: d015 beq.n 800880a { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80087de: 4b6c ldr r3, [pc, #432] ; (8008990 ) 80087e0: 6f1b ldr r3, [r3, #112] ; 0x70 80087e2: f423 7340 bic.w r3, r3, #768 ; 0x300 80087e6: f8c7 310c str.w r3, [r7, #268] ; 0x10c /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80087ea: 4b69 ldr r3, [pc, #420] ; (8008990 ) 80087ec: 6f1b ldr r3, [r3, #112] ; 0x70 80087ee: 4a68 ldr r2, [pc, #416] ; (8008990 ) 80087f0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80087f4: 6713 str r3, [r2, #112] ; 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 80087f6: 4b66 ldr r3, [pc, #408] ; (8008990 ) 80087f8: 6f1b ldr r3, [r3, #112] ; 0x70 80087fa: 4a65 ldr r2, [pc, #404] ; (8008990 ) 80087fc: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8008800: 6713 str r3, [r2, #112] ; 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 8008802: 4a63 ldr r2, [pc, #396] ; (8008990 ) 8008804: f8d7 310c ldr.w r3, [r7, #268] ; 0x10c 8008808: 6713 str r3, [r2, #112] ; 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 800880a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800880e: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8008812: f5b3 7f80 cmp.w r3, #256 ; 0x100 8008816: d118 bne.n 800884a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8008818: f7f9 fda4 bl 8002364 800881c: f8c7 0110 str.w r0, [r7, #272] ; 0x110 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8008820: e00d b.n 800883e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8008822: f7f9 fd9f bl 8002364 8008826: 4602 mov r2, r0 8008828: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 800882c: 1ad2 subs r2, r2, r3 800882e: f241 3388 movw r3, #5000 ; 0x1388 8008832: 429a cmp r2, r3 8008834: d903 bls.n 800883e { ret = HAL_TIMEOUT; 8008836: 2303 movs r3, #3 8008838: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 800883c: e005 b.n 800884a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800883e: 4b54 ldr r3, [pc, #336] ; (8008990 ) 8008840: 6f1b ldr r3, [r3, #112] ; 0x70 8008842: f003 0302 and.w r3, r3, #2 8008846: 2b00 cmp r3, #0 8008848: d0eb beq.n 8008822 } } } if (ret == HAL_OK) 800884a: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 800884e: 2b00 cmp r3, #0 8008850: d129 bne.n 80088a6 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8008852: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008856: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 800885a: f403 7340 and.w r3, r3, #768 ; 0x300 800885e: f5b3 7f40 cmp.w r3, #768 ; 0x300 8008862: d10e bne.n 8008882 8008864: 4b4a ldr r3, [pc, #296] ; (8008990 ) 8008866: 691b ldr r3, [r3, #16] 8008868: f423 517c bic.w r1, r3, #16128 ; 0x3f00 800886c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008870: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8008874: 091a lsrs r2, r3, #4 8008876: 4b48 ldr r3, [pc, #288] ; (8008998 ) 8008878: 4013 ands r3, r2 800887a: 4a45 ldr r2, [pc, #276] ; (8008990 ) 800887c: 430b orrs r3, r1 800887e: 6113 str r3, [r2, #16] 8008880: e005 b.n 800888e 8008882: 4b43 ldr r3, [pc, #268] ; (8008990 ) 8008884: 691b ldr r3, [r3, #16] 8008886: 4a42 ldr r2, [pc, #264] ; (8008990 ) 8008888: f423 537c bic.w r3, r3, #16128 ; 0x3f00 800888c: 6113 str r3, [r2, #16] 800888e: 4b40 ldr r3, [pc, #256] ; (8008990 ) 8008890: 6f19 ldr r1, [r3, #112] ; 0x70 8008892: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008896: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 800889a: f3c3 030b ubfx r3, r3, #0, #12 800889e: 4a3c ldr r2, [pc, #240] ; (8008990 ) 80088a0: 430b orrs r3, r1 80088a2: 6713 str r3, [r2, #112] ; 0x70 80088a4: e008 b.n 80088b8 } else { /* set overall return value */ status = ret; 80088a6: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80088aa: f887 3116 strb.w r3, [r7, #278] ; 0x116 80088ae: e003 b.n 80088b8 } } else { /* set overall return value */ status = ret; 80088b0: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80088b4: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 80088b8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80088bc: e9d3 2300 ldrd r2, r3, [r3] 80088c0: f002 0301 and.w r3, r2, #1 80088c4: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 80088c8: 2300 movs r3, #0 80088ca: f8c7 30bc str.w r3, [r7, #188] ; 0xbc 80088ce: e9d7 122e ldrd r1, r2, [r7, #184] ; 0xb8 80088d2: 460b mov r3, r1 80088d4: 4313 orrs r3, r2 80088d6: f000 808f beq.w 80089f8 { switch (PeriphClkInit->Usart16ClockSelection) 80088da: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80088de: 6f9b ldr r3, [r3, #120] ; 0x78 80088e0: 2b28 cmp r3, #40 ; 0x28 80088e2: d871 bhi.n 80089c8 80088e4: a201 add r2, pc, #4 ; (adr r2, 80088ec ) 80088e6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80088ea: bf00 nop 80088ec: 080089d1 .word 0x080089d1 80088f0: 080089c9 .word 0x080089c9 80088f4: 080089c9 .word 0x080089c9 80088f8: 080089c9 .word 0x080089c9 80088fc: 080089c9 .word 0x080089c9 8008900: 080089c9 .word 0x080089c9 8008904: 080089c9 .word 0x080089c9 8008908: 080089c9 .word 0x080089c9 800890c: 0800899d .word 0x0800899d 8008910: 080089c9 .word 0x080089c9 8008914: 080089c9 .word 0x080089c9 8008918: 080089c9 .word 0x080089c9 800891c: 080089c9 .word 0x080089c9 8008920: 080089c9 .word 0x080089c9 8008924: 080089c9 .word 0x080089c9 8008928: 080089c9 .word 0x080089c9 800892c: 080089b3 .word 0x080089b3 8008930: 080089c9 .word 0x080089c9 8008934: 080089c9 .word 0x080089c9 8008938: 080089c9 .word 0x080089c9 800893c: 080089c9 .word 0x080089c9 8008940: 080089c9 .word 0x080089c9 8008944: 080089c9 .word 0x080089c9 8008948: 080089c9 .word 0x080089c9 800894c: 080089d1 .word 0x080089d1 8008950: 080089c9 .word 0x080089c9 8008954: 080089c9 .word 0x080089c9 8008958: 080089c9 .word 0x080089c9 800895c: 080089c9 .word 0x080089c9 8008960: 080089c9 .word 0x080089c9 8008964: 080089c9 .word 0x080089c9 8008968: 080089c9 .word 0x080089c9 800896c: 080089d1 .word 0x080089d1 8008970: 080089c9 .word 0x080089c9 8008974: 080089c9 .word 0x080089c9 8008978: 080089c9 .word 0x080089c9 800897c: 080089c9 .word 0x080089c9 8008980: 080089c9 .word 0x080089c9 8008984: 080089c9 .word 0x080089c9 8008988: 080089c9 .word 0x080089c9 800898c: 080089d1 .word 0x080089d1 8008990: 58024400 .word 0x58024400 8008994: 58024800 .word 0x58024800 8008998: 00ffffcf .word 0x00ffffcf case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800899c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80089a0: 3308 adds r3, #8 80089a2: 2101 movs r1, #1 80089a4: 4618 mov r0, r3 80089a6: f001 fdcb bl 800a540 80089aa: 4603 mov r3, r0 80089ac: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* USART1/6 clock source configuration done later after clock selection check */ break; 80089b0: e00f b.n 80089d2 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 80089b2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80089b6: 3328 adds r3, #40 ; 0x28 80089b8: 2101 movs r1, #1 80089ba: 4618 mov r0, r3 80089bc: f001 fe72 bl 800a6a4 80089c0: 4603 mov r3, r0 80089c2: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* USART1/6 clock source configuration done later after clock selection check */ break; 80089c6: e004 b.n 80089d2 /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80089c8: 2301 movs r3, #1 80089ca: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 80089ce: e000 b.n 80089d2 break; 80089d0: bf00 nop } if (ret == HAL_OK) 80089d2: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80089d6: 2b00 cmp r3, #0 80089d8: d10a bne.n 80089f0 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 80089da: 4bbf ldr r3, [pc, #764] ; (8008cd8 ) 80089dc: 6d5b ldr r3, [r3, #84] ; 0x54 80089de: f023 0138 bic.w r1, r3, #56 ; 0x38 80089e2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80089e6: 6f9b ldr r3, [r3, #120] ; 0x78 80089e8: 4abb ldr r2, [pc, #748] ; (8008cd8 ) 80089ea: 430b orrs r3, r1 80089ec: 6553 str r3, [r2, #84] ; 0x54 80089ee: e003 b.n 80089f8 } else { /* set overall return value */ status = ret; 80089f0: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80089f4: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 80089f8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80089fc: e9d3 2300 ldrd r2, r3, [r3] 8008a00: f002 0302 and.w r3, r2, #2 8008a04: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 8008a08: 2300 movs r3, #0 8008a0a: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 8008a0e: e9d7 122c ldrd r1, r2, [r7, #176] ; 0xb0 8008a12: 460b mov r3, r1 8008a14: 4313 orrs r3, r2 8008a16: d041 beq.n 8008a9c { switch (PeriphClkInit->Usart234578ClockSelection) 8008a18: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008a1c: 6f5b ldr r3, [r3, #116] ; 0x74 8008a1e: 2b05 cmp r3, #5 8008a20: d824 bhi.n 8008a6c 8008a22: a201 add r2, pc, #4 ; (adr r2, 8008a28 ) 8008a24: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008a28: 08008a75 .word 0x08008a75 8008a2c: 08008a41 .word 0x08008a41 8008a30: 08008a57 .word 0x08008a57 8008a34: 08008a75 .word 0x08008a75 8008a38: 08008a75 .word 0x08008a75 8008a3c: 08008a75 .word 0x08008a75 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8008a40: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008a44: 3308 adds r3, #8 8008a46: 2101 movs r1, #1 8008a48: 4618 mov r0, r3 8008a4a: f001 fd79 bl 800a540 8008a4e: 4603 mov r3, r0 8008a50: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8008a54: e00f b.n 8008a76 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8008a56: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008a5a: 3328 adds r3, #40 ; 0x28 8008a5c: 2101 movs r1, #1 8008a5e: 4618 mov r0, r3 8008a60: f001 fe20 bl 800a6a4 8008a64: 4603 mov r3, r0 8008a66: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8008a6a: e004 b.n 8008a76 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8008a6c: 2301 movs r3, #1 8008a6e: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008a72: e000 b.n 8008a76 break; 8008a74: bf00 nop } if (ret == HAL_OK) 8008a76: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008a7a: 2b00 cmp r3, #0 8008a7c: d10a bne.n 8008a94 { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 8008a7e: 4b96 ldr r3, [pc, #600] ; (8008cd8 ) 8008a80: 6d5b ldr r3, [r3, #84] ; 0x54 8008a82: f023 0107 bic.w r1, r3, #7 8008a86: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008a8a: 6f5b ldr r3, [r3, #116] ; 0x74 8008a8c: 4a92 ldr r2, [pc, #584] ; (8008cd8 ) 8008a8e: 430b orrs r3, r1 8008a90: 6553 str r3, [r2, #84] ; 0x54 8008a92: e003 b.n 8008a9c } else { /* set overall return value */ status = ret; 8008a94: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008a98: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8008a9c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008aa0: e9d3 2300 ldrd r2, r3, [r3] 8008aa4: f002 0304 and.w r3, r2, #4 8008aa8: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 8008aac: 2300 movs r3, #0 8008aae: f8c7 30ac str.w r3, [r7, #172] ; 0xac 8008ab2: e9d7 122a ldrd r1, r2, [r7, #168] ; 0xa8 8008ab6: 460b mov r3, r1 8008ab8: 4313 orrs r3, r2 8008aba: d044 beq.n 8008b46 { switch (PeriphClkInit->Lpuart1ClockSelection) 8008abc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008ac0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8008ac4: 2b05 cmp r3, #5 8008ac6: d825 bhi.n 8008b14 8008ac8: a201 add r2, pc, #4 ; (adr r2, 8008ad0 ) 8008aca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008ace: bf00 nop 8008ad0: 08008b1d .word 0x08008b1d 8008ad4: 08008ae9 .word 0x08008ae9 8008ad8: 08008aff .word 0x08008aff 8008adc: 08008b1d .word 0x08008b1d 8008ae0: 08008b1d .word 0x08008b1d 8008ae4: 08008b1d .word 0x08008b1d case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8008ae8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008aec: 3308 adds r3, #8 8008aee: 2101 movs r1, #1 8008af0: 4618 mov r0, r3 8008af2: f001 fd25 bl 800a540 8008af6: 4603 mov r3, r0 8008af8: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* LPUART1 clock source configuration done later after clock selection check */ break; 8008afc: e00f b.n 8008b1e case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8008afe: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008b02: 3328 adds r3, #40 ; 0x28 8008b04: 2101 movs r1, #1 8008b06: 4618 mov r0, r3 8008b08: f001 fdcc bl 800a6a4 8008b0c: 4603 mov r3, r0 8008b0e: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* LPUART1 clock source configuration done later after clock selection check */ break; 8008b12: e004 b.n 8008b1e /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8008b14: 2301 movs r3, #1 8008b16: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008b1a: e000 b.n 8008b1e break; 8008b1c: bf00 nop } if (ret == HAL_OK) 8008b1e: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008b22: 2b00 cmp r3, #0 8008b24: d10b bne.n 8008b3e { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8008b26: 4b6c ldr r3, [pc, #432] ; (8008cd8 ) 8008b28: 6d9b ldr r3, [r3, #88] ; 0x58 8008b2a: f023 0107 bic.w r1, r3, #7 8008b2e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008b32: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8008b36: 4a68 ldr r2, [pc, #416] ; (8008cd8 ) 8008b38: 430b orrs r3, r1 8008b3a: 6593 str r3, [r2, #88] ; 0x58 8008b3c: e003 b.n 8008b46 } else { /* set overall return value */ status = ret; 8008b3e: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008b42: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8008b46: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008b4a: e9d3 2300 ldrd r2, r3, [r3] 8008b4e: f002 0320 and.w r3, r2, #32 8008b52: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 8008b56: 2300 movs r3, #0 8008b58: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 8008b5c: e9d7 1228 ldrd r1, r2, [r7, #160] ; 0xa0 8008b60: 460b mov r3, r1 8008b62: 4313 orrs r3, r2 8008b64: d055 beq.n 8008c12 { switch (PeriphClkInit->Lptim1ClockSelection) 8008b66: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008b6a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8008b6e: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8008b72: d033 beq.n 8008bdc 8008b74: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8008b78: d82c bhi.n 8008bd4 8008b7a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8008b7e: d02f beq.n 8008be0 8008b80: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8008b84: d826 bhi.n 8008bd4 8008b86: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8008b8a: d02b beq.n 8008be4 8008b8c: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8008b90: d820 bhi.n 8008bd4 8008b92: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8008b96: d012 beq.n 8008bbe 8008b98: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8008b9c: d81a bhi.n 8008bd4 8008b9e: 2b00 cmp r3, #0 8008ba0: d022 beq.n 8008be8 8008ba2: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8008ba6: d115 bne.n 8008bd4 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8008ba8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008bac: 3308 adds r3, #8 8008bae: 2100 movs r1, #0 8008bb0: 4618 mov r0, r3 8008bb2: f001 fcc5 bl 800a540 8008bb6: 4603 mov r3, r0 8008bb8: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* LPTIM1 clock source configuration done later after clock selection check */ break; 8008bbc: e015 b.n 8008bea case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8008bbe: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008bc2: 3328 adds r3, #40 ; 0x28 8008bc4: 2102 movs r1, #2 8008bc6: 4618 mov r0, r3 8008bc8: f001 fd6c bl 800a6a4 8008bcc: 4603 mov r3, r0 8008bce: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* LPTIM1 clock source configuration done later after clock selection check */ break; 8008bd2: e00a b.n 8008bea /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8008bd4: 2301 movs r3, #1 8008bd6: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008bda: e006 b.n 8008bea break; 8008bdc: bf00 nop 8008bde: e004 b.n 8008bea break; 8008be0: bf00 nop 8008be2: e002 b.n 8008bea break; 8008be4: bf00 nop 8008be6: e000 b.n 8008bea break; 8008be8: bf00 nop } if (ret == HAL_OK) 8008bea: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008bee: 2b00 cmp r3, #0 8008bf0: d10b bne.n 8008c0a { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8008bf2: 4b39 ldr r3, [pc, #228] ; (8008cd8 ) 8008bf4: 6d5b ldr r3, [r3, #84] ; 0x54 8008bf6: f023 41e0 bic.w r1, r3, #1879048192 ; 0x70000000 8008bfa: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008bfe: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8008c02: 4a35 ldr r2, [pc, #212] ; (8008cd8 ) 8008c04: 430b orrs r3, r1 8008c06: 6553 str r3, [r2, #84] ; 0x54 8008c08: e003 b.n 8008c12 } else { /* set overall return value */ status = ret; 8008c0a: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008c0e: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 8008c12: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008c16: e9d3 2300 ldrd r2, r3, [r3] 8008c1a: f002 0340 and.w r3, r2, #64 ; 0x40 8008c1e: f8c7 3098 str.w r3, [r7, #152] ; 0x98 8008c22: 2300 movs r3, #0 8008c24: f8c7 309c str.w r3, [r7, #156] ; 0x9c 8008c28: e9d7 1226 ldrd r1, r2, [r7, #152] ; 0x98 8008c2c: 460b mov r3, r1 8008c2e: 4313 orrs r3, r2 8008c30: d058 beq.n 8008ce4 { switch (PeriphClkInit->Lptim2ClockSelection) 8008c32: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008c36: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8008c3a: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 8008c3e: d033 beq.n 8008ca8 8008c40: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 8008c44: d82c bhi.n 8008ca0 8008c46: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8008c4a: d02f beq.n 8008cac 8008c4c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8008c50: d826 bhi.n 8008ca0 8008c52: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 8008c56: d02b beq.n 8008cb0 8008c58: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 8008c5c: d820 bhi.n 8008ca0 8008c5e: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8008c62: d012 beq.n 8008c8a 8008c64: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8008c68: d81a bhi.n 8008ca0 8008c6a: 2b00 cmp r3, #0 8008c6c: d022 beq.n 8008cb4 8008c6e: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8008c72: d115 bne.n 8008ca0 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8008c74: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008c78: 3308 adds r3, #8 8008c7a: 2100 movs r1, #0 8008c7c: 4618 mov r0, r3 8008c7e: f001 fc5f bl 800a540 8008c82: 4603 mov r3, r0 8008c84: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* LPTIM2 clock source configuration done later after clock selection check */ break; 8008c88: e015 b.n 8008cb6 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8008c8a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008c8e: 3328 adds r3, #40 ; 0x28 8008c90: 2102 movs r1, #2 8008c92: 4618 mov r0, r3 8008c94: f001 fd06 bl 800a6a4 8008c98: 4603 mov r3, r0 8008c9a: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* LPTIM2 clock source configuration done later after clock selection check */ break; 8008c9e: e00a b.n 8008cb6 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8008ca0: 2301 movs r3, #1 8008ca2: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008ca6: e006 b.n 8008cb6 break; 8008ca8: bf00 nop 8008caa: e004 b.n 8008cb6 break; 8008cac: bf00 nop 8008cae: e002 b.n 8008cb6 break; 8008cb0: bf00 nop 8008cb2: e000 b.n 8008cb6 break; 8008cb4: bf00 nop } if (ret == HAL_OK) 8008cb6: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008cba: 2b00 cmp r3, #0 8008cbc: d10e bne.n 8008cdc { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 8008cbe: 4b06 ldr r3, [pc, #24] ; (8008cd8 ) 8008cc0: 6d9b ldr r3, [r3, #88] ; 0x58 8008cc2: f423 51e0 bic.w r1, r3, #7168 ; 0x1c00 8008cc6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008cca: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8008cce: 4a02 ldr r2, [pc, #8] ; (8008cd8 ) 8008cd0: 430b orrs r3, r1 8008cd2: 6593 str r3, [r2, #88] ; 0x58 8008cd4: e006 b.n 8008ce4 8008cd6: bf00 nop 8008cd8: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8008cdc: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008ce0: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 8008ce4: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008ce8: e9d3 2300 ldrd r2, r3, [r3] 8008cec: f002 0380 and.w r3, r2, #128 ; 0x80 8008cf0: f8c7 3090 str.w r3, [r7, #144] ; 0x90 8008cf4: 2300 movs r3, #0 8008cf6: f8c7 3094 str.w r3, [r7, #148] ; 0x94 8008cfa: e9d7 1224 ldrd r1, r2, [r7, #144] ; 0x90 8008cfe: 460b mov r3, r1 8008d00: 4313 orrs r3, r2 8008d02: d055 beq.n 8008db0 { switch (PeriphClkInit->Lptim345ClockSelection) 8008d04: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008d08: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8008d0c: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 8008d10: d033 beq.n 8008d7a 8008d12: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 8008d16: d82c bhi.n 8008d72 8008d18: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8008d1c: d02f beq.n 8008d7e 8008d1e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8008d22: d826 bhi.n 8008d72 8008d24: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 8008d28: d02b beq.n 8008d82 8008d2a: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 8008d2e: d820 bhi.n 8008d72 8008d30: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8008d34: d012 beq.n 8008d5c 8008d36: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8008d3a: d81a bhi.n 8008d72 8008d3c: 2b00 cmp r3, #0 8008d3e: d022 beq.n 8008d86 8008d40: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8008d44: d115 bne.n 8008d72 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8008d46: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008d4a: 3308 adds r3, #8 8008d4c: 2100 movs r1, #0 8008d4e: 4618 mov r0, r3 8008d50: f001 fbf6 bl 800a540 8008d54: 4603 mov r3, r0 8008d56: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 8008d5a: e015 b.n 8008d88 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8008d5c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008d60: 3328 adds r3, #40 ; 0x28 8008d62: 2102 movs r1, #2 8008d64: 4618 mov r0, r3 8008d66: f001 fc9d bl 800a6a4 8008d6a: 4603 mov r3, r0 8008d6c: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 8008d70: e00a b.n 8008d88 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8008d72: 2301 movs r3, #1 8008d74: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008d78: e006 b.n 8008d88 break; 8008d7a: bf00 nop 8008d7c: e004 b.n 8008d88 break; 8008d7e: bf00 nop 8008d80: e002 b.n 8008d88 break; 8008d82: bf00 nop 8008d84: e000 b.n 8008d88 break; 8008d86: bf00 nop } if (ret == HAL_OK) 8008d88: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008d8c: 2b00 cmp r3, #0 8008d8e: d10b bne.n 8008da8 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 8008d90: 4ba0 ldr r3, [pc, #640] ; (8009014 ) 8008d92: 6d9b ldr r3, [r3, #88] ; 0x58 8008d94: f423 4160 bic.w r1, r3, #57344 ; 0xe000 8008d98: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008d9c: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8008da0: 4a9c ldr r2, [pc, #624] ; (8009014 ) 8008da2: 430b orrs r3, r1 8008da4: 6593 str r3, [r2, #88] ; 0x58 8008da6: e003 b.n 8008db0 } else { /* set overall return value */ status = ret; 8008da8: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008dac: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ #if defined(I2C5) if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) 8008db0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008db4: e9d3 2300 ldrd r2, r3, [r3] 8008db8: f002 0308 and.w r3, r2, #8 8008dbc: f8c7 3088 str.w r3, [r7, #136] ; 0x88 8008dc0: 2300 movs r3, #0 8008dc2: f8c7 308c str.w r3, [r7, #140] ; 0x8c 8008dc6: e9d7 1222 ldrd r1, r2, [r7, #136] ; 0x88 8008dca: 460b mov r3, r1 8008dcc: 4313 orrs r3, r2 8008dce: d01e beq.n 8008e0e { /* Check the parameters */ assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); if ((PeriphClkInit->I2c1235ClockSelection) == RCC_I2C1235CLKSOURCE_PLL3) 8008dd0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008dd4: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8008dd8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8008ddc: d10c bne.n 8008df8 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 8008dde: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008de2: 3328 adds r3, #40 ; 0x28 8008de4: 2102 movs r1, #2 8008de6: 4618 mov r0, r3 8008de8: f001 fc5c bl 800a6a4 8008dec: 4603 mov r3, r0 8008dee: 2b00 cmp r3, #0 8008df0: d002 beq.n 8008df8 { status = HAL_ERROR; 8008df2: 2301 movs r3, #1 8008df4: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); 8008df8: 4b86 ldr r3, [pc, #536] ; (8009014 ) 8008dfa: 6d5b ldr r3, [r3, #84] ; 0x54 8008dfc: f423 5140 bic.w r1, r3, #12288 ; 0x3000 8008e00: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008e04: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8008e08: 4a82 ldr r2, [pc, #520] ; (8009014 ) 8008e0a: 430b orrs r3, r1 8008e0c: 6553 str r3, [r2, #84] ; 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 8008e0e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008e12: e9d3 2300 ldrd r2, r3, [r3] 8008e16: f002 0310 and.w r3, r2, #16 8008e1a: f8c7 3080 str.w r3, [r7, #128] ; 0x80 8008e1e: 2300 movs r3, #0 8008e20: f8c7 3084 str.w r3, [r7, #132] ; 0x84 8008e24: e9d7 1220 ldrd r1, r2, [r7, #128] ; 0x80 8008e28: 460b mov r3, r1 8008e2a: 4313 orrs r3, r2 8008e2c: d01e beq.n 8008e6c { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 8008e2e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008e32: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8008e36: f5b3 7f80 cmp.w r3, #256 ; 0x100 8008e3a: d10c bne.n 8008e56 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 8008e3c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008e40: 3328 adds r3, #40 ; 0x28 8008e42: 2102 movs r1, #2 8008e44: 4618 mov r0, r3 8008e46: f001 fc2d bl 800a6a4 8008e4a: 4603 mov r3, r0 8008e4c: 2b00 cmp r3, #0 8008e4e: d002 beq.n 8008e56 { status = HAL_ERROR; 8008e50: 2301 movs r3, #1 8008e52: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8008e56: 4b6f ldr r3, [pc, #444] ; (8009014 ) 8008e58: 6d9b ldr r3, [r3, #88] ; 0x58 8008e5a: f423 7140 bic.w r1, r3, #768 ; 0x300 8008e5e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008e62: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8008e66: 4a6b ldr r2, [pc, #428] ; (8009014 ) 8008e68: 430b orrs r3, r1 8008e6a: 6593 str r3, [r2, #88] ; 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8008e6c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008e70: e9d3 2300 ldrd r2, r3, [r3] 8008e74: f402 2300 and.w r3, r2, #524288 ; 0x80000 8008e78: 67bb str r3, [r7, #120] ; 0x78 8008e7a: 2300 movs r3, #0 8008e7c: 67fb str r3, [r7, #124] ; 0x7c 8008e7e: e9d7 121e ldrd r1, r2, [r7, #120] ; 0x78 8008e82: 460b mov r3, r1 8008e84: 4313 orrs r3, r2 8008e86: d03e beq.n 8008f06 { switch (PeriphClkInit->AdcClockSelection) 8008e88: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008e8c: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 8008e90: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8008e94: d022 beq.n 8008edc 8008e96: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8008e9a: d81b bhi.n 8008ed4 8008e9c: 2b00 cmp r3, #0 8008e9e: d003 beq.n 8008ea8 8008ea0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8008ea4: d00b beq.n 8008ebe 8008ea6: e015 b.n 8008ed4 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8008ea8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008eac: 3308 adds r3, #8 8008eae: 2100 movs r1, #0 8008eb0: 4618 mov r0, r3 8008eb2: f001 fb45 bl 800a540 8008eb6: 4603 mov r3, r0 8008eb8: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* ADC clock source configuration done later after clock selection check */ break; 8008ebc: e00f b.n 8008ede case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8008ebe: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008ec2: 3328 adds r3, #40 ; 0x28 8008ec4: 2102 movs r1, #2 8008ec6: 4618 mov r0, r3 8008ec8: f001 fbec bl 800a6a4 8008ecc: 4603 mov r3, r0 8008ece: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* ADC clock source configuration done later after clock selection check */ break; 8008ed2: e004 b.n 8008ede /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8008ed4: 2301 movs r3, #1 8008ed6: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008eda: e000 b.n 8008ede break; 8008edc: bf00 nop } if (ret == HAL_OK) 8008ede: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008ee2: 2b00 cmp r3, #0 8008ee4: d10b bne.n 8008efe { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8008ee6: 4b4b ldr r3, [pc, #300] ; (8009014 ) 8008ee8: 6d9b ldr r3, [r3, #88] ; 0x58 8008eea: f423 3140 bic.w r1, r3, #196608 ; 0x30000 8008eee: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008ef2: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 8008ef6: 4a47 ldr r2, [pc, #284] ; (8009014 ) 8008ef8: 430b orrs r3, r1 8008efa: 6593 str r3, [r2, #88] ; 0x58 8008efc: e003 b.n 8008f06 } else { /* set overall return value */ status = ret; 8008efe: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008f02: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8008f06: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008f0a: e9d3 2300 ldrd r2, r3, [r3] 8008f0e: f402 2380 and.w r3, r2, #262144 ; 0x40000 8008f12: 673b str r3, [r7, #112] ; 0x70 8008f14: 2300 movs r3, #0 8008f16: 677b str r3, [r7, #116] ; 0x74 8008f18: e9d7 121c ldrd r1, r2, [r7, #112] ; 0x70 8008f1c: 460b mov r3, r1 8008f1e: 4313 orrs r3, r2 8008f20: d03b beq.n 8008f9a { switch (PeriphClkInit->UsbClockSelection) 8008f22: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008f26: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8008f2a: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8008f2e: d01f beq.n 8008f70 8008f30: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8008f34: d818 bhi.n 8008f68 8008f36: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8008f3a: d003 beq.n 8008f44 8008f3c: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8008f40: d007 beq.n 8008f52 8008f42: e011 b.n 8008f68 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008f44: 4b33 ldr r3, [pc, #204] ; (8009014 ) 8008f46: 6adb ldr r3, [r3, #44] ; 0x2c 8008f48: 4a32 ldr r2, [pc, #200] ; (8009014 ) 8008f4a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8008f4e: 62d3 str r3, [r2, #44] ; 0x2c /* USB clock source configuration done later after clock selection check */ break; 8008f50: e00f b.n 8008f72 case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8008f52: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008f56: 3328 adds r3, #40 ; 0x28 8008f58: 2101 movs r1, #1 8008f5a: 4618 mov r0, r3 8008f5c: f001 fba2 bl 800a6a4 8008f60: 4603 mov r3, r0 8008f62: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* USB clock source configuration done later after clock selection check */ break; 8008f66: e004 b.n 8008f72 /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8008f68: 2301 movs r3, #1 8008f6a: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008f6e: e000 b.n 8008f72 break; 8008f70: bf00 nop } if (ret == HAL_OK) 8008f72: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008f76: 2b00 cmp r3, #0 8008f78: d10b bne.n 8008f92 { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8008f7a: 4b26 ldr r3, [pc, #152] ; (8009014 ) 8008f7c: 6d5b ldr r3, [r3, #84] ; 0x54 8008f7e: f423 1140 bic.w r1, r3, #3145728 ; 0x300000 8008f82: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008f86: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8008f8a: 4a22 ldr r2, [pc, #136] ; (8009014 ) 8008f8c: 430b orrs r3, r1 8008f8e: 6553 str r3, [r2, #84] ; 0x54 8008f90: e003 b.n 8008f9a } else { /* set overall return value */ status = ret; 8008f92: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008f96: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 8008f9a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008f9e: e9d3 2300 ldrd r2, r3, [r3] 8008fa2: f402 3380 and.w r3, r2, #65536 ; 0x10000 8008fa6: 66bb str r3, [r7, #104] ; 0x68 8008fa8: 2300 movs r3, #0 8008faa: 66fb str r3, [r7, #108] ; 0x6c 8008fac: e9d7 121a ldrd r1, r2, [r7, #104] ; 0x68 8008fb0: 460b mov r3, r1 8008fb2: 4313 orrs r3, r2 8008fb4: d034 beq.n 8009020 { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 8008fb6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008fba: 6d1b ldr r3, [r3, #80] ; 0x50 8008fbc: 2b00 cmp r3, #0 8008fbe: d003 beq.n 8008fc8 8008fc0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8008fc4: d007 beq.n 8008fd6 8008fc6: e011 b.n 8008fec { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008fc8: 4b12 ldr r3, [pc, #72] ; (8009014 ) 8008fca: 6adb ldr r3, [r3, #44] ; 0x2c 8008fcc: 4a11 ldr r2, [pc, #68] ; (8009014 ) 8008fce: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8008fd2: 62d3 str r3, [r2, #44] ; 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 8008fd4: e00e b.n 8008ff4 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8008fd6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8008fda: 3308 adds r3, #8 8008fdc: 2102 movs r1, #2 8008fde: 4618 mov r0, r3 8008fe0: f001 faae bl 800a540 8008fe4: 4603 mov r3, r0 8008fe6: f887 3117 strb.w r3, [r7, #279] ; 0x117 /* SDMMC clock source configuration done later after clock selection check */ break; 8008fea: e003 b.n 8008ff4 default: ret = HAL_ERROR; 8008fec: 2301 movs r3, #1 8008fee: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 8008ff2: bf00 nop } if (ret == HAL_OK) 8008ff4: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8008ff8: 2b00 cmp r3, #0 8008ffa: d10d bne.n 8009018 { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 8008ffc: 4b05 ldr r3, [pc, #20] ; (8009014 ) 8008ffe: 6cdb ldr r3, [r3, #76] ; 0x4c 8009000: f423 3180 bic.w r1, r3, #65536 ; 0x10000 8009004: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009008: 6d1b ldr r3, [r3, #80] ; 0x50 800900a: 4a02 ldr r2, [pc, #8] ; (8009014 ) 800900c: 430b orrs r3, r1 800900e: 64d3 str r3, [r2, #76] ; 0x4c 8009010: e006 b.n 8009020 8009012: bf00 nop 8009014: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8009018: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 800901c: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } #if defined(LTDC) /*-------------------------------------- LTDC Configuration -----------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 8009020: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009024: e9d3 2300 ldrd r2, r3, [r3] 8009028: f002 5300 and.w r3, r2, #536870912 ; 0x20000000 800902c: 663b str r3, [r7, #96] ; 0x60 800902e: 2300 movs r3, #0 8009030: 667b str r3, [r7, #100] ; 0x64 8009032: e9d7 1218 ldrd r1, r2, [r7, #96] ; 0x60 8009036: 460b mov r3, r1 8009038: 4313 orrs r3, r2 800903a: d00c beq.n 8009056 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800903c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009040: 3328 adds r3, #40 ; 0x28 8009042: 2102 movs r1, #2 8009044: 4618 mov r0, r3 8009046: f001 fb2d bl 800a6a4 800904a: 4603 mov r3, r0 800904c: 2b00 cmp r3, #0 800904e: d002 beq.n 8009056 { status = HAL_ERROR; 8009050: 2301 movs r3, #1 8009052: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 8009056: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800905a: e9d3 2300 ldrd r2, r3, [r3] 800905e: f402 3300 and.w r3, r2, #131072 ; 0x20000 8009062: 65bb str r3, [r7, #88] ; 0x58 8009064: 2300 movs r3, #0 8009066: 65fb str r3, [r7, #92] ; 0x5c 8009068: e9d7 1216 ldrd r1, r2, [r7, #88] ; 0x58 800906c: 460b mov r3, r1 800906e: 4313 orrs r3, r2 8009070: d036 beq.n 80090e0 { switch (PeriphClkInit->RngClockSelection) 8009072: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009076: 6fdb ldr r3, [r3, #124] ; 0x7c 8009078: f5b3 7f40 cmp.w r3, #768 ; 0x300 800907c: d018 beq.n 80090b0 800907e: f5b3 7f40 cmp.w r3, #768 ; 0x300 8009082: d811 bhi.n 80090a8 8009084: f5b3 7f00 cmp.w r3, #512 ; 0x200 8009088: d014 beq.n 80090b4 800908a: f5b3 7f00 cmp.w r3, #512 ; 0x200 800908e: d80b bhi.n 80090a8 8009090: 2b00 cmp r3, #0 8009092: d011 beq.n 80090b8 8009094: f5b3 7f80 cmp.w r3, #256 ; 0x100 8009098: d106 bne.n 80090a8 { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800909a: 4bb7 ldr r3, [pc, #732] ; (8009378 ) 800909c: 6adb ldr r3, [r3, #44] ; 0x2c 800909e: 4ab6 ldr r2, [pc, #728] ; (8009378 ) 80090a0: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80090a4: 62d3 str r3, [r2, #44] ; 0x2c /* RNG clock source configuration done later after clock selection check */ break; 80090a6: e008 b.n 80090ba /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80090a8: 2301 movs r3, #1 80090aa: f887 3117 strb.w r3, [r7, #279] ; 0x117 break; 80090ae: e004 b.n 80090ba break; 80090b0: bf00 nop 80090b2: e002 b.n 80090ba break; 80090b4: bf00 nop 80090b6: e000 b.n 80090ba break; 80090b8: bf00 nop } if (ret == HAL_OK) 80090ba: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80090be: 2b00 cmp r3, #0 80090c0: d10a bne.n 80090d8 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 80090c2: 4bad ldr r3, [pc, #692] ; (8009378 ) 80090c4: 6d5b ldr r3, [r3, #84] ; 0x54 80090c6: f423 7140 bic.w r1, r3, #768 ; 0x300 80090ca: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80090ce: 6fdb ldr r3, [r3, #124] ; 0x7c 80090d0: 4aa9 ldr r2, [pc, #676] ; (8009378 ) 80090d2: 430b orrs r3, r1 80090d4: 6553 str r3, [r2, #84] ; 0x54 80090d6: e003 b.n 80090e0 } else { /* set overall return value */ status = ret; 80090d8: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80090dc: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 80090e0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80090e4: e9d3 2300 ldrd r2, r3, [r3] 80090e8: f402 1380 and.w r3, r2, #1048576 ; 0x100000 80090ec: 653b str r3, [r7, #80] ; 0x50 80090ee: 2300 movs r3, #0 80090f0: 657b str r3, [r7, #84] ; 0x54 80090f2: e9d7 1214 ldrd r1, r2, [r7, #80] ; 0x50 80090f6: 460b mov r3, r1 80090f8: 4313 orrs r3, r2 80090fa: d009 beq.n 8009110 { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 80090fc: 4b9e ldr r3, [pc, #632] ; (8009378 ) 80090fe: 6d1b ldr r3, [r3, #80] ; 0x50 8009100: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000 8009104: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009108: 6f1b ldr r3, [r3, #112] ; 0x70 800910a: 4a9b ldr r2, [pc, #620] ; (8009378 ) 800910c: 430b orrs r3, r1 800910e: 6513 str r3, [r2, #80] ; 0x50 /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 8009110: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009114: e9d3 2300 ldrd r2, r3, [r3] 8009118: f402 1300 and.w r3, r2, #2097152 ; 0x200000 800911c: 64bb str r3, [r7, #72] ; 0x48 800911e: 2300 movs r3, #0 8009120: 64fb str r3, [r7, #76] ; 0x4c 8009122: e9d7 1212 ldrd r1, r2, [r7, #72] ; 0x48 8009126: 460b mov r3, r1 8009128: 4313 orrs r3, r2 800912a: d009 beq.n 8009140 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800912c: 4b92 ldr r3, [pc, #584] ; (8009378 ) 800912e: 6d1b ldr r3, [r3, #80] ; 0x50 8009130: f023 7180 bic.w r1, r3, #16777216 ; 0x1000000 8009134: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009138: 6e9b ldr r3, [r3, #104] ; 0x68 800913a: 4a8f ldr r2, [pc, #572] ; (8009378 ) 800913c: 430b orrs r3, r1 800913e: 6513 str r3, [r2, #80] ; 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 8009140: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009144: e9d3 2300 ldrd r2, r3, [r3] 8009148: f002 4380 and.w r3, r2, #1073741824 ; 0x40000000 800914c: 643b str r3, [r7, #64] ; 0x40 800914e: 2300 movs r3, #0 8009150: 647b str r3, [r7, #68] ; 0x44 8009152: e9d7 1210 ldrd r1, r2, [r7, #64] ; 0x40 8009156: 460b mov r3, r1 8009158: 4313 orrs r3, r2 800915a: d00e beq.n 800917a { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800915c: 4b86 ldr r3, [pc, #536] ; (8009378 ) 800915e: 691b ldr r3, [r3, #16] 8009160: 4a85 ldr r2, [pc, #532] ; (8009378 ) 8009162: f423 4300 bic.w r3, r3, #32768 ; 0x8000 8009166: 6113 str r3, [r2, #16] 8009168: 4b83 ldr r3, [pc, #524] ; (8009378 ) 800916a: 6919 ldr r1, [r3, #16] 800916c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009170: f8d3 30b4 ldr.w r3, [r3, #180] ; 0xb4 8009174: 4a80 ldr r2, [pc, #512] ; (8009378 ) 8009176: 430b orrs r3, r1 8009178: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800917a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800917e: e9d3 2300 ldrd r2, r3, [r3] 8009182: f002 4300 and.w r3, r2, #2147483648 ; 0x80000000 8009186: 63bb str r3, [r7, #56] ; 0x38 8009188: 2300 movs r3, #0 800918a: 63fb str r3, [r7, #60] ; 0x3c 800918c: e9d7 120e ldrd r1, r2, [r7, #56] ; 0x38 8009190: 460b mov r3, r1 8009192: 4313 orrs r3, r2 8009194: d009 beq.n 80091aa { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 8009196: 4b78 ldr r3, [pc, #480] ; (8009378 ) 8009198: 6cdb ldr r3, [r3, #76] ; 0x4c 800919a: f023 5140 bic.w r1, r3, #805306368 ; 0x30000000 800919e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80091a2: 6d5b ldr r3, [r3, #84] ; 0x54 80091a4: 4a74 ldr r2, [pc, #464] ; (8009378 ) 80091a6: 430b orrs r3, r1 80091a8: 64d3 str r3, [r2, #76] ; 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80091aa: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80091ae: e9d3 2300 ldrd r2, r3, [r3] 80091b2: f402 0300 and.w r3, r2, #8388608 ; 0x800000 80091b6: 633b str r3, [r7, #48] ; 0x30 80091b8: 2300 movs r3, #0 80091ba: 637b str r3, [r7, #52] ; 0x34 80091bc: e9d7 120c ldrd r1, r2, [r7, #48] ; 0x30 80091c0: 460b mov r3, r1 80091c2: 4313 orrs r3, r2 80091c4: d00a beq.n 80091dc { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 80091c6: 4b6c ldr r3, [pc, #432] ; (8009378 ) 80091c8: 6d5b ldr r3, [r3, #84] ; 0x54 80091ca: f423 0140 bic.w r1, r3, #12582912 ; 0xc00000 80091ce: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80091d2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80091d6: 4a68 ldr r2, [pc, #416] ; (8009378 ) 80091d8: 430b orrs r3, r1 80091da: 6553 str r3, [r2, #84] ; 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 80091dc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80091e0: e9d3 2300 ldrd r2, r3, [r3] 80091e4: 2100 movs r1, #0 80091e6: 62b9 str r1, [r7, #40] ; 0x28 80091e8: f003 0301 and.w r3, r3, #1 80091ec: 62fb str r3, [r7, #44] ; 0x2c 80091ee: e9d7 120a ldrd r1, r2, [r7, #40] ; 0x28 80091f2: 460b mov r3, r1 80091f4: 4313 orrs r3, r2 80091f6: d011 beq.n 800921c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80091f8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80091fc: 3308 adds r3, #8 80091fe: 2100 movs r1, #0 8009200: 4618 mov r0, r3 8009202: f001 f99d bl 800a540 8009206: 4603 mov r3, r0 8009208: f887 3117 strb.w r3, [r7, #279] ; 0x117 if (ret == HAL_OK) 800920c: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8009210: 2b00 cmp r3, #0 8009212: d003 beq.n 800921c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8009214: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8009218: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 800921c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009220: e9d3 2300 ldrd r2, r3, [r3] 8009224: 2100 movs r1, #0 8009226: 6239 str r1, [r7, #32] 8009228: f003 0302 and.w r3, r3, #2 800922c: 627b str r3, [r7, #36] ; 0x24 800922e: e9d7 1208 ldrd r1, r2, [r7, #32] 8009232: 460b mov r3, r1 8009234: 4313 orrs r3, r2 8009236: d011 beq.n 800925c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8009238: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800923c: 3308 adds r3, #8 800923e: 2101 movs r1, #1 8009240: 4618 mov r0, r3 8009242: f001 f97d bl 800a540 8009246: 4603 mov r3, r0 8009248: f887 3117 strb.w r3, [r7, #279] ; 0x117 if (ret == HAL_OK) 800924c: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8009250: 2b00 cmp r3, #0 8009252: d003 beq.n 800925c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8009254: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8009258: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800925c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009260: e9d3 2300 ldrd r2, r3, [r3] 8009264: 2100 movs r1, #0 8009266: 61b9 str r1, [r7, #24] 8009268: f003 0304 and.w r3, r3, #4 800926c: 61fb str r3, [r7, #28] 800926e: e9d7 1206 ldrd r1, r2, [r7, #24] 8009272: 460b mov r3, r1 8009274: 4313 orrs r3, r2 8009276: d011 beq.n 800929c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8009278: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800927c: 3308 adds r3, #8 800927e: 2102 movs r1, #2 8009280: 4618 mov r0, r3 8009282: f001 f95d bl 800a540 8009286: 4603 mov r3, r0 8009288: f887 3117 strb.w r3, [r7, #279] ; 0x117 if (ret == HAL_OK) 800928c: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8009290: 2b00 cmp r3, #0 8009292: d003 beq.n 800929c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8009294: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8009298: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800929c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80092a0: e9d3 2300 ldrd r2, r3, [r3] 80092a4: 2100 movs r1, #0 80092a6: 6139 str r1, [r7, #16] 80092a8: f003 0308 and.w r3, r3, #8 80092ac: 617b str r3, [r7, #20] 80092ae: e9d7 1204 ldrd r1, r2, [r7, #16] 80092b2: 460b mov r3, r1 80092b4: 4313 orrs r3, r2 80092b6: d011 beq.n 80092dc { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 80092b8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80092bc: 3328 adds r3, #40 ; 0x28 80092be: 2100 movs r1, #0 80092c0: 4618 mov r0, r3 80092c2: f001 f9ef bl 800a6a4 80092c6: 4603 mov r3, r0 80092c8: f887 3117 strb.w r3, [r7, #279] ; 0x117 if (ret == HAL_OK) 80092cc: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80092d0: 2b00 cmp r3, #0 80092d2: d003 beq.n 80092dc /*Nothing to do*/ } else { /* set overall return value */ status = ret; 80092d4: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 80092d8: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 80092dc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80092e0: e9d3 2300 ldrd r2, r3, [r3] 80092e4: 2100 movs r1, #0 80092e6: 60b9 str r1, [r7, #8] 80092e8: f003 0310 and.w r3, r3, #16 80092ec: 60fb str r3, [r7, #12] 80092ee: e9d7 1202 ldrd r1, r2, [r7, #8] 80092f2: 460b mov r3, r1 80092f4: 4313 orrs r3, r2 80092f6: d011 beq.n 800931c { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 80092f8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 80092fc: 3328 adds r3, #40 ; 0x28 80092fe: 2101 movs r1, #1 8009300: 4618 mov r0, r3 8009302: f001 f9cf bl 800a6a4 8009306: 4603 mov r3, r0 8009308: f887 3117 strb.w r3, [r7, #279] ; 0x117 if (ret == HAL_OK) 800930c: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8009310: 2b00 cmp r3, #0 8009312: d003 beq.n 800931c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8009314: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8009318: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 800931c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 8009320: e9d3 2300 ldrd r2, r3, [r3] 8009324: 2100 movs r1, #0 8009326: 6039 str r1, [r7, #0] 8009328: f003 0320 and.w r3, r3, #32 800932c: 607b str r3, [r7, #4] 800932e: e9d7 1200 ldrd r1, r2, [r7] 8009332: 460b mov r3, r1 8009334: 4313 orrs r3, r2 8009336: d011 beq.n 800935c { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8009338: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 800933c: 3328 adds r3, #40 ; 0x28 800933e: 2102 movs r1, #2 8009340: 4618 mov r0, r3 8009342: f001 f9af bl 800a6a4 8009346: 4603 mov r3, r0 8009348: f887 3117 strb.w r3, [r7, #279] ; 0x117 if (ret == HAL_OK) 800934c: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8009350: 2b00 cmp r3, #0 8009352: d003 beq.n 800935c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8009354: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8009358: f887 3116 strb.w r3, [r7, #278] ; 0x116 } } if (status == HAL_OK) 800935c: f897 3116 ldrb.w r3, [r7, #278] ; 0x116 8009360: 2b00 cmp r3, #0 8009362: d101 bne.n 8009368 { return HAL_OK; 8009364: 2300 movs r3, #0 8009366: e000 b.n 800936a } return HAL_ERROR; 8009368: 2301 movs r3, #1 } 800936a: 4618 mov r0, r3 800936c: f507 778c add.w r7, r7, #280 ; 0x118 8009370: 46bd mov sp, r7 8009372: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8009376: bf00 nop 8009378: 58024400 .word 0x58024400 0800937c : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { 800937c: b580 push {r7, lr} 800937e: b090 sub sp, #64 ; 0x40 8009380: af00 add r7, sp, #0 8009382: e9c7 0100 strd r0, r1, [r7] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 8009386: e9d7 2300 ldrd r2, r3, [r7] 800938a: f5a2 7180 sub.w r1, r2, #256 ; 0x100 800938e: 430b orrs r3, r1 8009390: f040 8094 bne.w 80094bc { saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 8009394: 4b9b ldr r3, [pc, #620] ; (8009604 ) 8009396: 6d1b ldr r3, [r3, #80] ; 0x50 8009398: f003 0307 and.w r3, r3, #7 800939c: 633b str r3, [r7, #48] ; 0x30 switch (saiclocksource) 800939e: 6b3b ldr r3, [r7, #48] ; 0x30 80093a0: 2b04 cmp r3, #4 80093a2: f200 8087 bhi.w 80094b4 80093a6: a201 add r2, pc, #4 ; (adr r2, 80093ac ) 80093a8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80093ac: 080093c1 .word 0x080093c1 80093b0: 080093e9 .word 0x080093e9 80093b4: 08009411 .word 0x08009411 80093b8: 080094ad .word 0x080094ad 80093bc: 08009439 .word 0x08009439 { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 80093c0: 4b90 ldr r3, [pc, #576] ; (8009604 ) 80093c2: 681b ldr r3, [r3, #0] 80093c4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80093c8: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80093cc: d108 bne.n 80093e0 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 80093ce: f107 0324 add.w r3, r7, #36 ; 0x24 80093d2: 4618 mov r0, r3 80093d4: f000 ff62 bl 800a29c frequency = pll1_clocks.PLL1_Q_Frequency; 80093d8: 6abb ldr r3, [r7, #40] ; 0x28 80093da: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80093dc: f000 bc93 b.w 8009d06 frequency = 0; 80093e0: 2300 movs r3, #0 80093e2: 63fb str r3, [r7, #60] ; 0x3c break; 80093e4: f000 bc8f b.w 8009d06 } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80093e8: 4b86 ldr r3, [pc, #536] ; (8009604 ) 80093ea: 681b ldr r3, [r3, #0] 80093ec: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80093f0: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 80093f4: d108 bne.n 8009408 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80093f6: f107 0318 add.w r3, r7, #24 80093fa: 4618 mov r0, r3 80093fc: f000 fca6 bl 8009d4c frequency = pll2_clocks.PLL2_P_Frequency; 8009400: 69bb ldr r3, [r7, #24] 8009402: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009404: f000 bc7f b.w 8009d06 frequency = 0; 8009408: 2300 movs r3, #0 800940a: 63fb str r3, [r7, #60] ; 0x3c break; 800940c: f000 bc7b b.w 8009d06 } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8009410: 4b7c ldr r3, [pc, #496] ; (8009604 ) 8009412: 681b ldr r3, [r3, #0] 8009414: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8009418: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800941c: d108 bne.n 8009430 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800941e: f107 030c add.w r3, r7, #12 8009422: 4618 mov r0, r3 8009424: f000 fde6 bl 8009ff4 frequency = pll3_clocks.PLL3_P_Frequency; 8009428: 68fb ldr r3, [r7, #12] 800942a: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 800942c: f000 bc6b b.w 8009d06 frequency = 0; 8009430: 2300 movs r3, #0 8009432: 63fb str r3, [r7, #60] ; 0x3c break; 8009434: f000 bc67 b.w 8009d06 } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8009438: 4b72 ldr r3, [pc, #456] ; (8009604 ) 800943a: 6cdb ldr r3, [r3, #76] ; 0x4c 800943c: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 8009440: 637b str r3, [r7, #52] ; 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8009442: 4b70 ldr r3, [pc, #448] ; (8009604 ) 8009444: 681b ldr r3, [r3, #0] 8009446: f003 0304 and.w r3, r3, #4 800944a: 2b04 cmp r3, #4 800944c: d10c bne.n 8009468 800944e: 6b7b ldr r3, [r7, #52] ; 0x34 8009450: 2b00 cmp r3, #0 8009452: d109 bne.n 8009468 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8009454: 4b6b ldr r3, [pc, #428] ; (8009604 ) 8009456: 681b ldr r3, [r3, #0] 8009458: 08db lsrs r3, r3, #3 800945a: f003 0303 and.w r3, r3, #3 800945e: 4a6a ldr r2, [pc, #424] ; (8009608 ) 8009460: fa22 f303 lsr.w r3, r2, r3 8009464: 63fb str r3, [r7, #60] ; 0x3c 8009466: e01f b.n 80094a8 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8009468: 4b66 ldr r3, [pc, #408] ; (8009604 ) 800946a: 681b ldr r3, [r3, #0] 800946c: f403 7380 and.w r3, r3, #256 ; 0x100 8009470: f5b3 7f80 cmp.w r3, #256 ; 0x100 8009474: d106 bne.n 8009484 8009476: 6b7b ldr r3, [r7, #52] ; 0x34 8009478: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 800947c: d102 bne.n 8009484 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800947e: 4b63 ldr r3, [pc, #396] ; (800960c ) 8009480: 63fb str r3, [r7, #60] ; 0x3c 8009482: e011 b.n 80094a8 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8009484: 4b5f ldr r3, [pc, #380] ; (8009604 ) 8009486: 681b ldr r3, [r3, #0] 8009488: f403 3300 and.w r3, r3, #131072 ; 0x20000 800948c: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8009490: d106 bne.n 80094a0 8009492: 6b7b ldr r3, [r7, #52] ; 0x34 8009494: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8009498: d102 bne.n 80094a0 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800949a: 4b5d ldr r3, [pc, #372] ; (8009610 ) 800949c: 63fb str r3, [r7, #60] ; 0x3c 800949e: e003 b.n 80094a8 } else { /* In Case the CKPER is disabled*/ frequency = 0; 80094a0: 2300 movs r3, #0 80094a2: 63fb str r3, [r7, #60] ; 0x3c } break; 80094a4: f000 bc2f b.w 8009d06 80094a8: f000 bc2d b.w 8009d06 } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 80094ac: 4b59 ldr r3, [pc, #356] ; (8009614 ) 80094ae: 63fb str r3, [r7, #60] ; 0x3c break; 80094b0: f000 bc29 b.w 8009d06 } default : { frequency = 0; 80094b4: 2300 movs r3, #0 80094b6: 63fb str r3, [r7, #60] ; 0x3c break; 80094b8: f000 bc25 b.w 8009d06 } } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 80094bc: e9d7 2300 ldrd r2, r3, [r7] 80094c0: f5a2 6180 sub.w r1, r2, #1024 ; 0x400 80094c4: 430b orrs r3, r1 80094c6: f040 80a7 bne.w 8009618 { saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 80094ca: 4b4e ldr r3, [pc, #312] ; (8009604 ) 80094cc: 6d9b ldr r3, [r3, #88] ; 0x58 80094ce: f403 0360 and.w r3, r3, #14680064 ; 0xe00000 80094d2: 633b str r3, [r7, #48] ; 0x30 switch (saiclocksource) 80094d4: 6b3b ldr r3, [r7, #48] ; 0x30 80094d6: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 80094da: d054 beq.n 8009586 80094dc: 6b3b ldr r3, [r7, #48] ; 0x30 80094de: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 80094e2: f200 808b bhi.w 80095fc 80094e6: 6b3b ldr r3, [r7, #48] ; 0x30 80094e8: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000 80094ec: f000 8083 beq.w 80095f6 80094f0: 6b3b ldr r3, [r7, #48] ; 0x30 80094f2: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000 80094f6: f200 8081 bhi.w 80095fc 80094fa: 6b3b ldr r3, [r7, #48] ; 0x30 80094fc: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8009500: d02f beq.n 8009562 8009502: 6b3b ldr r3, [r7, #48] ; 0x30 8009504: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8009508: d878 bhi.n 80095fc 800950a: 6b3b ldr r3, [r7, #48] ; 0x30 800950c: 2b00 cmp r3, #0 800950e: d004 beq.n 800951a 8009510: 6b3b ldr r3, [r7, #48] ; 0x30 8009512: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8009516: d012 beq.n 800953e 8009518: e070 b.n 80095fc { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800951a: 4b3a ldr r3, [pc, #232] ; (8009604 ) 800951c: 681b ldr r3, [r3, #0] 800951e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8009522: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8009526: d107 bne.n 8009538 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8009528: f107 0324 add.w r3, r7, #36 ; 0x24 800952c: 4618 mov r0, r3 800952e: f000 feb5 bl 800a29c frequency = pll1_clocks.PLL1_Q_Frequency; 8009532: 6abb ldr r3, [r7, #40] ; 0x28 8009534: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009536: e3e6 b.n 8009d06 frequency = 0; 8009538: 2300 movs r3, #0 800953a: 63fb str r3, [r7, #60] ; 0x3c break; 800953c: e3e3 b.n 8009d06 } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800953e: 4b31 ldr r3, [pc, #196] ; (8009604 ) 8009540: 681b ldr r3, [r3, #0] 8009542: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8009546: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 800954a: d107 bne.n 800955c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800954c: f107 0318 add.w r3, r7, #24 8009550: 4618 mov r0, r3 8009552: f000 fbfb bl 8009d4c frequency = pll2_clocks.PLL2_P_Frequency; 8009556: 69bb ldr r3, [r7, #24] 8009558: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 800955a: e3d4 b.n 8009d06 frequency = 0; 800955c: 2300 movs r3, #0 800955e: 63fb str r3, [r7, #60] ; 0x3c break; 8009560: e3d1 b.n 8009d06 } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8009562: 4b28 ldr r3, [pc, #160] ; (8009604 ) 8009564: 681b ldr r3, [r3, #0] 8009566: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800956a: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800956e: d107 bne.n 8009580 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8009570: f107 030c add.w r3, r7, #12 8009574: 4618 mov r0, r3 8009576: f000 fd3d bl 8009ff4 frequency = pll3_clocks.PLL3_P_Frequency; 800957a: 68fb ldr r3, [r7, #12] 800957c: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 800957e: e3c2 b.n 8009d06 frequency = 0; 8009580: 2300 movs r3, #0 8009582: 63fb str r3, [r7, #60] ; 0x3c break; 8009584: e3bf b.n 8009d06 } case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8009586: 4b1f ldr r3, [pc, #124] ; (8009604 ) 8009588: 6cdb ldr r3, [r3, #76] ; 0x4c 800958a: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 800958e: 637b str r3, [r7, #52] ; 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8009590: 4b1c ldr r3, [pc, #112] ; (8009604 ) 8009592: 681b ldr r3, [r3, #0] 8009594: f003 0304 and.w r3, r3, #4 8009598: 2b04 cmp r3, #4 800959a: d10c bne.n 80095b6 800959c: 6b7b ldr r3, [r7, #52] ; 0x34 800959e: 2b00 cmp r3, #0 80095a0: d109 bne.n 80095b6 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80095a2: 4b18 ldr r3, [pc, #96] ; (8009604 ) 80095a4: 681b ldr r3, [r3, #0] 80095a6: 08db lsrs r3, r3, #3 80095a8: f003 0303 and.w r3, r3, #3 80095ac: 4a16 ldr r2, [pc, #88] ; (8009608 ) 80095ae: fa22 f303 lsr.w r3, r2, r3 80095b2: 63fb str r3, [r7, #60] ; 0x3c 80095b4: e01e b.n 80095f4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 80095b6: 4b13 ldr r3, [pc, #76] ; (8009604 ) 80095b8: 681b ldr r3, [r3, #0] 80095ba: f403 7380 and.w r3, r3, #256 ; 0x100 80095be: f5b3 7f80 cmp.w r3, #256 ; 0x100 80095c2: d106 bne.n 80095d2 80095c4: 6b7b ldr r3, [r7, #52] ; 0x34 80095c6: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 80095ca: d102 bne.n 80095d2 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 80095cc: 4b0f ldr r3, [pc, #60] ; (800960c ) 80095ce: 63fb str r3, [r7, #60] ; 0x3c 80095d0: e010 b.n 80095f4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 80095d2: 4b0c ldr r3, [pc, #48] ; (8009604 ) 80095d4: 681b ldr r3, [r3, #0] 80095d6: f403 3300 and.w r3, r3, #131072 ; 0x20000 80095da: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80095de: d106 bne.n 80095ee 80095e0: 6b7b ldr r3, [r7, #52] ; 0x34 80095e2: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80095e6: d102 bne.n 80095ee { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 80095e8: 4b09 ldr r3, [pc, #36] ; (8009610 ) 80095ea: 63fb str r3, [r7, #60] ; 0x3c 80095ec: e002 b.n 80095f4 } else { /* In Case the CKPER is disabled*/ frequency = 0; 80095ee: 2300 movs r3, #0 80095f0: 63fb str r3, [r7, #60] ; 0x3c } break; 80095f2: e388 b.n 8009d06 80095f4: e387 b.n 8009d06 } case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; 80095f6: 4b07 ldr r3, [pc, #28] ; (8009614 ) 80095f8: 63fb str r3, [r7, #60] ; 0x3c break; 80095fa: e384 b.n 8009d06 } default : { frequency = 0; 80095fc: 2300 movs r3, #0 80095fe: 63fb str r3, [r7, #60] ; 0x3c break; 8009600: e381 b.n 8009d06 8009602: bf00 nop 8009604: 58024400 .word 0x58024400 8009608: 03d09000 .word 0x03d09000 800960c: 003d0900 .word 0x003d0900 8009610: 017d7840 .word 0x017d7840 8009614: 00bb8000 .word 0x00bb8000 } } } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 8009618: e9d7 2300 ldrd r2, r3, [r7] 800961c: f5a2 6100 sub.w r1, r2, #2048 ; 0x800 8009620: 430b orrs r3, r1 8009622: f040 809c bne.w 800975e { saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 8009626: 4b9e ldr r3, [pc, #632] ; (80098a0 ) 8009628: 6d9b ldr r3, [r3, #88] ; 0x58 800962a: f003 63e0 and.w r3, r3, #117440512 ; 0x7000000 800962e: 633b str r3, [r7, #48] ; 0x30 switch (saiclocksource) 8009630: 6b3b ldr r3, [r7, #48] ; 0x30 8009632: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 8009636: d054 beq.n 80096e2 8009638: 6b3b ldr r3, [r7, #48] ; 0x30 800963a: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 800963e: f200 808b bhi.w 8009758 8009642: 6b3b ldr r3, [r7, #48] ; 0x30 8009644: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000 8009648: f000 8083 beq.w 8009752 800964c: 6b3b ldr r3, [r7, #48] ; 0x30 800964e: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000 8009652: f200 8081 bhi.w 8009758 8009656: 6b3b ldr r3, [r7, #48] ; 0x30 8009658: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800965c: d02f beq.n 80096be 800965e: 6b3b ldr r3, [r7, #48] ; 0x30 8009660: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8009664: d878 bhi.n 8009758 8009666: 6b3b ldr r3, [r7, #48] ; 0x30 8009668: 2b00 cmp r3, #0 800966a: d004 beq.n 8009676 800966c: 6b3b ldr r3, [r7, #48] ; 0x30 800966e: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8009672: d012 beq.n 800969a 8009674: e070 b.n 8009758 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8009676: 4b8a ldr r3, [pc, #552] ; (80098a0 ) 8009678: 681b ldr r3, [r3, #0] 800967a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800967e: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8009682: d107 bne.n 8009694 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8009684: f107 0324 add.w r3, r7, #36 ; 0x24 8009688: 4618 mov r0, r3 800968a: f000 fe07 bl 800a29c frequency = pll1_clocks.PLL1_Q_Frequency; 800968e: 6abb ldr r3, [r7, #40] ; 0x28 8009690: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009692: e338 b.n 8009d06 frequency = 0; 8009694: 2300 movs r3, #0 8009696: 63fb str r3, [r7, #60] ; 0x3c break; 8009698: e335 b.n 8009d06 } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800969a: 4b81 ldr r3, [pc, #516] ; (80098a0 ) 800969c: 681b ldr r3, [r3, #0] 800969e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80096a2: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 80096a6: d107 bne.n 80096b8 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80096a8: f107 0318 add.w r3, r7, #24 80096ac: 4618 mov r0, r3 80096ae: f000 fb4d bl 8009d4c frequency = pll2_clocks.PLL2_P_Frequency; 80096b2: 69bb ldr r3, [r7, #24] 80096b4: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80096b6: e326 b.n 8009d06 frequency = 0; 80096b8: 2300 movs r3, #0 80096ba: 63fb str r3, [r7, #60] ; 0x3c break; 80096bc: e323 b.n 8009d06 } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80096be: 4b78 ldr r3, [pc, #480] ; (80098a0 ) 80096c0: 681b ldr r3, [r3, #0] 80096c2: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 80096c6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80096ca: d107 bne.n 80096dc { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80096cc: f107 030c add.w r3, r7, #12 80096d0: 4618 mov r0, r3 80096d2: f000 fc8f bl 8009ff4 frequency = pll3_clocks.PLL3_P_Frequency; 80096d6: 68fb ldr r3, [r7, #12] 80096d8: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80096da: e314 b.n 8009d06 frequency = 0; 80096dc: 2300 movs r3, #0 80096de: 63fb str r3, [r7, #60] ; 0x3c break; 80096e0: e311 b.n 8009d06 } case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 80096e2: 4b6f ldr r3, [pc, #444] ; (80098a0 ) 80096e4: 6cdb ldr r3, [r3, #76] ; 0x4c 80096e6: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 80096ea: 637b str r3, [r7, #52] ; 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 80096ec: 4b6c ldr r3, [pc, #432] ; (80098a0 ) 80096ee: 681b ldr r3, [r3, #0] 80096f0: f003 0304 and.w r3, r3, #4 80096f4: 2b04 cmp r3, #4 80096f6: d10c bne.n 8009712 80096f8: 6b7b ldr r3, [r7, #52] ; 0x34 80096fa: 2b00 cmp r3, #0 80096fc: d109 bne.n 8009712 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80096fe: 4b68 ldr r3, [pc, #416] ; (80098a0 ) 8009700: 681b ldr r3, [r3, #0] 8009702: 08db lsrs r3, r3, #3 8009704: f003 0303 and.w r3, r3, #3 8009708: 4a66 ldr r2, [pc, #408] ; (80098a4 ) 800970a: fa22 f303 lsr.w r3, r2, r3 800970e: 63fb str r3, [r7, #60] ; 0x3c 8009710: e01e b.n 8009750 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8009712: 4b63 ldr r3, [pc, #396] ; (80098a0 ) 8009714: 681b ldr r3, [r3, #0] 8009716: f403 7380 and.w r3, r3, #256 ; 0x100 800971a: f5b3 7f80 cmp.w r3, #256 ; 0x100 800971e: d106 bne.n 800972e 8009720: 6b7b ldr r3, [r7, #52] ; 0x34 8009722: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8009726: d102 bne.n 800972e { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 8009728: 4b5f ldr r3, [pc, #380] ; (80098a8 ) 800972a: 63fb str r3, [r7, #60] ; 0x3c 800972c: e010 b.n 8009750 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800972e: 4b5c ldr r3, [pc, #368] ; (80098a0 ) 8009730: 681b ldr r3, [r3, #0] 8009732: f403 3300 and.w r3, r3, #131072 ; 0x20000 8009736: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 800973a: d106 bne.n 800974a 800973c: 6b7b ldr r3, [r7, #52] ; 0x34 800973e: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8009742: d102 bne.n 800974a { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 8009744: 4b59 ldr r3, [pc, #356] ; (80098ac ) 8009746: 63fb str r3, [r7, #60] ; 0x3c 8009748: e002 b.n 8009750 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800974a: 2300 movs r3, #0 800974c: 63fb str r3, [r7, #60] ; 0x3c } break; 800974e: e2da b.n 8009d06 8009750: e2d9 b.n 8009d06 } case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; 8009752: 4b57 ldr r3, [pc, #348] ; (80098b0 ) 8009754: 63fb str r3, [r7, #60] ; 0x3c break; 8009756: e2d6 b.n 8009d06 } default : { frequency = 0; 8009758: 2300 movs r3, #0 800975a: 63fb str r3, [r7, #60] ; 0x3c break; 800975c: e2d3 b.n 8009d06 } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 800975e: e9d7 2300 ldrd r2, r3, [r7] 8009762: f5a2 5180 sub.w r1, r2, #4096 ; 0x1000 8009766: 430b orrs r3, r1 8009768: f040 80a7 bne.w 80098ba { /* Get SPI1/2/3 clock source */ srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 800976c: 4b4c ldr r3, [pc, #304] ; (80098a0 ) 800976e: 6d1b ldr r3, [r3, #80] ; 0x50 8009770: f403 43e0 and.w r3, r3, #28672 ; 0x7000 8009774: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 8009776: 6bbb ldr r3, [r7, #56] ; 0x38 8009778: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 800977c: d055 beq.n 800982a 800977e: 6bbb ldr r3, [r7, #56] ; 0x38 8009780: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8009784: f200 8096 bhi.w 80098b4 8009788: 6bbb ldr r3, [r7, #56] ; 0x38 800978a: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 800978e: f000 8084 beq.w 800989a 8009792: 6bbb ldr r3, [r7, #56] ; 0x38 8009794: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 8009798: f200 808c bhi.w 80098b4 800979c: 6bbb ldr r3, [r7, #56] ; 0x38 800979e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80097a2: d030 beq.n 8009806 80097a4: 6bbb ldr r3, [r7, #56] ; 0x38 80097a6: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80097aa: f200 8083 bhi.w 80098b4 80097ae: 6bbb ldr r3, [r7, #56] ; 0x38 80097b0: 2b00 cmp r3, #0 80097b2: d004 beq.n 80097be 80097b4: 6bbb ldr r3, [r7, #56] ; 0x38 80097b6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80097ba: d012 beq.n 80097e2 80097bc: e07a b.n 80098b4 { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 80097be: 4b38 ldr r3, [pc, #224] ; (80098a0 ) 80097c0: 681b ldr r3, [r3, #0] 80097c2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80097c6: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80097ca: d107 bne.n 80097dc { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 80097cc: f107 0324 add.w r3, r7, #36 ; 0x24 80097d0: 4618 mov r0, r3 80097d2: f000 fd63 bl 800a29c frequency = pll1_clocks.PLL1_Q_Frequency; 80097d6: 6abb ldr r3, [r7, #40] ; 0x28 80097d8: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80097da: e294 b.n 8009d06 frequency = 0; 80097dc: 2300 movs r3, #0 80097de: 63fb str r3, [r7, #60] ; 0x3c break; 80097e0: e291 b.n 8009d06 } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80097e2: 4b2f ldr r3, [pc, #188] ; (80098a0 ) 80097e4: 681b ldr r3, [r3, #0] 80097e6: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80097ea: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 80097ee: d107 bne.n 8009800 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80097f0: f107 0318 add.w r3, r7, #24 80097f4: 4618 mov r0, r3 80097f6: f000 faa9 bl 8009d4c frequency = pll2_clocks.PLL2_P_Frequency; 80097fa: 69bb ldr r3, [r7, #24] 80097fc: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80097fe: e282 b.n 8009d06 frequency = 0; 8009800: 2300 movs r3, #0 8009802: 63fb str r3, [r7, #60] ; 0x3c break; 8009804: e27f b.n 8009d06 } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8009806: 4b26 ldr r3, [pc, #152] ; (80098a0 ) 8009808: 681b ldr r3, [r3, #0] 800980a: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800980e: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8009812: d107 bne.n 8009824 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8009814: f107 030c add.w r3, r7, #12 8009818: 4618 mov r0, r3 800981a: f000 fbeb bl 8009ff4 frequency = pll3_clocks.PLL3_P_Frequency; 800981e: 68fb ldr r3, [r7, #12] 8009820: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009822: e270 b.n 8009d06 frequency = 0; 8009824: 2300 movs r3, #0 8009826: 63fb str r3, [r7, #60] ; 0x3c break; 8009828: e26d b.n 8009d06 } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800982a: 4b1d ldr r3, [pc, #116] ; (80098a0 ) 800982c: 6cdb ldr r3, [r3, #76] ; 0x4c 800982e: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 8009832: 637b str r3, [r7, #52] ; 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8009834: 4b1a ldr r3, [pc, #104] ; (80098a0 ) 8009836: 681b ldr r3, [r3, #0] 8009838: f003 0304 and.w r3, r3, #4 800983c: 2b04 cmp r3, #4 800983e: d10c bne.n 800985a 8009840: 6b7b ldr r3, [r7, #52] ; 0x34 8009842: 2b00 cmp r3, #0 8009844: d109 bne.n 800985a { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8009846: 4b16 ldr r3, [pc, #88] ; (80098a0 ) 8009848: 681b ldr r3, [r3, #0] 800984a: 08db lsrs r3, r3, #3 800984c: f003 0303 and.w r3, r3, #3 8009850: 4a14 ldr r2, [pc, #80] ; (80098a4 ) 8009852: fa22 f303 lsr.w r3, r2, r3 8009856: 63fb str r3, [r7, #60] ; 0x3c 8009858: e01e b.n 8009898 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800985a: 4b11 ldr r3, [pc, #68] ; (80098a0 ) 800985c: 681b ldr r3, [r3, #0] 800985e: f403 7380 and.w r3, r3, #256 ; 0x100 8009862: f5b3 7f80 cmp.w r3, #256 ; 0x100 8009866: d106 bne.n 8009876 8009868: 6b7b ldr r3, [r7, #52] ; 0x34 800986a: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 800986e: d102 bne.n 8009876 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 8009870: 4b0d ldr r3, [pc, #52] ; (80098a8 ) 8009872: 63fb str r3, [r7, #60] ; 0x3c 8009874: e010 b.n 8009898 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8009876: 4b0a ldr r3, [pc, #40] ; (80098a0 ) 8009878: 681b ldr r3, [r3, #0] 800987a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800987e: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8009882: d106 bne.n 8009892 8009884: 6b7b ldr r3, [r7, #52] ; 0x34 8009886: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800988a: d102 bne.n 8009892 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800988c: 4b07 ldr r3, [pc, #28] ; (80098ac ) 800988e: 63fb str r3, [r7, #60] ; 0x3c 8009890: e002 b.n 8009898 } else { /* In Case the CKPER is disabled*/ frequency = 0; 8009892: 2300 movs r3, #0 8009894: 63fb str r3, [r7, #60] ; 0x3c } break; 8009896: e236 b.n 8009d06 8009898: e235 b.n 8009d06 } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 800989a: 4b05 ldr r3, [pc, #20] ; (80098b0 ) 800989c: 63fb str r3, [r7, #60] ; 0x3c break; 800989e: e232 b.n 8009d06 80098a0: 58024400 .word 0x58024400 80098a4: 03d09000 .word 0x03d09000 80098a8: 003d0900 .word 0x003d0900 80098ac: 017d7840 .word 0x017d7840 80098b0: 00bb8000 .word 0x00bb8000 } default : { frequency = 0; 80098b4: 2300 movs r3, #0 80098b6: 63fb str r3, [r7, #60] ; 0x3c break; 80098b8: e225 b.n 8009d06 } } } else if (PeriphClk == RCC_PERIPHCLK_SPI45) 80098ba: e9d7 2300 ldrd r2, r3, [r7] 80098be: f5a2 5100 sub.w r1, r2, #8192 ; 0x2000 80098c2: 430b orrs r3, r1 80098c4: f040 8085 bne.w 80099d2 { /* Get SPI45 clock source */ srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 80098c8: 4b9c ldr r3, [pc, #624] ; (8009b3c ) 80098ca: 6d1b ldr r3, [r3, #80] ; 0x50 80098cc: f403 23e0 and.w r3, r3, #458752 ; 0x70000 80098d0: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 80098d2: 6bbb ldr r3, [r7, #56] ; 0x38 80098d4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80098d8: d06b beq.n 80099b2 80098da: 6bbb ldr r3, [r7, #56] ; 0x38 80098dc: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80098e0: d874 bhi.n 80099cc 80098e2: 6bbb ldr r3, [r7, #56] ; 0x38 80098e4: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 80098e8: d056 beq.n 8009998 80098ea: 6bbb ldr r3, [r7, #56] ; 0x38 80098ec: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 80098f0: d86c bhi.n 80099cc 80098f2: 6bbb ldr r3, [r7, #56] ; 0x38 80098f4: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 80098f8: d03b beq.n 8009972 80098fa: 6bbb ldr r3, [r7, #56] ; 0x38 80098fc: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 8009900: d864 bhi.n 80099cc 8009902: 6bbb ldr r3, [r7, #56] ; 0x38 8009904: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8009908: d021 beq.n 800994e 800990a: 6bbb ldr r3, [r7, #56] ; 0x38 800990c: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8009910: d85c bhi.n 80099cc 8009912: 6bbb ldr r3, [r7, #56] ; 0x38 8009914: 2b00 cmp r3, #0 8009916: d004 beq.n 8009922 8009918: 6bbb ldr r3, [r7, #56] ; 0x38 800991a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800991e: d004 beq.n 800992a 8009920: e054 b.n 80099cc { case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ { frequency = HAL_RCC_GetPCLK1Freq(); 8009922: f7fe fb1d bl 8007f60 8009926: 63f8 str r0, [r7, #60] ; 0x3c break; 8009928: e1ed b.n 8009d06 } case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800992a: 4b84 ldr r3, [pc, #528] ; (8009b3c ) 800992c: 681b ldr r3, [r3, #0] 800992e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8009932: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8009936: d107 bne.n 8009948 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8009938: f107 0318 add.w r3, r7, #24 800993c: 4618 mov r0, r3 800993e: f000 fa05 bl 8009d4c frequency = pll2_clocks.PLL2_Q_Frequency; 8009942: 69fb ldr r3, [r7, #28] 8009944: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009946: e1de b.n 8009d06 frequency = 0; 8009948: 2300 movs r3, #0 800994a: 63fb str r3, [r7, #60] ; 0x3c break; 800994c: e1db b.n 8009d06 } case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800994e: 4b7b ldr r3, [pc, #492] ; (8009b3c ) 8009950: 681b ldr r3, [r3, #0] 8009952: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8009956: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800995a: d107 bne.n 800996c { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800995c: f107 030c add.w r3, r7, #12 8009960: 4618 mov r0, r3 8009962: f000 fb47 bl 8009ff4 frequency = pll3_clocks.PLL3_Q_Frequency; 8009966: 693b ldr r3, [r7, #16] 8009968: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 800996a: e1cc b.n 8009d06 frequency = 0; 800996c: 2300 movs r3, #0 800996e: 63fb str r3, [r7, #60] ; 0x3c break; 8009970: e1c9 b.n 8009d06 } case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 8009972: 4b72 ldr r3, [pc, #456] ; (8009b3c ) 8009974: 681b ldr r3, [r3, #0] 8009976: f003 0304 and.w r3, r3, #4 800997a: 2b04 cmp r3, #4 800997c: d109 bne.n 8009992 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800997e: 4b6f ldr r3, [pc, #444] ; (8009b3c ) 8009980: 681b ldr r3, [r3, #0] 8009982: 08db lsrs r3, r3, #3 8009984: f003 0303 and.w r3, r3, #3 8009988: 4a6d ldr r2, [pc, #436] ; (8009b40 ) 800998a: fa22 f303 lsr.w r3, r2, r3 800998e: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009990: e1b9 b.n 8009d06 frequency = 0; 8009992: 2300 movs r3, #0 8009994: 63fb str r3, [r7, #60] ; 0x3c break; 8009996: e1b6 b.n 8009d06 } case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 8009998: 4b68 ldr r3, [pc, #416] ; (8009b3c ) 800999a: 681b ldr r3, [r3, #0] 800999c: f403 7380 and.w r3, r3, #256 ; 0x100 80099a0: f5b3 7f80 cmp.w r3, #256 ; 0x100 80099a4: d102 bne.n 80099ac { frequency = CSI_VALUE; 80099a6: 4b67 ldr r3, [pc, #412] ; (8009b44 ) 80099a8: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80099aa: e1ac b.n 8009d06 frequency = 0; 80099ac: 2300 movs r3, #0 80099ae: 63fb str r3, [r7, #60] ; 0x3c break; 80099b0: e1a9 b.n 8009d06 } case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 80099b2: 4b62 ldr r3, [pc, #392] ; (8009b3c ) 80099b4: 681b ldr r3, [r3, #0] 80099b6: f403 3300 and.w r3, r3, #131072 ; 0x20000 80099ba: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80099be: d102 bne.n 80099c6 { frequency = HSE_VALUE; 80099c0: 4b61 ldr r3, [pc, #388] ; (8009b48 ) 80099c2: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80099c4: e19f b.n 8009d06 frequency = 0; 80099c6: 2300 movs r3, #0 80099c8: 63fb str r3, [r7, #60] ; 0x3c break; 80099ca: e19c b.n 8009d06 } default : { frequency = 0; 80099cc: 2300 movs r3, #0 80099ce: 63fb str r3, [r7, #60] ; 0x3c break; 80099d0: e199 b.n 8009d06 } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 80099d2: e9d7 2300 ldrd r2, r3, [r7] 80099d6: f5a2 2100 sub.w r1, r2, #524288 ; 0x80000 80099da: 430b orrs r3, r1 80099dc: d173 bne.n 8009ac6 { /* Get ADC clock source */ srcclk = __HAL_RCC_GET_ADC_SOURCE(); 80099de: 4b57 ldr r3, [pc, #348] ; (8009b3c ) 80099e0: 6d9b ldr r3, [r3, #88] ; 0x58 80099e2: f403 3340 and.w r3, r3, #196608 ; 0x30000 80099e6: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 80099e8: 6bbb ldr r3, [r7, #56] ; 0x38 80099ea: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80099ee: d02f beq.n 8009a50 80099f0: 6bbb ldr r3, [r7, #56] ; 0x38 80099f2: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80099f6: d863 bhi.n 8009ac0 80099f8: 6bbb ldr r3, [r7, #56] ; 0x38 80099fa: 2b00 cmp r3, #0 80099fc: d004 beq.n 8009a08 80099fe: 6bbb ldr r3, [r7, #56] ; 0x38 8009a00: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8009a04: d012 beq.n 8009a2c 8009a06: e05b b.n 8009ac0 { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8009a08: 4b4c ldr r3, [pc, #304] ; (8009b3c ) 8009a0a: 681b ldr r3, [r3, #0] 8009a0c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8009a10: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8009a14: d107 bne.n 8009a26 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8009a16: f107 0318 add.w r3, r7, #24 8009a1a: 4618 mov r0, r3 8009a1c: f000 f996 bl 8009d4c frequency = pll2_clocks.PLL2_P_Frequency; 8009a20: 69bb ldr r3, [r7, #24] 8009a22: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009a24: e16f b.n 8009d06 frequency = 0; 8009a26: 2300 movs r3, #0 8009a28: 63fb str r3, [r7, #60] ; 0x3c break; 8009a2a: e16c b.n 8009d06 } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8009a2c: 4b43 ldr r3, [pc, #268] ; (8009b3c ) 8009a2e: 681b ldr r3, [r3, #0] 8009a30: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8009a34: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8009a38: d107 bne.n 8009a4a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8009a3a: f107 030c add.w r3, r7, #12 8009a3e: 4618 mov r0, r3 8009a40: f000 fad8 bl 8009ff4 frequency = pll3_clocks.PLL3_R_Frequency; 8009a44: 697b ldr r3, [r7, #20] 8009a46: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009a48: e15d b.n 8009d06 frequency = 0; 8009a4a: 2300 movs r3, #0 8009a4c: 63fb str r3, [r7, #60] ; 0x3c break; 8009a4e: e15a b.n 8009d06 } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8009a50: 4b3a ldr r3, [pc, #232] ; (8009b3c ) 8009a52: 6cdb ldr r3, [r3, #76] ; 0x4c 8009a54: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 8009a58: 637b str r3, [r7, #52] ; 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8009a5a: 4b38 ldr r3, [pc, #224] ; (8009b3c ) 8009a5c: 681b ldr r3, [r3, #0] 8009a5e: f003 0304 and.w r3, r3, #4 8009a62: 2b04 cmp r3, #4 8009a64: d10c bne.n 8009a80 8009a66: 6b7b ldr r3, [r7, #52] ; 0x34 8009a68: 2b00 cmp r3, #0 8009a6a: d109 bne.n 8009a80 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8009a6c: 4b33 ldr r3, [pc, #204] ; (8009b3c ) 8009a6e: 681b ldr r3, [r3, #0] 8009a70: 08db lsrs r3, r3, #3 8009a72: f003 0303 and.w r3, r3, #3 8009a76: 4a32 ldr r2, [pc, #200] ; (8009b40 ) 8009a78: fa22 f303 lsr.w r3, r2, r3 8009a7c: 63fb str r3, [r7, #60] ; 0x3c 8009a7e: e01e b.n 8009abe } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8009a80: 4b2e ldr r3, [pc, #184] ; (8009b3c ) 8009a82: 681b ldr r3, [r3, #0] 8009a84: f403 7380 and.w r3, r3, #256 ; 0x100 8009a88: f5b3 7f80 cmp.w r3, #256 ; 0x100 8009a8c: d106 bne.n 8009a9c 8009a8e: 6b7b ldr r3, [r7, #52] ; 0x34 8009a90: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8009a94: d102 bne.n 8009a9c { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 8009a96: 4b2b ldr r3, [pc, #172] ; (8009b44 ) 8009a98: 63fb str r3, [r7, #60] ; 0x3c 8009a9a: e010 b.n 8009abe } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8009a9c: 4b27 ldr r3, [pc, #156] ; (8009b3c ) 8009a9e: 681b ldr r3, [r3, #0] 8009aa0: f403 3300 and.w r3, r3, #131072 ; 0x20000 8009aa4: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8009aa8: d106 bne.n 8009ab8 8009aaa: 6b7b ldr r3, [r7, #52] ; 0x34 8009aac: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8009ab0: d102 bne.n 8009ab8 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 8009ab2: 4b25 ldr r3, [pc, #148] ; (8009b48 ) 8009ab4: 63fb str r3, [r7, #60] ; 0x3c 8009ab6: e002 b.n 8009abe } else { /* In Case the CKPER is disabled*/ frequency = 0; 8009ab8: 2300 movs r3, #0 8009aba: 63fb str r3, [r7, #60] ; 0x3c } break; 8009abc: e123 b.n 8009d06 8009abe: e122 b.n 8009d06 } default : { frequency = 0; 8009ac0: 2300 movs r3, #0 8009ac2: 63fb str r3, [r7, #60] ; 0x3c break; 8009ac4: e11f b.n 8009d06 } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 8009ac6: e9d7 2300 ldrd r2, r3, [r7] 8009aca: f5a2 3180 sub.w r1, r2, #65536 ; 0x10000 8009ace: 430b orrs r3, r1 8009ad0: d13c bne.n 8009b4c { /* Get SDMMC clock source */ srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 8009ad2: 4b1a ldr r3, [pc, #104] ; (8009b3c ) 8009ad4: 6cdb ldr r3, [r3, #76] ; 0x4c 8009ad6: f403 3380 and.w r3, r3, #65536 ; 0x10000 8009ada: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 8009adc: 6bbb ldr r3, [r7, #56] ; 0x38 8009ade: 2b00 cmp r3, #0 8009ae0: d004 beq.n 8009aec 8009ae2: 6bbb ldr r3, [r7, #56] ; 0x38 8009ae4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8009ae8: d012 beq.n 8009b10 8009aea: e023 b.n 8009b34 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8009aec: 4b13 ldr r3, [pc, #76] ; (8009b3c ) 8009aee: 681b ldr r3, [r3, #0] 8009af0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8009af4: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8009af8: d107 bne.n 8009b0a { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8009afa: f107 0324 add.w r3, r7, #36 ; 0x24 8009afe: 4618 mov r0, r3 8009b00: f000 fbcc bl 800a29c frequency = pll1_clocks.PLL1_Q_Frequency; 8009b04: 6abb ldr r3, [r7, #40] ; 0x28 8009b06: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009b08: e0fd b.n 8009d06 frequency = 0; 8009b0a: 2300 movs r3, #0 8009b0c: 63fb str r3, [r7, #60] ; 0x3c break; 8009b0e: e0fa b.n 8009d06 } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8009b10: 4b0a ldr r3, [pc, #40] ; (8009b3c ) 8009b12: 681b ldr r3, [r3, #0] 8009b14: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8009b18: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8009b1c: d107 bne.n 8009b2e { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8009b1e: f107 0318 add.w r3, r7, #24 8009b22: 4618 mov r0, r3 8009b24: f000 f912 bl 8009d4c frequency = pll2_clocks.PLL2_R_Frequency; 8009b28: 6a3b ldr r3, [r7, #32] 8009b2a: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009b2c: e0eb b.n 8009d06 frequency = 0; 8009b2e: 2300 movs r3, #0 8009b30: 63fb str r3, [r7, #60] ; 0x3c break; 8009b32: e0e8 b.n 8009d06 } default : { frequency = 0; 8009b34: 2300 movs r3, #0 8009b36: 63fb str r3, [r7, #60] ; 0x3c break; 8009b38: e0e5 b.n 8009d06 8009b3a: bf00 nop 8009b3c: 58024400 .word 0x58024400 8009b40: 03d09000 .word 0x03d09000 8009b44: 003d0900 .word 0x003d0900 8009b48: 017d7840 .word 0x017d7840 } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 8009b4c: e9d7 2300 ldrd r2, r3, [r7] 8009b50: f5a2 4180 sub.w r1, r2, #16384 ; 0x4000 8009b54: 430b orrs r3, r1 8009b56: f040 8085 bne.w 8009c64 { /* Get SPI6 clock source */ srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 8009b5a: 4b6d ldr r3, [pc, #436] ; (8009d10 ) 8009b5c: 6d9b ldr r3, [r3, #88] ; 0x58 8009b5e: f003 43e0 and.w r3, r3, #1879048192 ; 0x70000000 8009b62: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 8009b64: 6bbb ldr r3, [r7, #56] ; 0x38 8009b66: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8009b6a: d06b beq.n 8009c44 8009b6c: 6bbb ldr r3, [r7, #56] ; 0x38 8009b6e: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8009b72: d874 bhi.n 8009c5e 8009b74: 6bbb ldr r3, [r7, #56] ; 0x38 8009b76: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8009b7a: d056 beq.n 8009c2a 8009b7c: 6bbb ldr r3, [r7, #56] ; 0x38 8009b7e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8009b82: d86c bhi.n 8009c5e 8009b84: 6bbb ldr r3, [r7, #56] ; 0x38 8009b86: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8009b8a: d03b beq.n 8009c04 8009b8c: 6bbb ldr r3, [r7, #56] ; 0x38 8009b8e: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8009b92: d864 bhi.n 8009c5e 8009b94: 6bbb ldr r3, [r7, #56] ; 0x38 8009b96: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8009b9a: d021 beq.n 8009be0 8009b9c: 6bbb ldr r3, [r7, #56] ; 0x38 8009b9e: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8009ba2: d85c bhi.n 8009c5e 8009ba4: 6bbb ldr r3, [r7, #56] ; 0x38 8009ba6: 2b00 cmp r3, #0 8009ba8: d004 beq.n 8009bb4 8009baa: 6bbb ldr r3, [r7, #56] ; 0x38 8009bac: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8009bb0: d004 beq.n 8009bbc 8009bb2: e054 b.n 8009c5e { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 8009bb4: f000 f8b4 bl 8009d20 8009bb8: 63f8 str r0, [r7, #60] ; 0x3c break; 8009bba: e0a4 b.n 8009d06 } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8009bbc: 4b54 ldr r3, [pc, #336] ; (8009d10 ) 8009bbe: 681b ldr r3, [r3, #0] 8009bc0: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8009bc4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8009bc8: d107 bne.n 8009bda { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8009bca: f107 0318 add.w r3, r7, #24 8009bce: 4618 mov r0, r3 8009bd0: f000 f8bc bl 8009d4c frequency = pll2_clocks.PLL2_Q_Frequency; 8009bd4: 69fb ldr r3, [r7, #28] 8009bd6: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009bd8: e095 b.n 8009d06 frequency = 0; 8009bda: 2300 movs r3, #0 8009bdc: 63fb str r3, [r7, #60] ; 0x3c break; 8009bde: e092 b.n 8009d06 } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8009be0: 4b4b ldr r3, [pc, #300] ; (8009d10 ) 8009be2: 681b ldr r3, [r3, #0] 8009be4: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8009be8: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8009bec: d107 bne.n 8009bfe { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8009bee: f107 030c add.w r3, r7, #12 8009bf2: 4618 mov r0, r3 8009bf4: f000 f9fe bl 8009ff4 frequency = pll3_clocks.PLL3_Q_Frequency; 8009bf8: 693b ldr r3, [r7, #16] 8009bfa: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009bfc: e083 b.n 8009d06 frequency = 0; 8009bfe: 2300 movs r3, #0 8009c00: 63fb str r3, [r7, #60] ; 0x3c break; 8009c02: e080 b.n 8009d06 } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 8009c04: 4b42 ldr r3, [pc, #264] ; (8009d10 ) 8009c06: 681b ldr r3, [r3, #0] 8009c08: f003 0304 and.w r3, r3, #4 8009c0c: 2b04 cmp r3, #4 8009c0e: d109 bne.n 8009c24 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8009c10: 4b3f ldr r3, [pc, #252] ; (8009d10 ) 8009c12: 681b ldr r3, [r3, #0] 8009c14: 08db lsrs r3, r3, #3 8009c16: f003 0303 and.w r3, r3, #3 8009c1a: 4a3e ldr r2, [pc, #248] ; (8009d14 ) 8009c1c: fa22 f303 lsr.w r3, r2, r3 8009c20: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009c22: e070 b.n 8009d06 frequency = 0; 8009c24: 2300 movs r3, #0 8009c26: 63fb str r3, [r7, #60] ; 0x3c break; 8009c28: e06d b.n 8009d06 } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 8009c2a: 4b39 ldr r3, [pc, #228] ; (8009d10 ) 8009c2c: 681b ldr r3, [r3, #0] 8009c2e: f403 7380 and.w r3, r3, #256 ; 0x100 8009c32: f5b3 7f80 cmp.w r3, #256 ; 0x100 8009c36: d102 bne.n 8009c3e { frequency = CSI_VALUE; 8009c38: 4b37 ldr r3, [pc, #220] ; (8009d18 ) 8009c3a: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009c3c: e063 b.n 8009d06 frequency = 0; 8009c3e: 2300 movs r3, #0 8009c40: 63fb str r3, [r7, #60] ; 0x3c break; 8009c42: e060 b.n 8009d06 } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 8009c44: 4b32 ldr r3, [pc, #200] ; (8009d10 ) 8009c46: 681b ldr r3, [r3, #0] 8009c48: f403 3300 and.w r3, r3, #131072 ; 0x20000 8009c4c: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8009c50: d102 bne.n 8009c58 { frequency = HSE_VALUE; 8009c52: 4b32 ldr r3, [pc, #200] ; (8009d1c ) 8009c54: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009c56: e056 b.n 8009d06 frequency = 0; 8009c58: 2300 movs r3, #0 8009c5a: 63fb str r3, [r7, #60] ; 0x3c break; 8009c5c: e053 b.n 8009d06 break; } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 8009c5e: 2300 movs r3, #0 8009c60: 63fb str r3, [r7, #60] ; 0x3c break; 8009c62: e050 b.n 8009d06 } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 8009c64: e9d7 2300 ldrd r2, r3, [r7] 8009c68: f5a2 4100 sub.w r1, r2, #32768 ; 0x8000 8009c6c: 430b orrs r3, r1 8009c6e: d148 bne.n 8009d02 { /* Get FDCAN clock source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 8009c70: 4b27 ldr r3, [pc, #156] ; (8009d10 ) 8009c72: 6d1b ldr r3, [r3, #80] ; 0x50 8009c74: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 8009c78: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 8009c7a: 6bbb ldr r3, [r7, #56] ; 0x38 8009c7c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8009c80: d02a beq.n 8009cd8 8009c82: 6bbb ldr r3, [r7, #56] ; 0x38 8009c84: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8009c88: d838 bhi.n 8009cfc 8009c8a: 6bbb ldr r3, [r7, #56] ; 0x38 8009c8c: 2b00 cmp r3, #0 8009c8e: d004 beq.n 8009c9a 8009c90: 6bbb ldr r3, [r7, #56] ; 0x38 8009c92: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8009c96: d00d beq.n 8009cb4 8009c98: e030 b.n 8009cfc { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 8009c9a: 4b1d ldr r3, [pc, #116] ; (8009d10 ) 8009c9c: 681b ldr r3, [r3, #0] 8009c9e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8009ca2: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8009ca6: d102 bne.n 8009cae { frequency = HSE_VALUE; 8009ca8: 4b1c ldr r3, [pc, #112] ; (8009d1c ) 8009caa: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009cac: e02b b.n 8009d06 frequency = 0; 8009cae: 2300 movs r3, #0 8009cb0: 63fb str r3, [r7, #60] ; 0x3c break; 8009cb2: e028 b.n 8009d06 } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8009cb4: 4b16 ldr r3, [pc, #88] ; (8009d10 ) 8009cb6: 681b ldr r3, [r3, #0] 8009cb8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8009cbc: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8009cc0: d107 bne.n 8009cd2 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8009cc2: f107 0324 add.w r3, r7, #36 ; 0x24 8009cc6: 4618 mov r0, r3 8009cc8: f000 fae8 bl 800a29c frequency = pll1_clocks.PLL1_Q_Frequency; 8009ccc: 6abb ldr r3, [r7, #40] ; 0x28 8009cce: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009cd0: e019 b.n 8009d06 frequency = 0; 8009cd2: 2300 movs r3, #0 8009cd4: 63fb str r3, [r7, #60] ; 0x3c break; 8009cd6: e016 b.n 8009d06 } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8009cd8: 4b0d ldr r3, [pc, #52] ; (8009d10 ) 8009cda: 681b ldr r3, [r3, #0] 8009cdc: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8009ce0: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8009ce4: d107 bne.n 8009cf6 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8009ce6: f107 0318 add.w r3, r7, #24 8009cea: 4618 mov r0, r3 8009cec: f000 f82e bl 8009d4c frequency = pll2_clocks.PLL2_Q_Frequency; 8009cf0: 69fb ldr r3, [r7, #28] 8009cf2: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8009cf4: e007 b.n 8009d06 frequency = 0; 8009cf6: 2300 movs r3, #0 8009cf8: 63fb str r3, [r7, #60] ; 0x3c break; 8009cfa: e004 b.n 8009d06 } default : { frequency = 0; 8009cfc: 2300 movs r3, #0 8009cfe: 63fb str r3, [r7, #60] ; 0x3c break; 8009d00: e001 b.n 8009d06 } } } else { frequency = 0; 8009d02: 2300 movs r3, #0 8009d04: 63fb str r3, [r7, #60] ; 0x3c } return frequency; 8009d06: 6bfb ldr r3, [r7, #60] ; 0x3c } 8009d08: 4618 mov r0, r3 8009d0a: 3740 adds r7, #64 ; 0x40 8009d0c: 46bd mov sp, r7 8009d0e: bd80 pop {r7, pc} 8009d10: 58024400 .word 0x58024400 8009d14: 03d09000 .word 0x03d09000 8009d18: 003d0900 .word 0x003d0900 8009d1c: 017d7840 .word 0x017d7840 08009d20 : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 8009d20: b580 push {r7, lr} 8009d22: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 8009d24: f7fe f8ec bl 8007f00 8009d28: 4602 mov r2, r0 8009d2a: 4b06 ldr r3, [pc, #24] ; (8009d44 ) 8009d2c: 6a1b ldr r3, [r3, #32] 8009d2e: 091b lsrs r3, r3, #4 8009d30: f003 0307 and.w r3, r3, #7 8009d34: 4904 ldr r1, [pc, #16] ; (8009d48 ) 8009d36: 5ccb ldrb r3, [r1, r3] 8009d38: f003 031f and.w r3, r3, #31 8009d3c: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 8009d40: 4618 mov r0, r3 8009d42: bd80 pop {r7, pc} 8009d44: 58024400 .word 0x58024400 8009d48: 08026b40 .word 0x08026b40 08009d4c : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 8009d4c: b480 push {r7} 8009d4e: b089 sub sp, #36 ; 0x24 8009d50: af00 add r7, sp, #0 8009d52: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8009d54: 4ba1 ldr r3, [pc, #644] ; (8009fdc ) 8009d56: 6a9b ldr r3, [r3, #40] ; 0x28 8009d58: f003 0303 and.w r3, r3, #3 8009d5c: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 8009d5e: 4b9f ldr r3, [pc, #636] ; (8009fdc ) 8009d60: 6a9b ldr r3, [r3, #40] ; 0x28 8009d62: 0b1b lsrs r3, r3, #12 8009d64: f003 033f and.w r3, r3, #63 ; 0x3f 8009d68: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 8009d6a: 4b9c ldr r3, [pc, #624] ; (8009fdc ) 8009d6c: 6adb ldr r3, [r3, #44] ; 0x2c 8009d6e: 091b lsrs r3, r3, #4 8009d70: f003 0301 and.w r3, r3, #1 8009d74: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 8009d76: 4b99 ldr r3, [pc, #612] ; (8009fdc ) 8009d78: 6bdb ldr r3, [r3, #60] ; 0x3c 8009d7a: 08db lsrs r3, r3, #3 8009d7c: f3c3 030c ubfx r3, r3, #0, #13 8009d80: 693a ldr r2, [r7, #16] 8009d82: fb02 f303 mul.w r3, r2, r3 8009d86: ee07 3a90 vmov s15, r3 8009d8a: eef8 7a67 vcvt.f32.u32 s15, s15 8009d8e: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 8009d92: 697b ldr r3, [r7, #20] 8009d94: 2b00 cmp r3, #0 8009d96: f000 8111 beq.w 8009fbc { switch (pllsource) 8009d9a: 69bb ldr r3, [r7, #24] 8009d9c: 2b02 cmp r3, #2 8009d9e: f000 8083 beq.w 8009ea8 8009da2: 69bb ldr r3, [r7, #24] 8009da4: 2b02 cmp r3, #2 8009da6: f200 80a1 bhi.w 8009eec 8009daa: 69bb ldr r3, [r7, #24] 8009dac: 2b00 cmp r3, #0 8009dae: d003 beq.n 8009db8 8009db0: 69bb ldr r3, [r7, #24] 8009db2: 2b01 cmp r3, #1 8009db4: d056 beq.n 8009e64 8009db6: e099 b.n 8009eec { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8009db8: 4b88 ldr r3, [pc, #544] ; (8009fdc ) 8009dba: 681b ldr r3, [r3, #0] 8009dbc: f003 0320 and.w r3, r3, #32 8009dc0: 2b00 cmp r3, #0 8009dc2: d02d beq.n 8009e20 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8009dc4: 4b85 ldr r3, [pc, #532] ; (8009fdc ) 8009dc6: 681b ldr r3, [r3, #0] 8009dc8: 08db lsrs r3, r3, #3 8009dca: f003 0303 and.w r3, r3, #3 8009dce: 4a84 ldr r2, [pc, #528] ; (8009fe0 ) 8009dd0: fa22 f303 lsr.w r3, r2, r3 8009dd4: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8009dd6: 68bb ldr r3, [r7, #8] 8009dd8: ee07 3a90 vmov s15, r3 8009ddc: eef8 6a67 vcvt.f32.u32 s13, s15 8009de0: 697b ldr r3, [r7, #20] 8009de2: ee07 3a90 vmov s15, r3 8009de6: eef8 7a67 vcvt.f32.u32 s15, s15 8009dea: ee86 7aa7 vdiv.f32 s14, s13, s15 8009dee: 4b7b ldr r3, [pc, #492] ; (8009fdc ) 8009df0: 6b9b ldr r3, [r3, #56] ; 0x38 8009df2: f3c3 0308 ubfx r3, r3, #0, #9 8009df6: ee07 3a90 vmov s15, r3 8009dfa: eef8 6a67 vcvt.f32.u32 s13, s15 8009dfe: ed97 6a03 vldr s12, [r7, #12] 8009e02: eddf 5a78 vldr s11, [pc, #480] ; 8009fe4 8009e06: eec6 7a25 vdiv.f32 s15, s12, s11 8009e0a: ee76 7aa7 vadd.f32 s15, s13, s15 8009e0e: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8009e12: ee77 7aa6 vadd.f32 s15, s15, s13 8009e16: ee67 7a27 vmul.f32 s15, s14, s15 8009e1a: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 8009e1e: e087 b.n 8009f30 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8009e20: 697b ldr r3, [r7, #20] 8009e22: ee07 3a90 vmov s15, r3 8009e26: eef8 7a67 vcvt.f32.u32 s15, s15 8009e2a: eddf 6a6f vldr s13, [pc, #444] ; 8009fe8 8009e2e: ee86 7aa7 vdiv.f32 s14, s13, s15 8009e32: 4b6a ldr r3, [pc, #424] ; (8009fdc ) 8009e34: 6b9b ldr r3, [r3, #56] ; 0x38 8009e36: f3c3 0308 ubfx r3, r3, #0, #9 8009e3a: ee07 3a90 vmov s15, r3 8009e3e: eef8 6a67 vcvt.f32.u32 s13, s15 8009e42: ed97 6a03 vldr s12, [r7, #12] 8009e46: eddf 5a67 vldr s11, [pc, #412] ; 8009fe4 8009e4a: eec6 7a25 vdiv.f32 s15, s12, s11 8009e4e: ee76 7aa7 vadd.f32 s15, s13, s15 8009e52: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8009e56: ee77 7aa6 vadd.f32 s15, s15, s13 8009e5a: ee67 7a27 vmul.f32 s15, s14, s15 8009e5e: edc7 7a07 vstr s15, [r7, #28] break; 8009e62: e065 b.n 8009f30 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8009e64: 697b ldr r3, [r7, #20] 8009e66: ee07 3a90 vmov s15, r3 8009e6a: eef8 7a67 vcvt.f32.u32 s15, s15 8009e6e: eddf 6a5f vldr s13, [pc, #380] ; 8009fec 8009e72: ee86 7aa7 vdiv.f32 s14, s13, s15 8009e76: 4b59 ldr r3, [pc, #356] ; (8009fdc ) 8009e78: 6b9b ldr r3, [r3, #56] ; 0x38 8009e7a: f3c3 0308 ubfx r3, r3, #0, #9 8009e7e: ee07 3a90 vmov s15, r3 8009e82: eef8 6a67 vcvt.f32.u32 s13, s15 8009e86: ed97 6a03 vldr s12, [r7, #12] 8009e8a: eddf 5a56 vldr s11, [pc, #344] ; 8009fe4 8009e8e: eec6 7a25 vdiv.f32 s15, s12, s11 8009e92: ee76 7aa7 vadd.f32 s15, s13, s15 8009e96: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8009e9a: ee77 7aa6 vadd.f32 s15, s15, s13 8009e9e: ee67 7a27 vmul.f32 s15, s14, s15 8009ea2: edc7 7a07 vstr s15, [r7, #28] break; 8009ea6: e043 b.n 8009f30 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8009ea8: 697b ldr r3, [r7, #20] 8009eaa: ee07 3a90 vmov s15, r3 8009eae: eef8 7a67 vcvt.f32.u32 s15, s15 8009eb2: eddf 6a4f vldr s13, [pc, #316] ; 8009ff0 8009eb6: ee86 7aa7 vdiv.f32 s14, s13, s15 8009eba: 4b48 ldr r3, [pc, #288] ; (8009fdc ) 8009ebc: 6b9b ldr r3, [r3, #56] ; 0x38 8009ebe: f3c3 0308 ubfx r3, r3, #0, #9 8009ec2: ee07 3a90 vmov s15, r3 8009ec6: eef8 6a67 vcvt.f32.u32 s13, s15 8009eca: ed97 6a03 vldr s12, [r7, #12] 8009ece: eddf 5a45 vldr s11, [pc, #276] ; 8009fe4 8009ed2: eec6 7a25 vdiv.f32 s15, s12, s11 8009ed6: ee76 7aa7 vadd.f32 s15, s13, s15 8009eda: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8009ede: ee77 7aa6 vadd.f32 s15, s15, s13 8009ee2: ee67 7a27 vmul.f32 s15, s14, s15 8009ee6: edc7 7a07 vstr s15, [r7, #28] break; 8009eea: e021 b.n 8009f30 default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8009eec: 697b ldr r3, [r7, #20] 8009eee: ee07 3a90 vmov s15, r3 8009ef2: eef8 7a67 vcvt.f32.u32 s15, s15 8009ef6: eddf 6a3d vldr s13, [pc, #244] ; 8009fec 8009efa: ee86 7aa7 vdiv.f32 s14, s13, s15 8009efe: 4b37 ldr r3, [pc, #220] ; (8009fdc ) 8009f00: 6b9b ldr r3, [r3, #56] ; 0x38 8009f02: f3c3 0308 ubfx r3, r3, #0, #9 8009f06: ee07 3a90 vmov s15, r3 8009f0a: eef8 6a67 vcvt.f32.u32 s13, s15 8009f0e: ed97 6a03 vldr s12, [r7, #12] 8009f12: eddf 5a34 vldr s11, [pc, #208] ; 8009fe4 8009f16: eec6 7a25 vdiv.f32 s15, s12, s11 8009f1a: ee76 7aa7 vadd.f32 s15, s13, s15 8009f1e: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8009f22: ee77 7aa6 vadd.f32 s15, s15, s13 8009f26: ee67 7a27 vmul.f32 s15, s14, s15 8009f2a: edc7 7a07 vstr s15, [r7, #28] break; 8009f2e: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 8009f30: 4b2a ldr r3, [pc, #168] ; (8009fdc ) 8009f32: 6b9b ldr r3, [r3, #56] ; 0x38 8009f34: 0a5b lsrs r3, r3, #9 8009f36: f003 037f and.w r3, r3, #127 ; 0x7f 8009f3a: ee07 3a90 vmov s15, r3 8009f3e: eef8 7a67 vcvt.f32.u32 s15, s15 8009f42: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8009f46: ee37 7a87 vadd.f32 s14, s15, s14 8009f4a: edd7 6a07 vldr s13, [r7, #28] 8009f4e: eec6 7a87 vdiv.f32 s15, s13, s14 8009f52: eefc 7ae7 vcvt.u32.f32 s15, s15 8009f56: ee17 2a90 vmov r2, s15 8009f5a: 687b ldr r3, [r7, #4] 8009f5c: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 8009f5e: 4b1f ldr r3, [pc, #124] ; (8009fdc ) 8009f60: 6b9b ldr r3, [r3, #56] ; 0x38 8009f62: 0c1b lsrs r3, r3, #16 8009f64: f003 037f and.w r3, r3, #127 ; 0x7f 8009f68: ee07 3a90 vmov s15, r3 8009f6c: eef8 7a67 vcvt.f32.u32 s15, s15 8009f70: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8009f74: ee37 7a87 vadd.f32 s14, s15, s14 8009f78: edd7 6a07 vldr s13, [r7, #28] 8009f7c: eec6 7a87 vdiv.f32 s15, s13, s14 8009f80: eefc 7ae7 vcvt.u32.f32 s15, s15 8009f84: ee17 2a90 vmov r2, s15 8009f88: 687b ldr r3, [r7, #4] 8009f8a: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 8009f8c: 4b13 ldr r3, [pc, #76] ; (8009fdc ) 8009f8e: 6b9b ldr r3, [r3, #56] ; 0x38 8009f90: 0e1b lsrs r3, r3, #24 8009f92: f003 037f and.w r3, r3, #127 ; 0x7f 8009f96: ee07 3a90 vmov s15, r3 8009f9a: eef8 7a67 vcvt.f32.u32 s15, s15 8009f9e: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8009fa2: ee37 7a87 vadd.f32 s14, s15, s14 8009fa6: edd7 6a07 vldr s13, [r7, #28] 8009faa: eec6 7a87 vdiv.f32 s15, s13, s14 8009fae: eefc 7ae7 vcvt.u32.f32 s15, s15 8009fb2: ee17 2a90 vmov r2, s15 8009fb6: 687b ldr r3, [r7, #4] 8009fb8: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 8009fba: e008 b.n 8009fce PLL2_Clocks->PLL2_P_Frequency = 0U; 8009fbc: 687b ldr r3, [r7, #4] 8009fbe: 2200 movs r2, #0 8009fc0: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 8009fc2: 687b ldr r3, [r7, #4] 8009fc4: 2200 movs r2, #0 8009fc6: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 8009fc8: 687b ldr r3, [r7, #4] 8009fca: 2200 movs r2, #0 8009fcc: 609a str r2, [r3, #8] } 8009fce: bf00 nop 8009fd0: 3724 adds r7, #36 ; 0x24 8009fd2: 46bd mov sp, r7 8009fd4: f85d 7b04 ldr.w r7, [sp], #4 8009fd8: 4770 bx lr 8009fda: bf00 nop 8009fdc: 58024400 .word 0x58024400 8009fe0: 03d09000 .word 0x03d09000 8009fe4: 46000000 .word 0x46000000 8009fe8: 4c742400 .word 0x4c742400 8009fec: 4a742400 .word 0x4a742400 8009ff0: 4bbebc20 .word 0x4bbebc20 08009ff4 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 8009ff4: b480 push {r7} 8009ff6: b089 sub sp, #36 ; 0x24 8009ff8: af00 add r7, sp, #0 8009ffa: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8009ffc: 4ba1 ldr r3, [pc, #644] ; (800a284 ) 8009ffe: 6a9b ldr r3, [r3, #40] ; 0x28 800a000: f003 0303 and.w r3, r3, #3 800a004: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 800a006: 4b9f ldr r3, [pc, #636] ; (800a284 ) 800a008: 6a9b ldr r3, [r3, #40] ; 0x28 800a00a: 0d1b lsrs r3, r3, #20 800a00c: f003 033f and.w r3, r3, #63 ; 0x3f 800a010: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 800a012: 4b9c ldr r3, [pc, #624] ; (800a284 ) 800a014: 6adb ldr r3, [r3, #44] ; 0x2c 800a016: 0a1b lsrs r3, r3, #8 800a018: f003 0301 and.w r3, r3, #1 800a01c: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 800a01e: 4b99 ldr r3, [pc, #612] ; (800a284 ) 800a020: 6c5b ldr r3, [r3, #68] ; 0x44 800a022: 08db lsrs r3, r3, #3 800a024: f3c3 030c ubfx r3, r3, #0, #13 800a028: 693a ldr r2, [r7, #16] 800a02a: fb02 f303 mul.w r3, r2, r3 800a02e: ee07 3a90 vmov s15, r3 800a032: eef8 7a67 vcvt.f32.u32 s15, s15 800a036: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 800a03a: 697b ldr r3, [r7, #20] 800a03c: 2b00 cmp r3, #0 800a03e: f000 8111 beq.w 800a264 { switch (pllsource) 800a042: 69bb ldr r3, [r7, #24] 800a044: 2b02 cmp r3, #2 800a046: f000 8083 beq.w 800a150 800a04a: 69bb ldr r3, [r7, #24] 800a04c: 2b02 cmp r3, #2 800a04e: f200 80a1 bhi.w 800a194 800a052: 69bb ldr r3, [r7, #24] 800a054: 2b00 cmp r3, #0 800a056: d003 beq.n 800a060 800a058: 69bb ldr r3, [r7, #24] 800a05a: 2b01 cmp r3, #1 800a05c: d056 beq.n 800a10c 800a05e: e099 b.n 800a194 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800a060: 4b88 ldr r3, [pc, #544] ; (800a284 ) 800a062: 681b ldr r3, [r3, #0] 800a064: f003 0320 and.w r3, r3, #32 800a068: 2b00 cmp r3, #0 800a06a: d02d beq.n 800a0c8 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800a06c: 4b85 ldr r3, [pc, #532] ; (800a284 ) 800a06e: 681b ldr r3, [r3, #0] 800a070: 08db lsrs r3, r3, #3 800a072: f003 0303 and.w r3, r3, #3 800a076: 4a84 ldr r2, [pc, #528] ; (800a288 ) 800a078: fa22 f303 lsr.w r3, r2, r3 800a07c: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800a07e: 68bb ldr r3, [r7, #8] 800a080: ee07 3a90 vmov s15, r3 800a084: eef8 6a67 vcvt.f32.u32 s13, s15 800a088: 697b ldr r3, [r7, #20] 800a08a: ee07 3a90 vmov s15, r3 800a08e: eef8 7a67 vcvt.f32.u32 s15, s15 800a092: ee86 7aa7 vdiv.f32 s14, s13, s15 800a096: 4b7b ldr r3, [pc, #492] ; (800a284 ) 800a098: 6c1b ldr r3, [r3, #64] ; 0x40 800a09a: f3c3 0308 ubfx r3, r3, #0, #9 800a09e: ee07 3a90 vmov s15, r3 800a0a2: eef8 6a67 vcvt.f32.u32 s13, s15 800a0a6: ed97 6a03 vldr s12, [r7, #12] 800a0aa: eddf 5a78 vldr s11, [pc, #480] ; 800a28c 800a0ae: eec6 7a25 vdiv.f32 s15, s12, s11 800a0b2: ee76 7aa7 vadd.f32 s15, s13, s15 800a0b6: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800a0ba: ee77 7aa6 vadd.f32 s15, s15, s13 800a0be: ee67 7a27 vmul.f32 s15, s14, s15 800a0c2: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 800a0c6: e087 b.n 800a1d8 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800a0c8: 697b ldr r3, [r7, #20] 800a0ca: ee07 3a90 vmov s15, r3 800a0ce: eef8 7a67 vcvt.f32.u32 s15, s15 800a0d2: eddf 6a6f vldr s13, [pc, #444] ; 800a290 800a0d6: ee86 7aa7 vdiv.f32 s14, s13, s15 800a0da: 4b6a ldr r3, [pc, #424] ; (800a284 ) 800a0dc: 6c1b ldr r3, [r3, #64] ; 0x40 800a0de: f3c3 0308 ubfx r3, r3, #0, #9 800a0e2: ee07 3a90 vmov s15, r3 800a0e6: eef8 6a67 vcvt.f32.u32 s13, s15 800a0ea: ed97 6a03 vldr s12, [r7, #12] 800a0ee: eddf 5a67 vldr s11, [pc, #412] ; 800a28c 800a0f2: eec6 7a25 vdiv.f32 s15, s12, s11 800a0f6: ee76 7aa7 vadd.f32 s15, s13, s15 800a0fa: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800a0fe: ee77 7aa6 vadd.f32 s15, s15, s13 800a102: ee67 7a27 vmul.f32 s15, s14, s15 800a106: edc7 7a07 vstr s15, [r7, #28] break; 800a10a: e065 b.n 800a1d8 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800a10c: 697b ldr r3, [r7, #20] 800a10e: ee07 3a90 vmov s15, r3 800a112: eef8 7a67 vcvt.f32.u32 s15, s15 800a116: eddf 6a5f vldr s13, [pc, #380] ; 800a294 800a11a: ee86 7aa7 vdiv.f32 s14, s13, s15 800a11e: 4b59 ldr r3, [pc, #356] ; (800a284 ) 800a120: 6c1b ldr r3, [r3, #64] ; 0x40 800a122: f3c3 0308 ubfx r3, r3, #0, #9 800a126: ee07 3a90 vmov s15, r3 800a12a: eef8 6a67 vcvt.f32.u32 s13, s15 800a12e: ed97 6a03 vldr s12, [r7, #12] 800a132: eddf 5a56 vldr s11, [pc, #344] ; 800a28c 800a136: eec6 7a25 vdiv.f32 s15, s12, s11 800a13a: ee76 7aa7 vadd.f32 s15, s13, s15 800a13e: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800a142: ee77 7aa6 vadd.f32 s15, s15, s13 800a146: ee67 7a27 vmul.f32 s15, s14, s15 800a14a: edc7 7a07 vstr s15, [r7, #28] break; 800a14e: e043 b.n 800a1d8 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800a150: 697b ldr r3, [r7, #20] 800a152: ee07 3a90 vmov s15, r3 800a156: eef8 7a67 vcvt.f32.u32 s15, s15 800a15a: eddf 6a4f vldr s13, [pc, #316] ; 800a298 800a15e: ee86 7aa7 vdiv.f32 s14, s13, s15 800a162: 4b48 ldr r3, [pc, #288] ; (800a284 ) 800a164: 6c1b ldr r3, [r3, #64] ; 0x40 800a166: f3c3 0308 ubfx r3, r3, #0, #9 800a16a: ee07 3a90 vmov s15, r3 800a16e: eef8 6a67 vcvt.f32.u32 s13, s15 800a172: ed97 6a03 vldr s12, [r7, #12] 800a176: eddf 5a45 vldr s11, [pc, #276] ; 800a28c 800a17a: eec6 7a25 vdiv.f32 s15, s12, s11 800a17e: ee76 7aa7 vadd.f32 s15, s13, s15 800a182: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800a186: ee77 7aa6 vadd.f32 s15, s15, s13 800a18a: ee67 7a27 vmul.f32 s15, s14, s15 800a18e: edc7 7a07 vstr s15, [r7, #28] break; 800a192: e021 b.n 800a1d8 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800a194: 697b ldr r3, [r7, #20] 800a196: ee07 3a90 vmov s15, r3 800a19a: eef8 7a67 vcvt.f32.u32 s15, s15 800a19e: eddf 6a3d vldr s13, [pc, #244] ; 800a294 800a1a2: ee86 7aa7 vdiv.f32 s14, s13, s15 800a1a6: 4b37 ldr r3, [pc, #220] ; (800a284 ) 800a1a8: 6c1b ldr r3, [r3, #64] ; 0x40 800a1aa: f3c3 0308 ubfx r3, r3, #0, #9 800a1ae: ee07 3a90 vmov s15, r3 800a1b2: eef8 6a67 vcvt.f32.u32 s13, s15 800a1b6: ed97 6a03 vldr s12, [r7, #12] 800a1ba: eddf 5a34 vldr s11, [pc, #208] ; 800a28c 800a1be: eec6 7a25 vdiv.f32 s15, s12, s11 800a1c2: ee76 7aa7 vadd.f32 s15, s13, s15 800a1c6: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800a1ca: ee77 7aa6 vadd.f32 s15, s15, s13 800a1ce: ee67 7a27 vmul.f32 s15, s14, s15 800a1d2: edc7 7a07 vstr s15, [r7, #28] break; 800a1d6: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 800a1d8: 4b2a ldr r3, [pc, #168] ; (800a284 ) 800a1da: 6c1b ldr r3, [r3, #64] ; 0x40 800a1dc: 0a5b lsrs r3, r3, #9 800a1de: f003 037f and.w r3, r3, #127 ; 0x7f 800a1e2: ee07 3a90 vmov s15, r3 800a1e6: eef8 7a67 vcvt.f32.u32 s15, s15 800a1ea: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 800a1ee: ee37 7a87 vadd.f32 s14, s15, s14 800a1f2: edd7 6a07 vldr s13, [r7, #28] 800a1f6: eec6 7a87 vdiv.f32 s15, s13, s14 800a1fa: eefc 7ae7 vcvt.u32.f32 s15, s15 800a1fe: ee17 2a90 vmov r2, s15 800a202: 687b ldr r3, [r7, #4] 800a204: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 800a206: 4b1f ldr r3, [pc, #124] ; (800a284 ) 800a208: 6c1b ldr r3, [r3, #64] ; 0x40 800a20a: 0c1b lsrs r3, r3, #16 800a20c: f003 037f and.w r3, r3, #127 ; 0x7f 800a210: ee07 3a90 vmov s15, r3 800a214: eef8 7a67 vcvt.f32.u32 s15, s15 800a218: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 800a21c: ee37 7a87 vadd.f32 s14, s15, s14 800a220: edd7 6a07 vldr s13, [r7, #28] 800a224: eec6 7a87 vdiv.f32 s15, s13, s14 800a228: eefc 7ae7 vcvt.u32.f32 s15, s15 800a22c: ee17 2a90 vmov r2, s15 800a230: 687b ldr r3, [r7, #4] 800a232: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 800a234: 4b13 ldr r3, [pc, #76] ; (800a284 ) 800a236: 6c1b ldr r3, [r3, #64] ; 0x40 800a238: 0e1b lsrs r3, r3, #24 800a23a: f003 037f and.w r3, r3, #127 ; 0x7f 800a23e: ee07 3a90 vmov s15, r3 800a242: eef8 7a67 vcvt.f32.u32 s15, s15 800a246: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 800a24a: ee37 7a87 vadd.f32 s14, s15, s14 800a24e: edd7 6a07 vldr s13, [r7, #28] 800a252: eec6 7a87 vdiv.f32 s15, s13, s14 800a256: eefc 7ae7 vcvt.u32.f32 s15, s15 800a25a: ee17 2a90 vmov r2, s15 800a25e: 687b ldr r3, [r7, #4] 800a260: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800a262: e008 b.n 800a276 PLL3_Clocks->PLL3_P_Frequency = 0U; 800a264: 687b ldr r3, [r7, #4] 800a266: 2200 movs r2, #0 800a268: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 800a26a: 687b ldr r3, [r7, #4] 800a26c: 2200 movs r2, #0 800a26e: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800a270: 687b ldr r3, [r7, #4] 800a272: 2200 movs r2, #0 800a274: 609a str r2, [r3, #8] } 800a276: bf00 nop 800a278: 3724 adds r7, #36 ; 0x24 800a27a: 46bd mov sp, r7 800a27c: f85d 7b04 ldr.w r7, [sp], #4 800a280: 4770 bx lr 800a282: bf00 nop 800a284: 58024400 .word 0x58024400 800a288: 03d09000 .word 0x03d09000 800a28c: 46000000 .word 0x46000000 800a290: 4c742400 .word 0x4c742400 800a294: 4a742400 .word 0x4a742400 800a298: 4bbebc20 .word 0x4bbebc20 0800a29c : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { 800a29c: b480 push {r7} 800a29e: b089 sub sp, #36 ; 0x24 800a2a0: af00 add r7, sp, #0 800a2a2: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800a2a4: 4ba0 ldr r3, [pc, #640] ; (800a528 ) 800a2a6: 6a9b ldr r3, [r3, #40] ; 0x28 800a2a8: f003 0303 and.w r3, r3, #3 800a2ac: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 800a2ae: 4b9e ldr r3, [pc, #632] ; (800a528 ) 800a2b0: 6a9b ldr r3, [r3, #40] ; 0x28 800a2b2: 091b lsrs r3, r3, #4 800a2b4: f003 033f and.w r3, r3, #63 ; 0x3f 800a2b8: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 800a2ba: 4b9b ldr r3, [pc, #620] ; (800a528 ) 800a2bc: 6adb ldr r3, [r3, #44] ; 0x2c 800a2be: f003 0301 and.w r3, r3, #1 800a2c2: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800a2c4: 4b98 ldr r3, [pc, #608] ; (800a528 ) 800a2c6: 6b5b ldr r3, [r3, #52] ; 0x34 800a2c8: 08db lsrs r3, r3, #3 800a2ca: f3c3 030c ubfx r3, r3, #0, #13 800a2ce: 693a ldr r2, [r7, #16] 800a2d0: fb02 f303 mul.w r3, r2, r3 800a2d4: ee07 3a90 vmov s15, r3 800a2d8: eef8 7a67 vcvt.f32.u32 s15, s15 800a2dc: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 800a2e0: 697b ldr r3, [r7, #20] 800a2e2: 2b00 cmp r3, #0 800a2e4: f000 8111 beq.w 800a50a { switch (pllsource) 800a2e8: 69bb ldr r3, [r7, #24] 800a2ea: 2b02 cmp r3, #2 800a2ec: f000 8083 beq.w 800a3f6 800a2f0: 69bb ldr r3, [r7, #24] 800a2f2: 2b02 cmp r3, #2 800a2f4: f200 80a1 bhi.w 800a43a 800a2f8: 69bb ldr r3, [r7, #24] 800a2fa: 2b00 cmp r3, #0 800a2fc: d003 beq.n 800a306 800a2fe: 69bb ldr r3, [r7, #24] 800a300: 2b01 cmp r3, #1 800a302: d056 beq.n 800a3b2 800a304: e099 b.n 800a43a { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800a306: 4b88 ldr r3, [pc, #544] ; (800a528 ) 800a308: 681b ldr r3, [r3, #0] 800a30a: f003 0320 and.w r3, r3, #32 800a30e: 2b00 cmp r3, #0 800a310: d02d beq.n 800a36e { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800a312: 4b85 ldr r3, [pc, #532] ; (800a528 ) 800a314: 681b ldr r3, [r3, #0] 800a316: 08db lsrs r3, r3, #3 800a318: f003 0303 and.w r3, r3, #3 800a31c: 4a83 ldr r2, [pc, #524] ; (800a52c ) 800a31e: fa22 f303 lsr.w r3, r2, r3 800a322: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800a324: 68bb ldr r3, [r7, #8] 800a326: ee07 3a90 vmov s15, r3 800a32a: eef8 6a67 vcvt.f32.u32 s13, s15 800a32e: 697b ldr r3, [r7, #20] 800a330: ee07 3a90 vmov s15, r3 800a334: eef8 7a67 vcvt.f32.u32 s15, s15 800a338: ee86 7aa7 vdiv.f32 s14, s13, s15 800a33c: 4b7a ldr r3, [pc, #488] ; (800a528 ) 800a33e: 6b1b ldr r3, [r3, #48] ; 0x30 800a340: f3c3 0308 ubfx r3, r3, #0, #9 800a344: ee07 3a90 vmov s15, r3 800a348: eef8 6a67 vcvt.f32.u32 s13, s15 800a34c: ed97 6a03 vldr s12, [r7, #12] 800a350: eddf 5a77 vldr s11, [pc, #476] ; 800a530 800a354: eec6 7a25 vdiv.f32 s15, s12, s11 800a358: ee76 7aa7 vadd.f32 s15, s13, s15 800a35c: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800a360: ee77 7aa6 vadd.f32 s15, s15, s13 800a364: ee67 7a27 vmul.f32 s15, s14, s15 800a368: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800a36c: e087 b.n 800a47e pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800a36e: 697b ldr r3, [r7, #20] 800a370: ee07 3a90 vmov s15, r3 800a374: eef8 7a67 vcvt.f32.u32 s15, s15 800a378: eddf 6a6e vldr s13, [pc, #440] ; 800a534 800a37c: ee86 7aa7 vdiv.f32 s14, s13, s15 800a380: 4b69 ldr r3, [pc, #420] ; (800a528 ) 800a382: 6b1b ldr r3, [r3, #48] ; 0x30 800a384: f3c3 0308 ubfx r3, r3, #0, #9 800a388: ee07 3a90 vmov s15, r3 800a38c: eef8 6a67 vcvt.f32.u32 s13, s15 800a390: ed97 6a03 vldr s12, [r7, #12] 800a394: eddf 5a66 vldr s11, [pc, #408] ; 800a530 800a398: eec6 7a25 vdiv.f32 s15, s12, s11 800a39c: ee76 7aa7 vadd.f32 s15, s13, s15 800a3a0: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800a3a4: ee77 7aa6 vadd.f32 s15, s15, s13 800a3a8: ee67 7a27 vmul.f32 s15, s14, s15 800a3ac: edc7 7a07 vstr s15, [r7, #28] break; 800a3b0: e065 b.n 800a47e case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800a3b2: 697b ldr r3, [r7, #20] 800a3b4: ee07 3a90 vmov s15, r3 800a3b8: eef8 7a67 vcvt.f32.u32 s15, s15 800a3bc: eddf 6a5e vldr s13, [pc, #376] ; 800a538 800a3c0: ee86 7aa7 vdiv.f32 s14, s13, s15 800a3c4: 4b58 ldr r3, [pc, #352] ; (800a528 ) 800a3c6: 6b1b ldr r3, [r3, #48] ; 0x30 800a3c8: f3c3 0308 ubfx r3, r3, #0, #9 800a3cc: ee07 3a90 vmov s15, r3 800a3d0: eef8 6a67 vcvt.f32.u32 s13, s15 800a3d4: ed97 6a03 vldr s12, [r7, #12] 800a3d8: eddf 5a55 vldr s11, [pc, #340] ; 800a530 800a3dc: eec6 7a25 vdiv.f32 s15, s12, s11 800a3e0: ee76 7aa7 vadd.f32 s15, s13, s15 800a3e4: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800a3e8: ee77 7aa6 vadd.f32 s15, s15, s13 800a3ec: ee67 7a27 vmul.f32 s15, s14, s15 800a3f0: edc7 7a07 vstr s15, [r7, #28] break; 800a3f4: e043 b.n 800a47e case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800a3f6: 697b ldr r3, [r7, #20] 800a3f8: ee07 3a90 vmov s15, r3 800a3fc: eef8 7a67 vcvt.f32.u32 s15, s15 800a400: eddf 6a4e vldr s13, [pc, #312] ; 800a53c 800a404: ee86 7aa7 vdiv.f32 s14, s13, s15 800a408: 4b47 ldr r3, [pc, #284] ; (800a528 ) 800a40a: 6b1b ldr r3, [r3, #48] ; 0x30 800a40c: f3c3 0308 ubfx r3, r3, #0, #9 800a410: ee07 3a90 vmov s15, r3 800a414: eef8 6a67 vcvt.f32.u32 s13, s15 800a418: ed97 6a03 vldr s12, [r7, #12] 800a41c: eddf 5a44 vldr s11, [pc, #272] ; 800a530 800a420: eec6 7a25 vdiv.f32 s15, s12, s11 800a424: ee76 7aa7 vadd.f32 s15, s13, s15 800a428: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800a42c: ee77 7aa6 vadd.f32 s15, s15, s13 800a430: ee67 7a27 vmul.f32 s15, s14, s15 800a434: edc7 7a07 vstr s15, [r7, #28] break; 800a438: e021 b.n 800a47e default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800a43a: 697b ldr r3, [r7, #20] 800a43c: ee07 3a90 vmov s15, r3 800a440: eef8 7a67 vcvt.f32.u32 s15, s15 800a444: eddf 6a3b vldr s13, [pc, #236] ; 800a534 800a448: ee86 7aa7 vdiv.f32 s14, s13, s15 800a44c: 4b36 ldr r3, [pc, #216] ; (800a528 ) 800a44e: 6b1b ldr r3, [r3, #48] ; 0x30 800a450: f3c3 0308 ubfx r3, r3, #0, #9 800a454: ee07 3a90 vmov s15, r3 800a458: eef8 6a67 vcvt.f32.u32 s13, s15 800a45c: ed97 6a03 vldr s12, [r7, #12] 800a460: eddf 5a33 vldr s11, [pc, #204] ; 800a530 800a464: eec6 7a25 vdiv.f32 s15, s12, s11 800a468: ee76 7aa7 vadd.f32 s15, s13, s15 800a46c: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800a470: ee77 7aa6 vadd.f32 s15, s15, s13 800a474: ee67 7a27 vmul.f32 s15, s14, s15 800a478: edc7 7a07 vstr s15, [r7, #28] break; 800a47c: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 800a47e: 4b2a ldr r3, [pc, #168] ; (800a528 ) 800a480: 6b1b ldr r3, [r3, #48] ; 0x30 800a482: 0a5b lsrs r3, r3, #9 800a484: f003 037f and.w r3, r3, #127 ; 0x7f 800a488: ee07 3a90 vmov s15, r3 800a48c: eef8 7a67 vcvt.f32.u32 s15, s15 800a490: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 800a494: ee37 7a87 vadd.f32 s14, s15, s14 800a498: edd7 6a07 vldr s13, [r7, #28] 800a49c: eec6 7a87 vdiv.f32 s15, s13, s14 800a4a0: eefc 7ae7 vcvt.u32.f32 s15, s15 800a4a4: ee17 2a90 vmov r2, s15 800a4a8: 687b ldr r3, [r7, #4] 800a4aa: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 800a4ac: 4b1e ldr r3, [pc, #120] ; (800a528 ) 800a4ae: 6b1b ldr r3, [r3, #48] ; 0x30 800a4b0: 0c1b lsrs r3, r3, #16 800a4b2: f003 037f and.w r3, r3, #127 ; 0x7f 800a4b6: ee07 3a90 vmov s15, r3 800a4ba: eef8 7a67 vcvt.f32.u32 s15, s15 800a4be: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 800a4c2: ee37 7a87 vadd.f32 s14, s15, s14 800a4c6: edd7 6a07 vldr s13, [r7, #28] 800a4ca: eec6 7a87 vdiv.f32 s15, s13, s14 800a4ce: eefc 7ae7 vcvt.u32.f32 s15, s15 800a4d2: ee17 2a90 vmov r2, s15 800a4d6: 687b ldr r3, [r7, #4] 800a4d8: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 800a4da: 4b13 ldr r3, [pc, #76] ; (800a528 ) 800a4dc: 6b1b ldr r3, [r3, #48] ; 0x30 800a4de: 0e1b lsrs r3, r3, #24 800a4e0: f003 037f and.w r3, r3, #127 ; 0x7f 800a4e4: ee07 3a90 vmov s15, r3 800a4e8: eef8 7a67 vcvt.f32.u32 s15, s15 800a4ec: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 800a4f0: ee37 7a87 vadd.f32 s14, s15, s14 800a4f4: edd7 6a07 vldr s13, [r7, #28] 800a4f8: eec6 7a87 vdiv.f32 s15, s13, s14 800a4fc: eefc 7ae7 vcvt.u32.f32 s15, s15 800a500: ee17 2a90 vmov r2, s15 800a504: 687b ldr r3, [r7, #4] 800a506: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 800a508: e008 b.n 800a51c PLL1_Clocks->PLL1_P_Frequency = 0U; 800a50a: 687b ldr r3, [r7, #4] 800a50c: 2200 movs r2, #0 800a50e: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800a510: 687b ldr r3, [r7, #4] 800a512: 2200 movs r2, #0 800a514: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 800a516: 687b ldr r3, [r7, #4] 800a518: 2200 movs r2, #0 800a51a: 609a str r2, [r3, #8] } 800a51c: bf00 nop 800a51e: 3724 adds r7, #36 ; 0x24 800a520: 46bd mov sp, r7 800a522: f85d 7b04 ldr.w r7, [sp], #4 800a526: 4770 bx lr 800a528: 58024400 .word 0x58024400 800a52c: 03d09000 .word 0x03d09000 800a530: 46000000 .word 0x46000000 800a534: 4c742400 .word 0x4c742400 800a538: 4a742400 .word 0x4a742400 800a53c: 4bbebc20 .word 0x4bbebc20 0800a540 : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800a540: b580 push {r7, lr} 800a542: b084 sub sp, #16 800a544: af00 add r7, sp, #0 800a546: 6078 str r0, [r7, #4] 800a548: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800a54a: 2300 movs r3, #0 800a54c: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800a54e: 4b53 ldr r3, [pc, #332] ; (800a69c ) 800a550: 6a9b ldr r3, [r3, #40] ; 0x28 800a552: f003 0303 and.w r3, r3, #3 800a556: 2b03 cmp r3, #3 800a558: d101 bne.n 800a55e { return HAL_ERROR; 800a55a: 2301 movs r3, #1 800a55c: e099 b.n 800a692 else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800a55e: 4b4f ldr r3, [pc, #316] ; (800a69c ) 800a560: 681b ldr r3, [r3, #0] 800a562: 4a4e ldr r2, [pc, #312] ; (800a69c ) 800a564: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 800a568: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a56a: f7f7 fefb bl 8002364 800a56e: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800a570: e008 b.n 800a584 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800a572: f7f7 fef7 bl 8002364 800a576: 4602 mov r2, r0 800a578: 68bb ldr r3, [r7, #8] 800a57a: 1ad3 subs r3, r2, r3 800a57c: 2b02 cmp r3, #2 800a57e: d901 bls.n 800a584 { return HAL_TIMEOUT; 800a580: 2303 movs r3, #3 800a582: e086 b.n 800a692 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800a584: 4b45 ldr r3, [pc, #276] ; (800a69c ) 800a586: 681b ldr r3, [r3, #0] 800a588: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 800a58c: 2b00 cmp r3, #0 800a58e: d1f0 bne.n 800a572 } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 800a590: 4b42 ldr r3, [pc, #264] ; (800a69c ) 800a592: 6a9b ldr r3, [r3, #40] ; 0x28 800a594: f423 327c bic.w r2, r3, #258048 ; 0x3f000 800a598: 687b ldr r3, [r7, #4] 800a59a: 681b ldr r3, [r3, #0] 800a59c: 031b lsls r3, r3, #12 800a59e: 493f ldr r1, [pc, #252] ; (800a69c ) 800a5a0: 4313 orrs r3, r2 800a5a2: 628b str r3, [r1, #40] ; 0x28 800a5a4: 687b ldr r3, [r7, #4] 800a5a6: 685b ldr r3, [r3, #4] 800a5a8: 3b01 subs r3, #1 800a5aa: f3c3 0208 ubfx r2, r3, #0, #9 800a5ae: 687b ldr r3, [r7, #4] 800a5b0: 689b ldr r3, [r3, #8] 800a5b2: 3b01 subs r3, #1 800a5b4: 025b lsls r3, r3, #9 800a5b6: b29b uxth r3, r3 800a5b8: 431a orrs r2, r3 800a5ba: 687b ldr r3, [r7, #4] 800a5bc: 68db ldr r3, [r3, #12] 800a5be: 3b01 subs r3, #1 800a5c0: 041b lsls r3, r3, #16 800a5c2: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 800a5c6: 431a orrs r2, r3 800a5c8: 687b ldr r3, [r7, #4] 800a5ca: 691b ldr r3, [r3, #16] 800a5cc: 3b01 subs r3, #1 800a5ce: 061b lsls r3, r3, #24 800a5d0: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 800a5d4: 4931 ldr r1, [pc, #196] ; (800a69c ) 800a5d6: 4313 orrs r3, r2 800a5d8: 638b str r3, [r1, #56] ; 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 800a5da: 4b30 ldr r3, [pc, #192] ; (800a69c ) 800a5dc: 6adb ldr r3, [r3, #44] ; 0x2c 800a5de: f023 02c0 bic.w r2, r3, #192 ; 0xc0 800a5e2: 687b ldr r3, [r7, #4] 800a5e4: 695b ldr r3, [r3, #20] 800a5e6: 492d ldr r1, [pc, #180] ; (800a69c ) 800a5e8: 4313 orrs r3, r2 800a5ea: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 800a5ec: 4b2b ldr r3, [pc, #172] ; (800a69c ) 800a5ee: 6adb ldr r3, [r3, #44] ; 0x2c 800a5f0: f023 0220 bic.w r2, r3, #32 800a5f4: 687b ldr r3, [r7, #4] 800a5f6: 699b ldr r3, [r3, #24] 800a5f8: 4928 ldr r1, [pc, #160] ; (800a69c ) 800a5fa: 4313 orrs r3, r2 800a5fc: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800a5fe: 4b27 ldr r3, [pc, #156] ; (800a69c ) 800a600: 6adb ldr r3, [r3, #44] ; 0x2c 800a602: 4a26 ldr r2, [pc, #152] ; (800a69c ) 800a604: f023 0310 bic.w r3, r3, #16 800a608: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 800a60a: 4b24 ldr r3, [pc, #144] ; (800a69c ) 800a60c: 6bda ldr r2, [r3, #60] ; 0x3c 800a60e: 4b24 ldr r3, [pc, #144] ; (800a6a0 ) 800a610: 4013 ands r3, r2 800a612: 687a ldr r2, [r7, #4] 800a614: 69d2 ldr r2, [r2, #28] 800a616: 00d2 lsls r2, r2, #3 800a618: 4920 ldr r1, [pc, #128] ; (800a69c ) 800a61a: 4313 orrs r3, r2 800a61c: 63cb str r3, [r1, #60] ; 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800a61e: 4b1f ldr r3, [pc, #124] ; (800a69c ) 800a620: 6adb ldr r3, [r3, #44] ; 0x2c 800a622: 4a1e ldr r2, [pc, #120] ; (800a69c ) 800a624: f043 0310 orr.w r3, r3, #16 800a628: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 800a62a: 683b ldr r3, [r7, #0] 800a62c: 2b00 cmp r3, #0 800a62e: d106 bne.n 800a63e { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800a630: 4b1a ldr r3, [pc, #104] ; (800a69c ) 800a632: 6adb ldr r3, [r3, #44] ; 0x2c 800a634: 4a19 ldr r2, [pc, #100] ; (800a69c ) 800a636: f443 2300 orr.w r3, r3, #524288 ; 0x80000 800a63a: 62d3 str r3, [r2, #44] ; 0x2c 800a63c: e00f b.n 800a65e } else if (Divider == DIVIDER_Q_UPDATE) 800a63e: 683b ldr r3, [r7, #0] 800a640: 2b01 cmp r3, #1 800a642: d106 bne.n 800a652 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 800a644: 4b15 ldr r3, [pc, #84] ; (800a69c ) 800a646: 6adb ldr r3, [r3, #44] ; 0x2c 800a648: 4a14 ldr r2, [pc, #80] ; (800a69c ) 800a64a: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 800a64e: 62d3 str r3, [r2, #44] ; 0x2c 800a650: e005 b.n 800a65e } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800a652: 4b12 ldr r3, [pc, #72] ; (800a69c ) 800a654: 6adb ldr r3, [r3, #44] ; 0x2c 800a656: 4a11 ldr r2, [pc, #68] ; (800a69c ) 800a658: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 800a65c: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800a65e: 4b0f ldr r3, [pc, #60] ; (800a69c ) 800a660: 681b ldr r3, [r3, #0] 800a662: 4a0e ldr r2, [pc, #56] ; (800a69c ) 800a664: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 800a668: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a66a: f7f7 fe7b bl 8002364 800a66e: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800a670: e008 b.n 800a684 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800a672: f7f7 fe77 bl 8002364 800a676: 4602 mov r2, r0 800a678: 68bb ldr r3, [r7, #8] 800a67a: 1ad3 subs r3, r2, r3 800a67c: 2b02 cmp r3, #2 800a67e: d901 bls.n 800a684 { return HAL_TIMEOUT; 800a680: 2303 movs r3, #3 800a682: e006 b.n 800a692 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800a684: 4b05 ldr r3, [pc, #20] ; (800a69c ) 800a686: 681b ldr r3, [r3, #0] 800a688: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 800a68c: 2b00 cmp r3, #0 800a68e: d0f0 beq.n 800a672 } } return status; 800a690: 7bfb ldrb r3, [r7, #15] } 800a692: 4618 mov r0, r3 800a694: 3710 adds r7, #16 800a696: 46bd mov sp, r7 800a698: bd80 pop {r7, pc} 800a69a: bf00 nop 800a69c: 58024400 .word 0x58024400 800a6a0: ffff0007 .word 0xffff0007 0800a6a4 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 800a6a4: b580 push {r7, lr} 800a6a6: b084 sub sp, #16 800a6a8: af00 add r7, sp, #0 800a6aa: 6078 str r0, [r7, #4] 800a6ac: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800a6ae: 2300 movs r3, #0 800a6b0: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800a6b2: 4b53 ldr r3, [pc, #332] ; (800a800 ) 800a6b4: 6a9b ldr r3, [r3, #40] ; 0x28 800a6b6: f003 0303 and.w r3, r3, #3 800a6ba: 2b03 cmp r3, #3 800a6bc: d101 bne.n 800a6c2 { return HAL_ERROR; 800a6be: 2301 movs r3, #1 800a6c0: e099 b.n 800a7f6 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 800a6c2: 4b4f ldr r3, [pc, #316] ; (800a800 ) 800a6c4: 681b ldr r3, [r3, #0] 800a6c6: 4a4e ldr r2, [pc, #312] ; (800a800 ) 800a6c8: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800a6cc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a6ce: f7f7 fe49 bl 8002364 800a6d2: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800a6d4: e008 b.n 800a6e8 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800a6d6: f7f7 fe45 bl 8002364 800a6da: 4602 mov r2, r0 800a6dc: 68bb ldr r3, [r7, #8] 800a6de: 1ad3 subs r3, r2, r3 800a6e0: 2b02 cmp r3, #2 800a6e2: d901 bls.n 800a6e8 { return HAL_TIMEOUT; 800a6e4: 2303 movs r3, #3 800a6e6: e086 b.n 800a7f6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800a6e8: 4b45 ldr r3, [pc, #276] ; (800a800 ) 800a6ea: 681b ldr r3, [r3, #0] 800a6ec: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800a6f0: 2b00 cmp r3, #0 800a6f2: d1f0 bne.n 800a6d6 } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 800a6f4: 4b42 ldr r3, [pc, #264] ; (800a800 ) 800a6f6: 6a9b ldr r3, [r3, #40] ; 0x28 800a6f8: f023 727c bic.w r2, r3, #66060288 ; 0x3f00000 800a6fc: 687b ldr r3, [r7, #4] 800a6fe: 681b ldr r3, [r3, #0] 800a700: 051b lsls r3, r3, #20 800a702: 493f ldr r1, [pc, #252] ; (800a800 ) 800a704: 4313 orrs r3, r2 800a706: 628b str r3, [r1, #40] ; 0x28 800a708: 687b ldr r3, [r7, #4] 800a70a: 685b ldr r3, [r3, #4] 800a70c: 3b01 subs r3, #1 800a70e: f3c3 0208 ubfx r2, r3, #0, #9 800a712: 687b ldr r3, [r7, #4] 800a714: 689b ldr r3, [r3, #8] 800a716: 3b01 subs r3, #1 800a718: 025b lsls r3, r3, #9 800a71a: b29b uxth r3, r3 800a71c: 431a orrs r2, r3 800a71e: 687b ldr r3, [r7, #4] 800a720: 68db ldr r3, [r3, #12] 800a722: 3b01 subs r3, #1 800a724: 041b lsls r3, r3, #16 800a726: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 800a72a: 431a orrs r2, r3 800a72c: 687b ldr r3, [r7, #4] 800a72e: 691b ldr r3, [r3, #16] 800a730: 3b01 subs r3, #1 800a732: 061b lsls r3, r3, #24 800a734: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 800a738: 4931 ldr r1, [pc, #196] ; (800a800 ) 800a73a: 4313 orrs r3, r2 800a73c: 640b str r3, [r1, #64] ; 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800a73e: 4b30 ldr r3, [pc, #192] ; (800a800 ) 800a740: 6adb ldr r3, [r3, #44] ; 0x2c 800a742: f423 6240 bic.w r2, r3, #3072 ; 0xc00 800a746: 687b ldr r3, [r7, #4] 800a748: 695b ldr r3, [r3, #20] 800a74a: 492d ldr r1, [pc, #180] ; (800a800 ) 800a74c: 4313 orrs r3, r2 800a74e: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800a750: 4b2b ldr r3, [pc, #172] ; (800a800 ) 800a752: 6adb ldr r3, [r3, #44] ; 0x2c 800a754: f423 7200 bic.w r2, r3, #512 ; 0x200 800a758: 687b ldr r3, [r7, #4] 800a75a: 699b ldr r3, [r3, #24] 800a75c: 4928 ldr r1, [pc, #160] ; (800a800 ) 800a75e: 4313 orrs r3, r2 800a760: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800a762: 4b27 ldr r3, [pc, #156] ; (800a800 ) 800a764: 6adb ldr r3, [r3, #44] ; 0x2c 800a766: 4a26 ldr r2, [pc, #152] ; (800a800 ) 800a768: f423 7380 bic.w r3, r3, #256 ; 0x100 800a76c: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800a76e: 4b24 ldr r3, [pc, #144] ; (800a800 ) 800a770: 6c5a ldr r2, [r3, #68] ; 0x44 800a772: 4b24 ldr r3, [pc, #144] ; (800a804 ) 800a774: 4013 ands r3, r2 800a776: 687a ldr r2, [r7, #4] 800a778: 69d2 ldr r2, [r2, #28] 800a77a: 00d2 lsls r2, r2, #3 800a77c: 4920 ldr r1, [pc, #128] ; (800a800 ) 800a77e: 4313 orrs r3, r2 800a780: 644b str r3, [r1, #68] ; 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800a782: 4b1f ldr r3, [pc, #124] ; (800a800 ) 800a784: 6adb ldr r3, [r3, #44] ; 0x2c 800a786: 4a1e ldr r2, [pc, #120] ; (800a800 ) 800a788: f443 7380 orr.w r3, r3, #256 ; 0x100 800a78c: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 800a78e: 683b ldr r3, [r7, #0] 800a790: 2b00 cmp r3, #0 800a792: d106 bne.n 800a7a2 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 800a794: 4b1a ldr r3, [pc, #104] ; (800a800 ) 800a796: 6adb ldr r3, [r3, #44] ; 0x2c 800a798: 4a19 ldr r2, [pc, #100] ; (800a800 ) 800a79a: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 800a79e: 62d3 str r3, [r2, #44] ; 0x2c 800a7a0: e00f b.n 800a7c2 } else if (Divider == DIVIDER_Q_UPDATE) 800a7a2: 683b ldr r3, [r7, #0] 800a7a4: 2b01 cmp r3, #1 800a7a6: d106 bne.n 800a7b6 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800a7a8: 4b15 ldr r3, [pc, #84] ; (800a800 ) 800a7aa: 6adb ldr r3, [r3, #44] ; 0x2c 800a7ac: 4a14 ldr r2, [pc, #80] ; (800a800 ) 800a7ae: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 800a7b2: 62d3 str r3, [r2, #44] ; 0x2c 800a7b4: e005 b.n 800a7c2 } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 800a7b6: 4b12 ldr r3, [pc, #72] ; (800a800 ) 800a7b8: 6adb ldr r3, [r3, #44] ; 0x2c 800a7ba: 4a11 ldr r2, [pc, #68] ; (800a800 ) 800a7bc: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 800a7c0: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 800a7c2: 4b0f ldr r3, [pc, #60] ; (800a800 ) 800a7c4: 681b ldr r3, [r3, #0] 800a7c6: 4a0e ldr r2, [pc, #56] ; (800a800 ) 800a7c8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 800a7cc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a7ce: f7f7 fdc9 bl 8002364 800a7d2: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800a7d4: e008 b.n 800a7e8 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800a7d6: f7f7 fdc5 bl 8002364 800a7da: 4602 mov r2, r0 800a7dc: 68bb ldr r3, [r7, #8] 800a7de: 1ad3 subs r3, r2, r3 800a7e0: 2b02 cmp r3, #2 800a7e2: d901 bls.n 800a7e8 { return HAL_TIMEOUT; 800a7e4: 2303 movs r3, #3 800a7e6: e006 b.n 800a7f6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800a7e8: 4b05 ldr r3, [pc, #20] ; (800a800 ) 800a7ea: 681b ldr r3, [r3, #0] 800a7ec: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800a7f0: 2b00 cmp r3, #0 800a7f2: d0f0 beq.n 800a7d6 } } return status; 800a7f4: 7bfb ldrb r3, [r7, #15] } 800a7f6: 4618 mov r0, r3 800a7f8: 3710 adds r7, #16 800a7fa: 46bd mov sp, r7 800a7fc: bd80 pop {r7, pc} 800a7fe: bf00 nop 800a800: 58024400 .word 0x58024400 800a804: ffff0007 .word 0xffff0007 0800a808 : SD_HandleTypeDef and create the associated handle. * @param hsd: Pointer to the SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { 800a808: b580 push {r7, lr} 800a80a: b08a sub sp, #40 ; 0x28 800a80c: af00 add r7, sp, #0 800a80e: 6078 str r0, [r7, #4] uint32_t speedgrade; uint32_t unitsize; uint32_t tickstart; /* Check the SD handle allocation */ if (hsd == NULL) 800a810: 687b ldr r3, [r7, #4] 800a812: 2b00 cmp r3, #0 800a814: d101 bne.n 800a81a { return HAL_ERROR; 800a816: 2301 movs r3, #1 800a818: e075 b.n 800a906 assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide)); assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv)); if (hsd->State == HAL_SD_STATE_RESET) 800a81a: 687b ldr r3, [r7, #4] 800a81c: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 800a820: b2db uxtb r3, r3 800a822: 2b00 cmp r3, #0 800a824: d105 bne.n 800a832 { /* Allocate lock resource and initialize it */ hsd->Lock = HAL_UNLOCKED; 800a826: 687b ldr r3, [r7, #4] 800a828: 2200 movs r2, #0 800a82a: 761a strb r2, [r3, #24] /* Init the low level hardware */ hsd->MspInitCallback(hsd); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_SD_MspInit(hsd); 800a82c: 6878 ldr r0, [r7, #4] 800a82e: f7f6 ffc5 bl 80017bc #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } hsd->State = HAL_SD_STATE_PROGRAMMING; 800a832: 687b ldr r3, [r7, #4] 800a834: 2204 movs r2, #4 800a836: f883 2030 strb.w r2, [r3, #48] ; 0x30 /* Initialize the Card parameters */ if (HAL_SD_InitCard(hsd) != HAL_OK) 800a83a: 6878 ldr r0, [r7, #4] 800a83c: f000 f868 bl 800a910 800a840: 4603 mov r3, r0 800a842: 2b00 cmp r3, #0 800a844: d001 beq.n 800a84a { return HAL_ERROR; 800a846: 2301 movs r3, #1 800a848: e05d b.n 800a906 } if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK) 800a84a: f107 0308 add.w r3, r7, #8 800a84e: 4619 mov r1, r3 800a850: 6878 ldr r0, [r7, #4] 800a852: f000 fdaf bl 800b3b4 800a856: 4603 mov r3, r0 800a858: 2b00 cmp r3, #0 800a85a: d001 beq.n 800a860 { return HAL_ERROR; 800a85c: 2301 movs r3, #1 800a85e: e052 b.n 800a906 } /* Get Initial Card Speed from Card Status*/ speedgrade = CardStatus.UhsSpeedGrade; 800a860: 7e3b ldrb r3, [r7, #24] 800a862: b2db uxtb r3, r3 800a864: 627b str r3, [r7, #36] ; 0x24 unitsize = CardStatus.UhsAllocationUnitSize; 800a866: 7e7b ldrb r3, [r7, #25] 800a868: b2db uxtb r3, r3 800a86a: 623b str r3, [r7, #32] if ((hsd->SdCard.CardType == CARD_SDHC_SDXC) && ((speedgrade != 0U) || (unitsize != 0U))) 800a86c: 687b ldr r3, [r7, #4] 800a86e: 6b9b ldr r3, [r3, #56] ; 0x38 800a870: 2b01 cmp r3, #1 800a872: d10a bne.n 800a88a 800a874: 6a7b ldr r3, [r7, #36] ; 0x24 800a876: 2b00 cmp r3, #0 800a878: d102 bne.n 800a880 800a87a: 6a3b ldr r3, [r7, #32] 800a87c: 2b00 cmp r3, #0 800a87e: d004 beq.n 800a88a { hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; 800a880: 687b ldr r3, [r7, #4] 800a882: f44f 7200 mov.w r2, #512 ; 0x200 800a886: 659a str r2, [r3, #88] ; 0x58 800a888: e00b b.n 800a8a2 } else { if (hsd->SdCard.CardType == CARD_SDHC_SDXC) 800a88a: 687b ldr r3, [r7, #4] 800a88c: 6b9b ldr r3, [r3, #56] ; 0x38 800a88e: 2b01 cmp r3, #1 800a890: d104 bne.n 800a89c { hsd->SdCard.CardSpeed = CARD_HIGH_SPEED; 800a892: 687b ldr r3, [r7, #4] 800a894: f44f 7280 mov.w r2, #256 ; 0x100 800a898: 659a str r2, [r3, #88] ; 0x58 800a89a: e002 b.n 800a8a2 } else { hsd->SdCard.CardSpeed = CARD_NORMAL_SPEED; 800a89c: 687b ldr r3, [r7, #4] 800a89e: 2200 movs r2, #0 800a8a0: 659a str r2, [r3, #88] ; 0x58 } } /* Configure the bus wide */ if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) 800a8a2: 687b ldr r3, [r7, #4] 800a8a4: 68db ldr r3, [r3, #12] 800a8a6: 4619 mov r1, r3 800a8a8: 6878 ldr r0, [r7, #4] 800a8aa: f000 fe6d bl 800b588 800a8ae: 4603 mov r3, r0 800a8b0: 2b00 cmp r3, #0 800a8b2: d001 beq.n 800a8b8 { return HAL_ERROR; 800a8b4: 2301 movs r3, #1 800a8b6: e026 b.n 800a906 } /* Verify that SD card is ready to use after Initialization */ tickstart = HAL_GetTick(); 800a8b8: f7f7 fd54 bl 8002364 800a8bc: 61f8 str r0, [r7, #28] while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) 800a8be: e011 b.n 800a8e4 { if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) 800a8c0: f7f7 fd50 bl 8002364 800a8c4: 4602 mov r2, r0 800a8c6: 69fb ldr r3, [r7, #28] 800a8c8: 1ad3 subs r3, r2, r3 800a8ca: f1b3 3fff cmp.w r3, #4294967295 800a8ce: d109 bne.n 800a8e4 { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; 800a8d0: 687b ldr r3, [r7, #4] 800a8d2: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 800a8d6: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800a8d8: 687b ldr r3, [r7, #4] 800a8da: 2201 movs r2, #1 800a8dc: f883 2030 strb.w r2, [r3, #48] ; 0x30 return HAL_TIMEOUT; 800a8e0: 2303 movs r3, #3 800a8e2: e010 b.n 800a906 while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) 800a8e4: 6878 ldr r0, [r7, #4] 800a8e6: f000 ff61 bl 800b7ac 800a8ea: 4603 mov r3, r0 800a8ec: 2b04 cmp r3, #4 800a8ee: d1e7 bne.n 800a8c0 } } /* Initialize the error code */ hsd->ErrorCode = HAL_SD_ERROR_NONE; 800a8f0: 687b ldr r3, [r7, #4] 800a8f2: 2200 movs r2, #0 800a8f4: 635a str r2, [r3, #52] ; 0x34 /* Initialize the SD operation */ hsd->Context = SD_CONTEXT_NONE; 800a8f6: 687b ldr r3, [r7, #4] 800a8f8: 2200 movs r2, #0 800a8fa: 62da str r2, [r3, #44] ; 0x2c /* Initialize the SD state */ hsd->State = HAL_SD_STATE_READY; 800a8fc: 687b ldr r3, [r7, #4] 800a8fe: 2201 movs r2, #1 800a900: f883 2030 strb.w r2, [r3, #48] ; 0x30 return HAL_OK; 800a904: 2300 movs r3, #0 } 800a906: 4618 mov r0, r3 800a908: 3728 adds r7, #40 ; 0x28 800a90a: 46bd mov sp, r7 800a90c: bd80 pop {r7, pc} ... 0800a910 : * @note This function initializes the SD card. It could be used when a card re-initialization is needed. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { 800a910: b590 push {r4, r7, lr} 800a912: b08d sub sp, #52 ; 0x34 800a914: af02 add r7, sp, #8 800a916: 6078 str r0, [r7, #4] uint32_t errorstate; SD_InitTypeDef Init; uint32_t sdmmc_clk; /* Default SDMMC peripheral configuration for SD card initialization */ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; 800a918: 2300 movs r3, #0 800a91a: 60fb str r3, [r7, #12] Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; 800a91c: 2300 movs r3, #0 800a91e: 613b str r3, [r7, #16] Init.BusWide = SDMMC_BUS_WIDE_1B; 800a920: 2300 movs r3, #0 800a922: 617b str r3, [r7, #20] Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; 800a924: 2300 movs r3, #0 800a926: 61bb str r3, [r7, #24] /* Init Clock should be less or equal to 400Khz*/ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); 800a928: f44f 3080 mov.w r0, #65536 ; 0x10000 800a92c: f04f 0100 mov.w r1, #0 800a930: f7fe fd24 bl 800937c 800a934: 6278 str r0, [r7, #36] ; 0x24 if (sdmmc_clk == 0U) 800a936: 6a7b ldr r3, [r7, #36] ; 0x24 800a938: 2b00 cmp r3, #0 800a93a: d109 bne.n 800a950 { hsd->State = HAL_SD_STATE_READY; 800a93c: 687b ldr r3, [r7, #4] 800a93e: 2201 movs r2, #1 800a940: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; 800a944: 687b ldr r3, [r7, #4] 800a946: f04f 6200 mov.w r2, #134217728 ; 0x8000000 800a94a: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800a94c: 2301 movs r3, #1 800a94e: e070 b.n 800aa32 } Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ); 800a950: 6a7b ldr r3, [r7, #36] ; 0x24 800a952: 0a1b lsrs r3, r3, #8 800a954: 4a39 ldr r2, [pc, #228] ; (800aa3c ) 800a956: fba2 2303 umull r2, r3, r2, r3 800a95a: 091b lsrs r3, r3, #4 800a95c: 61fb str r3, [r7, #28] /* Set Transceiver polarity */ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; #endif /* USE_SD_TRANSCEIVER */ /* Initialize SDMMC peripheral interface with default configuration */ (void)SDMMC_Init(hsd->Instance, Init); 800a95e: 687b ldr r3, [r7, #4] 800a960: 681c ldr r4, [r3, #0] 800a962: 466a mov r2, sp 800a964: f107 0318 add.w r3, r7, #24 800a968: e893 0003 ldmia.w r3, {r0, r1} 800a96c: e882 0003 stmia.w r2, {r0, r1} 800a970: f107 030c add.w r3, r7, #12 800a974: cb0e ldmia r3, {r1, r2, r3} 800a976: 4620 mov r0, r4 800a978: f003 faa0 bl 800debc /* Set Power State to ON */ (void)SDMMC_PowerState_ON(hsd->Instance); 800a97c: 687b ldr r3, [r7, #4] 800a97e: 681b ldr r3, [r3, #0] 800a980: 4618 mov r0, r3 800a982: f003 fae3 bl 800df4c /* wait 74 Cycles: required power up waiting time before starting the SD initialization sequence */ if (Init.ClockDiv != 0U) 800a986: 69fb ldr r3, [r7, #28] 800a988: 2b00 cmp r3, #0 800a98a: d005 beq.n 800a998 { sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); 800a98c: 69fb ldr r3, [r7, #28] 800a98e: 005b lsls r3, r3, #1 800a990: 6a7a ldr r2, [r7, #36] ; 0x24 800a992: fbb2 f3f3 udiv r3, r2, r3 800a996: 627b str r3, [r7, #36] ; 0x24 } if (sdmmc_clk != 0U) 800a998: 6a7b ldr r3, [r7, #36] ; 0x24 800a99a: 2b00 cmp r3, #0 800a99c: d007 beq.n 800a9ae { HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); 800a99e: 4a28 ldr r2, [pc, #160] ; (800aa40 ) 800a9a0: 6a7b ldr r3, [r7, #36] ; 0x24 800a9a2: fbb2 f3f3 udiv r3, r2, r3 800a9a6: 3301 adds r3, #1 800a9a8: 4618 mov r0, r3 800a9aa: f7f7 fce7 bl 800237c } /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); 800a9ae: 6878 ldr r0, [r7, #4] 800a9b0: f000 ffea bl 800b988 800a9b4: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 800a9b6: 6a3b ldr r3, [r7, #32] 800a9b8: 2b00 cmp r3, #0 800a9ba: d00b beq.n 800a9d4 { hsd->State = HAL_SD_STATE_READY; 800a9bc: 687b ldr r3, [r7, #4] 800a9be: 2201 movs r2, #1 800a9c0: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->ErrorCode |= errorstate; 800a9c4: 687b ldr r3, [r7, #4] 800a9c6: 6b5a ldr r2, [r3, #52] ; 0x34 800a9c8: 6a3b ldr r3, [r7, #32] 800a9ca: 431a orrs r2, r3 800a9cc: 687b ldr r3, [r7, #4] 800a9ce: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800a9d0: 2301 movs r3, #1 800a9d2: e02e b.n 800aa32 } /* Card initialization */ errorstate = SD_InitCard(hsd); 800a9d4: 6878 ldr r0, [r7, #4] 800a9d6: f000 ff09 bl 800b7ec 800a9da: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 800a9dc: 6a3b ldr r3, [r7, #32] 800a9de: 2b00 cmp r3, #0 800a9e0: d00b beq.n 800a9fa { hsd->State = HAL_SD_STATE_READY; 800a9e2: 687b ldr r3, [r7, #4] 800a9e4: 2201 movs r2, #1 800a9e6: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->ErrorCode |= errorstate; 800a9ea: 687b ldr r3, [r7, #4] 800a9ec: 6b5a ldr r2, [r3, #52] ; 0x34 800a9ee: 6a3b ldr r3, [r7, #32] 800a9f0: 431a orrs r2, r3 800a9f2: 687b ldr r3, [r7, #4] 800a9f4: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800a9f6: 2301 movs r3, #1 800a9f8: e01b b.n 800aa32 } /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); 800a9fa: 687b ldr r3, [r7, #4] 800a9fc: 681b ldr r3, [r3, #0] 800a9fe: f44f 7100 mov.w r1, #512 ; 0x200 800aa02: 4618 mov r0, r3 800aa04: f003 fb38 bl 800e078 800aa08: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 800aa0a: 6a3b ldr r3, [r7, #32] 800aa0c: 2b00 cmp r3, #0 800aa0e: d00f beq.n 800aa30 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800aa10: 687b ldr r3, [r7, #4] 800aa12: 681b ldr r3, [r3, #0] 800aa14: 4a0b ldr r2, [pc, #44] ; (800aa44 ) 800aa16: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 800aa18: 687b ldr r3, [r7, #4] 800aa1a: 6b5a ldr r2, [r3, #52] ; 0x34 800aa1c: 6a3b ldr r3, [r7, #32] 800aa1e: 431a orrs r2, r3 800aa20: 687b ldr r3, [r7, #4] 800aa22: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800aa24: 687b ldr r3, [r7, #4] 800aa26: 2201 movs r2, #1 800aa28: f883 2030 strb.w r2, [r3, #48] ; 0x30 return HAL_ERROR; 800aa2c: 2301 movs r3, #1 800aa2e: e000 b.n 800aa32 } return HAL_OK; 800aa30: 2300 movs r3, #0 } 800aa32: 4618 mov r0, r3 800aa34: 372c adds r7, #44 ; 0x2c 800aa36: 46bd mov sp, r7 800aa38: bd90 pop {r4, r7, pc} 800aa3a: bf00 nop 800aa3c: 014f8b59 .word 0x014f8b59 800aa40: 00012110 .word 0x00012110 800aa44: 1fe00fff .word 0x1fe00fff 0800aa48 : * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { 800aa48: b580 push {r7, lr} 800aa4a: b08c sub sp, #48 ; 0x30 800aa4c: af00 add r7, sp, #0 800aa4e: 60f8 str r0, [r7, #12] 800aa50: 60b9 str r1, [r7, #8] 800aa52: 607a str r2, [r7, #4] 800aa54: 603b str r3, [r7, #0] SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; 800aa56: 687b ldr r3, [r7, #4] 800aa58: 62bb str r3, [r7, #40] ; 0x28 if (NULL == pData) 800aa5a: 68bb ldr r3, [r7, #8] 800aa5c: 2b00 cmp r3, #0 800aa5e: d107 bne.n 800aa70 { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; 800aa60: 68fb ldr r3, [r7, #12] 800aa62: 6b5b ldr r3, [r3, #52] ; 0x34 800aa64: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 800aa68: 68fb ldr r3, [r7, #12] 800aa6a: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800aa6c: 2301 movs r3, #1 800aa6e: e08d b.n 800ab8c } if (hsd->State == HAL_SD_STATE_READY) 800aa70: 68fb ldr r3, [r7, #12] 800aa72: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 800aa76: b2db uxtb r3, r3 800aa78: 2b01 cmp r3, #1 800aa7a: f040 8086 bne.w 800ab8a { hsd->ErrorCode = HAL_SD_ERROR_NONE; 800aa7e: 68fb ldr r3, [r7, #12] 800aa80: 2200 movs r2, #0 800aa82: 635a str r2, [r3, #52] ; 0x34 if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) 800aa84: 6aba ldr r2, [r7, #40] ; 0x28 800aa86: 683b ldr r3, [r7, #0] 800aa88: 441a add r2, r3 800aa8a: 68fb ldr r3, [r7, #12] 800aa8c: 6d1b ldr r3, [r3, #80] ; 0x50 800aa8e: 429a cmp r2, r3 800aa90: d907 bls.n 800aaa2 { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; 800aa92: 68fb ldr r3, [r7, #12] 800aa94: 6b5b ldr r3, [r3, #52] ; 0x34 800aa96: f043 7200 orr.w r2, r3, #33554432 ; 0x2000000 800aa9a: 68fb ldr r3, [r7, #12] 800aa9c: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800aa9e: 2301 movs r3, #1 800aaa0: e074 b.n 800ab8c } hsd->State = HAL_SD_STATE_BUSY; 800aaa2: 68fb ldr r3, [r7, #12] 800aaa4: 2203 movs r2, #3 800aaa6: f883 2030 strb.w r2, [r3, #48] ; 0x30 /* Initialize data control register */ hsd->Instance->DCTRL = 0U; 800aaaa: 68fb ldr r3, [r7, #12] 800aaac: 681b ldr r3, [r3, #0] 800aaae: 2200 movs r2, #0 800aab0: 62da str r2, [r3, #44] ; 0x2c hsd->pRxBuffPtr = pData; 800aab2: 68fb ldr r3, [r7, #12] 800aab4: 68ba ldr r2, [r7, #8] 800aab6: 625a str r2, [r3, #36] ; 0x24 hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; 800aab8: 683b ldr r3, [r7, #0] 800aaba: 025a lsls r2, r3, #9 800aabc: 68fb ldr r3, [r7, #12] 800aabe: 629a str r2, [r3, #40] ; 0x28 if (hsd->SdCard.CardType != CARD_SDHC_SDXC) 800aac0: 68fb ldr r3, [r7, #12] 800aac2: 6b9b ldr r3, [r3, #56] ; 0x38 800aac4: 2b01 cmp r3, #1 800aac6: d002 beq.n 800aace { add *= 512U; 800aac8: 6abb ldr r3, [r7, #40] ; 0x28 800aaca: 025b lsls r3, r3, #9 800aacc: 62bb str r3, [r7, #40] ; 0x28 } /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; 800aace: f04f 33ff mov.w r3, #4294967295 800aad2: 613b str r3, [r7, #16] config.DataLength = BLOCKSIZE * NumberOfBlocks; 800aad4: 683b ldr r3, [r7, #0] 800aad6: 025b lsls r3, r3, #9 800aad8: 617b str r3, [r7, #20] config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; 800aada: 2390 movs r3, #144 ; 0x90 800aadc: 61bb str r3, [r7, #24] config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; 800aade: 2302 movs r3, #2 800aae0: 61fb str r3, [r7, #28] config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; 800aae2: 2300 movs r3, #0 800aae4: 623b str r3, [r7, #32] config.DPSM = SDMMC_DPSM_DISABLE; 800aae6: 2300 movs r3, #0 800aae8: 627b str r3, [r7, #36] ; 0x24 (void)SDMMC_ConfigData(hsd->Instance, &config); 800aaea: 68fb ldr r3, [r7, #12] 800aaec: 681b ldr r3, [r3, #0] 800aaee: f107 0210 add.w r2, r7, #16 800aaf2: 4611 mov r1, r2 800aaf4: 4618 mov r0, r3 800aaf6: f003 fa93 bl 800e020 __SDMMC_CMDTRANS_ENABLE(hsd->Instance); 800aafa: 68fb ldr r3, [r7, #12] 800aafc: 681b ldr r3, [r3, #0] 800aafe: 68da ldr r2, [r3, #12] 800ab00: 68fb ldr r3, [r7, #12] 800ab02: 681b ldr r3, [r3, #0] 800ab04: f042 0240 orr.w r2, r2, #64 ; 0x40 800ab08: 60da str r2, [r3, #12] hsd->Instance->IDMABASE0 = (uint32_t) pData ; 800ab0a: 68fb ldr r3, [r7, #12] 800ab0c: 681b ldr r3, [r3, #0] 800ab0e: 68ba ldr r2, [r7, #8] 800ab10: 659a str r2, [r3, #88] ; 0x58 hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; 800ab12: 68fb ldr r3, [r7, #12] 800ab14: 681b ldr r3, [r3, #0] 800ab16: 2201 movs r2, #1 800ab18: 651a str r2, [r3, #80] ; 0x50 /* Read Blocks in DMA mode */ if (NumberOfBlocks > 1U) 800ab1a: 683b ldr r3, [r7, #0] 800ab1c: 2b01 cmp r3, #1 800ab1e: d90a bls.n 800ab36 { hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); 800ab20: 68fb ldr r3, [r7, #12] 800ab22: 2282 movs r2, #130 ; 0x82 800ab24: 62da str r2, [r3, #44] ; 0x2c /* Read Multi Block command */ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); 800ab26: 68fb ldr r3, [r7, #12] 800ab28: 681b ldr r3, [r3, #0] 800ab2a: 6ab9 ldr r1, [r7, #40] ; 0x28 800ab2c: 4618 mov r0, r3 800ab2e: f003 fae9 bl 800e104 800ab32: 62f8 str r0, [r7, #44] ; 0x2c 800ab34: e009 b.n 800ab4a } else { hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); 800ab36: 68fb ldr r3, [r7, #12] 800ab38: 2281 movs r2, #129 ; 0x81 800ab3a: 62da str r2, [r3, #44] ; 0x2c /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); 800ab3c: 68fb ldr r3, [r7, #12] 800ab3e: 681b ldr r3, [r3, #0] 800ab40: 6ab9 ldr r1, [r7, #40] ; 0x28 800ab42: 4618 mov r0, r3 800ab44: f003 fabb bl 800e0be 800ab48: 62f8 str r0, [r7, #44] ; 0x2c } if (errorstate != HAL_SD_ERROR_NONE) 800ab4a: 6afb ldr r3, [r7, #44] ; 0x2c 800ab4c: 2b00 cmp r3, #0 800ab4e: d012 beq.n 800ab76 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800ab50: 68fb ldr r3, [r7, #12] 800ab52: 681b ldr r3, [r3, #0] 800ab54: 4a0f ldr r2, [pc, #60] ; (800ab94 ) 800ab56: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 800ab58: 68fb ldr r3, [r7, #12] 800ab5a: 6b5a ldr r2, [r3, #52] ; 0x34 800ab5c: 6afb ldr r3, [r7, #44] ; 0x2c 800ab5e: 431a orrs r2, r3 800ab60: 68fb ldr r3, [r7, #12] 800ab62: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800ab64: 68fb ldr r3, [r7, #12] 800ab66: 2201 movs r2, #1 800ab68: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800ab6c: 68fb ldr r3, [r7, #12] 800ab6e: 2200 movs r2, #0 800ab70: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800ab72: 2301 movs r3, #1 800ab74: e00a b.n 800ab8c } /* Enable transfer interrupts */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); 800ab76: 68fb ldr r3, [r7, #12] 800ab78: 681b ldr r3, [r3, #0] 800ab7a: 6bda ldr r2, [r3, #60] ; 0x3c 800ab7c: 68fb ldr r3, [r7, #12] 800ab7e: 681b ldr r3, [r3, #0] 800ab80: f442 7295 orr.w r2, r2, #298 ; 0x12a 800ab84: 63da str r2, [r3, #60] ; 0x3c return HAL_OK; 800ab86: 2300 movs r3, #0 800ab88: e000 b.n 800ab8c } else { return HAL_BUSY; 800ab8a: 2302 movs r3, #2 } } 800ab8c: 4618 mov r0, r3 800ab8e: 3730 adds r7, #48 ; 0x30 800ab90: 46bd mov sp, r7 800ab92: bd80 pop {r7, pc} 800ab94: 1fe00fff .word 0x1fe00fff 0800ab98 : * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { 800ab98: b580 push {r7, lr} 800ab9a: b08c sub sp, #48 ; 0x30 800ab9c: af00 add r7, sp, #0 800ab9e: 60f8 str r0, [r7, #12] 800aba0: 60b9 str r1, [r7, #8] 800aba2: 607a str r2, [r7, #4] 800aba4: 603b str r3, [r7, #0] SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; 800aba6: 687b ldr r3, [r7, #4] 800aba8: 62bb str r3, [r7, #40] ; 0x28 if (NULL == pData) 800abaa: 68bb ldr r3, [r7, #8] 800abac: 2b00 cmp r3, #0 800abae: d107 bne.n 800abc0 { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; 800abb0: 68fb ldr r3, [r7, #12] 800abb2: 6b5b ldr r3, [r3, #52] ; 0x34 800abb4: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 800abb8: 68fb ldr r3, [r7, #12] 800abba: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800abbc: 2301 movs r3, #1 800abbe: e08d b.n 800acdc } if (hsd->State == HAL_SD_STATE_READY) 800abc0: 68fb ldr r3, [r7, #12] 800abc2: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 800abc6: b2db uxtb r3, r3 800abc8: 2b01 cmp r3, #1 800abca: f040 8086 bne.w 800acda { hsd->ErrorCode = HAL_SD_ERROR_NONE; 800abce: 68fb ldr r3, [r7, #12] 800abd0: 2200 movs r2, #0 800abd2: 635a str r2, [r3, #52] ; 0x34 if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) 800abd4: 6aba ldr r2, [r7, #40] ; 0x28 800abd6: 683b ldr r3, [r7, #0] 800abd8: 441a add r2, r3 800abda: 68fb ldr r3, [r7, #12] 800abdc: 6d1b ldr r3, [r3, #80] ; 0x50 800abde: 429a cmp r2, r3 800abe0: d907 bls.n 800abf2 { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; 800abe2: 68fb ldr r3, [r7, #12] 800abe4: 6b5b ldr r3, [r3, #52] ; 0x34 800abe6: f043 7200 orr.w r2, r3, #33554432 ; 0x2000000 800abea: 68fb ldr r3, [r7, #12] 800abec: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800abee: 2301 movs r3, #1 800abf0: e074 b.n 800acdc } hsd->State = HAL_SD_STATE_BUSY; 800abf2: 68fb ldr r3, [r7, #12] 800abf4: 2203 movs r2, #3 800abf6: f883 2030 strb.w r2, [r3, #48] ; 0x30 /* Initialize data control register */ hsd->Instance->DCTRL = 0U; 800abfa: 68fb ldr r3, [r7, #12] 800abfc: 681b ldr r3, [r3, #0] 800abfe: 2200 movs r2, #0 800ac00: 62da str r2, [r3, #44] ; 0x2c hsd->pTxBuffPtr = pData; 800ac02: 68fb ldr r3, [r7, #12] 800ac04: 68ba ldr r2, [r7, #8] 800ac06: 61da str r2, [r3, #28] hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; 800ac08: 683b ldr r3, [r7, #0] 800ac0a: 025a lsls r2, r3, #9 800ac0c: 68fb ldr r3, [r7, #12] 800ac0e: 621a str r2, [r3, #32] if (hsd->SdCard.CardType != CARD_SDHC_SDXC) 800ac10: 68fb ldr r3, [r7, #12] 800ac12: 6b9b ldr r3, [r3, #56] ; 0x38 800ac14: 2b01 cmp r3, #1 800ac16: d002 beq.n 800ac1e { add *= 512U; 800ac18: 6abb ldr r3, [r7, #40] ; 0x28 800ac1a: 025b lsls r3, r3, #9 800ac1c: 62bb str r3, [r7, #40] ; 0x28 } /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; 800ac1e: f04f 33ff mov.w r3, #4294967295 800ac22: 613b str r3, [r7, #16] config.DataLength = BLOCKSIZE * NumberOfBlocks; 800ac24: 683b ldr r3, [r7, #0] 800ac26: 025b lsls r3, r3, #9 800ac28: 617b str r3, [r7, #20] config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; 800ac2a: 2390 movs r3, #144 ; 0x90 800ac2c: 61bb str r3, [r7, #24] config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; 800ac2e: 2300 movs r3, #0 800ac30: 61fb str r3, [r7, #28] config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; 800ac32: 2300 movs r3, #0 800ac34: 623b str r3, [r7, #32] config.DPSM = SDMMC_DPSM_DISABLE; 800ac36: 2300 movs r3, #0 800ac38: 627b str r3, [r7, #36] ; 0x24 (void)SDMMC_ConfigData(hsd->Instance, &config); 800ac3a: 68fb ldr r3, [r7, #12] 800ac3c: 681b ldr r3, [r3, #0] 800ac3e: f107 0210 add.w r2, r7, #16 800ac42: 4611 mov r1, r2 800ac44: 4618 mov r0, r3 800ac46: f003 f9eb bl 800e020 __SDMMC_CMDTRANS_ENABLE(hsd->Instance); 800ac4a: 68fb ldr r3, [r7, #12] 800ac4c: 681b ldr r3, [r3, #0] 800ac4e: 68da ldr r2, [r3, #12] 800ac50: 68fb ldr r3, [r7, #12] 800ac52: 681b ldr r3, [r3, #0] 800ac54: f042 0240 orr.w r2, r2, #64 ; 0x40 800ac58: 60da str r2, [r3, #12] hsd->Instance->IDMABASE0 = (uint32_t) pData ; 800ac5a: 68fb ldr r3, [r7, #12] 800ac5c: 681b ldr r3, [r3, #0] 800ac5e: 68ba ldr r2, [r7, #8] 800ac60: 659a str r2, [r3, #88] ; 0x58 hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; 800ac62: 68fb ldr r3, [r7, #12] 800ac64: 681b ldr r3, [r3, #0] 800ac66: 2201 movs r2, #1 800ac68: 651a str r2, [r3, #80] ; 0x50 /* Write Blocks in Polling mode */ if (NumberOfBlocks > 1U) 800ac6a: 683b ldr r3, [r7, #0] 800ac6c: 2b01 cmp r3, #1 800ac6e: d90a bls.n 800ac86 { hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); 800ac70: 68fb ldr r3, [r7, #12] 800ac72: 22a0 movs r2, #160 ; 0xa0 800ac74: 62da str r2, [r3, #44] ; 0x2c /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); 800ac76: 68fb ldr r3, [r7, #12] 800ac78: 681b ldr r3, [r3, #0] 800ac7a: 6ab9 ldr r1, [r7, #40] ; 0x28 800ac7c: 4618 mov r0, r3 800ac7e: f003 fa87 bl 800e190 800ac82: 62f8 str r0, [r7, #44] ; 0x2c 800ac84: e009 b.n 800ac9a } else { hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); 800ac86: 68fb ldr r3, [r7, #12] 800ac88: 2290 movs r2, #144 ; 0x90 800ac8a: 62da str r2, [r3, #44] ; 0x2c /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); 800ac8c: 68fb ldr r3, [r7, #12] 800ac8e: 681b ldr r3, [r3, #0] 800ac90: 6ab9 ldr r1, [r7, #40] ; 0x28 800ac92: 4618 mov r0, r3 800ac94: f003 fa59 bl 800e14a 800ac98: 62f8 str r0, [r7, #44] ; 0x2c } if (errorstate != HAL_SD_ERROR_NONE) 800ac9a: 6afb ldr r3, [r7, #44] ; 0x2c 800ac9c: 2b00 cmp r3, #0 800ac9e: d012 beq.n 800acc6 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800aca0: 68fb ldr r3, [r7, #12] 800aca2: 681b ldr r3, [r3, #0] 800aca4: 4a0f ldr r2, [pc, #60] ; (800ace4 ) 800aca6: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 800aca8: 68fb ldr r3, [r7, #12] 800acaa: 6b5a ldr r2, [r3, #52] ; 0x34 800acac: 6afb ldr r3, [r7, #44] ; 0x2c 800acae: 431a orrs r2, r3 800acb0: 68fb ldr r3, [r7, #12] 800acb2: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800acb4: 68fb ldr r3, [r7, #12] 800acb6: 2201 movs r2, #1 800acb8: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800acbc: 68fb ldr r3, [r7, #12] 800acbe: 2200 movs r2, #0 800acc0: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800acc2: 2301 movs r3, #1 800acc4: e00a b.n 800acdc } /* Enable transfer interrupts */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); 800acc6: 68fb ldr r3, [r7, #12] 800acc8: 681b ldr r3, [r3, #0] 800acca: 6bda ldr r2, [r3, #60] ; 0x3c 800accc: 68fb ldr r3, [r7, #12] 800acce: 681b ldr r3, [r3, #0] 800acd0: f442 728d orr.w r2, r2, #282 ; 0x11a 800acd4: 63da str r2, [r3, #60] ; 0x3c return HAL_OK; 800acd6: 2300 movs r3, #0 800acd8: e000 b.n 800acdc } else { return HAL_BUSY; 800acda: 2302 movs r3, #2 } } 800acdc: 4618 mov r0, r3 800acde: 3730 adds r7, #48 ; 0x30 800ace0: 46bd mov sp, r7 800ace2: bd80 pop {r7, pc} 800ace4: 1fe00fff .word 0x1fe00fff 0800ace8 : * @brief This function handles SD card interrupt request. * @param hsd: Pointer to SD handle * @retval None */ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) { 800ace8: b580 push {r7, lr} 800acea: b084 sub sp, #16 800acec: af00 add r7, sp, #0 800acee: 6078 str r0, [r7, #4] uint32_t errorstate; uint32_t context = hsd->Context; 800acf0: 687b ldr r3, [r7, #4] 800acf2: 6adb ldr r3, [r3, #44] ; 0x2c 800acf4: 60fb str r3, [r7, #12] /* Check for SDMMC interrupt flags */ if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) 800acf6: 687b ldr r3, [r7, #4] 800acf8: 681b ldr r3, [r3, #0] 800acfa: 6b5b ldr r3, [r3, #52] ; 0x34 800acfc: f403 4300 and.w r3, r3, #32768 ; 0x8000 800ad00: 2b00 cmp r3, #0 800ad02: d008 beq.n 800ad16 800ad04: 68fb ldr r3, [r7, #12] 800ad06: f003 0308 and.w r3, r3, #8 800ad0a: 2b00 cmp r3, #0 800ad0c: d003 beq.n 800ad16 { SD_Read_IT(hsd); 800ad0e: 6878 ldr r0, [r7, #4] 800ad10: f001 f926 bl 800bf60 800ad14: e19a b.n 800b04c } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) 800ad16: 687b ldr r3, [r7, #4] 800ad18: 681b ldr r3, [r3, #0] 800ad1a: 6b5b ldr r3, [r3, #52] ; 0x34 800ad1c: f403 7380 and.w r3, r3, #256 ; 0x100 800ad20: 2b00 cmp r3, #0 800ad22: f000 80ac beq.w 800ae7e { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); 800ad26: 687b ldr r3, [r7, #4] 800ad28: 681b ldr r3, [r3, #0] 800ad2a: f44f 7280 mov.w r2, #256 ; 0x100 800ad2e: 639a str r2, [r3, #56] ; 0x38 __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ 800ad30: 687b ldr r3, [r7, #4] 800ad32: 681b ldr r3, [r3, #0] 800ad34: 6bd9 ldr r1, [r3, #60] ; 0x3c 800ad36: 687b ldr r3, [r7, #4] 800ad38: 681a ldr r2, [r3, #0] 800ad3a: 4b59 ldr r3, [pc, #356] ; (800aea0 ) 800ad3c: 400b ands r3, r1 800ad3e: 63d3 str r3, [r2, #60] ; 0x3c SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \ SDMMC_IT_RXFIFOHF); __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); 800ad40: 687b ldr r3, [r7, #4] 800ad42: 681b ldr r3, [r3, #0] 800ad44: 6bda ldr r2, [r3, #60] ; 0x3c 800ad46: 687b ldr r3, [r7, #4] 800ad48: 681b ldr r3, [r3, #0] 800ad4a: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000 800ad4e: 63da str r2, [r3, #60] ; 0x3c __SDMMC_CMDTRANS_DISABLE(hsd->Instance); 800ad50: 687b ldr r3, [r7, #4] 800ad52: 681b ldr r3, [r3, #0] 800ad54: 68da ldr r2, [r3, #12] 800ad56: 687b ldr r3, [r7, #4] 800ad58: 681b ldr r3, [r3, #0] 800ad5a: f022 0240 bic.w r2, r2, #64 ; 0x40 800ad5e: 60da str r2, [r3, #12] if ((context & SD_CONTEXT_IT) != 0U) 800ad60: 68fb ldr r3, [r7, #12] 800ad62: f003 0308 and.w r3, r3, #8 800ad66: 2b00 cmp r3, #0 800ad68: d038 beq.n 800addc { if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) 800ad6a: 68fb ldr r3, [r7, #12] 800ad6c: f003 0302 and.w r3, r3, #2 800ad70: 2b00 cmp r3, #0 800ad72: d104 bne.n 800ad7e 800ad74: 68fb ldr r3, [r7, #12] 800ad76: f003 0320 and.w r3, r3, #32 800ad7a: 2b00 cmp r3, #0 800ad7c: d011 beq.n 800ada2 { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); 800ad7e: 687b ldr r3, [r7, #4] 800ad80: 681b ldr r3, [r3, #0] 800ad82: 4618 mov r0, r3 800ad84: f003 fa28 bl 800e1d8 800ad88: 60b8 str r0, [r7, #8] if (errorstate != HAL_SD_ERROR_NONE) 800ad8a: 68bb ldr r3, [r7, #8] 800ad8c: 2b00 cmp r3, #0 800ad8e: d008 beq.n 800ada2 { hsd->ErrorCode |= errorstate; 800ad90: 687b ldr r3, [r7, #4] 800ad92: 6b5a ldr r2, [r3, #52] ; 0x34 800ad94: 68bb ldr r3, [r7, #8] 800ad96: 431a orrs r2, r3 800ad98: 687b ldr r3, [r7, #4] 800ad9a: 635a str r2, [r3, #52] ; 0x34 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->ErrorCallback(hsd); #else HAL_SD_ErrorCallback(hsd); 800ad9c: 6878 ldr r0, [r7, #4] 800ad9e: f000 f95b bl 800b058 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); 800ada2: 687b ldr r3, [r7, #4] 800ada4: 681b ldr r3, [r3, #0] 800ada6: 4a3f ldr r2, [pc, #252] ; (800aea4 ) 800ada8: 639a str r2, [r3, #56] ; 0x38 hsd->State = HAL_SD_STATE_READY; 800adaa: 687b ldr r3, [r7, #4] 800adac: 2201 movs r2, #1 800adae: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800adb2: 687b ldr r3, [r7, #4] 800adb4: 2200 movs r2, #0 800adb6: 62da str r2, [r3, #44] ; 0x2c if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) 800adb8: 68fb ldr r3, [r7, #12] 800adba: f003 0301 and.w r3, r3, #1 800adbe: 2b00 cmp r3, #0 800adc0: d104 bne.n 800adcc 800adc2: 68fb ldr r3, [r7, #12] 800adc4: f003 0302 and.w r3, r3, #2 800adc8: 2b00 cmp r3, #0 800adca: d003 beq.n 800add4 { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->RxCpltCallback(hsd); #else HAL_SD_RxCpltCallback(hsd); 800adcc: 6878 ldr r0, [r7, #4] 800adce: f003 fed3 bl 800eb78 800add2: e13b b.n 800b04c else { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->TxCpltCallback(hsd); #else HAL_SD_TxCpltCallback(hsd); 800add4: 6878 ldr r0, [r7, #4] 800add6: f003 fec5 bl 800eb64 } else { /* Nothing to do */ } } 800adda: e137 b.n 800b04c else if ((context & SD_CONTEXT_DMA) != 0U) 800addc: 68fb ldr r3, [r7, #12] 800adde: f003 0380 and.w r3, r3, #128 ; 0x80 800ade2: 2b00 cmp r3, #0 800ade4: f000 8132 beq.w 800b04c hsd->Instance->DLEN = 0; 800ade8: 687b ldr r3, [r7, #4] 800adea: 681b ldr r3, [r3, #0] 800adec: 2200 movs r2, #0 800adee: 629a str r2, [r3, #40] ; 0x28 hsd->Instance->DCTRL = 0; 800adf0: 687b ldr r3, [r7, #4] 800adf2: 681b ldr r3, [r3, #0] 800adf4: 2200 movs r2, #0 800adf6: 62da str r2, [r3, #44] ; 0x2c hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; 800adf8: 687b ldr r3, [r7, #4] 800adfa: 681b ldr r3, [r3, #0] 800adfc: 2200 movs r2, #0 800adfe: 651a str r2, [r3, #80] ; 0x50 if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) 800ae00: 68fb ldr r3, [r7, #12] 800ae02: f003 0302 and.w r3, r3, #2 800ae06: 2b00 cmp r3, #0 800ae08: d104 bne.n 800ae14 800ae0a: 68fb ldr r3, [r7, #12] 800ae0c: f003 0320 and.w r3, r3, #32 800ae10: 2b00 cmp r3, #0 800ae12: d011 beq.n 800ae38 errorstate = SDMMC_CmdStopTransfer(hsd->Instance); 800ae14: 687b ldr r3, [r7, #4] 800ae16: 681b ldr r3, [r3, #0] 800ae18: 4618 mov r0, r3 800ae1a: f003 f9dd bl 800e1d8 800ae1e: 60b8 str r0, [r7, #8] if (errorstate != HAL_SD_ERROR_NONE) 800ae20: 68bb ldr r3, [r7, #8] 800ae22: 2b00 cmp r3, #0 800ae24: d008 beq.n 800ae38 hsd->ErrorCode |= errorstate; 800ae26: 687b ldr r3, [r7, #4] 800ae28: 6b5a ldr r2, [r3, #52] ; 0x34 800ae2a: 68bb ldr r3, [r7, #8] 800ae2c: 431a orrs r2, r3 800ae2e: 687b ldr r3, [r7, #4] 800ae30: 635a str r2, [r3, #52] ; 0x34 HAL_SD_ErrorCallback(hsd); 800ae32: 6878 ldr r0, [r7, #4] 800ae34: f000 f910 bl 800b058 hsd->State = HAL_SD_STATE_READY; 800ae38: 687b ldr r3, [r7, #4] 800ae3a: 2201 movs r2, #1 800ae3c: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800ae40: 687b ldr r3, [r7, #4] 800ae42: 2200 movs r2, #0 800ae44: 62da str r2, [r3, #44] ; 0x2c if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) 800ae46: 68fb ldr r3, [r7, #12] 800ae48: f003 0310 and.w r3, r3, #16 800ae4c: 2b00 cmp r3, #0 800ae4e: d104 bne.n 800ae5a 800ae50: 68fb ldr r3, [r7, #12] 800ae52: f003 0320 and.w r3, r3, #32 800ae56: 2b00 cmp r3, #0 800ae58: d002 beq.n 800ae60 HAL_SD_TxCpltCallback(hsd); 800ae5a: 6878 ldr r0, [r7, #4] 800ae5c: f003 fe82 bl 800eb64 if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) 800ae60: 68fb ldr r3, [r7, #12] 800ae62: f003 0301 and.w r3, r3, #1 800ae66: 2b00 cmp r3, #0 800ae68: d105 bne.n 800ae76 800ae6a: 68fb ldr r3, [r7, #12] 800ae6c: f003 0302 and.w r3, r3, #2 800ae70: 2b00 cmp r3, #0 800ae72: f000 80eb beq.w 800b04c HAL_SD_RxCpltCallback(hsd); 800ae76: 6878 ldr r0, [r7, #4] 800ae78: f003 fe7e bl 800eb78 } 800ae7c: e0e6 b.n 800b04c else if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) 800ae7e: 687b ldr r3, [r7, #4] 800ae80: 681b ldr r3, [r3, #0] 800ae82: 6b5b ldr r3, [r3, #52] ; 0x34 800ae84: f403 4380 and.w r3, r3, #16384 ; 0x4000 800ae88: 2b00 cmp r3, #0 800ae8a: d00d beq.n 800aea8 800ae8c: 68fb ldr r3, [r7, #12] 800ae8e: f003 0308 and.w r3, r3, #8 800ae92: 2b00 cmp r3, #0 800ae94: d008 beq.n 800aea8 SD_Write_IT(hsd); 800ae96: 6878 ldr r0, [r7, #4] 800ae98: f001 f8a8 bl 800bfec 800ae9c: e0d6 b.n 800b04c 800ae9e: bf00 nop 800aea0: ffff3ec5 .word 0xffff3ec5 800aea4: 18000f3a .word 0x18000f3a else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | 800aea8: 687b ldr r3, [r7, #4] 800aeaa: 681b ldr r3, [r3, #0] 800aeac: 6b5b ldr r3, [r3, #52] ; 0x34 800aeae: f003 033a and.w r3, r3, #58 ; 0x3a 800aeb2: 2b00 cmp r3, #0 800aeb4: f000 809d beq.w 800aff2 if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET) 800aeb8: 687b ldr r3, [r7, #4] 800aeba: 681b ldr r3, [r3, #0] 800aebc: 6b5b ldr r3, [r3, #52] ; 0x34 800aebe: f003 0302 and.w r3, r3, #2 800aec2: 2b00 cmp r3, #0 800aec4: d005 beq.n 800aed2 hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; 800aec6: 687b ldr r3, [r7, #4] 800aec8: 6b5b ldr r3, [r3, #52] ; 0x34 800aeca: f043 0202 orr.w r2, r3, #2 800aece: 687b ldr r3, [r7, #4] 800aed0: 635a str r2, [r3, #52] ; 0x34 if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET) 800aed2: 687b ldr r3, [r7, #4] 800aed4: 681b ldr r3, [r3, #0] 800aed6: 6b5b ldr r3, [r3, #52] ; 0x34 800aed8: f003 0308 and.w r3, r3, #8 800aedc: 2b00 cmp r3, #0 800aede: d005 beq.n 800aeec hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; 800aee0: 687b ldr r3, [r7, #4] 800aee2: 6b5b ldr r3, [r3, #52] ; 0x34 800aee4: f043 0208 orr.w r2, r3, #8 800aee8: 687b ldr r3, [r7, #4] 800aeea: 635a str r2, [r3, #52] ; 0x34 if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET) 800aeec: 687b ldr r3, [r7, #4] 800aeee: 681b ldr r3, [r3, #0] 800aef0: 6b5b ldr r3, [r3, #52] ; 0x34 800aef2: f003 0320 and.w r3, r3, #32 800aef6: 2b00 cmp r3, #0 800aef8: d005 beq.n 800af06 hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; 800aefa: 687b ldr r3, [r7, #4] 800aefc: 6b5b ldr r3, [r3, #52] ; 0x34 800aefe: f043 0220 orr.w r2, r3, #32 800af02: 687b ldr r3, [r7, #4] 800af04: 635a str r2, [r3, #52] ; 0x34 if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET) 800af06: 687b ldr r3, [r7, #4] 800af08: 681b ldr r3, [r3, #0] 800af0a: 6b5b ldr r3, [r3, #52] ; 0x34 800af0c: f003 0310 and.w r3, r3, #16 800af10: 2b00 cmp r3, #0 800af12: d005 beq.n 800af20 hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; 800af14: 687b ldr r3, [r7, #4] 800af16: 6b5b ldr r3, [r3, #52] ; 0x34 800af18: f043 0210 orr.w r2, r3, #16 800af1c: 687b ldr r3, [r7, #4] 800af1e: 635a str r2, [r3, #52] ; 0x34 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); 800af20: 687b ldr r3, [r7, #4] 800af22: 681b ldr r3, [r3, #0] 800af24: 4a4b ldr r2, [pc, #300] ; (800b054 ) 800af26: 639a str r2, [r3, #56] ; 0x38 __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ 800af28: 687b ldr r3, [r7, #4] 800af2a: 681b ldr r3, [r3, #0] 800af2c: 6bda ldr r2, [r3, #60] ; 0x3c 800af2e: 687b ldr r3, [r7, #4] 800af30: 681b ldr r3, [r3, #0] 800af32: f422 729d bic.w r2, r2, #314 ; 0x13a 800af36: 63da str r2, [r3, #60] ; 0x3c __SDMMC_CMDTRANS_DISABLE(hsd->Instance); 800af38: 687b ldr r3, [r7, #4] 800af3a: 681b ldr r3, [r3, #0] 800af3c: 68da ldr r2, [r3, #12] 800af3e: 687b ldr r3, [r7, #4] 800af40: 681b ldr r3, [r3, #0] 800af42: f022 0240 bic.w r2, r2, #64 ; 0x40 800af46: 60da str r2, [r3, #12] hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; 800af48: 687b ldr r3, [r7, #4] 800af4a: 681b ldr r3, [r3, #0] 800af4c: 6ada ldr r2, [r3, #44] ; 0x2c 800af4e: 687b ldr r3, [r7, #4] 800af50: 681b ldr r3, [r3, #0] 800af52: f442 5200 orr.w r2, r2, #8192 ; 0x2000 800af56: 62da str r2, [r3, #44] ; 0x2c hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP; 800af58: 687b ldr r3, [r7, #4] 800af5a: 681b ldr r3, [r3, #0] 800af5c: 68da ldr r2, [r3, #12] 800af5e: 687b ldr r3, [r7, #4] 800af60: 681b ldr r3, [r3, #0] 800af62: f042 0280 orr.w r2, r2, #128 ; 0x80 800af66: 60da str r2, [r3, #12] hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); 800af68: 687b ldr r3, [r7, #4] 800af6a: 681b ldr r3, [r3, #0] 800af6c: 4618 mov r0, r3 800af6e: f003 f933 bl 800e1d8 800af72: 4602 mov r2, r0 800af74: 687b ldr r3, [r7, #4] 800af76: 6b5b ldr r3, [r3, #52] ; 0x34 800af78: 431a orrs r2, r3 800af7a: 687b ldr r3, [r7, #4] 800af7c: 635a str r2, [r3, #52] ; 0x34 hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP); 800af7e: 687b ldr r3, [r7, #4] 800af80: 681b ldr r3, [r3, #0] 800af82: 68da ldr r2, [r3, #12] 800af84: 687b ldr r3, [r7, #4] 800af86: 681b ldr r3, [r3, #0] 800af88: f022 0280 bic.w r2, r2, #128 ; 0x80 800af8c: 60da str r2, [r3, #12] __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT); 800af8e: 687b ldr r3, [r7, #4] 800af90: 681b ldr r3, [r3, #0] 800af92: f44f 6200 mov.w r2, #2048 ; 0x800 800af96: 639a str r2, [r3, #56] ; 0x38 if ((context & SD_CONTEXT_IT) != 0U) 800af98: 68fb ldr r3, [r7, #12] 800af9a: f003 0308 and.w r3, r3, #8 800af9e: 2b00 cmp r3, #0 800afa0: d00a beq.n 800afb8 hsd->State = HAL_SD_STATE_READY; 800afa2: 687b ldr r3, [r7, #4] 800afa4: 2201 movs r2, #1 800afa6: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800afaa: 687b ldr r3, [r7, #4] 800afac: 2200 movs r2, #0 800afae: 62da str r2, [r3, #44] ; 0x2c HAL_SD_ErrorCallback(hsd); 800afb0: 6878 ldr r0, [r7, #4] 800afb2: f000 f851 bl 800b058 } 800afb6: e049 b.n 800b04c else if ((context & SD_CONTEXT_DMA) != 0U) 800afb8: 68fb ldr r3, [r7, #12] 800afba: f003 0380 and.w r3, r3, #128 ; 0x80 800afbe: 2b00 cmp r3, #0 800afc0: d044 beq.n 800b04c if (hsd->ErrorCode != HAL_SD_ERROR_NONE) 800afc2: 687b ldr r3, [r7, #4] 800afc4: 6b5b ldr r3, [r3, #52] ; 0x34 800afc6: 2b00 cmp r3, #0 800afc8: d040 beq.n 800b04c __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); 800afca: 687b ldr r3, [r7, #4] 800afcc: 681b ldr r3, [r3, #0] 800afce: 6bda ldr r2, [r3, #60] ; 0x3c 800afd0: 687b ldr r3, [r7, #4] 800afd2: 681b ldr r3, [r3, #0] 800afd4: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000 800afd8: 63da str r2, [r3, #60] ; 0x3c hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; 800afda: 687b ldr r3, [r7, #4] 800afdc: 681b ldr r3, [r3, #0] 800afde: 2200 movs r2, #0 800afe0: 651a str r2, [r3, #80] ; 0x50 hsd->State = HAL_SD_STATE_READY; 800afe2: 687b ldr r3, [r7, #4] 800afe4: 2201 movs r2, #1 800afe6: f883 2030 strb.w r2, [r3, #48] ; 0x30 HAL_SD_ErrorCallback(hsd); 800afea: 6878 ldr r0, [r7, #4] 800afec: f000 f834 bl 800b058 } 800aff0: e02c b.n 800b04c else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET) 800aff2: 687b ldr r3, [r7, #4] 800aff4: 681b ldr r3, [r3, #0] 800aff6: 6b5b ldr r3, [r3, #52] ; 0x34 800aff8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800affc: 2b00 cmp r3, #0 800affe: d025 beq.n 800b04c __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); 800b000: 687b ldr r3, [r7, #4] 800b002: 681b ldr r3, [r3, #0] 800b004: f04f 5280 mov.w r2, #268435456 ; 0x10000000 800b008: 639a str r2, [r3, #56] ; 0x38 if (READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) 800b00a: 687b ldr r3, [r7, #4] 800b00c: 681b ldr r3, [r3, #0] 800b00e: 6d1b ldr r3, [r3, #80] ; 0x50 800b010: f003 0304 and.w r3, r3, #4 800b014: 2b00 cmp r3, #0 800b016: d10c bne.n 800b032 if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) 800b018: 68fb ldr r3, [r7, #12] 800b01a: f003 0320 and.w r3, r3, #32 800b01e: 2b00 cmp r3, #0 800b020: d003 beq.n 800b02a HAL_SDEx_Write_DMADoubleBuf1CpltCallback(hsd); 800b022: 6878 ldr r0, [r7, #4] 800b024: f001 f84a bl 800c0bc } 800b028: e010 b.n 800b04c HAL_SDEx_Read_DMADoubleBuf1CpltCallback(hsd); 800b02a: 6878 ldr r0, [r7, #4] 800b02c: f001 f832 bl 800c094 } 800b030: e00c b.n 800b04c if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) 800b032: 68fb ldr r3, [r7, #12] 800b034: f003 0320 and.w r3, r3, #32 800b038: 2b00 cmp r3, #0 800b03a: d003 beq.n 800b044 HAL_SDEx_Write_DMADoubleBuf0CpltCallback(hsd); 800b03c: 6878 ldr r0, [r7, #4] 800b03e: f001 f833 bl 800c0a8 } 800b042: e003 b.n 800b04c HAL_SDEx_Read_DMADoubleBuf0CpltCallback(hsd); 800b044: 6878 ldr r0, [r7, #4] 800b046: f001 f81b bl 800c080 } 800b04a: e7ff b.n 800b04c 800b04c: bf00 nop 800b04e: 3710 adds r7, #16 800b050: 46bd mov sp, r7 800b052: bd80 pop {r7, pc} 800b054: 18000f3a .word 0x18000f3a 0800b058 : * @brief SD error callbacks * @param hsd: Pointer SD handle * @retval None */ __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) { 800b058: b480 push {r7} 800b05a: b083 sub sp, #12 800b05c: af00 add r7, sp, #0 800b05e: 6078 str r0, [r7, #4] UNUSED(hsd); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SD_ErrorCallback can be implemented in the user file */ } 800b060: bf00 nop 800b062: 370c adds r7, #12 800b064: 46bd mov sp, r7 800b066: f85d 7b04 ldr.w r7, [sp], #4 800b06a: 4770 bx lr 0800b06c : * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that * contains all CSD register parameters * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) { 800b06c: b480 push {r7} 800b06e: b083 sub sp, #12 800b070: af00 add r7, sp, #0 800b072: 6078 str r0, [r7, #4] 800b074: 6039 str r1, [r7, #0] pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); 800b076: 687b ldr r3, [r7, #4] 800b078: 6ddb ldr r3, [r3, #92] ; 0x5c 800b07a: 0f9b lsrs r3, r3, #30 800b07c: b2da uxtb r2, r3 800b07e: 683b ldr r3, [r7, #0] 800b080: 701a strb r2, [r3, #0] pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); 800b082: 687b ldr r3, [r7, #4] 800b084: 6ddb ldr r3, [r3, #92] ; 0x5c 800b086: 0e9b lsrs r3, r3, #26 800b088: b2db uxtb r3, r3 800b08a: f003 030f and.w r3, r3, #15 800b08e: b2da uxtb r2, r3 800b090: 683b ldr r3, [r7, #0] 800b092: 705a strb r2, [r3, #1] pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); 800b094: 687b ldr r3, [r7, #4] 800b096: 6ddb ldr r3, [r3, #92] ; 0x5c 800b098: 0e1b lsrs r3, r3, #24 800b09a: b2db uxtb r3, r3 800b09c: f003 0303 and.w r3, r3, #3 800b0a0: b2da uxtb r2, r3 800b0a2: 683b ldr r3, [r7, #0] 800b0a4: 709a strb r2, [r3, #2] pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); 800b0a6: 687b ldr r3, [r7, #4] 800b0a8: 6ddb ldr r3, [r3, #92] ; 0x5c 800b0aa: 0c1b lsrs r3, r3, #16 800b0ac: b2da uxtb r2, r3 800b0ae: 683b ldr r3, [r7, #0] 800b0b0: 70da strb r2, [r3, #3] pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); 800b0b2: 687b ldr r3, [r7, #4] 800b0b4: 6ddb ldr r3, [r3, #92] ; 0x5c 800b0b6: 0a1b lsrs r3, r3, #8 800b0b8: b2da uxtb r2, r3 800b0ba: 683b ldr r3, [r7, #0] 800b0bc: 711a strb r2, [r3, #4] pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); 800b0be: 687b ldr r3, [r7, #4] 800b0c0: 6ddb ldr r3, [r3, #92] ; 0x5c 800b0c2: b2da uxtb r2, r3 800b0c4: 683b ldr r3, [r7, #0] 800b0c6: 715a strb r2, [r3, #5] pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); 800b0c8: 687b ldr r3, [r7, #4] 800b0ca: 6e1b ldr r3, [r3, #96] ; 0x60 800b0cc: 0d1b lsrs r3, r3, #20 800b0ce: b29a uxth r2, r3 800b0d0: 683b ldr r3, [r7, #0] 800b0d2: 80da strh r2, [r3, #6] pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); 800b0d4: 687b ldr r3, [r7, #4] 800b0d6: 6e1b ldr r3, [r3, #96] ; 0x60 800b0d8: 0c1b lsrs r3, r3, #16 800b0da: b2db uxtb r3, r3 800b0dc: f003 030f and.w r3, r3, #15 800b0e0: b2da uxtb r2, r3 800b0e2: 683b ldr r3, [r7, #0] 800b0e4: 721a strb r2, [r3, #8] pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); 800b0e6: 687b ldr r3, [r7, #4] 800b0e8: 6e1b ldr r3, [r3, #96] ; 0x60 800b0ea: 0bdb lsrs r3, r3, #15 800b0ec: b2db uxtb r3, r3 800b0ee: f003 0301 and.w r3, r3, #1 800b0f2: b2da uxtb r2, r3 800b0f4: 683b ldr r3, [r7, #0] 800b0f6: 725a strb r2, [r3, #9] pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); 800b0f8: 687b ldr r3, [r7, #4] 800b0fa: 6e1b ldr r3, [r3, #96] ; 0x60 800b0fc: 0b9b lsrs r3, r3, #14 800b0fe: b2db uxtb r3, r3 800b100: f003 0301 and.w r3, r3, #1 800b104: b2da uxtb r2, r3 800b106: 683b ldr r3, [r7, #0] 800b108: 729a strb r2, [r3, #10] pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); 800b10a: 687b ldr r3, [r7, #4] 800b10c: 6e1b ldr r3, [r3, #96] ; 0x60 800b10e: 0b5b lsrs r3, r3, #13 800b110: b2db uxtb r3, r3 800b112: f003 0301 and.w r3, r3, #1 800b116: b2da uxtb r2, r3 800b118: 683b ldr r3, [r7, #0] 800b11a: 72da strb r2, [r3, #11] pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); 800b11c: 687b ldr r3, [r7, #4] 800b11e: 6e1b ldr r3, [r3, #96] ; 0x60 800b120: 0b1b lsrs r3, r3, #12 800b122: b2db uxtb r3, r3 800b124: f003 0301 and.w r3, r3, #1 800b128: b2da uxtb r2, r3 800b12a: 683b ldr r3, [r7, #0] 800b12c: 731a strb r2, [r3, #12] pCSD->Reserved2 = 0U; /*!< Reserved */ 800b12e: 683b ldr r3, [r7, #0] 800b130: 2200 movs r2, #0 800b132: 735a strb r2, [r3, #13] if (hsd->SdCard.CardType == CARD_SDSC) 800b134: 687b ldr r3, [r7, #4] 800b136: 6b9b ldr r3, [r3, #56] ; 0x38 800b138: 2b00 cmp r3, #0 800b13a: d163 bne.n 800b204 { pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); 800b13c: 687b ldr r3, [r7, #4] 800b13e: 6e1b ldr r3, [r3, #96] ; 0x60 800b140: 009a lsls r2, r3, #2 800b142: f640 73fc movw r3, #4092 ; 0xffc 800b146: 4013 ands r3, r2 800b148: 687a ldr r2, [r7, #4] 800b14a: 6e52 ldr r2, [r2, #100] ; 0x64 800b14c: 0f92 lsrs r2, r2, #30 800b14e: 431a orrs r2, r3 800b150: 683b ldr r3, [r7, #0] 800b152: 611a str r2, [r3, #16] pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); 800b154: 687b ldr r3, [r7, #4] 800b156: 6e5b ldr r3, [r3, #100] ; 0x64 800b158: 0edb lsrs r3, r3, #27 800b15a: b2db uxtb r3, r3 800b15c: f003 0307 and.w r3, r3, #7 800b160: b2da uxtb r2, r3 800b162: 683b ldr r3, [r7, #0] 800b164: 751a strb r2, [r3, #20] pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); 800b166: 687b ldr r3, [r7, #4] 800b168: 6e5b ldr r3, [r3, #100] ; 0x64 800b16a: 0e1b lsrs r3, r3, #24 800b16c: b2db uxtb r3, r3 800b16e: f003 0307 and.w r3, r3, #7 800b172: b2da uxtb r2, r3 800b174: 683b ldr r3, [r7, #0] 800b176: 755a strb r2, [r3, #21] pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); 800b178: 687b ldr r3, [r7, #4] 800b17a: 6e5b ldr r3, [r3, #100] ; 0x64 800b17c: 0d5b lsrs r3, r3, #21 800b17e: b2db uxtb r3, r3 800b180: f003 0307 and.w r3, r3, #7 800b184: b2da uxtb r2, r3 800b186: 683b ldr r3, [r7, #0] 800b188: 759a strb r2, [r3, #22] pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); 800b18a: 687b ldr r3, [r7, #4] 800b18c: 6e5b ldr r3, [r3, #100] ; 0x64 800b18e: 0c9b lsrs r3, r3, #18 800b190: b2db uxtb r3, r3 800b192: f003 0307 and.w r3, r3, #7 800b196: b2da uxtb r2, r3 800b198: 683b ldr r3, [r7, #0] 800b19a: 75da strb r2, [r3, #23] pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); 800b19c: 687b ldr r3, [r7, #4] 800b19e: 6e5b ldr r3, [r3, #100] ; 0x64 800b1a0: 0bdb lsrs r3, r3, #15 800b1a2: b2db uxtb r3, r3 800b1a4: f003 0307 and.w r3, r3, #7 800b1a8: b2da uxtb r2, r3 800b1aa: 683b ldr r3, [r7, #0] 800b1ac: 761a strb r2, [r3, #24] hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; 800b1ae: 683b ldr r3, [r7, #0] 800b1b0: 691b ldr r3, [r3, #16] 800b1b2: 1c5a adds r2, r3, #1 800b1b4: 687b ldr r3, [r7, #4] 800b1b6: 649a str r2, [r3, #72] ; 0x48 hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); 800b1b8: 683b ldr r3, [r7, #0] 800b1ba: 7e1b ldrb r3, [r3, #24] 800b1bc: b2db uxtb r3, r3 800b1be: f003 0307 and.w r3, r3, #7 800b1c2: 3302 adds r3, #2 800b1c4: 2201 movs r2, #1 800b1c6: fa02 f303 lsl.w r3, r2, r3 800b1ca: 687a ldr r2, [r7, #4] 800b1cc: 6c92 ldr r2, [r2, #72] ; 0x48 800b1ce: fb03 f202 mul.w r2, r3, r2 800b1d2: 687b ldr r3, [r7, #4] 800b1d4: 649a str r2, [r3, #72] ; 0x48 hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); 800b1d6: 683b ldr r3, [r7, #0] 800b1d8: 7a1b ldrb r3, [r3, #8] 800b1da: b2db uxtb r3, r3 800b1dc: f003 030f and.w r3, r3, #15 800b1e0: 2201 movs r2, #1 800b1e2: 409a lsls r2, r3 800b1e4: 687b ldr r3, [r7, #4] 800b1e6: 64da str r2, [r3, #76] ; 0x4c hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); 800b1e8: 687b ldr r3, [r7, #4] 800b1ea: 6c9b ldr r3, [r3, #72] ; 0x48 800b1ec: 687a ldr r2, [r7, #4] 800b1ee: 6cd2 ldr r2, [r2, #76] ; 0x4c 800b1f0: 0a52 lsrs r2, r2, #9 800b1f2: fb03 f202 mul.w r2, r3, r2 800b1f6: 687b ldr r3, [r7, #4] 800b1f8: 651a str r2, [r3, #80] ; 0x50 hsd->SdCard.LogBlockSize = 512U; 800b1fa: 687b ldr r3, [r7, #4] 800b1fc: f44f 7200 mov.w r2, #512 ; 0x200 800b200: 655a str r2, [r3, #84] ; 0x54 800b202: e031 b.n 800b268 } else if (hsd->SdCard.CardType == CARD_SDHC_SDXC) 800b204: 687b ldr r3, [r7, #4] 800b206: 6b9b ldr r3, [r3, #56] ; 0x38 800b208: 2b01 cmp r3, #1 800b20a: d11d bne.n 800b248 { /* Byte 7 */ pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); 800b20c: 687b ldr r3, [r7, #4] 800b20e: 6e1b ldr r3, [r3, #96] ; 0x60 800b210: 041b lsls r3, r3, #16 800b212: f403 127c and.w r2, r3, #4128768 ; 0x3f0000 800b216: 687b ldr r3, [r7, #4] 800b218: 6e5b ldr r3, [r3, #100] ; 0x64 800b21a: 0c1b lsrs r3, r3, #16 800b21c: 431a orrs r2, r3 800b21e: 683b ldr r3, [r7, #0] 800b220: 611a str r2, [r3, #16] hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); 800b222: 683b ldr r3, [r7, #0] 800b224: 691b ldr r3, [r3, #16] 800b226: 3301 adds r3, #1 800b228: 029a lsls r2, r3, #10 800b22a: 687b ldr r3, [r7, #4] 800b22c: 649a str r2, [r3, #72] ; 0x48 hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; 800b22e: 687b ldr r3, [r7, #4] 800b230: 6c9a ldr r2, [r3, #72] ; 0x48 800b232: 687b ldr r3, [r7, #4] 800b234: 651a str r2, [r3, #80] ; 0x50 hsd->SdCard.BlockSize = 512U; 800b236: 687b ldr r3, [r7, #4] 800b238: f44f 7200 mov.w r2, #512 ; 0x200 800b23c: 64da str r2, [r3, #76] ; 0x4c hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; 800b23e: 687b ldr r3, [r7, #4] 800b240: 6cda ldr r2, [r3, #76] ; 0x4c 800b242: 687b ldr r3, [r7, #4] 800b244: 655a str r2, [r3, #84] ; 0x54 800b246: e00f b.n 800b268 } else { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800b248: 687b ldr r3, [r7, #4] 800b24a: 681b ldr r3, [r3, #0] 800b24c: 4a58 ldr r2, [pc, #352] ; (800b3b0 ) 800b24e: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800b250: 687b ldr r3, [r7, #4] 800b252: 6b5b ldr r3, [r3, #52] ; 0x34 800b254: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 800b258: 687b ldr r3, [r7, #4] 800b25a: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800b25c: 687b ldr r3, [r7, #4] 800b25e: 2201 movs r2, #1 800b260: f883 2030 strb.w r2, [r3, #48] ; 0x30 return HAL_ERROR; 800b264: 2301 movs r3, #1 800b266: e09d b.n 800b3a4 } pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); 800b268: 687b ldr r3, [r7, #4] 800b26a: 6e5b ldr r3, [r3, #100] ; 0x64 800b26c: 0b9b lsrs r3, r3, #14 800b26e: b2db uxtb r3, r3 800b270: f003 0301 and.w r3, r3, #1 800b274: b2da uxtb r2, r3 800b276: 683b ldr r3, [r7, #0] 800b278: 765a strb r2, [r3, #25] pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); 800b27a: 687b ldr r3, [r7, #4] 800b27c: 6e5b ldr r3, [r3, #100] ; 0x64 800b27e: 09db lsrs r3, r3, #7 800b280: b2db uxtb r3, r3 800b282: f003 037f and.w r3, r3, #127 ; 0x7f 800b286: b2da uxtb r2, r3 800b288: 683b ldr r3, [r7, #0] 800b28a: 769a strb r2, [r3, #26] pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); 800b28c: 687b ldr r3, [r7, #4] 800b28e: 6e5b ldr r3, [r3, #100] ; 0x64 800b290: b2db uxtb r3, r3 800b292: f003 037f and.w r3, r3, #127 ; 0x7f 800b296: b2da uxtb r2, r3 800b298: 683b ldr r3, [r7, #0] 800b29a: 76da strb r2, [r3, #27] pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); 800b29c: 687b ldr r3, [r7, #4] 800b29e: 6e9b ldr r3, [r3, #104] ; 0x68 800b2a0: 0fdb lsrs r3, r3, #31 800b2a2: b2da uxtb r2, r3 800b2a4: 683b ldr r3, [r7, #0] 800b2a6: 771a strb r2, [r3, #28] pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); 800b2a8: 687b ldr r3, [r7, #4] 800b2aa: 6e9b ldr r3, [r3, #104] ; 0x68 800b2ac: 0f5b lsrs r3, r3, #29 800b2ae: b2db uxtb r3, r3 800b2b0: f003 0303 and.w r3, r3, #3 800b2b4: b2da uxtb r2, r3 800b2b6: 683b ldr r3, [r7, #0] 800b2b8: 775a strb r2, [r3, #29] pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); 800b2ba: 687b ldr r3, [r7, #4] 800b2bc: 6e9b ldr r3, [r3, #104] ; 0x68 800b2be: 0e9b lsrs r3, r3, #26 800b2c0: b2db uxtb r3, r3 800b2c2: f003 0307 and.w r3, r3, #7 800b2c6: b2da uxtb r2, r3 800b2c8: 683b ldr r3, [r7, #0] 800b2ca: 779a strb r2, [r3, #30] pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); 800b2cc: 687b ldr r3, [r7, #4] 800b2ce: 6e9b ldr r3, [r3, #104] ; 0x68 800b2d0: 0d9b lsrs r3, r3, #22 800b2d2: b2db uxtb r3, r3 800b2d4: f003 030f and.w r3, r3, #15 800b2d8: b2da uxtb r2, r3 800b2da: 683b ldr r3, [r7, #0] 800b2dc: 77da strb r2, [r3, #31] pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); 800b2de: 687b ldr r3, [r7, #4] 800b2e0: 6e9b ldr r3, [r3, #104] ; 0x68 800b2e2: 0d5b lsrs r3, r3, #21 800b2e4: b2db uxtb r3, r3 800b2e6: f003 0301 and.w r3, r3, #1 800b2ea: b2da uxtb r2, r3 800b2ec: 683b ldr r3, [r7, #0] 800b2ee: f883 2020 strb.w r2, [r3, #32] pCSD->Reserved3 = 0; 800b2f2: 683b ldr r3, [r7, #0] 800b2f4: 2200 movs r2, #0 800b2f6: f883 2021 strb.w r2, [r3, #33] ; 0x21 pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); 800b2fa: 687b ldr r3, [r7, #4] 800b2fc: 6e9b ldr r3, [r3, #104] ; 0x68 800b2fe: 0c1b lsrs r3, r3, #16 800b300: b2db uxtb r3, r3 800b302: f003 0301 and.w r3, r3, #1 800b306: b2da uxtb r2, r3 800b308: 683b ldr r3, [r7, #0] 800b30a: f883 2022 strb.w r2, [r3, #34] ; 0x22 pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); 800b30e: 687b ldr r3, [r7, #4] 800b310: 6e9b ldr r3, [r3, #104] ; 0x68 800b312: 0bdb lsrs r3, r3, #15 800b314: b2db uxtb r3, r3 800b316: f003 0301 and.w r3, r3, #1 800b31a: b2da uxtb r2, r3 800b31c: 683b ldr r3, [r7, #0] 800b31e: f883 2023 strb.w r2, [r3, #35] ; 0x23 pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); 800b322: 687b ldr r3, [r7, #4] 800b324: 6e9b ldr r3, [r3, #104] ; 0x68 800b326: 0b9b lsrs r3, r3, #14 800b328: b2db uxtb r3, r3 800b32a: f003 0301 and.w r3, r3, #1 800b32e: b2da uxtb r2, r3 800b330: 683b ldr r3, [r7, #0] 800b332: f883 2024 strb.w r2, [r3, #36] ; 0x24 pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); 800b336: 687b ldr r3, [r7, #4] 800b338: 6e9b ldr r3, [r3, #104] ; 0x68 800b33a: 0b5b lsrs r3, r3, #13 800b33c: b2db uxtb r3, r3 800b33e: f003 0301 and.w r3, r3, #1 800b342: b2da uxtb r2, r3 800b344: 683b ldr r3, [r7, #0] 800b346: f883 2025 strb.w r2, [r3, #37] ; 0x25 pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); 800b34a: 687b ldr r3, [r7, #4] 800b34c: 6e9b ldr r3, [r3, #104] ; 0x68 800b34e: 0b1b lsrs r3, r3, #12 800b350: b2db uxtb r3, r3 800b352: f003 0301 and.w r3, r3, #1 800b356: b2da uxtb r2, r3 800b358: 683b ldr r3, [r7, #0] 800b35a: f883 2026 strb.w r2, [r3, #38] ; 0x26 pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); 800b35e: 687b ldr r3, [r7, #4] 800b360: 6e9b ldr r3, [r3, #104] ; 0x68 800b362: 0a9b lsrs r3, r3, #10 800b364: b2db uxtb r3, r3 800b366: f003 0303 and.w r3, r3, #3 800b36a: b2da uxtb r2, r3 800b36c: 683b ldr r3, [r7, #0] 800b36e: f883 2027 strb.w r2, [r3, #39] ; 0x27 pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); 800b372: 687b ldr r3, [r7, #4] 800b374: 6e9b ldr r3, [r3, #104] ; 0x68 800b376: 0a1b lsrs r3, r3, #8 800b378: b2db uxtb r3, r3 800b37a: f003 0303 and.w r3, r3, #3 800b37e: b2da uxtb r2, r3 800b380: 683b ldr r3, [r7, #0] 800b382: f883 2028 strb.w r2, [r3, #40] ; 0x28 pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); 800b386: 687b ldr r3, [r7, #4] 800b388: 6e9b ldr r3, [r3, #104] ; 0x68 800b38a: 085b lsrs r3, r3, #1 800b38c: b2db uxtb r3, r3 800b38e: f003 037f and.w r3, r3, #127 ; 0x7f 800b392: b2da uxtb r2, r3 800b394: 683b ldr r3, [r7, #0] 800b396: f883 2029 strb.w r2, [r3, #41] ; 0x29 pCSD->Reserved4 = 1; 800b39a: 683b ldr r3, [r7, #0] 800b39c: 2201 movs r2, #1 800b39e: f883 202a strb.w r2, [r3, #42] ; 0x2a return HAL_OK; 800b3a2: 2300 movs r3, #0 } 800b3a4: 4618 mov r0, r3 800b3a6: 370c adds r7, #12 800b3a8: 46bd mov sp, r7 800b3aa: f85d 7b04 ldr.w r7, [sp], #4 800b3ae: 4770 bx lr 800b3b0: 1fe00fff .word 0x1fe00fff 0800b3b4 : * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that * will contain the SD card status information * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) { 800b3b4: b580 push {r7, lr} 800b3b6: b094 sub sp, #80 ; 0x50 800b3b8: af00 add r7, sp, #0 800b3ba: 6078 str r0, [r7, #4] 800b3bc: 6039 str r1, [r7, #0] uint32_t sd_status[16]; uint32_t errorstate; HAL_StatusTypeDef status = HAL_OK; 800b3be: 2300 movs r3, #0 800b3c0: f887 304f strb.w r3, [r7, #79] ; 0x4f if (hsd->State == HAL_SD_STATE_BUSY) 800b3c4: 687b ldr r3, [r7, #4] 800b3c6: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 800b3ca: b2db uxtb r3, r3 800b3cc: 2b03 cmp r3, #3 800b3ce: d101 bne.n 800b3d4 { return HAL_ERROR; 800b3d0: 2301 movs r3, #1 800b3d2: e0a7 b.n 800b524 } errorstate = SD_SendSDStatus(hsd, sd_status); 800b3d4: f107 0308 add.w r3, r7, #8 800b3d8: 4619 mov r1, r3 800b3da: 6878 ldr r0, [r7, #4] 800b3dc: f000 fb62 bl 800baa4 800b3e0: 64b8 str r0, [r7, #72] ; 0x48 if (errorstate != HAL_SD_ERROR_NONE) 800b3e2: 6cbb ldr r3, [r7, #72] ; 0x48 800b3e4: 2b00 cmp r3, #0 800b3e6: d011 beq.n 800b40c { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800b3e8: 687b ldr r3, [r7, #4] 800b3ea: 681b ldr r3, [r3, #0] 800b3ec: 4a4f ldr r2, [pc, #316] ; (800b52c ) 800b3ee: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 800b3f0: 687b ldr r3, [r7, #4] 800b3f2: 6b5a ldr r2, [r3, #52] ; 0x34 800b3f4: 6cbb ldr r3, [r7, #72] ; 0x48 800b3f6: 431a orrs r2, r3 800b3f8: 687b ldr r3, [r7, #4] 800b3fa: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800b3fc: 687b ldr r3, [r7, #4] 800b3fe: 2201 movs r2, #1 800b400: f883 2030 strb.w r2, [r3, #48] ; 0x30 status = HAL_ERROR; 800b404: 2301 movs r3, #1 800b406: f887 304f strb.w r3, [r7, #79] ; 0x4f 800b40a: e070 b.n 800b4ee } else { pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U); 800b40c: 68bb ldr r3, [r7, #8] 800b40e: 099b lsrs r3, r3, #6 800b410: b2db uxtb r3, r3 800b412: f003 0303 and.w r3, r3, #3 800b416: b2da uxtb r2, r3 800b418: 683b ldr r3, [r7, #0] 800b41a: 701a strb r2, [r3, #0] pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U); 800b41c: 68bb ldr r3, [r7, #8] 800b41e: 095b lsrs r3, r3, #5 800b420: b2db uxtb r3, r3 800b422: f003 0301 and.w r3, r3, #1 800b426: b2da uxtb r2, r3 800b428: 683b ldr r3, [r7, #0] 800b42a: 705a strb r2, [r3, #1] pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U)); 800b42c: 68bb ldr r3, [r7, #8] 800b42e: 0a1b lsrs r3, r3, #8 800b430: b29b uxth r3, r3 800b432: f023 03ff bic.w r3, r3, #255 ; 0xff 800b436: b29a uxth r2, r3 800b438: 68bb ldr r3, [r7, #8] 800b43a: 0e1b lsrs r3, r3, #24 800b43c: b29b uxth r3, r3 800b43e: 4313 orrs r3, r2 800b440: b29a uxth r2, r3 800b442: 683b ldr r3, [r7, #0] 800b444: 805a strh r2, [r3, #2] pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | 800b446: 68fb ldr r3, [r7, #12] 800b448: 061a lsls r2, r3, #24 800b44a: 68fb ldr r3, [r7, #12] 800b44c: 021b lsls r3, r3, #8 800b44e: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800b452: 431a orrs r2, r3 ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); 800b454: 68fb ldr r3, [r7, #12] 800b456: 0a1b lsrs r3, r3, #8 800b458: f403 437f and.w r3, r3, #65280 ; 0xff00 pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | 800b45c: 431a orrs r2, r3 ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); 800b45e: 68fb ldr r3, [r7, #12] 800b460: 0e1b lsrs r3, r3, #24 800b462: 431a orrs r2, r3 pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | 800b464: 683b ldr r3, [r7, #0] 800b466: 605a str r2, [r3, #4] pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU); 800b468: 693b ldr r3, [r7, #16] 800b46a: b2da uxtb r2, r3 800b46c: 683b ldr r3, [r7, #0] 800b46e: 721a strb r2, [r3, #8] pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U); 800b470: 693b ldr r3, [r7, #16] 800b472: 0a1b lsrs r3, r3, #8 800b474: b2da uxtb r2, r3 800b476: 683b ldr r3, [r7, #0] 800b478: 725a strb r2, [r3, #9] pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U); 800b47a: 693b ldr r3, [r7, #16] 800b47c: 0d1b lsrs r3, r3, #20 800b47e: b2db uxtb r3, r3 800b480: f003 030f and.w r3, r3, #15 800b484: b2da uxtb r2, r3 800b486: 683b ldr r3, [r7, #0] 800b488: 729a strb r2, [r3, #10] pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU)); 800b48a: 693b ldr r3, [r7, #16] 800b48c: 0c1b lsrs r3, r3, #16 800b48e: b29b uxth r3, r3 800b490: f023 03ff bic.w r3, r3, #255 ; 0xff 800b494: b29a uxth r2, r3 800b496: 697b ldr r3, [r7, #20] 800b498: b29b uxth r3, r3 800b49a: b2db uxtb r3, r3 800b49c: b29b uxth r3, r3 800b49e: 4313 orrs r3, r2 800b4a0: b29a uxth r2, r3 800b4a2: 683b ldr r3, [r7, #0] 800b4a4: 819a strh r2, [r3, #12] pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U); 800b4a6: 697b ldr r3, [r7, #20] 800b4a8: 0a9b lsrs r3, r3, #10 800b4aa: b2db uxtb r3, r3 800b4ac: f003 033f and.w r3, r3, #63 ; 0x3f 800b4b0: b2da uxtb r2, r3 800b4b2: 683b ldr r3, [r7, #0] 800b4b4: 739a strb r2, [r3, #14] pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); 800b4b6: 697b ldr r3, [r7, #20] 800b4b8: 0a1b lsrs r3, r3, #8 800b4ba: b2db uxtb r3, r3 800b4bc: f003 0303 and.w r3, r3, #3 800b4c0: b2da uxtb r2, r3 800b4c2: 683b ldr r3, [r7, #0] 800b4c4: 73da strb r2, [r3, #15] pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U); 800b4c6: 697b ldr r3, [r7, #20] 800b4c8: 091b lsrs r3, r3, #4 800b4ca: b2db uxtb r3, r3 800b4cc: f003 030f and.w r3, r3, #15 800b4d0: b2da uxtb r2, r3 800b4d2: 683b ldr r3, [r7, #0] 800b4d4: 741a strb r2, [r3, #16] pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ; 800b4d6: 697b ldr r3, [r7, #20] 800b4d8: b2db uxtb r3, r3 800b4da: f003 030f and.w r3, r3, #15 800b4de: b2da uxtb r2, r3 800b4e0: 683b ldr r3, [r7, #0] 800b4e2: 745a strb r2, [r3, #17] pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U); 800b4e4: 69bb ldr r3, [r7, #24] 800b4e6: 0e1b lsrs r3, r3, #24 800b4e8: b2da uxtb r2, r3 800b4ea: 683b ldr r3, [r7, #0] 800b4ec: 749a strb r2, [r3, #18] } /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); 800b4ee: 687b ldr r3, [r7, #4] 800b4f0: 681b ldr r3, [r3, #0] 800b4f2: f44f 7100 mov.w r1, #512 ; 0x200 800b4f6: 4618 mov r0, r3 800b4f8: f002 fdbe bl 800e078 800b4fc: 64b8 str r0, [r7, #72] ; 0x48 if (errorstate != HAL_SD_ERROR_NONE) 800b4fe: 6cbb ldr r3, [r7, #72] ; 0x48 800b500: 2b00 cmp r3, #0 800b502: d00d beq.n 800b520 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800b504: 687b ldr r3, [r7, #4] 800b506: 681b ldr r3, [r3, #0] 800b508: 4a08 ldr r2, [pc, #32] ; (800b52c ) 800b50a: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode = errorstate; 800b50c: 687b ldr r3, [r7, #4] 800b50e: 6cba ldr r2, [r7, #72] ; 0x48 800b510: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800b512: 687b ldr r3, [r7, #4] 800b514: 2201 movs r2, #1 800b516: f883 2030 strb.w r2, [r3, #48] ; 0x30 status = HAL_ERROR; 800b51a: 2301 movs r3, #1 800b51c: f887 304f strb.w r3, [r7, #79] ; 0x4f } return status; 800b520: f897 304f ldrb.w r3, [r7, #79] ; 0x4f } 800b524: 4618 mov r0, r3 800b526: 3750 adds r7, #80 ; 0x50 800b528: 46bd mov sp, r7 800b52a: bd80 pop {r7, pc} 800b52c: 1fe00fff .word 0x1fe00fff 0800b530 : * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that * will contain the SD card status information * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { 800b530: b480 push {r7} 800b532: b083 sub sp, #12 800b534: af00 add r7, sp, #0 800b536: 6078 str r0, [r7, #4] 800b538: 6039 str r1, [r7, #0] pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); 800b53a: 687b ldr r3, [r7, #4] 800b53c: 6b9a ldr r2, [r3, #56] ; 0x38 800b53e: 683b ldr r3, [r7, #0] 800b540: 601a str r2, [r3, #0] pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); 800b542: 687b ldr r3, [r7, #4] 800b544: 6bda ldr r2, [r3, #60] ; 0x3c 800b546: 683b ldr r3, [r7, #0] 800b548: 605a str r2, [r3, #4] pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); 800b54a: 687b ldr r3, [r7, #4] 800b54c: 6c1a ldr r2, [r3, #64] ; 0x40 800b54e: 683b ldr r3, [r7, #0] 800b550: 609a str r2, [r3, #8] pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); 800b552: 687b ldr r3, [r7, #4] 800b554: 6c5a ldr r2, [r3, #68] ; 0x44 800b556: 683b ldr r3, [r7, #0] 800b558: 60da str r2, [r3, #12] pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); 800b55a: 687b ldr r3, [r7, #4] 800b55c: 6c9a ldr r2, [r3, #72] ; 0x48 800b55e: 683b ldr r3, [r7, #0] 800b560: 611a str r2, [r3, #16] pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); 800b562: 687b ldr r3, [r7, #4] 800b564: 6cda ldr r2, [r3, #76] ; 0x4c 800b566: 683b ldr r3, [r7, #0] 800b568: 615a str r2, [r3, #20] pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); 800b56a: 687b ldr r3, [r7, #4] 800b56c: 6d1a ldr r2, [r3, #80] ; 0x50 800b56e: 683b ldr r3, [r7, #0] 800b570: 619a str r2, [r3, #24] pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); 800b572: 687b ldr r3, [r7, #4] 800b574: 6d5a ldr r2, [r3, #84] ; 0x54 800b576: 683b ldr r3, [r7, #0] 800b578: 61da str r2, [r3, #28] return HAL_OK; 800b57a: 2300 movs r3, #0 } 800b57c: 4618 mov r0, r3 800b57e: 370c adds r7, #12 800b580: 46bd mov sp, r7 800b582: f85d 7b04 ldr.w r7, [sp], #4 800b586: 4770 bx lr 0800b588 : * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) { 800b588: b590 push {r4, r7, lr} 800b58a: b08d sub sp, #52 ; 0x34 800b58c: af02 add r7, sp, #8 800b58e: 6078 str r0, [r7, #4] 800b590: 6039 str r1, [r7, #0] SDMMC_InitTypeDef Init; uint32_t errorstate; uint32_t sdmmc_clk; HAL_StatusTypeDef status = HAL_OK; 800b592: 2300 movs r3, #0 800b594: f887 3027 strb.w r3, [r7, #39] ; 0x27 /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); /* Change State */ hsd->State = HAL_SD_STATE_BUSY; 800b598: 687b ldr r3, [r7, #4] 800b59a: 2203 movs r2, #3 800b59c: f883 2030 strb.w r2, [r3, #48] ; 0x30 if (hsd->SdCard.CardType != CARD_SECURED) 800b5a0: 687b ldr r3, [r7, #4] 800b5a2: 6b9b ldr r3, [r3, #56] ; 0x38 800b5a4: 2b03 cmp r3, #3 800b5a6: d02e beq.n 800b606 { if (WideMode == SDMMC_BUS_WIDE_8B) 800b5a8: 683b ldr r3, [r7, #0] 800b5aa: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 800b5ae: d106 bne.n 800b5be { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800b5b0: 687b ldr r3, [r7, #4] 800b5b2: 6b5b ldr r3, [r3, #52] ; 0x34 800b5b4: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 800b5b8: 687b ldr r3, [r7, #4] 800b5ba: 635a str r2, [r3, #52] ; 0x34 800b5bc: e029 b.n 800b612 } else if (WideMode == SDMMC_BUS_WIDE_4B) 800b5be: 683b ldr r3, [r7, #0] 800b5c0: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 800b5c4: d10a bne.n 800b5dc { errorstate = SD_WideBus_Enable(hsd); 800b5c6: 6878 ldr r0, [r7, #4] 800b5c8: f000 fb64 bl 800bc94 800b5cc: 6238 str r0, [r7, #32] hsd->ErrorCode |= errorstate; 800b5ce: 687b ldr r3, [r7, #4] 800b5d0: 6b5a ldr r2, [r3, #52] ; 0x34 800b5d2: 6a3b ldr r3, [r7, #32] 800b5d4: 431a orrs r2, r3 800b5d6: 687b ldr r3, [r7, #4] 800b5d8: 635a str r2, [r3, #52] ; 0x34 800b5da: e01a b.n 800b612 } else if (WideMode == SDMMC_BUS_WIDE_1B) 800b5dc: 683b ldr r3, [r7, #0] 800b5de: 2b00 cmp r3, #0 800b5e0: d10a bne.n 800b5f8 { errorstate = SD_WideBus_Disable(hsd); 800b5e2: 6878 ldr r0, [r7, #4] 800b5e4: f000 fba1 bl 800bd2a 800b5e8: 6238 str r0, [r7, #32] hsd->ErrorCode |= errorstate; 800b5ea: 687b ldr r3, [r7, #4] 800b5ec: 6b5a ldr r2, [r3, #52] ; 0x34 800b5ee: 6a3b ldr r3, [r7, #32] 800b5f0: 431a orrs r2, r3 800b5f2: 687b ldr r3, [r7, #4] 800b5f4: 635a str r2, [r3, #52] ; 0x34 800b5f6: e00c b.n 800b612 } else { /* WideMode is not a valid argument*/ hsd->ErrorCode |= HAL_SD_ERROR_PARAM; 800b5f8: 687b ldr r3, [r7, #4] 800b5fa: 6b5b ldr r3, [r3, #52] ; 0x34 800b5fc: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 800b600: 687b ldr r3, [r7, #4] 800b602: 635a str r2, [r3, #52] ; 0x34 800b604: e005 b.n 800b612 } } else { /* SD Card does not support this feature */ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800b606: 687b ldr r3, [r7, #4] 800b608: 6b5b ldr r3, [r3, #52] ; 0x34 800b60a: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 800b60e: 687b ldr r3, [r7, #4] 800b610: 635a str r2, [r3, #52] ; 0x34 } if (hsd->ErrorCode != HAL_SD_ERROR_NONE) 800b612: 687b ldr r3, [r7, #4] 800b614: 6b5b ldr r3, [r3, #52] ; 0x34 800b616: 2b00 cmp r3, #0 800b618: d007 beq.n 800b62a { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800b61a: 687b ldr r3, [r7, #4] 800b61c: 681b ldr r3, [r3, #0] 800b61e: 4a5f ldr r2, [pc, #380] ; (800b79c ) 800b620: 639a str r2, [r3, #56] ; 0x38 status = HAL_ERROR; 800b622: 2301 movs r3, #1 800b624: f887 3027 strb.w r3, [r7, #39] ; 0x27 800b628: e096 b.n 800b758 } else { sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); 800b62a: f44f 3080 mov.w r0, #65536 ; 0x10000 800b62e: f04f 0100 mov.w r1, #0 800b632: f7fd fea3 bl 800937c 800b636: 61f8 str r0, [r7, #28] if (sdmmc_clk != 0U) 800b638: 69fb ldr r3, [r7, #28] 800b63a: 2b00 cmp r3, #0 800b63c: f000 8083 beq.w 800b746 { /* Configure the SDMMC peripheral */ Init.ClockEdge = hsd->Init.ClockEdge; 800b640: 687b ldr r3, [r7, #4] 800b642: 685b ldr r3, [r3, #4] 800b644: 60bb str r3, [r7, #8] Init.ClockPowerSave = hsd->Init.ClockPowerSave; 800b646: 687b ldr r3, [r7, #4] 800b648: 689b ldr r3, [r3, #8] 800b64a: 60fb str r3, [r7, #12] Init.BusWide = WideMode; 800b64c: 683b ldr r3, [r7, #0] 800b64e: 613b str r3, [r7, #16] Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; 800b650: 687b ldr r3, [r7, #4] 800b652: 691b ldr r3, [r3, #16] 800b654: 617b str r3, [r7, #20] /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ))) 800b656: 687b ldr r3, [r7, #4] 800b658: 695a ldr r2, [r3, #20] 800b65a: 69fb ldr r3, [r7, #28] 800b65c: 4950 ldr r1, [pc, #320] ; (800b7a0 ) 800b65e: fba1 1303 umull r1, r3, r1, r3 800b662: 0e1b lsrs r3, r3, #24 800b664: 429a cmp r2, r3 800b666: d303 bcc.n 800b670 { Init.ClockDiv = hsd->Init.ClockDiv; 800b668: 687b ldr r3, [r7, #4] 800b66a: 695b ldr r3, [r3, #20] 800b66c: 61bb str r3, [r7, #24] 800b66e: e05a b.n 800b726 } else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) 800b670: 687b ldr r3, [r7, #4] 800b672: 6d9b ldr r3, [r3, #88] ; 0x58 800b674: f5b3 7f00 cmp.w r3, #512 ; 0x200 800b678: d103 bne.n 800b682 { /* UltraHigh speed SD card,user Clock div */ Init.ClockDiv = hsd->Init.ClockDiv; 800b67a: 687b ldr r3, [r7, #4] 800b67c: 695b ldr r3, [r3, #20] 800b67e: 61bb str r3, [r7, #24] 800b680: e051 b.n 800b726 } else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) 800b682: 687b ldr r3, [r7, #4] 800b684: 6d9b ldr r3, [r3, #88] ; 0x58 800b686: f5b3 7f80 cmp.w r3, #256 ; 0x100 800b68a: d126 bne.n 800b6da { /* High speed SD card, Max Frequency = 50Mhz */ if (hsd->Init.ClockDiv == 0U) 800b68c: 687b ldr r3, [r7, #4] 800b68e: 695b ldr r3, [r3, #20] 800b690: 2b00 cmp r3, #0 800b692: d10e bne.n 800b6b2 { if (sdmmc_clk > SD_HIGH_SPEED_FREQ) 800b694: 69fb ldr r3, [r7, #28] 800b696: 4a43 ldr r2, [pc, #268] ; (800b7a4 ) 800b698: 4293 cmp r3, r2 800b69a: d906 bls.n 800b6aa { Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); 800b69c: 69fb ldr r3, [r7, #28] 800b69e: 4a40 ldr r2, [pc, #256] ; (800b7a0 ) 800b6a0: fba2 2303 umull r2, r3, r2, r3 800b6a4: 0e5b lsrs r3, r3, #25 800b6a6: 61bb str r3, [r7, #24] 800b6a8: e03d b.n 800b726 } else { Init.ClockDiv = hsd->Init.ClockDiv; 800b6aa: 687b ldr r3, [r7, #4] 800b6ac: 695b ldr r3, [r3, #20] 800b6ae: 61bb str r3, [r7, #24] 800b6b0: e039 b.n 800b726 } } else { if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ) 800b6b2: 687b ldr r3, [r7, #4] 800b6b4: 695b ldr r3, [r3, #20] 800b6b6: 005b lsls r3, r3, #1 800b6b8: 69fa ldr r2, [r7, #28] 800b6ba: fbb2 f3f3 udiv r3, r2, r3 800b6be: 4a39 ldr r2, [pc, #228] ; (800b7a4 ) 800b6c0: 4293 cmp r3, r2 800b6c2: d906 bls.n 800b6d2 { Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); 800b6c4: 69fb ldr r3, [r7, #28] 800b6c6: 4a36 ldr r2, [pc, #216] ; (800b7a0 ) 800b6c8: fba2 2303 umull r2, r3, r2, r3 800b6cc: 0e5b lsrs r3, r3, #25 800b6ce: 61bb str r3, [r7, #24] 800b6d0: e029 b.n 800b726 } else { Init.ClockDiv = hsd->Init.ClockDiv; 800b6d2: 687b ldr r3, [r7, #4] 800b6d4: 695b ldr r3, [r3, #20] 800b6d6: 61bb str r3, [r7, #24] 800b6d8: e025 b.n 800b726 } } else { /* No High speed SD card, Max Frequency = 25Mhz */ if (hsd->Init.ClockDiv == 0U) 800b6da: 687b ldr r3, [r7, #4] 800b6dc: 695b ldr r3, [r3, #20] 800b6de: 2b00 cmp r3, #0 800b6e0: d10e bne.n 800b700 { if (sdmmc_clk > SD_NORMAL_SPEED_FREQ) 800b6e2: 69fb ldr r3, [r7, #28] 800b6e4: 4a30 ldr r2, [pc, #192] ; (800b7a8 ) 800b6e6: 4293 cmp r3, r2 800b6e8: d906 bls.n 800b6f8 { Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); 800b6ea: 69fb ldr r3, [r7, #28] 800b6ec: 4a2c ldr r2, [pc, #176] ; (800b7a0 ) 800b6ee: fba2 2303 umull r2, r3, r2, r3 800b6f2: 0e1b lsrs r3, r3, #24 800b6f4: 61bb str r3, [r7, #24] 800b6f6: e016 b.n 800b726 } else { Init.ClockDiv = hsd->Init.ClockDiv; 800b6f8: 687b ldr r3, [r7, #4] 800b6fa: 695b ldr r3, [r3, #20] 800b6fc: 61bb str r3, [r7, #24] 800b6fe: e012 b.n 800b726 } } else { if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ) 800b700: 687b ldr r3, [r7, #4] 800b702: 695b ldr r3, [r3, #20] 800b704: 005b lsls r3, r3, #1 800b706: 69fa ldr r2, [r7, #28] 800b708: fbb2 f3f3 udiv r3, r2, r3 800b70c: 4a26 ldr r2, [pc, #152] ; (800b7a8 ) 800b70e: 4293 cmp r3, r2 800b710: d906 bls.n 800b720 { Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); 800b712: 69fb ldr r3, [r7, #28] 800b714: 4a22 ldr r2, [pc, #136] ; (800b7a0 ) 800b716: fba2 2303 umull r2, r3, r2, r3 800b71a: 0e1b lsrs r3, r3, #24 800b71c: 61bb str r3, [r7, #24] 800b71e: e002 b.n 800b726 } else { Init.ClockDiv = hsd->Init.ClockDiv; 800b720: 687b ldr r3, [r7, #4] 800b722: 695b ldr r3, [r3, #20] 800b724: 61bb str r3, [r7, #24] #if (USE_SD_TRANSCEIVER != 0U) Init.TranceiverPresent = hsd->Init.TranceiverPresent; #endif /* USE_SD_TRANSCEIVER */ (void)SDMMC_Init(hsd->Instance, Init); 800b726: 687b ldr r3, [r7, #4] 800b728: 681c ldr r4, [r3, #0] 800b72a: 466a mov r2, sp 800b72c: f107 0314 add.w r3, r7, #20 800b730: e893 0003 ldmia.w r3, {r0, r1} 800b734: e882 0003 stmia.w r2, {r0, r1} 800b738: f107 0308 add.w r3, r7, #8 800b73c: cb0e ldmia r3, {r1, r2, r3} 800b73e: 4620 mov r0, r4 800b740: f002 fbbc bl 800debc 800b744: e008 b.n 800b758 } else { hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER; 800b746: 687b ldr r3, [r7, #4] 800b748: 6b5b ldr r3, [r3, #52] ; 0x34 800b74a: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 800b74e: 687b ldr r3, [r7, #4] 800b750: 635a str r2, [r3, #52] ; 0x34 status = HAL_ERROR; 800b752: 2301 movs r3, #1 800b754: f887 3027 strb.w r3, [r7, #39] ; 0x27 } } /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); 800b758: 687b ldr r3, [r7, #4] 800b75a: 681b ldr r3, [r3, #0] 800b75c: f44f 7100 mov.w r1, #512 ; 0x200 800b760: 4618 mov r0, r3 800b762: f002 fc89 bl 800e078 800b766: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 800b768: 6a3b ldr r3, [r7, #32] 800b76a: 2b00 cmp r3, #0 800b76c: d00c beq.n 800b788 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800b76e: 687b ldr r3, [r7, #4] 800b770: 681b ldr r3, [r3, #0] 800b772: 4a0a ldr r2, [pc, #40] ; (800b79c ) 800b774: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 800b776: 687b ldr r3, [r7, #4] 800b778: 6b5a ldr r2, [r3, #52] ; 0x34 800b77a: 6a3b ldr r3, [r7, #32] 800b77c: 431a orrs r2, r3 800b77e: 687b ldr r3, [r7, #4] 800b780: 635a str r2, [r3, #52] ; 0x34 status = HAL_ERROR; 800b782: 2301 movs r3, #1 800b784: f887 3027 strb.w r3, [r7, #39] ; 0x27 } /* Change State */ hsd->State = HAL_SD_STATE_READY; 800b788: 687b ldr r3, [r7, #4] 800b78a: 2201 movs r2, #1 800b78c: f883 2030 strb.w r2, [r3, #48] ; 0x30 return status; 800b790: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 } 800b794: 4618 mov r0, r3 800b796: 372c adds r7, #44 ; 0x2c 800b798: 46bd mov sp, r7 800b79a: bd90 pop {r4, r7, pc} 800b79c: 1fe00fff .word 0x1fe00fff 800b7a0: 55e63b89 .word 0x55e63b89 800b7a4: 02faf080 .word 0x02faf080 800b7a8: 017d7840 .word 0x017d7840 0800b7ac : * @brief Gets the current sd card data state. * @param hsd: pointer to SD handle * @retval Card state */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) { 800b7ac: b580 push {r7, lr} 800b7ae: b086 sub sp, #24 800b7b0: af00 add r7, sp, #0 800b7b2: 6078 str r0, [r7, #4] uint32_t cardstate; uint32_t errorstate; uint32_t resp1 = 0; 800b7b4: 2300 movs r3, #0 800b7b6: 60fb str r3, [r7, #12] errorstate = SD_SendStatus(hsd, &resp1); 800b7b8: f107 030c add.w r3, r7, #12 800b7bc: 4619 mov r1, r3 800b7be: 6878 ldr r0, [r7, #4] 800b7c0: f000 fa40 bl 800bc44 800b7c4: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800b7c6: 697b ldr r3, [r7, #20] 800b7c8: 2b00 cmp r3, #0 800b7ca: d005 beq.n 800b7d8 { hsd->ErrorCode |= errorstate; 800b7cc: 687b ldr r3, [r7, #4] 800b7ce: 6b5a ldr r2, [r3, #52] ; 0x34 800b7d0: 697b ldr r3, [r7, #20] 800b7d2: 431a orrs r2, r3 800b7d4: 687b ldr r3, [r7, #4] 800b7d6: 635a str r2, [r3, #52] ; 0x34 } cardstate = ((resp1 >> 9U) & 0x0FU); 800b7d8: 68fb ldr r3, [r7, #12] 800b7da: 0a5b lsrs r3, r3, #9 800b7dc: f003 030f and.w r3, r3, #15 800b7e0: 613b str r3, [r7, #16] return (HAL_SD_CardStateTypeDef)cardstate; 800b7e2: 693b ldr r3, [r7, #16] } 800b7e4: 4618 mov r0, r3 800b7e6: 3718 adds r7, #24 800b7e8: 46bd mov sp, r7 800b7ea: bd80 pop {r7, pc} 0800b7ec : * @brief Initializes the sd card. * @param hsd: Pointer to SD handle * @retval SD Card error state */ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { 800b7ec: b580 push {r7, lr} 800b7ee: b090 sub sp, #64 ; 0x40 800b7f0: af00 add r7, sp, #0 800b7f2: 6078 str r0, [r7, #4] HAL_SD_CardCSDTypeDef CSD; uint32_t errorstate; uint16_t sd_rca = 0U; 800b7f4: 2300 movs r3, #0 800b7f6: 817b strh r3, [r7, #10] uint32_t tickstart = HAL_GetTick(); 800b7f8: f7f6 fdb4 bl 8002364 800b7fc: 63f8 str r0, [r7, #60] ; 0x3c /* Check the power State */ if (SDMMC_GetPowerState(hsd->Instance) == 0U) 800b7fe: 687b ldr r3, [r7, #4] 800b800: 681b ldr r3, [r3, #0] 800b802: 4618 mov r0, r3 800b804: f002 fbb3 bl 800df6e 800b808: 4603 mov r3, r0 800b80a: 2b00 cmp r3, #0 800b80c: d102 bne.n 800b814 { /* Power off */ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; 800b80e: f04f 6380 mov.w r3, #67108864 ; 0x4000000 800b812: e0b5 b.n 800b980 } if (hsd->SdCard.CardType != CARD_SECURED) 800b814: 687b ldr r3, [r7, #4] 800b816: 6b9b ldr r3, [r3, #56] ; 0x38 800b818: 2b03 cmp r3, #3 800b81a: d02e beq.n 800b87a { /* Send CMD2 ALL_SEND_CID */ errorstate = SDMMC_CmdSendCID(hsd->Instance); 800b81c: 687b ldr r3, [r7, #4] 800b81e: 681b ldr r3, [r3, #0] 800b820: 4618 mov r0, r3 800b822: f002 fdfe bl 800e422 800b826: 63b8 str r0, [r7, #56] ; 0x38 if (errorstate != HAL_SD_ERROR_NONE) 800b828: 6bbb ldr r3, [r7, #56] ; 0x38 800b82a: 2b00 cmp r3, #0 800b82c: d001 beq.n 800b832 { return errorstate; 800b82e: 6bbb ldr r3, [r7, #56] ; 0x38 800b830: e0a6 b.n 800b980 } else { /* Get Card identification number data */ hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); 800b832: 687b ldr r3, [r7, #4] 800b834: 681b ldr r3, [r3, #0] 800b836: 2100 movs r1, #0 800b838: 4618 mov r0, r3 800b83a: f002 fbde bl 800dffa 800b83e: 4602 mov r2, r0 800b840: 687b ldr r3, [r7, #4] 800b842: 66da str r2, [r3, #108] ; 0x6c hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); 800b844: 687b ldr r3, [r7, #4] 800b846: 681b ldr r3, [r3, #0] 800b848: 2104 movs r1, #4 800b84a: 4618 mov r0, r3 800b84c: f002 fbd5 bl 800dffa 800b850: 4602 mov r2, r0 800b852: 687b ldr r3, [r7, #4] 800b854: 671a str r2, [r3, #112] ; 0x70 hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); 800b856: 687b ldr r3, [r7, #4] 800b858: 681b ldr r3, [r3, #0] 800b85a: 2108 movs r1, #8 800b85c: 4618 mov r0, r3 800b85e: f002 fbcc bl 800dffa 800b862: 4602 mov r2, r0 800b864: 687b ldr r3, [r7, #4] 800b866: 675a str r2, [r3, #116] ; 0x74 hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); 800b868: 687b ldr r3, [r7, #4] 800b86a: 681b ldr r3, [r3, #0] 800b86c: 210c movs r1, #12 800b86e: 4618 mov r0, r3 800b870: f002 fbc3 bl 800dffa 800b874: 4602 mov r2, r0 800b876: 687b ldr r3, [r7, #4] 800b878: 679a str r2, [r3, #120] ; 0x78 } } if (hsd->SdCard.CardType != CARD_SECURED) 800b87a: 687b ldr r3, [r7, #4] 800b87c: 6b9b ldr r3, [r3, #56] ; 0x38 800b87e: 2b03 cmp r3, #3 800b880: d01d beq.n 800b8be { /* Send CMD3 SET_REL_ADDR with argument 0 */ /* SD Card publishes its RCA. */ while (sd_rca == 0U) 800b882: e019 b.n 800b8b8 { errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); 800b884: 687b ldr r3, [r7, #4] 800b886: 681b ldr r3, [r3, #0] 800b888: f107 020a add.w r2, r7, #10 800b88c: 4611 mov r1, r2 800b88e: 4618 mov r0, r3 800b890: f002 fe06 bl 800e4a0 800b894: 63b8 str r0, [r7, #56] ; 0x38 if (errorstate != HAL_SD_ERROR_NONE) 800b896: 6bbb ldr r3, [r7, #56] ; 0x38 800b898: 2b00 cmp r3, #0 800b89a: d001 beq.n 800b8a0 { return errorstate; 800b89c: 6bbb ldr r3, [r7, #56] ; 0x38 800b89e: e06f b.n 800b980 } if ((HAL_GetTick() - tickstart) >= SDMMC_CMDTIMEOUT) 800b8a0: f7f6 fd60 bl 8002364 800b8a4: 4602 mov r2, r0 800b8a6: 6bfb ldr r3, [r7, #60] ; 0x3c 800b8a8: 1ad3 subs r3, r2, r3 800b8aa: f241 3287 movw r2, #4999 ; 0x1387 800b8ae: 4293 cmp r3, r2 800b8b0: d902 bls.n 800b8b8 { return HAL_SD_ERROR_TIMEOUT; 800b8b2: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800b8b6: e063 b.n 800b980 while (sd_rca == 0U) 800b8b8: 897b ldrh r3, [r7, #10] 800b8ba: 2b00 cmp r3, #0 800b8bc: d0e2 beq.n 800b884 } } } if (hsd->SdCard.CardType != CARD_SECURED) 800b8be: 687b ldr r3, [r7, #4] 800b8c0: 6b9b ldr r3, [r3, #56] ; 0x38 800b8c2: 2b03 cmp r3, #3 800b8c4: d036 beq.n 800b934 { /* Get the SD card RCA */ hsd->SdCard.RelCardAdd = sd_rca; 800b8c6: 897b ldrh r3, [r7, #10] 800b8c8: 461a mov r2, r3 800b8ca: 687b ldr r3, [r7, #4] 800b8cc: 645a str r2, [r3, #68] ; 0x44 /* Send CMD9 SEND_CSD with argument as card's RCA */ errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 800b8ce: 687b ldr r3, [r7, #4] 800b8d0: 681a ldr r2, [r3, #0] 800b8d2: 687b ldr r3, [r7, #4] 800b8d4: 6c5b ldr r3, [r3, #68] ; 0x44 800b8d6: 041b lsls r3, r3, #16 800b8d8: 4619 mov r1, r3 800b8da: 4610 mov r0, r2 800b8dc: f002 fdc0 bl 800e460 800b8e0: 63b8 str r0, [r7, #56] ; 0x38 if (errorstate != HAL_SD_ERROR_NONE) 800b8e2: 6bbb ldr r3, [r7, #56] ; 0x38 800b8e4: 2b00 cmp r3, #0 800b8e6: d001 beq.n 800b8ec { return errorstate; 800b8e8: 6bbb ldr r3, [r7, #56] ; 0x38 800b8ea: e049 b.n 800b980 } else { /* Get Card Specific Data */ hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); 800b8ec: 687b ldr r3, [r7, #4] 800b8ee: 681b ldr r3, [r3, #0] 800b8f0: 2100 movs r1, #0 800b8f2: 4618 mov r0, r3 800b8f4: f002 fb81 bl 800dffa 800b8f8: 4602 mov r2, r0 800b8fa: 687b ldr r3, [r7, #4] 800b8fc: 65da str r2, [r3, #92] ; 0x5c hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); 800b8fe: 687b ldr r3, [r7, #4] 800b900: 681b ldr r3, [r3, #0] 800b902: 2104 movs r1, #4 800b904: 4618 mov r0, r3 800b906: f002 fb78 bl 800dffa 800b90a: 4602 mov r2, r0 800b90c: 687b ldr r3, [r7, #4] 800b90e: 661a str r2, [r3, #96] ; 0x60 hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); 800b910: 687b ldr r3, [r7, #4] 800b912: 681b ldr r3, [r3, #0] 800b914: 2108 movs r1, #8 800b916: 4618 mov r0, r3 800b918: f002 fb6f bl 800dffa 800b91c: 4602 mov r2, r0 800b91e: 687b ldr r3, [r7, #4] 800b920: 665a str r2, [r3, #100] ; 0x64 hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); 800b922: 687b ldr r3, [r7, #4] 800b924: 681b ldr r3, [r3, #0] 800b926: 210c movs r1, #12 800b928: 4618 mov r0, r3 800b92a: f002 fb66 bl 800dffa 800b92e: 4602 mov r2, r0 800b930: 687b ldr r3, [r7, #4] 800b932: 669a str r2, [r3, #104] ; 0x68 } } /* Get the Card Class */ hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U); 800b934: 687b ldr r3, [r7, #4] 800b936: 681b ldr r3, [r3, #0] 800b938: 2104 movs r1, #4 800b93a: 4618 mov r0, r3 800b93c: f002 fb5d bl 800dffa 800b940: 4603 mov r3, r0 800b942: 0d1a lsrs r2, r3, #20 800b944: 687b ldr r3, [r7, #4] 800b946: 641a str r2, [r3, #64] ; 0x40 /* Get CSD parameters */ if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) 800b948: f107 030c add.w r3, r7, #12 800b94c: 4619 mov r1, r3 800b94e: 6878 ldr r0, [r7, #4] 800b950: f7ff fb8c bl 800b06c 800b954: 4603 mov r3, r0 800b956: 2b00 cmp r3, #0 800b958: d002 beq.n 800b960 { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800b95a: f04f 5380 mov.w r3, #268435456 ; 0x10000000 800b95e: e00f b.n 800b980 } /* Select the Card */ errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); 800b960: 687b ldr r3, [r7, #4] 800b962: 681a ldr r2, [r3, #0] 800b964: 687b ldr r3, [r7, #4] 800b966: 6c5b ldr r3, [r3, #68] ; 0x44 800b968: 041b lsls r3, r3, #16 800b96a: 4619 mov r1, r3 800b96c: 4610 mov r0, r2 800b96e: f002 fc6f bl 800e250 800b972: 63b8 str r0, [r7, #56] ; 0x38 if (errorstate != HAL_SD_ERROR_NONE) 800b974: 6bbb ldr r3, [r7, #56] ; 0x38 800b976: 2b00 cmp r3, #0 800b978: d001 beq.n 800b97e { return errorstate; 800b97a: 6bbb ldr r3, [r7, #56] ; 0x38 800b97c: e000 b.n 800b980 } /* All cards are initialized */ return HAL_SD_ERROR_NONE; 800b97e: 2300 movs r3, #0 } 800b980: 4618 mov r0, r3 800b982: 3740 adds r7, #64 ; 0x40 800b984: 46bd mov sp, r7 800b986: bd80 pop {r7, pc} 0800b988 : * in the SD handle. * @param hsd: Pointer to SD handle * @retval error state */ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { 800b988: b580 push {r7, lr} 800b98a: b086 sub sp, #24 800b98c: af00 add r7, sp, #0 800b98e: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 800b990: 2300 movs r3, #0 800b992: 60bb str r3, [r7, #8] uint32_t response = 0U; 800b994: 2300 movs r3, #0 800b996: 617b str r3, [r7, #20] uint32_t validvoltage = 0U; 800b998: 2300 movs r3, #0 800b99a: 613b str r3, [r7, #16] #if (USE_SD_TRANSCEIVER != 0U) uint32_t tickstart = HAL_GetTick(); #endif /* USE_SD_TRANSCEIVER */ /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); 800b99c: 687b ldr r3, [r7, #4] 800b99e: 681b ldr r3, [r3, #0] 800b9a0: 4618 mov r0, r3 800b9a2: f002 fc78 bl 800e296 800b9a6: 60f8 str r0, [r7, #12] if (errorstate != HAL_SD_ERROR_NONE) 800b9a8: 68fb ldr r3, [r7, #12] 800b9aa: 2b00 cmp r3, #0 800b9ac: d001 beq.n 800b9b2 { return errorstate; 800b9ae: 68fb ldr r3, [r7, #12] 800b9b0: e072 b.n 800ba98 } /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); 800b9b2: 687b ldr r3, [r7, #4] 800b9b4: 681b ldr r3, [r3, #0] 800b9b6: 4618 mov r0, r3 800b9b8: f002 fc8b bl 800e2d2 800b9bc: 60f8 str r0, [r7, #12] if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */ 800b9be: 68fb ldr r3, [r7, #12] 800b9c0: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 800b9c4: d10d bne.n 800b9e2 { hsd->SdCard.CardVersion = CARD_V1_X; 800b9c6: 687b ldr r3, [r7, #4] 800b9c8: 2200 movs r2, #0 800b9ca: 63da str r2, [r3, #60] ; 0x3c /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); 800b9cc: 687b ldr r3, [r7, #4] 800b9ce: 681b ldr r3, [r3, #0] 800b9d0: 4618 mov r0, r3 800b9d2: f002 fc60 bl 800e296 800b9d6: 60f8 str r0, [r7, #12] if (errorstate != HAL_SD_ERROR_NONE) 800b9d8: 68fb ldr r3, [r7, #12] 800b9da: 2b00 cmp r3, #0 800b9dc: d004 beq.n 800b9e8 { return errorstate; 800b9de: 68fb ldr r3, [r7, #12] 800b9e0: e05a b.n 800ba98 } } else { hsd->SdCard.CardVersion = CARD_V2_X; 800b9e2: 687b ldr r3, [r7, #4] 800b9e4: 2201 movs r2, #1 800b9e6: 63da str r2, [r3, #60] ; 0x3c } if (hsd->SdCard.CardVersion == CARD_V2_X) 800b9e8: 687b ldr r3, [r7, #4] 800b9ea: 6bdb ldr r3, [r3, #60] ; 0x3c 800b9ec: 2b01 cmp r3, #1 800b9ee: d137 bne.n 800ba60 { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); 800b9f0: 687b ldr r3, [r7, #4] 800b9f2: 681b ldr r3, [r3, #0] 800b9f4: 2100 movs r1, #0 800b9f6: 4618 mov r0, r3 800b9f8: f002 fc8b bl 800e312 800b9fc: 60f8 str r0, [r7, #12] if (errorstate != HAL_SD_ERROR_NONE) 800b9fe: 68fb ldr r3, [r7, #12] 800ba00: 2b00 cmp r3, #0 800ba02: d02d beq.n 800ba60 { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800ba04: f04f 5380 mov.w r3, #268435456 ; 0x10000000 800ba08: e046 b.n 800ba98 /* SD CARD */ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); 800ba0a: 687b ldr r3, [r7, #4] 800ba0c: 681b ldr r3, [r3, #0] 800ba0e: 2100 movs r1, #0 800ba10: 4618 mov r0, r3 800ba12: f002 fc7e bl 800e312 800ba16: 60f8 str r0, [r7, #12] if (errorstate != HAL_SD_ERROR_NONE) 800ba18: 68fb ldr r3, [r7, #12] 800ba1a: 2b00 cmp r3, #0 800ba1c: d001 beq.n 800ba22 { return errorstate; 800ba1e: 68fb ldr r3, [r7, #12] 800ba20: e03a b.n 800ba98 } /* Send CMD41 */ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | 800ba22: 687b ldr r3, [r7, #4] 800ba24: 681b ldr r3, [r3, #0] 800ba26: 491e ldr r1, [pc, #120] ; (800baa0 ) 800ba28: 4618 mov r0, r3 800ba2a: f002 fc95 bl 800e358 800ba2e: 60f8 str r0, [r7, #12] SD_SWITCH_1_8V_CAPACITY); if (errorstate != HAL_SD_ERROR_NONE) 800ba30: 68fb ldr r3, [r7, #12] 800ba32: 2b00 cmp r3, #0 800ba34: d002 beq.n 800ba3c { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800ba36: f04f 5380 mov.w r3, #268435456 ; 0x10000000 800ba3a: e02d b.n 800ba98 } /* Get command response */ response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); 800ba3c: 687b ldr r3, [r7, #4] 800ba3e: 681b ldr r3, [r3, #0] 800ba40: 2100 movs r1, #0 800ba42: 4618 mov r0, r3 800ba44: f002 fad9 bl 800dffa 800ba48: 6178 str r0, [r7, #20] /* Get operating voltage*/ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); 800ba4a: 697b ldr r3, [r7, #20] 800ba4c: 0fdb lsrs r3, r3, #31 800ba4e: 2b01 cmp r3, #1 800ba50: d101 bne.n 800ba56 800ba52: 2301 movs r3, #1 800ba54: e000 b.n 800ba58 800ba56: 2300 movs r3, #0 800ba58: 613b str r3, [r7, #16] count++; 800ba5a: 68bb ldr r3, [r7, #8] 800ba5c: 3301 adds r3, #1 800ba5e: 60bb str r3, [r7, #8] while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) 800ba60: 68bb ldr r3, [r7, #8] 800ba62: f64f 72fe movw r2, #65534 ; 0xfffe 800ba66: 4293 cmp r3, r2 800ba68: d802 bhi.n 800ba70 800ba6a: 693b ldr r3, [r7, #16] 800ba6c: 2b00 cmp r3, #0 800ba6e: d0cc beq.n 800ba0a } if (count >= SDMMC_MAX_VOLT_TRIAL) 800ba70: 68bb ldr r3, [r7, #8] 800ba72: f64f 72fe movw r2, #65534 ; 0xfffe 800ba76: 4293 cmp r3, r2 800ba78: d902 bls.n 800ba80 { return HAL_SD_ERROR_INVALID_VOLTRANGE; 800ba7a: f04f 7380 mov.w r3, #16777216 ; 0x1000000 800ba7e: e00b b.n 800ba98 } /* Set default card type */ hsd->SdCard.CardType = CARD_SDSC; 800ba80: 687b ldr r3, [r7, #4] 800ba82: 2200 movs r2, #0 800ba84: 639a str r2, [r3, #56] ; 0x38 if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) 800ba86: 697b ldr r3, [r7, #20] 800ba88: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 800ba8c: 2b00 cmp r3, #0 800ba8e: d002 beq.n 800ba96 { hsd->SdCard.CardType = CARD_SDHC_SDXC; 800ba90: 687b ldr r3, [r7, #4] 800ba92: 2201 movs r2, #1 800ba94: 639a str r2, [r3, #56] ; 0x38 } } #endif /* USE_SD_TRANSCEIVER */ } return HAL_SD_ERROR_NONE; 800ba96: 2300 movs r3, #0 } 800ba98: 4618 mov r0, r3 800ba9a: 3718 adds r7, #24 800ba9c: 46bd mov sp, r7 800ba9e: bd80 pop {r7, pc} 800baa0: c1100000 .word 0xc1100000 0800baa4 : * @param pSDstatus: Pointer to the buffer that will contain the SD card status * SD Status register) * @retval error state */ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { 800baa4: b580 push {r7, lr} 800baa6: b08c sub sp, #48 ; 0x30 800baa8: af00 add r7, sp, #0 800baaa: 6078 str r0, [r7, #4] 800baac: 6039 str r1, [r7, #0] SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); 800baae: f7f6 fc59 bl 8002364 800bab2: 6278 str r0, [r7, #36] ; 0x24 uint32_t count; uint32_t *pData = pSDstatus; 800bab4: 683b ldr r3, [r7, #0] 800bab6: 62bb str r3, [r7, #40] ; 0x28 /* Check SD response */ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) 800bab8: 687b ldr r3, [r7, #4] 800baba: 681b ldr r3, [r3, #0] 800babc: 2100 movs r1, #0 800babe: 4618 mov r0, r3 800bac0: f002 fa9b bl 800dffa 800bac4: 4603 mov r3, r0 800bac6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800baca: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800bace: d102 bne.n 800bad6 { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; 800bad0: f44f 6300 mov.w r3, #2048 ; 0x800 800bad4: e0b0 b.n 800bc38 } /* Set block size for card if it is not equal to current block size for card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); 800bad6: 687b ldr r3, [r7, #4] 800bad8: 681b ldr r3, [r3, #0] 800bada: 2140 movs r1, #64 ; 0x40 800badc: 4618 mov r0, r3 800bade: f002 facb bl 800e078 800bae2: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 800bae4: 6a3b ldr r3, [r7, #32] 800bae6: 2b00 cmp r3, #0 800bae8: d005 beq.n 800baf6 { hsd->ErrorCode |= HAL_SD_ERROR_NONE; 800baea: 687b ldr r3, [r7, #4] 800baec: 6b5a ldr r2, [r3, #52] ; 0x34 800baee: 687b ldr r3, [r7, #4] 800baf0: 635a str r2, [r3, #52] ; 0x34 return errorstate; 800baf2: 6a3b ldr r3, [r7, #32] 800baf4: e0a0 b.n 800bc38 } /* Send CMD55 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 800baf6: 687b ldr r3, [r7, #4] 800baf8: 681a ldr r2, [r3, #0] 800bafa: 687b ldr r3, [r7, #4] 800bafc: 6c5b ldr r3, [r3, #68] ; 0x44 800bafe: 041b lsls r3, r3, #16 800bb00: 4619 mov r1, r3 800bb02: 4610 mov r0, r2 800bb04: f002 fc05 bl 800e312 800bb08: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 800bb0a: 6a3b ldr r3, [r7, #32] 800bb0c: 2b00 cmp r3, #0 800bb0e: d005 beq.n 800bb1c { hsd->ErrorCode |= HAL_SD_ERROR_NONE; 800bb10: 687b ldr r3, [r7, #4] 800bb12: 6b5a ldr r2, [r3, #52] ; 0x34 800bb14: 687b ldr r3, [r7, #4] 800bb16: 635a str r2, [r3, #52] ; 0x34 return errorstate; 800bb18: 6a3b ldr r3, [r7, #32] 800bb1a: e08d b.n 800bc38 } /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; 800bb1c: f04f 33ff mov.w r3, #4294967295 800bb20: 60bb str r3, [r7, #8] config.DataLength = 64U; 800bb22: 2340 movs r3, #64 ; 0x40 800bb24: 60fb str r3, [r7, #12] config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; 800bb26: 2360 movs r3, #96 ; 0x60 800bb28: 613b str r3, [r7, #16] config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; 800bb2a: 2302 movs r3, #2 800bb2c: 617b str r3, [r7, #20] config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; 800bb2e: 2300 movs r3, #0 800bb30: 61bb str r3, [r7, #24] config.DPSM = SDMMC_DPSM_ENABLE; 800bb32: 2301 movs r3, #1 800bb34: 61fb str r3, [r7, #28] (void)SDMMC_ConfigData(hsd->Instance, &config); 800bb36: 687b ldr r3, [r7, #4] 800bb38: 681b ldr r3, [r3, #0] 800bb3a: f107 0208 add.w r2, r7, #8 800bb3e: 4611 mov r1, r2 800bb40: 4618 mov r0, r3 800bb42: f002 fa6d bl 800e020 /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ errorstate = SDMMC_CmdStatusRegister(hsd->Instance); 800bb46: 687b ldr r3, [r7, #4] 800bb48: 681b ldr r3, [r3, #0] 800bb4a: 4618 mov r0, r3 800bb4c: f002 fced bl 800e52a 800bb50: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 800bb52: 6a3b ldr r3, [r7, #32] 800bb54: 2b00 cmp r3, #0 800bb56: d02b beq.n 800bbb0 { hsd->ErrorCode |= HAL_SD_ERROR_NONE; 800bb58: 687b ldr r3, [r7, #4] 800bb5a: 6b5a ldr r2, [r3, #52] ; 0x34 800bb5c: 687b ldr r3, [r7, #4] 800bb5e: 635a str r2, [r3, #52] ; 0x34 return errorstate; 800bb60: 6a3b ldr r3, [r7, #32] 800bb62: e069 b.n 800bc38 } /* Get status data */ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) 800bb64: 687b ldr r3, [r7, #4] 800bb66: 681b ldr r3, [r3, #0] 800bb68: 6b5b ldr r3, [r3, #52] ; 0x34 800bb6a: f403 4300 and.w r3, r3, #32768 ; 0x8000 800bb6e: 2b00 cmp r3, #0 800bb70: d013 beq.n 800bb9a { for (count = 0U; count < 8U; count++) 800bb72: 2300 movs r3, #0 800bb74: 62fb str r3, [r7, #44] ; 0x2c 800bb76: e00d b.n 800bb94 { *pData = SDMMC_ReadFIFO(hsd->Instance); 800bb78: 687b ldr r3, [r7, #4] 800bb7a: 681b ldr r3, [r3, #0] 800bb7c: 4618 mov r0, r3 800bb7e: f002 f9c7 bl 800df10 800bb82: 4602 mov r2, r0 800bb84: 6abb ldr r3, [r7, #40] ; 0x28 800bb86: 601a str r2, [r3, #0] pData++; 800bb88: 6abb ldr r3, [r7, #40] ; 0x28 800bb8a: 3304 adds r3, #4 800bb8c: 62bb str r3, [r7, #40] ; 0x28 for (count = 0U; count < 8U; count++) 800bb8e: 6afb ldr r3, [r7, #44] ; 0x2c 800bb90: 3301 adds r3, #1 800bb92: 62fb str r3, [r7, #44] ; 0x2c 800bb94: 6afb ldr r3, [r7, #44] ; 0x2c 800bb96: 2b07 cmp r3, #7 800bb98: d9ee bls.n 800bb78 } } if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) 800bb9a: f7f6 fbe3 bl 8002364 800bb9e: 4602 mov r2, r0 800bba0: 6a7b ldr r3, [r7, #36] ; 0x24 800bba2: 1ad3 subs r3, r2, r3 800bba4: f1b3 3fff cmp.w r3, #4294967295 800bba8: d102 bne.n 800bbb0 { return HAL_SD_ERROR_TIMEOUT; 800bbaa: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800bbae: e043 b.n 800bc38 while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) 800bbb0: 687b ldr r3, [r7, #4] 800bbb2: 681b ldr r3, [r3, #0] 800bbb4: 6b5b ldr r3, [r3, #52] ; 0x34 800bbb6: f403 7395 and.w r3, r3, #298 ; 0x12a 800bbba: 2b00 cmp r3, #0 800bbbc: d0d2 beq.n 800bb64 } } if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) 800bbbe: 687b ldr r3, [r7, #4] 800bbc0: 681b ldr r3, [r3, #0] 800bbc2: 6b5b ldr r3, [r3, #52] ; 0x34 800bbc4: f003 0308 and.w r3, r3, #8 800bbc8: 2b00 cmp r3, #0 800bbca: d001 beq.n 800bbd0 { return HAL_SD_ERROR_DATA_TIMEOUT; 800bbcc: 2308 movs r3, #8 800bbce: e033 b.n 800bc38 } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) 800bbd0: 687b ldr r3, [r7, #4] 800bbd2: 681b ldr r3, [r3, #0] 800bbd4: 6b5b ldr r3, [r3, #52] ; 0x34 800bbd6: f003 0302 and.w r3, r3, #2 800bbda: 2b00 cmp r3, #0 800bbdc: d001 beq.n 800bbe2 { return HAL_SD_ERROR_DATA_CRC_FAIL; 800bbde: 2302 movs r3, #2 800bbe0: e02a b.n 800bc38 } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) 800bbe2: 687b ldr r3, [r7, #4] 800bbe4: 681b ldr r3, [r3, #0] 800bbe6: 6b5b ldr r3, [r3, #52] ; 0x34 800bbe8: f003 0320 and.w r3, r3, #32 800bbec: 2b00 cmp r3, #0 800bbee: d017 beq.n 800bc20 { return HAL_SD_ERROR_RX_OVERRUN; 800bbf0: 2320 movs r3, #32 800bbf2: e021 b.n 800bc38 /* Nothing to do */ } while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT))) { *pData = SDMMC_ReadFIFO(hsd->Instance); 800bbf4: 687b ldr r3, [r7, #4] 800bbf6: 681b ldr r3, [r3, #0] 800bbf8: 4618 mov r0, r3 800bbfa: f002 f989 bl 800df10 800bbfe: 4602 mov r2, r0 800bc00: 6abb ldr r3, [r7, #40] ; 0x28 800bc02: 601a str r2, [r3, #0] pData++; 800bc04: 6abb ldr r3, [r7, #40] ; 0x28 800bc06: 3304 adds r3, #4 800bc08: 62bb str r3, [r7, #40] ; 0x28 if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) 800bc0a: f7f6 fbab bl 8002364 800bc0e: 4602 mov r2, r0 800bc10: 6a7b ldr r3, [r7, #36] ; 0x24 800bc12: 1ad3 subs r3, r2, r3 800bc14: f1b3 3fff cmp.w r3, #4294967295 800bc18: d102 bne.n 800bc20 { return HAL_SD_ERROR_TIMEOUT; 800bc1a: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800bc1e: e00b b.n 800bc38 while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT))) 800bc20: 687b ldr r3, [r7, #4] 800bc22: 681b ldr r3, [r3, #0] 800bc24: 6b5b ldr r3, [r3, #52] ; 0x34 800bc26: f403 5380 and.w r3, r3, #4096 ; 0x1000 800bc2a: 2b00 cmp r3, #0 800bc2c: d1e2 bne.n 800bbf4 } } /* Clear all the static status flags*/ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); 800bc2e: 687b ldr r3, [r7, #4] 800bc30: 681b ldr r3, [r3, #0] 800bc32: 4a03 ldr r2, [pc, #12] ; (800bc40 ) 800bc34: 639a str r2, [r3, #56] ; 0x38 return HAL_SD_ERROR_NONE; 800bc36: 2300 movs r3, #0 } 800bc38: 4618 mov r0, r3 800bc3a: 3730 adds r7, #48 ; 0x30 800bc3c: 46bd mov sp, r7 800bc3e: bd80 pop {r7, pc} 800bc40: 18000f3a .word 0x18000f3a 0800bc44 : * @param pCardStatus: pointer to the buffer that will contain the SD card * status (Card Status register) * @retval error state */ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) { 800bc44: b580 push {r7, lr} 800bc46: b084 sub sp, #16 800bc48: af00 add r7, sp, #0 800bc4a: 6078 str r0, [r7, #4] 800bc4c: 6039 str r1, [r7, #0] uint32_t errorstate; if (pCardStatus == NULL) 800bc4e: 683b ldr r3, [r7, #0] 800bc50: 2b00 cmp r3, #0 800bc52: d102 bne.n 800bc5a { return HAL_SD_ERROR_PARAM; 800bc54: f04f 6300 mov.w r3, #134217728 ; 0x8000000 800bc58: e018 b.n 800bc8c } /* Send Status command */ errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 800bc5a: 687b ldr r3, [r7, #4] 800bc5c: 681a ldr r2, [r3, #0] 800bc5e: 687b ldr r3, [r7, #4] 800bc60: 6c5b ldr r3, [r3, #68] ; 0x44 800bc62: 041b lsls r3, r3, #16 800bc64: 4619 mov r1, r3 800bc66: 4610 mov r0, r2 800bc68: f002 fc3c bl 800e4e4 800bc6c: 60f8 str r0, [r7, #12] if (errorstate != HAL_SD_ERROR_NONE) 800bc6e: 68fb ldr r3, [r7, #12] 800bc70: 2b00 cmp r3, #0 800bc72: d001 beq.n 800bc78 { return errorstate; 800bc74: 68fb ldr r3, [r7, #12] 800bc76: e009 b.n 800bc8c } /* Get SD card status */ *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); 800bc78: 687b ldr r3, [r7, #4] 800bc7a: 681b ldr r3, [r3, #0] 800bc7c: 2100 movs r1, #0 800bc7e: 4618 mov r0, r3 800bc80: f002 f9bb bl 800dffa 800bc84: 4602 mov r2, r0 800bc86: 683b ldr r3, [r7, #0] 800bc88: 601a str r2, [r3, #0] return HAL_SD_ERROR_NONE; 800bc8a: 2300 movs r3, #0 } 800bc8c: 4618 mov r0, r3 800bc8e: 3710 adds r7, #16 800bc90: 46bd mov sp, r7 800bc92: bd80 pop {r7, pc} 0800bc94 : * @brief Enables the SDMMC wide bus mode. * @param hsd: pointer to SD handle * @retval error state */ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { 800bc94: b580 push {r7, lr} 800bc96: b086 sub sp, #24 800bc98: af00 add r7, sp, #0 800bc9a: 6078 str r0, [r7, #4] uint32_t scr[2U] = {0UL, 0UL}; 800bc9c: 2300 movs r3, #0 800bc9e: 60fb str r3, [r7, #12] 800bca0: 2300 movs r3, #0 800bca2: 613b str r3, [r7, #16] uint32_t errorstate; if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) 800bca4: 687b ldr r3, [r7, #4] 800bca6: 681b ldr r3, [r3, #0] 800bca8: 2100 movs r1, #0 800bcaa: 4618 mov r0, r3 800bcac: f002 f9a5 bl 800dffa 800bcb0: 4603 mov r3, r0 800bcb2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800bcb6: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800bcba: d102 bne.n 800bcc2 { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; 800bcbc: f44f 6300 mov.w r3, #2048 ; 0x800 800bcc0: e02f b.n 800bd22 } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); 800bcc2: f107 030c add.w r3, r7, #12 800bcc6: 4619 mov r1, r3 800bcc8: 6878 ldr r0, [r7, #4] 800bcca: f000 f879 bl 800bdc0 800bcce: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800bcd0: 697b ldr r3, [r7, #20] 800bcd2: 2b00 cmp r3, #0 800bcd4: d001 beq.n 800bcda { return errorstate; 800bcd6: 697b ldr r3, [r7, #20] 800bcd8: e023 b.n 800bd22 } /* If requested card supports wide bus operation */ if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) 800bcda: 693b ldr r3, [r7, #16] 800bcdc: f403 2380 and.w r3, r3, #262144 ; 0x40000 800bce0: 2b00 cmp r3, #0 800bce2: d01c beq.n 800bd1e { /* Send CMD55 APP_CMD with argument as card's RCA.*/ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 800bce4: 687b ldr r3, [r7, #4] 800bce6: 681a ldr r2, [r3, #0] 800bce8: 687b ldr r3, [r7, #4] 800bcea: 6c5b ldr r3, [r3, #68] ; 0x44 800bcec: 041b lsls r3, r3, #16 800bcee: 4619 mov r1, r3 800bcf0: 4610 mov r0, r2 800bcf2: f002 fb0e bl 800e312 800bcf6: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800bcf8: 697b ldr r3, [r7, #20] 800bcfa: 2b00 cmp r3, #0 800bcfc: d001 beq.n 800bd02 { return errorstate; 800bcfe: 697b ldr r3, [r7, #20] 800bd00: e00f b.n 800bd22 } /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); 800bd02: 687b ldr r3, [r7, #4] 800bd04: 681b ldr r3, [r3, #0] 800bd06: 2102 movs r1, #2 800bd08: 4618 mov r0, r3 800bd0a: f002 fb45 bl 800e398 800bd0e: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800bd10: 697b ldr r3, [r7, #20] 800bd12: 2b00 cmp r3, #0 800bd14: d001 beq.n 800bd1a { return errorstate; 800bd16: 697b ldr r3, [r7, #20] 800bd18: e003 b.n 800bd22 } return HAL_SD_ERROR_NONE; 800bd1a: 2300 movs r3, #0 800bd1c: e001 b.n 800bd22 } else { return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; 800bd1e: f04f 6380 mov.w r3, #67108864 ; 0x4000000 } } 800bd22: 4618 mov r0, r3 800bd24: 3718 adds r7, #24 800bd26: 46bd mov sp, r7 800bd28: bd80 pop {r7, pc} 0800bd2a : * @brief Disables the SDMMC wide bus mode. * @param hsd: Pointer to SD handle * @retval error state */ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { 800bd2a: b580 push {r7, lr} 800bd2c: b086 sub sp, #24 800bd2e: af00 add r7, sp, #0 800bd30: 6078 str r0, [r7, #4] uint32_t scr[2U] = {0UL, 0UL}; 800bd32: 2300 movs r3, #0 800bd34: 60fb str r3, [r7, #12] 800bd36: 2300 movs r3, #0 800bd38: 613b str r3, [r7, #16] uint32_t errorstate; if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) 800bd3a: 687b ldr r3, [r7, #4] 800bd3c: 681b ldr r3, [r3, #0] 800bd3e: 2100 movs r1, #0 800bd40: 4618 mov r0, r3 800bd42: f002 f95a bl 800dffa 800bd46: 4603 mov r3, r0 800bd48: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800bd4c: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800bd50: d102 bne.n 800bd58 { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; 800bd52: f44f 6300 mov.w r3, #2048 ; 0x800 800bd56: e02f b.n 800bdb8 } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); 800bd58: f107 030c add.w r3, r7, #12 800bd5c: 4619 mov r1, r3 800bd5e: 6878 ldr r0, [r7, #4] 800bd60: f000 f82e bl 800bdc0 800bd64: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800bd66: 697b ldr r3, [r7, #20] 800bd68: 2b00 cmp r3, #0 800bd6a: d001 beq.n 800bd70 { return errorstate; 800bd6c: 697b ldr r3, [r7, #20] 800bd6e: e023 b.n 800bdb8 } /* If requested card supports 1 bit mode operation */ if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) 800bd70: 693b ldr r3, [r7, #16] 800bd72: f403 3380 and.w r3, r3, #65536 ; 0x10000 800bd76: 2b00 cmp r3, #0 800bd78: d01c beq.n 800bdb4 { /* Send CMD55 APP_CMD with argument as card's RCA */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 800bd7a: 687b ldr r3, [r7, #4] 800bd7c: 681a ldr r2, [r3, #0] 800bd7e: 687b ldr r3, [r7, #4] 800bd80: 6c5b ldr r3, [r3, #68] ; 0x44 800bd82: 041b lsls r3, r3, #16 800bd84: 4619 mov r1, r3 800bd86: 4610 mov r0, r2 800bd88: f002 fac3 bl 800e312 800bd8c: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800bd8e: 697b ldr r3, [r7, #20] 800bd90: 2b00 cmp r3, #0 800bd92: d001 beq.n 800bd98 { return errorstate; 800bd94: 697b ldr r3, [r7, #20] 800bd96: e00f b.n 800bdb8 } /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); 800bd98: 687b ldr r3, [r7, #4] 800bd9a: 681b ldr r3, [r3, #0] 800bd9c: 2100 movs r1, #0 800bd9e: 4618 mov r0, r3 800bda0: f002 fafa bl 800e398 800bda4: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800bda6: 697b ldr r3, [r7, #20] 800bda8: 2b00 cmp r3, #0 800bdaa: d001 beq.n 800bdb0 { return errorstate; 800bdac: 697b ldr r3, [r7, #20] 800bdae: e003 b.n 800bdb8 } return HAL_SD_ERROR_NONE; 800bdb0: 2300 movs r3, #0 800bdb2: e001 b.n 800bdb8 } else { return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; 800bdb4: f04f 6380 mov.w r3, #67108864 ; 0x4000000 } } 800bdb8: 4618 mov r0, r3 800bdba: 3718 adds r7, #24 800bdbc: 46bd mov sp, r7 800bdbe: bd80 pop {r7, pc} 0800bdc0 : * @param hsd: Pointer to SD handle * @param pSCR: pointer to the buffer that will contain the SCR value * @retval error state */ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { 800bdc0: b580 push {r7, lr} 800bdc2: b08e sub sp, #56 ; 0x38 800bdc4: af00 add r7, sp, #0 800bdc6: 6078 str r0, [r7, #4] 800bdc8: 6039 str r1, [r7, #0] SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); 800bdca: f7f6 facb bl 8002364 800bdce: 6338 str r0, [r7, #48] ; 0x30 uint32_t index = 0U; 800bdd0: 2300 movs r3, #0 800bdd2: 637b str r3, [r7, #52] ; 0x34 uint32_t tempscr[2U] = {0UL, 0UL}; 800bdd4: 2300 movs r3, #0 800bdd6: 60bb str r3, [r7, #8] 800bdd8: 2300 movs r3, #0 800bdda: 60fb str r3, [r7, #12] uint32_t *scr = pSCR; 800bddc: 683b ldr r3, [r7, #0] 800bdde: 62fb str r3, [r7, #44] ; 0x2c /* Set Block Size To 8 Bytes */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); 800bde0: 687b ldr r3, [r7, #4] 800bde2: 681b ldr r3, [r3, #0] 800bde4: 2108 movs r1, #8 800bde6: 4618 mov r0, r3 800bde8: f002 f946 bl 800e078 800bdec: 62b8 str r0, [r7, #40] ; 0x28 if (errorstate != HAL_SD_ERROR_NONE) 800bdee: 6abb ldr r3, [r7, #40] ; 0x28 800bdf0: 2b00 cmp r3, #0 800bdf2: d001 beq.n 800bdf8 { return errorstate; 800bdf4: 6abb ldr r3, [r7, #40] ; 0x28 800bdf6: e0ad b.n 800bf54 } /* Send CMD55 APP_CMD with argument as card's RCA */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); 800bdf8: 687b ldr r3, [r7, #4] 800bdfa: 681a ldr r2, [r3, #0] 800bdfc: 687b ldr r3, [r7, #4] 800bdfe: 6c5b ldr r3, [r3, #68] ; 0x44 800be00: 041b lsls r3, r3, #16 800be02: 4619 mov r1, r3 800be04: 4610 mov r0, r2 800be06: f002 fa84 bl 800e312 800be0a: 62b8 str r0, [r7, #40] ; 0x28 if (errorstate != HAL_SD_ERROR_NONE) 800be0c: 6abb ldr r3, [r7, #40] ; 0x28 800be0e: 2b00 cmp r3, #0 800be10: d001 beq.n 800be16 { return errorstate; 800be12: 6abb ldr r3, [r7, #40] ; 0x28 800be14: e09e b.n 800bf54 } config.DataTimeOut = SDMMC_DATATIMEOUT; 800be16: f04f 33ff mov.w r3, #4294967295 800be1a: 613b str r3, [r7, #16] config.DataLength = 8U; 800be1c: 2308 movs r3, #8 800be1e: 617b str r3, [r7, #20] config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; 800be20: 2330 movs r3, #48 ; 0x30 800be22: 61bb str r3, [r7, #24] config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; 800be24: 2302 movs r3, #2 800be26: 61fb str r3, [r7, #28] config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; 800be28: 2300 movs r3, #0 800be2a: 623b str r3, [r7, #32] config.DPSM = SDMMC_DPSM_ENABLE; 800be2c: 2301 movs r3, #1 800be2e: 627b str r3, [r7, #36] ; 0x24 (void)SDMMC_ConfigData(hsd->Instance, &config); 800be30: 687b ldr r3, [r7, #4] 800be32: 681b ldr r3, [r3, #0] 800be34: f107 0210 add.w r2, r7, #16 800be38: 4611 mov r1, r2 800be3a: 4618 mov r0, r3 800be3c: f002 f8f0 bl 800e020 /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ errorstate = SDMMC_CmdSendSCR(hsd->Instance); 800be40: 687b ldr r3, [r7, #4] 800be42: 681b ldr r3, [r3, #0] 800be44: 4618 mov r0, r3 800be46: f002 faca bl 800e3de 800be4a: 62b8 str r0, [r7, #40] ; 0x28 if (errorstate != HAL_SD_ERROR_NONE) 800be4c: 6abb ldr r3, [r7, #40] ; 0x28 800be4e: 2b00 cmp r3, #0 800be50: d027 beq.n 800bea2 { return errorstate; 800be52: 6abb ldr r3, [r7, #40] ; 0x28 800be54: e07e b.n 800bf54 } while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND)) { if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U)) 800be56: 687b ldr r3, [r7, #4] 800be58: 681b ldr r3, [r3, #0] 800be5a: 6b5b ldr r3, [r3, #52] ; 0x34 800be5c: f403 2300 and.w r3, r3, #524288 ; 0x80000 800be60: 2b00 cmp r3, #0 800be62: d113 bne.n 800be8c 800be64: 6b7b ldr r3, [r7, #52] ; 0x34 800be66: 2b00 cmp r3, #0 800be68: d110 bne.n 800be8c { tempscr[0] = SDMMC_ReadFIFO(hsd->Instance); 800be6a: 687b ldr r3, [r7, #4] 800be6c: 681b ldr r3, [r3, #0] 800be6e: 4618 mov r0, r3 800be70: f002 f84e bl 800df10 800be74: 4603 mov r3, r0 800be76: 60bb str r3, [r7, #8] tempscr[1] = SDMMC_ReadFIFO(hsd->Instance); 800be78: 687b ldr r3, [r7, #4] 800be7a: 681b ldr r3, [r3, #0] 800be7c: 4618 mov r0, r3 800be7e: f002 f847 bl 800df10 800be82: 4603 mov r3, r0 800be84: 60fb str r3, [r7, #12] index++; 800be86: 6b7b ldr r3, [r7, #52] ; 0x34 800be88: 3301 adds r3, #1 800be8a: 637b str r3, [r7, #52] ; 0x34 } if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) 800be8c: f7f6 fa6a bl 8002364 800be90: 4602 mov r2, r0 800be92: 6b3b ldr r3, [r7, #48] ; 0x30 800be94: 1ad3 subs r3, r2, r3 800be96: f1b3 3fff cmp.w r3, #4294967295 800be9a: d102 bne.n 800bea2 { return HAL_SD_ERROR_TIMEOUT; 800be9c: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800bea0: e058 b.n 800bf54 while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | 800bea2: 687b ldr r3, [r7, #4] 800bea4: 681b ldr r3, [r3, #0] 800bea6: 6b5a ldr r2, [r3, #52] ; 0x34 800bea8: f240 532a movw r3, #1322 ; 0x52a 800beac: 4013 ands r3, r2 800beae: 2b00 cmp r3, #0 800beb0: d0d1 beq.n 800be56 } } if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) 800beb2: 687b ldr r3, [r7, #4] 800beb4: 681b ldr r3, [r3, #0] 800beb6: 6b5b ldr r3, [r3, #52] ; 0x34 800beb8: f003 0308 and.w r3, r3, #8 800bebc: 2b00 cmp r3, #0 800bebe: d005 beq.n 800becc { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); 800bec0: 687b ldr r3, [r7, #4] 800bec2: 681b ldr r3, [r3, #0] 800bec4: 2208 movs r2, #8 800bec6: 639a str r2, [r3, #56] ; 0x38 return HAL_SD_ERROR_DATA_TIMEOUT; 800bec8: 2308 movs r3, #8 800beca: e043 b.n 800bf54 } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) 800becc: 687b ldr r3, [r7, #4] 800bece: 681b ldr r3, [r3, #0] 800bed0: 6b5b ldr r3, [r3, #52] ; 0x34 800bed2: f003 0302 and.w r3, r3, #2 800bed6: 2b00 cmp r3, #0 800bed8: d005 beq.n 800bee6 { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); 800beda: 687b ldr r3, [r7, #4] 800bedc: 681b ldr r3, [r3, #0] 800bede: 2202 movs r2, #2 800bee0: 639a str r2, [r3, #56] ; 0x38 return HAL_SD_ERROR_DATA_CRC_FAIL; 800bee2: 2302 movs r3, #2 800bee4: e036 b.n 800bf54 } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) 800bee6: 687b ldr r3, [r7, #4] 800bee8: 681b ldr r3, [r3, #0] 800beea: 6b5b ldr r3, [r3, #52] ; 0x34 800beec: f003 0320 and.w r3, r3, #32 800bef0: 2b00 cmp r3, #0 800bef2: d005 beq.n 800bf00 { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); 800bef4: 687b ldr r3, [r7, #4] 800bef6: 681b ldr r3, [r3, #0] 800bef8: 2220 movs r2, #32 800befa: 639a str r2, [r3, #56] ; 0x38 return HAL_SD_ERROR_RX_OVERRUN; 800befc: 2320 movs r3, #32 800befe: e029 b.n 800bf54 } else { /* No error flag set */ /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); 800bf00: 687b ldr r3, [r7, #4] 800bf02: 681b ldr r3, [r3, #0] 800bf04: 4a15 ldr r2, [pc, #84] ; (800bf5c ) 800bf06: 639a str r2, [r3, #56] ; 0x38 *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ 800bf08: 68fb ldr r3, [r7, #12] 800bf0a: 061a lsls r2, r3, #24 800bf0c: 68fb ldr r3, [r7, #12] 800bf0e: 021b lsls r3, r3, #8 800bf10: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800bf14: 431a orrs r2, r3 ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); 800bf16: 68fb ldr r3, [r7, #12] 800bf18: 0a1b lsrs r3, r3, #8 800bf1a: f403 437f and.w r3, r3, #65280 ; 0xff00 *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ 800bf1e: 431a orrs r2, r3 ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); 800bf20: 68fb ldr r3, [r7, #12] 800bf22: 0e1b lsrs r3, r3, #24 800bf24: 431a orrs r2, r3 *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ 800bf26: 6afb ldr r3, [r7, #44] ; 0x2c 800bf28: 601a str r2, [r3, #0] scr++; 800bf2a: 6afb ldr r3, [r7, #44] ; 0x2c 800bf2c: 3304 adds r3, #4 800bf2e: 62fb str r3, [r7, #44] ; 0x2c *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ 800bf30: 68bb ldr r3, [r7, #8] 800bf32: 061a lsls r2, r3, #24 800bf34: 68bb ldr r3, [r7, #8] 800bf36: 021b lsls r3, r3, #8 800bf38: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800bf3c: 431a orrs r2, r3 ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); 800bf3e: 68bb ldr r3, [r7, #8] 800bf40: 0a1b lsrs r3, r3, #8 800bf42: f403 437f and.w r3, r3, #65280 ; 0xff00 *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ 800bf46: 431a orrs r2, r3 ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); 800bf48: 68bb ldr r3, [r7, #8] 800bf4a: 0e1b lsrs r3, r3, #24 800bf4c: 431a orrs r2, r3 *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ 800bf4e: 6afb ldr r3, [r7, #44] ; 0x2c 800bf50: 601a str r2, [r3, #0] } return HAL_SD_ERROR_NONE; 800bf52: 2300 movs r3, #0 } 800bf54: 4618 mov r0, r3 800bf56: 3738 adds r7, #56 ; 0x38 800bf58: 46bd mov sp, r7 800bf5a: bd80 pop {r7, pc} 800bf5c: 18000f3a .word 0x18000f3a 0800bf60 : * @param hsd: pointer to a SD_HandleTypeDef structure that contains * the configuration information. * @retval None */ static void SD_Read_IT(SD_HandleTypeDef *hsd) { 800bf60: b580 push {r7, lr} 800bf62: b086 sub sp, #24 800bf64: af00 add r7, sp, #0 800bf66: 6078 str r0, [r7, #4] uint32_t count; uint32_t data; uint8_t *tmp; tmp = hsd->pRxBuffPtr; 800bf68: 687b ldr r3, [r7, #4] 800bf6a: 6a5b ldr r3, [r3, #36] ; 0x24 800bf6c: 613b str r3, [r7, #16] if (hsd->RxXferSize >= 32U) 800bf6e: 687b ldr r3, [r7, #4] 800bf70: 6a9b ldr r3, [r3, #40] ; 0x28 800bf72: 2b1f cmp r3, #31 800bf74: d936 bls.n 800bfe4 { /* Read data from SDMMC Rx FIFO */ for (count = 0U; count < 8U; count++) 800bf76: 2300 movs r3, #0 800bf78: 617b str r3, [r7, #20] 800bf7a: e027 b.n 800bfcc { data = SDMMC_ReadFIFO(hsd->Instance); 800bf7c: 687b ldr r3, [r7, #4] 800bf7e: 681b ldr r3, [r3, #0] 800bf80: 4618 mov r0, r3 800bf82: f001 ffc5 bl 800df10 800bf86: 60f8 str r0, [r7, #12] *tmp = (uint8_t)(data & 0xFFU); 800bf88: 68fb ldr r3, [r7, #12] 800bf8a: b2da uxtb r2, r3 800bf8c: 693b ldr r3, [r7, #16] 800bf8e: 701a strb r2, [r3, #0] tmp++; 800bf90: 693b ldr r3, [r7, #16] 800bf92: 3301 adds r3, #1 800bf94: 613b str r3, [r7, #16] *tmp = (uint8_t)((data >> 8U) & 0xFFU); 800bf96: 68fb ldr r3, [r7, #12] 800bf98: 0a1b lsrs r3, r3, #8 800bf9a: b2da uxtb r2, r3 800bf9c: 693b ldr r3, [r7, #16] 800bf9e: 701a strb r2, [r3, #0] tmp++; 800bfa0: 693b ldr r3, [r7, #16] 800bfa2: 3301 adds r3, #1 800bfa4: 613b str r3, [r7, #16] *tmp = (uint8_t)((data >> 16U) & 0xFFU); 800bfa6: 68fb ldr r3, [r7, #12] 800bfa8: 0c1b lsrs r3, r3, #16 800bfaa: b2da uxtb r2, r3 800bfac: 693b ldr r3, [r7, #16] 800bfae: 701a strb r2, [r3, #0] tmp++; 800bfb0: 693b ldr r3, [r7, #16] 800bfb2: 3301 adds r3, #1 800bfb4: 613b str r3, [r7, #16] *tmp = (uint8_t)((data >> 24U) & 0xFFU); 800bfb6: 68fb ldr r3, [r7, #12] 800bfb8: 0e1b lsrs r3, r3, #24 800bfba: b2da uxtb r2, r3 800bfbc: 693b ldr r3, [r7, #16] 800bfbe: 701a strb r2, [r3, #0] tmp++; 800bfc0: 693b ldr r3, [r7, #16] 800bfc2: 3301 adds r3, #1 800bfc4: 613b str r3, [r7, #16] for (count = 0U; count < 8U; count++) 800bfc6: 697b ldr r3, [r7, #20] 800bfc8: 3301 adds r3, #1 800bfca: 617b str r3, [r7, #20] 800bfcc: 697b ldr r3, [r7, #20] 800bfce: 2b07 cmp r3, #7 800bfd0: d9d4 bls.n 800bf7c } hsd->pRxBuffPtr = tmp; 800bfd2: 687b ldr r3, [r7, #4] 800bfd4: 693a ldr r2, [r7, #16] 800bfd6: 625a str r2, [r3, #36] ; 0x24 hsd->RxXferSize -= 32U; 800bfd8: 687b ldr r3, [r7, #4] 800bfda: 6a9b ldr r3, [r3, #40] ; 0x28 800bfdc: f1a3 0220 sub.w r2, r3, #32 800bfe0: 687b ldr r3, [r7, #4] 800bfe2: 629a str r2, [r3, #40] ; 0x28 } } 800bfe4: bf00 nop 800bfe6: 3718 adds r7, #24 800bfe8: 46bd mov sp, r7 800bfea: bd80 pop {r7, pc} 0800bfec : * @param hsd: pointer to a SD_HandleTypeDef structure that contains * the configuration information. * @retval None */ static void SD_Write_IT(SD_HandleTypeDef *hsd) { 800bfec: b580 push {r7, lr} 800bfee: b086 sub sp, #24 800bff0: af00 add r7, sp, #0 800bff2: 6078 str r0, [r7, #4] uint32_t count; uint32_t data; const uint8_t *tmp; tmp = hsd->pTxBuffPtr; 800bff4: 687b ldr r3, [r7, #4] 800bff6: 69db ldr r3, [r3, #28] 800bff8: 613b str r3, [r7, #16] if (hsd->TxXferSize >= 32U) 800bffa: 687b ldr r3, [r7, #4] 800bffc: 6a1b ldr r3, [r3, #32] 800bffe: 2b1f cmp r3, #31 800c000: d93a bls.n 800c078 { /* Write data to SDMMC Tx FIFO */ for (count = 0U; count < 8U; count++) 800c002: 2300 movs r3, #0 800c004: 617b str r3, [r7, #20] 800c006: e02b b.n 800c060 { data = (uint32_t)(*tmp); 800c008: 693b ldr r3, [r7, #16] 800c00a: 781b ldrb r3, [r3, #0] 800c00c: 60fb str r3, [r7, #12] tmp++; 800c00e: 693b ldr r3, [r7, #16] 800c010: 3301 adds r3, #1 800c012: 613b str r3, [r7, #16] data |= ((uint32_t)(*tmp) << 8U); 800c014: 693b ldr r3, [r7, #16] 800c016: 781b ldrb r3, [r3, #0] 800c018: 021a lsls r2, r3, #8 800c01a: 68fb ldr r3, [r7, #12] 800c01c: 4313 orrs r3, r2 800c01e: 60fb str r3, [r7, #12] tmp++; 800c020: 693b ldr r3, [r7, #16] 800c022: 3301 adds r3, #1 800c024: 613b str r3, [r7, #16] data |= ((uint32_t)(*tmp) << 16U); 800c026: 693b ldr r3, [r7, #16] 800c028: 781b ldrb r3, [r3, #0] 800c02a: 041a lsls r2, r3, #16 800c02c: 68fb ldr r3, [r7, #12] 800c02e: 4313 orrs r3, r2 800c030: 60fb str r3, [r7, #12] tmp++; 800c032: 693b ldr r3, [r7, #16] 800c034: 3301 adds r3, #1 800c036: 613b str r3, [r7, #16] data |= ((uint32_t)(*tmp) << 24U); 800c038: 693b ldr r3, [r7, #16] 800c03a: 781b ldrb r3, [r3, #0] 800c03c: 061a lsls r2, r3, #24 800c03e: 68fb ldr r3, [r7, #12] 800c040: 4313 orrs r3, r2 800c042: 60fb str r3, [r7, #12] tmp++; 800c044: 693b ldr r3, [r7, #16] 800c046: 3301 adds r3, #1 800c048: 613b str r3, [r7, #16] (void)SDMMC_WriteFIFO(hsd->Instance, &data); 800c04a: 687b ldr r3, [r7, #4] 800c04c: 681b ldr r3, [r3, #0] 800c04e: f107 020c add.w r2, r7, #12 800c052: 4611 mov r1, r2 800c054: 4618 mov r0, r3 800c056: f001 ff68 bl 800df2a for (count = 0U; count < 8U; count++) 800c05a: 697b ldr r3, [r7, #20] 800c05c: 3301 adds r3, #1 800c05e: 617b str r3, [r7, #20] 800c060: 697b ldr r3, [r7, #20] 800c062: 2b07 cmp r3, #7 800c064: d9d0 bls.n 800c008 } hsd->pTxBuffPtr = tmp; 800c066: 687b ldr r3, [r7, #4] 800c068: 693a ldr r2, [r7, #16] 800c06a: 61da str r2, [r3, #28] hsd->TxXferSize -= 32U; 800c06c: 687b ldr r3, [r7, #4] 800c06e: 6a1b ldr r3, [r3, #32] 800c070: f1a3 0220 sub.w r2, r3, #32 800c074: 687b ldr r3, [r7, #4] 800c076: 621a str r2, [r3, #32] } } 800c078: bf00 nop 800c07a: 3718 adds r7, #24 800c07c: 46bd mov sp, r7 800c07e: bd80 pop {r7, pc} 0800c080 : * @brief Read DMA Buffer 0 Transfer completed callbacks * @param hsd: SD handle * @retval None */ __weak void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd) { 800c080: b480 push {r7} 800c082: b083 sub sp, #12 800c084: af00 add r7, sp, #0 800c086: 6078 str r0, [r7, #4] UNUSED(hsd); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SDEx_Read_DMADoubleBuf0CpltCallback can be implemented in the user file */ } 800c088: bf00 nop 800c08a: 370c adds r7, #12 800c08c: 46bd mov sp, r7 800c08e: f85d 7b04 ldr.w r7, [sp], #4 800c092: 4770 bx lr 0800c094 : * @brief Read DMA Buffer 1 Transfer completed callbacks * @param hsd: SD handle * @retval None */ __weak void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd) { 800c094: b480 push {r7} 800c096: b083 sub sp, #12 800c098: af00 add r7, sp, #0 800c09a: 6078 str r0, [r7, #4] UNUSED(hsd); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SDEx_Read_DMADoubleBuf1CpltCallback can be implemented in the user file */ } 800c09c: bf00 nop 800c09e: 370c adds r7, #12 800c0a0: 46bd mov sp, r7 800c0a2: f85d 7b04 ldr.w r7, [sp], #4 800c0a6: 4770 bx lr 0800c0a8 : * @brief Write DMA Buffer 0 Transfer completed callbacks * @param hsd: SD handle * @retval None */ __weak void HAL_SDEx_Write_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd) { 800c0a8: b480 push {r7} 800c0aa: b083 sub sp, #12 800c0ac: af00 add r7, sp, #0 800c0ae: 6078 str r0, [r7, #4] UNUSED(hsd); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SDEx_Write_DMADoubleBuf0CpltCallback can be implemented in the user file */ } 800c0b0: bf00 nop 800c0b2: 370c adds r7, #12 800c0b4: 46bd mov sp, r7 800c0b6: f85d 7b04 ldr.w r7, [sp], #4 800c0ba: 4770 bx lr 0800c0bc : * @brief Write DMA Buffer 1 Transfer completed callbacks * @param hsd: SD handle * @retval None */ __weak void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd) { 800c0bc: b480 push {r7} 800c0be: b083 sub sp, #12 800c0c0: af00 add r7, sp, #0 800c0c2: 6078 str r0, [r7, #4] UNUSED(hsd); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SDEx_Write_DMADoubleBuf1CpltCallback can be implemented in the user file */ } 800c0c4: bf00 nop 800c0c6: 370c adds r7, #12 800c0c8: 46bd mov sp, r7 800c0ca: f85d 7b04 ldr.w r7, [sp], #4 800c0ce: 4770 bx lr 0800c0d0 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800c0d0: b580 push {r7, lr} 800c0d2: b082 sub sp, #8 800c0d4: af00 add r7, sp, #0 800c0d6: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800c0d8: 687b ldr r3, [r7, #4] 800c0da: 2b00 cmp r3, #0 800c0dc: d101 bne.n 800c0e2 { return HAL_ERROR; 800c0de: 2301 movs r3, #1 800c0e0: e049 b.n 800c176 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800c0e2: 687b ldr r3, [r7, #4] 800c0e4: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 800c0e8: b2db uxtb r3, r3 800c0ea: 2b00 cmp r3, #0 800c0ec: d106 bne.n 800c0fc { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800c0ee: 687b ldr r3, [r7, #4] 800c0f0: 2200 movs r2, #0 800c0f2: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800c0f6: 6878 ldr r0, [r7, #4] 800c0f8: f7f5 fbf6 bl 80018e8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800c0fc: 687b ldr r3, [r7, #4] 800c0fe: 2202 movs r2, #2 800c100: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800c104: 687b ldr r3, [r7, #4] 800c106: 681a ldr r2, [r3, #0] 800c108: 687b ldr r3, [r7, #4] 800c10a: 3304 adds r3, #4 800c10c: 4619 mov r1, r3 800c10e: 4610 mov r0, r2 800c110: f000 fafc bl 800c70c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800c114: 687b ldr r3, [r7, #4] 800c116: 2201 movs r2, #1 800c118: f883 2048 strb.w r2, [r3, #72] ; 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800c11c: 687b ldr r3, [r7, #4] 800c11e: 2201 movs r2, #1 800c120: f883 203e strb.w r2, [r3, #62] ; 0x3e 800c124: 687b ldr r3, [r7, #4] 800c126: 2201 movs r2, #1 800c128: f883 203f strb.w r2, [r3, #63] ; 0x3f 800c12c: 687b ldr r3, [r7, #4] 800c12e: 2201 movs r2, #1 800c130: f883 2040 strb.w r2, [r3, #64] ; 0x40 800c134: 687b ldr r3, [r7, #4] 800c136: 2201 movs r2, #1 800c138: f883 2041 strb.w r2, [r3, #65] ; 0x41 800c13c: 687b ldr r3, [r7, #4] 800c13e: 2201 movs r2, #1 800c140: f883 2042 strb.w r2, [r3, #66] ; 0x42 800c144: 687b ldr r3, [r7, #4] 800c146: 2201 movs r2, #1 800c148: f883 2043 strb.w r2, [r3, #67] ; 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800c14c: 687b ldr r3, [r7, #4] 800c14e: 2201 movs r2, #1 800c150: f883 2044 strb.w r2, [r3, #68] ; 0x44 800c154: 687b ldr r3, [r7, #4] 800c156: 2201 movs r2, #1 800c158: f883 2045 strb.w r2, [r3, #69] ; 0x45 800c15c: 687b ldr r3, [r7, #4] 800c15e: 2201 movs r2, #1 800c160: f883 2046 strb.w r2, [r3, #70] ; 0x46 800c164: 687b ldr r3, [r7, #4] 800c166: 2201 movs r2, #1 800c168: f883 2047 strb.w r2, [r3, #71] ; 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800c16c: 687b ldr r3, [r7, #4] 800c16e: 2201 movs r2, #1 800c170: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 800c174: 2300 movs r3, #0 } 800c176: 4618 mov r0, r3 800c178: 3708 adds r7, #8 800c17a: 46bd mov sp, r7 800c17c: bd80 pop {r7, pc} ... 0800c180 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800c180: b480 push {r7} 800c182: b085 sub sp, #20 800c184: af00 add r7, sp, #0 800c186: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800c188: 687b ldr r3, [r7, #4] 800c18a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 800c18e: b2db uxtb r3, r3 800c190: 2b01 cmp r3, #1 800c192: d001 beq.n 800c198 { return HAL_ERROR; 800c194: 2301 movs r3, #1 800c196: e05e b.n 800c256 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800c198: 687b ldr r3, [r7, #4] 800c19a: 2202 movs r2, #2 800c19c: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800c1a0: 687b ldr r3, [r7, #4] 800c1a2: 681b ldr r3, [r3, #0] 800c1a4: 68da ldr r2, [r3, #12] 800c1a6: 687b ldr r3, [r7, #4] 800c1a8: 681b ldr r3, [r3, #0] 800c1aa: f042 0201 orr.w r2, r2, #1 800c1ae: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800c1b0: 687b ldr r3, [r7, #4] 800c1b2: 681b ldr r3, [r3, #0] 800c1b4: 4a2b ldr r2, [pc, #172] ; (800c264 ) 800c1b6: 4293 cmp r3, r2 800c1b8: d02c beq.n 800c214 800c1ba: 687b ldr r3, [r7, #4] 800c1bc: 681b ldr r3, [r3, #0] 800c1be: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800c1c2: d027 beq.n 800c214 800c1c4: 687b ldr r3, [r7, #4] 800c1c6: 681b ldr r3, [r3, #0] 800c1c8: 4a27 ldr r2, [pc, #156] ; (800c268 ) 800c1ca: 4293 cmp r3, r2 800c1cc: d022 beq.n 800c214 800c1ce: 687b ldr r3, [r7, #4] 800c1d0: 681b ldr r3, [r3, #0] 800c1d2: 4a26 ldr r2, [pc, #152] ; (800c26c ) 800c1d4: 4293 cmp r3, r2 800c1d6: d01d beq.n 800c214 800c1d8: 687b ldr r3, [r7, #4] 800c1da: 681b ldr r3, [r3, #0] 800c1dc: 4a24 ldr r2, [pc, #144] ; (800c270 ) 800c1de: 4293 cmp r3, r2 800c1e0: d018 beq.n 800c214 800c1e2: 687b ldr r3, [r7, #4] 800c1e4: 681b ldr r3, [r3, #0] 800c1e6: 4a23 ldr r2, [pc, #140] ; (800c274 ) 800c1e8: 4293 cmp r3, r2 800c1ea: d013 beq.n 800c214 800c1ec: 687b ldr r3, [r7, #4] 800c1ee: 681b ldr r3, [r3, #0] 800c1f0: 4a21 ldr r2, [pc, #132] ; (800c278 ) 800c1f2: 4293 cmp r3, r2 800c1f4: d00e beq.n 800c214 800c1f6: 687b ldr r3, [r7, #4] 800c1f8: 681b ldr r3, [r3, #0] 800c1fa: 4a20 ldr r2, [pc, #128] ; (800c27c ) 800c1fc: 4293 cmp r3, r2 800c1fe: d009 beq.n 800c214 800c200: 687b ldr r3, [r7, #4] 800c202: 681b ldr r3, [r3, #0] 800c204: 4a1e ldr r2, [pc, #120] ; (800c280 ) 800c206: 4293 cmp r3, r2 800c208: d004 beq.n 800c214 800c20a: 687b ldr r3, [r7, #4] 800c20c: 681b ldr r3, [r3, #0] 800c20e: 4a1d ldr r2, [pc, #116] ; (800c284 ) 800c210: 4293 cmp r3, r2 800c212: d115 bne.n 800c240 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800c214: 687b ldr r3, [r7, #4] 800c216: 681b ldr r3, [r3, #0] 800c218: 689a ldr r2, [r3, #8] 800c21a: 4b1b ldr r3, [pc, #108] ; (800c288 ) 800c21c: 4013 ands r3, r2 800c21e: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800c220: 68fb ldr r3, [r7, #12] 800c222: 2b06 cmp r3, #6 800c224: d015 beq.n 800c252 800c226: 68fb ldr r3, [r7, #12] 800c228: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800c22c: d011 beq.n 800c252 { __HAL_TIM_ENABLE(htim); 800c22e: 687b ldr r3, [r7, #4] 800c230: 681b ldr r3, [r3, #0] 800c232: 681a ldr r2, [r3, #0] 800c234: 687b ldr r3, [r7, #4] 800c236: 681b ldr r3, [r3, #0] 800c238: f042 0201 orr.w r2, r2, #1 800c23c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800c23e: e008 b.n 800c252 } } else { __HAL_TIM_ENABLE(htim); 800c240: 687b ldr r3, [r7, #4] 800c242: 681b ldr r3, [r3, #0] 800c244: 681a ldr r2, [r3, #0] 800c246: 687b ldr r3, [r7, #4] 800c248: 681b ldr r3, [r3, #0] 800c24a: f042 0201 orr.w r2, r2, #1 800c24e: 601a str r2, [r3, #0] 800c250: e000 b.n 800c254 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800c252: bf00 nop } /* Return function status */ return HAL_OK; 800c254: 2300 movs r3, #0 } 800c256: 4618 mov r0, r3 800c258: 3714 adds r7, #20 800c25a: 46bd mov sp, r7 800c25c: f85d 7b04 ldr.w r7, [sp], #4 800c260: 4770 bx lr 800c262: bf00 nop 800c264: 40010000 .word 0x40010000 800c268: 40000400 .word 0x40000400 800c26c: 40000800 .word 0x40000800 800c270: 40000c00 .word 0x40000c00 800c274: 40010400 .word 0x40010400 800c278: 40001800 .word 0x40001800 800c27c: 40014000 .word 0x40014000 800c280: 4000e000 .word 0x4000e000 800c284: 4000e400 .word 0x4000e400 800c288: 00010007 .word 0x00010007 0800c28c : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800c28c: b580 push {r7, lr} 800c28e: b082 sub sp, #8 800c290: af00 add r7, sp, #0 800c292: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 800c294: 687b ldr r3, [r7, #4] 800c296: 681b ldr r3, [r3, #0] 800c298: 691b ldr r3, [r3, #16] 800c29a: f003 0302 and.w r3, r3, #2 800c29e: 2b02 cmp r3, #2 800c2a0: d122 bne.n 800c2e8 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 800c2a2: 687b ldr r3, [r7, #4] 800c2a4: 681b ldr r3, [r3, #0] 800c2a6: 68db ldr r3, [r3, #12] 800c2a8: f003 0302 and.w r3, r3, #2 800c2ac: 2b02 cmp r3, #2 800c2ae: d11b bne.n 800c2e8 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 800c2b0: 687b ldr r3, [r7, #4] 800c2b2: 681b ldr r3, [r3, #0] 800c2b4: f06f 0202 mvn.w r2, #2 800c2b8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800c2ba: 687b ldr r3, [r7, #4] 800c2bc: 2201 movs r2, #1 800c2be: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800c2c0: 687b ldr r3, [r7, #4] 800c2c2: 681b ldr r3, [r3, #0] 800c2c4: 699b ldr r3, [r3, #24] 800c2c6: f003 0303 and.w r3, r3, #3 800c2ca: 2b00 cmp r3, #0 800c2cc: d003 beq.n 800c2d6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800c2ce: 6878 ldr r0, [r7, #4] 800c2d0: f000 f9fe bl 800c6d0 800c2d4: e005 b.n 800c2e2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800c2d6: 6878 ldr r0, [r7, #4] 800c2d8: f000 f9f0 bl 800c6bc HAL_TIM_PWM_PulseFinishedCallback(htim); 800c2dc: 6878 ldr r0, [r7, #4] 800c2de: f000 fa01 bl 800c6e4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800c2e2: 687b ldr r3, [r7, #4] 800c2e4: 2200 movs r2, #0 800c2e6: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 800c2e8: 687b ldr r3, [r7, #4] 800c2ea: 681b ldr r3, [r3, #0] 800c2ec: 691b ldr r3, [r3, #16] 800c2ee: f003 0304 and.w r3, r3, #4 800c2f2: 2b04 cmp r3, #4 800c2f4: d122 bne.n 800c33c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 800c2f6: 687b ldr r3, [r7, #4] 800c2f8: 681b ldr r3, [r3, #0] 800c2fa: 68db ldr r3, [r3, #12] 800c2fc: f003 0304 and.w r3, r3, #4 800c300: 2b04 cmp r3, #4 800c302: d11b bne.n 800c33c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 800c304: 687b ldr r3, [r7, #4] 800c306: 681b ldr r3, [r3, #0] 800c308: f06f 0204 mvn.w r2, #4 800c30c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800c30e: 687b ldr r3, [r7, #4] 800c310: 2202 movs r2, #2 800c312: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800c314: 687b ldr r3, [r7, #4] 800c316: 681b ldr r3, [r3, #0] 800c318: 699b ldr r3, [r3, #24] 800c31a: f403 7340 and.w r3, r3, #768 ; 0x300 800c31e: 2b00 cmp r3, #0 800c320: d003 beq.n 800c32a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800c322: 6878 ldr r0, [r7, #4] 800c324: f000 f9d4 bl 800c6d0 800c328: e005 b.n 800c336 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800c32a: 6878 ldr r0, [r7, #4] 800c32c: f000 f9c6 bl 800c6bc HAL_TIM_PWM_PulseFinishedCallback(htim); 800c330: 6878 ldr r0, [r7, #4] 800c332: f000 f9d7 bl 800c6e4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800c336: 687b ldr r3, [r7, #4] 800c338: 2200 movs r2, #0 800c33a: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 800c33c: 687b ldr r3, [r7, #4] 800c33e: 681b ldr r3, [r3, #0] 800c340: 691b ldr r3, [r3, #16] 800c342: f003 0308 and.w r3, r3, #8 800c346: 2b08 cmp r3, #8 800c348: d122 bne.n 800c390 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 800c34a: 687b ldr r3, [r7, #4] 800c34c: 681b ldr r3, [r3, #0] 800c34e: 68db ldr r3, [r3, #12] 800c350: f003 0308 and.w r3, r3, #8 800c354: 2b08 cmp r3, #8 800c356: d11b bne.n 800c390 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 800c358: 687b ldr r3, [r7, #4] 800c35a: 681b ldr r3, [r3, #0] 800c35c: f06f 0208 mvn.w r2, #8 800c360: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800c362: 687b ldr r3, [r7, #4] 800c364: 2204 movs r2, #4 800c366: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800c368: 687b ldr r3, [r7, #4] 800c36a: 681b ldr r3, [r3, #0] 800c36c: 69db ldr r3, [r3, #28] 800c36e: f003 0303 and.w r3, r3, #3 800c372: 2b00 cmp r3, #0 800c374: d003 beq.n 800c37e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800c376: 6878 ldr r0, [r7, #4] 800c378: f000 f9aa bl 800c6d0 800c37c: e005 b.n 800c38a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800c37e: 6878 ldr r0, [r7, #4] 800c380: f000 f99c bl 800c6bc HAL_TIM_PWM_PulseFinishedCallback(htim); 800c384: 6878 ldr r0, [r7, #4] 800c386: f000 f9ad bl 800c6e4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800c38a: 687b ldr r3, [r7, #4] 800c38c: 2200 movs r2, #0 800c38e: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 800c390: 687b ldr r3, [r7, #4] 800c392: 681b ldr r3, [r3, #0] 800c394: 691b ldr r3, [r3, #16] 800c396: f003 0310 and.w r3, r3, #16 800c39a: 2b10 cmp r3, #16 800c39c: d122 bne.n 800c3e4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 800c39e: 687b ldr r3, [r7, #4] 800c3a0: 681b ldr r3, [r3, #0] 800c3a2: 68db ldr r3, [r3, #12] 800c3a4: f003 0310 and.w r3, r3, #16 800c3a8: 2b10 cmp r3, #16 800c3aa: d11b bne.n 800c3e4 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 800c3ac: 687b ldr r3, [r7, #4] 800c3ae: 681b ldr r3, [r3, #0] 800c3b0: f06f 0210 mvn.w r2, #16 800c3b4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800c3b6: 687b ldr r3, [r7, #4] 800c3b8: 2208 movs r2, #8 800c3ba: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800c3bc: 687b ldr r3, [r7, #4] 800c3be: 681b ldr r3, [r3, #0] 800c3c0: 69db ldr r3, [r3, #28] 800c3c2: f403 7340 and.w r3, r3, #768 ; 0x300 800c3c6: 2b00 cmp r3, #0 800c3c8: d003 beq.n 800c3d2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800c3ca: 6878 ldr r0, [r7, #4] 800c3cc: f000 f980 bl 800c6d0 800c3d0: e005 b.n 800c3de { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800c3d2: 6878 ldr r0, [r7, #4] 800c3d4: f000 f972 bl 800c6bc HAL_TIM_PWM_PulseFinishedCallback(htim); 800c3d8: 6878 ldr r0, [r7, #4] 800c3da: f000 f983 bl 800c6e4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800c3de: 687b ldr r3, [r7, #4] 800c3e0: 2200 movs r2, #0 800c3e2: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 800c3e4: 687b ldr r3, [r7, #4] 800c3e6: 681b ldr r3, [r3, #0] 800c3e8: 691b ldr r3, [r3, #16] 800c3ea: f003 0301 and.w r3, r3, #1 800c3ee: 2b01 cmp r3, #1 800c3f0: d10e bne.n 800c410 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 800c3f2: 687b ldr r3, [r7, #4] 800c3f4: 681b ldr r3, [r3, #0] 800c3f6: 68db ldr r3, [r3, #12] 800c3f8: f003 0301 and.w r3, r3, #1 800c3fc: 2b01 cmp r3, #1 800c3fe: d107 bne.n 800c410 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 800c400: 687b ldr r3, [r7, #4] 800c402: 681b ldr r3, [r3, #0] 800c404: f06f 0201 mvn.w r2, #1 800c408: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800c40a: 6878 ldr r0, [r7, #4] 800c40c: f7f5 f860 bl 80014d0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 800c410: 687b ldr r3, [r7, #4] 800c412: 681b ldr r3, [r3, #0] 800c414: 691b ldr r3, [r3, #16] 800c416: f003 0380 and.w r3, r3, #128 ; 0x80 800c41a: 2b80 cmp r3, #128 ; 0x80 800c41c: d10e bne.n 800c43c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 800c41e: 687b ldr r3, [r7, #4] 800c420: 681b ldr r3, [r3, #0] 800c422: 68db ldr r3, [r3, #12] 800c424: f003 0380 and.w r3, r3, #128 ; 0x80 800c428: 2b80 cmp r3, #128 ; 0x80 800c42a: d107 bne.n 800c43c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 800c42c: 687b ldr r3, [r7, #4] 800c42e: 681b ldr r3, [r3, #0] 800c430: f06f 0280 mvn.w r2, #128 ; 0x80 800c434: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 800c436: 6878 ldr r0, [r7, #4] 800c438: f000 fb52 bl 800cae0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) 800c43c: 687b ldr r3, [r7, #4] 800c43e: 681b ldr r3, [r3, #0] 800c440: 691b ldr r3, [r3, #16] 800c442: f403 7380 and.w r3, r3, #256 ; 0x100 800c446: f5b3 7f80 cmp.w r3, #256 ; 0x100 800c44a: d10e bne.n 800c46a { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 800c44c: 687b ldr r3, [r7, #4] 800c44e: 681b ldr r3, [r3, #0] 800c450: 68db ldr r3, [r3, #12] 800c452: f003 0380 and.w r3, r3, #128 ; 0x80 800c456: 2b80 cmp r3, #128 ; 0x80 800c458: d107 bne.n 800c46a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800c45a: 687b ldr r3, [r7, #4] 800c45c: 681b ldr r3, [r3, #0] 800c45e: f46f 7280 mvn.w r2, #256 ; 0x100 800c462: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800c464: 6878 ldr r0, [r7, #4] 800c466: f000 fb45 bl 800caf4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 800c46a: 687b ldr r3, [r7, #4] 800c46c: 681b ldr r3, [r3, #0] 800c46e: 691b ldr r3, [r3, #16] 800c470: f003 0340 and.w r3, r3, #64 ; 0x40 800c474: 2b40 cmp r3, #64 ; 0x40 800c476: d10e bne.n 800c496 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 800c478: 687b ldr r3, [r7, #4] 800c47a: 681b ldr r3, [r3, #0] 800c47c: 68db ldr r3, [r3, #12] 800c47e: f003 0340 and.w r3, r3, #64 ; 0x40 800c482: 2b40 cmp r3, #64 ; 0x40 800c484: d107 bne.n 800c496 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 800c486: 687b ldr r3, [r7, #4] 800c488: 681b ldr r3, [r3, #0] 800c48a: f06f 0240 mvn.w r2, #64 ; 0x40 800c48e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800c490: 6878 ldr r0, [r7, #4] 800c492: f000 f931 bl 800c6f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 800c496: 687b ldr r3, [r7, #4] 800c498: 681b ldr r3, [r3, #0] 800c49a: 691b ldr r3, [r3, #16] 800c49c: f003 0320 and.w r3, r3, #32 800c4a0: 2b20 cmp r3, #32 800c4a2: d10e bne.n 800c4c2 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 800c4a4: 687b ldr r3, [r7, #4] 800c4a6: 681b ldr r3, [r3, #0] 800c4a8: 68db ldr r3, [r3, #12] 800c4aa: f003 0320 and.w r3, r3, #32 800c4ae: 2b20 cmp r3, #32 800c4b0: d107 bne.n 800c4c2 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 800c4b2: 687b ldr r3, [r7, #4] 800c4b4: 681b ldr r3, [r3, #0] 800c4b6: f06f 0220 mvn.w r2, #32 800c4ba: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800c4bc: 6878 ldr r0, [r7, #4] 800c4be: f000 fb05 bl 800cacc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800c4c2: bf00 nop 800c4c4: 3708 adds r7, #8 800c4c6: 46bd mov sp, r7 800c4c8: bd80 pop {r7, pc} ... 0800c4cc : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 800c4cc: b580 push {r7, lr} 800c4ce: b084 sub sp, #16 800c4d0: af00 add r7, sp, #0 800c4d2: 6078 str r0, [r7, #4] 800c4d4: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800c4d6: 2300 movs r3, #0 800c4d8: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 800c4da: 687b ldr r3, [r7, #4] 800c4dc: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800c4e0: 2b01 cmp r3, #1 800c4e2: d101 bne.n 800c4e8 800c4e4: 2302 movs r3, #2 800c4e6: e0dc b.n 800c6a2 800c4e8: 687b ldr r3, [r7, #4] 800c4ea: 2201 movs r2, #1 800c4ec: f883 203c strb.w r2, [r3, #60] ; 0x3c htim->State = HAL_TIM_STATE_BUSY; 800c4f0: 687b ldr r3, [r7, #4] 800c4f2: 2202 movs r2, #2 800c4f4: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 800c4f8: 687b ldr r3, [r7, #4] 800c4fa: 681b ldr r3, [r3, #0] 800c4fc: 689b ldr r3, [r3, #8] 800c4fe: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 800c500: 68ba ldr r2, [r7, #8] 800c502: 4b6a ldr r3, [pc, #424] ; (800c6ac ) 800c504: 4013 ands r3, r2 800c506: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800c508: 68bb ldr r3, [r7, #8] 800c50a: f423 437f bic.w r3, r3, #65280 ; 0xff00 800c50e: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 800c510: 687b ldr r3, [r7, #4] 800c512: 681b ldr r3, [r3, #0] 800c514: 68ba ldr r2, [r7, #8] 800c516: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 800c518: 683b ldr r3, [r7, #0] 800c51a: 681b ldr r3, [r3, #0] 800c51c: 4a64 ldr r2, [pc, #400] ; (800c6b0 ) 800c51e: 4293 cmp r3, r2 800c520: f000 80a9 beq.w 800c676 800c524: 4a62 ldr r2, [pc, #392] ; (800c6b0 ) 800c526: 4293 cmp r3, r2 800c528: f200 80ae bhi.w 800c688 800c52c: 4a61 ldr r2, [pc, #388] ; (800c6b4 ) 800c52e: 4293 cmp r3, r2 800c530: f000 80a1 beq.w 800c676 800c534: 4a5f ldr r2, [pc, #380] ; (800c6b4 ) 800c536: 4293 cmp r3, r2 800c538: f200 80a6 bhi.w 800c688 800c53c: 4a5e ldr r2, [pc, #376] ; (800c6b8 ) 800c53e: 4293 cmp r3, r2 800c540: f000 8099 beq.w 800c676 800c544: 4a5c ldr r2, [pc, #368] ; (800c6b8 ) 800c546: 4293 cmp r3, r2 800c548: f200 809e bhi.w 800c688 800c54c: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010 800c550: f000 8091 beq.w 800c676 800c554: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010 800c558: f200 8096 bhi.w 800c688 800c55c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800c560: f000 8089 beq.w 800c676 800c564: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800c568: f200 808e bhi.w 800c688 800c56c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800c570: d03e beq.n 800c5f0 800c572: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800c576: f200 8087 bhi.w 800c688 800c57a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800c57e: f000 8086 beq.w 800c68e 800c582: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800c586: d87f bhi.n 800c688 800c588: 2b70 cmp r3, #112 ; 0x70 800c58a: d01a beq.n 800c5c2 800c58c: 2b70 cmp r3, #112 ; 0x70 800c58e: d87b bhi.n 800c688 800c590: 2b60 cmp r3, #96 ; 0x60 800c592: d050 beq.n 800c636 800c594: 2b60 cmp r3, #96 ; 0x60 800c596: d877 bhi.n 800c688 800c598: 2b50 cmp r3, #80 ; 0x50 800c59a: d03c beq.n 800c616 800c59c: 2b50 cmp r3, #80 ; 0x50 800c59e: d873 bhi.n 800c688 800c5a0: 2b40 cmp r3, #64 ; 0x40 800c5a2: d058 beq.n 800c656 800c5a4: 2b40 cmp r3, #64 ; 0x40 800c5a6: d86f bhi.n 800c688 800c5a8: 2b30 cmp r3, #48 ; 0x30 800c5aa: d064 beq.n 800c676 800c5ac: 2b30 cmp r3, #48 ; 0x30 800c5ae: d86b bhi.n 800c688 800c5b0: 2b20 cmp r3, #32 800c5b2: d060 beq.n 800c676 800c5b4: 2b20 cmp r3, #32 800c5b6: d867 bhi.n 800c688 800c5b8: 2b00 cmp r3, #0 800c5ba: d05c beq.n 800c676 800c5bc: 2b10 cmp r3, #16 800c5be: d05a beq.n 800c676 800c5c0: e062 b.n 800c688 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800c5c2: 687b ldr r3, [r7, #4] 800c5c4: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800c5c6: 683b ldr r3, [r7, #0] 800c5c8: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800c5ca: 683b ldr r3, [r7, #0] 800c5cc: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800c5ce: 683b ldr r3, [r7, #0] 800c5d0: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800c5d2: f000 f9bf bl 800c954 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 800c5d6: 687b ldr r3, [r7, #4] 800c5d8: 681b ldr r3, [r3, #0] 800c5da: 689b ldr r3, [r3, #8] 800c5dc: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 800c5de: 68bb ldr r3, [r7, #8] 800c5e0: f043 0377 orr.w r3, r3, #119 ; 0x77 800c5e4: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800c5e6: 687b ldr r3, [r7, #4] 800c5e8: 681b ldr r3, [r3, #0] 800c5ea: 68ba ldr r2, [r7, #8] 800c5ec: 609a str r2, [r3, #8] break; 800c5ee: e04f b.n 800c690 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800c5f0: 687b ldr r3, [r7, #4] 800c5f2: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800c5f4: 683b ldr r3, [r7, #0] 800c5f6: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800c5f8: 683b ldr r3, [r7, #0] 800c5fa: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800c5fc: 683b ldr r3, [r7, #0] 800c5fe: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800c600: f000 f9a8 bl 800c954 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 800c604: 687b ldr r3, [r7, #4] 800c606: 681b ldr r3, [r3, #0] 800c608: 689a ldr r2, [r3, #8] 800c60a: 687b ldr r3, [r7, #4] 800c60c: 681b ldr r3, [r3, #0] 800c60e: f442 4280 orr.w r2, r2, #16384 ; 0x4000 800c612: 609a str r2, [r3, #8] break; 800c614: e03c b.n 800c690 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800c616: 687b ldr r3, [r7, #4] 800c618: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800c61a: 683b ldr r3, [r7, #0] 800c61c: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800c61e: 683b ldr r3, [r7, #0] 800c620: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800c622: 461a mov r2, r3 800c624: f000 f918 bl 800c858 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 800c628: 687b ldr r3, [r7, #4] 800c62a: 681b ldr r3, [r3, #0] 800c62c: 2150 movs r1, #80 ; 0x50 800c62e: 4618 mov r0, r3 800c630: f000 f972 bl 800c918 break; 800c634: e02c b.n 800c690 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 800c636: 687b ldr r3, [r7, #4] 800c638: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800c63a: 683b ldr r3, [r7, #0] 800c63c: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800c63e: 683b ldr r3, [r7, #0] 800c640: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 800c642: 461a mov r2, r3 800c644: f000 f937 bl 800c8b6 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 800c648: 687b ldr r3, [r7, #4] 800c64a: 681b ldr r3, [r3, #0] 800c64c: 2160 movs r1, #96 ; 0x60 800c64e: 4618 mov r0, r3 800c650: f000 f962 bl 800c918 break; 800c654: e01c b.n 800c690 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800c656: 687b ldr r3, [r7, #4] 800c658: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800c65a: 683b ldr r3, [r7, #0] 800c65c: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800c65e: 683b ldr r3, [r7, #0] 800c660: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800c662: 461a mov r2, r3 800c664: f000 f8f8 bl 800c858 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 800c668: 687b ldr r3, [r7, #4] 800c66a: 681b ldr r3, [r3, #0] 800c66c: 2140 movs r1, #64 ; 0x40 800c66e: 4618 mov r0, r3 800c670: f000 f952 bl 800c918 break; 800c674: e00c b.n 800c690 case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 800c676: 687b ldr r3, [r7, #4] 800c678: 681a ldr r2, [r3, #0] 800c67a: 683b ldr r3, [r7, #0] 800c67c: 681b ldr r3, [r3, #0] 800c67e: 4619 mov r1, r3 800c680: 4610 mov r0, r2 800c682: f000 f949 bl 800c918 break; 800c686: e003 b.n 800c690 } default: status = HAL_ERROR; 800c688: 2301 movs r3, #1 800c68a: 73fb strb r3, [r7, #15] break; 800c68c: e000 b.n 800c690 break; 800c68e: bf00 nop } htim->State = HAL_TIM_STATE_READY; 800c690: 687b ldr r3, [r7, #4] 800c692: 2201 movs r2, #1 800c694: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 800c698: 687b ldr r3, [r7, #4] 800c69a: 2200 movs r2, #0 800c69c: f883 203c strb.w r2, [r3, #60] ; 0x3c return status; 800c6a0: 7bfb ldrb r3, [r7, #15] } 800c6a2: 4618 mov r0, r3 800c6a4: 3710 adds r7, #16 800c6a6: 46bd mov sp, r7 800c6a8: bd80 pop {r7, pc} 800c6aa: bf00 nop 800c6ac: ffceff88 .word 0xffceff88 800c6b0: 00100040 .word 0x00100040 800c6b4: 00100030 .word 0x00100030 800c6b8: 00100020 .word 0x00100020 0800c6bc : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800c6bc: b480 push {r7} 800c6be: b083 sub sp, #12 800c6c0: af00 add r7, sp, #0 800c6c2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800c6c4: bf00 nop 800c6c6: 370c adds r7, #12 800c6c8: 46bd mov sp, r7 800c6ca: f85d 7b04 ldr.w r7, [sp], #4 800c6ce: 4770 bx lr 0800c6d0 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 800c6d0: b480 push {r7} 800c6d2: b083 sub sp, #12 800c6d4: af00 add r7, sp, #0 800c6d6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 800c6d8: bf00 nop 800c6da: 370c adds r7, #12 800c6dc: 46bd mov sp, r7 800c6de: f85d 7b04 ldr.w r7, [sp], #4 800c6e2: 4770 bx lr 0800c6e4 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800c6e4: b480 push {r7} 800c6e6: b083 sub sp, #12 800c6e8: af00 add r7, sp, #0 800c6ea: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 800c6ec: bf00 nop 800c6ee: 370c adds r7, #12 800c6f0: 46bd mov sp, r7 800c6f2: f85d 7b04 ldr.w r7, [sp], #4 800c6f6: 4770 bx lr 0800c6f8 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800c6f8: b480 push {r7} 800c6fa: b083 sub sp, #12 800c6fc: af00 add r7, sp, #0 800c6fe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 800c700: bf00 nop 800c702: 370c adds r7, #12 800c704: 46bd mov sp, r7 800c706: f85d 7b04 ldr.w r7, [sp], #4 800c70a: 4770 bx lr 0800c70c : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 800c70c: b480 push {r7} 800c70e: b085 sub sp, #20 800c710: af00 add r7, sp, #0 800c712: 6078 str r0, [r7, #4] 800c714: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800c716: 687b ldr r3, [r7, #4] 800c718: 681b ldr r3, [r3, #0] 800c71a: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800c71c: 687b ldr r3, [r7, #4] 800c71e: 4a44 ldr r2, [pc, #272] ; (800c830 ) 800c720: 4293 cmp r3, r2 800c722: d013 beq.n 800c74c 800c724: 687b ldr r3, [r7, #4] 800c726: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800c72a: d00f beq.n 800c74c 800c72c: 687b ldr r3, [r7, #4] 800c72e: 4a41 ldr r2, [pc, #260] ; (800c834 ) 800c730: 4293 cmp r3, r2 800c732: d00b beq.n 800c74c 800c734: 687b ldr r3, [r7, #4] 800c736: 4a40 ldr r2, [pc, #256] ; (800c838 ) 800c738: 4293 cmp r3, r2 800c73a: d007 beq.n 800c74c 800c73c: 687b ldr r3, [r7, #4] 800c73e: 4a3f ldr r2, [pc, #252] ; (800c83c ) 800c740: 4293 cmp r3, r2 800c742: d003 beq.n 800c74c 800c744: 687b ldr r3, [r7, #4] 800c746: 4a3e ldr r2, [pc, #248] ; (800c840 ) 800c748: 4293 cmp r3, r2 800c74a: d108 bne.n 800c75e { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800c74c: 68fb ldr r3, [r7, #12] 800c74e: f023 0370 bic.w r3, r3, #112 ; 0x70 800c752: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 800c754: 683b ldr r3, [r7, #0] 800c756: 685b ldr r3, [r3, #4] 800c758: 68fa ldr r2, [r7, #12] 800c75a: 4313 orrs r3, r2 800c75c: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800c75e: 687b ldr r3, [r7, #4] 800c760: 4a33 ldr r2, [pc, #204] ; (800c830 ) 800c762: 4293 cmp r3, r2 800c764: d027 beq.n 800c7b6 800c766: 687b ldr r3, [r7, #4] 800c768: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800c76c: d023 beq.n 800c7b6 800c76e: 687b ldr r3, [r7, #4] 800c770: 4a30 ldr r2, [pc, #192] ; (800c834 ) 800c772: 4293 cmp r3, r2 800c774: d01f beq.n 800c7b6 800c776: 687b ldr r3, [r7, #4] 800c778: 4a2f ldr r2, [pc, #188] ; (800c838 ) 800c77a: 4293 cmp r3, r2 800c77c: d01b beq.n 800c7b6 800c77e: 687b ldr r3, [r7, #4] 800c780: 4a2e ldr r2, [pc, #184] ; (800c83c ) 800c782: 4293 cmp r3, r2 800c784: d017 beq.n 800c7b6 800c786: 687b ldr r3, [r7, #4] 800c788: 4a2d ldr r2, [pc, #180] ; (800c840 ) 800c78a: 4293 cmp r3, r2 800c78c: d013 beq.n 800c7b6 800c78e: 687b ldr r3, [r7, #4] 800c790: 4a2c ldr r2, [pc, #176] ; (800c844 ) 800c792: 4293 cmp r3, r2 800c794: d00f beq.n 800c7b6 800c796: 687b ldr r3, [r7, #4] 800c798: 4a2b ldr r2, [pc, #172] ; (800c848 ) 800c79a: 4293 cmp r3, r2 800c79c: d00b beq.n 800c7b6 800c79e: 687b ldr r3, [r7, #4] 800c7a0: 4a2a ldr r2, [pc, #168] ; (800c84c ) 800c7a2: 4293 cmp r3, r2 800c7a4: d007 beq.n 800c7b6 800c7a6: 687b ldr r3, [r7, #4] 800c7a8: 4a29 ldr r2, [pc, #164] ; (800c850 ) 800c7aa: 4293 cmp r3, r2 800c7ac: d003 beq.n 800c7b6 800c7ae: 687b ldr r3, [r7, #4] 800c7b0: 4a28 ldr r2, [pc, #160] ; (800c854 ) 800c7b2: 4293 cmp r3, r2 800c7b4: d108 bne.n 800c7c8 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800c7b6: 68fb ldr r3, [r7, #12] 800c7b8: f423 7340 bic.w r3, r3, #768 ; 0x300 800c7bc: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800c7be: 683b ldr r3, [r7, #0] 800c7c0: 68db ldr r3, [r3, #12] 800c7c2: 68fa ldr r2, [r7, #12] 800c7c4: 4313 orrs r3, r2 800c7c6: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800c7c8: 68fb ldr r3, [r7, #12] 800c7ca: f023 0280 bic.w r2, r3, #128 ; 0x80 800c7ce: 683b ldr r3, [r7, #0] 800c7d0: 695b ldr r3, [r3, #20] 800c7d2: 4313 orrs r3, r2 800c7d4: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800c7d6: 687b ldr r3, [r7, #4] 800c7d8: 68fa ldr r2, [r7, #12] 800c7da: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800c7dc: 683b ldr r3, [r7, #0] 800c7de: 689a ldr r2, [r3, #8] 800c7e0: 687b ldr r3, [r7, #4] 800c7e2: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800c7e4: 683b ldr r3, [r7, #0] 800c7e6: 681a ldr r2, [r3, #0] 800c7e8: 687b ldr r3, [r7, #4] 800c7ea: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800c7ec: 687b ldr r3, [r7, #4] 800c7ee: 4a10 ldr r2, [pc, #64] ; (800c830 ) 800c7f0: 4293 cmp r3, r2 800c7f2: d00f beq.n 800c814 800c7f4: 687b ldr r3, [r7, #4] 800c7f6: 4a12 ldr r2, [pc, #72] ; (800c840 ) 800c7f8: 4293 cmp r3, r2 800c7fa: d00b beq.n 800c814 800c7fc: 687b ldr r3, [r7, #4] 800c7fe: 4a11 ldr r2, [pc, #68] ; (800c844 ) 800c800: 4293 cmp r3, r2 800c802: d007 beq.n 800c814 800c804: 687b ldr r3, [r7, #4] 800c806: 4a10 ldr r2, [pc, #64] ; (800c848 ) 800c808: 4293 cmp r3, r2 800c80a: d003 beq.n 800c814 800c80c: 687b ldr r3, [r7, #4] 800c80e: 4a0f ldr r2, [pc, #60] ; (800c84c ) 800c810: 4293 cmp r3, r2 800c812: d103 bne.n 800c81c { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800c814: 683b ldr r3, [r7, #0] 800c816: 691a ldr r2, [r3, #16] 800c818: 687b ldr r3, [r7, #4] 800c81a: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800c81c: 687b ldr r3, [r7, #4] 800c81e: 2201 movs r2, #1 800c820: 615a str r2, [r3, #20] } 800c822: bf00 nop 800c824: 3714 adds r7, #20 800c826: 46bd mov sp, r7 800c828: f85d 7b04 ldr.w r7, [sp], #4 800c82c: 4770 bx lr 800c82e: bf00 nop 800c830: 40010000 .word 0x40010000 800c834: 40000400 .word 0x40000400 800c838: 40000800 .word 0x40000800 800c83c: 40000c00 .word 0x40000c00 800c840: 40010400 .word 0x40010400 800c844: 40014000 .word 0x40014000 800c848: 40014400 .word 0x40014400 800c84c: 40014800 .word 0x40014800 800c850: 4000e000 .word 0x4000e000 800c854: 4000e400 .word 0x4000e400 0800c858 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 800c858: b480 push {r7} 800c85a: b087 sub sp, #28 800c85c: af00 add r7, sp, #0 800c85e: 60f8 str r0, [r7, #12] 800c860: 60b9 str r1, [r7, #8] 800c862: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 800c864: 68fb ldr r3, [r7, #12] 800c866: 6a1b ldr r3, [r3, #32] 800c868: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 800c86a: 68fb ldr r3, [r7, #12] 800c86c: 6a1b ldr r3, [r3, #32] 800c86e: f023 0201 bic.w r2, r3, #1 800c872: 68fb ldr r3, [r7, #12] 800c874: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 800c876: 68fb ldr r3, [r7, #12] 800c878: 699b ldr r3, [r3, #24] 800c87a: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 800c87c: 693b ldr r3, [r7, #16] 800c87e: f023 03f0 bic.w r3, r3, #240 ; 0xf0 800c882: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 800c884: 687b ldr r3, [r7, #4] 800c886: 011b lsls r3, r3, #4 800c888: 693a ldr r2, [r7, #16] 800c88a: 4313 orrs r3, r2 800c88c: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 800c88e: 697b ldr r3, [r7, #20] 800c890: f023 030a bic.w r3, r3, #10 800c894: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 800c896: 697a ldr r2, [r7, #20] 800c898: 68bb ldr r3, [r7, #8] 800c89a: 4313 orrs r3, r2 800c89c: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 800c89e: 68fb ldr r3, [r7, #12] 800c8a0: 693a ldr r2, [r7, #16] 800c8a2: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 800c8a4: 68fb ldr r3, [r7, #12] 800c8a6: 697a ldr r2, [r7, #20] 800c8a8: 621a str r2, [r3, #32] } 800c8aa: bf00 nop 800c8ac: 371c adds r7, #28 800c8ae: 46bd mov sp, r7 800c8b0: f85d 7b04 ldr.w r7, [sp], #4 800c8b4: 4770 bx lr 0800c8b6 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 800c8b6: b480 push {r7} 800c8b8: b087 sub sp, #28 800c8ba: af00 add r7, sp, #0 800c8bc: 60f8 str r0, [r7, #12] 800c8be: 60b9 str r1, [r7, #8] 800c8c0: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 800c8c2: 68fb ldr r3, [r7, #12] 800c8c4: 6a1b ldr r3, [r3, #32] 800c8c6: f023 0210 bic.w r2, r3, #16 800c8ca: 68fb ldr r3, [r7, #12] 800c8cc: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 800c8ce: 68fb ldr r3, [r7, #12] 800c8d0: 699b ldr r3, [r3, #24] 800c8d2: 617b str r3, [r7, #20] tmpccer = TIMx->CCER; 800c8d4: 68fb ldr r3, [r7, #12] 800c8d6: 6a1b ldr r3, [r3, #32] 800c8d8: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 800c8da: 697b ldr r3, [r7, #20] 800c8dc: f423 4370 bic.w r3, r3, #61440 ; 0xf000 800c8e0: 617b str r3, [r7, #20] tmpccmr1 |= (TIM_ICFilter << 12U); 800c8e2: 687b ldr r3, [r7, #4] 800c8e4: 031b lsls r3, r3, #12 800c8e6: 697a ldr r2, [r7, #20] 800c8e8: 4313 orrs r3, r2 800c8ea: 617b str r3, [r7, #20] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 800c8ec: 693b ldr r3, [r7, #16] 800c8ee: f023 03a0 bic.w r3, r3, #160 ; 0xa0 800c8f2: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity << 4U); 800c8f4: 68bb ldr r3, [r7, #8] 800c8f6: 011b lsls r3, r3, #4 800c8f8: 693a ldr r2, [r7, #16] 800c8fa: 4313 orrs r3, r2 800c8fc: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 800c8fe: 68fb ldr r3, [r7, #12] 800c900: 697a ldr r2, [r7, #20] 800c902: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 800c904: 68fb ldr r3, [r7, #12] 800c906: 693a ldr r2, [r7, #16] 800c908: 621a str r2, [r3, #32] } 800c90a: bf00 nop 800c90c: 371c adds r7, #28 800c90e: 46bd mov sp, r7 800c910: f85d 7b04 ldr.w r7, [sp], #4 800c914: 4770 bx lr ... 0800c918 : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 800c918: b480 push {r7} 800c91a: b085 sub sp, #20 800c91c: af00 add r7, sp, #0 800c91e: 6078 str r0, [r7, #4] 800c920: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 800c922: 687b ldr r3, [r7, #4] 800c924: 689b ldr r3, [r3, #8] 800c926: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 800c928: 68fa ldr r2, [r7, #12] 800c92a: 4b09 ldr r3, [pc, #36] ; (800c950 ) 800c92c: 4013 ands r3, r2 800c92e: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 800c930: 683a ldr r2, [r7, #0] 800c932: 68fb ldr r3, [r7, #12] 800c934: 4313 orrs r3, r2 800c936: f043 0307 orr.w r3, r3, #7 800c93a: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 800c93c: 687b ldr r3, [r7, #4] 800c93e: 68fa ldr r2, [r7, #12] 800c940: 609a str r2, [r3, #8] } 800c942: bf00 nop 800c944: 3714 adds r7, #20 800c946: 46bd mov sp, r7 800c948: f85d 7b04 ldr.w r7, [sp], #4 800c94c: 4770 bx lr 800c94e: bf00 nop 800c950: ffcfff8f .word 0xffcfff8f 0800c954 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 800c954: b480 push {r7} 800c956: b087 sub sp, #28 800c958: af00 add r7, sp, #0 800c95a: 60f8 str r0, [r7, #12] 800c95c: 60b9 str r1, [r7, #8] 800c95e: 607a str r2, [r7, #4] 800c960: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 800c962: 68fb ldr r3, [r7, #12] 800c964: 689b ldr r3, [r3, #8] 800c966: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800c968: 697b ldr r3, [r7, #20] 800c96a: f423 437f bic.w r3, r3, #65280 ; 0xff00 800c96e: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800c970: 683b ldr r3, [r7, #0] 800c972: 021a lsls r2, r3, #8 800c974: 687b ldr r3, [r7, #4] 800c976: 431a orrs r2, r3 800c978: 68bb ldr r3, [r7, #8] 800c97a: 4313 orrs r3, r2 800c97c: 697a ldr r2, [r7, #20] 800c97e: 4313 orrs r3, r2 800c980: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 800c982: 68fb ldr r3, [r7, #12] 800c984: 697a ldr r2, [r7, #20] 800c986: 609a str r2, [r3, #8] } 800c988: bf00 nop 800c98a: 371c adds r7, #28 800c98c: 46bd mov sp, r7 800c98e: f85d 7b04 ldr.w r7, [sp], #4 800c992: 4770 bx lr 0800c994 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 800c994: b480 push {r7} 800c996: b085 sub sp, #20 800c998: af00 add r7, sp, #0 800c99a: 6078 str r0, [r7, #4] 800c99c: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800c99e: 687b ldr r3, [r7, #4] 800c9a0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800c9a4: 2b01 cmp r3, #1 800c9a6: d101 bne.n 800c9ac 800c9a8: 2302 movs r3, #2 800c9aa: e077 b.n 800ca9c 800c9ac: 687b ldr r3, [r7, #4] 800c9ae: 2201 movs r2, #1 800c9b0: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 800c9b4: 687b ldr r3, [r7, #4] 800c9b6: 2202 movs r2, #2 800c9b8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 800c9bc: 687b ldr r3, [r7, #4] 800c9be: 681b ldr r3, [r3, #0] 800c9c0: 685b ldr r3, [r3, #4] 800c9c2: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 800c9c4: 687b ldr r3, [r7, #4] 800c9c6: 681b ldr r3, [r3, #0] 800c9c8: 689b ldr r3, [r3, #8] 800c9ca: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 800c9cc: 687b ldr r3, [r7, #4] 800c9ce: 681b ldr r3, [r3, #0] 800c9d0: 4a35 ldr r2, [pc, #212] ; (800caa8 ) 800c9d2: 4293 cmp r3, r2 800c9d4: d004 beq.n 800c9e0 800c9d6: 687b ldr r3, [r7, #4] 800c9d8: 681b ldr r3, [r3, #0] 800c9da: 4a34 ldr r2, [pc, #208] ; (800caac ) 800c9dc: 4293 cmp r3, r2 800c9de: d108 bne.n 800c9f2 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 800c9e0: 68fb ldr r3, [r7, #12] 800c9e2: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 800c9e6: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 800c9e8: 683b ldr r3, [r7, #0] 800c9ea: 685b ldr r3, [r3, #4] 800c9ec: 68fa ldr r2, [r7, #12] 800c9ee: 4313 orrs r3, r2 800c9f0: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 800c9f2: 68fb ldr r3, [r7, #12] 800c9f4: f023 0370 bic.w r3, r3, #112 ; 0x70 800c9f8: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 800c9fa: 683b ldr r3, [r7, #0] 800c9fc: 681b ldr r3, [r3, #0] 800c9fe: 68fa ldr r2, [r7, #12] 800ca00: 4313 orrs r3, r2 800ca02: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 800ca04: 687b ldr r3, [r7, #4] 800ca06: 681b ldr r3, [r3, #0] 800ca08: 68fa ldr r2, [r7, #12] 800ca0a: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800ca0c: 687b ldr r3, [r7, #4] 800ca0e: 681b ldr r3, [r3, #0] 800ca10: 4a25 ldr r2, [pc, #148] ; (800caa8 ) 800ca12: 4293 cmp r3, r2 800ca14: d02c beq.n 800ca70 800ca16: 687b ldr r3, [r7, #4] 800ca18: 681b ldr r3, [r3, #0] 800ca1a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800ca1e: d027 beq.n 800ca70 800ca20: 687b ldr r3, [r7, #4] 800ca22: 681b ldr r3, [r3, #0] 800ca24: 4a22 ldr r2, [pc, #136] ; (800cab0 ) 800ca26: 4293 cmp r3, r2 800ca28: d022 beq.n 800ca70 800ca2a: 687b ldr r3, [r7, #4] 800ca2c: 681b ldr r3, [r3, #0] 800ca2e: 4a21 ldr r2, [pc, #132] ; (800cab4 ) 800ca30: 4293 cmp r3, r2 800ca32: d01d beq.n 800ca70 800ca34: 687b ldr r3, [r7, #4] 800ca36: 681b ldr r3, [r3, #0] 800ca38: 4a1f ldr r2, [pc, #124] ; (800cab8 ) 800ca3a: 4293 cmp r3, r2 800ca3c: d018 beq.n 800ca70 800ca3e: 687b ldr r3, [r7, #4] 800ca40: 681b ldr r3, [r3, #0] 800ca42: 4a1a ldr r2, [pc, #104] ; (800caac ) 800ca44: 4293 cmp r3, r2 800ca46: d013 beq.n 800ca70 800ca48: 687b ldr r3, [r7, #4] 800ca4a: 681b ldr r3, [r3, #0] 800ca4c: 4a1b ldr r2, [pc, #108] ; (800cabc ) 800ca4e: 4293 cmp r3, r2 800ca50: d00e beq.n 800ca70 800ca52: 687b ldr r3, [r7, #4] 800ca54: 681b ldr r3, [r3, #0] 800ca56: 4a1a ldr r2, [pc, #104] ; (800cac0 ) 800ca58: 4293 cmp r3, r2 800ca5a: d009 beq.n 800ca70 800ca5c: 687b ldr r3, [r7, #4] 800ca5e: 681b ldr r3, [r3, #0] 800ca60: 4a18 ldr r2, [pc, #96] ; (800cac4 ) 800ca62: 4293 cmp r3, r2 800ca64: d004 beq.n 800ca70 800ca66: 687b ldr r3, [r7, #4] 800ca68: 681b ldr r3, [r3, #0] 800ca6a: 4a17 ldr r2, [pc, #92] ; (800cac8 ) 800ca6c: 4293 cmp r3, r2 800ca6e: d10c bne.n 800ca8a { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 800ca70: 68bb ldr r3, [r7, #8] 800ca72: f023 0380 bic.w r3, r3, #128 ; 0x80 800ca76: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800ca78: 683b ldr r3, [r7, #0] 800ca7a: 689b ldr r3, [r3, #8] 800ca7c: 68ba ldr r2, [r7, #8] 800ca7e: 4313 orrs r3, r2 800ca80: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800ca82: 687b ldr r3, [r7, #4] 800ca84: 681b ldr r3, [r3, #0] 800ca86: 68ba ldr r2, [r7, #8] 800ca88: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 800ca8a: 687b ldr r3, [r7, #4] 800ca8c: 2201 movs r2, #1 800ca8e: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 800ca92: 687b ldr r3, [r7, #4] 800ca94: 2200 movs r2, #0 800ca96: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 800ca9a: 2300 movs r3, #0 } 800ca9c: 4618 mov r0, r3 800ca9e: 3714 adds r7, #20 800caa0: 46bd mov sp, r7 800caa2: f85d 7b04 ldr.w r7, [sp], #4 800caa6: 4770 bx lr 800caa8: 40010000 .word 0x40010000 800caac: 40010400 .word 0x40010400 800cab0: 40000400 .word 0x40000400 800cab4: 40000800 .word 0x40000800 800cab8: 40000c00 .word 0x40000c00 800cabc: 40001800 .word 0x40001800 800cac0: 40014000 .word 0x40014000 800cac4: 4000e000 .word 0x4000e000 800cac8: 4000e400 .word 0x4000e400 0800cacc : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 800cacc: b480 push {r7} 800cace: b083 sub sp, #12 800cad0: af00 add r7, sp, #0 800cad2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 800cad4: bf00 nop 800cad6: 370c adds r7, #12 800cad8: 46bd mov sp, r7 800cada: f85d 7b04 ldr.w r7, [sp], #4 800cade: 4770 bx lr 0800cae0 : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 800cae0: b480 push {r7} 800cae2: b083 sub sp, #12 800cae4: af00 add r7, sp, #0 800cae6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 800cae8: bf00 nop 800caea: 370c adds r7, #12 800caec: 46bd mov sp, r7 800caee: f85d 7b04 ldr.w r7, [sp], #4 800caf2: 4770 bx lr 0800caf4 : * @brief Hall Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 800caf4: b480 push {r7} 800caf6: b083 sub sp, #12 800caf8: af00 add r7, sp, #0 800cafa: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 800cafc: bf00 nop 800cafe: 370c adds r7, #12 800cb00: 46bd mov sp, r7 800cb02: f85d 7b04 ldr.w r7, [sp], #4 800cb06: 4770 bx lr 0800cb08 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 800cb08: b580 push {r7, lr} 800cb0a: b082 sub sp, #8 800cb0c: af00 add r7, sp, #0 800cb0e: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 800cb10: 687b ldr r3, [r7, #4] 800cb12: 2b00 cmp r3, #0 800cb14: d101 bne.n 800cb1a { return HAL_ERROR; 800cb16: 2301 movs r3, #1 800cb18: e042 b.n 800cba0 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 800cb1a: 687b ldr r3, [r7, #4] 800cb1c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 800cb20: 2b00 cmp r3, #0 800cb22: d106 bne.n 800cb32 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800cb24: 687b ldr r3, [r7, #4] 800cb26: 2200 movs r2, #0 800cb28: f883 2084 strb.w r2, [r3, #132] ; 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 800cb2c: 6878 ldr r0, [r7, #4] 800cb2e: f7f4 fefd bl 800192c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 800cb32: 687b ldr r3, [r7, #4] 800cb34: 2224 movs r2, #36 ; 0x24 800cb36: f8c3 2088 str.w r2, [r3, #136] ; 0x88 __HAL_UART_DISABLE(huart); 800cb3a: 687b ldr r3, [r7, #4] 800cb3c: 681b ldr r3, [r3, #0] 800cb3e: 681a ldr r2, [r3, #0] 800cb40: 687b ldr r3, [r7, #4] 800cb42: 681b ldr r3, [r3, #0] 800cb44: f022 0201 bic.w r2, r2, #1 800cb48: 601a str r2, [r3, #0] /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 800cb4a: 6878 ldr r0, [r7, #4] 800cb4c: f000 f82c bl 800cba8 800cb50: 4603 mov r3, r0 800cb52: 2b01 cmp r3, #1 800cb54: d101 bne.n 800cb5a { return HAL_ERROR; 800cb56: 2301 movs r3, #1 800cb58: e022 b.n 800cba0 } if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 800cb5a: 687b ldr r3, [r7, #4] 800cb5c: 6a9b ldr r3, [r3, #40] ; 0x28 800cb5e: 2b00 cmp r3, #0 800cb60: d002 beq.n 800cb68 { UART_AdvFeatureConfig(huart); 800cb62: 6878 ldr r0, [r7, #4] 800cb64: f000 fe8c bl 800d880 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800cb68: 687b ldr r3, [r7, #4] 800cb6a: 681b ldr r3, [r3, #0] 800cb6c: 685a ldr r2, [r3, #4] 800cb6e: 687b ldr r3, [r7, #4] 800cb70: 681b ldr r3, [r3, #0] 800cb72: f422 4290 bic.w r2, r2, #18432 ; 0x4800 800cb76: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 800cb78: 687b ldr r3, [r7, #4] 800cb7a: 681b ldr r3, [r3, #0] 800cb7c: 689a ldr r2, [r3, #8] 800cb7e: 687b ldr r3, [r7, #4] 800cb80: 681b ldr r3, [r3, #0] 800cb82: f022 022a bic.w r2, r2, #42 ; 0x2a 800cb86: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 800cb88: 687b ldr r3, [r7, #4] 800cb8a: 681b ldr r3, [r3, #0] 800cb8c: 681a ldr r2, [r3, #0] 800cb8e: 687b ldr r3, [r7, #4] 800cb90: 681b ldr r3, [r3, #0] 800cb92: f042 0201 orr.w r2, r2, #1 800cb96: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 800cb98: 6878 ldr r0, [r7, #4] 800cb9a: f000 ff13 bl 800d9c4 800cb9e: 4603 mov r3, r0 } 800cba0: 4618 mov r0, r3 800cba2: 3708 adds r7, #8 800cba4: 46bd mov sp, r7 800cba6: bd80 pop {r7, pc} 0800cba8 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 800cba8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800cbac: b092 sub sp, #72 ; 0x48 800cbae: af00 add r7, sp, #0 800cbb0: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 800cbb2: 2300 movs r3, #0 800cbb4: f887 3042 strb.w r3, [r7, #66] ; 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800cbb8: 697b ldr r3, [r7, #20] 800cbba: 689a ldr r2, [r3, #8] 800cbbc: 697b ldr r3, [r7, #20] 800cbbe: 691b ldr r3, [r3, #16] 800cbc0: 431a orrs r2, r3 800cbc2: 697b ldr r3, [r7, #20] 800cbc4: 695b ldr r3, [r3, #20] 800cbc6: 431a orrs r2, r3 800cbc8: 697b ldr r3, [r7, #20] 800cbca: 69db ldr r3, [r3, #28] 800cbcc: 4313 orrs r3, r2 800cbce: 647b str r3, [r7, #68] ; 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 800cbd0: 697b ldr r3, [r7, #20] 800cbd2: 681b ldr r3, [r3, #0] 800cbd4: 681a ldr r2, [r3, #0] 800cbd6: 4bbe ldr r3, [pc, #760] ; (800ced0 ) 800cbd8: 4013 ands r3, r2 800cbda: 697a ldr r2, [r7, #20] 800cbdc: 6812 ldr r2, [r2, #0] 800cbde: 6c79 ldr r1, [r7, #68] ; 0x44 800cbe0: 430b orrs r3, r1 800cbe2: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800cbe4: 697b ldr r3, [r7, #20] 800cbe6: 681b ldr r3, [r3, #0] 800cbe8: 685b ldr r3, [r3, #4] 800cbea: f423 5140 bic.w r1, r3, #12288 ; 0x3000 800cbee: 697b ldr r3, [r7, #20] 800cbf0: 68da ldr r2, [r3, #12] 800cbf2: 697b ldr r3, [r7, #20] 800cbf4: 681b ldr r3, [r3, #0] 800cbf6: 430a orrs r2, r1 800cbf8: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 800cbfa: 697b ldr r3, [r7, #20] 800cbfc: 699b ldr r3, [r3, #24] 800cbfe: 647b str r3, [r7, #68] ; 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 800cc00: 697b ldr r3, [r7, #20] 800cc02: 681b ldr r3, [r3, #0] 800cc04: 4ab3 ldr r2, [pc, #716] ; (800ced4 ) 800cc06: 4293 cmp r3, r2 800cc08: d004 beq.n 800cc14 { tmpreg |= huart->Init.OneBitSampling; 800cc0a: 697b ldr r3, [r7, #20] 800cc0c: 6a1b ldr r3, [r3, #32] 800cc0e: 6c7a ldr r2, [r7, #68] ; 0x44 800cc10: 4313 orrs r3, r2 800cc12: 647b str r3, [r7, #68] ; 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 800cc14: 697b ldr r3, [r7, #20] 800cc16: 681b ldr r3, [r3, #0] 800cc18: 689a ldr r2, [r3, #8] 800cc1a: 4baf ldr r3, [pc, #700] ; (800ced8 ) 800cc1c: 4013 ands r3, r2 800cc1e: 697a ldr r2, [r7, #20] 800cc20: 6812 ldr r2, [r2, #0] 800cc22: 6c79 ldr r1, [r7, #68] ; 0x44 800cc24: 430b orrs r3, r1 800cc26: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 800cc28: 697b ldr r3, [r7, #20] 800cc2a: 681b ldr r3, [r3, #0] 800cc2c: 6adb ldr r3, [r3, #44] ; 0x2c 800cc2e: f023 010f bic.w r1, r3, #15 800cc32: 697b ldr r3, [r7, #20] 800cc34: 6a5a ldr r2, [r3, #36] ; 0x24 800cc36: 697b ldr r3, [r7, #20] 800cc38: 681b ldr r3, [r3, #0] 800cc3a: 430a orrs r2, r1 800cc3c: 62da str r2, [r3, #44] ; 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 800cc3e: 697b ldr r3, [r7, #20] 800cc40: 681b ldr r3, [r3, #0] 800cc42: 4aa6 ldr r2, [pc, #664] ; (800cedc ) 800cc44: 4293 cmp r3, r2 800cc46: d177 bne.n 800cd38 800cc48: 4ba5 ldr r3, [pc, #660] ; (800cee0 ) 800cc4a: 6d5b ldr r3, [r3, #84] ; 0x54 800cc4c: f003 0338 and.w r3, r3, #56 ; 0x38 800cc50: 2b28 cmp r3, #40 ; 0x28 800cc52: d86d bhi.n 800cd30 800cc54: a201 add r2, pc, #4 ; (adr r2, 800cc5c ) 800cc56: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cc5a: bf00 nop 800cc5c: 0800cd01 .word 0x0800cd01 800cc60: 0800cd31 .word 0x0800cd31 800cc64: 0800cd31 .word 0x0800cd31 800cc68: 0800cd31 .word 0x0800cd31 800cc6c: 0800cd31 .word 0x0800cd31 800cc70: 0800cd31 .word 0x0800cd31 800cc74: 0800cd31 .word 0x0800cd31 800cc78: 0800cd31 .word 0x0800cd31 800cc7c: 0800cd09 .word 0x0800cd09 800cc80: 0800cd31 .word 0x0800cd31 800cc84: 0800cd31 .word 0x0800cd31 800cc88: 0800cd31 .word 0x0800cd31 800cc8c: 0800cd31 .word 0x0800cd31 800cc90: 0800cd31 .word 0x0800cd31 800cc94: 0800cd31 .word 0x0800cd31 800cc98: 0800cd31 .word 0x0800cd31 800cc9c: 0800cd11 .word 0x0800cd11 800cca0: 0800cd31 .word 0x0800cd31 800cca4: 0800cd31 .word 0x0800cd31 800cca8: 0800cd31 .word 0x0800cd31 800ccac: 0800cd31 .word 0x0800cd31 800ccb0: 0800cd31 .word 0x0800cd31 800ccb4: 0800cd31 .word 0x0800cd31 800ccb8: 0800cd31 .word 0x0800cd31 800ccbc: 0800cd19 .word 0x0800cd19 800ccc0: 0800cd31 .word 0x0800cd31 800ccc4: 0800cd31 .word 0x0800cd31 800ccc8: 0800cd31 .word 0x0800cd31 800cccc: 0800cd31 .word 0x0800cd31 800ccd0: 0800cd31 .word 0x0800cd31 800ccd4: 0800cd31 .word 0x0800cd31 800ccd8: 0800cd31 .word 0x0800cd31 800ccdc: 0800cd21 .word 0x0800cd21 800cce0: 0800cd31 .word 0x0800cd31 800cce4: 0800cd31 .word 0x0800cd31 800cce8: 0800cd31 .word 0x0800cd31 800ccec: 0800cd31 .word 0x0800cd31 800ccf0: 0800cd31 .word 0x0800cd31 800ccf4: 0800cd31 .word 0x0800cd31 800ccf8: 0800cd31 .word 0x0800cd31 800ccfc: 0800cd29 .word 0x0800cd29 800cd00: 2301 movs r3, #1 800cd02: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd06: e326 b.n 800d356 800cd08: 2304 movs r3, #4 800cd0a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd0e: e322 b.n 800d356 800cd10: 2308 movs r3, #8 800cd12: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd16: e31e b.n 800d356 800cd18: 2310 movs r3, #16 800cd1a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd1e: e31a b.n 800d356 800cd20: 2320 movs r3, #32 800cd22: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd26: e316 b.n 800d356 800cd28: 2340 movs r3, #64 ; 0x40 800cd2a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd2e: e312 b.n 800d356 800cd30: 2380 movs r3, #128 ; 0x80 800cd32: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd36: e30e b.n 800d356 800cd38: 697b ldr r3, [r7, #20] 800cd3a: 681b ldr r3, [r3, #0] 800cd3c: 4a69 ldr r2, [pc, #420] ; (800cee4 ) 800cd3e: 4293 cmp r3, r2 800cd40: d130 bne.n 800cda4 800cd42: 4b67 ldr r3, [pc, #412] ; (800cee0 ) 800cd44: 6d5b ldr r3, [r3, #84] ; 0x54 800cd46: f003 0307 and.w r3, r3, #7 800cd4a: 2b05 cmp r3, #5 800cd4c: d826 bhi.n 800cd9c 800cd4e: a201 add r2, pc, #4 ; (adr r2, 800cd54 ) 800cd50: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cd54: 0800cd6d .word 0x0800cd6d 800cd58: 0800cd75 .word 0x0800cd75 800cd5c: 0800cd7d .word 0x0800cd7d 800cd60: 0800cd85 .word 0x0800cd85 800cd64: 0800cd8d .word 0x0800cd8d 800cd68: 0800cd95 .word 0x0800cd95 800cd6c: 2300 movs r3, #0 800cd6e: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd72: e2f0 b.n 800d356 800cd74: 2304 movs r3, #4 800cd76: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd7a: e2ec b.n 800d356 800cd7c: 2308 movs r3, #8 800cd7e: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd82: e2e8 b.n 800d356 800cd84: 2310 movs r3, #16 800cd86: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd8a: e2e4 b.n 800d356 800cd8c: 2320 movs r3, #32 800cd8e: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd92: e2e0 b.n 800d356 800cd94: 2340 movs r3, #64 ; 0x40 800cd96: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cd9a: e2dc b.n 800d356 800cd9c: 2380 movs r3, #128 ; 0x80 800cd9e: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cda2: e2d8 b.n 800d356 800cda4: 697b ldr r3, [r7, #20] 800cda6: 681b ldr r3, [r3, #0] 800cda8: 4a4f ldr r2, [pc, #316] ; (800cee8 ) 800cdaa: 4293 cmp r3, r2 800cdac: d130 bne.n 800ce10 800cdae: 4b4c ldr r3, [pc, #304] ; (800cee0 ) 800cdb0: 6d5b ldr r3, [r3, #84] ; 0x54 800cdb2: f003 0307 and.w r3, r3, #7 800cdb6: 2b05 cmp r3, #5 800cdb8: d826 bhi.n 800ce08 800cdba: a201 add r2, pc, #4 ; (adr r2, 800cdc0 ) 800cdbc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cdc0: 0800cdd9 .word 0x0800cdd9 800cdc4: 0800cde1 .word 0x0800cde1 800cdc8: 0800cde9 .word 0x0800cde9 800cdcc: 0800cdf1 .word 0x0800cdf1 800cdd0: 0800cdf9 .word 0x0800cdf9 800cdd4: 0800ce01 .word 0x0800ce01 800cdd8: 2300 movs r3, #0 800cdda: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cdde: e2ba b.n 800d356 800cde0: 2304 movs r3, #4 800cde2: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cde6: e2b6 b.n 800d356 800cde8: 2308 movs r3, #8 800cdea: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cdee: e2b2 b.n 800d356 800cdf0: 2310 movs r3, #16 800cdf2: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cdf6: e2ae b.n 800d356 800cdf8: 2320 movs r3, #32 800cdfa: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cdfe: e2aa b.n 800d356 800ce00: 2340 movs r3, #64 ; 0x40 800ce02: f887 3043 strb.w r3, [r7, #67] ; 0x43 800ce06: e2a6 b.n 800d356 800ce08: 2380 movs r3, #128 ; 0x80 800ce0a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800ce0e: e2a2 b.n 800d356 800ce10: 697b ldr r3, [r7, #20] 800ce12: 681b ldr r3, [r3, #0] 800ce14: 4a35 ldr r2, [pc, #212] ; (800ceec ) 800ce16: 4293 cmp r3, r2 800ce18: d130 bne.n 800ce7c 800ce1a: 4b31 ldr r3, [pc, #196] ; (800cee0 ) 800ce1c: 6d5b ldr r3, [r3, #84] ; 0x54 800ce1e: f003 0307 and.w r3, r3, #7 800ce22: 2b05 cmp r3, #5 800ce24: d826 bhi.n 800ce74 800ce26: a201 add r2, pc, #4 ; (adr r2, 800ce2c ) 800ce28: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ce2c: 0800ce45 .word 0x0800ce45 800ce30: 0800ce4d .word 0x0800ce4d 800ce34: 0800ce55 .word 0x0800ce55 800ce38: 0800ce5d .word 0x0800ce5d 800ce3c: 0800ce65 .word 0x0800ce65 800ce40: 0800ce6d .word 0x0800ce6d 800ce44: 2300 movs r3, #0 800ce46: f887 3043 strb.w r3, [r7, #67] ; 0x43 800ce4a: e284 b.n 800d356 800ce4c: 2304 movs r3, #4 800ce4e: f887 3043 strb.w r3, [r7, #67] ; 0x43 800ce52: e280 b.n 800d356 800ce54: 2308 movs r3, #8 800ce56: f887 3043 strb.w r3, [r7, #67] ; 0x43 800ce5a: e27c b.n 800d356 800ce5c: 2310 movs r3, #16 800ce5e: f887 3043 strb.w r3, [r7, #67] ; 0x43 800ce62: e278 b.n 800d356 800ce64: 2320 movs r3, #32 800ce66: f887 3043 strb.w r3, [r7, #67] ; 0x43 800ce6a: e274 b.n 800d356 800ce6c: 2340 movs r3, #64 ; 0x40 800ce6e: f887 3043 strb.w r3, [r7, #67] ; 0x43 800ce72: e270 b.n 800d356 800ce74: 2380 movs r3, #128 ; 0x80 800ce76: f887 3043 strb.w r3, [r7, #67] ; 0x43 800ce7a: e26c b.n 800d356 800ce7c: 697b ldr r3, [r7, #20] 800ce7e: 681b ldr r3, [r3, #0] 800ce80: 4a1b ldr r2, [pc, #108] ; (800cef0 ) 800ce82: 4293 cmp r3, r2 800ce84: d142 bne.n 800cf0c 800ce86: 4b16 ldr r3, [pc, #88] ; (800cee0 ) 800ce88: 6d5b ldr r3, [r3, #84] ; 0x54 800ce8a: f003 0307 and.w r3, r3, #7 800ce8e: 2b05 cmp r3, #5 800ce90: d838 bhi.n 800cf04 800ce92: a201 add r2, pc, #4 ; (adr r2, 800ce98 ) 800ce94: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ce98: 0800ceb1 .word 0x0800ceb1 800ce9c: 0800ceb9 .word 0x0800ceb9 800cea0: 0800cec1 .word 0x0800cec1 800cea4: 0800cec9 .word 0x0800cec9 800cea8: 0800cef5 .word 0x0800cef5 800ceac: 0800cefd .word 0x0800cefd 800ceb0: 2300 movs r3, #0 800ceb2: f887 3043 strb.w r3, [r7, #67] ; 0x43 800ceb6: e24e b.n 800d356 800ceb8: 2304 movs r3, #4 800ceba: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cebe: e24a b.n 800d356 800cec0: 2308 movs r3, #8 800cec2: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cec6: e246 b.n 800d356 800cec8: 2310 movs r3, #16 800ceca: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cece: e242 b.n 800d356 800ced0: cfff69f3 .word 0xcfff69f3 800ced4: 58000c00 .word 0x58000c00 800ced8: 11fff4ff .word 0x11fff4ff 800cedc: 40011000 .word 0x40011000 800cee0: 58024400 .word 0x58024400 800cee4: 40004400 .word 0x40004400 800cee8: 40004800 .word 0x40004800 800ceec: 40004c00 .word 0x40004c00 800cef0: 40005000 .word 0x40005000 800cef4: 2320 movs r3, #32 800cef6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cefa: e22c b.n 800d356 800cefc: 2340 movs r3, #64 ; 0x40 800cefe: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cf02: e228 b.n 800d356 800cf04: 2380 movs r3, #128 ; 0x80 800cf06: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cf0a: e224 b.n 800d356 800cf0c: 697b ldr r3, [r7, #20] 800cf0e: 681b ldr r3, [r3, #0] 800cf10: 4ab1 ldr r2, [pc, #708] ; (800d1d8 ) 800cf12: 4293 cmp r3, r2 800cf14: d176 bne.n 800d004 800cf16: 4bb1 ldr r3, [pc, #708] ; (800d1dc ) 800cf18: 6d5b ldr r3, [r3, #84] ; 0x54 800cf1a: f003 0338 and.w r3, r3, #56 ; 0x38 800cf1e: 2b28 cmp r3, #40 ; 0x28 800cf20: d86c bhi.n 800cffc 800cf22: a201 add r2, pc, #4 ; (adr r2, 800cf28 ) 800cf24: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cf28: 0800cfcd .word 0x0800cfcd 800cf2c: 0800cffd .word 0x0800cffd 800cf30: 0800cffd .word 0x0800cffd 800cf34: 0800cffd .word 0x0800cffd 800cf38: 0800cffd .word 0x0800cffd 800cf3c: 0800cffd .word 0x0800cffd 800cf40: 0800cffd .word 0x0800cffd 800cf44: 0800cffd .word 0x0800cffd 800cf48: 0800cfd5 .word 0x0800cfd5 800cf4c: 0800cffd .word 0x0800cffd 800cf50: 0800cffd .word 0x0800cffd 800cf54: 0800cffd .word 0x0800cffd 800cf58: 0800cffd .word 0x0800cffd 800cf5c: 0800cffd .word 0x0800cffd 800cf60: 0800cffd .word 0x0800cffd 800cf64: 0800cffd .word 0x0800cffd 800cf68: 0800cfdd .word 0x0800cfdd 800cf6c: 0800cffd .word 0x0800cffd 800cf70: 0800cffd .word 0x0800cffd 800cf74: 0800cffd .word 0x0800cffd 800cf78: 0800cffd .word 0x0800cffd 800cf7c: 0800cffd .word 0x0800cffd 800cf80: 0800cffd .word 0x0800cffd 800cf84: 0800cffd .word 0x0800cffd 800cf88: 0800cfe5 .word 0x0800cfe5 800cf8c: 0800cffd .word 0x0800cffd 800cf90: 0800cffd .word 0x0800cffd 800cf94: 0800cffd .word 0x0800cffd 800cf98: 0800cffd .word 0x0800cffd 800cf9c: 0800cffd .word 0x0800cffd 800cfa0: 0800cffd .word 0x0800cffd 800cfa4: 0800cffd .word 0x0800cffd 800cfa8: 0800cfed .word 0x0800cfed 800cfac: 0800cffd .word 0x0800cffd 800cfb0: 0800cffd .word 0x0800cffd 800cfb4: 0800cffd .word 0x0800cffd 800cfb8: 0800cffd .word 0x0800cffd 800cfbc: 0800cffd .word 0x0800cffd 800cfc0: 0800cffd .word 0x0800cffd 800cfc4: 0800cffd .word 0x0800cffd 800cfc8: 0800cff5 .word 0x0800cff5 800cfcc: 2301 movs r3, #1 800cfce: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cfd2: e1c0 b.n 800d356 800cfd4: 2304 movs r3, #4 800cfd6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cfda: e1bc b.n 800d356 800cfdc: 2308 movs r3, #8 800cfde: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cfe2: e1b8 b.n 800d356 800cfe4: 2310 movs r3, #16 800cfe6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cfea: e1b4 b.n 800d356 800cfec: 2320 movs r3, #32 800cfee: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cff2: e1b0 b.n 800d356 800cff4: 2340 movs r3, #64 ; 0x40 800cff6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800cffa: e1ac b.n 800d356 800cffc: 2380 movs r3, #128 ; 0x80 800cffe: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d002: e1a8 b.n 800d356 800d004: 697b ldr r3, [r7, #20] 800d006: 681b ldr r3, [r3, #0] 800d008: 4a75 ldr r2, [pc, #468] ; (800d1e0 ) 800d00a: 4293 cmp r3, r2 800d00c: d130 bne.n 800d070 800d00e: 4b73 ldr r3, [pc, #460] ; (800d1dc ) 800d010: 6d5b ldr r3, [r3, #84] ; 0x54 800d012: f003 0307 and.w r3, r3, #7 800d016: 2b05 cmp r3, #5 800d018: d826 bhi.n 800d068 800d01a: a201 add r2, pc, #4 ; (adr r2, 800d020 ) 800d01c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d020: 0800d039 .word 0x0800d039 800d024: 0800d041 .word 0x0800d041 800d028: 0800d049 .word 0x0800d049 800d02c: 0800d051 .word 0x0800d051 800d030: 0800d059 .word 0x0800d059 800d034: 0800d061 .word 0x0800d061 800d038: 2300 movs r3, #0 800d03a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d03e: e18a b.n 800d356 800d040: 2304 movs r3, #4 800d042: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d046: e186 b.n 800d356 800d048: 2308 movs r3, #8 800d04a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d04e: e182 b.n 800d356 800d050: 2310 movs r3, #16 800d052: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d056: e17e b.n 800d356 800d058: 2320 movs r3, #32 800d05a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d05e: e17a b.n 800d356 800d060: 2340 movs r3, #64 ; 0x40 800d062: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d066: e176 b.n 800d356 800d068: 2380 movs r3, #128 ; 0x80 800d06a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d06e: e172 b.n 800d356 800d070: 697b ldr r3, [r7, #20] 800d072: 681b ldr r3, [r3, #0] 800d074: 4a5b ldr r2, [pc, #364] ; (800d1e4 ) 800d076: 4293 cmp r3, r2 800d078: d130 bne.n 800d0dc 800d07a: 4b58 ldr r3, [pc, #352] ; (800d1dc ) 800d07c: 6d5b ldr r3, [r3, #84] ; 0x54 800d07e: f003 0307 and.w r3, r3, #7 800d082: 2b05 cmp r3, #5 800d084: d826 bhi.n 800d0d4 800d086: a201 add r2, pc, #4 ; (adr r2, 800d08c ) 800d088: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d08c: 0800d0a5 .word 0x0800d0a5 800d090: 0800d0ad .word 0x0800d0ad 800d094: 0800d0b5 .word 0x0800d0b5 800d098: 0800d0bd .word 0x0800d0bd 800d09c: 0800d0c5 .word 0x0800d0c5 800d0a0: 0800d0cd .word 0x0800d0cd 800d0a4: 2300 movs r3, #0 800d0a6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d0aa: e154 b.n 800d356 800d0ac: 2304 movs r3, #4 800d0ae: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d0b2: e150 b.n 800d356 800d0b4: 2308 movs r3, #8 800d0b6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d0ba: e14c b.n 800d356 800d0bc: 2310 movs r3, #16 800d0be: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d0c2: e148 b.n 800d356 800d0c4: 2320 movs r3, #32 800d0c6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d0ca: e144 b.n 800d356 800d0cc: 2340 movs r3, #64 ; 0x40 800d0ce: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d0d2: e140 b.n 800d356 800d0d4: 2380 movs r3, #128 ; 0x80 800d0d6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d0da: e13c b.n 800d356 800d0dc: 697b ldr r3, [r7, #20] 800d0de: 681b ldr r3, [r3, #0] 800d0e0: 4a41 ldr r2, [pc, #260] ; (800d1e8 ) 800d0e2: 4293 cmp r3, r2 800d0e4: f040 8082 bne.w 800d1ec 800d0e8: 4b3c ldr r3, [pc, #240] ; (800d1dc ) 800d0ea: 6d5b ldr r3, [r3, #84] ; 0x54 800d0ec: f003 0338 and.w r3, r3, #56 ; 0x38 800d0f0: 2b28 cmp r3, #40 ; 0x28 800d0f2: d86d bhi.n 800d1d0 800d0f4: a201 add r2, pc, #4 ; (adr r2, 800d0fc ) 800d0f6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d0fa: bf00 nop 800d0fc: 0800d1a1 .word 0x0800d1a1 800d100: 0800d1d1 .word 0x0800d1d1 800d104: 0800d1d1 .word 0x0800d1d1 800d108: 0800d1d1 .word 0x0800d1d1 800d10c: 0800d1d1 .word 0x0800d1d1 800d110: 0800d1d1 .word 0x0800d1d1 800d114: 0800d1d1 .word 0x0800d1d1 800d118: 0800d1d1 .word 0x0800d1d1 800d11c: 0800d1a9 .word 0x0800d1a9 800d120: 0800d1d1 .word 0x0800d1d1 800d124: 0800d1d1 .word 0x0800d1d1 800d128: 0800d1d1 .word 0x0800d1d1 800d12c: 0800d1d1 .word 0x0800d1d1 800d130: 0800d1d1 .word 0x0800d1d1 800d134: 0800d1d1 .word 0x0800d1d1 800d138: 0800d1d1 .word 0x0800d1d1 800d13c: 0800d1b1 .word 0x0800d1b1 800d140: 0800d1d1 .word 0x0800d1d1 800d144: 0800d1d1 .word 0x0800d1d1 800d148: 0800d1d1 .word 0x0800d1d1 800d14c: 0800d1d1 .word 0x0800d1d1 800d150: 0800d1d1 .word 0x0800d1d1 800d154: 0800d1d1 .word 0x0800d1d1 800d158: 0800d1d1 .word 0x0800d1d1 800d15c: 0800d1b9 .word 0x0800d1b9 800d160: 0800d1d1 .word 0x0800d1d1 800d164: 0800d1d1 .word 0x0800d1d1 800d168: 0800d1d1 .word 0x0800d1d1 800d16c: 0800d1d1 .word 0x0800d1d1 800d170: 0800d1d1 .word 0x0800d1d1 800d174: 0800d1d1 .word 0x0800d1d1 800d178: 0800d1d1 .word 0x0800d1d1 800d17c: 0800d1c1 .word 0x0800d1c1 800d180: 0800d1d1 .word 0x0800d1d1 800d184: 0800d1d1 .word 0x0800d1d1 800d188: 0800d1d1 .word 0x0800d1d1 800d18c: 0800d1d1 .word 0x0800d1d1 800d190: 0800d1d1 .word 0x0800d1d1 800d194: 0800d1d1 .word 0x0800d1d1 800d198: 0800d1d1 .word 0x0800d1d1 800d19c: 0800d1c9 .word 0x0800d1c9 800d1a0: 2301 movs r3, #1 800d1a2: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d1a6: e0d6 b.n 800d356 800d1a8: 2304 movs r3, #4 800d1aa: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d1ae: e0d2 b.n 800d356 800d1b0: 2308 movs r3, #8 800d1b2: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d1b6: e0ce b.n 800d356 800d1b8: 2310 movs r3, #16 800d1ba: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d1be: e0ca b.n 800d356 800d1c0: 2320 movs r3, #32 800d1c2: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d1c6: e0c6 b.n 800d356 800d1c8: 2340 movs r3, #64 ; 0x40 800d1ca: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d1ce: e0c2 b.n 800d356 800d1d0: 2380 movs r3, #128 ; 0x80 800d1d2: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d1d6: e0be b.n 800d356 800d1d8: 40011400 .word 0x40011400 800d1dc: 58024400 .word 0x58024400 800d1e0: 40007800 .word 0x40007800 800d1e4: 40007c00 .word 0x40007c00 800d1e8: 40011800 .word 0x40011800 800d1ec: 697b ldr r3, [r7, #20] 800d1ee: 681b ldr r3, [r3, #0] 800d1f0: 4aad ldr r2, [pc, #692] ; (800d4a8 ) 800d1f2: 4293 cmp r3, r2 800d1f4: d176 bne.n 800d2e4 800d1f6: 4bad ldr r3, [pc, #692] ; (800d4ac ) 800d1f8: 6d5b ldr r3, [r3, #84] ; 0x54 800d1fa: f003 0338 and.w r3, r3, #56 ; 0x38 800d1fe: 2b28 cmp r3, #40 ; 0x28 800d200: d86c bhi.n 800d2dc 800d202: a201 add r2, pc, #4 ; (adr r2, 800d208 ) 800d204: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d208: 0800d2ad .word 0x0800d2ad 800d20c: 0800d2dd .word 0x0800d2dd 800d210: 0800d2dd .word 0x0800d2dd 800d214: 0800d2dd .word 0x0800d2dd 800d218: 0800d2dd .word 0x0800d2dd 800d21c: 0800d2dd .word 0x0800d2dd 800d220: 0800d2dd .word 0x0800d2dd 800d224: 0800d2dd .word 0x0800d2dd 800d228: 0800d2b5 .word 0x0800d2b5 800d22c: 0800d2dd .word 0x0800d2dd 800d230: 0800d2dd .word 0x0800d2dd 800d234: 0800d2dd .word 0x0800d2dd 800d238: 0800d2dd .word 0x0800d2dd 800d23c: 0800d2dd .word 0x0800d2dd 800d240: 0800d2dd .word 0x0800d2dd 800d244: 0800d2dd .word 0x0800d2dd 800d248: 0800d2bd .word 0x0800d2bd 800d24c: 0800d2dd .word 0x0800d2dd 800d250: 0800d2dd .word 0x0800d2dd 800d254: 0800d2dd .word 0x0800d2dd 800d258: 0800d2dd .word 0x0800d2dd 800d25c: 0800d2dd .word 0x0800d2dd 800d260: 0800d2dd .word 0x0800d2dd 800d264: 0800d2dd .word 0x0800d2dd 800d268: 0800d2c5 .word 0x0800d2c5 800d26c: 0800d2dd .word 0x0800d2dd 800d270: 0800d2dd .word 0x0800d2dd 800d274: 0800d2dd .word 0x0800d2dd 800d278: 0800d2dd .word 0x0800d2dd 800d27c: 0800d2dd .word 0x0800d2dd 800d280: 0800d2dd .word 0x0800d2dd 800d284: 0800d2dd .word 0x0800d2dd 800d288: 0800d2cd .word 0x0800d2cd 800d28c: 0800d2dd .word 0x0800d2dd 800d290: 0800d2dd .word 0x0800d2dd 800d294: 0800d2dd .word 0x0800d2dd 800d298: 0800d2dd .word 0x0800d2dd 800d29c: 0800d2dd .word 0x0800d2dd 800d2a0: 0800d2dd .word 0x0800d2dd 800d2a4: 0800d2dd .word 0x0800d2dd 800d2a8: 0800d2d5 .word 0x0800d2d5 800d2ac: 2301 movs r3, #1 800d2ae: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d2b2: e050 b.n 800d356 800d2b4: 2304 movs r3, #4 800d2b6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d2ba: e04c b.n 800d356 800d2bc: 2308 movs r3, #8 800d2be: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d2c2: e048 b.n 800d356 800d2c4: 2310 movs r3, #16 800d2c6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d2ca: e044 b.n 800d356 800d2cc: 2320 movs r3, #32 800d2ce: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d2d2: e040 b.n 800d356 800d2d4: 2340 movs r3, #64 ; 0x40 800d2d6: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d2da: e03c b.n 800d356 800d2dc: 2380 movs r3, #128 ; 0x80 800d2de: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d2e2: e038 b.n 800d356 800d2e4: 697b ldr r3, [r7, #20] 800d2e6: 681b ldr r3, [r3, #0] 800d2e8: 4a71 ldr r2, [pc, #452] ; (800d4b0 ) 800d2ea: 4293 cmp r3, r2 800d2ec: d130 bne.n 800d350 800d2ee: 4b6f ldr r3, [pc, #444] ; (800d4ac ) 800d2f0: 6d9b ldr r3, [r3, #88] ; 0x58 800d2f2: f003 0307 and.w r3, r3, #7 800d2f6: 2b05 cmp r3, #5 800d2f8: d826 bhi.n 800d348 800d2fa: a201 add r2, pc, #4 ; (adr r2, 800d300 ) 800d2fc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d300: 0800d319 .word 0x0800d319 800d304: 0800d321 .word 0x0800d321 800d308: 0800d329 .word 0x0800d329 800d30c: 0800d331 .word 0x0800d331 800d310: 0800d339 .word 0x0800d339 800d314: 0800d341 .word 0x0800d341 800d318: 2302 movs r3, #2 800d31a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d31e: e01a b.n 800d356 800d320: 2304 movs r3, #4 800d322: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d326: e016 b.n 800d356 800d328: 2308 movs r3, #8 800d32a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d32e: e012 b.n 800d356 800d330: 2310 movs r3, #16 800d332: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d336: e00e b.n 800d356 800d338: 2320 movs r3, #32 800d33a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d33e: e00a b.n 800d356 800d340: 2340 movs r3, #64 ; 0x40 800d342: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d346: e006 b.n 800d356 800d348: 2380 movs r3, #128 ; 0x80 800d34a: f887 3043 strb.w r3, [r7, #67] ; 0x43 800d34e: e002 b.n 800d356 800d350: 2380 movs r3, #128 ; 0x80 800d352: f887 3043 strb.w r3, [r7, #67] ; 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 800d356: 697b ldr r3, [r7, #20] 800d358: 681b ldr r3, [r3, #0] 800d35a: 4a55 ldr r2, [pc, #340] ; (800d4b0 ) 800d35c: 4293 cmp r3, r2 800d35e: f040 80f8 bne.w 800d552 { /* Retrieve frequency clock */ switch (clocksource) 800d362: f897 3043 ldrb.w r3, [r7, #67] ; 0x43 800d366: 2b20 cmp r3, #32 800d368: dc46 bgt.n 800d3f8 800d36a: 2b02 cmp r3, #2 800d36c: db75 blt.n 800d45a 800d36e: 3b02 subs r3, #2 800d370: 2b1e cmp r3, #30 800d372: d872 bhi.n 800d45a 800d374: a201 add r2, pc, #4 ; (adr r2, 800d37c ) 800d376: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d37a: bf00 nop 800d37c: 0800d3ff .word 0x0800d3ff 800d380: 0800d45b .word 0x0800d45b 800d384: 0800d407 .word 0x0800d407 800d388: 0800d45b .word 0x0800d45b 800d38c: 0800d45b .word 0x0800d45b 800d390: 0800d45b .word 0x0800d45b 800d394: 0800d417 .word 0x0800d417 800d398: 0800d45b .word 0x0800d45b 800d39c: 0800d45b .word 0x0800d45b 800d3a0: 0800d45b .word 0x0800d45b 800d3a4: 0800d45b .word 0x0800d45b 800d3a8: 0800d45b .word 0x0800d45b 800d3ac: 0800d45b .word 0x0800d45b 800d3b0: 0800d45b .word 0x0800d45b 800d3b4: 0800d427 .word 0x0800d427 800d3b8: 0800d45b .word 0x0800d45b 800d3bc: 0800d45b .word 0x0800d45b 800d3c0: 0800d45b .word 0x0800d45b 800d3c4: 0800d45b .word 0x0800d45b 800d3c8: 0800d45b .word 0x0800d45b 800d3cc: 0800d45b .word 0x0800d45b 800d3d0: 0800d45b .word 0x0800d45b 800d3d4: 0800d45b .word 0x0800d45b 800d3d8: 0800d45b .word 0x0800d45b 800d3dc: 0800d45b .word 0x0800d45b 800d3e0: 0800d45b .word 0x0800d45b 800d3e4: 0800d45b .word 0x0800d45b 800d3e8: 0800d45b .word 0x0800d45b 800d3ec: 0800d45b .word 0x0800d45b 800d3f0: 0800d45b .word 0x0800d45b 800d3f4: 0800d44d .word 0x0800d44d 800d3f8: 2b40 cmp r3, #64 ; 0x40 800d3fa: d02a beq.n 800d452 800d3fc: e02d b.n 800d45a { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 800d3fe: f7fc fc8f bl 8009d20 800d402: 63f8 str r0, [r7, #60] ; 0x3c break; 800d404: e02f b.n 800d466 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800d406: f107 0324 add.w r3, r7, #36 ; 0x24 800d40a: 4618 mov r0, r3 800d40c: f7fc fc9e bl 8009d4c pclk = pll2_clocks.PLL2_Q_Frequency; 800d410: 6abb ldr r3, [r7, #40] ; 0x28 800d412: 63fb str r3, [r7, #60] ; 0x3c break; 800d414: e027 b.n 800d466 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800d416: f107 0318 add.w r3, r7, #24 800d41a: 4618 mov r0, r3 800d41c: f7fc fdea bl 8009ff4 pclk = pll3_clocks.PLL3_Q_Frequency; 800d420: 69fb ldr r3, [r7, #28] 800d422: 63fb str r3, [r7, #60] ; 0x3c break; 800d424: e01f b.n 800d466 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800d426: 4b21 ldr r3, [pc, #132] ; (800d4ac ) 800d428: 681b ldr r3, [r3, #0] 800d42a: f003 0320 and.w r3, r3, #32 800d42e: 2b00 cmp r3, #0 800d430: d009 beq.n 800d446 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800d432: 4b1e ldr r3, [pc, #120] ; (800d4ac ) 800d434: 681b ldr r3, [r3, #0] 800d436: 08db lsrs r3, r3, #3 800d438: f003 0303 and.w r3, r3, #3 800d43c: 4a1d ldr r2, [pc, #116] ; (800d4b4 ) 800d43e: fa22 f303 lsr.w r3, r2, r3 800d442: 63fb str r3, [r7, #60] ; 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 800d444: e00f b.n 800d466 pclk = (uint32_t) HSI_VALUE; 800d446: 4b1b ldr r3, [pc, #108] ; (800d4b4 ) 800d448: 63fb str r3, [r7, #60] ; 0x3c break; 800d44a: e00c b.n 800d466 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 800d44c: 4b1a ldr r3, [pc, #104] ; (800d4b8 ) 800d44e: 63fb str r3, [r7, #60] ; 0x3c break; 800d450: e009 b.n 800d466 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800d452: f44f 4300 mov.w r3, #32768 ; 0x8000 800d456: 63fb str r3, [r7, #60] ; 0x3c break; 800d458: e005 b.n 800d466 default: pclk = 0U; 800d45a: 2300 movs r3, #0 800d45c: 63fb str r3, [r7, #60] ; 0x3c ret = HAL_ERROR; 800d45e: 2301 movs r3, #1 800d460: f887 3042 strb.w r3, [r7, #66] ; 0x42 break; 800d464: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 800d466: 6bfb ldr r3, [r7, #60] ; 0x3c 800d468: 2b00 cmp r3, #0 800d46a: f000 81ee beq.w 800d84a { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 800d46e: 697b ldr r3, [r7, #20] 800d470: 6a5b ldr r3, [r3, #36] ; 0x24 800d472: 4a12 ldr r2, [pc, #72] ; (800d4bc ) 800d474: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800d478: 461a mov r2, r3 800d47a: 6bfb ldr r3, [r7, #60] ; 0x3c 800d47c: fbb3 f3f2 udiv r3, r3, r2 800d480: 633b str r3, [r7, #48] ; 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 800d482: 697b ldr r3, [r7, #20] 800d484: 685a ldr r2, [r3, #4] 800d486: 4613 mov r3, r2 800d488: 005b lsls r3, r3, #1 800d48a: 4413 add r3, r2 800d48c: 6b3a ldr r2, [r7, #48] ; 0x30 800d48e: 429a cmp r2, r3 800d490: d305 bcc.n 800d49e (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 800d492: 697b ldr r3, [r7, #20] 800d494: 685b ldr r3, [r3, #4] 800d496: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 800d498: 6b3a ldr r2, [r7, #48] ; 0x30 800d49a: 429a cmp r2, r3 800d49c: d910 bls.n 800d4c0 { ret = HAL_ERROR; 800d49e: 2301 movs r3, #1 800d4a0: f887 3042 strb.w r3, [r7, #66] ; 0x42 800d4a4: e1d1 b.n 800d84a 800d4a6: bf00 nop 800d4a8: 40011c00 .word 0x40011c00 800d4ac: 58024400 .word 0x58024400 800d4b0: 58000c00 .word 0x58000c00 800d4b4: 03d09000 .word 0x03d09000 800d4b8: 003d0900 .word 0x003d0900 800d4bc: 08026b58 .word 0x08026b58 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800d4c0: 6bfb ldr r3, [r7, #60] ; 0x3c 800d4c2: 2200 movs r2, #0 800d4c4: 60bb str r3, [r7, #8] 800d4c6: 60fa str r2, [r7, #12] 800d4c8: 697b ldr r3, [r7, #20] 800d4ca: 6a5b ldr r3, [r3, #36] ; 0x24 800d4cc: 4ac0 ldr r2, [pc, #768] ; (800d7d0 ) 800d4ce: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800d4d2: b29b uxth r3, r3 800d4d4: 2200 movs r2, #0 800d4d6: 603b str r3, [r7, #0] 800d4d8: 607a str r2, [r7, #4] 800d4da: e9d7 2300 ldrd r2, r3, [r7] 800d4de: e9d7 0102 ldrd r0, r1, [r7, #8] 800d4e2: f7f2 ff7d bl 80003e0 <__aeabi_uldivmod> 800d4e6: 4602 mov r2, r0 800d4e8: 460b mov r3, r1 800d4ea: 4610 mov r0, r2 800d4ec: 4619 mov r1, r3 800d4ee: f04f 0200 mov.w r2, #0 800d4f2: f04f 0300 mov.w r3, #0 800d4f6: 020b lsls r3, r1, #8 800d4f8: ea43 6310 orr.w r3, r3, r0, lsr #24 800d4fc: 0202 lsls r2, r0, #8 800d4fe: 6979 ldr r1, [r7, #20] 800d500: 6849 ldr r1, [r1, #4] 800d502: 0849 lsrs r1, r1, #1 800d504: 2000 movs r0, #0 800d506: 460c mov r4, r1 800d508: 4605 mov r5, r0 800d50a: eb12 0804 adds.w r8, r2, r4 800d50e: eb43 0905 adc.w r9, r3, r5 800d512: 697b ldr r3, [r7, #20] 800d514: 685b ldr r3, [r3, #4] 800d516: 2200 movs r2, #0 800d518: 469a mov sl, r3 800d51a: 4693 mov fp, r2 800d51c: 4652 mov r2, sl 800d51e: 465b mov r3, fp 800d520: 4640 mov r0, r8 800d522: 4649 mov r1, r9 800d524: f7f2 ff5c bl 80003e0 <__aeabi_uldivmod> 800d528: 4602 mov r2, r0 800d52a: 460b mov r3, r1 800d52c: 4613 mov r3, r2 800d52e: 63bb str r3, [r7, #56] ; 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 800d530: 6bbb ldr r3, [r7, #56] ; 0x38 800d532: f5b3 7f40 cmp.w r3, #768 ; 0x300 800d536: d308 bcc.n 800d54a 800d538: 6bbb ldr r3, [r7, #56] ; 0x38 800d53a: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800d53e: d204 bcs.n 800d54a { huart->Instance->BRR = usartdiv; 800d540: 697b ldr r3, [r7, #20] 800d542: 681b ldr r3, [r3, #0] 800d544: 6bba ldr r2, [r7, #56] ; 0x38 800d546: 60da str r2, [r3, #12] 800d548: e17f b.n 800d84a } else { ret = HAL_ERROR; 800d54a: 2301 movs r3, #1 800d54c: f887 3042 strb.w r3, [r7, #66] ; 0x42 800d550: e17b b.n 800d84a } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800d552: 697b ldr r3, [r7, #20] 800d554: 69db ldr r3, [r3, #28] 800d556: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 800d55a: f040 80bd bne.w 800d6d8 { switch (clocksource) 800d55e: f897 3043 ldrb.w r3, [r7, #67] ; 0x43 800d562: 2b20 cmp r3, #32 800d564: dc48 bgt.n 800d5f8 800d566: 2b00 cmp r3, #0 800d568: db7b blt.n 800d662 800d56a: 2b20 cmp r3, #32 800d56c: d879 bhi.n 800d662 800d56e: a201 add r2, pc, #4 ; (adr r2, 800d574 ) 800d570: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d574: 0800d5ff .word 0x0800d5ff 800d578: 0800d607 .word 0x0800d607 800d57c: 0800d663 .word 0x0800d663 800d580: 0800d663 .word 0x0800d663 800d584: 0800d60f .word 0x0800d60f 800d588: 0800d663 .word 0x0800d663 800d58c: 0800d663 .word 0x0800d663 800d590: 0800d663 .word 0x0800d663 800d594: 0800d61f .word 0x0800d61f 800d598: 0800d663 .word 0x0800d663 800d59c: 0800d663 .word 0x0800d663 800d5a0: 0800d663 .word 0x0800d663 800d5a4: 0800d663 .word 0x0800d663 800d5a8: 0800d663 .word 0x0800d663 800d5ac: 0800d663 .word 0x0800d663 800d5b0: 0800d663 .word 0x0800d663 800d5b4: 0800d62f .word 0x0800d62f 800d5b8: 0800d663 .word 0x0800d663 800d5bc: 0800d663 .word 0x0800d663 800d5c0: 0800d663 .word 0x0800d663 800d5c4: 0800d663 .word 0x0800d663 800d5c8: 0800d663 .word 0x0800d663 800d5cc: 0800d663 .word 0x0800d663 800d5d0: 0800d663 .word 0x0800d663 800d5d4: 0800d663 .word 0x0800d663 800d5d8: 0800d663 .word 0x0800d663 800d5dc: 0800d663 .word 0x0800d663 800d5e0: 0800d663 .word 0x0800d663 800d5e4: 0800d663 .word 0x0800d663 800d5e8: 0800d663 .word 0x0800d663 800d5ec: 0800d663 .word 0x0800d663 800d5f0: 0800d663 .word 0x0800d663 800d5f4: 0800d655 .word 0x0800d655 800d5f8: 2b40 cmp r3, #64 ; 0x40 800d5fa: d02e beq.n 800d65a 800d5fc: e031 b.n 800d662 { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 800d5fe: f7fa fcaf bl 8007f60 800d602: 63f8 str r0, [r7, #60] ; 0x3c break; 800d604: e033 b.n 800d66e case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 800d606: f7fa fcc1 bl 8007f8c 800d60a: 63f8 str r0, [r7, #60] ; 0x3c break; 800d60c: e02f b.n 800d66e case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800d60e: f107 0324 add.w r3, r7, #36 ; 0x24 800d612: 4618 mov r0, r3 800d614: f7fc fb9a bl 8009d4c pclk = pll2_clocks.PLL2_Q_Frequency; 800d618: 6abb ldr r3, [r7, #40] ; 0x28 800d61a: 63fb str r3, [r7, #60] ; 0x3c break; 800d61c: e027 b.n 800d66e case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800d61e: f107 0318 add.w r3, r7, #24 800d622: 4618 mov r0, r3 800d624: f7fc fce6 bl 8009ff4 pclk = pll3_clocks.PLL3_Q_Frequency; 800d628: 69fb ldr r3, [r7, #28] 800d62a: 63fb str r3, [r7, #60] ; 0x3c break; 800d62c: e01f b.n 800d66e case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800d62e: 4b69 ldr r3, [pc, #420] ; (800d7d4 ) 800d630: 681b ldr r3, [r3, #0] 800d632: f003 0320 and.w r3, r3, #32 800d636: 2b00 cmp r3, #0 800d638: d009 beq.n 800d64e { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800d63a: 4b66 ldr r3, [pc, #408] ; (800d7d4 ) 800d63c: 681b ldr r3, [r3, #0] 800d63e: 08db lsrs r3, r3, #3 800d640: f003 0303 and.w r3, r3, #3 800d644: 4a64 ldr r2, [pc, #400] ; (800d7d8 ) 800d646: fa22 f303 lsr.w r3, r2, r3 800d64a: 63fb str r3, [r7, #60] ; 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 800d64c: e00f b.n 800d66e pclk = (uint32_t) HSI_VALUE; 800d64e: 4b62 ldr r3, [pc, #392] ; (800d7d8 ) 800d650: 63fb str r3, [r7, #60] ; 0x3c break; 800d652: e00c b.n 800d66e case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 800d654: 4b61 ldr r3, [pc, #388] ; (800d7dc ) 800d656: 63fb str r3, [r7, #60] ; 0x3c break; 800d658: e009 b.n 800d66e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800d65a: f44f 4300 mov.w r3, #32768 ; 0x8000 800d65e: 63fb str r3, [r7, #60] ; 0x3c break; 800d660: e005 b.n 800d66e default: pclk = 0U; 800d662: 2300 movs r3, #0 800d664: 63fb str r3, [r7, #60] ; 0x3c ret = HAL_ERROR; 800d666: 2301 movs r3, #1 800d668: f887 3042 strb.w r3, [r7, #66] ; 0x42 break; 800d66c: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 800d66e: 6bfb ldr r3, [r7, #60] ; 0x3c 800d670: 2b00 cmp r3, #0 800d672: f000 80ea beq.w 800d84a { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800d676: 697b ldr r3, [r7, #20] 800d678: 6a5b ldr r3, [r3, #36] ; 0x24 800d67a: 4a55 ldr r2, [pc, #340] ; (800d7d0 ) 800d67c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800d680: 461a mov r2, r3 800d682: 6bfb ldr r3, [r7, #60] ; 0x3c 800d684: fbb3 f3f2 udiv r3, r3, r2 800d688: 005a lsls r2, r3, #1 800d68a: 697b ldr r3, [r7, #20] 800d68c: 685b ldr r3, [r3, #4] 800d68e: 085b lsrs r3, r3, #1 800d690: 441a add r2, r3 800d692: 697b ldr r3, [r7, #20] 800d694: 685b ldr r3, [r3, #4] 800d696: fbb2 f3f3 udiv r3, r2, r3 800d69a: 63bb str r3, [r7, #56] ; 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800d69c: 6bbb ldr r3, [r7, #56] ; 0x38 800d69e: 2b0f cmp r3, #15 800d6a0: d916 bls.n 800d6d0 800d6a2: 6bbb ldr r3, [r7, #56] ; 0x38 800d6a4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800d6a8: d212 bcs.n 800d6d0 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 800d6aa: 6bbb ldr r3, [r7, #56] ; 0x38 800d6ac: b29b uxth r3, r3 800d6ae: f023 030f bic.w r3, r3, #15 800d6b2: 86fb strh r3, [r7, #54] ; 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 800d6b4: 6bbb ldr r3, [r7, #56] ; 0x38 800d6b6: 085b lsrs r3, r3, #1 800d6b8: b29b uxth r3, r3 800d6ba: f003 0307 and.w r3, r3, #7 800d6be: b29a uxth r2, r3 800d6c0: 8efb ldrh r3, [r7, #54] ; 0x36 800d6c2: 4313 orrs r3, r2 800d6c4: 86fb strh r3, [r7, #54] ; 0x36 huart->Instance->BRR = brrtemp; 800d6c6: 697b ldr r3, [r7, #20] 800d6c8: 681b ldr r3, [r3, #0] 800d6ca: 8efa ldrh r2, [r7, #54] ; 0x36 800d6cc: 60da str r2, [r3, #12] 800d6ce: e0bc b.n 800d84a } else { ret = HAL_ERROR; 800d6d0: 2301 movs r3, #1 800d6d2: f887 3042 strb.w r3, [r7, #66] ; 0x42 800d6d6: e0b8 b.n 800d84a } } } else { switch (clocksource) 800d6d8: f897 3043 ldrb.w r3, [r7, #67] ; 0x43 800d6dc: 2b20 cmp r3, #32 800d6de: dc4b bgt.n 800d778 800d6e0: 2b00 cmp r3, #0 800d6e2: f2c0 8087 blt.w 800d7f4 800d6e6: 2b20 cmp r3, #32 800d6e8: f200 8084 bhi.w 800d7f4 800d6ec: a201 add r2, pc, #4 ; (adr r2, 800d6f4 ) 800d6ee: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d6f2: bf00 nop 800d6f4: 0800d77f .word 0x0800d77f 800d6f8: 0800d787 .word 0x0800d787 800d6fc: 0800d7f5 .word 0x0800d7f5 800d700: 0800d7f5 .word 0x0800d7f5 800d704: 0800d78f .word 0x0800d78f 800d708: 0800d7f5 .word 0x0800d7f5 800d70c: 0800d7f5 .word 0x0800d7f5 800d710: 0800d7f5 .word 0x0800d7f5 800d714: 0800d79f .word 0x0800d79f 800d718: 0800d7f5 .word 0x0800d7f5 800d71c: 0800d7f5 .word 0x0800d7f5 800d720: 0800d7f5 .word 0x0800d7f5 800d724: 0800d7f5 .word 0x0800d7f5 800d728: 0800d7f5 .word 0x0800d7f5 800d72c: 0800d7f5 .word 0x0800d7f5 800d730: 0800d7f5 .word 0x0800d7f5 800d734: 0800d7af .word 0x0800d7af 800d738: 0800d7f5 .word 0x0800d7f5 800d73c: 0800d7f5 .word 0x0800d7f5 800d740: 0800d7f5 .word 0x0800d7f5 800d744: 0800d7f5 .word 0x0800d7f5 800d748: 0800d7f5 .word 0x0800d7f5 800d74c: 0800d7f5 .word 0x0800d7f5 800d750: 0800d7f5 .word 0x0800d7f5 800d754: 0800d7f5 .word 0x0800d7f5 800d758: 0800d7f5 .word 0x0800d7f5 800d75c: 0800d7f5 .word 0x0800d7f5 800d760: 0800d7f5 .word 0x0800d7f5 800d764: 0800d7f5 .word 0x0800d7f5 800d768: 0800d7f5 .word 0x0800d7f5 800d76c: 0800d7f5 .word 0x0800d7f5 800d770: 0800d7f5 .word 0x0800d7f5 800d774: 0800d7e7 .word 0x0800d7e7 800d778: 2b40 cmp r3, #64 ; 0x40 800d77a: d037 beq.n 800d7ec 800d77c: e03a b.n 800d7f4 { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 800d77e: f7fa fbef bl 8007f60 800d782: 63f8 str r0, [r7, #60] ; 0x3c break; 800d784: e03c b.n 800d800 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 800d786: f7fa fc01 bl 8007f8c 800d78a: 63f8 str r0, [r7, #60] ; 0x3c break; 800d78c: e038 b.n 800d800 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800d78e: f107 0324 add.w r3, r7, #36 ; 0x24 800d792: 4618 mov r0, r3 800d794: f7fc fada bl 8009d4c pclk = pll2_clocks.PLL2_Q_Frequency; 800d798: 6abb ldr r3, [r7, #40] ; 0x28 800d79a: 63fb str r3, [r7, #60] ; 0x3c break; 800d79c: e030 b.n 800d800 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800d79e: f107 0318 add.w r3, r7, #24 800d7a2: 4618 mov r0, r3 800d7a4: f7fc fc26 bl 8009ff4 pclk = pll3_clocks.PLL3_Q_Frequency; 800d7a8: 69fb ldr r3, [r7, #28] 800d7aa: 63fb str r3, [r7, #60] ; 0x3c break; 800d7ac: e028 b.n 800d800 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800d7ae: 4b09 ldr r3, [pc, #36] ; (800d7d4 ) 800d7b0: 681b ldr r3, [r3, #0] 800d7b2: f003 0320 and.w r3, r3, #32 800d7b6: 2b00 cmp r3, #0 800d7b8: d012 beq.n 800d7e0 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800d7ba: 4b06 ldr r3, [pc, #24] ; (800d7d4 ) 800d7bc: 681b ldr r3, [r3, #0] 800d7be: 08db lsrs r3, r3, #3 800d7c0: f003 0303 and.w r3, r3, #3 800d7c4: 4a04 ldr r2, [pc, #16] ; (800d7d8 ) 800d7c6: fa22 f303 lsr.w r3, r2, r3 800d7ca: 63fb str r3, [r7, #60] ; 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 800d7cc: e018 b.n 800d800 800d7ce: bf00 nop 800d7d0: 08026b58 .word 0x08026b58 800d7d4: 58024400 .word 0x58024400 800d7d8: 03d09000 .word 0x03d09000 800d7dc: 003d0900 .word 0x003d0900 pclk = (uint32_t) HSI_VALUE; 800d7e0: 4b24 ldr r3, [pc, #144] ; (800d874 ) 800d7e2: 63fb str r3, [r7, #60] ; 0x3c break; 800d7e4: e00c b.n 800d800 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 800d7e6: 4b24 ldr r3, [pc, #144] ; (800d878 ) 800d7e8: 63fb str r3, [r7, #60] ; 0x3c break; 800d7ea: e009 b.n 800d800 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800d7ec: f44f 4300 mov.w r3, #32768 ; 0x8000 800d7f0: 63fb str r3, [r7, #60] ; 0x3c break; 800d7f2: e005 b.n 800d800 default: pclk = 0U; 800d7f4: 2300 movs r3, #0 800d7f6: 63fb str r3, [r7, #60] ; 0x3c ret = HAL_ERROR; 800d7f8: 2301 movs r3, #1 800d7fa: f887 3042 strb.w r3, [r7, #66] ; 0x42 break; 800d7fe: bf00 nop } if (pclk != 0U) 800d800: 6bfb ldr r3, [r7, #60] ; 0x3c 800d802: 2b00 cmp r3, #0 800d804: d021 beq.n 800d84a { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800d806: 697b ldr r3, [r7, #20] 800d808: 6a5b ldr r3, [r3, #36] ; 0x24 800d80a: 4a1c ldr r2, [pc, #112] ; (800d87c ) 800d80c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800d810: 461a mov r2, r3 800d812: 6bfb ldr r3, [r7, #60] ; 0x3c 800d814: fbb3 f2f2 udiv r2, r3, r2 800d818: 697b ldr r3, [r7, #20] 800d81a: 685b ldr r3, [r3, #4] 800d81c: 085b lsrs r3, r3, #1 800d81e: 441a add r2, r3 800d820: 697b ldr r3, [r7, #20] 800d822: 685b ldr r3, [r3, #4] 800d824: fbb2 f3f3 udiv r3, r2, r3 800d828: 63bb str r3, [r7, #56] ; 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800d82a: 6bbb ldr r3, [r7, #56] ; 0x38 800d82c: 2b0f cmp r3, #15 800d82e: d909 bls.n 800d844 800d830: 6bbb ldr r3, [r7, #56] ; 0x38 800d832: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800d836: d205 bcs.n 800d844 { huart->Instance->BRR = (uint16_t)usartdiv; 800d838: 6bbb ldr r3, [r7, #56] ; 0x38 800d83a: b29a uxth r2, r3 800d83c: 697b ldr r3, [r7, #20] 800d83e: 681b ldr r3, [r3, #0] 800d840: 60da str r2, [r3, #12] 800d842: e002 b.n 800d84a } else { ret = HAL_ERROR; 800d844: 2301 movs r3, #1 800d846: f887 3042 strb.w r3, [r7, #66] ; 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 800d84a: 697b ldr r3, [r7, #20] 800d84c: 2201 movs r2, #1 800d84e: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = 1; 800d852: 697b ldr r3, [r7, #20] 800d854: 2201 movs r2, #1 800d856: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 800d85a: 697b ldr r3, [r7, #20] 800d85c: 2200 movs r2, #0 800d85e: 675a str r2, [r3, #116] ; 0x74 huart->TxISR = NULL; 800d860: 697b ldr r3, [r7, #20] 800d862: 2200 movs r2, #0 800d864: 679a str r2, [r3, #120] ; 0x78 return ret; 800d866: f897 3042 ldrb.w r3, [r7, #66] ; 0x42 } 800d86a: 4618 mov r0, r3 800d86c: 3748 adds r7, #72 ; 0x48 800d86e: 46bd mov sp, r7 800d870: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800d874: 03d09000 .word 0x03d09000 800d878: 003d0900 .word 0x003d0900 800d87c: 08026b58 .word 0x08026b58 0800d880 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 800d880: b480 push {r7} 800d882: b083 sub sp, #12 800d884: af00 add r7, sp, #0 800d886: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 800d888: 687b ldr r3, [r7, #4] 800d88a: 6a9b ldr r3, [r3, #40] ; 0x28 800d88c: f003 0301 and.w r3, r3, #1 800d890: 2b00 cmp r3, #0 800d892: d00a beq.n 800d8aa { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 800d894: 687b ldr r3, [r7, #4] 800d896: 681b ldr r3, [r3, #0] 800d898: 685b ldr r3, [r3, #4] 800d89a: f423 3100 bic.w r1, r3, #131072 ; 0x20000 800d89e: 687b ldr r3, [r7, #4] 800d8a0: 6ada ldr r2, [r3, #44] ; 0x2c 800d8a2: 687b ldr r3, [r7, #4] 800d8a4: 681b ldr r3, [r3, #0] 800d8a6: 430a orrs r2, r1 800d8a8: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 800d8aa: 687b ldr r3, [r7, #4] 800d8ac: 6a9b ldr r3, [r3, #40] ; 0x28 800d8ae: f003 0302 and.w r3, r3, #2 800d8b2: 2b00 cmp r3, #0 800d8b4: d00a beq.n 800d8cc { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 800d8b6: 687b ldr r3, [r7, #4] 800d8b8: 681b ldr r3, [r3, #0] 800d8ba: 685b ldr r3, [r3, #4] 800d8bc: f423 3180 bic.w r1, r3, #65536 ; 0x10000 800d8c0: 687b ldr r3, [r7, #4] 800d8c2: 6b1a ldr r2, [r3, #48] ; 0x30 800d8c4: 687b ldr r3, [r7, #4] 800d8c6: 681b ldr r3, [r3, #0] 800d8c8: 430a orrs r2, r1 800d8ca: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 800d8cc: 687b ldr r3, [r7, #4] 800d8ce: 6a9b ldr r3, [r3, #40] ; 0x28 800d8d0: f003 0304 and.w r3, r3, #4 800d8d4: 2b00 cmp r3, #0 800d8d6: d00a beq.n 800d8ee { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 800d8d8: 687b ldr r3, [r7, #4] 800d8da: 681b ldr r3, [r3, #0] 800d8dc: 685b ldr r3, [r3, #4] 800d8de: f423 2180 bic.w r1, r3, #262144 ; 0x40000 800d8e2: 687b ldr r3, [r7, #4] 800d8e4: 6b5a ldr r2, [r3, #52] ; 0x34 800d8e6: 687b ldr r3, [r7, #4] 800d8e8: 681b ldr r3, [r3, #0] 800d8ea: 430a orrs r2, r1 800d8ec: 605a str r2, [r3, #4] } /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 800d8ee: 687b ldr r3, [r7, #4] 800d8f0: 6a9b ldr r3, [r3, #40] ; 0x28 800d8f2: f003 0308 and.w r3, r3, #8 800d8f6: 2b00 cmp r3, #0 800d8f8: d00a beq.n 800d910 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 800d8fa: 687b ldr r3, [r7, #4] 800d8fc: 681b ldr r3, [r3, #0] 800d8fe: 685b ldr r3, [r3, #4] 800d900: f423 4100 bic.w r1, r3, #32768 ; 0x8000 800d904: 687b ldr r3, [r7, #4] 800d906: 6b9a ldr r2, [r3, #56] ; 0x38 800d908: 687b ldr r3, [r7, #4] 800d90a: 681b ldr r3, [r3, #0] 800d90c: 430a orrs r2, r1 800d90e: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 800d910: 687b ldr r3, [r7, #4] 800d912: 6a9b ldr r3, [r3, #40] ; 0x28 800d914: f003 0310 and.w r3, r3, #16 800d918: 2b00 cmp r3, #0 800d91a: d00a beq.n 800d932 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 800d91c: 687b ldr r3, [r7, #4] 800d91e: 681b ldr r3, [r3, #0] 800d920: 689b ldr r3, [r3, #8] 800d922: f423 5180 bic.w r1, r3, #4096 ; 0x1000 800d926: 687b ldr r3, [r7, #4] 800d928: 6bda ldr r2, [r3, #60] ; 0x3c 800d92a: 687b ldr r3, [r7, #4] 800d92c: 681b ldr r3, [r3, #0] 800d92e: 430a orrs r2, r1 800d930: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 800d932: 687b ldr r3, [r7, #4] 800d934: 6a9b ldr r3, [r3, #40] ; 0x28 800d936: f003 0320 and.w r3, r3, #32 800d93a: 2b00 cmp r3, #0 800d93c: d00a beq.n 800d954 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 800d93e: 687b ldr r3, [r7, #4] 800d940: 681b ldr r3, [r3, #0] 800d942: 689b ldr r3, [r3, #8] 800d944: f423 5100 bic.w r1, r3, #8192 ; 0x2000 800d948: 687b ldr r3, [r7, #4] 800d94a: 6c1a ldr r2, [r3, #64] ; 0x40 800d94c: 687b ldr r3, [r7, #4] 800d94e: 681b ldr r3, [r3, #0] 800d950: 430a orrs r2, r1 800d952: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 800d954: 687b ldr r3, [r7, #4] 800d956: 6a9b ldr r3, [r3, #40] ; 0x28 800d958: f003 0340 and.w r3, r3, #64 ; 0x40 800d95c: 2b00 cmp r3, #0 800d95e: d01a beq.n 800d996 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 800d960: 687b ldr r3, [r7, #4] 800d962: 681b ldr r3, [r3, #0] 800d964: 685b ldr r3, [r3, #4] 800d966: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 800d96a: 687b ldr r3, [r7, #4] 800d96c: 6c5a ldr r2, [r3, #68] ; 0x44 800d96e: 687b ldr r3, [r7, #4] 800d970: 681b ldr r3, [r3, #0] 800d972: 430a orrs r2, r1 800d974: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 800d976: 687b ldr r3, [r7, #4] 800d978: 6c5b ldr r3, [r3, #68] ; 0x44 800d97a: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800d97e: d10a bne.n 800d996 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 800d980: 687b ldr r3, [r7, #4] 800d982: 681b ldr r3, [r3, #0] 800d984: 685b ldr r3, [r3, #4] 800d986: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 800d98a: 687b ldr r3, [r7, #4] 800d98c: 6c9a ldr r2, [r3, #72] ; 0x48 800d98e: 687b ldr r3, [r7, #4] 800d990: 681b ldr r3, [r3, #0] 800d992: 430a orrs r2, r1 800d994: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 800d996: 687b ldr r3, [r7, #4] 800d998: 6a9b ldr r3, [r3, #40] ; 0x28 800d99a: f003 0380 and.w r3, r3, #128 ; 0x80 800d99e: 2b00 cmp r3, #0 800d9a0: d00a beq.n 800d9b8 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 800d9a2: 687b ldr r3, [r7, #4] 800d9a4: 681b ldr r3, [r3, #0] 800d9a6: 685b ldr r3, [r3, #4] 800d9a8: f423 2100 bic.w r1, r3, #524288 ; 0x80000 800d9ac: 687b ldr r3, [r7, #4] 800d9ae: 6cda ldr r2, [r3, #76] ; 0x4c 800d9b0: 687b ldr r3, [r7, #4] 800d9b2: 681b ldr r3, [r3, #0] 800d9b4: 430a orrs r2, r1 800d9b6: 605a str r2, [r3, #4] } } 800d9b8: bf00 nop 800d9ba: 370c adds r7, #12 800d9bc: 46bd mov sp, r7 800d9be: f85d 7b04 ldr.w r7, [sp], #4 800d9c2: 4770 bx lr 0800d9c4 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 800d9c4: b580 push {r7, lr} 800d9c6: b098 sub sp, #96 ; 0x60 800d9c8: af02 add r7, sp, #8 800d9ca: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800d9cc: 687b ldr r3, [r7, #4] 800d9ce: 2200 movs r2, #0 800d9d0: f8c3 2090 str.w r2, [r3, #144] ; 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 800d9d4: f7f4 fcc6 bl 8002364 800d9d8: 6578 str r0, [r7, #84] ; 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 800d9da: 687b ldr r3, [r7, #4] 800d9dc: 681b ldr r3, [r3, #0] 800d9de: 681b ldr r3, [r3, #0] 800d9e0: f003 0308 and.w r3, r3, #8 800d9e4: 2b08 cmp r3, #8 800d9e6: d12f bne.n 800da48 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 800d9e8: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 800d9ec: 9300 str r3, [sp, #0] 800d9ee: 6d7b ldr r3, [r7, #84] ; 0x54 800d9f0: 2200 movs r2, #0 800d9f2: f44f 1100 mov.w r1, #2097152 ; 0x200000 800d9f6: 6878 ldr r0, [r7, #4] 800d9f8: f000 f88e bl 800db18 800d9fc: 4603 mov r3, r0 800d9fe: 2b00 cmp r3, #0 800da00: d022 beq.n 800da48 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 800da02: 687b ldr r3, [r7, #4] 800da04: 681b ldr r3, [r3, #0] 800da06: 63bb str r3, [r7, #56] ; 0x38 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800da08: 6bbb ldr r3, [r7, #56] ; 0x38 800da0a: e853 3f00 ldrex r3, [r3] 800da0e: 637b str r3, [r7, #52] ; 0x34 return(result); 800da10: 6b7b ldr r3, [r7, #52] ; 0x34 800da12: f023 0380 bic.w r3, r3, #128 ; 0x80 800da16: 653b str r3, [r7, #80] ; 0x50 800da18: 687b ldr r3, [r7, #4] 800da1a: 681b ldr r3, [r3, #0] 800da1c: 461a mov r2, r3 800da1e: 6d3b ldr r3, [r7, #80] ; 0x50 800da20: 647b str r3, [r7, #68] ; 0x44 800da22: 643a str r2, [r7, #64] ; 0x40 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800da24: 6c39 ldr r1, [r7, #64] ; 0x40 800da26: 6c7a ldr r2, [r7, #68] ; 0x44 800da28: e841 2300 strex r3, r2, [r1] 800da2c: 63fb str r3, [r7, #60] ; 0x3c return(result); 800da2e: 6bfb ldr r3, [r7, #60] ; 0x3c 800da30: 2b00 cmp r3, #0 800da32: d1e6 bne.n 800da02 huart->gState = HAL_UART_STATE_READY; 800da34: 687b ldr r3, [r7, #4] 800da36: 2220 movs r2, #32 800da38: f8c3 2088 str.w r2, [r3, #136] ; 0x88 __HAL_UNLOCK(huart); 800da3c: 687b ldr r3, [r7, #4] 800da3e: 2200 movs r2, #0 800da40: f883 2084 strb.w r2, [r3, #132] ; 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 800da44: 2303 movs r3, #3 800da46: e063 b.n 800db10 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 800da48: 687b ldr r3, [r7, #4] 800da4a: 681b ldr r3, [r3, #0] 800da4c: 681b ldr r3, [r3, #0] 800da4e: f003 0304 and.w r3, r3, #4 800da52: 2b04 cmp r3, #4 800da54: d149 bne.n 800daea { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 800da56: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 800da5a: 9300 str r3, [sp, #0] 800da5c: 6d7b ldr r3, [r7, #84] ; 0x54 800da5e: 2200 movs r2, #0 800da60: f44f 0180 mov.w r1, #4194304 ; 0x400000 800da64: 6878 ldr r0, [r7, #4] 800da66: f000 f857 bl 800db18 800da6a: 4603 mov r3, r0 800da6c: 2b00 cmp r3, #0 800da6e: d03c beq.n 800daea { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800da70: 687b ldr r3, [r7, #4] 800da72: 681b ldr r3, [r3, #0] 800da74: 627b str r3, [r7, #36] ; 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800da76: 6a7b ldr r3, [r7, #36] ; 0x24 800da78: e853 3f00 ldrex r3, [r3] 800da7c: 623b str r3, [r7, #32] return(result); 800da7e: 6a3b ldr r3, [r7, #32] 800da80: f423 7390 bic.w r3, r3, #288 ; 0x120 800da84: 64fb str r3, [r7, #76] ; 0x4c 800da86: 687b ldr r3, [r7, #4] 800da88: 681b ldr r3, [r3, #0] 800da8a: 461a mov r2, r3 800da8c: 6cfb ldr r3, [r7, #76] ; 0x4c 800da8e: 633b str r3, [r7, #48] ; 0x30 800da90: 62fa str r2, [r7, #44] ; 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800da92: 6af9 ldr r1, [r7, #44] ; 0x2c 800da94: 6b3a ldr r2, [r7, #48] ; 0x30 800da96: e841 2300 strex r3, r2, [r1] 800da9a: 62bb str r3, [r7, #40] ; 0x28 return(result); 800da9c: 6abb ldr r3, [r7, #40] ; 0x28 800da9e: 2b00 cmp r3, #0 800daa0: d1e6 bne.n 800da70 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800daa2: 687b ldr r3, [r7, #4] 800daa4: 681b ldr r3, [r3, #0] 800daa6: 3308 adds r3, #8 800daa8: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800daaa: 693b ldr r3, [r7, #16] 800daac: e853 3f00 ldrex r3, [r3] 800dab0: 60fb str r3, [r7, #12] return(result); 800dab2: 68fb ldr r3, [r7, #12] 800dab4: f023 0301 bic.w r3, r3, #1 800dab8: 64bb str r3, [r7, #72] ; 0x48 800daba: 687b ldr r3, [r7, #4] 800dabc: 681b ldr r3, [r3, #0] 800dabe: 3308 adds r3, #8 800dac0: 6cba ldr r2, [r7, #72] ; 0x48 800dac2: 61fa str r2, [r7, #28] 800dac4: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800dac6: 69b9 ldr r1, [r7, #24] 800dac8: 69fa ldr r2, [r7, #28] 800daca: e841 2300 strex r3, r2, [r1] 800dace: 617b str r3, [r7, #20] return(result); 800dad0: 697b ldr r3, [r7, #20] 800dad2: 2b00 cmp r3, #0 800dad4: d1e5 bne.n 800daa2 huart->RxState = HAL_UART_STATE_READY; 800dad6: 687b ldr r3, [r7, #4] 800dad8: 2220 movs r2, #32 800dada: f8c3 208c str.w r2, [r3, #140] ; 0x8c __HAL_UNLOCK(huart); 800dade: 687b ldr r3, [r7, #4] 800dae0: 2200 movs r2, #0 800dae2: f883 2084 strb.w r2, [r3, #132] ; 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 800dae6: 2303 movs r3, #3 800dae8: e012 b.n 800db10 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 800daea: 687b ldr r3, [r7, #4] 800daec: 2220 movs r2, #32 800daee: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->RxState = HAL_UART_STATE_READY; 800daf2: 687b ldr r3, [r7, #4] 800daf4: 2220 movs r2, #32 800daf6: f8c3 208c str.w r2, [r3, #140] ; 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800dafa: 687b ldr r3, [r7, #4] 800dafc: 2200 movs r2, #0 800dafe: 66da str r2, [r3, #108] ; 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 800db00: 687b ldr r3, [r7, #4] 800db02: 2200 movs r2, #0 800db04: 671a str r2, [r3, #112] ; 0x70 __HAL_UNLOCK(huart); 800db06: 687b ldr r3, [r7, #4] 800db08: 2200 movs r2, #0 800db0a: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_OK; 800db0e: 2300 movs r3, #0 } 800db10: 4618 mov r0, r3 800db12: 3758 adds r7, #88 ; 0x58 800db14: 46bd mov sp, r7 800db16: bd80 pop {r7, pc} 0800db18 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 800db18: b580 push {r7, lr} 800db1a: b084 sub sp, #16 800db1c: af00 add r7, sp, #0 800db1e: 60f8 str r0, [r7, #12] 800db20: 60b9 str r1, [r7, #8] 800db22: 603b str r3, [r7, #0] 800db24: 4613 mov r3, r2 800db26: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800db28: e049 b.n 800dbbe { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800db2a: 69bb ldr r3, [r7, #24] 800db2c: f1b3 3fff cmp.w r3, #4294967295 800db30: d045 beq.n 800dbbe { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800db32: f7f4 fc17 bl 8002364 800db36: 4602 mov r2, r0 800db38: 683b ldr r3, [r7, #0] 800db3a: 1ad3 subs r3, r2, r3 800db3c: 69ba ldr r2, [r7, #24] 800db3e: 429a cmp r2, r3 800db40: d302 bcc.n 800db48 800db42: 69bb ldr r3, [r7, #24] 800db44: 2b00 cmp r3, #0 800db46: d101 bne.n 800db4c { return HAL_TIMEOUT; 800db48: 2303 movs r3, #3 800db4a: e048 b.n 800dbde } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) 800db4c: 68fb ldr r3, [r7, #12] 800db4e: 681b ldr r3, [r3, #0] 800db50: 681b ldr r3, [r3, #0] 800db52: f003 0304 and.w r3, r3, #4 800db56: 2b00 cmp r3, #0 800db58: d031 beq.n 800dbbe { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 800db5a: 68fb ldr r3, [r7, #12] 800db5c: 681b ldr r3, [r3, #0] 800db5e: 69db ldr r3, [r3, #28] 800db60: f003 0308 and.w r3, r3, #8 800db64: 2b08 cmp r3, #8 800db66: d110 bne.n 800db8a { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 800db68: 68fb ldr r3, [r7, #12] 800db6a: 681b ldr r3, [r3, #0] 800db6c: 2208 movs r2, #8 800db6e: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 800db70: 68f8 ldr r0, [r7, #12] 800db72: f000 f839 bl 800dbe8 huart->ErrorCode = HAL_UART_ERROR_ORE; 800db76: 68fb ldr r3, [r7, #12] 800db78: 2208 movs r2, #8 800db7a: f8c3 2090 str.w r2, [r3, #144] ; 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 800db7e: 68fb ldr r3, [r7, #12] 800db80: 2200 movs r2, #0 800db82: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_ERROR; 800db86: 2301 movs r3, #1 800db88: e029 b.n 800dbde } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 800db8a: 68fb ldr r3, [r7, #12] 800db8c: 681b ldr r3, [r3, #0] 800db8e: 69db ldr r3, [r3, #28] 800db90: f403 6300 and.w r3, r3, #2048 ; 0x800 800db94: f5b3 6f00 cmp.w r3, #2048 ; 0x800 800db98: d111 bne.n 800dbbe { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 800db9a: 68fb ldr r3, [r7, #12] 800db9c: 681b ldr r3, [r3, #0] 800db9e: f44f 6200 mov.w r2, #2048 ; 0x800 800dba2: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 800dba4: 68f8 ldr r0, [r7, #12] 800dba6: f000 f81f bl 800dbe8 huart->ErrorCode = HAL_UART_ERROR_RTO; 800dbaa: 68fb ldr r3, [r7, #12] 800dbac: 2220 movs r2, #32 800dbae: f8c3 2090 str.w r2, [r3, #144] ; 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 800dbb2: 68fb ldr r3, [r7, #12] 800dbb4: 2200 movs r2, #0 800dbb6: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_TIMEOUT; 800dbba: 2303 movs r3, #3 800dbbc: e00f b.n 800dbde while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800dbbe: 68fb ldr r3, [r7, #12] 800dbc0: 681b ldr r3, [r3, #0] 800dbc2: 69da ldr r2, [r3, #28] 800dbc4: 68bb ldr r3, [r7, #8] 800dbc6: 4013 ands r3, r2 800dbc8: 68ba ldr r2, [r7, #8] 800dbca: 429a cmp r2, r3 800dbcc: bf0c ite eq 800dbce: 2301 moveq r3, #1 800dbd0: 2300 movne r3, #0 800dbd2: b2db uxtb r3, r3 800dbd4: 461a mov r2, r3 800dbd6: 79fb ldrb r3, [r7, #7] 800dbd8: 429a cmp r2, r3 800dbda: d0a6 beq.n 800db2a } } } } return HAL_OK; 800dbdc: 2300 movs r3, #0 } 800dbde: 4618 mov r0, r3 800dbe0: 3710 adds r7, #16 800dbe2: 46bd mov sp, r7 800dbe4: bd80 pop {r7, pc} ... 0800dbe8 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 800dbe8: b480 push {r7} 800dbea: b095 sub sp, #84 ; 0x54 800dbec: af00 add r7, sp, #0 800dbee: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800dbf0: 687b ldr r3, [r7, #4] 800dbf2: 681b ldr r3, [r3, #0] 800dbf4: 637b str r3, [r7, #52] ; 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800dbf6: 6b7b ldr r3, [r7, #52] ; 0x34 800dbf8: e853 3f00 ldrex r3, [r3] 800dbfc: 633b str r3, [r7, #48] ; 0x30 return(result); 800dbfe: 6b3b ldr r3, [r7, #48] ; 0x30 800dc00: f423 7390 bic.w r3, r3, #288 ; 0x120 800dc04: 64fb str r3, [r7, #76] ; 0x4c 800dc06: 687b ldr r3, [r7, #4] 800dc08: 681b ldr r3, [r3, #0] 800dc0a: 461a mov r2, r3 800dc0c: 6cfb ldr r3, [r7, #76] ; 0x4c 800dc0e: 643b str r3, [r7, #64] ; 0x40 800dc10: 63fa str r2, [r7, #60] ; 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800dc12: 6bf9 ldr r1, [r7, #60] ; 0x3c 800dc14: 6c3a ldr r2, [r7, #64] ; 0x40 800dc16: e841 2300 strex r3, r2, [r1] 800dc1a: 63bb str r3, [r7, #56] ; 0x38 return(result); 800dc1c: 6bbb ldr r3, [r7, #56] ; 0x38 800dc1e: 2b00 cmp r3, #0 800dc20: d1e6 bne.n 800dbf0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800dc22: 687b ldr r3, [r7, #4] 800dc24: 681b ldr r3, [r3, #0] 800dc26: 3308 adds r3, #8 800dc28: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800dc2a: 6a3b ldr r3, [r7, #32] 800dc2c: e853 3f00 ldrex r3, [r3] 800dc30: 61fb str r3, [r7, #28] return(result); 800dc32: 69fa ldr r2, [r7, #28] 800dc34: 4b1e ldr r3, [pc, #120] ; (800dcb0 ) 800dc36: 4013 ands r3, r2 800dc38: 64bb str r3, [r7, #72] ; 0x48 800dc3a: 687b ldr r3, [r7, #4] 800dc3c: 681b ldr r3, [r3, #0] 800dc3e: 3308 adds r3, #8 800dc40: 6cba ldr r2, [r7, #72] ; 0x48 800dc42: 62fa str r2, [r7, #44] ; 0x2c 800dc44: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800dc46: 6ab9 ldr r1, [r7, #40] ; 0x28 800dc48: 6afa ldr r2, [r7, #44] ; 0x2c 800dc4a: e841 2300 strex r3, r2, [r1] 800dc4e: 627b str r3, [r7, #36] ; 0x24 return(result); 800dc50: 6a7b ldr r3, [r7, #36] ; 0x24 800dc52: 2b00 cmp r3, #0 800dc54: d1e5 bne.n 800dc22 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800dc56: 687b ldr r3, [r7, #4] 800dc58: 6edb ldr r3, [r3, #108] ; 0x6c 800dc5a: 2b01 cmp r3, #1 800dc5c: d118 bne.n 800dc90 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800dc5e: 687b ldr r3, [r7, #4] 800dc60: 681b ldr r3, [r3, #0] 800dc62: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800dc64: 68fb ldr r3, [r7, #12] 800dc66: e853 3f00 ldrex r3, [r3] 800dc6a: 60bb str r3, [r7, #8] return(result); 800dc6c: 68bb ldr r3, [r7, #8] 800dc6e: f023 0310 bic.w r3, r3, #16 800dc72: 647b str r3, [r7, #68] ; 0x44 800dc74: 687b ldr r3, [r7, #4] 800dc76: 681b ldr r3, [r3, #0] 800dc78: 461a mov r2, r3 800dc7a: 6c7b ldr r3, [r7, #68] ; 0x44 800dc7c: 61bb str r3, [r7, #24] 800dc7e: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800dc80: 6979 ldr r1, [r7, #20] 800dc82: 69ba ldr r2, [r7, #24] 800dc84: e841 2300 strex r3, r2, [r1] 800dc88: 613b str r3, [r7, #16] return(result); 800dc8a: 693b ldr r3, [r7, #16] 800dc8c: 2b00 cmp r3, #0 800dc8e: d1e6 bne.n 800dc5e } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800dc90: 687b ldr r3, [r7, #4] 800dc92: 2220 movs r2, #32 800dc94: f8c3 208c str.w r2, [r3, #140] ; 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800dc98: 687b ldr r3, [r7, #4] 800dc9a: 2200 movs r2, #0 800dc9c: 66da str r2, [r3, #108] ; 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 800dc9e: 687b ldr r3, [r7, #4] 800dca0: 2200 movs r2, #0 800dca2: 675a str r2, [r3, #116] ; 0x74 } 800dca4: bf00 nop 800dca6: 3754 adds r7, #84 ; 0x54 800dca8: 46bd mov sp, r7 800dcaa: f85d 7b04 ldr.w r7, [sp], #4 800dcae: 4770 bx lr 800dcb0: effffffe .word 0xeffffffe 0800dcb4 : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 800dcb4: b480 push {r7} 800dcb6: b085 sub sp, #20 800dcb8: af00 add r7, sp, #0 800dcba: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 800dcbc: 687b ldr r3, [r7, #4] 800dcbe: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 800dcc2: 2b01 cmp r3, #1 800dcc4: d101 bne.n 800dcca 800dcc6: 2302 movs r3, #2 800dcc8: e027 b.n 800dd1a 800dcca: 687b ldr r3, [r7, #4] 800dccc: 2201 movs r2, #1 800dcce: f883 2084 strb.w r2, [r3, #132] ; 0x84 huart->gState = HAL_UART_STATE_BUSY; 800dcd2: 687b ldr r3, [r7, #4] 800dcd4: 2224 movs r2, #36 ; 0x24 800dcd6: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800dcda: 687b ldr r3, [r7, #4] 800dcdc: 681b ldr r3, [r3, #0] 800dcde: 681b ldr r3, [r3, #0] 800dce0: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800dce2: 687b ldr r3, [r7, #4] 800dce4: 681b ldr r3, [r3, #0] 800dce6: 681a ldr r2, [r3, #0] 800dce8: 687b ldr r3, [r7, #4] 800dcea: 681b ldr r3, [r3, #0] 800dcec: f022 0201 bic.w r2, r2, #1 800dcf0: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 800dcf2: 68fb ldr r3, [r7, #12] 800dcf4: f023 5300 bic.w r3, r3, #536870912 ; 0x20000000 800dcf8: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 800dcfa: 687b ldr r3, [r7, #4] 800dcfc: 2200 movs r2, #0 800dcfe: 665a str r2, [r3, #100] ; 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800dd00: 687b ldr r3, [r7, #4] 800dd02: 681b ldr r3, [r3, #0] 800dd04: 68fa ldr r2, [r7, #12] 800dd06: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800dd08: 687b ldr r3, [r7, #4] 800dd0a: 2220 movs r2, #32 800dd0c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800dd10: 687b ldr r3, [r7, #4] 800dd12: 2200 movs r2, #0 800dd14: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_OK; 800dd18: 2300 movs r3, #0 } 800dd1a: 4618 mov r0, r3 800dd1c: 3714 adds r7, #20 800dd1e: 46bd mov sp, r7 800dd20: f85d 7b04 ldr.w r7, [sp], #4 800dd24: 4770 bx lr 0800dd26 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 800dd26: b580 push {r7, lr} 800dd28: b084 sub sp, #16 800dd2a: af00 add r7, sp, #0 800dd2c: 6078 str r0, [r7, #4] 800dd2e: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800dd30: 687b ldr r3, [r7, #4] 800dd32: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 800dd36: 2b01 cmp r3, #1 800dd38: d101 bne.n 800dd3e 800dd3a: 2302 movs r3, #2 800dd3c: e02d b.n 800dd9a 800dd3e: 687b ldr r3, [r7, #4] 800dd40: 2201 movs r2, #1 800dd42: f883 2084 strb.w r2, [r3, #132] ; 0x84 huart->gState = HAL_UART_STATE_BUSY; 800dd46: 687b ldr r3, [r7, #4] 800dd48: 2224 movs r2, #36 ; 0x24 800dd4a: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800dd4e: 687b ldr r3, [r7, #4] 800dd50: 681b ldr r3, [r3, #0] 800dd52: 681b ldr r3, [r3, #0] 800dd54: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800dd56: 687b ldr r3, [r7, #4] 800dd58: 681b ldr r3, [r3, #0] 800dd5a: 681a ldr r2, [r3, #0] 800dd5c: 687b ldr r3, [r7, #4] 800dd5e: 681b ldr r3, [r3, #0] 800dd60: f022 0201 bic.w r2, r2, #1 800dd64: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 800dd66: 687b ldr r3, [r7, #4] 800dd68: 681b ldr r3, [r3, #0] 800dd6a: 689b ldr r3, [r3, #8] 800dd6c: f023 4160 bic.w r1, r3, #3758096384 ; 0xe0000000 800dd70: 687b ldr r3, [r7, #4] 800dd72: 681b ldr r3, [r3, #0] 800dd74: 683a ldr r2, [r7, #0] 800dd76: 430a orrs r2, r1 800dd78: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 800dd7a: 6878 ldr r0, [r7, #4] 800dd7c: f000 f850 bl 800de20 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800dd80: 687b ldr r3, [r7, #4] 800dd82: 681b ldr r3, [r3, #0] 800dd84: 68fa ldr r2, [r7, #12] 800dd86: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800dd88: 687b ldr r3, [r7, #4] 800dd8a: 2220 movs r2, #32 800dd8c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800dd90: 687b ldr r3, [r7, #4] 800dd92: 2200 movs r2, #0 800dd94: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_OK; 800dd98: 2300 movs r3, #0 } 800dd9a: 4618 mov r0, r3 800dd9c: 3710 adds r7, #16 800dd9e: 46bd mov sp, r7 800dda0: bd80 pop {r7, pc} 0800dda2 : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 800dda2: b580 push {r7, lr} 800dda4: b084 sub sp, #16 800dda6: af00 add r7, sp, #0 800dda8: 6078 str r0, [r7, #4] 800ddaa: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800ddac: 687b ldr r3, [r7, #4] 800ddae: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 800ddb2: 2b01 cmp r3, #1 800ddb4: d101 bne.n 800ddba 800ddb6: 2302 movs r3, #2 800ddb8: e02d b.n 800de16 800ddba: 687b ldr r3, [r7, #4] 800ddbc: 2201 movs r2, #1 800ddbe: f883 2084 strb.w r2, [r3, #132] ; 0x84 huart->gState = HAL_UART_STATE_BUSY; 800ddc2: 687b ldr r3, [r7, #4] 800ddc4: 2224 movs r2, #36 ; 0x24 800ddc6: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800ddca: 687b ldr r3, [r7, #4] 800ddcc: 681b ldr r3, [r3, #0] 800ddce: 681b ldr r3, [r3, #0] 800ddd0: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800ddd2: 687b ldr r3, [r7, #4] 800ddd4: 681b ldr r3, [r3, #0] 800ddd6: 681a ldr r2, [r3, #0] 800ddd8: 687b ldr r3, [r7, #4] 800ddda: 681b ldr r3, [r3, #0] 800dddc: f022 0201 bic.w r2, r2, #1 800dde0: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 800dde2: 687b ldr r3, [r7, #4] 800dde4: 681b ldr r3, [r3, #0] 800dde6: 689b ldr r3, [r3, #8] 800dde8: f023 6160 bic.w r1, r3, #234881024 ; 0xe000000 800ddec: 687b ldr r3, [r7, #4] 800ddee: 681b ldr r3, [r3, #0] 800ddf0: 683a ldr r2, [r7, #0] 800ddf2: 430a orrs r2, r1 800ddf4: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 800ddf6: 6878 ldr r0, [r7, #4] 800ddf8: f000 f812 bl 800de20 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800ddfc: 687b ldr r3, [r7, #4] 800ddfe: 681b ldr r3, [r3, #0] 800de00: 68fa ldr r2, [r7, #12] 800de02: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800de04: 687b ldr r3, [r7, #4] 800de06: 2220 movs r2, #32 800de08: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800de0c: 687b ldr r3, [r7, #4] 800de0e: 2200 movs r2, #0 800de10: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_OK; 800de14: 2300 movs r3, #0 } 800de16: 4618 mov r0, r3 800de18: 3710 adds r7, #16 800de1a: 46bd mov sp, r7 800de1c: bd80 pop {r7, pc} ... 0800de20 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 800de20: b480 push {r7} 800de22: b085 sub sp, #20 800de24: af00 add r7, sp, #0 800de26: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 800de28: 687b ldr r3, [r7, #4] 800de2a: 6e5b ldr r3, [r3, #100] ; 0x64 800de2c: 2b00 cmp r3, #0 800de2e: d108 bne.n 800de42 { huart->NbTxDataToProcess = 1U; 800de30: 687b ldr r3, [r7, #4] 800de32: 2201 movs r2, #1 800de34: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = 1U; 800de38: 687b ldr r3, [r7, #4] 800de3a: 2201 movs r2, #1 800de3c: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 800de40: e031 b.n 800dea6 rx_fifo_depth = RX_FIFO_DEPTH; 800de42: 2310 movs r3, #16 800de44: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 800de46: 2310 movs r3, #16 800de48: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 800de4a: 687b ldr r3, [r7, #4] 800de4c: 681b ldr r3, [r3, #0] 800de4e: 689b ldr r3, [r3, #8] 800de50: 0e5b lsrs r3, r3, #25 800de52: b2db uxtb r3, r3 800de54: f003 0307 and.w r3, r3, #7 800de58: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 800de5a: 687b ldr r3, [r7, #4] 800de5c: 681b ldr r3, [r3, #0] 800de5e: 689b ldr r3, [r3, #8] 800de60: 0f5b lsrs r3, r3, #29 800de62: b2db uxtb r3, r3 800de64: f003 0307 and.w r3, r3, #7 800de68: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800de6a: 7bbb ldrb r3, [r7, #14] 800de6c: 7b3a ldrb r2, [r7, #12] 800de6e: 4911 ldr r1, [pc, #68] ; (800deb4 ) 800de70: 5c8a ldrb r2, [r1, r2] 800de72: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 800de76: 7b3a ldrb r2, [r7, #12] 800de78: 490f ldr r1, [pc, #60] ; (800deb8 ) 800de7a: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800de7c: fb93 f3f2 sdiv r3, r3, r2 800de80: b29a uxth r2, r3 800de82: 687b ldr r3, [r7, #4] 800de84: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800de88: 7bfb ldrb r3, [r7, #15] 800de8a: 7b7a ldrb r2, [r7, #13] 800de8c: 4909 ldr r1, [pc, #36] ; (800deb4 ) 800de8e: 5c8a ldrb r2, [r1, r2] 800de90: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 800de94: 7b7a ldrb r2, [r7, #13] 800de96: 4908 ldr r1, [pc, #32] ; (800deb8 ) 800de98: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800de9a: fb93 f3f2 sdiv r3, r3, r2 800de9e: b29a uxth r2, r3 800dea0: 687b ldr r3, [r7, #4] 800dea2: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 } 800dea6: bf00 nop 800dea8: 3714 adds r7, #20 800deaa: 46bd mov sp, r7 800deac: f85d 7b04 ldr.w r7, [sp], #4 800deb0: 4770 bx lr 800deb2: bf00 nop 800deb4: 08026b70 .word 0x08026b70 800deb8: 08026b78 .word 0x08026b78 0800debc : * @param SDMMCx: Pointer to SDMMC register base * @param Init: SDMMC initialization structure * @retval HAL status */ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) { 800debc: b084 sub sp, #16 800debe: b480 push {r7} 800dec0: b085 sub sp, #20 800dec2: af00 add r7, sp, #0 800dec4: 6078 str r0, [r7, #4] 800dec6: f107 001c add.w r0, r7, #28 800deca: e880 000e stmia.w r0, {r1, r2, r3} uint32_t tmpreg = 0; 800dece: 2300 movs r3, #0 800ded0: 60fb str r3, [r7, #12] assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); /* Set SDMMC configuration parameters */ tmpreg |= (Init.ClockEdge | \ 800ded2: 69fa ldr r2, [r7, #28] Init.ClockPowerSave | \ 800ded4: 6a3b ldr r3, [r7, #32] tmpreg |= (Init.ClockEdge | \ 800ded6: 431a orrs r2, r3 Init.BusWide | \ 800ded8: 6a7b ldr r3, [r7, #36] ; 0x24 Init.ClockPowerSave | \ 800deda: 431a orrs r2, r3 Init.HardwareFlowControl | \ 800dedc: 6abb ldr r3, [r7, #40] ; 0x28 Init.BusWide | \ 800dede: 431a orrs r2, r3 Init.ClockDiv 800dee0: 6afb ldr r3, [r7, #44] ; 0x2c Init.HardwareFlowControl | \ 800dee2: 4313 orrs r3, r2 tmpreg |= (Init.ClockEdge | \ 800dee4: 68fa ldr r2, [r7, #12] 800dee6: 4313 orrs r3, r2 800dee8: 60fb str r3, [r7, #12] ); /* Write to SDMMC CLKCR */ MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); 800deea: 687b ldr r3, [r7, #4] 800deec: 685a ldr r2, [r3, #4] 800deee: 4b07 ldr r3, [pc, #28] ; (800df0c ) 800def0: 4013 ands r3, r2 800def2: 68fa ldr r2, [r7, #12] 800def4: 431a orrs r2, r3 800def6: 687b ldr r3, [r7, #4] 800def8: 605a str r2, [r3, #4] return HAL_OK; 800defa: 2300 movs r3, #0 } 800defc: 4618 mov r0, r3 800defe: 3714 adds r7, #20 800df00: 46bd mov sp, r7 800df02: f85d 7b04 ldr.w r7, [sp], #4 800df06: b004 add sp, #16 800df08: 4770 bx lr 800df0a: bf00 nop 800df0c: ffc02c00 .word 0xffc02c00 0800df10 : * @brief Read data (word) from Rx FIFO in blocking mode (polling) * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) { 800df10: b480 push {r7} 800df12: b083 sub sp, #12 800df14: af00 add r7, sp, #0 800df16: 6078 str r0, [r7, #4] /* Read data from Rx FIFO */ return (SDMMCx->FIFO); 800df18: 687b ldr r3, [r7, #4] 800df1a: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 } 800df1e: 4618 mov r0, r3 800df20: 370c adds r7, #12 800df22: 46bd mov sp, r7 800df24: f85d 7b04 ldr.w r7, [sp], #4 800df28: 4770 bx lr 0800df2a : * @param SDMMCx: Pointer to SDMMC register base * @param pWriteData: pointer to data to write * @retval HAL status */ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) { 800df2a: b480 push {r7} 800df2c: b083 sub sp, #12 800df2e: af00 add r7, sp, #0 800df30: 6078 str r0, [r7, #4] 800df32: 6039 str r1, [r7, #0] /* Write data to FIFO */ SDMMCx->FIFO = *pWriteData; 800df34: 683b ldr r3, [r7, #0] 800df36: 681a ldr r2, [r3, #0] 800df38: 687b ldr r3, [r7, #4] 800df3a: f8c3 2080 str.w r2, [r3, #128] ; 0x80 return HAL_OK; 800df3e: 2300 movs r3, #0 } 800df40: 4618 mov r0, r3 800df42: 370c adds r7, #12 800df44: 46bd mov sp, r7 800df46: f85d 7b04 ldr.w r7, [sp], #4 800df4a: 4770 bx lr 0800df4c : * @brief Set SDMMC Power state to ON. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) { 800df4c: b480 push {r7} 800df4e: b083 sub sp, #12 800df50: af00 add r7, sp, #0 800df52: 6078 str r0, [r7, #4] /* Set power state to ON */ SDMMCx->POWER |= SDMMC_POWER_PWRCTRL; 800df54: 687b ldr r3, [r7, #4] 800df56: 681b ldr r3, [r3, #0] 800df58: f043 0203 orr.w r2, r3, #3 800df5c: 687b ldr r3, [r7, #4] 800df5e: 601a str r2, [r3, #0] return HAL_OK; 800df60: 2300 movs r3, #0 } 800df62: 4618 mov r0, r3 800df64: 370c adds r7, #12 800df66: 46bd mov sp, r7 800df68: f85d 7b04 ldr.w r7, [sp], #4 800df6c: 4770 bx lr 0800df6e : * - 0x00: Power OFF * - 0x02: Power UP * - 0x03: Power ON */ uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) { 800df6e: b480 push {r7} 800df70: b083 sub sp, #12 800df72: af00 add r7, sp, #0 800df74: 6078 str r0, [r7, #4] return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); 800df76: 687b ldr r3, [r7, #4] 800df78: 681b ldr r3, [r3, #0] 800df7a: f003 0303 and.w r3, r3, #3 } 800df7e: 4618 mov r0, r3 800df80: 370c adds r7, #12 800df82: 46bd mov sp, r7 800df84: f85d 7b04 ldr.w r7, [sp], #4 800df88: 4770 bx lr ... 0800df8c : * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains * the configuration information for the SDMMC command * @retval HAL status */ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) { 800df8c: b480 push {r7} 800df8e: b085 sub sp, #20 800df90: af00 add r7, sp, #0 800df92: 6078 str r0, [r7, #4] 800df94: 6039 str r1, [r7, #0] uint32_t tmpreg = 0; 800df96: 2300 movs r3, #0 800df98: 60fb str r3, [r7, #12] assert_param(IS_SDMMC_RESPONSE(Command->Response)); assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt)); assert_param(IS_SDMMC_CPSM(Command->CPSM)); /* Set the SDMMC Argument value */ SDMMCx->ARG = Command->Argument; 800df9a: 683b ldr r3, [r7, #0] 800df9c: 681a ldr r2, [r3, #0] 800df9e: 687b ldr r3, [r7, #4] 800dfa0: 609a str r2, [r3, #8] /* Set SDMMC command parameters */ tmpreg |= (uint32_t)(Command->CmdIndex | \ 800dfa2: 683b ldr r3, [r7, #0] 800dfa4: 685a ldr r2, [r3, #4] Command->Response | \ 800dfa6: 683b ldr r3, [r7, #0] 800dfa8: 689b ldr r3, [r3, #8] tmpreg |= (uint32_t)(Command->CmdIndex | \ 800dfaa: 431a orrs r2, r3 Command->WaitForInterrupt | \ 800dfac: 683b ldr r3, [r7, #0] 800dfae: 68db ldr r3, [r3, #12] Command->Response | \ 800dfb0: 431a orrs r2, r3 Command->CPSM); 800dfb2: 683b ldr r3, [r7, #0] 800dfb4: 691b ldr r3, [r3, #16] Command->WaitForInterrupt | \ 800dfb6: 4313 orrs r3, r2 tmpreg |= (uint32_t)(Command->CmdIndex | \ 800dfb8: 68fa ldr r2, [r7, #12] 800dfba: 4313 orrs r3, r2 800dfbc: 60fb str r3, [r7, #12] /* Write to SDMMC CMD register */ MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); 800dfbe: 687b ldr r3, [r7, #4] 800dfc0: 68da ldr r2, [r3, #12] 800dfc2: 4b06 ldr r3, [pc, #24] ; (800dfdc ) 800dfc4: 4013 ands r3, r2 800dfc6: 68fa ldr r2, [r7, #12] 800dfc8: 431a orrs r2, r3 800dfca: 687b ldr r3, [r7, #4] 800dfcc: 60da str r2, [r3, #12] return HAL_OK; 800dfce: 2300 movs r3, #0 } 800dfd0: 4618 mov r0, r3 800dfd2: 3714 adds r7, #20 800dfd4: 46bd mov sp, r7 800dfd6: f85d 7b04 ldr.w r7, [sp], #4 800dfda: 4770 bx lr 800dfdc: fffee0c0 .word 0xfffee0c0 0800dfe0 : * @brief Return the command index of last command for which response received * @param SDMMCx: Pointer to SDMMC register base * @retval Command index of the last command response received */ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) { 800dfe0: b480 push {r7} 800dfe2: b083 sub sp, #12 800dfe4: af00 add r7, sp, #0 800dfe6: 6078 str r0, [r7, #4] return (uint8_t)(SDMMCx->RESPCMD); 800dfe8: 687b ldr r3, [r7, #4] 800dfea: 691b ldr r3, [r3, #16] 800dfec: b2db uxtb r3, r3 } 800dfee: 4618 mov r0, r3 800dff0: 370c adds r7, #12 800dff2: 46bd mov sp, r7 800dff4: f85d 7b04 ldr.w r7, [sp], #4 800dff8: 4770 bx lr 0800dffa : * @arg SDMMC_RESP3: Response Register 3 * @arg SDMMC_RESP4: Response Register 4 * @retval The Corresponding response register value */ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) { 800dffa: b480 push {r7} 800dffc: b085 sub sp, #20 800dffe: af00 add r7, sp, #0 800e000: 6078 str r0, [r7, #4] 800e002: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_SDMMC_RESP(Response)); /* Get the response */ tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response; 800e004: 687b ldr r3, [r7, #4] 800e006: 3314 adds r3, #20 800e008: 461a mov r2, r3 800e00a: 683b ldr r3, [r7, #0] 800e00c: 4413 add r3, r2 800e00e: 60fb str r3, [r7, #12] return (*(__IO uint32_t *) tmp); 800e010: 68fb ldr r3, [r7, #12] 800e012: 681b ldr r3, [r3, #0] } 800e014: 4618 mov r0, r3 800e016: 3714 adds r7, #20 800e018: 46bd mov sp, r7 800e01a: f85d 7b04 ldr.w r7, [sp], #4 800e01e: 4770 bx lr 0800e020 : * @param Data : pointer to a SDMMC_DataInitTypeDef structure * that contains the configuration information for the SDMMC data. * @retval HAL status */ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) { 800e020: b480 push {r7} 800e022: b085 sub sp, #20 800e024: af00 add r7, sp, #0 800e026: 6078 str r0, [r7, #4] 800e028: 6039 str r1, [r7, #0] uint32_t tmpreg = 0; 800e02a: 2300 movs r3, #0 800e02c: 60fb str r3, [r7, #12] assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir)); assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode)); assert_param(IS_SDMMC_DPSM(Data->DPSM)); /* Set the SDMMC Data TimeOut value */ SDMMCx->DTIMER = Data->DataTimeOut; 800e02e: 683b ldr r3, [r7, #0] 800e030: 681a ldr r2, [r3, #0] 800e032: 687b ldr r3, [r7, #4] 800e034: 625a str r2, [r3, #36] ; 0x24 /* Set the SDMMC DataLength value */ SDMMCx->DLEN = Data->DataLength; 800e036: 683b ldr r3, [r7, #0] 800e038: 685a ldr r2, [r3, #4] 800e03a: 687b ldr r3, [r7, #4] 800e03c: 629a str r2, [r3, #40] ; 0x28 /* Set the SDMMC data configuration parameters */ tmpreg |= (uint32_t)(Data->DataBlockSize | \ 800e03e: 683b ldr r3, [r7, #0] 800e040: 689a ldr r2, [r3, #8] Data->TransferDir | \ 800e042: 683b ldr r3, [r7, #0] 800e044: 68db ldr r3, [r3, #12] tmpreg |= (uint32_t)(Data->DataBlockSize | \ 800e046: 431a orrs r2, r3 Data->TransferMode | \ 800e048: 683b ldr r3, [r7, #0] 800e04a: 691b ldr r3, [r3, #16] Data->TransferDir | \ 800e04c: 431a orrs r2, r3 Data->DPSM); 800e04e: 683b ldr r3, [r7, #0] 800e050: 695b ldr r3, [r3, #20] Data->TransferMode | \ 800e052: 4313 orrs r3, r2 tmpreg |= (uint32_t)(Data->DataBlockSize | \ 800e054: 68fa ldr r2, [r7, #12] 800e056: 4313 orrs r3, r2 800e058: 60fb str r3, [r7, #12] /* Write to SDMMC DCTRL */ MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); 800e05a: 687b ldr r3, [r7, #4] 800e05c: 6adb ldr r3, [r3, #44] ; 0x2c 800e05e: f023 02ff bic.w r2, r3, #255 ; 0xff 800e062: 68fb ldr r3, [r7, #12] 800e064: 431a orrs r2, r3 800e066: 687b ldr r3, [r7, #4] 800e068: 62da str r2, [r3, #44] ; 0x2c return HAL_OK; 800e06a: 2300 movs r3, #0 } 800e06c: 4618 mov r0, r3 800e06e: 3714 adds r7, #20 800e070: 46bd mov sp, r7 800e072: f85d 7b04 ldr.w r7, [sp], #4 800e076: 4770 bx lr 0800e078 : * @brief Send the Data Block Length command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) { 800e078: b580 push {r7, lr} 800e07a: b088 sub sp, #32 800e07c: af00 add r7, sp, #0 800e07e: 6078 str r0, [r7, #4] 800e080: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)BlockSize; 800e082: 683b ldr r3, [r7, #0] 800e084: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; 800e086: 2310 movs r3, #16 800e088: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e08a: f44f 7380 mov.w r3, #256 ; 0x100 800e08e: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e090: 2300 movs r3, #0 800e092: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e094: f44f 5380 mov.w r3, #4096 ; 0x1000 800e098: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e09a: f107 0308 add.w r3, r7, #8 800e09e: 4619 mov r1, r3 800e0a0: 6878 ldr r0, [r7, #4] 800e0a2: f7ff ff73 bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT); 800e0a6: f241 3288 movw r2, #5000 ; 0x1388 800e0aa: 2110 movs r1, #16 800e0ac: 6878 ldr r0, [r7, #4] 800e0ae: f000 fa5f bl 800e570 800e0b2: 61f8 str r0, [r7, #28] return errorstate; 800e0b4: 69fb ldr r3, [r7, #28] } 800e0b6: 4618 mov r0, r3 800e0b8: 3720 adds r7, #32 800e0ba: 46bd mov sp, r7 800e0bc: bd80 pop {r7, pc} 0800e0be : * @brief Send the Read Single Block command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) { 800e0be: b580 push {r7, lr} 800e0c0: b088 sub sp, #32 800e0c2: af00 add r7, sp, #0 800e0c4: 6078 str r0, [r7, #4] 800e0c6: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; 800e0c8: 683b ldr r3, [r7, #0] 800e0ca: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; 800e0cc: 2311 movs r3, #17 800e0ce: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e0d0: f44f 7380 mov.w r3, #256 ; 0x100 800e0d4: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e0d6: 2300 movs r3, #0 800e0d8: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e0da: f44f 5380 mov.w r3, #4096 ; 0x1000 800e0de: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e0e0: f107 0308 add.w r3, r7, #8 800e0e4: 4619 mov r1, r3 800e0e6: 6878 ldr r0, [r7, #4] 800e0e8: f7ff ff50 bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); 800e0ec: f241 3288 movw r2, #5000 ; 0x1388 800e0f0: 2111 movs r1, #17 800e0f2: 6878 ldr r0, [r7, #4] 800e0f4: f000 fa3c bl 800e570 800e0f8: 61f8 str r0, [r7, #28] return errorstate; 800e0fa: 69fb ldr r3, [r7, #28] } 800e0fc: 4618 mov r0, r3 800e0fe: 3720 adds r7, #32 800e100: 46bd mov sp, r7 800e102: bd80 pop {r7, pc} 0800e104 : * @brief Send the Read Multi Block command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) { 800e104: b580 push {r7, lr} 800e106: b088 sub sp, #32 800e108: af00 add r7, sp, #0 800e10a: 6078 str r0, [r7, #4] 800e10c: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; 800e10e: 683b ldr r3, [r7, #0] 800e110: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; 800e112: 2312 movs r3, #18 800e114: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e116: f44f 7380 mov.w r3, #256 ; 0x100 800e11a: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e11c: 2300 movs r3, #0 800e11e: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e120: f44f 5380 mov.w r3, #4096 ; 0x1000 800e124: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e126: f107 0308 add.w r3, r7, #8 800e12a: 4619 mov r1, r3 800e12c: 6878 ldr r0, [r7, #4] 800e12e: f7ff ff2d bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT); 800e132: f241 3288 movw r2, #5000 ; 0x1388 800e136: 2112 movs r1, #18 800e138: 6878 ldr r0, [r7, #4] 800e13a: f000 fa19 bl 800e570 800e13e: 61f8 str r0, [r7, #28] return errorstate; 800e140: 69fb ldr r3, [r7, #28] } 800e142: 4618 mov r0, r3 800e144: 3720 adds r7, #32 800e146: 46bd mov sp, r7 800e148: bd80 pop {r7, pc} 0800e14a : * @brief Send the Write Single Block command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) { 800e14a: b580 push {r7, lr} 800e14c: b088 sub sp, #32 800e14e: af00 add r7, sp, #0 800e150: 6078 str r0, [r7, #4] 800e152: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; 800e154: 683b ldr r3, [r7, #0] 800e156: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; 800e158: 2318 movs r3, #24 800e15a: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e15c: f44f 7380 mov.w r3, #256 ; 0x100 800e160: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e162: 2300 movs r3, #0 800e164: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e166: f44f 5380 mov.w r3, #4096 ; 0x1000 800e16a: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e16c: f107 0308 add.w r3, r7, #8 800e170: 4619 mov r1, r3 800e172: 6878 ldr r0, [r7, #4] 800e174: f7ff ff0a bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); 800e178: f241 3288 movw r2, #5000 ; 0x1388 800e17c: 2118 movs r1, #24 800e17e: 6878 ldr r0, [r7, #4] 800e180: f000 f9f6 bl 800e570 800e184: 61f8 str r0, [r7, #28] return errorstate; 800e186: 69fb ldr r3, [r7, #28] } 800e188: 4618 mov r0, r3 800e18a: 3720 adds r7, #32 800e18c: 46bd mov sp, r7 800e18e: bd80 pop {r7, pc} 0800e190 : * @brief Send the Write Multi Block command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) { 800e190: b580 push {r7, lr} 800e192: b088 sub sp, #32 800e194: af00 add r7, sp, #0 800e196: 6078 str r0, [r7, #4] 800e198: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; 800e19a: 683b ldr r3, [r7, #0] 800e19c: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; 800e19e: 2319 movs r3, #25 800e1a0: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e1a2: f44f 7380 mov.w r3, #256 ; 0x100 800e1a6: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e1a8: 2300 movs r3, #0 800e1aa: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e1ac: f44f 5380 mov.w r3, #4096 ; 0x1000 800e1b0: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e1b2: f107 0308 add.w r3, r7, #8 800e1b6: 4619 mov r1, r3 800e1b8: 6878 ldr r0, [r7, #4] 800e1ba: f7ff fee7 bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT); 800e1be: f241 3288 movw r2, #5000 ; 0x1388 800e1c2: 2119 movs r1, #25 800e1c4: 6878 ldr r0, [r7, #4] 800e1c6: f000 f9d3 bl 800e570 800e1ca: 61f8 str r0, [r7, #28] return errorstate; 800e1cc: 69fb ldr r3, [r7, #28] } 800e1ce: 4618 mov r0, r3 800e1d0: 3720 adds r7, #32 800e1d2: 46bd mov sp, r7 800e1d4: bd80 pop {r7, pc} ... 0800e1d8 : * @brief Send the Stop Transfer command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) { 800e1d8: b580 push {r7, lr} 800e1da: b088 sub sp, #32 800e1dc: af00 add r7, sp, #0 800e1de: 6078 str r0, [r7, #4] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD12 STOP_TRANSMISSION */ sdmmc_cmdinit.Argument = 0U; 800e1e0: 2300 movs r3, #0 800e1e2: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; 800e1e4: 230c movs r3, #12 800e1e6: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e1e8: f44f 7380 mov.w r3, #256 ; 0x100 800e1ec: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e1ee: 2300 movs r3, #0 800e1f0: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e1f2: f44f 5380 mov.w r3, #4096 ; 0x1000 800e1f6: 61bb str r3, [r7, #24] __SDMMC_CMDSTOP_ENABLE(SDMMCx); 800e1f8: 687b ldr r3, [r7, #4] 800e1fa: 68db ldr r3, [r3, #12] 800e1fc: f043 0280 orr.w r2, r3, #128 ; 0x80 800e200: 687b ldr r3, [r7, #4] 800e202: 60da str r2, [r3, #12] __SDMMC_CMDTRANS_DISABLE(SDMMCx); 800e204: 687b ldr r3, [r7, #4] 800e206: 68db ldr r3, [r3, #12] 800e208: f023 0240 bic.w r2, r3, #64 ; 0x40 800e20c: 687b ldr r3, [r7, #4] 800e20e: 60da str r2, [r3, #12] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e210: f107 0308 add.w r3, r7, #8 800e214: 4619 mov r1, r3 800e216: 6878 ldr r0, [r7, #4] 800e218: f7ff feb8 bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT); 800e21c: 4a0b ldr r2, [pc, #44] ; (800e24c ) 800e21e: 210c movs r1, #12 800e220: 6878 ldr r0, [r7, #4] 800e222: f000 f9a5 bl 800e570 800e226: 61f8 str r0, [r7, #28] __SDMMC_CMDSTOP_DISABLE(SDMMCx); 800e228: 687b ldr r3, [r7, #4] 800e22a: 68db ldr r3, [r3, #12] 800e22c: f023 0280 bic.w r2, r3, #128 ; 0x80 800e230: 687b ldr r3, [r7, #4] 800e232: 60da str r2, [r3, #12] /* Ignore Address Out Of Range Error, Not relevant at end of memory */ if (errorstate == SDMMC_ERROR_ADDR_OUT_OF_RANGE) 800e234: 69fb ldr r3, [r7, #28] 800e236: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800e23a: d101 bne.n 800e240 { errorstate = SDMMC_ERROR_NONE; 800e23c: 2300 movs r3, #0 800e23e: 61fb str r3, [r7, #28] } return errorstate; 800e240: 69fb ldr r3, [r7, #28] } 800e242: 4618 mov r0, r3 800e244: 3720 adds r7, #32 800e246: 46bd mov sp, r7 800e248: bd80 pop {r7, pc} 800e24a: bf00 nop 800e24c: 05f5e100 .word 0x05f5e100 0800e250 : * @param SDMMCx: Pointer to SDMMC register base * @param addr: Address of the card to be selected * @retval HAL status */ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr) { 800e250: b580 push {r7, lr} 800e252: b088 sub sp, #32 800e254: af00 add r7, sp, #0 800e256: 6078 str r0, [r7, #4] 800e258: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD7 SDMMC_SEL_DESEL_CARD */ sdmmc_cmdinit.Argument = (uint32_t)Addr; 800e25a: 683b ldr r3, [r7, #0] 800e25c: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; 800e25e: 2307 movs r3, #7 800e260: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e262: f44f 7380 mov.w r3, #256 ; 0x100 800e266: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e268: 2300 movs r3, #0 800e26a: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e26c: f44f 5380 mov.w r3, #4096 ; 0x1000 800e270: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e272: f107 0308 add.w r3, r7, #8 800e276: 4619 mov r1, r3 800e278: 6878 ldr r0, [r7, #4] 800e27a: f7ff fe87 bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT); 800e27e: f241 3288 movw r2, #5000 ; 0x1388 800e282: 2107 movs r1, #7 800e284: 6878 ldr r0, [r7, #4] 800e286: f000 f973 bl 800e570 800e28a: 61f8 str r0, [r7, #28] return errorstate; 800e28c: 69fb ldr r3, [r7, #28] } 800e28e: 4618 mov r0, r3 800e290: 3720 adds r7, #32 800e292: 46bd mov sp, r7 800e294: bd80 pop {r7, pc} 0800e296 : * @brief Send the Go Idle State command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) { 800e296: b580 push {r7, lr} 800e298: b088 sub sp, #32 800e29a: af00 add r7, sp, #0 800e29c: 6078 str r0, [r7, #4] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = 0U; 800e29e: 2300 movs r3, #0 800e2a0: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; 800e2a2: 2300 movs r3, #0 800e2a4: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; 800e2a6: 2300 movs r3, #0 800e2a8: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e2aa: 2300 movs r3, #0 800e2ac: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e2ae: f44f 5380 mov.w r3, #4096 ; 0x1000 800e2b2: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e2b4: f107 0308 add.w r3, r7, #8 800e2b8: 4619 mov r1, r3 800e2ba: 6878 ldr r0, [r7, #4] 800e2bc: f7ff fe66 bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdError(SDMMCx); 800e2c0: 6878 ldr r0, [r7, #4] 800e2c2: f000 fb97 bl 800e9f4 800e2c6: 61f8 str r0, [r7, #28] return errorstate; 800e2c8: 69fb ldr r3, [r7, #28] } 800e2ca: 4618 mov r0, r3 800e2cc: 3720 adds r7, #32 800e2ce: 46bd mov sp, r7 800e2d0: bd80 pop {r7, pc} 0800e2d2 : * @brief Send the Operating Condition command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) { 800e2d2: b580 push {r7, lr} 800e2d4: b088 sub sp, #32 800e2d6: af00 add r7, sp, #0 800e2d8: 6078 str r0, [r7, #4] /* Send CMD8 to verify SD card interface operating condition */ /* Argument: - [31:12]: Reserved (shall be set to '0') - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - [7:0]: Check Pattern (recommended 0xAA) */ /* CMD Response: R7 */ sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; 800e2da: f44f 73d5 mov.w r3, #426 ; 0x1aa 800e2de: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; 800e2e0: 2308 movs r3, #8 800e2e2: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e2e4: f44f 7380 mov.w r3, #256 ; 0x100 800e2e8: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e2ea: 2300 movs r3, #0 800e2ec: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e2ee: f44f 5380 mov.w r3, #4096 ; 0x1000 800e2f2: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e2f4: f107 0308 add.w r3, r7, #8 800e2f8: 4619 mov r1, r3 800e2fa: 6878 ldr r0, [r7, #4] 800e2fc: f7ff fe46 bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp7(SDMMCx); 800e300: 6878 ldr r0, [r7, #4] 800e302: f000 fb29 bl 800e958 800e306: 61f8 str r0, [r7, #28] return errorstate; 800e308: 69fb ldr r3, [r7, #28] } 800e30a: 4618 mov r0, r3 800e30c: 3720 adds r7, #32 800e30e: 46bd mov sp, r7 800e310: bd80 pop {r7, pc} 0800e312 : * @param SDMMCx: Pointer to SDMMC register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { 800e312: b580 push {r7, lr} 800e314: b088 sub sp, #32 800e316: af00 add r7, sp, #0 800e318: 6078 str r0, [r7, #4] 800e31a: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = (uint32_t)Argument; 800e31c: 683b ldr r3, [r7, #0] 800e31e: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; 800e320: 2337 movs r3, #55 ; 0x37 800e322: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e324: f44f 7380 mov.w r3, #256 ; 0x100 800e328: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e32a: 2300 movs r3, #0 800e32c: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e32e: f44f 5380 mov.w r3, #4096 ; 0x1000 800e332: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e334: f107 0308 add.w r3, r7, #8 800e338: 4619 mov r1, r3 800e33a: 6878 ldr r0, [r7, #4] 800e33c: f7ff fe26 bl 800df8c /* Check for error conditions */ /* If there is a HAL_ERROR, it is a MMC card, else it is a SD card: SD card 2.0 (voltage range mismatch) or SD card 1.x */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT); 800e340: f241 3288 movw r2, #5000 ; 0x1388 800e344: 2137 movs r1, #55 ; 0x37 800e346: 6878 ldr r0, [r7, #4] 800e348: f000 f912 bl 800e570 800e34c: 61f8 str r0, [r7, #28] return errorstate; 800e34e: 69fb ldr r3, [r7, #28] } 800e350: 4618 mov r0, r3 800e352: 3720 adds r7, #32 800e354: 46bd mov sp, r7 800e356: bd80 pop {r7, pc} 0800e358 : * @param SDMMCx: Pointer to SDMMC register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { 800e358: b580 push {r7, lr} 800e35a: b088 sub sp, #32 800e35c: af00 add r7, sp, #0 800e35e: 6078 str r0, [r7, #4] 800e360: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = Argument; 800e362: 683b ldr r3, [r7, #0] 800e364: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; 800e366: 2329 movs r3, #41 ; 0x29 800e368: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e36a: f44f 7380 mov.w r3, #256 ; 0x100 800e36e: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e370: 2300 movs r3, #0 800e372: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e374: f44f 5380 mov.w r3, #4096 ; 0x1000 800e378: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e37a: f107 0308 add.w r3, r7, #8 800e37e: 4619 mov r1, r3 800e380: 6878 ldr r0, [r7, #4] 800e382: f7ff fe03 bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp3(SDMMCx); 800e386: 6878 ldr r0, [r7, #4] 800e388: f000 fa2e bl 800e7e8 800e38c: 61f8 str r0, [r7, #28] return errorstate; 800e38e: 69fb ldr r3, [r7, #28] } 800e390: 4618 mov r0, r3 800e392: 3720 adds r7, #32 800e394: 46bd mov sp, r7 800e396: bd80 pop {r7, pc} 0800e398 : * @param SDMMCx: Pointer to SDMMC register base * @param BusWidth: BusWidth * @retval HAL status */ uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) { 800e398: b580 push {r7, lr} 800e39a: b088 sub sp, #32 800e39c: af00 add r7, sp, #0 800e39e: 6078 str r0, [r7, #4] 800e3a0: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = (uint32_t)BusWidth; 800e3a2: 683b ldr r3, [r7, #0] 800e3a4: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; 800e3a6: 2306 movs r3, #6 800e3a8: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e3aa: f44f 7380 mov.w r3, #256 ; 0x100 800e3ae: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e3b0: 2300 movs r3, #0 800e3b2: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e3b4: f44f 5380 mov.w r3, #4096 ; 0x1000 800e3b8: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e3ba: f107 0308 add.w r3, r7, #8 800e3be: 4619 mov r1, r3 800e3c0: 6878 ldr r0, [r7, #4] 800e3c2: f7ff fde3 bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT); 800e3c6: f241 3288 movw r2, #5000 ; 0x1388 800e3ca: 2106 movs r1, #6 800e3cc: 6878 ldr r0, [r7, #4] 800e3ce: f000 f8cf bl 800e570 800e3d2: 61f8 str r0, [r7, #28] return errorstate; 800e3d4: 69fb ldr r3, [r7, #28] } 800e3d6: 4618 mov r0, r3 800e3d8: 3720 adds r7, #32 800e3da: 46bd mov sp, r7 800e3dc: bd80 pop {r7, pc} 0800e3de : * @brief Send the Send SCR command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) { 800e3de: b580 push {r7, lr} 800e3e0: b088 sub sp, #32 800e3e2: af00 add r7, sp, #0 800e3e4: 6078 str r0, [r7, #4] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD51 SD_APP_SEND_SCR */ sdmmc_cmdinit.Argument = 0U; 800e3e6: 2300 movs r3, #0 800e3e8: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; 800e3ea: 2333 movs r3, #51 ; 0x33 800e3ec: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e3ee: f44f 7380 mov.w r3, #256 ; 0x100 800e3f2: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e3f4: 2300 movs r3, #0 800e3f6: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e3f8: f44f 5380 mov.w r3, #4096 ; 0x1000 800e3fc: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e3fe: f107 0308 add.w r3, r7, #8 800e402: 4619 mov r1, r3 800e404: 6878 ldr r0, [r7, #4] 800e406: f7ff fdc1 bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT); 800e40a: f241 3288 movw r2, #5000 ; 0x1388 800e40e: 2133 movs r1, #51 ; 0x33 800e410: 6878 ldr r0, [r7, #4] 800e412: f000 f8ad bl 800e570 800e416: 61f8 str r0, [r7, #28] return errorstate; 800e418: 69fb ldr r3, [r7, #28] } 800e41a: 4618 mov r0, r3 800e41c: 3720 adds r7, #32 800e41e: 46bd mov sp, r7 800e420: bd80 pop {r7, pc} 0800e422 : * @brief Send the Send CID command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) { 800e422: b580 push {r7, lr} 800e424: b088 sub sp, #32 800e426: af00 add r7, sp, #0 800e428: 6078 str r0, [r7, #4] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD2 ALL_SEND_CID */ sdmmc_cmdinit.Argument = 0U; 800e42a: 2300 movs r3, #0 800e42c: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; 800e42e: 2302 movs r3, #2 800e430: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; 800e432: f44f 7340 mov.w r3, #768 ; 0x300 800e436: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e438: 2300 movs r3, #0 800e43a: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e43c: f44f 5380 mov.w r3, #4096 ; 0x1000 800e440: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e442: f107 0308 add.w r3, r7, #8 800e446: 4619 mov r1, r3 800e448: 6878 ldr r0, [r7, #4] 800e44a: f7ff fd9f bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDMMCx); 800e44e: 6878 ldr r0, [r7, #4] 800e450: f000 f980 bl 800e754 800e454: 61f8 str r0, [r7, #28] return errorstate; 800e456: 69fb ldr r3, [r7, #28] } 800e458: 4618 mov r0, r3 800e45a: 3720 adds r7, #32 800e45c: 46bd mov sp, r7 800e45e: bd80 pop {r7, pc} 0800e460 : * @param SDMMCx: Pointer to SDMMC register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { 800e460: b580 push {r7, lr} 800e462: b088 sub sp, #32 800e464: af00 add r7, sp, #0 800e466: 6078 str r0, [r7, #4] 800e468: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD9 SEND_CSD */ sdmmc_cmdinit.Argument = Argument; 800e46a: 683b ldr r3, [r7, #0] 800e46c: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; 800e46e: 2309 movs r3, #9 800e470: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; 800e472: f44f 7340 mov.w r3, #768 ; 0x300 800e476: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e478: 2300 movs r3, #0 800e47a: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e47c: f44f 5380 mov.w r3, #4096 ; 0x1000 800e480: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e482: f107 0308 add.w r3, r7, #8 800e486: 4619 mov r1, r3 800e488: 6878 ldr r0, [r7, #4] 800e48a: f7ff fd7f bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDMMCx); 800e48e: 6878 ldr r0, [r7, #4] 800e490: f000 f960 bl 800e754 800e494: 61f8 str r0, [r7, #28] return errorstate; 800e496: 69fb ldr r3, [r7, #28] } 800e498: 4618 mov r0, r3 800e49a: 3720 adds r7, #32 800e49c: 46bd mov sp, r7 800e49e: bd80 pop {r7, pc} 0800e4a0 : * @param SDMMCx: Pointer to SDMMC register base * @param pRCA: Card RCA * @retval HAL status */ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) { 800e4a0: b580 push {r7, lr} 800e4a2: b088 sub sp, #32 800e4a4: af00 add r7, sp, #0 800e4a6: 6078 str r0, [r7, #4] 800e4a8: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD3 SD_CMD_SET_REL_ADDR */ sdmmc_cmdinit.Argument = 0U; 800e4aa: 2300 movs r3, #0 800e4ac: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; 800e4ae: 2303 movs r3, #3 800e4b0: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e4b2: f44f 7380 mov.w r3, #256 ; 0x100 800e4b6: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e4b8: 2300 movs r3, #0 800e4ba: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e4bc: f44f 5380 mov.w r3, #4096 ; 0x1000 800e4c0: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e4c2: f107 0308 add.w r3, r7, #8 800e4c6: 4619 mov r1, r3 800e4c8: 6878 ldr r0, [r7, #4] 800e4ca: f7ff fd5f bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA); 800e4ce: 683a ldr r2, [r7, #0] 800e4d0: 2103 movs r1, #3 800e4d2: 6878 ldr r0, [r7, #4] 800e4d4: f000 f9c8 bl 800e868 800e4d8: 61f8 str r0, [r7, #28] return errorstate; 800e4da: 69fb ldr r3, [r7, #28] } 800e4dc: 4618 mov r0, r3 800e4de: 3720 adds r7, #32 800e4e0: 46bd mov sp, r7 800e4e2: bd80 pop {r7, pc} 0800e4e4 : * @param SDMMCx: Pointer to SDMMC register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { 800e4e4: b580 push {r7, lr} 800e4e6: b088 sub sp, #32 800e4e8: af00 add r7, sp, #0 800e4ea: 6078 str r0, [r7, #4] 800e4ec: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = Argument; 800e4ee: 683b ldr r3, [r7, #0] 800e4f0: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; 800e4f2: 230d movs r3, #13 800e4f4: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e4f6: f44f 7380 mov.w r3, #256 ; 0x100 800e4fa: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e4fc: 2300 movs r3, #0 800e4fe: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e500: f44f 5380 mov.w r3, #4096 ; 0x1000 800e504: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e506: f107 0308 add.w r3, r7, #8 800e50a: 4619 mov r1, r3 800e50c: 6878 ldr r0, [r7, #4] 800e50e: f7ff fd3d bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT); 800e512: f241 3288 movw r2, #5000 ; 0x1388 800e516: 210d movs r1, #13 800e518: 6878 ldr r0, [r7, #4] 800e51a: f000 f829 bl 800e570 800e51e: 61f8 str r0, [r7, #28] return errorstate; 800e520: 69fb ldr r3, [r7, #28] } 800e522: 4618 mov r0, r3 800e524: 3720 adds r7, #32 800e526: 46bd mov sp, r7 800e528: bd80 pop {r7, pc} 0800e52a : * @brief Send the Status register command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) { 800e52a: b580 push {r7, lr} 800e52c: b088 sub sp, #32 800e52e: af00 add r7, sp, #0 800e530: 6078 str r0, [r7, #4] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = 0U; 800e532: 2300 movs r3, #0 800e534: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; 800e536: 230d movs r3, #13 800e538: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800e53a: f44f 7380 mov.w r3, #256 ; 0x100 800e53e: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800e540: 2300 movs r3, #0 800e542: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800e544: f44f 5380 mov.w r3, #4096 ; 0x1000 800e548: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800e54a: f107 0308 add.w r3, r7, #8 800e54e: 4619 mov r1, r3 800e550: 6878 ldr r0, [r7, #4] 800e552: f7ff fd1b bl 800df8c /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT); 800e556: f241 3288 movw r2, #5000 ; 0x1388 800e55a: 210d movs r1, #13 800e55c: 6878 ldr r0, [r7, #4] 800e55e: f000 f807 bl 800e570 800e562: 61f8 str r0, [r7, #28] return errorstate; 800e564: 69fb ldr r3, [r7, #28] } 800e566: 4618 mov r0, r3 800e568: 3720 adds r7, #32 800e56a: 46bd mov sp, r7 800e56c: bd80 pop {r7, pc} ... 0800e570 : * @param hsd: SD handle * @param SD_CMD: The sent command index * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) { 800e570: b580 push {r7, lr} 800e572: b088 sub sp, #32 800e574: af00 add r7, sp, #0 800e576: 60f8 str r0, [r7, #12] 800e578: 460b mov r3, r1 800e57a: 607a str r2, [r7, #4] 800e57c: 72fb strb r3, [r7, #11] uint32_t response_r1; uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The Timeout is expressed in ms */ uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U); 800e57e: 4b70 ldr r3, [pc, #448] ; (800e740 ) 800e580: 681b ldr r3, [r3, #0] 800e582: 4a70 ldr r2, [pc, #448] ; (800e744 ) 800e584: fba2 2303 umull r2, r3, r2, r3 800e588: 0a5a lsrs r2, r3, #9 800e58a: 687b ldr r3, [r7, #4] 800e58c: fb02 f303 mul.w r3, r2, r3 800e590: 61fb str r3, [r7, #28] do { if (count-- == 0U) 800e592: 69fb ldr r3, [r7, #28] 800e594: 1e5a subs r2, r3, #1 800e596: 61fa str r2, [r7, #28] 800e598: 2b00 cmp r3, #0 800e59a: d102 bne.n 800e5a2 { return SDMMC_ERROR_TIMEOUT; 800e59c: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800e5a0: e0c9 b.n 800e736 } sta_reg = SDMMCx->STA; 800e5a2: 68fb ldr r3, [r7, #12] 800e5a4: 6b5b ldr r3, [r3, #52] ; 0x34 800e5a6: 61bb str r3, [r7, #24] } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | 800e5a8: 69ba ldr r2, [r7, #24] 800e5aa: 4b67 ldr r3, [pc, #412] ; (800e748 ) 800e5ac: 4013 ands r3, r2 SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); 800e5ae: 2b00 cmp r3, #0 800e5b0: d0ef beq.n 800e592 800e5b2: 69bb ldr r3, [r7, #24] 800e5b4: f403 5300 and.w r3, r3, #8192 ; 0x2000 800e5b8: 2b00 cmp r3, #0 800e5ba: d1ea bne.n 800e592 if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) 800e5bc: 68fb ldr r3, [r7, #12] 800e5be: 6b5b ldr r3, [r3, #52] ; 0x34 800e5c0: f003 0304 and.w r3, r3, #4 800e5c4: 2b00 cmp r3, #0 800e5c6: d004 beq.n 800e5d2 { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); 800e5c8: 68fb ldr r3, [r7, #12] 800e5ca: 2204 movs r2, #4 800e5cc: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 800e5ce: 2304 movs r3, #4 800e5d0: e0b1 b.n 800e736 } else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) 800e5d2: 68fb ldr r3, [r7, #12] 800e5d4: 6b5b ldr r3, [r3, #52] ; 0x34 800e5d6: f003 0301 and.w r3, r3, #1 800e5da: 2b00 cmp r3, #0 800e5dc: d004 beq.n 800e5e8 { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); 800e5de: 68fb ldr r3, [r7, #12] 800e5e0: 2201 movs r2, #1 800e5e2: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 800e5e4: 2301 movs r3, #1 800e5e6: e0a6 b.n 800e736 { /* Nothing to do */ } /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); 800e5e8: 68fb ldr r3, [r7, #12] 800e5ea: 4a58 ldr r2, [pc, #352] ; (800e74c ) 800e5ec: 639a str r2, [r3, #56] ; 0x38 /* Check response received is of desired command */ if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) 800e5ee: 68f8 ldr r0, [r7, #12] 800e5f0: f7ff fcf6 bl 800dfe0 800e5f4: 4603 mov r3, r0 800e5f6: 461a mov r2, r3 800e5f8: 7afb ldrb r3, [r7, #11] 800e5fa: 4293 cmp r3, r2 800e5fc: d001 beq.n 800e602 { return SDMMC_ERROR_CMD_CRC_FAIL; 800e5fe: 2301 movs r3, #1 800e600: e099 b.n 800e736 } /* We have received response, retrieve it for analysis */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); 800e602: 2100 movs r1, #0 800e604: 68f8 ldr r0, [r7, #12] 800e606: f7ff fcf8 bl 800dffa 800e60a: 6178 str r0, [r7, #20] if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) 800e60c: 697a ldr r2, [r7, #20] 800e60e: 4b50 ldr r3, [pc, #320] ; (800e750 ) 800e610: 4013 ands r3, r2 800e612: 2b00 cmp r3, #0 800e614: d101 bne.n 800e61a { return SDMMC_ERROR_NONE; 800e616: 2300 movs r3, #0 800e618: e08d b.n 800e736 } else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) 800e61a: 697b ldr r3, [r7, #20] 800e61c: 2b00 cmp r3, #0 800e61e: da02 bge.n 800e626 { return SDMMC_ERROR_ADDR_OUT_OF_RANGE; 800e620: f04f 7300 mov.w r3, #33554432 ; 0x2000000 800e624: e087 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) 800e626: 697b ldr r3, [r7, #20] 800e628: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 800e62c: 2b00 cmp r3, #0 800e62e: d001 beq.n 800e634 { return SDMMC_ERROR_ADDR_MISALIGNED; 800e630: 2340 movs r3, #64 ; 0x40 800e632: e080 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) 800e634: 697b ldr r3, [r7, #20] 800e636: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800e63a: 2b00 cmp r3, #0 800e63c: d001 beq.n 800e642 { return SDMMC_ERROR_BLOCK_LEN_ERR; 800e63e: 2380 movs r3, #128 ; 0x80 800e640: e079 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) 800e642: 697b ldr r3, [r7, #20] 800e644: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800e648: 2b00 cmp r3, #0 800e64a: d002 beq.n 800e652 { return SDMMC_ERROR_ERASE_SEQ_ERR; 800e64c: f44f 7380 mov.w r3, #256 ; 0x100 800e650: e071 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) 800e652: 697b ldr r3, [r7, #20] 800e654: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 800e658: 2b00 cmp r3, #0 800e65a: d002 beq.n 800e662 { return SDMMC_ERROR_BAD_ERASE_PARAM; 800e65c: f44f 7300 mov.w r3, #512 ; 0x200 800e660: e069 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) 800e662: 697b ldr r3, [r7, #20] 800e664: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 800e668: 2b00 cmp r3, #0 800e66a: d002 beq.n 800e672 { return SDMMC_ERROR_WRITE_PROT_VIOLATION; 800e66c: f44f 6380 mov.w r3, #1024 ; 0x400 800e670: e061 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) 800e672: 697b ldr r3, [r7, #20] 800e674: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 800e678: 2b00 cmp r3, #0 800e67a: d002 beq.n 800e682 { return SDMMC_ERROR_LOCK_UNLOCK_FAILED; 800e67c: f44f 6300 mov.w r3, #2048 ; 0x800 800e680: e059 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) 800e682: 697b ldr r3, [r7, #20] 800e684: f403 0300 and.w r3, r3, #8388608 ; 0x800000 800e688: 2b00 cmp r3, #0 800e68a: d002 beq.n 800e692 { return SDMMC_ERROR_COM_CRC_FAILED; 800e68c: f44f 5380 mov.w r3, #4096 ; 0x1000 800e690: e051 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) 800e692: 697b ldr r3, [r7, #20] 800e694: f403 0380 and.w r3, r3, #4194304 ; 0x400000 800e698: 2b00 cmp r3, #0 800e69a: d002 beq.n 800e6a2 { return SDMMC_ERROR_ILLEGAL_CMD; 800e69c: f44f 5300 mov.w r3, #8192 ; 0x2000 800e6a0: e049 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) 800e6a2: 697b ldr r3, [r7, #20] 800e6a4: f403 1300 and.w r3, r3, #2097152 ; 0x200000 800e6a8: 2b00 cmp r3, #0 800e6aa: d002 beq.n 800e6b2 { return SDMMC_ERROR_CARD_ECC_FAILED; 800e6ac: f44f 4380 mov.w r3, #16384 ; 0x4000 800e6b0: e041 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) 800e6b2: 697b ldr r3, [r7, #20] 800e6b4: f403 1380 and.w r3, r3, #1048576 ; 0x100000 800e6b8: 2b00 cmp r3, #0 800e6ba: d002 beq.n 800e6c2 { return SDMMC_ERROR_CC_ERR; 800e6bc: f44f 4300 mov.w r3, #32768 ; 0x8000 800e6c0: e039 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) 800e6c2: 697b ldr r3, [r7, #20] 800e6c4: f403 2380 and.w r3, r3, #262144 ; 0x40000 800e6c8: 2b00 cmp r3, #0 800e6ca: d002 beq.n 800e6d2 { return SDMMC_ERROR_STREAM_READ_UNDERRUN; 800e6cc: f44f 3300 mov.w r3, #131072 ; 0x20000 800e6d0: e031 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) 800e6d2: 697b ldr r3, [r7, #20] 800e6d4: f403 3300 and.w r3, r3, #131072 ; 0x20000 800e6d8: 2b00 cmp r3, #0 800e6da: d002 beq.n 800e6e2 { return SDMMC_ERROR_STREAM_WRITE_OVERRUN; 800e6dc: f44f 2380 mov.w r3, #262144 ; 0x40000 800e6e0: e029 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) 800e6e2: 697b ldr r3, [r7, #20] 800e6e4: f403 3380 and.w r3, r3, #65536 ; 0x10000 800e6e8: 2b00 cmp r3, #0 800e6ea: d002 beq.n 800e6f2 { return SDMMC_ERROR_CID_CSD_OVERWRITE; 800e6ec: f44f 2300 mov.w r3, #524288 ; 0x80000 800e6f0: e021 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) 800e6f2: 697b ldr r3, [r7, #20] 800e6f4: f403 4300 and.w r3, r3, #32768 ; 0x8000 800e6f8: 2b00 cmp r3, #0 800e6fa: d002 beq.n 800e702 { return SDMMC_ERROR_WP_ERASE_SKIP; 800e6fc: f44f 1380 mov.w r3, #1048576 ; 0x100000 800e700: e019 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) 800e702: 697b ldr r3, [r7, #20] 800e704: f403 4380 and.w r3, r3, #16384 ; 0x4000 800e708: 2b00 cmp r3, #0 800e70a: d002 beq.n 800e712 { return SDMMC_ERROR_CARD_ECC_DISABLED; 800e70c: f44f 1300 mov.w r3, #2097152 ; 0x200000 800e710: e011 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) 800e712: 697b ldr r3, [r7, #20] 800e714: f403 5300 and.w r3, r3, #8192 ; 0x2000 800e718: 2b00 cmp r3, #0 800e71a: d002 beq.n 800e722 { return SDMMC_ERROR_ERASE_RESET; 800e71c: f44f 0380 mov.w r3, #4194304 ; 0x400000 800e720: e009 b.n 800e736 } else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) 800e722: 697b ldr r3, [r7, #20] 800e724: f003 0308 and.w r3, r3, #8 800e728: 2b00 cmp r3, #0 800e72a: d002 beq.n 800e732 { return SDMMC_ERROR_AKE_SEQ_ERR; 800e72c: f44f 0300 mov.w r3, #8388608 ; 0x800000 800e730: e001 b.n 800e736 } else { return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; 800e732: f44f 3380 mov.w r3, #65536 ; 0x10000 } } 800e736: 4618 mov r0, r3 800e738: 3720 adds r7, #32 800e73a: 46bd mov sp, r7 800e73c: bd80 pop {r7, pc} 800e73e: bf00 nop 800e740: 24000014 .word 0x24000014 800e744: 10624dd3 .word 0x10624dd3 800e748: 00200045 .word 0x00200045 800e74c: 002000c5 .word 0x002000c5 800e750: fdffe008 .word 0xfdffe008 0800e754 : * @brief Checks for error conditions for R2 (CID or CSD) response. * @param hsd: SD handle * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) { 800e754: b480 push {r7} 800e756: b085 sub sp, #20 800e758: af00 add r7, sp, #0 800e75a: 6078 str r0, [r7, #4] uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); 800e75c: 4b1f ldr r3, [pc, #124] ; (800e7dc ) 800e75e: 681b ldr r3, [r3, #0] 800e760: 4a1f ldr r2, [pc, #124] ; (800e7e0 ) 800e762: fba2 2303 umull r2, r3, r2, r3 800e766: 0a5b lsrs r3, r3, #9 800e768: f241 3288 movw r2, #5000 ; 0x1388 800e76c: fb02 f303 mul.w r3, r2, r3 800e770: 60fb str r3, [r7, #12] do { if (count-- == 0U) 800e772: 68fb ldr r3, [r7, #12] 800e774: 1e5a subs r2, r3, #1 800e776: 60fa str r2, [r7, #12] 800e778: 2b00 cmp r3, #0 800e77a: d102 bne.n 800e782 { return SDMMC_ERROR_TIMEOUT; 800e77c: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800e780: e026 b.n 800e7d0 } sta_reg = SDMMCx->STA; 800e782: 687b ldr r3, [r7, #4] 800e784: 6b5b ldr r3, [r3, #52] ; 0x34 800e786: 60bb str r3, [r7, #8] } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e788: 68bb ldr r3, [r7, #8] 800e78a: f003 0345 and.w r3, r3, #69 ; 0x45 800e78e: 2b00 cmp r3, #0 800e790: d0ef beq.n 800e772 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); 800e792: 68bb ldr r3, [r7, #8] 800e794: f403 5300 and.w r3, r3, #8192 ; 0x2000 } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e798: 2b00 cmp r3, #0 800e79a: d1ea bne.n 800e772 if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) 800e79c: 687b ldr r3, [r7, #4] 800e79e: 6b5b ldr r3, [r3, #52] ; 0x34 800e7a0: f003 0304 and.w r3, r3, #4 800e7a4: 2b00 cmp r3, #0 800e7a6: d004 beq.n 800e7b2 { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); 800e7a8: 687b ldr r3, [r7, #4] 800e7aa: 2204 movs r2, #4 800e7ac: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 800e7ae: 2304 movs r3, #4 800e7b0: e00e b.n 800e7d0 } else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) 800e7b2: 687b ldr r3, [r7, #4] 800e7b4: 6b5b ldr r3, [r3, #52] ; 0x34 800e7b6: f003 0301 and.w r3, r3, #1 800e7ba: 2b00 cmp r3, #0 800e7bc: d004 beq.n 800e7c8 { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); 800e7be: 687b ldr r3, [r7, #4] 800e7c0: 2201 movs r2, #1 800e7c2: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 800e7c4: 2301 movs r3, #1 800e7c6: e003 b.n 800e7d0 } else { /* No error flag set */ /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); 800e7c8: 687b ldr r3, [r7, #4] 800e7ca: 4a06 ldr r2, [pc, #24] ; (800e7e4 ) 800e7cc: 639a str r2, [r3, #56] ; 0x38 } return SDMMC_ERROR_NONE; 800e7ce: 2300 movs r3, #0 } 800e7d0: 4618 mov r0, r3 800e7d2: 3714 adds r7, #20 800e7d4: 46bd mov sp, r7 800e7d6: f85d 7b04 ldr.w r7, [sp], #4 800e7da: 4770 bx lr 800e7dc: 24000014 .word 0x24000014 800e7e0: 10624dd3 .word 0x10624dd3 800e7e4: 002000c5 .word 0x002000c5 0800e7e8 : * @brief Checks for error conditions for R3 (OCR) response. * @param hsd: SD handle * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) { 800e7e8: b480 push {r7} 800e7ea: b085 sub sp, #20 800e7ec: af00 add r7, sp, #0 800e7ee: 6078 str r0, [r7, #4] uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); 800e7f0: 4b1a ldr r3, [pc, #104] ; (800e85c ) 800e7f2: 681b ldr r3, [r3, #0] 800e7f4: 4a1a ldr r2, [pc, #104] ; (800e860 ) 800e7f6: fba2 2303 umull r2, r3, r2, r3 800e7fa: 0a5b lsrs r3, r3, #9 800e7fc: f241 3288 movw r2, #5000 ; 0x1388 800e800: fb02 f303 mul.w r3, r2, r3 800e804: 60fb str r3, [r7, #12] do { if (count-- == 0U) 800e806: 68fb ldr r3, [r7, #12] 800e808: 1e5a subs r2, r3, #1 800e80a: 60fa str r2, [r7, #12] 800e80c: 2b00 cmp r3, #0 800e80e: d102 bne.n 800e816 { return SDMMC_ERROR_TIMEOUT; 800e810: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800e814: e01b b.n 800e84e } sta_reg = SDMMCx->STA; 800e816: 687b ldr r3, [r7, #4] 800e818: 6b5b ldr r3, [r3, #52] ; 0x34 800e81a: 60bb str r3, [r7, #8] } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e81c: 68bb ldr r3, [r7, #8] 800e81e: f003 0345 and.w r3, r3, #69 ; 0x45 800e822: 2b00 cmp r3, #0 800e824: d0ef beq.n 800e806 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); 800e826: 68bb ldr r3, [r7, #8] 800e828: f403 5300 and.w r3, r3, #8192 ; 0x2000 } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e82c: 2b00 cmp r3, #0 800e82e: d1ea bne.n 800e806 if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) 800e830: 687b ldr r3, [r7, #4] 800e832: 6b5b ldr r3, [r3, #52] ; 0x34 800e834: f003 0304 and.w r3, r3, #4 800e838: 2b00 cmp r3, #0 800e83a: d004 beq.n 800e846 { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); 800e83c: 687b ldr r3, [r7, #4] 800e83e: 2204 movs r2, #4 800e840: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 800e842: 2304 movs r3, #4 800e844: e003 b.n 800e84e } else { /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); 800e846: 687b ldr r3, [r7, #4] 800e848: 4a06 ldr r2, [pc, #24] ; (800e864 ) 800e84a: 639a str r2, [r3, #56] ; 0x38 } return SDMMC_ERROR_NONE; 800e84c: 2300 movs r3, #0 } 800e84e: 4618 mov r0, r3 800e850: 3714 adds r7, #20 800e852: 46bd mov sp, r7 800e854: f85d 7b04 ldr.w r7, [sp], #4 800e858: 4770 bx lr 800e85a: bf00 nop 800e85c: 24000014 .word 0x24000014 800e860: 10624dd3 .word 0x10624dd3 800e864: 002000c5 .word 0x002000c5 0800e868 : * @param pRCA: Pointer to the variable that will contain the SD card relative * address RCA * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) { 800e868: b580 push {r7, lr} 800e86a: b088 sub sp, #32 800e86c: af00 add r7, sp, #0 800e86e: 60f8 str r0, [r7, #12] 800e870: 460b mov r3, r1 800e872: 607a str r2, [r7, #4] 800e874: 72fb strb r3, [r7, #11] uint32_t response_r1; uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); 800e876: 4b35 ldr r3, [pc, #212] ; (800e94c ) 800e878: 681b ldr r3, [r3, #0] 800e87a: 4a35 ldr r2, [pc, #212] ; (800e950 ) 800e87c: fba2 2303 umull r2, r3, r2, r3 800e880: 0a5b lsrs r3, r3, #9 800e882: f241 3288 movw r2, #5000 ; 0x1388 800e886: fb02 f303 mul.w r3, r2, r3 800e88a: 61fb str r3, [r7, #28] do { if (count-- == 0U) 800e88c: 69fb ldr r3, [r7, #28] 800e88e: 1e5a subs r2, r3, #1 800e890: 61fa str r2, [r7, #28] 800e892: 2b00 cmp r3, #0 800e894: d102 bne.n 800e89c { return SDMMC_ERROR_TIMEOUT; 800e896: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800e89a: e052 b.n 800e942 } sta_reg = SDMMCx->STA; 800e89c: 68fb ldr r3, [r7, #12] 800e89e: 6b5b ldr r3, [r3, #52] ; 0x34 800e8a0: 61bb str r3, [r7, #24] } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e8a2: 69bb ldr r3, [r7, #24] 800e8a4: f003 0345 and.w r3, r3, #69 ; 0x45 800e8a8: 2b00 cmp r3, #0 800e8aa: d0ef beq.n 800e88c ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); 800e8ac: 69bb ldr r3, [r7, #24] 800e8ae: f403 5300 and.w r3, r3, #8192 ; 0x2000 } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e8b2: 2b00 cmp r3, #0 800e8b4: d1ea bne.n 800e88c if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) 800e8b6: 68fb ldr r3, [r7, #12] 800e8b8: 6b5b ldr r3, [r3, #52] ; 0x34 800e8ba: f003 0304 and.w r3, r3, #4 800e8be: 2b00 cmp r3, #0 800e8c0: d004 beq.n 800e8cc { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); 800e8c2: 68fb ldr r3, [r7, #12] 800e8c4: 2204 movs r2, #4 800e8c6: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 800e8c8: 2304 movs r3, #4 800e8ca: e03a b.n 800e942 } else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) 800e8cc: 68fb ldr r3, [r7, #12] 800e8ce: 6b5b ldr r3, [r3, #52] ; 0x34 800e8d0: f003 0301 and.w r3, r3, #1 800e8d4: 2b00 cmp r3, #0 800e8d6: d004 beq.n 800e8e2 { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); 800e8d8: 68fb ldr r3, [r7, #12] 800e8da: 2201 movs r2, #1 800e8dc: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 800e8de: 2301 movs r3, #1 800e8e0: e02f b.n 800e942 { /* Nothing to do */ } /* Check response received is of desired command */ if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) 800e8e2: 68f8 ldr r0, [r7, #12] 800e8e4: f7ff fb7c bl 800dfe0 800e8e8: 4603 mov r3, r0 800e8ea: 461a mov r2, r3 800e8ec: 7afb ldrb r3, [r7, #11] 800e8ee: 4293 cmp r3, r2 800e8f0: d001 beq.n 800e8f6 { return SDMMC_ERROR_CMD_CRC_FAIL; 800e8f2: 2301 movs r3, #1 800e8f4: e025 b.n 800e942 } /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); 800e8f6: 68fb ldr r3, [r7, #12] 800e8f8: 4a16 ldr r2, [pc, #88] ; (800e954 ) 800e8fa: 639a str r2, [r3, #56] ; 0x38 /* We have received response, retrieve it. */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); 800e8fc: 2100 movs r1, #0 800e8fe: 68f8 ldr r0, [r7, #12] 800e900: f7ff fb7b bl 800dffa 800e904: 6178 str r0, [r7, #20] if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | 800e906: 697b ldr r3, [r7, #20] 800e908: f403 4360 and.w r3, r3, #57344 ; 0xe000 800e90c: 2b00 cmp r3, #0 800e90e: d106 bne.n 800e91e SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) { *pRCA = (uint16_t)(response_r1 >> 16); 800e910: 697b ldr r3, [r7, #20] 800e912: 0c1b lsrs r3, r3, #16 800e914: b29a uxth r2, r3 800e916: 687b ldr r3, [r7, #4] 800e918: 801a strh r2, [r3, #0] return SDMMC_ERROR_NONE; 800e91a: 2300 movs r3, #0 800e91c: e011 b.n 800e942 } else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) 800e91e: 697b ldr r3, [r7, #20] 800e920: f403 4380 and.w r3, r3, #16384 ; 0x4000 800e924: 2b00 cmp r3, #0 800e926: d002 beq.n 800e92e { return SDMMC_ERROR_ILLEGAL_CMD; 800e928: f44f 5300 mov.w r3, #8192 ; 0x2000 800e92c: e009 b.n 800e942 } else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) 800e92e: 697b ldr r3, [r7, #20] 800e930: f403 4300 and.w r3, r3, #32768 ; 0x8000 800e934: 2b00 cmp r3, #0 800e936: d002 beq.n 800e93e { return SDMMC_ERROR_COM_CRC_FAILED; 800e938: f44f 5380 mov.w r3, #4096 ; 0x1000 800e93c: e001 b.n 800e942 } else { return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; 800e93e: f44f 3380 mov.w r3, #65536 ; 0x10000 } } 800e942: 4618 mov r0, r3 800e944: 3720 adds r7, #32 800e946: 46bd mov sp, r7 800e948: bd80 pop {r7, pc} 800e94a: bf00 nop 800e94c: 24000014 .word 0x24000014 800e950: 10624dd3 .word 0x10624dd3 800e954: 002000c5 .word 0x002000c5 0800e958 : * @brief Checks for error conditions for R7 response. * @param hsd: SD handle * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) { 800e958: b480 push {r7} 800e95a: b085 sub sp, #20 800e95c: af00 add r7, sp, #0 800e95e: 6078 str r0, [r7, #4] uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); 800e960: 4b22 ldr r3, [pc, #136] ; (800e9ec ) 800e962: 681b ldr r3, [r3, #0] 800e964: 4a22 ldr r2, [pc, #136] ; (800e9f0 ) 800e966: fba2 2303 umull r2, r3, r2, r3 800e96a: 0a5b lsrs r3, r3, #9 800e96c: f241 3288 movw r2, #5000 ; 0x1388 800e970: fb02 f303 mul.w r3, r2, r3 800e974: 60fb str r3, [r7, #12] do { if (count-- == 0U) 800e976: 68fb ldr r3, [r7, #12] 800e978: 1e5a subs r2, r3, #1 800e97a: 60fa str r2, [r7, #12] 800e97c: 2b00 cmp r3, #0 800e97e: d102 bne.n 800e986 { return SDMMC_ERROR_TIMEOUT; 800e980: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800e984: e02c b.n 800e9e0 } sta_reg = SDMMCx->STA; 800e986: 687b ldr r3, [r7, #4] 800e988: 6b5b ldr r3, [r3, #52] ; 0x34 800e98a: 60bb str r3, [r7, #8] } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e98c: 68bb ldr r3, [r7, #8] 800e98e: f003 0345 and.w r3, r3, #69 ; 0x45 800e992: 2b00 cmp r3, #0 800e994: d0ef beq.n 800e976 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); 800e996: 68bb ldr r3, [r7, #8] 800e998: f403 5300 and.w r3, r3, #8192 ; 0x2000 } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e99c: 2b00 cmp r3, #0 800e99e: d1ea bne.n 800e976 if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) 800e9a0: 687b ldr r3, [r7, #4] 800e9a2: 6b5b ldr r3, [r3, #52] ; 0x34 800e9a4: f003 0304 and.w r3, r3, #4 800e9a8: 2b00 cmp r3, #0 800e9aa: d004 beq.n 800e9b6 { /* Card is not SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); 800e9ac: 687b ldr r3, [r7, #4] 800e9ae: 2204 movs r2, #4 800e9b0: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 800e9b2: 2304 movs r3, #4 800e9b4: e014 b.n 800e9e0 } else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) 800e9b6: 687b ldr r3, [r7, #4] 800e9b8: 6b5b ldr r3, [r3, #52] ; 0x34 800e9ba: f003 0301 and.w r3, r3, #1 800e9be: 2b00 cmp r3, #0 800e9c0: d004 beq.n 800e9cc { /* Card is not SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); 800e9c2: 687b ldr r3, [r7, #4] 800e9c4: 2201 movs r2, #1 800e9c6: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 800e9c8: 2301 movs r3, #1 800e9ca: e009 b.n 800e9e0 else { /* Nothing to do */ } if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) 800e9cc: 687b ldr r3, [r7, #4] 800e9ce: 6b5b ldr r3, [r3, #52] ; 0x34 800e9d0: f003 0340 and.w r3, r3, #64 ; 0x40 800e9d4: 2b00 cmp r3, #0 800e9d6: d002 beq.n 800e9de { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); 800e9d8: 687b ldr r3, [r7, #4] 800e9da: 2240 movs r2, #64 ; 0x40 800e9dc: 639a str r2, [r3, #56] ; 0x38 } return SDMMC_ERROR_NONE; 800e9de: 2300 movs r3, #0 } 800e9e0: 4618 mov r0, r3 800e9e2: 3714 adds r7, #20 800e9e4: 46bd mov sp, r7 800e9e6: f85d 7b04 ldr.w r7, [sp], #4 800e9ea: 4770 bx lr 800e9ec: 24000014 .word 0x24000014 800e9f0: 10624dd3 .word 0x10624dd3 0800e9f4 : * @brief Checks for error conditions for CMD0. * @param hsd: SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) { 800e9f4: b480 push {r7} 800e9f6: b085 sub sp, #20 800e9f8: af00 add r7, sp, #0 800e9fa: 6078 str r0, [r7, #4] /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); 800e9fc: 4b11 ldr r3, [pc, #68] ; (800ea44 ) 800e9fe: 681b ldr r3, [r3, #0] 800ea00: 4a11 ldr r2, [pc, #68] ; (800ea48 ) 800ea02: fba2 2303 umull r2, r3, r2, r3 800ea06: 0a5b lsrs r3, r3, #9 800ea08: f241 3288 movw r2, #5000 ; 0x1388 800ea0c: fb02 f303 mul.w r3, r2, r3 800ea10: 60fb str r3, [r7, #12] do { if (count-- == 0U) 800ea12: 68fb ldr r3, [r7, #12] 800ea14: 1e5a subs r2, r3, #1 800ea16: 60fa str r2, [r7, #12] 800ea18: 2b00 cmp r3, #0 800ea1a: d102 bne.n 800ea22 { return SDMMC_ERROR_TIMEOUT; 800ea1c: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800ea20: e009 b.n 800ea36 } } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); 800ea22: 687b ldr r3, [r7, #4] 800ea24: 6b5b ldr r3, [r3, #52] ; 0x34 800ea26: f003 0380 and.w r3, r3, #128 ; 0x80 800ea2a: 2b00 cmp r3, #0 800ea2c: d0f1 beq.n 800ea12 /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); 800ea2e: 687b ldr r3, [r7, #4] 800ea30: 4a06 ldr r2, [pc, #24] ; (800ea4c ) 800ea32: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_NONE; 800ea34: 2300 movs r3, #0 } 800ea36: 4618 mov r0, r3 800ea38: 3714 adds r7, #20 800ea3a: 46bd mov sp, r7 800ea3c: f85d 7b04 ldr.w r7, [sp], #4 800ea40: 4770 bx lr 800ea42: bf00 nop 800ea44: 24000014 .word 0x24000014 800ea48: 10624dd3 .word 0x10624dd3 800ea4c: 002000c5 .word 0x002000c5 0800ea50 : /* USER CODE BEGIN Variables */ /* USER CODE END Variables */ void MX_FATFS_Init(void) { 800ea50: b580 push {r7, lr} 800ea52: af00 add r7, sp, #0 /*## FatFS: Link the SD driver ###########################*/ retSD = FATFS_LinkDriver(&SD_Driver, SDPath); 800ea54: 4904 ldr r1, [pc, #16] ; (800ea68 ) 800ea56: 4805 ldr r0, [pc, #20] ; (800ea6c ) 800ea58: f001 fbea bl 8010230 800ea5c: 4603 mov r3, r0 800ea5e: 461a mov r2, r3 800ea60: 4b03 ldr r3, [pc, #12] ; (800ea70 ) 800ea62: 701a strb r2, [r3, #0] /* USER CODE BEGIN Init */ /* additional user code for init */ /* USER CODE END Init */ } 800ea64: bf00 nop 800ea66: bd80 pop {r7, pc} 800ea68: 240073dc .word 0x240073dc 800ea6c: 08026b80 .word 0x08026b80 800ea70: 240073d8 .word 0x240073d8 0800ea74 : /** * @brief Initializes the SD card device. * @retval SD status */ __weak uint8_t BSP_SD_Init(void) { 800ea74: b580 push {r7, lr} 800ea76: b082 sub sp, #8 800ea78: af00 add r7, sp, #0 uint8_t sd_state = MSD_OK; 800ea7a: 2300 movs r3, #0 800ea7c: 71fb strb r3, [r7, #7] /* Check if the SD card is plugged in the slot */ if (BSP_SD_IsDetected() != SD_PRESENT) 800ea7e: f000 f885 bl 800eb8c 800ea82: 4603 mov r3, r0 800ea84: 2b01 cmp r3, #1 800ea86: d001 beq.n 800ea8c { return MSD_ERROR_SD_NOT_PRESENT; 800ea88: 2302 movs r3, #2 800ea8a: e012 b.n 800eab2 } /* HAL SD initialization */ sd_state = HAL_SD_Init(&hsd1); 800ea8c: 480b ldr r0, [pc, #44] ; (800eabc ) 800ea8e: f7fb febb bl 800a808 800ea92: 4603 mov r3, r0 800ea94: 71fb strb r3, [r7, #7] /* Configure SD Bus width (4 bits mode selected) */ if (sd_state == MSD_OK) 800ea96: 79fb ldrb r3, [r7, #7] 800ea98: 2b00 cmp r3, #0 800ea9a: d109 bne.n 800eab0 { /* Enable wide operation */ if (HAL_SD_ConfigWideBusOperation(&hsd1, SDMMC_BUS_WIDE_4B) != HAL_OK) 800ea9c: f44f 4180 mov.w r1, #16384 ; 0x4000 800eaa0: 4806 ldr r0, [pc, #24] ; (800eabc ) 800eaa2: f7fc fd71 bl 800b588 800eaa6: 4603 mov r3, r0 800eaa8: 2b00 cmp r3, #0 800eaaa: d001 beq.n 800eab0 { sd_state = MSD_ERROR; 800eaac: 2301 movs r3, #1 800eaae: 71fb strb r3, [r7, #7] } } return sd_state; 800eab0: 79fb ldrb r3, [r7, #7] } 800eab2: 4618 mov r0, r3 800eab4: 3708 adds r7, #8 800eab6: 46bd mov sp, r7 800eab8: bd80 pop {r7, pc} 800eaba: bf00 nop 800eabc: 24000f48 .word 0x24000f48 0800eac0 : * @param ReadAddr: Address from where data is to be read * @param NumOfBlocks: Number of SD blocks to read * @retval SD status */ __weak uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks) { 800eac0: b580 push {r7, lr} 800eac2: b086 sub sp, #24 800eac4: af00 add r7, sp, #0 800eac6: 60f8 str r0, [r7, #12] 800eac8: 60b9 str r1, [r7, #8] 800eaca: 607a str r2, [r7, #4] uint8_t sd_state = MSD_OK; 800eacc: 2300 movs r3, #0 800eace: 75fb strb r3, [r7, #23] /* Read block(s) in DMA transfer mode */ if (HAL_SD_ReadBlocks_DMA(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK) 800ead0: 687b ldr r3, [r7, #4] 800ead2: 68ba ldr r2, [r7, #8] 800ead4: 68f9 ldr r1, [r7, #12] 800ead6: 4806 ldr r0, [pc, #24] ; (800eaf0 ) 800ead8: f7fb ffb6 bl 800aa48 800eadc: 4603 mov r3, r0 800eade: 2b00 cmp r3, #0 800eae0: d001 beq.n 800eae6 { sd_state = MSD_ERROR; 800eae2: 2301 movs r3, #1 800eae4: 75fb strb r3, [r7, #23] } return sd_state; 800eae6: 7dfb ldrb r3, [r7, #23] } 800eae8: 4618 mov r0, r3 800eaea: 3718 adds r7, #24 800eaec: 46bd mov sp, r7 800eaee: bd80 pop {r7, pc} 800eaf0: 24000f48 .word 0x24000f48 0800eaf4 : * @param WriteAddr: Address from where data is to be written * @param NumOfBlocks: Number of SD blocks to write * @retval SD status */ __weak uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks) { 800eaf4: b580 push {r7, lr} 800eaf6: b086 sub sp, #24 800eaf8: af00 add r7, sp, #0 800eafa: 60f8 str r0, [r7, #12] 800eafc: 60b9 str r1, [r7, #8] 800eafe: 607a str r2, [r7, #4] uint8_t sd_state = MSD_OK; 800eb00: 2300 movs r3, #0 800eb02: 75fb strb r3, [r7, #23] /* Write block(s) in DMA transfer mode */ if (HAL_SD_WriteBlocks_DMA(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK) 800eb04: 687b ldr r3, [r7, #4] 800eb06: 68ba ldr r2, [r7, #8] 800eb08: 68f9 ldr r1, [r7, #12] 800eb0a: 4806 ldr r0, [pc, #24] ; (800eb24 ) 800eb0c: f7fc f844 bl 800ab98 800eb10: 4603 mov r3, r0 800eb12: 2b00 cmp r3, #0 800eb14: d001 beq.n 800eb1a { sd_state = MSD_ERROR; 800eb16: 2301 movs r3, #1 800eb18: 75fb strb r3, [r7, #23] } return sd_state; 800eb1a: 7dfb ldrb r3, [r7, #23] } 800eb1c: 4618 mov r0, r3 800eb1e: 3718 adds r7, #24 800eb20: 46bd mov sp, r7 800eb22: bd80 pop {r7, pc} 800eb24: 24000f48 .word 0x24000f48 0800eb28 : * This value can be one of the following values: * @arg SD_TRANSFER_OK: No data transfer is acting * @arg SD_TRANSFER_BUSY: Data transfer is acting */ __weak uint8_t BSP_SD_GetCardState(void) { 800eb28: b580 push {r7, lr} 800eb2a: af00 add r7, sp, #0 return ((HAL_SD_GetCardState(&hsd1) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY); 800eb2c: 4805 ldr r0, [pc, #20] ; (800eb44 ) 800eb2e: f7fc fe3d bl 800b7ac 800eb32: 4603 mov r3, r0 800eb34: 2b04 cmp r3, #4 800eb36: bf14 ite ne 800eb38: 2301 movne r3, #1 800eb3a: 2300 moveq r3, #0 800eb3c: b2db uxtb r3, r3 } 800eb3e: 4618 mov r0, r3 800eb40: bd80 pop {r7, pc} 800eb42: bf00 nop 800eb44: 24000f48 .word 0x24000f48 0800eb48 : * @brief Get SD information about specific SD card. * @param CardInfo: Pointer to HAL_SD_CardInfoTypedef structure * @retval None */ __weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo) { 800eb48: b580 push {r7, lr} 800eb4a: b082 sub sp, #8 800eb4c: af00 add r7, sp, #0 800eb4e: 6078 str r0, [r7, #4] /* Get SD card Information */ HAL_SD_GetCardInfo(&hsd1, CardInfo); 800eb50: 6879 ldr r1, [r7, #4] 800eb52: 4803 ldr r0, [pc, #12] ; (800eb60 ) 800eb54: f7fc fcec bl 800b530 } 800eb58: bf00 nop 800eb5a: 3708 adds r7, #8 800eb5c: 46bd mov sp, r7 800eb5e: bd80 pop {r7, pc} 800eb60: 24000f48 .word 0x24000f48 0800eb64 : * @brief Tx Transfer completed callback * @param hsd: SD handle * @retval None */ void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) { 800eb64: b580 push {r7, lr} 800eb66: b082 sub sp, #8 800eb68: af00 add r7, sp, #0 800eb6a: 6078 str r0, [r7, #4] BSP_SD_WriteCpltCallback(); 800eb6c: f000 f9bc bl 800eee8 } 800eb70: bf00 nop 800eb72: 3708 adds r7, #8 800eb74: 46bd mov sp, r7 800eb76: bd80 pop {r7, pc} 0800eb78 : * @brief Rx Transfer completed callback * @param hsd: SD handle * @retval None */ void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) { 800eb78: b580 push {r7, lr} 800eb7a: b082 sub sp, #8 800eb7c: af00 add r7, sp, #0 800eb7e: 6078 str r0, [r7, #4] BSP_SD_ReadCpltCallback(); 800eb80: f000 f9c0 bl 800ef04 } 800eb84: bf00 nop 800eb86: 3708 adds r7, #8 800eb88: 46bd mov sp, r7 800eb8a: bd80 pop {r7, pc} 0800eb8c : * @brief Detects if SD card is correctly plugged in the memory slot or not. * @param None * @retval Returns if SD is detected or not */ __weak uint8_t BSP_SD_IsDetected(void) { 800eb8c: b580 push {r7, lr} 800eb8e: b082 sub sp, #8 800eb90: af00 add r7, sp, #0 __IO uint8_t status = SD_PRESENT; 800eb92: 2301 movs r3, #1 800eb94: 71fb strb r3, [r7, #7] if (BSP_PlatformIsDetected() == 0x0) 800eb96: f000 f80b bl 800ebb0 800eb9a: 4603 mov r3, r0 800eb9c: 2b00 cmp r3, #0 800eb9e: d101 bne.n 800eba4 { status = SD_NOT_PRESENT; 800eba0: 2300 movs r3, #0 800eba2: 71fb strb r3, [r7, #7] } return status; 800eba4: 79fb ldrb r3, [r7, #7] 800eba6: b2db uxtb r3, r3 } 800eba8: 4618 mov r0, r3 800ebaa: 3708 adds r7, #8 800ebac: 46bd mov sp, r7 800ebae: bd80 pop {r7, pc} 0800ebb0 : ****************************************************************************** */ /* USER CODE END Header */ #include "fatfs_platform.h" uint8_t BSP_PlatformIsDetected(void) { 800ebb0: b580 push {r7, lr} 800ebb2: b082 sub sp, #8 800ebb4: af00 add r7, sp, #0 uint8_t status = SD_PRESENT; 800ebb6: 2301 movs r3, #1 800ebb8: 71fb strb r3, [r7, #7] /* Check SD card detect pin */ if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET) 800ebba: f44f 4100 mov.w r1, #32768 ; 0x8000 800ebbe: 4806 ldr r0, [pc, #24] ; (800ebd8 ) 800ebc0: f7f7 ff9e bl 8006b00 800ebc4: 4603 mov r3, r0 800ebc6: 2b00 cmp r3, #0 800ebc8: d001 beq.n 800ebce { status = SD_NOT_PRESENT; 800ebca: 2300 movs r3, #0 800ebcc: 71fb strb r3, [r7, #7] } /* USER CODE BEGIN 1 */ /* user code can be inserted here */ /* USER CODE END 1 */ return status; 800ebce: 79fb ldrb r3, [r7, #7] } 800ebd0: 4618 mov r0, r3 800ebd2: 3708 adds r7, #8 800ebd4: 46bd mov sp, r7 800ebd6: bd80 pop {r7, pc} 800ebd8: 58020400 .word 0x58020400 0800ebdc : /* USER CODE END beforeFunctionSection */ /* Private functions ---------------------------------------------------------*/ static int SD_CheckStatusWithTimeout(uint32_t timeout) { 800ebdc: b580 push {r7, lr} 800ebde: b084 sub sp, #16 800ebe0: af00 add r7, sp, #0 800ebe2: 6078 str r0, [r7, #4] uint32_t timer; /* block until SDIO peripheral is ready again or a timeout occur */ #if (osCMSIS <= 0x20000U) timer = osKernelSysTick(); 800ebe4: f001 fb70 bl 80102c8 800ebe8: 60f8 str r0, [r7, #12] while( osKernelSysTick() - timer < timeout) 800ebea: e006 b.n 800ebfa #else timer = osKernelGetTickCount(); while( osKernelGetTickCount() - timer < timeout) #endif { if (BSP_SD_GetCardState() == SD_TRANSFER_OK) 800ebec: f7ff ff9c bl 800eb28 800ebf0: 4603 mov r3, r0 800ebf2: 2b00 cmp r3, #0 800ebf4: d101 bne.n 800ebfa { return 0; 800ebf6: 2300 movs r3, #0 800ebf8: e009 b.n 800ec0e while( osKernelSysTick() - timer < timeout) 800ebfa: f001 fb65 bl 80102c8 800ebfe: 4602 mov r2, r0 800ec00: 68fb ldr r3, [r7, #12] 800ec02: 1ad3 subs r3, r2, r3 800ec04: 687a ldr r2, [r7, #4] 800ec06: 429a cmp r2, r3 800ec08: d8f0 bhi.n 800ebec } } return -1; 800ec0a: f04f 33ff mov.w r3, #4294967295 } 800ec0e: 4618 mov r0, r3 800ec10: 3710 adds r7, #16 800ec12: 46bd mov sp, r7 800ec14: bd80 pop {r7, pc} ... 0800ec18 : static DSTATUS SD_CheckStatus(BYTE lun) { 800ec18: b580 push {r7, lr} 800ec1a: b082 sub sp, #8 800ec1c: af00 add r7, sp, #0 800ec1e: 4603 mov r3, r0 800ec20: 71fb strb r3, [r7, #7] Stat = STA_NOINIT; 800ec22: 4b0b ldr r3, [pc, #44] ; (800ec50 ) 800ec24: 2201 movs r2, #1 800ec26: 701a strb r2, [r3, #0] if(BSP_SD_GetCardState() == SD_TRANSFER_OK) 800ec28: f7ff ff7e bl 800eb28 800ec2c: 4603 mov r3, r0 800ec2e: 2b00 cmp r3, #0 800ec30: d107 bne.n 800ec42 { Stat &= ~STA_NOINIT; 800ec32: 4b07 ldr r3, [pc, #28] ; (800ec50 ) 800ec34: 781b ldrb r3, [r3, #0] 800ec36: b2db uxtb r3, r3 800ec38: f023 0301 bic.w r3, r3, #1 800ec3c: b2da uxtb r2, r3 800ec3e: 4b04 ldr r3, [pc, #16] ; (800ec50 ) 800ec40: 701a strb r2, [r3, #0] } return Stat; 800ec42: 4b03 ldr r3, [pc, #12] ; (800ec50 ) 800ec44: 781b ldrb r3, [r3, #0] 800ec46: b2db uxtb r3, r3 } 800ec48: 4618 mov r0, r3 800ec4a: 3708 adds r7, #8 800ec4c: 46bd mov sp, r7 800ec4e: bd80 pop {r7, pc} 800ec50: 24000021 .word 0x24000021 0800ec54 : * @brief Initializes a Drive * @param lun : not used * @retval DSTATUS: Operation status */ DSTATUS SD_initialize(BYTE lun) { 800ec54: b590 push {r4, r7, lr} 800ec56: b087 sub sp, #28 800ec58: af00 add r7, sp, #0 800ec5a: 4603 mov r3, r0 800ec5c: 71fb strb r3, [r7, #7] Stat = STA_NOINIT; 800ec5e: 4b20 ldr r3, [pc, #128] ; (800ece0 ) 800ec60: 2201 movs r2, #1 800ec62: 701a strb r2, [r3, #0] /* * check that the kernel has been started before continuing * as the osMessage API will fail otherwise */ #if (osCMSIS <= 0x20000U) if(osKernelRunning()) 800ec64: f001 fb24 bl 80102b0 800ec68: 4603 mov r3, r0 800ec6a: 2b00 cmp r3, #0 800ec6c: d030 beq.n 800ecd0 if(osKernelGetState() == osKernelRunning) #endif { #if !defined(DISABLE_SD_INIT) if(BSP_SD_Init() == MSD_OK) 800ec6e: f7ff ff01 bl 800ea74 800ec72: 4603 mov r3, r0 800ec74: 2b00 cmp r3, #0 800ec76: d107 bne.n 800ec88 { Stat = SD_CheckStatus(lun); 800ec78: 79fb ldrb r3, [r7, #7] 800ec7a: 4618 mov r0, r3 800ec7c: f7ff ffcc bl 800ec18 800ec80: 4603 mov r3, r0 800ec82: 461a mov r2, r3 800ec84: 4b16 ldr r3, [pc, #88] ; (800ece0 ) 800ec86: 701a strb r2, [r3, #0] /* * if the SD is correctly initialized, create the operation queue * if not already created */ if (Stat != STA_NOINIT) 800ec88: 4b15 ldr r3, [pc, #84] ; (800ece0 ) 800ec8a: 781b ldrb r3, [r3, #0] 800ec8c: b2db uxtb r3, r3 800ec8e: 2b01 cmp r3, #1 800ec90: d01e beq.n 800ecd0 { if (SDQueueID == NULL) 800ec92: 4b14 ldr r3, [pc, #80] ; (800ece4 ) 800ec94: 681b ldr r3, [r3, #0] 800ec96: 2b00 cmp r3, #0 800ec98: d10e bne.n 800ecb8 { #if (osCMSIS <= 0x20000U) osMessageQDef(SD_Queue, QUEUE_SIZE, uint16_t); 800ec9a: 4b13 ldr r3, [pc, #76] ; (800ece8 ) 800ec9c: f107 0408 add.w r4, r7, #8 800eca0: cb0f ldmia r3, {r0, r1, r2, r3} 800eca2: e884 000f stmia.w r4, {r0, r1, r2, r3} SDQueueID = osMessageCreate (osMessageQ(SD_Queue), NULL); 800eca6: f107 0308 add.w r3, r7, #8 800ecaa: 2100 movs r1, #0 800ecac: 4618 mov r0, r3 800ecae: f001 fce0 bl 8010672 800ecb2: 4603 mov r3, r0 800ecb4: 4a0b ldr r2, [pc, #44] ; (800ece4 ) 800ecb6: 6013 str r3, [r2, #0] #else SDQueueID = osMessageQueueNew(QUEUE_SIZE, 2, NULL); #endif } if (SDQueueID == NULL) 800ecb8: 4b0a ldr r3, [pc, #40] ; (800ece4 ) 800ecba: 681b ldr r3, [r3, #0] 800ecbc: 2b00 cmp r3, #0 800ecbe: d107 bne.n 800ecd0 { Stat |= STA_NOINIT; 800ecc0: 4b07 ldr r3, [pc, #28] ; (800ece0 ) 800ecc2: 781b ldrb r3, [r3, #0] 800ecc4: b2db uxtb r3, r3 800ecc6: f043 0301 orr.w r3, r3, #1 800ecca: b2da uxtb r2, r3 800eccc: 4b04 ldr r3, [pc, #16] ; (800ece0 ) 800ecce: 701a strb r2, [r3, #0] } } } return Stat; 800ecd0: 4b03 ldr r3, [pc, #12] ; (800ece0 ) 800ecd2: 781b ldrb r3, [r3, #0] 800ecd4: b2db uxtb r3, r3 } 800ecd6: 4618 mov r0, r3 800ecd8: 371c adds r7, #28 800ecda: 46bd mov sp, r7 800ecdc: bd90 pop {r4, r7, pc} 800ecde: bf00 nop 800ece0: 24000021 .word 0x24000021 800ece4: 240073e0 .word 0x240073e0 800ece8: 08022e84 .word 0x08022e84 0800ecec : * @brief Gets Disk Status * @param lun : not used * @retval DSTATUS: Operation status */ DSTATUS SD_status(BYTE lun) { 800ecec: b580 push {r7, lr} 800ecee: b082 sub sp, #8 800ecf0: af00 add r7, sp, #0 800ecf2: 4603 mov r3, r0 800ecf4: 71fb strb r3, [r7, #7] return SD_CheckStatus(lun); 800ecf6: 79fb ldrb r3, [r7, #7] 800ecf8: 4618 mov r0, r3 800ecfa: f7ff ff8d bl 800ec18 800ecfe: 4603 mov r3, r0 } 800ed00: 4618 mov r0, r3 800ed02: 3708 adds r7, #8 800ed04: 46bd mov sp, r7 800ed06: bd80 pop {r7, pc} 0800ed08 : * @param count: Number of sectors to read (1..128) * @retval DRESULT: Operation result */ DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) { 800ed08: b580 push {r7, lr} 800ed0a: b08a sub sp, #40 ; 0x28 800ed0c: af00 add r7, sp, #0 800ed0e: 60b9 str r1, [r7, #8] 800ed10: 607a str r2, [r7, #4] 800ed12: 603b str r3, [r7, #0] 800ed14: 4603 mov r3, r0 800ed16: 73fb strb r3, [r7, #15] uint8_t ret; DRESULT res = RES_ERROR; 800ed18: 2301 movs r3, #1 800ed1a: f887 3027 strb.w r3, [r7, #39] ; 0x27 #endif /* * ensure the SDCard is ready for a new operation */ if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) 800ed1e: f247 5030 movw r0, #30000 ; 0x7530 800ed22: f7ff ff5b bl 800ebdc 800ed26: 4603 mov r3, r0 800ed28: 2b00 cmp r3, #0 800ed2a: da02 bge.n 800ed32 { return res; 800ed2c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 800ed30: e032 b.n 800ed98 #if defined(ENABLE_SCRATCH_BUFFER) if (!((uint32_t)buff & 0x3)) { #endif /* Fast path cause destination buffer is correctly aligned */ ret = BSP_SD_ReadBlocks_DMA((uint32_t*)buff, (uint32_t)(sector), count); 800ed32: 683a ldr r2, [r7, #0] 800ed34: 6879 ldr r1, [r7, #4] 800ed36: 68b8 ldr r0, [r7, #8] 800ed38: f7ff fec2 bl 800eac0 800ed3c: 4603 mov r3, r0 800ed3e: f887 3026 strb.w r3, [r7, #38] ; 0x26 if (ret == MSD_OK) { 800ed42: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 800ed46: 2b00 cmp r3, #0 800ed48: d124 bne.n 800ed94 #if (osCMSIS < 0x20000U) /* wait for a message from the queue or a timeout */ event = osMessageGet(SDQueueID, SD_TIMEOUT); 800ed4a: 4b15 ldr r3, [pc, #84] ; (800eda0 ) 800ed4c: 6819 ldr r1, [r3, #0] 800ed4e: f107 0314 add.w r3, r7, #20 800ed52: f247 5230 movw r2, #30000 ; 0x7530 800ed56: 4618 mov r0, r3 800ed58: f001 fcf4 bl 8010744 if (event.status == osEventMessage) 800ed5c: 697b ldr r3, [r7, #20] 800ed5e: 2b10 cmp r3, #16 800ed60: d118 bne.n 800ed94 { if (event.value.v == READ_CPLT_MSG) 800ed62: 69bb ldr r3, [r7, #24] 800ed64: 2b01 cmp r3, #1 800ed66: d115 bne.n 800ed94 { timer = osKernelSysTick(); 800ed68: f001 faae bl 80102c8 800ed6c: 6238 str r0, [r7, #32] /* block until SDIO IP is ready or a timeout occur */ while(osKernelSysTick() - timer timer = osKernelGetTickCount(); /* block until SDIO IP is ready or a timeout occur */ while(osKernelGetTickCount() - timer 800ed74: 4603 mov r3, r0 800ed76: 2b00 cmp r3, #0 800ed78: d103 bne.n 800ed82 { res = RES_OK; 800ed7a: 2300 movs r3, #0 800ed7c: f887 3027 strb.w r3, [r7, #39] ; 0x27 adjust the address and the D-Cache size to invalidate accordingly. */ alignedAddr = (uint32_t)buff & ~0x1F; SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); #endif break; 800ed80: e008 b.n 800ed94 while(osKernelSysTick() - timer 800ed86: 4602 mov r2, r0 800ed88: 6a3b ldr r3, [r7, #32] 800ed8a: 1ad3 subs r3, r2, r3 800ed8c: f247 522f movw r2, #29999 ; 0x752f 800ed90: 4293 cmp r3, r2 800ed92: d9ed bls.n 800ed70 if ((i == count) && (ret == MSD_OK )) res = RES_OK; } #endif return res; 800ed94: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 } 800ed98: 4618 mov r0, r3 800ed9a: 3728 adds r7, #40 ; 0x28 800ed9c: 46bd mov sp, r7 800ed9e: bd80 pop {r7, pc} 800eda0: 240073e0 .word 0x240073e0 0800eda4 : * @retval DRESULT: Operation result */ #if _USE_WRITE == 1 DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) { 800eda4: b580 push {r7, lr} 800eda6: b08a sub sp, #40 ; 0x28 800eda8: af00 add r7, sp, #0 800edaa: 60b9 str r1, [r7, #8] 800edac: 607a str r2, [r7, #4] 800edae: 603b str r3, [r7, #0] 800edb0: 4603 mov r3, r0 800edb2: 73fb strb r3, [r7, #15] DRESULT res = RES_ERROR; 800edb4: 2301 movs r3, #1 800edb6: f887 3027 strb.w r3, [r7, #39] ; 0x27 /* * ensure the SDCard is ready for a new operation */ if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) 800edba: f247 5030 movw r0, #30000 ; 0x7530 800edbe: f7ff ff0d bl 800ebdc 800edc2: 4603 mov r3, r0 800edc4: 2b00 cmp r3, #0 800edc6: da02 bge.n 800edce { return res; 800edc8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 800edcc: e02e b.n 800ee2c */ alignedAddr = (uint32_t)buff & ~0x1F; SCB_CleanDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); #endif if(BSP_SD_WriteBlocks_DMA((uint32_t*)buff, 800edce: 683a ldr r2, [r7, #0] 800edd0: 6879 ldr r1, [r7, #4] 800edd2: 68b8 ldr r0, [r7, #8] 800edd4: f7ff fe8e bl 800eaf4 800edd8: 4603 mov r3, r0 800edda: 2b00 cmp r3, #0 800eddc: d124 bne.n 800ee28 (uint32_t) (sector), count) == MSD_OK) { #if (osCMSIS < 0x20000U) /* Get the message from the queue */ event = osMessageGet(SDQueueID, SD_TIMEOUT); 800edde: 4b15 ldr r3, [pc, #84] ; (800ee34 ) 800ede0: 6819 ldr r1, [r3, #0] 800ede2: f107 0314 add.w r3, r7, #20 800ede6: f247 5230 movw r2, #30000 ; 0x7530 800edea: 4618 mov r0, r3 800edec: f001 fcaa bl 8010744 if (event.status == osEventMessage) 800edf0: 697b ldr r3, [r7, #20] 800edf2: 2b10 cmp r3, #16 800edf4: d118 bne.n 800ee28 { if (event.value.v == WRITE_CPLT_MSG) 800edf6: 69bb ldr r3, [r7, #24] 800edf8: 2b02 cmp r3, #2 800edfa: d115 bne.n 800ee28 status = osMessageQueueGet(SDQueueID, (void *)&event, NULL, SD_TIMEOUT); if ((status == osOK) && (event == WRITE_CPLT_MSG)) { #endif #if (osCMSIS < 0x20000U) timer = osKernelSysTick(); 800edfc: f001 fa64 bl 80102c8 800ee00: 6238 str r0, [r7, #32] /* block until SDIO IP is ready or a timeout occur */ while(osKernelSysTick() - timer < SD_TIMEOUT) 800ee02: e008 b.n 800ee16 timer = osKernelGetTickCount(); /* block until SDIO IP is ready or a timeout occur */ while(osKernelGetTickCount() - timer < SD_TIMEOUT) #endif { if (BSP_SD_GetCardState() == SD_TRANSFER_OK) 800ee04: f7ff fe90 bl 800eb28 800ee08: 4603 mov r3, r0 800ee0a: 2b00 cmp r3, #0 800ee0c: d103 bne.n 800ee16 { res = RES_OK; 800ee0e: 2300 movs r3, #0 800ee10: f887 3027 strb.w r3, [r7, #39] ; 0x27 break; 800ee14: e008 b.n 800ee28 while(osKernelSysTick() - timer < SD_TIMEOUT) 800ee16: f001 fa57 bl 80102c8 800ee1a: 4602 mov r2, r0 800ee1c: 6a3b ldr r3, [r7, #32] 800ee1e: 1ad3 subs r3, r2, r3 800ee20: f247 522f movw r2, #29999 ; 0x752f 800ee24: 4293 cmp r3, r2 800ee26: d9ed bls.n 800ee04 } } #endif return res; 800ee28: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 } 800ee2c: 4618 mov r0, r3 800ee2e: 3728 adds r7, #40 ; 0x28 800ee30: 46bd mov sp, r7 800ee32: bd80 pop {r7, pc} 800ee34: 240073e0 .word 0x240073e0 0800ee38 : * @param *buff: Buffer to send/receive control data * @retval DRESULT: Operation result */ #if _USE_IOCTL == 1 DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) { 800ee38: b580 push {r7, lr} 800ee3a: b08c sub sp, #48 ; 0x30 800ee3c: af00 add r7, sp, #0 800ee3e: 4603 mov r3, r0 800ee40: 603a str r2, [r7, #0] 800ee42: 71fb strb r3, [r7, #7] 800ee44: 460b mov r3, r1 800ee46: 71bb strb r3, [r7, #6] DRESULT res = RES_ERROR; 800ee48: 2301 movs r3, #1 800ee4a: f887 302f strb.w r3, [r7, #47] ; 0x2f BSP_SD_CardInfo CardInfo; if (Stat & STA_NOINIT) return RES_NOTRDY; 800ee4e: 4b25 ldr r3, [pc, #148] ; (800eee4 ) 800ee50: 781b ldrb r3, [r3, #0] 800ee52: b2db uxtb r3, r3 800ee54: f003 0301 and.w r3, r3, #1 800ee58: 2b00 cmp r3, #0 800ee5a: d001 beq.n 800ee60 800ee5c: 2303 movs r3, #3 800ee5e: e03c b.n 800eeda switch (cmd) 800ee60: 79bb ldrb r3, [r7, #6] 800ee62: 2b03 cmp r3, #3 800ee64: d834 bhi.n 800eed0 800ee66: a201 add r2, pc, #4 ; (adr r2, 800ee6c ) 800ee68: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ee6c: 0800ee7d .word 0x0800ee7d 800ee70: 0800ee85 .word 0x0800ee85 800ee74: 0800ee9d .word 0x0800ee9d 800ee78: 0800eeb7 .word 0x0800eeb7 { /* Make sure that no pending write process */ case CTRL_SYNC : res = RES_OK; 800ee7c: 2300 movs r3, #0 800ee7e: f887 302f strb.w r3, [r7, #47] ; 0x2f break; 800ee82: e028 b.n 800eed6 /* Get number of sectors on the disk (DWORD) */ case GET_SECTOR_COUNT : BSP_SD_GetCardInfo(&CardInfo); 800ee84: f107 0308 add.w r3, r7, #8 800ee88: 4618 mov r0, r3 800ee8a: f7ff fe5d bl 800eb48 *(DWORD*)buff = CardInfo.LogBlockNbr; 800ee8e: 6a3a ldr r2, [r7, #32] 800ee90: 683b ldr r3, [r7, #0] 800ee92: 601a str r2, [r3, #0] res = RES_OK; 800ee94: 2300 movs r3, #0 800ee96: f887 302f strb.w r3, [r7, #47] ; 0x2f break; 800ee9a: e01c b.n 800eed6 /* Get R/W sector size (WORD) */ case GET_SECTOR_SIZE : BSP_SD_GetCardInfo(&CardInfo); 800ee9c: f107 0308 add.w r3, r7, #8 800eea0: 4618 mov r0, r3 800eea2: f7ff fe51 bl 800eb48 *(WORD*)buff = CardInfo.LogBlockSize; 800eea6: 6a7b ldr r3, [r7, #36] ; 0x24 800eea8: b29a uxth r2, r3 800eeaa: 683b ldr r3, [r7, #0] 800eeac: 801a strh r2, [r3, #0] res = RES_OK; 800eeae: 2300 movs r3, #0 800eeb0: f887 302f strb.w r3, [r7, #47] ; 0x2f break; 800eeb4: e00f b.n 800eed6 /* Get erase block size in unit of sector (DWORD) */ case GET_BLOCK_SIZE : BSP_SD_GetCardInfo(&CardInfo); 800eeb6: f107 0308 add.w r3, r7, #8 800eeba: 4618 mov r0, r3 800eebc: f7ff fe44 bl 800eb48 *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE; 800eec0: 6a7b ldr r3, [r7, #36] ; 0x24 800eec2: 0a5a lsrs r2, r3, #9 800eec4: 683b ldr r3, [r7, #0] 800eec6: 601a str r2, [r3, #0] res = RES_OK; 800eec8: 2300 movs r3, #0 800eeca: f887 302f strb.w r3, [r7, #47] ; 0x2f break; 800eece: e002 b.n 800eed6 default: res = RES_PARERR; 800eed0: 2304 movs r3, #4 800eed2: f887 302f strb.w r3, [r7, #47] ; 0x2f } return res; 800eed6: f897 302f ldrb.w r3, [r7, #47] ; 0x2f } 800eeda: 4618 mov r0, r3 800eedc: 3730 adds r7, #48 ; 0x30 800eede: 46bd mov sp, r7 800eee0: bd80 pop {r7, pc} 800eee2: bf00 nop 800eee4: 24000021 .word 0x24000021 0800eee8 : * @brief Tx Transfer completed callbacks * @param hsd: SD handle * @retval None */ void BSP_SD_WriteCpltCallback(void) { 800eee8: b580 push {r7, lr} 800eeea: af00 add r7, sp, #0 /* * No need to add an "osKernelRunning()" check here, as the SD_initialize() * is always called before any SD_Read()/SD_Write() call */ #if (osCMSIS < 0x20000U) osMessagePut(SDQueueID, WRITE_CPLT_MSG, 0); 800eeec: 4b04 ldr r3, [pc, #16] ; (800ef00 ) 800eeee: 681b ldr r3, [r3, #0] 800eef0: 2200 movs r2, #0 800eef2: 2102 movs r1, #2 800eef4: 4618 mov r0, r3 800eef6: f001 fbe5 bl 80106c4 #else const uint16_t msg = WRITE_CPLT_MSG; osMessageQueuePut(SDQueueID, (const void *)&msg, 0, 0); #endif } 800eefa: bf00 nop 800eefc: bd80 pop {r7, pc} 800eefe: bf00 nop 800ef00: 240073e0 .word 0x240073e0 0800ef04 : * @brief Rx Transfer completed callbacks * @param hsd: SD handle * @retval None */ void BSP_SD_ReadCpltCallback(void) { 800ef04: b580 push {r7, lr} 800ef06: af00 add r7, sp, #0 /* * No need to add an "osKernelRunning()" check here, as the SD_initialize() * is always called before any SD_Read()/SD_Write() call */ #if (osCMSIS < 0x20000U) osMessagePut(SDQueueID, READ_CPLT_MSG, 0); 800ef08: 4b04 ldr r3, [pc, #16] ; (800ef1c ) 800ef0a: 681b ldr r3, [r3, #0] 800ef0c: 2200 movs r2, #0 800ef0e: 2101 movs r1, #1 800ef10: 4618 mov r0, r3 800ef12: f001 fbd7 bl 80106c4 #else const uint16_t msg = READ_CPLT_MSG; osMessageQueuePut(SDQueueID, (const void *)&msg, 0, 0); #endif } 800ef16: bf00 nop 800ef18: bd80 pop {r7, pc} 800ef1a: bf00 nop 800ef1c: 240073e0 .word 0x240073e0 0800ef20 : #include "lwftpc.h" /** send the data to the connected connection */ err_t lwftp_send(struct netconn *conn, const char *data) { 800ef20: b580 push {r7, lr} 800ef22: b086 sub sp, #24 800ef24: af02 add r7, sp, #8 800ef26: 6078 str r0, [r7, #4] 800ef28: 6039 str r1, [r7, #0] err_t err = 0; 800ef2a: 2300 movs r3, #0 800ef2c: 73fb strb r3, [r7, #15] if (strcmp(data, "\r\n") == 0) 800ef2e: 4911 ldr r1, [pc, #68] ; (800ef74 ) 800ef30: 6838 ldr r0, [r7, #0] 800ef32: f7f1 f9ed bl 8000310 800ef36: 4603 mov r3, r0 800ef38: 2b00 cmp r3, #0 800ef3a: d103 bne.n 800ef44 printf(">> lwftp: ----> send \r\n"); 800ef3c: 480e ldr r0, [pc, #56] ; (800ef78 ) 800ef3e: f012 fd91 bl 8021a64 800ef42: e003 b.n 800ef4c else printf(">> lwftp: ----> send %s", data); 800ef44: 6839 ldr r1, [r7, #0] 800ef46: 480d ldr r0, [pc, #52] ; (800ef7c ) 800ef48: f012 fd1e bl 8021988 err = netconn_write(conn, data, strlen(data), NETCONN_COPY); 800ef4c: 6838 ldr r0, [r7, #0] 800ef4e: f7f1 f9e9 bl 8000324 800ef52: 4602 mov r2, r0 800ef54: 2300 movs r3, #0 800ef56: 9300 str r3, [sp, #0] 800ef58: 2301 movs r3, #1 800ef5a: 6839 ldr r1, [r7, #0] 800ef5c: 6878 ldr r0, [r7, #4] 800ef5e: f005 f89d bl 801409c 800ef62: 4603 mov r3, r0 800ef64: 73fb strb r3, [r7, #15] #if FTPSemaphore // relaese the semaphore sys_sem_signal(&ftpsem); #endif return err; 800ef66: f997 300f ldrsb.w r3, [r7, #15] } 800ef6a: 4618 mov r0, r3 800ef6c: 3710 adds r7, #16 800ef6e: 46bd mov sp, r7 800ef70: bd80 pop {r7, pc} 800ef72: bf00 nop 800ef74: 08022e94 .word 0x08022e94 800ef78: 08022e98 .word 0x08022e98 800ef7c: 08022eb8 .word 0x08022eb8 0800ef80 : err_t lwftp_data_open(lwftp_session_t *s, const char *response) { 800ef80: b580 push {r7, lr} 800ef82: b08a sub sp, #40 ; 0x28 800ef84: af00 add r7, sp, #0 800ef86: 6078 str r0, [r7, #4] 800ef88: 6039 str r1, [r7, #0] err_t err = ERR_VAL; 800ef8a: 23fa movs r3, #250 ; 0xfa 800ef8c: f887 3027 strb.w r3, [r7, #39] ; 0x27 char *ptr; ip_addr_t addr_d; ptr = strchr(response, '('); 800ef90: 2128 movs r1, #40 ; 0x28 800ef92: 6838 ldr r0, [r7, #0] 800ef94: f012 feac bl 8021cf0 800ef98: 4603 mov r3, r0 800ef9a: 613b str r3, [r7, #16] if (ptr) { 800ef9c: 693b ldr r3, [r7, #16] 800ef9e: 2b00 cmp r3, #0 800efa0: f000 80ae beq.w 800f100 unsigned int a = strtoul(ptr + 1, &ptr, 10); 800efa4: 693b ldr r3, [r7, #16] 800efa6: 3301 adds r3, #1 800efa8: f107 0110 add.w r1, r7, #16 800efac: 220a movs r2, #10 800efae: 4618 mov r0, r3 800efb0: f012 fc1e bl 80217f0 800efb4: 6238 str r0, [r7, #32] unsigned int b = strtoul(ptr + 1, &ptr, 10); 800efb6: 693b ldr r3, [r7, #16] 800efb8: 3301 adds r3, #1 800efba: f107 0110 add.w r1, r7, #16 800efbe: 220a movs r2, #10 800efc0: 4618 mov r0, r3 800efc2: f012 fc15 bl 80217f0 800efc6: 61f8 str r0, [r7, #28] unsigned int c = strtoul(ptr + 1, &ptr, 10); 800efc8: 693b ldr r3, [r7, #16] 800efca: 3301 adds r3, #1 800efcc: f107 0110 add.w r1, r7, #16 800efd0: 220a movs r2, #10 800efd2: 4618 mov r0, r3 800efd4: f012 fc0c bl 80217f0 800efd8: 61b8 str r0, [r7, #24] unsigned int d = strtoul(ptr + 1, &ptr, 10); 800efda: 693b ldr r3, [r7, #16] 800efdc: 3301 adds r3, #1 800efde: f107 0110 add.w r1, r7, #16 800efe2: 220a movs r2, #10 800efe4: 4618 mov r0, r3 800efe6: f012 fc03 bl 80217f0 800efea: 6178 str r0, [r7, #20] IP4_ADDR(&addr_d, a, b, c, d); 800efec: 6a3b ldr r3, [r7, #32] 800efee: 061a lsls r2, r3, #24 800eff0: 69fb ldr r3, [r7, #28] 800eff2: 041b lsls r3, r3, #16 800eff4: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800eff8: 431a orrs r2, r3 800effa: 69bb ldr r3, [r7, #24] 800effc: 021b lsls r3, r3, #8 800effe: b29b uxth r3, r3 800f000: 431a orrs r2, r3 800f002: 697b ldr r3, [r7, #20] 800f004: b2db uxtb r3, r3 800f006: 4313 orrs r3, r2 800f008: 061a lsls r2, r3, #24 800f00a: 6a3b ldr r3, [r7, #32] 800f00c: 0619 lsls r1, r3, #24 800f00e: 69fb ldr r3, [r7, #28] 800f010: 041b lsls r3, r3, #16 800f012: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800f016: 4319 orrs r1, r3 800f018: 69bb ldr r3, [r7, #24] 800f01a: 021b lsls r3, r3, #8 800f01c: b29b uxth r3, r3 800f01e: 4319 orrs r1, r3 800f020: 697b ldr r3, [r7, #20] 800f022: b2db uxtb r3, r3 800f024: 430b orrs r3, r1 800f026: 021b lsls r3, r3, #8 800f028: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800f02c: 431a orrs r2, r3 800f02e: 6a3b ldr r3, [r7, #32] 800f030: 0619 lsls r1, r3, #24 800f032: 69fb ldr r3, [r7, #28] 800f034: 041b lsls r3, r3, #16 800f036: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800f03a: 4319 orrs r1, r3 800f03c: 69bb ldr r3, [r7, #24] 800f03e: 021b lsls r3, r3, #8 800f040: b29b uxth r3, r3 800f042: 4319 orrs r1, r3 800f044: 697b ldr r3, [r7, #20] 800f046: b2db uxtb r3, r3 800f048: 430b orrs r3, r1 800f04a: 0a1b lsrs r3, r3, #8 800f04c: f403 437f and.w r3, r3, #65280 ; 0xff00 800f050: 431a orrs r2, r3 800f052: 6a3b ldr r3, [r7, #32] 800f054: 0619 lsls r1, r3, #24 800f056: 69fb ldr r3, [r7, #28] 800f058: 041b lsls r3, r3, #16 800f05a: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800f05e: 4319 orrs r1, r3 800f060: 69bb ldr r3, [r7, #24] 800f062: 021b lsls r3, r3, #8 800f064: b29b uxth r3, r3 800f066: 4319 orrs r1, r3 800f068: 697b ldr r3, [r7, #20] 800f06a: b2db uxtb r3, r3 800f06c: 430b orrs r3, r1 800f06e: 0e1b lsrs r3, r3, #24 800f070: 4313 orrs r3, r2 800f072: 60fb str r3, [r7, #12] s->data_port = strtoul(ptr + 1, &ptr, 10) << 8; 800f074: 693b ldr r3, [r7, #16] 800f076: 3301 adds r3, #1 800f078: f107 0110 add.w r1, r7, #16 800f07c: 220a movs r2, #10 800f07e: 4618 mov r0, r3 800f080: f012 fbb6 bl 80217f0 800f084: 4603 mov r3, r0 800f086: b29b uxth r3, r3 800f088: 021b lsls r3, r3, #8 800f08a: b29a uxth r2, r3 800f08c: 687b ldr r3, [r7, #4] 800f08e: 815a strh r2, [r3, #10] s->data_port |= strtoul(ptr + 1, &ptr, 10) & 255; 800f090: 693b ldr r3, [r7, #16] 800f092: 3301 adds r3, #1 800f094: f107 0110 add.w r1, r7, #16 800f098: 220a movs r2, #10 800f09a: 4618 mov r0, r3 800f09c: f012 fba8 bl 80217f0 800f0a0: 4603 mov r3, r0 800f0a2: b2d9 uxtb r1, r3 800f0a4: 687b ldr r3, [r7, #4] 800f0a6: 895a ldrh r2, [r3, #10] 800f0a8: b28b uxth r3, r1 800f0aa: 4313 orrs r3, r2 800f0ac: b29a uxth r2, r3 800f0ae: 687b ldr r3, [r7, #4] 800f0b0: 815a strh r2, [r3, #10] printf(">> lwftp: server data port: '%d'\r\n", s->data_port); 800f0b2: 687b ldr r3, [r7, #4] 800f0b4: 895b ldrh r3, [r3, #10] 800f0b6: 4619 mov r1, r3 800f0b8: 4816 ldr r0, [pc, #88] ; (800f114 ) 800f0ba: f012 fc65 bl 8021988 if (*ptr == ')') { 800f0be: 693b ldr r3, [r7, #16] 800f0c0: 781b ldrb r3, [r3, #0] 800f0c2: 2b29 cmp r3, #41 ; 0x29 800f0c4: d11f bne.n 800f106 s->data_conn = netconn_new(NETCONN_TCP); 800f0c6: 2200 movs r2, #0 800f0c8: 2100 movs r1, #0 800f0ca: 2010 movs r0, #16 800f0cc: f004 fcc6 bl 8013a5c 800f0d0: 4602 mov r2, r0 800f0d2: 687b ldr r3, [r7, #4] 800f0d4: 61da str r2, [r3, #28] if (s->data_conn != NULL) { 800f0d6: 687b ldr r3, [r7, #4] 800f0d8: 69db ldr r3, [r3, #28] 800f0da: 2b00 cmp r3, #0 800f0dc: d00c beq.n 800f0f8 err = netconn_connect(s->data_conn, &addr_d, s->data_port); 800f0de: 687b ldr r3, [r7, #4] 800f0e0: 69d8 ldr r0, [r3, #28] 800f0e2: 687b ldr r3, [r7, #4] 800f0e4: 895a ldrh r2, [r3, #10] 800f0e6: f107 030c add.w r3, r7, #12 800f0ea: 4619 mov r1, r3 800f0ec: f004 fda8 bl 8013c40 800f0f0: 4603 mov r3, r0 800f0f2: f887 3027 strb.w r3, [r7, #39] ; 0x27 800f0f6: e006 b.n 800f106 } else { err = ERR_MEM; 800f0f8: 23ff movs r3, #255 ; 0xff 800f0fa: f887 3027 strb.w r3, [r7, #39] ; 0x27 800f0fe: e002 b.n 800f106 } } } else { err = ERR_BUF; 800f100: 23fe movs r3, #254 ; 0xfe 800f102: f887 3027 strb.w r3, [r7, #39] ; 0x27 } return err; 800f106: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 } 800f10a: 4618 mov r0, r3 800f10c: 3728 adds r7, #40 ; 0x28 800f10e: 46bd mov sp, r7 800f110: bd80 pop {r7, pc} 800f112: bf00 nop 800f114: 08022ed0 .word 0x08022ed0 0800f118 : return err; } /* Get data from Server*/ err_t lwftp_retrieve(lwftp_session_t *s, const char *filename) { 800f118: b580 push {r7, lr} 800f11a: b0c4 sub sp, #272 ; 0x110 800f11c: af00 add r7, sp, #0 800f11e: f507 7388 add.w r3, r7, #272 ; 0x110 800f122: f5a3 7386 sub.w r3, r3, #268 ; 0x10c 800f126: 6018 str r0, [r3, #0] 800f128: f507 7388 add.w r3, r7, #272 ; 0x110 800f12c: f5a3 7388 sub.w r3, r3, #272 ; 0x110 800f130: 6019 str r1, [r3, #0] char cmd[256]; err_t err; snprintf(cmd, sizeof(cmd), "RETR %s\r\n", filename); 800f132: f507 7388 add.w r3, r7, #272 ; 0x110 800f136: f5a3 7388 sub.w r3, r3, #272 ; 0x110 800f13a: f107 000c add.w r0, r7, #12 800f13e: 681b ldr r3, [r3, #0] 800f140: 4a14 ldr r2, [pc, #80] ; (800f194 ) 800f142: f44f 7180 mov.w r1, #256 ; 0x100 800f146: f012 fc95 bl 8021a74 err = lwftp_send(s->conn, cmd); 800f14a: f507 7388 add.w r3, r7, #272 ; 0x110 800f14e: f5a3 7386 sub.w r3, r3, #268 ; 0x10c 800f152: 681b ldr r3, [r3, #0] 800f154: 699b ldr r3, [r3, #24] 800f156: f107 020c add.w r2, r7, #12 800f15a: 4611 mov r1, r2 800f15c: 4618 mov r0, r3 800f15e: f7ff fedf bl 800ef20 800f162: 4603 mov r3, r0 800f164: f887 310f strb.w r3, [r7, #271] ; 0x10f if (err == ERR_OK) { 800f168: f997 310f ldrsb.w r3, [r7, #271] ; 0x10f 800f16c: 2b00 cmp r3, #0 800f16e: d103 bne.n 800f178 printf(">> lwftp: command sent successfully\r\n"); 800f170: 4809 ldr r0, [pc, #36] ; (800f198 ) 800f172: f012 fc77 bl 8021a64 800f176: e005 b.n 800f184 } else { printf(">> lwftp: send command failed with code %d\r\n", err); 800f178: f997 310f ldrsb.w r3, [r7, #271] ; 0x10f 800f17c: 4619 mov r1, r3 800f17e: 4807 ldr r0, [pc, #28] ; (800f19c ) 800f180: f012 fc02 bl 8021988 } return err; 800f184: f997 310f ldrsb.w r3, [r7, #271] ; 0x10f } 800f188: 4618 mov r0, r3 800f18a: f507 7788 add.w r7, r7, #272 ; 0x110 800f18e: 46bd mov sp, r7 800f190: bd80 pop {r7, pc} 800f192: bf00 nop 800f194: 08022f80 .word 0x08022f80 800f198: 08022f8c .word 0x08022f8c 800f19c: 08022f50 .word 0x08022f50 0800f1a0 : return err; } void onDataReceived(void *data, size_t size) { 800f1a0: b580 push {r7, lr} 800f1a2: b082 sub sp, #8 800f1a4: af00 add r7, sp, #0 800f1a6: 6078 str r0, [r7, #4] 800f1a8: 6039 str r1, [r7, #0] osDelay(1000); 800f1aa: f44f 707a mov.w r0, #1000 ; 0x3e8 800f1ae: f001 f8e7 bl 8010380 printf("%s\r\n", (char*) data); 800f1b2: 6879 ldr r1, [r7, #4] 800f1b4: 4803 ldr r0, [pc, #12] ; (800f1c4 ) 800f1b6: f012 fbe7 bl 8021988 } 800f1ba: bf00 nop 800f1bc: 3708 adds r7, #8 800f1be: 46bd mov sp, r7 800f1c0: bd80 pop {r7, pc} 800f1c2: bf00 nop 800f1c4: 08022fbc .word 0x08022fbc 0800f1c8 : // } // } // } //} void lwftp_data_thread(void *arg) { 800f1c8: b580 push {r7, lr} 800f1ca: b086 sub sp, #24 800f1cc: af00 add r7, sp, #0 800f1ce: 6078 str r0, [r7, #4] lwftp_session_t *s = (lwftp_session_t*) arg; 800f1d0: 687b ldr r3, [r7, #4] 800f1d2: 617b str r3, [r7, #20] static struct netbuf *d_buf; while (1) { if (s->data_conn != NULL && s->data_state == LWFTP_CONNECTED) { 800f1d4: 697b ldr r3, [r7, #20] 800f1d6: 69db ldr r3, [r3, #28] 800f1d8: 2b00 cmp r3, #0 800f1da: d030 beq.n 800f23e 800f1dc: 697b ldr r3, [r7, #20] 800f1de: 7d5b ldrb r3, [r3, #21] 800f1e0: 2b01 cmp r3, #1 800f1e2: d12c bne.n 800f23e err_t err = netconn_recv(s->data_conn, &d_buf); 800f1e4: 697b ldr r3, [r7, #20] 800f1e6: 69db ldr r3, [r3, #28] 800f1e8: 4918 ldr r1, [pc, #96] ; (800f24c ) 800f1ea: 4618 mov r0, r3 800f1ec: f004 fedc bl 8013fa8 800f1f0: 4603 mov r3, r0 800f1f2: 74fb strb r3, [r7, #19] if (err == ERR_OK && d_buf != NULL) { 800f1f4: f997 3013 ldrsb.w r3, [r7, #19] 800f1f8: 2b00 cmp r3, #0 800f1fa: d124 bne.n 800f246 800f1fc: 4b13 ldr r3, [pc, #76] ; (800f24c ) 800f1fe: 681b ldr r3, [r3, #0] 800f200: 2b00 cmp r3, #0 800f202: d020 beq.n 800f246 void *data; u16_t len; do { netbuf_data(d_buf, &data, &len); 800f204: 4b11 ldr r3, [pc, #68] ; (800f24c ) 800f206: 681b ldr r3, [r3, #0] 800f208: f107 020a add.w r2, r7, #10 800f20c: f107 010c add.w r1, r7, #12 800f210: 4618 mov r0, r3 800f212: f006 fc63 bl 8015adc onDataReceived(data, len); 800f216: 68fb ldr r3, [r7, #12] 800f218: 897a ldrh r2, [r7, #10] 800f21a: 4611 mov r1, r2 800f21c: 4618 mov r0, r3 800f21e: f7ff ffbf bl 800f1a0 } while (netbuf_next(d_buf) >= 0); 800f222: 4b0a ldr r3, [pc, #40] ; (800f24c ) 800f224: 681b ldr r3, [r3, #0] 800f226: 4618 mov r0, r3 800f228: f006 fca2 bl 8015b70 800f22c: 4603 mov r3, r0 800f22e: 2b00 cmp r3, #0 800f230: dae8 bge.n 800f204 netbuf_delete(d_buf); 800f232: 4b06 ldr r3, [pc, #24] ; (800f24c ) 800f234: 681b ldr r3, [r3, #0] 800f236: 4618 mov r0, r3 800f238: f006 fc30 bl 8015a9c if (s->data_conn != NULL && s->data_state == LWFTP_CONNECTED) { 800f23c: e003 b.n 800f246 } else { } } else { vTaskDelay(pdMS_TO_TICKS(100)); 800f23e: 2064 movs r0, #100 ; 0x64 800f240: f002 fd96 bl 8011d70 800f244: e7c6 b.n 800f1d4 if (s->data_conn != NULL && s->data_state == LWFTP_CONNECTED) { 800f246: bf00 nop 800f248: e7c4 b.n 800f1d4 800f24a: bf00 nop 800f24c: 240073e4 .word 0x240073e4 0800f250 : } } } void lwftp_ctrl_thread(void *arg) { 800f250: b580 push {r7, lr} 800f252: b0c6 sub sp, #280 ; 0x118 800f254: af00 add r7, sp, #0 800f256: f507 738c add.w r3, r7, #280 ; 0x118 800f25a: f5a3 738a sub.w r3, r3, #276 ; 0x114 800f25e: 6018 str r0, [r3, #0] lwftp_session_t *s = (lwftp_session_t*) arg; 800f260: f507 738c add.w r3, r7, #280 ; 0x118 800f264: f5a3 738a sub.w r3, r3, #276 ; 0x114 800f268: 681b ldr r3, [r3, #0] 800f26a: f8c7 3114 str.w r3, [r7, #276] ; 0x114 static struct netbuf *buf; uint response = 0; 800f26e: 2300 movs r3, #0 800f270: f8c7 3110 str.w r3, [r7, #272] ; 0x110 char cmd[256]; err_t err; // check session data invalid if ((s->control_state != LWFTP_CLOSED) || s->conn || s->data_conn || !s->user 800f274: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f278: 7d1b ldrb r3, [r3, #20] 800f27a: 2b00 cmp r3, #0 800f27c: d113 bne.n 800f2a6 800f27e: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f282: 699b ldr r3, [r3, #24] 800f284: 2b00 cmp r3, #0 800f286: d10e bne.n 800f2a6 800f288: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f28c: 69db ldr r3, [r3, #28] 800f28e: 2b00 cmp r3, #0 800f290: d109 bne.n 800f2a6 800f292: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f296: 68db ldr r3, [r3, #12] 800f298: 2b00 cmp r3, #0 800f29a: d004 beq.n 800f2a6 || !s->pass) { 800f29c: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f2a0: 691b ldr r3, [r3, #16] 800f2a2: 2b00 cmp r3, #0 800f2a4: d103 bne.n 800f2ae printf(">> lwftp: invalid session data\r\n"); 800f2a6: 4894 ldr r0, [pc, #592] ; (800f4f8 ) 800f2a8: f012 fbdc bl 8021a64 800f2ac: e120 b.n 800f4f0 return; } s->conn = netconn_new(NETCONN_TCP); 800f2ae: 2200 movs r2, #0 800f2b0: 2100 movs r1, #0 800f2b2: 2010 movs r0, #16 800f2b4: f004 fbd2 bl 8013a5c 800f2b8: 4602 mov r2, r0 800f2ba: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f2be: 619a str r2, [r3, #24] s->data_conn = netconn_new(NETCONN_TCP); 800f2c0: 2200 movs r2, #0 800f2c2: 2100 movs r1, #0 800f2c4: 2010 movs r0, #16 800f2c6: f004 fbc9 bl 8013a5c 800f2ca: 4602 mov r2, r0 800f2cc: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f2d0: 61da str r2, [r3, #28] // create a new connection identifier if (s->conn != NULL) { 800f2d2: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f2d6: 699b ldr r3, [r3, #24] 800f2d8: 2b00 cmp r3, #0 800f2da: f000 80e8 beq.w 800f4ae err = netconn_bind(s->conn, &s->cli_ip, 0); 800f2de: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f2e2: 699b ldr r3, [r3, #24] 800f2e4: f8d7 1114 ldr.w r1, [r7, #276] ; 0x114 800f2e8: 2200 movs r2, #0 800f2ea: 4618 mov r0, r3 800f2ec: f004 fc70 bl 8013bd0 800f2f0: 4603 mov r3, r0 800f2f2: f887 310f strb.w r3, [r7, #271] ; 0x10f if (err == ERR_OK) { 800f2f6: f997 310f ldrsb.w r3, [r7, #271] ; 0x10f 800f2fa: 2b00 cmp r3, #0 800f2fc: f040 80d0 bne.w 800f4a0 printf(">> lwftp: client IP bind OK\r\n"); 800f300: 487e ldr r0, [pc, #504] ; (800f4fc ) 800f302: f012 fbaf bl 8021a64 err = netconn_connect(s->conn, &s->svr_ip, s->svr_port); 800f306: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f30a: 6998 ldr r0, [r3, #24] 800f30c: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f310: 1d19 adds r1, r3, #4 800f312: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f316: 891b ldrh r3, [r3, #8] 800f318: 461a mov r2, r3 800f31a: f004 fc91 bl 8013c40 800f31e: 4603 mov r3, r0 800f320: f887 310f strb.w r3, [r7, #271] ; 0x10f // If the connection to the server is established, the following will continue, else delete the connection if (err == ERR_OK) { 800f324: f997 310f ldrsb.w r3, [r7, #271] ; 0x10f 800f328: 2b00 cmp r3, #0 800f32a: f040 80b2 bne.w 800f492 printf(">> lwftp: server connect OK\r\n"); 800f32e: 4874 ldr r0, [pc, #464] ; (800f500 ) 800f330: f012 fb98 bl 8021a64 * Response processing * ===================== */ while (1) { /* wait until the data is sent by the server*/ if (netconn_recv(s->conn, &buf) == ERR_OK) { 800f334: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f338: 699b ldr r3, [r3, #24] 800f33a: 4972 ldr r1, [pc, #456] ; (800f504 ) 800f33c: 4618 mov r0, r3 800f33e: f004 fe33 bl 8013fa8 800f342: 4603 mov r3, r0 800f344: 2b00 cmp r3, #0 800f346: f040 808e bne.w 800f466 if (buf) { 800f34a: 4b6e ldr r3, [pc, #440] ; (800f504 ) 800f34c: 681b ldr r3, [r3, #0] 800f34e: 2b00 cmp r3, #0 800f350: f000 8089 beq.w 800f466 response = strtoul(buf->p->payload, NULL, 10); 800f354: 4b6b ldr r3, [pc, #428] ; (800f504 ) 800f356: 681b ldr r3, [r3, #0] 800f358: 681b ldr r3, [r3, #0] 800f35a: 685b ldr r3, [r3, #4] 800f35c: 220a movs r2, #10 800f35e: 2100 movs r1, #0 800f360: 4618 mov r0, r3 800f362: f012 fa45 bl 80217f0 800f366: f8c7 0110 str.w r0, [r7, #272] ; 0x110 printf("\n>> lwftp: <==== resp '%d'\r\n", response); 800f36a: f8d7 1110 ldr.w r1, [r7, #272] ; 0x110 800f36e: 4866 ldr r0, [pc, #408] ; (800f508 ) 800f370: f012 fb0a bl 8021988 /** [Response 220] Service ready for new user.*/ if (response == 220) { 800f374: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 800f378: 2bdc cmp r3, #220 ; 0xdc 800f37a: d113 bne.n 800f3a4 snprintf(cmd, sizeof(cmd), "USER %s\r\n", s->user); 800f37c: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f380: 68db ldr r3, [r3, #12] 800f382: f107 000c add.w r0, r7, #12 800f386: 4a61 ldr r2, [pc, #388] ; (800f50c ) 800f388: f44f 7180 mov.w r1, #256 ; 0x100 800f38c: f012 fb72 bl 8021a74 lwftp_send(s->conn, cmd); 800f390: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f394: 699b ldr r3, [r3, #24] 800f396: f107 020c add.w r2, r7, #12 800f39a: 4611 mov r1, r2 800f39c: 4618 mov r0, r3 800f39e: f7ff fdbf bl 800ef20 800f3a2: e060 b.n 800f466 } /** [Response 331] User name okay, need password.*/ else if (response == 331) { 800f3a4: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 800f3a8: f240 124b movw r2, #331 ; 0x14b 800f3ac: 4293 cmp r3, r2 800f3ae: d113 bne.n 800f3d8 snprintf(cmd, sizeof(cmd), "PASS %s\r\n", s->pass); 800f3b0: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f3b4: 691b ldr r3, [r3, #16] 800f3b6: f107 000c add.w r0, r7, #12 800f3ba: 4a55 ldr r2, [pc, #340] ; (800f510 ) 800f3bc: f44f 7180 mov.w r1, #256 ; 0x100 800f3c0: f012 fb58 bl 8021a74 lwftp_send(s->conn, cmd); 800f3c4: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f3c8: 699b ldr r3, [r3, #24] 800f3ca: f107 020c add.w r2, r7, #12 800f3ce: 4611 mov r1, r2 800f3d0: 4618 mov r0, r3 800f3d2: f7ff fda5 bl 800ef20 800f3d6: e046 b.n 800f466 } /** [Response 230] User logged in, proceed.*/ else if (response == 230) { 800f3d8: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 800f3dc: 2be6 cmp r3, #230 ; 0xe6 800f3de: d10a bne.n 800f3f6 printf(">> lwftp: now logged in\r\n"); 800f3e0: 484c ldr r0, [pc, #304] ; (800f514 ) 800f3e2: f012 fb3f bl 8021a64 lwftp_send(s->conn, "PASV\r\n"); 800f3e6: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f3ea: 699b ldr r3, [r3, #24] 800f3ec: 494a ldr r1, [pc, #296] ; (800f518 ) 800f3ee: 4618 mov r0, r3 800f3f0: f7ff fd96 bl 800ef20 800f3f4: e037 b.n 800f466 } /** [Response 227] Entering Passive Mode (h1,h2,h3,h4,p1,p2).*/ else if (response == 227) { 800f3f6: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 800f3fa: 2be3 cmp r3, #227 ; 0xe3 800f3fc: d121 bne.n 800f442 printf(">> lwftp: entering passive Mode\r\n"); 800f3fe: 4847 ldr r0, [pc, #284] ; (800f51c ) 800f400: f012 fb30 bl 8021a64 err = lwftp_data_open(s, buf->p->payload); 800f404: 4b3f ldr r3, [pc, #252] ; (800f504 ) 800f406: 681b ldr r3, [r3, #0] 800f408: 681b ldr r3, [r3, #0] 800f40a: 685b ldr r3, [r3, #4] 800f40c: 4619 mov r1, r3 800f40e: f8d7 0114 ldr.w r0, [r7, #276] ; 0x114 800f412: f7ff fdb5 bl 800ef80 800f416: 4603 mov r3, r0 800f418: f887 310f strb.w r3, [r7, #271] ; 0x10f if (err != ERR_OK) { 800f41c: f997 310f ldrsb.w r3, [r7, #271] ; 0x10f 800f420: 2b00 cmp r3, #0 800f422: d006 beq.n 800f432 printf(">> lwftp: data port connection failed with code %d\r\n",err); 800f424: f997 310f ldrsb.w r3, [r7, #271] ; 0x10f 800f428: 4619 mov r1, r3 800f42a: 483d ldr r0, [pc, #244] ; (800f520 ) 800f42c: f012 faac bl 8021988 goto exit; 800f430: e03e b.n 800f4b0 } s->data_state = LWFTP_CONNECTED; 800f432: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f436: 2201 movs r2, #1 800f438: 755a strb r2, [r3, #21] printf(">> lwftp: data port connect OK\r\n"); 800f43a: 483a ldr r0, [pc, #232] ; (800f524 ) 800f43c: f012 fb12 bl 8021a64 800f440: e011 b.n 800f466 } /** [Response 125] Data connection already open; transfer starting.*/ else if (response == 125) { 800f442: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 800f446: 2b7d cmp r3, #125 ; 0x7d 800f448: d103 bne.n 800f452 printf(">> lwftp: transfer starting.\r\n"); 800f44a: 4837 ldr r0, [pc, #220] ; (800f528 ) 800f44c: f012 fb0a bl 8021a64 800f450: e009 b.n 800f466 } /** [Response 226] Closing data connection. Requested file action successful*/ else if (response == 226) { 800f452: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 800f456: 2be2 cmp r3, #226 ; 0xe2 800f458: d105 bne.n 800f466 printf(">> lwftp: closing data connection.\r\n"); 800f45a: 4834 ldr r0, [pc, #208] ; (800f52c ) 800f45c: f012 fb02 bl 8021a64 printf(">> lwftp: requested file action successful.\r\n"); 800f460: 4833 ldr r0, [pc, #204] ; (800f530 ) 800f462: f012 faff bl 8021a64 } } } memset(cmd, 0, sizeof(cmd)); 800f466: f107 030c add.w r3, r7, #12 800f46a: f44f 7280 mov.w r2, #256 ; 0x100 800f46e: 2100 movs r1, #0 800f470: 4618 mov r0, r3 800f472: f012 fc35 bl 8021ce0 if (buf != NULL) { 800f476: 4b23 ldr r3, [pc, #140] ; (800f504 ) 800f478: 681b ldr r3, [r3, #0] 800f47a: 2b00 cmp r3, #0 800f47c: f43f af5a beq.w 800f334 netbuf_delete(buf); 800f480: 4b20 ldr r3, [pc, #128] ; (800f504 ) 800f482: 681b ldr r3, [r3, #0] 800f484: 4618 mov r0, r3 800f486: f006 fb09 bl 8015a9c buf = NULL; 800f48a: 4b1e ldr r3, [pc, #120] ; (800f504 ) 800f48c: 2200 movs r2, #0 800f48e: 601a str r2, [r3, #0] if (netconn_recv(s->conn, &buf) == ERR_OK) { 800f490: e750 b.n 800f334 } } } else { printf(">> lwftp: server connection failed with code %d\r\n", err); 800f492: f997 310f ldrsb.w r3, [r7, #271] ; 0x10f 800f496: 4619 mov r1, r3 800f498: 4826 ldr r0, [pc, #152] ; (800f534 ) 800f49a: f012 fa75 bl 8021988 goto exit; 800f49e: e007 b.n 800f4b0 } } else { printf(">> lwftp: client IP binding failed with code %d\r\n", err); 800f4a0: f997 310f ldrsb.w r3, [r7, #271] ; 0x10f 800f4a4: 4619 mov r1, r3 800f4a6: 4824 ldr r0, [pc, #144] ; (800f538 ) 800f4a8: f012 fa6e bl 8021988 goto exit; 800f4ac: e000 b.n 800f4b0 } } exit: if (s->data_conn) { 800f4ae: bf00 nop 800f4b0: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f4b4: 69db ldr r3, [r3, #28] 800f4b6: 2b00 cmp r3, #0 800f4b8: d00b beq.n 800f4d2 netconn_close(s->data_conn); 800f4ba: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f4be: 69db ldr r3, [r3, #28] 800f4c0: 4618 mov r0, r3 800f4c2: f004 feed bl 80142a0 netconn_delete(s->data_conn); 800f4c6: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f4ca: 69db ldr r3, [r3, #28] 800f4cc: 4618 mov r0, r3 800f4ce: f004 fb63 bl 8013b98 } netconn_close(s->conn); 800f4d2: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f4d6: 699b ldr r3, [r3, #24] 800f4d8: 4618 mov r0, r3 800f4da: f004 fee1 bl 80142a0 netconn_delete(s->conn); 800f4de: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114 800f4e2: 699b ldr r3, [r3, #24] 800f4e4: 4618 mov r0, r3 800f4e6: f004 fb57 bl 8013b98 printf(">> lwftp: all ftp connection closed\r\n"); 800f4ea: 4814 ldr r0, [pc, #80] ; (800f53c ) 800f4ec: f012 faba bl 8021a64 } 800f4f0: f507 778c add.w r7, r7, #280 ; 0x118 800f4f4: 46bd mov sp, r7 800f4f6: bd80 pop {r7, pc} 800f4f8: 08022fc4 .word 0x08022fc4 800f4fc: 08022fe4 .word 0x08022fe4 800f500: 08023004 .word 0x08023004 800f504: 240073e8 .word 0x240073e8 800f508: 08023024 .word 0x08023024 800f50c: 08023044 .word 0x08023044 800f510: 08023050 .word 0x08023050 800f514: 0802305c .word 0x0802305c 800f518: 08023078 .word 0x08023078 800f51c: 08023080 .word 0x08023080 800f520: 080230a4 .word 0x080230a4 800f524: 080230dc .word 0x080230dc 800f528: 080230fc .word 0x080230fc 800f52c: 0802311c .word 0x0802311c 800f530: 08023140 .word 0x08023140 800f534: 08023170 .word 0x08023170 800f538: 080231a4 .word 0x080231a4 800f53c: 080231d8 .word 0x080231d8 0800f540 : /** * LwIP initialization function */ void MX_LWIP_Init(void) { 800f540: b5b0 push {r4, r5, r7, lr} 800f542: b08c sub sp, #48 ; 0x30 800f544: af04 add r7, sp, #16 /* IP addresses initialization */ IP_ADDRESS[0] = 192; 800f546: 4b8f ldr r3, [pc, #572] ; (800f784 ) 800f548: 22c0 movs r2, #192 ; 0xc0 800f54a: 701a strb r2, [r3, #0] IP_ADDRESS[1] = 168; 800f54c: 4b8d ldr r3, [pc, #564] ; (800f784 ) 800f54e: 22a8 movs r2, #168 ; 0xa8 800f550: 705a strb r2, [r3, #1] IP_ADDRESS[2] = 0; 800f552: 4b8c ldr r3, [pc, #560] ; (800f784 ) 800f554: 2200 movs r2, #0 800f556: 709a strb r2, [r3, #2] IP_ADDRESS[3] = 120; 800f558: 4b8a ldr r3, [pc, #552] ; (800f784 ) 800f55a: 2278 movs r2, #120 ; 0x78 800f55c: 70da strb r2, [r3, #3] NETMASK_ADDRESS[0] = 255; 800f55e: 4b8a ldr r3, [pc, #552] ; (800f788 ) 800f560: 22ff movs r2, #255 ; 0xff 800f562: 701a strb r2, [r3, #0] NETMASK_ADDRESS[1] = 255; 800f564: 4b88 ldr r3, [pc, #544] ; (800f788 ) 800f566: 22ff movs r2, #255 ; 0xff 800f568: 705a strb r2, [r3, #1] NETMASK_ADDRESS[2] = 255; 800f56a: 4b87 ldr r3, [pc, #540] ; (800f788 ) 800f56c: 22ff movs r2, #255 ; 0xff 800f56e: 709a strb r2, [r3, #2] NETMASK_ADDRESS[3] = 0; 800f570: 4b85 ldr r3, [pc, #532] ; (800f788 ) 800f572: 2200 movs r2, #0 800f574: 70da strb r2, [r3, #3] GATEWAY_ADDRESS[0] = 0; 800f576: 4b85 ldr r3, [pc, #532] ; (800f78c ) 800f578: 2200 movs r2, #0 800f57a: 701a strb r2, [r3, #0] GATEWAY_ADDRESS[1] = 0; 800f57c: 4b83 ldr r3, [pc, #524] ; (800f78c ) 800f57e: 2200 movs r2, #0 800f580: 705a strb r2, [r3, #1] GATEWAY_ADDRESS[2] = 0; 800f582: 4b82 ldr r3, [pc, #520] ; (800f78c ) 800f584: 2200 movs r2, #0 800f586: 709a strb r2, [r3, #2] GATEWAY_ADDRESS[3] = 0; 800f588: 4b80 ldr r3, [pc, #512] ; (800f78c ) 800f58a: 2200 movs r2, #0 800f58c: 70da strb r2, [r3, #3] /* USER CODE BEGIN IP_ADDRESSES */ /* USER CODE END IP_ADDRESSES */ /* Initilialize the LwIP stack with RTOS */ tcpip_init( NULL, NULL ); 800f58e: 2100 movs r1, #0 800f590: 2000 movs r0, #0 800f592: f006 fc8b bl 8015eac /* IP addresses initialization without DHCP (IPv4) */ IP4_ADDR(&ipaddr, IP_ADDRESS[0], IP_ADDRESS[1], IP_ADDRESS[2], IP_ADDRESS[3]); 800f596: 4b7b ldr r3, [pc, #492] ; (800f784 ) 800f598: 781b ldrb r3, [r3, #0] 800f59a: 061a lsls r2, r3, #24 800f59c: 4b79 ldr r3, [pc, #484] ; (800f784 ) 800f59e: 785b ldrb r3, [r3, #1] 800f5a0: 041b lsls r3, r3, #16 800f5a2: 431a orrs r2, r3 800f5a4: 4b77 ldr r3, [pc, #476] ; (800f784 ) 800f5a6: 789b ldrb r3, [r3, #2] 800f5a8: 021b lsls r3, r3, #8 800f5aa: 4313 orrs r3, r2 800f5ac: 4a75 ldr r2, [pc, #468] ; (800f784 ) 800f5ae: 78d2 ldrb r2, [r2, #3] 800f5b0: 4313 orrs r3, r2 800f5b2: 061a lsls r2, r3, #24 800f5b4: 4b73 ldr r3, [pc, #460] ; (800f784 ) 800f5b6: 781b ldrb r3, [r3, #0] 800f5b8: 0619 lsls r1, r3, #24 800f5ba: 4b72 ldr r3, [pc, #456] ; (800f784 ) 800f5bc: 785b ldrb r3, [r3, #1] 800f5be: 041b lsls r3, r3, #16 800f5c0: 4319 orrs r1, r3 800f5c2: 4b70 ldr r3, [pc, #448] ; (800f784 ) 800f5c4: 789b ldrb r3, [r3, #2] 800f5c6: 021b lsls r3, r3, #8 800f5c8: 430b orrs r3, r1 800f5ca: 496e ldr r1, [pc, #440] ; (800f784 ) 800f5cc: 78c9 ldrb r1, [r1, #3] 800f5ce: 430b orrs r3, r1 800f5d0: 021b lsls r3, r3, #8 800f5d2: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800f5d6: 431a orrs r2, r3 800f5d8: 4b6a ldr r3, [pc, #424] ; (800f784 ) 800f5da: 781b ldrb r3, [r3, #0] 800f5dc: 0619 lsls r1, r3, #24 800f5de: 4b69 ldr r3, [pc, #420] ; (800f784 ) 800f5e0: 785b ldrb r3, [r3, #1] 800f5e2: 041b lsls r3, r3, #16 800f5e4: 4319 orrs r1, r3 800f5e6: 4b67 ldr r3, [pc, #412] ; (800f784 ) 800f5e8: 789b ldrb r3, [r3, #2] 800f5ea: 021b lsls r3, r3, #8 800f5ec: 430b orrs r3, r1 800f5ee: 4965 ldr r1, [pc, #404] ; (800f784 ) 800f5f0: 78c9 ldrb r1, [r1, #3] 800f5f2: 430b orrs r3, r1 800f5f4: 0a1b lsrs r3, r3, #8 800f5f6: f403 437f and.w r3, r3, #65280 ; 0xff00 800f5fa: 431a orrs r2, r3 800f5fc: 4b61 ldr r3, [pc, #388] ; (800f784 ) 800f5fe: 781b ldrb r3, [r3, #0] 800f600: 0619 lsls r1, r3, #24 800f602: 4b60 ldr r3, [pc, #384] ; (800f784 ) 800f604: 785b ldrb r3, [r3, #1] 800f606: 041b lsls r3, r3, #16 800f608: 4319 orrs r1, r3 800f60a: 4b5e ldr r3, [pc, #376] ; (800f784 ) 800f60c: 789b ldrb r3, [r3, #2] 800f60e: 021b lsls r3, r3, #8 800f610: 430b orrs r3, r1 800f612: 495c ldr r1, [pc, #368] ; (800f784 ) 800f614: 78c9 ldrb r1, [r1, #3] 800f616: 430b orrs r3, r1 800f618: 0e1b lsrs r3, r3, #24 800f61a: 4313 orrs r3, r2 800f61c: 4a5c ldr r2, [pc, #368] ; (800f790 ) 800f61e: 6013 str r3, [r2, #0] IP4_ADDR(&netmask, NETMASK_ADDRESS[0], NETMASK_ADDRESS[1] , NETMASK_ADDRESS[2], NETMASK_ADDRESS[3]); 800f620: 4b59 ldr r3, [pc, #356] ; (800f788 ) 800f622: 781b ldrb r3, [r3, #0] 800f624: 061a lsls r2, r3, #24 800f626: 4b58 ldr r3, [pc, #352] ; (800f788 ) 800f628: 785b ldrb r3, [r3, #1] 800f62a: 041b lsls r3, r3, #16 800f62c: 431a orrs r2, r3 800f62e: 4b56 ldr r3, [pc, #344] ; (800f788 ) 800f630: 789b ldrb r3, [r3, #2] 800f632: 021b lsls r3, r3, #8 800f634: 4313 orrs r3, r2 800f636: 4a54 ldr r2, [pc, #336] ; (800f788 ) 800f638: 78d2 ldrb r2, [r2, #3] 800f63a: 4313 orrs r3, r2 800f63c: 061a lsls r2, r3, #24 800f63e: 4b52 ldr r3, [pc, #328] ; (800f788 ) 800f640: 781b ldrb r3, [r3, #0] 800f642: 0619 lsls r1, r3, #24 800f644: 4b50 ldr r3, [pc, #320] ; (800f788 ) 800f646: 785b ldrb r3, [r3, #1] 800f648: 041b lsls r3, r3, #16 800f64a: 4319 orrs r1, r3 800f64c: 4b4e ldr r3, [pc, #312] ; (800f788 ) 800f64e: 789b ldrb r3, [r3, #2] 800f650: 021b lsls r3, r3, #8 800f652: 430b orrs r3, r1 800f654: 494c ldr r1, [pc, #304] ; (800f788 ) 800f656: 78c9 ldrb r1, [r1, #3] 800f658: 430b orrs r3, r1 800f65a: 021b lsls r3, r3, #8 800f65c: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800f660: 431a orrs r2, r3 800f662: 4b49 ldr r3, [pc, #292] ; (800f788 ) 800f664: 781b ldrb r3, [r3, #0] 800f666: 0619 lsls r1, r3, #24 800f668: 4b47 ldr r3, [pc, #284] ; (800f788 ) 800f66a: 785b ldrb r3, [r3, #1] 800f66c: 041b lsls r3, r3, #16 800f66e: 4319 orrs r1, r3 800f670: 4b45 ldr r3, [pc, #276] ; (800f788 ) 800f672: 789b ldrb r3, [r3, #2] 800f674: 021b lsls r3, r3, #8 800f676: 430b orrs r3, r1 800f678: 4943 ldr r1, [pc, #268] ; (800f788 ) 800f67a: 78c9 ldrb r1, [r1, #3] 800f67c: 430b orrs r3, r1 800f67e: 0a1b lsrs r3, r3, #8 800f680: f403 437f and.w r3, r3, #65280 ; 0xff00 800f684: 431a orrs r2, r3 800f686: 4b40 ldr r3, [pc, #256] ; (800f788 ) 800f688: 781b ldrb r3, [r3, #0] 800f68a: 0619 lsls r1, r3, #24 800f68c: 4b3e ldr r3, [pc, #248] ; (800f788 ) 800f68e: 785b ldrb r3, [r3, #1] 800f690: 041b lsls r3, r3, #16 800f692: 4319 orrs r1, r3 800f694: 4b3c ldr r3, [pc, #240] ; (800f788 ) 800f696: 789b ldrb r3, [r3, #2] 800f698: 021b lsls r3, r3, #8 800f69a: 430b orrs r3, r1 800f69c: 493a ldr r1, [pc, #232] ; (800f788 ) 800f69e: 78c9 ldrb r1, [r1, #3] 800f6a0: 430b orrs r3, r1 800f6a2: 0e1b lsrs r3, r3, #24 800f6a4: 4313 orrs r3, r2 800f6a6: 4a3b ldr r2, [pc, #236] ; (800f794 ) 800f6a8: 6013 str r3, [r2, #0] IP4_ADDR(&gw, GATEWAY_ADDRESS[0], GATEWAY_ADDRESS[1], GATEWAY_ADDRESS[2], GATEWAY_ADDRESS[3]); 800f6aa: 4b38 ldr r3, [pc, #224] ; (800f78c ) 800f6ac: 781b ldrb r3, [r3, #0] 800f6ae: 061a lsls r2, r3, #24 800f6b0: 4b36 ldr r3, [pc, #216] ; (800f78c ) 800f6b2: 785b ldrb r3, [r3, #1] 800f6b4: 041b lsls r3, r3, #16 800f6b6: 431a orrs r2, r3 800f6b8: 4b34 ldr r3, [pc, #208] ; (800f78c ) 800f6ba: 789b ldrb r3, [r3, #2] 800f6bc: 021b lsls r3, r3, #8 800f6be: 4313 orrs r3, r2 800f6c0: 4a32 ldr r2, [pc, #200] ; (800f78c ) 800f6c2: 78d2 ldrb r2, [r2, #3] 800f6c4: 4313 orrs r3, r2 800f6c6: 061a lsls r2, r3, #24 800f6c8: 4b30 ldr r3, [pc, #192] ; (800f78c ) 800f6ca: 781b ldrb r3, [r3, #0] 800f6cc: 0619 lsls r1, r3, #24 800f6ce: 4b2f ldr r3, [pc, #188] ; (800f78c ) 800f6d0: 785b ldrb r3, [r3, #1] 800f6d2: 041b lsls r3, r3, #16 800f6d4: 4319 orrs r1, r3 800f6d6: 4b2d ldr r3, [pc, #180] ; (800f78c ) 800f6d8: 789b ldrb r3, [r3, #2] 800f6da: 021b lsls r3, r3, #8 800f6dc: 430b orrs r3, r1 800f6de: 492b ldr r1, [pc, #172] ; (800f78c ) 800f6e0: 78c9 ldrb r1, [r1, #3] 800f6e2: 430b orrs r3, r1 800f6e4: 021b lsls r3, r3, #8 800f6e6: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800f6ea: 431a orrs r2, r3 800f6ec: 4b27 ldr r3, [pc, #156] ; (800f78c ) 800f6ee: 781b ldrb r3, [r3, #0] 800f6f0: 0619 lsls r1, r3, #24 800f6f2: 4b26 ldr r3, [pc, #152] ; (800f78c ) 800f6f4: 785b ldrb r3, [r3, #1] 800f6f6: 041b lsls r3, r3, #16 800f6f8: 4319 orrs r1, r3 800f6fa: 4b24 ldr r3, [pc, #144] ; (800f78c ) 800f6fc: 789b ldrb r3, [r3, #2] 800f6fe: 021b lsls r3, r3, #8 800f700: 430b orrs r3, r1 800f702: 4922 ldr r1, [pc, #136] ; (800f78c ) 800f704: 78c9 ldrb r1, [r1, #3] 800f706: 430b orrs r3, r1 800f708: 0a1b lsrs r3, r3, #8 800f70a: f403 437f and.w r3, r3, #65280 ; 0xff00 800f70e: 431a orrs r2, r3 800f710: 4b1e ldr r3, [pc, #120] ; (800f78c ) 800f712: 781b ldrb r3, [r3, #0] 800f714: 0619 lsls r1, r3, #24 800f716: 4b1d ldr r3, [pc, #116] ; (800f78c ) 800f718: 785b ldrb r3, [r3, #1] 800f71a: 041b lsls r3, r3, #16 800f71c: 4319 orrs r1, r3 800f71e: 4b1b ldr r3, [pc, #108] ; (800f78c ) 800f720: 789b ldrb r3, [r3, #2] 800f722: 021b lsls r3, r3, #8 800f724: 430b orrs r3, r1 800f726: 4919 ldr r1, [pc, #100] ; (800f78c ) 800f728: 78c9 ldrb r1, [r1, #3] 800f72a: 430b orrs r3, r1 800f72c: 0e1b lsrs r3, r3, #24 800f72e: 4313 orrs r3, r2 800f730: 4a19 ldr r2, [pc, #100] ; (800f798 ) 800f732: 6013 str r3, [r2, #0] /* add the network interface (IPv4/IPv6) with RTOS */ netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, &tcpip_input); 800f734: 4b19 ldr r3, [pc, #100] ; (800f79c ) 800f736: 9302 str r3, [sp, #8] 800f738: 4b19 ldr r3, [pc, #100] ; (800f7a0 ) 800f73a: 9301 str r3, [sp, #4] 800f73c: 2300 movs r3, #0 800f73e: 9300 str r3, [sp, #0] 800f740: 4b15 ldr r3, [pc, #84] ; (800f798 ) 800f742: 4a14 ldr r2, [pc, #80] ; (800f794 ) 800f744: 4912 ldr r1, [pc, #72] ; (800f790 ) 800f746: 4817 ldr r0, [pc, #92] ; (800f7a4 ) 800f748: f007 fa6a bl 8016c20 /* Registers the default network interface */ netif_set_default(&gnetif); 800f74c: 4815 ldr r0, [pc, #84] ; (800f7a4 ) 800f74e: f007 fcfb bl 8017148 /* We must always bring the network interface up connection or not... */ netif_set_up(&gnetif); 800f752: 4814 ldr r0, [pc, #80] ; (800f7a4 ) 800f754: f007 fd1c bl 8017190 /* Set the link callback function, this function is called on change of link status*/ netif_set_link_callback(&gnetif, ethernet_link_status_updated); 800f758: 4913 ldr r1, [pc, #76] ; (800f7a8 ) 800f75a: 4812 ldr r0, [pc, #72] ; (800f7a4 ) 800f75c: f007 fe1a bl 8017394 /* Create the Ethernet link handler thread */ /* USER CODE BEGIN H7_OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */ osThreadDef(EthLink, ethernet_link_thread, osPriorityBelowNormal, 0, configMINIMAL_STACK_SIZE *2); 800f760: 4b12 ldr r3, [pc, #72] ; (800f7ac ) 800f762: 1d3c adds r4, r7, #4 800f764: 461d mov r5, r3 800f766: cd0f ldmia r5!, {r0, r1, r2, r3} 800f768: c40f stmia r4!, {r0, r1, r2, r3} 800f76a: e895 0007 ldmia.w r5, {r0, r1, r2} 800f76e: e884 0007 stmia.w r4, {r0, r1, r2} osThreadCreate (osThread(EthLink), &gnetif); 800f772: 1d3b adds r3, r7, #4 800f774: 490b ldr r1, [pc, #44] ; (800f7a4 ) 800f776: 4618 mov r0, r3 800f778: f000 fdb6 bl 80102e8 /* USER CODE END H7_OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */ /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ } 800f77c: bf00 nop 800f77e: 3720 adds r7, #32 800f780: 46bd mov sp, r7 800f782: bdb0 pop {r4, r5, r7, pc} 800f784: 2400742c .word 0x2400742c 800f788: 24007430 .word 0x24007430 800f78c: 24007434 .word 0x24007434 800f790: 24007420 .word 0x24007420 800f794: 24007424 .word 0x24007424 800f798: 24007428 .word 0x24007428 800f79c: 08015dbd .word 0x08015dbd 800f7a0: 0800fc85 .word 0x0800fc85 800f7a4: 240073ec .word 0x240073ec 800f7a8: 0800f7b1 .word 0x0800f7b1 800f7ac: 08023208 .word 0x08023208 0800f7b0 : * @brief Notify the User about the network interface config status * @param netif: the network interface * @retval None */ static void ethernet_link_status_updated(struct netif *netif) { 800f7b0: b480 push {r7} 800f7b2: b083 sub sp, #12 800f7b4: af00 add r7, sp, #0 800f7b6: 6078 str r0, [r7, #4] else /* netif is down */ { /* USER CODE BEGIN 6 */ /* USER CODE END 6 */ } } 800f7b8: bf00 nop 800f7ba: 370c adds r7, #12 800f7bc: 46bd mov sp, r7 800f7be: f85d 7b04 ldr.w r7, [sp], #4 800f7c2: 4770 bx lr 0800f7c4 : * @brief Ethernet Rx Transfer completed callback * @param handlerEth: ETH handler * @retval None */ void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *handlerEth) { 800f7c4: b580 push {r7, lr} 800f7c6: b082 sub sp, #8 800f7c8: af00 add r7, sp, #0 800f7ca: 6078 str r0, [r7, #4] osSemaphoreRelease(RxPktSemaphore); 800f7cc: 4b04 ldr r3, [pc, #16] ; (800f7e0 ) 800f7ce: 681b ldr r3, [r3, #0] 800f7d0: 4618 mov r0, r3 800f7d2: f000 ff05 bl 80105e0 } 800f7d6: bf00 nop 800f7d8: 3708 adds r7, #8 800f7da: 46bd mov sp, r7 800f7dc: bd80 pop {r7, pc} 800f7de: bf00 nop 800f7e0: 2400bdc4 .word 0x2400bdc4 0800f7e4 : * @brief Ethernet Tx Transfer completed callback * @param handlerEth: ETH handler * @retval None */ void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *handlerEth) { 800f7e4: b580 push {r7, lr} 800f7e6: b082 sub sp, #8 800f7e8: af00 add r7, sp, #0 800f7ea: 6078 str r0, [r7, #4] osSemaphoreRelease(TxPktSemaphore); 800f7ec: 4b04 ldr r3, [pc, #16] ; (800f800 ) 800f7ee: 681b ldr r3, [r3, #0] 800f7f0: 4618 mov r0, r3 800f7f2: f000 fef5 bl 80105e0 } 800f7f6: bf00 nop 800f7f8: 3708 adds r7, #8 800f7fa: 46bd mov sp, r7 800f7fc: bd80 pop {r7, pc} 800f7fe: bf00 nop 800f800: 2400bdc8 .word 0x2400bdc8 0800f804 : * @brief Ethernet DMA transfer error callback * @param handlerEth: ETH handler * @retval None */ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *handlerEth) { 800f804: b580 push {r7, lr} 800f806: b082 sub sp, #8 800f808: af00 add r7, sp, #0 800f80a: 6078 str r0, [r7, #4] if((HAL_ETH_GetDMAError(handlerEth) & ETH_DMACSR_RBU) == ETH_DMACSR_RBU) 800f80c: 6878 ldr r0, [r7, #4] 800f80e: f7f5 fbe7 bl 8004fe0 800f812: 4603 mov r3, r0 800f814: f003 0380 and.w r3, r3, #128 ; 0x80 800f818: 2b80 cmp r3, #128 ; 0x80 800f81a: d104 bne.n 800f826 { osSemaphoreRelease(RxPktSemaphore); 800f81c: 4b04 ldr r3, [pc, #16] ; (800f830 ) 800f81e: 681b ldr r3, [r3, #0] 800f820: 4618 mov r0, r3 800f822: f000 fedd bl 80105e0 } } 800f826: bf00 nop 800f828: 3708 adds r7, #8 800f82a: 46bd mov sp, r7 800f82c: bd80 pop {r7, pc} 800f82e: bf00 nop 800f830: 2400bdc4 .word 0x2400bdc4 0800f834 : * * @param netif the already initialized lwip network interface structure * for this ethernetif */ static void low_level_init(struct netif *netif) { 800f834: b5b0 push {r4, r5, r7, lr} 800f836: b0ac sub sp, #176 ; 0xb0 800f838: af00 add r7, sp, #0 800f83a: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_eth_init_status = HAL_OK; 800f83c: 2300 movs r3, #0 800f83e: f887 30a7 strb.w r3, [r7, #167] ; 0xa7 uint32_t duplex, speed = 0; 800f842: 2300 movs r3, #0 800f844: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 int32_t PHYLinkState = 0; 800f848: 2300 movs r3, #0 800f84a: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 ETH_MACConfigTypeDef MACConf = {0}; 800f84e: f107 033c add.w r3, r7, #60 ; 0x3c 800f852: 2264 movs r2, #100 ; 0x64 800f854: 2100 movs r1, #0 800f856: 4618 mov r0, r3 800f858: f012 fa42 bl 8021ce0 /* Start ETH HAL Init */ uint8_t MACAddr[6] ; heth.Instance = ETH; 800f85c: 4b8f ldr r3, [pc, #572] ; (800fa9c ) 800f85e: 4a90 ldr r2, [pc, #576] ; (800faa0 ) 800f860: 601a str r2, [r3, #0] MACAddr[0] = 0x00; 800f862: 2300 movs r3, #0 800f864: f887 3034 strb.w r3, [r7, #52] ; 0x34 MACAddr[1] = 0x80; 800f868: 2380 movs r3, #128 ; 0x80 800f86a: f887 3035 strb.w r3, [r7, #53] ; 0x35 MACAddr[2] = 0xE1; 800f86e: 23e1 movs r3, #225 ; 0xe1 800f870: f887 3036 strb.w r3, [r7, #54] ; 0x36 MACAddr[3] = 0x00; 800f874: 2300 movs r3, #0 800f876: f887 3037 strb.w r3, [r7, #55] ; 0x37 MACAddr[4] = 0x00; 800f87a: 2300 movs r3, #0 800f87c: f887 3038 strb.w r3, [r7, #56] ; 0x38 MACAddr[5] = 0x00; 800f880: 2300 movs r3, #0 800f882: f887 3039 strb.w r3, [r7, #57] ; 0x39 heth.Init.MACAddr = &MACAddr[0]; 800f886: 4a85 ldr r2, [pc, #532] ; (800fa9c ) 800f888: f107 0334 add.w r3, r7, #52 ; 0x34 800f88c: 6053 str r3, [r2, #4] heth.Init.MediaInterface = HAL_ETH_RMII_MODE; 800f88e: 4b83 ldr r3, [pc, #524] ; (800fa9c ) 800f890: 2201 movs r2, #1 800f892: 721a strb r2, [r3, #8] heth.Init.TxDesc = DMATxDscrTab; 800f894: 4b81 ldr r3, [pc, #516] ; (800fa9c ) 800f896: 4a83 ldr r2, [pc, #524] ; (800faa4 ) 800f898: 60da str r2, [r3, #12] heth.Init.RxDesc = DMARxDscrTab; 800f89a: 4b80 ldr r3, [pc, #512] ; (800fa9c ) 800f89c: 4a82 ldr r2, [pc, #520] ; (800faa8 ) 800f89e: 611a str r2, [r3, #16] heth.Init.RxBuffLen = 1536; 800f8a0: 4b7e ldr r3, [pc, #504] ; (800fa9c ) 800f8a2: f44f 62c0 mov.w r2, #1536 ; 0x600 800f8a6: 615a str r2, [r3, #20] /* USER CODE BEGIN MACADDRESS */ /* USER CODE END MACADDRESS */ hal_eth_init_status = HAL_ETH_Init(&heth); 800f8a8: 487c ldr r0, [pc, #496] ; (800fa9c ) 800f8aa: f7f4 fbb9 bl 8004020 800f8ae: 4603 mov r3, r0 800f8b0: f887 30a7 strb.w r3, [r7, #167] ; 0xa7 memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); 800f8b4: 2238 movs r2, #56 ; 0x38 800f8b6: 2100 movs r1, #0 800f8b8: 487c ldr r0, [pc, #496] ; (800faac ) 800f8ba: f012 fa11 bl 8021ce0 TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; 800f8be: 4b7b ldr r3, [pc, #492] ; (800faac ) 800f8c0: 2221 movs r2, #33 ; 0x21 800f8c2: 601a str r2, [r3, #0] TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; 800f8c4: 4b79 ldr r3, [pc, #484] ; (800faac ) 800f8c6: f44f 3240 mov.w r2, #196608 ; 0x30000 800f8ca: 615a str r2, [r3, #20] TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; 800f8cc: 4b77 ldr r3, [pc, #476] ; (800faac ) 800f8ce: 2200 movs r2, #0 800f8d0: 611a str r2, [r3, #16] /* End ETH HAL Init */ /* Initialize the RX POOL */ LWIP_MEMPOOL_INIT(RX_POOL); 800f8d2: 4877 ldr r0, [pc, #476] ; (800fab0 ) 800f8d4: f007 f856 bl 8016984 #if LWIP_ARP || LWIP_ETHERNET /* set MAC hardware address length */ netif->hwaddr_len = ETH_HWADDR_LEN; 800f8d8: 687b ldr r3, [r7, #4] 800f8da: 2206 movs r2, #6 800f8dc: f883 202c strb.w r2, [r3, #44] ; 0x2c /* set MAC hardware address */ netif->hwaddr[0] = heth.Init.MACAddr[0]; 800f8e0: 4b6e ldr r3, [pc, #440] ; (800fa9c ) 800f8e2: 685b ldr r3, [r3, #4] 800f8e4: 781a ldrb r2, [r3, #0] 800f8e6: 687b ldr r3, [r7, #4] 800f8e8: f883 2026 strb.w r2, [r3, #38] ; 0x26 netif->hwaddr[1] = heth.Init.MACAddr[1]; 800f8ec: 4b6b ldr r3, [pc, #428] ; (800fa9c ) 800f8ee: 685b ldr r3, [r3, #4] 800f8f0: 785a ldrb r2, [r3, #1] 800f8f2: 687b ldr r3, [r7, #4] 800f8f4: f883 2027 strb.w r2, [r3, #39] ; 0x27 netif->hwaddr[2] = heth.Init.MACAddr[2]; 800f8f8: 4b68 ldr r3, [pc, #416] ; (800fa9c ) 800f8fa: 685b ldr r3, [r3, #4] 800f8fc: 789a ldrb r2, [r3, #2] 800f8fe: 687b ldr r3, [r7, #4] 800f900: f883 2028 strb.w r2, [r3, #40] ; 0x28 netif->hwaddr[3] = heth.Init.MACAddr[3]; 800f904: 4b65 ldr r3, [pc, #404] ; (800fa9c ) 800f906: 685b ldr r3, [r3, #4] 800f908: 78da ldrb r2, [r3, #3] 800f90a: 687b ldr r3, [r7, #4] 800f90c: f883 2029 strb.w r2, [r3, #41] ; 0x29 netif->hwaddr[4] = heth.Init.MACAddr[4]; 800f910: 4b62 ldr r3, [pc, #392] ; (800fa9c ) 800f912: 685b ldr r3, [r3, #4] 800f914: 791a ldrb r2, [r3, #4] 800f916: 687b ldr r3, [r7, #4] 800f918: f883 202a strb.w r2, [r3, #42] ; 0x2a netif->hwaddr[5] = heth.Init.MACAddr[5]; 800f91c: 4b5f ldr r3, [pc, #380] ; (800fa9c ) 800f91e: 685b ldr r3, [r3, #4] 800f920: 795a ldrb r2, [r3, #5] 800f922: 687b ldr r3, [r7, #4] 800f924: f883 202b strb.w r2, [r3, #43] ; 0x2b /* maximum transfer unit */ netif->mtu = ETH_MAX_PAYLOAD; 800f928: 687b ldr r3, [r7, #4] 800f92a: f240 52dc movw r2, #1500 ; 0x5dc 800f92e: 849a strh r2, [r3, #36] ; 0x24 /* Accept broadcast address and ARP traffic */ /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ #if LWIP_ARP netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; 800f930: 687b ldr r3, [r7, #4] 800f932: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 800f936: f043 030a orr.w r3, r3, #10 800f93a: b2da uxtb r2, r3 800f93c: 687b ldr r3, [r7, #4] 800f93e: f883 202d strb.w r2, [r3, #45] ; 0x2d #else netif->flags |= NETIF_FLAG_BROADCAST; #endif /* LWIP_ARP */ /* create a binary semaphore used for informing ethernetif of frame reception */ osSemaphoreDef(RxSem); 800f942: 2300 movs r3, #0 800f944: 62fb str r3, [r7, #44] ; 0x2c 800f946: 2300 movs r3, #0 800f948: 633b str r3, [r7, #48] ; 0x30 RxPktSemaphore = osSemaphoreCreate(osSemaphore(RxSem), 1); 800f94a: f107 032c add.w r3, r7, #44 ; 0x2c 800f94e: 2101 movs r1, #1 800f950: 4618 mov r0, r3 800f952: f000 fdc5 bl 80104e0 800f956: 4603 mov r3, r0 800f958: 4a56 ldr r2, [pc, #344] ; (800fab4 ) 800f95a: 6013 str r3, [r2, #0] /* create a binary semaphore used for informing ethernetif of frame transmission */ osSemaphoreDef(TxSem); 800f95c: 2300 movs r3, #0 800f95e: 627b str r3, [r7, #36] ; 0x24 800f960: 2300 movs r3, #0 800f962: 62bb str r3, [r7, #40] ; 0x28 TxPktSemaphore = osSemaphoreCreate(osSemaphore(TxSem), 1); 800f964: f107 0324 add.w r3, r7, #36 ; 0x24 800f968: 2101 movs r1, #1 800f96a: 4618 mov r0, r3 800f96c: f000 fdb8 bl 80104e0 800f970: 4603 mov r3, r0 800f972: 4a51 ldr r2, [pc, #324] ; (800fab8 ) 800f974: 6013 str r3, [r2, #0] /* Decrease the semaphore's initial count from 1 to 0 */ osSemaphoreWait(RxPktSemaphore, 0); 800f976: 4b4f ldr r3, [pc, #316] ; (800fab4 ) 800f978: 681b ldr r3, [r3, #0] 800f97a: 2100 movs r1, #0 800f97c: 4618 mov r0, r3 800f97e: f000 fde1 bl 8010544 osSemaphoreWait(TxPktSemaphore, 0); 800f982: 4b4d ldr r3, [pc, #308] ; (800fab8 ) 800f984: 681b ldr r3, [r3, #0] 800f986: 2100 movs r1, #0 800f988: 4618 mov r0, r3 800f98a: f000 fddb bl 8010544 /* create the task that handles the ETH_MAC */ /* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */ osThreadDef(EthIf, ethernetif_input, osPriorityRealtime, 0, INTERFACE_THREAD_STACK_SIZE); 800f98e: 4b4b ldr r3, [pc, #300] ; (800fabc ) 800f990: f107 0408 add.w r4, r7, #8 800f994: 461d mov r5, r3 800f996: cd0f ldmia r5!, {r0, r1, r2, r3} 800f998: c40f stmia r4!, {r0, r1, r2, r3} 800f99a: e895 0007 ldmia.w r5, {r0, r1, r2} 800f99e: e884 0007 stmia.w r4, {r0, r1, r2} osThreadCreate (osThread(EthIf), netif); 800f9a2: f107 0308 add.w r3, r7, #8 800f9a6: 6879 ldr r1, [r7, #4] 800f9a8: 4618 mov r0, r3 800f9aa: f000 fc9d bl 80102e8 /* USER CODE BEGIN PHY_PRE_CONFIG */ /* USER CODE END PHY_PRE_CONFIG */ /* Set PHY IO functions */ LAN8742_RegisterBusIO(&LAN8742, &LAN8742_IOCtx); 800f9ae: 4944 ldr r1, [pc, #272] ; (800fac0 ) 800f9b0: 4844 ldr r0, [pc, #272] ; (800fac4 ) 800f9b2: f7f2 fb26 bl 8002002 /* Initialize the LAN8742 ETH PHY */ LAN8742_Init(&LAN8742); 800f9b6: 4843 ldr r0, [pc, #268] ; (800fac4 ) 800f9b8: f7f2 fb55 bl 8002066 if (hal_eth_init_status == HAL_OK) 800f9bc: f897 30a7 ldrb.w r3, [r7, #167] ; 0xa7 800f9c0: 2b00 cmp r3, #0 800f9c2: d164 bne.n 800fa8e { PHYLinkState = LAN8742_GetLinkState(&LAN8742); 800f9c4: 483f ldr r0, [pc, #252] ; (800fac4 ) 800f9c6: f7f2 fbf6 bl 80021b6 800f9ca: f8c7 00a0 str.w r0, [r7, #160] ; 0xa0 /* Get link state */ if(PHYLinkState <= LAN8742_STATUS_LINK_DOWN) 800f9ce: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 800f9d2: 2b01 cmp r3, #1 800f9d4: dc06 bgt.n 800f9e4 { netif_set_link_down(netif); 800f9d6: 6878 ldr r0, [r7, #4] 800f9d8: f007 fcac bl 8017334 netif_set_down(netif); 800f9dc: 6878 ldr r0, [r7, #4] 800f9de: f007 fc43 bl 8017268 #endif /* LWIP_ARP || LWIP_ETHERNET */ /* USER CODE BEGIN LOW_LEVEL_INIT */ /* USER CODE END LOW_LEVEL_INIT */ } 800f9e2: e056 b.n 800fa92 switch (PHYLinkState) 800f9e4: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 800f9e8: 3b02 subs r3, #2 800f9ea: 2b03 cmp r3, #3 800f9ec: d82a bhi.n 800fa44 800f9ee: a201 add r2, pc, #4 ; (adr r2, 800f9f4 ) 800f9f0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800f9f4: 0800fa05 .word 0x0800fa05 800f9f8: 0800fa17 .word 0x0800fa17 800f9fc: 0800fa27 .word 0x0800fa27 800fa00: 0800fa37 .word 0x0800fa37 duplex = ETH_FULLDUPLEX_MODE; 800fa04: f44f 5300 mov.w r3, #8192 ; 0x2000 800fa08: f8c7 30ac str.w r3, [r7, #172] ; 0xac speed = ETH_SPEED_100M; 800fa0c: f44f 4380 mov.w r3, #16384 ; 0x4000 800fa10: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 break; 800fa14: e01f b.n 800fa56 duplex = ETH_HALFDUPLEX_MODE; 800fa16: 2300 movs r3, #0 800fa18: f8c7 30ac str.w r3, [r7, #172] ; 0xac speed = ETH_SPEED_100M; 800fa1c: f44f 4380 mov.w r3, #16384 ; 0x4000 800fa20: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 break; 800fa24: e017 b.n 800fa56 duplex = ETH_FULLDUPLEX_MODE; 800fa26: f44f 5300 mov.w r3, #8192 ; 0x2000 800fa2a: f8c7 30ac str.w r3, [r7, #172] ; 0xac speed = ETH_SPEED_10M; 800fa2e: 2300 movs r3, #0 800fa30: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 break; 800fa34: e00f b.n 800fa56 duplex = ETH_HALFDUPLEX_MODE; 800fa36: 2300 movs r3, #0 800fa38: f8c7 30ac str.w r3, [r7, #172] ; 0xac speed = ETH_SPEED_10M; 800fa3c: 2300 movs r3, #0 800fa3e: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 break; 800fa42: e008 b.n 800fa56 duplex = ETH_FULLDUPLEX_MODE; 800fa44: f44f 5300 mov.w r3, #8192 ; 0x2000 800fa48: f8c7 30ac str.w r3, [r7, #172] ; 0xac speed = ETH_SPEED_100M; 800fa4c: f44f 4380 mov.w r3, #16384 ; 0x4000 800fa50: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 break; 800fa54: bf00 nop HAL_ETH_GetMACConfig(&heth, &MACConf); 800fa56: f107 033c add.w r3, r7, #60 ; 0x3c 800fa5a: 4619 mov r1, r3 800fa5c: 480f ldr r0, [pc, #60] ; (800fa9c ) 800fa5e: f7f5 f879 bl 8004b54 MACConf.DuplexMode = duplex; 800fa62: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac 800fa66: 657b str r3, [r7, #84] ; 0x54 MACConf.Speed = speed; 800fa68: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 800fa6c: 653b str r3, [r7, #80] ; 0x50 HAL_ETH_SetMACConfig(&heth, &MACConf); 800fa6e: f107 033c add.w r3, r7, #60 ; 0x3c 800fa72: 4619 mov r1, r3 800fa74: 4809 ldr r0, [pc, #36] ; (800fa9c ) 800fa76: f7f5 fa41 bl 8004efc HAL_ETH_Start_IT(&heth); 800fa7a: 4808 ldr r0, [pc, #32] ; (800fa9c ) 800fa7c: f7f4 fbb6 bl 80041ec netif_set_up(netif); 800fa80: 6878 ldr r0, [r7, #4] 800fa82: f007 fb85 bl 8017190 netif_set_link_up(netif); 800fa86: 6878 ldr r0, [r7, #4] 800fa88: f007 fc20 bl 80172cc } 800fa8c: e001 b.n 800fa92 Error_Handler(); 800fa8e: f7f1 fd31 bl 80014f4 } 800fa92: bf00 nop 800fa94: 37b0 adds r7, #176 ; 0xb0 800fa96: 46bd mov sp, r7 800fa98: bdb0 pop {r4, r5, r7, pc} 800fa9a: bf00 nop 800fa9c: 2400bdcc .word 0x2400bdcc 800faa0: 40028000 .word 0x40028000 800faa4: 30000100 .word 0x30000100 800faa8: 30000000 .word 0x30000000 800faac: 2400be7c .word 0x2400be7c 800fab0: 08026b94 .word 0x08026b94 800fab4: 2400bdc4 .word 0x2400bdc4 800fab8: 2400bdc8 .word 0x2400bdc8 800fabc: 08023244 .word 0x08023244 800fac0: 24000024 .word 0x24000024 800fac4: 2400beb4 .word 0x2400beb4 0800fac8 : * to become available since the stack doesn't retry to send a packet * dropped because of memory failure (except for the TCP timers). */ static err_t low_level_output(struct netif *netif, struct pbuf *p) { 800fac8: b580 push {r7, lr} 800faca: b092 sub sp, #72 ; 0x48 800facc: af00 add r7, sp, #0 800face: 6078 str r0, [r7, #4] 800fad0: 6039 str r1, [r7, #0] uint32_t i = 0U; 800fad2: 2300 movs r3, #0 800fad4: 647b str r3, [r7, #68] ; 0x44 struct pbuf *q = NULL; 800fad6: 2300 movs r3, #0 800fad8: 643b str r3, [r7, #64] ; 0x40 err_t errval = ERR_OK; 800fada: 2300 movs r3, #0 800fadc: f887 303f strb.w r3, [r7, #63] ; 0x3f ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0}; 800fae0: f107 030c add.w r3, r7, #12 800fae4: 2230 movs r2, #48 ; 0x30 800fae6: 2100 movs r1, #0 800fae8: 4618 mov r0, r3 800faea: f012 f8f9 bl 8021ce0 memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef)); 800faee: f107 030c add.w r3, r7, #12 800faf2: 2230 movs r2, #48 ; 0x30 800faf4: 2100 movs r1, #0 800faf6: 4618 mov r0, r3 800faf8: f012 f8f2 bl 8021ce0 for(q = p; q != NULL; q = q->next) 800fafc: 683b ldr r3, [r7, #0] 800fafe: 643b str r3, [r7, #64] ; 0x40 800fb00: e045 b.n 800fb8e { if(i >= ETH_TX_DESC_CNT) 800fb02: 6c7b ldr r3, [r7, #68] ; 0x44 800fb04: 2b03 cmp r3, #3 800fb06: d902 bls.n 800fb0e return ERR_IF; 800fb08: f06f 030b mvn.w r3, #11 800fb0c: e06c b.n 800fbe8 Txbuffer[i].buffer = q->payload; 800fb0e: 6c3b ldr r3, [r7, #64] ; 0x40 800fb10: 6859 ldr r1, [r3, #4] 800fb12: 6c7a ldr r2, [r7, #68] ; 0x44 800fb14: 4613 mov r3, r2 800fb16: 005b lsls r3, r3, #1 800fb18: 4413 add r3, r2 800fb1a: 009b lsls r3, r3, #2 800fb1c: 3348 adds r3, #72 ; 0x48 800fb1e: 443b add r3, r7 800fb20: 3b3c subs r3, #60 ; 0x3c 800fb22: 6019 str r1, [r3, #0] Txbuffer[i].len = q->len; 800fb24: 6c3b ldr r3, [r7, #64] ; 0x40 800fb26: 895b ldrh r3, [r3, #10] 800fb28: 4619 mov r1, r3 800fb2a: 6c7a ldr r2, [r7, #68] ; 0x44 800fb2c: 4613 mov r3, r2 800fb2e: 005b lsls r3, r3, #1 800fb30: 4413 add r3, r2 800fb32: 009b lsls r3, r3, #2 800fb34: 3348 adds r3, #72 ; 0x48 800fb36: 443b add r3, r7 800fb38: 3b38 subs r3, #56 ; 0x38 800fb3a: 6019 str r1, [r3, #0] if(i>0) 800fb3c: 6c7b ldr r3, [r7, #68] ; 0x44 800fb3e: 2b00 cmp r3, #0 800fb40: d011 beq.n 800fb66 { Txbuffer[i-1].next = &Txbuffer[i]; 800fb42: 6c7b ldr r3, [r7, #68] ; 0x44 800fb44: 1e5a subs r2, r3, #1 800fb46: f107 000c add.w r0, r7, #12 800fb4a: 6c79 ldr r1, [r7, #68] ; 0x44 800fb4c: 460b mov r3, r1 800fb4e: 005b lsls r3, r3, #1 800fb50: 440b add r3, r1 800fb52: 009b lsls r3, r3, #2 800fb54: 18c1 adds r1, r0, r3 800fb56: 4613 mov r3, r2 800fb58: 005b lsls r3, r3, #1 800fb5a: 4413 add r3, r2 800fb5c: 009b lsls r3, r3, #2 800fb5e: 3348 adds r3, #72 ; 0x48 800fb60: 443b add r3, r7 800fb62: 3b34 subs r3, #52 ; 0x34 800fb64: 6019 str r1, [r3, #0] } if(q->next == NULL) 800fb66: 6c3b ldr r3, [r7, #64] ; 0x40 800fb68: 681b ldr r3, [r3, #0] 800fb6a: 2b00 cmp r3, #0 800fb6c: d109 bne.n 800fb82 { Txbuffer[i].next = NULL; 800fb6e: 6c7a ldr r2, [r7, #68] ; 0x44 800fb70: 4613 mov r3, r2 800fb72: 005b lsls r3, r3, #1 800fb74: 4413 add r3, r2 800fb76: 009b lsls r3, r3, #2 800fb78: 3348 adds r3, #72 ; 0x48 800fb7a: 443b add r3, r7 800fb7c: 3b34 subs r3, #52 ; 0x34 800fb7e: 2200 movs r2, #0 800fb80: 601a str r2, [r3, #0] } i++; 800fb82: 6c7b ldr r3, [r7, #68] ; 0x44 800fb84: 3301 adds r3, #1 800fb86: 647b str r3, [r7, #68] ; 0x44 for(q = p; q != NULL; q = q->next) 800fb88: 6c3b ldr r3, [r7, #64] ; 0x40 800fb8a: 681b ldr r3, [r3, #0] 800fb8c: 643b str r3, [r7, #64] ; 0x40 800fb8e: 6c3b ldr r3, [r7, #64] ; 0x40 800fb90: 2b00 cmp r3, #0 800fb92: d1b6 bne.n 800fb02 } TxConfig.Length = p->tot_len; 800fb94: 683b ldr r3, [r7, #0] 800fb96: 891b ldrh r3, [r3, #8] 800fb98: 461a mov r2, r3 800fb9a: 4b15 ldr r3, [pc, #84] ; (800fbf0 ) 800fb9c: 605a str r2, [r3, #4] TxConfig.TxBuffer = Txbuffer; 800fb9e: 4a14 ldr r2, [pc, #80] ; (800fbf0 ) 800fba0: f107 030c add.w r3, r7, #12 800fba4: 6093 str r3, [r2, #8] TxConfig.pData = p; 800fba6: 4a12 ldr r2, [pc, #72] ; (800fbf0 ) 800fba8: 683b ldr r3, [r7, #0] 800fbaa: 6353 str r3, [r2, #52] ; 0x34 pbuf_ref(p); 800fbac: 6838 ldr r0, [r7, #0] 800fbae: f008 f849 bl 8017c44 if (HAL_ETH_Transmit_IT(&heth, &TxConfig) == HAL_OK) { 800fbb2: 490f ldr r1, [pc, #60] ; (800fbf0 ) 800fbb4: 480f ldr r0, [pc, #60] ; (800fbf4 ) 800fbb6: f7f4 fc1d bl 80043f4 800fbba: 4603 mov r3, r0 800fbbc: 2b00 cmp r3, #0 800fbbe: d10e bne.n 800fbde while(osSemaphoreWait(TxPktSemaphore, TIME_WAITING_FOR_INPUT)!=osOK) 800fbc0: bf00 nop 800fbc2: 4b0d ldr r3, [pc, #52] ; (800fbf8 ) 800fbc4: 681b ldr r3, [r3, #0] 800fbc6: f04f 31ff mov.w r1, #4294967295 800fbca: 4618 mov r0, r3 800fbcc: f000 fcba bl 8010544 800fbd0: 4603 mov r3, r0 800fbd2: 2b00 cmp r3, #0 800fbd4: d1f5 bne.n 800fbc2 { } HAL_ETH_ReleaseTxPacket(&heth); 800fbd6: 4807 ldr r0, [pc, #28] ; (800fbf4 ) 800fbd8: f7f4 fd8b bl 80046f2 800fbdc: e002 b.n 800fbe4 } else { pbuf_free(p); 800fbde: 6838 ldr r0, [r7, #0] 800fbe0: f007 ff8a bl 8017af8 } return errval; 800fbe4: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f } 800fbe8: 4618 mov r0, r3 800fbea: 3748 adds r7, #72 ; 0x48 800fbec: 46bd mov sp, r7 800fbee: bd80 pop {r7, pc} 800fbf0: 2400be7c .word 0x2400be7c 800fbf4: 2400bdcc .word 0x2400bdcc 800fbf8: 2400bdc8 .word 0x2400bdc8 0800fbfc : * @param netif the lwip network interface structure for this ethernetif * @return a pbuf filled with the received packet (including MAC header) * NULL on memory error */ static struct pbuf * low_level_input(struct netif *netif) { 800fbfc: b580 push {r7, lr} 800fbfe: b084 sub sp, #16 800fc00: af00 add r7, sp, #0 800fc02: 6078 str r0, [r7, #4] struct pbuf *p = NULL; 800fc04: 2300 movs r3, #0 800fc06: 60fb str r3, [r7, #12] if(RxAllocStatus == RX_ALLOC_OK) 800fc08: 4b07 ldr r3, [pc, #28] ; (800fc28 ) 800fc0a: 781b ldrb r3, [r3, #0] 800fc0c: 2b00 cmp r3, #0 800fc0e: d105 bne.n 800fc1c { HAL_ETH_ReadData(&heth, (void **)&p); 800fc10: f107 030c add.w r3, r7, #12 800fc14: 4619 mov r1, r3 800fc16: 4805 ldr r0, [pc, #20] ; (800fc2c ) 800fc18: f7f4 fc3d bl 8004496 } return p; 800fc1c: 68fb ldr r3, [r7, #12] } 800fc1e: 4618 mov r0, r3 800fc20: 3710 adds r7, #16 800fc22: 46bd mov sp, r7 800fc24: bd80 pop {r7, pc} 800fc26: bf00 nop 800fc28: 2400bdc0 .word 0x2400bdc0 800fc2c: 2400bdcc .word 0x2400bdcc 0800fc30 : * the appropriate input function is called. * * @param netif the lwip network interface structure for this ethernetif */ static void ethernetif_input(void const * argument) { 800fc30: b580 push {r7, lr} 800fc32: b084 sub sp, #16 800fc34: af00 add r7, sp, #0 800fc36: 6078 str r0, [r7, #4] struct pbuf *p = NULL; 800fc38: 2300 movs r3, #0 800fc3a: 60fb str r3, [r7, #12] struct netif *netif = (struct netif *) argument; 800fc3c: 687b ldr r3, [r7, #4] 800fc3e: 60bb str r3, [r7, #8] for( ;; ) { if (osSemaphoreWait(RxPktSemaphore, TIME_WAITING_FOR_INPUT) == osOK) 800fc40: 4b0f ldr r3, [pc, #60] ; (800fc80 ) 800fc42: 681b ldr r3, [r3, #0] 800fc44: f04f 31ff mov.w r1, #4294967295 800fc48: 4618 mov r0, r3 800fc4a: f000 fc7b bl 8010544 800fc4e: 4603 mov r3, r0 800fc50: 2b00 cmp r3, #0 800fc52: d1f5 bne.n 800fc40 { do { p = low_level_input( netif ); 800fc54: 68b8 ldr r0, [r7, #8] 800fc56: f7ff ffd1 bl 800fbfc 800fc5a: 60f8 str r0, [r7, #12] if (p != NULL) 800fc5c: 68fb ldr r3, [r7, #12] 800fc5e: 2b00 cmp r3, #0 800fc60: d00a beq.n 800fc78 { if (netif->input( p, netif) != ERR_OK ) 800fc62: 68bb ldr r3, [r7, #8] 800fc64: 691b ldr r3, [r3, #16] 800fc66: 68b9 ldr r1, [r7, #8] 800fc68: 68f8 ldr r0, [r7, #12] 800fc6a: 4798 blx r3 800fc6c: 4603 mov r3, r0 800fc6e: 2b00 cmp r3, #0 800fc70: d002 beq.n 800fc78 { pbuf_free(p); 800fc72: 68f8 ldr r0, [r7, #12] 800fc74: f007 ff40 bl 8017af8 } } } while(p!=NULL); 800fc78: 68fb ldr r3, [r7, #12] 800fc7a: 2b00 cmp r3, #0 800fc7c: d1ea bne.n 800fc54 if (osSemaphoreWait(RxPktSemaphore, TIME_WAITING_FOR_INPUT) == osOK) 800fc7e: e7df b.n 800fc40 800fc80: 2400bdc4 .word 0x2400bdc4 0800fc84 : * @return ERR_OK if the loopif is initialized * ERR_MEM if private data couldn't be allocated * any other err_t on error */ err_t ethernetif_init(struct netif *netif) { 800fc84: b580 push {r7, lr} 800fc86: b082 sub sp, #8 800fc88: af00 add r7, sp, #0 800fc8a: 6078 str r0, [r7, #4] LWIP_ASSERT("netif != NULL", (netif != NULL)); 800fc8c: 687b ldr r3, [r7, #4] 800fc8e: 2b00 cmp r3, #0 800fc90: d106 bne.n 800fca0 800fc92: 4b0e ldr r3, [pc, #56] ; (800fccc ) 800fc94: f240 12f9 movw r2, #505 ; 0x1f9 800fc98: 490d ldr r1, [pc, #52] ; (800fcd0 ) 800fc9a: 480e ldr r0, [pc, #56] ; (800fcd4 ) 800fc9c: f011 fe74 bl 8021988 * The last argument should be replaced with your link speed, in units * of bits per second. */ // MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS); netif->name[0] = IFNAME0; 800fca0: 687b ldr r3, [r7, #4] 800fca2: 2273 movs r2, #115 ; 0x73 800fca4: f883 202e strb.w r2, [r3, #46] ; 0x2e netif->name[1] = IFNAME1; 800fca8: 687b ldr r3, [r7, #4] 800fcaa: 2274 movs r2, #116 ; 0x74 800fcac: f883 202f strb.w r2, [r3, #47] ; 0x2f * is available...) */ #if LWIP_IPV4 #if LWIP_ARP || LWIP_ETHERNET #if LWIP_ARP netif->output = etharp_output; 800fcb0: 687b ldr r3, [r7, #4] 800fcb2: 4a09 ldr r2, [pc, #36] ; (800fcd8 ) 800fcb4: 615a str r2, [r3, #20] #if LWIP_IPV6 netif->output_ip6 = ethip6_output; #endif /* LWIP_IPV6 */ netif->linkoutput = low_level_output; 800fcb6: 687b ldr r3, [r7, #4] 800fcb8: 4a08 ldr r2, [pc, #32] ; (800fcdc ) 800fcba: 619a str r2, [r3, #24] /* initialize the hardware */ low_level_init(netif); 800fcbc: 6878 ldr r0, [r7, #4] 800fcbe: f7ff fdb9 bl 800f834 return ERR_OK; 800fcc2: 2300 movs r3, #0 } 800fcc4: 4618 mov r0, r3 800fcc6: 3708 adds r7, #8 800fcc8: 46bd mov sp, r7 800fcca: bd80 pop {r7, pc} 800fccc: 08023260 .word 0x08023260 800fcd0: 0802327c .word 0x0802327c 800fcd4: 0802328c .word 0x0802328c 800fcd8: 0801f585 .word 0x0801f585 800fcdc: 0800fac9 .word 0x0800fac9 0800fce0 : * @brief Custom Rx pbuf free callback * @param pbuf: pbuf to be freed * @retval None */ void pbuf_free_custom(struct pbuf *p) { 800fce0: b580 push {r7, lr} 800fce2: b084 sub sp, #16 800fce4: af00 add r7, sp, #0 800fce6: 6078 str r0, [r7, #4] struct pbuf_custom* custom_pbuf = (struct pbuf_custom*)p; 800fce8: 687b ldr r3, [r7, #4] 800fcea: 60fb str r3, [r7, #12] LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf); 800fcec: 68f9 ldr r1, [r7, #12] 800fcee: 4809 ldr r0, [pc, #36] ; (800fd14 ) 800fcf0: f006 ff40 bl 8016b74 /* If the Rx Buffer Pool was exhausted, signal the ethernetif_input task to * call HAL_ETH_GetRxDataBuffer to rebuild the Rx descriptors. */ if (RxAllocStatus == RX_ALLOC_ERROR) 800fcf4: 4b08 ldr r3, [pc, #32] ; (800fd18 ) 800fcf6: 781b ldrb r3, [r3, #0] 800fcf8: 2b01 cmp r3, #1 800fcfa: d107 bne.n 800fd0c { RxAllocStatus = RX_ALLOC_OK; 800fcfc: 4b06 ldr r3, [pc, #24] ; (800fd18 ) 800fcfe: 2200 movs r2, #0 800fd00: 701a strb r2, [r3, #0] osSemaphoreRelease(RxPktSemaphore); 800fd02: 4b06 ldr r3, [pc, #24] ; (800fd1c ) 800fd04: 681b ldr r3, [r3, #0] 800fd06: 4618 mov r0, r3 800fd08: f000 fc6a bl 80105e0 } } 800fd0c: bf00 nop 800fd0e: 3710 adds r7, #16 800fd10: 46bd mov sp, r7 800fd12: bd80 pop {r7, pc} 800fd14: 08026b94 .word 0x08026b94 800fd18: 2400bdc0 .word 0x2400bdc0 800fd1c: 2400bdc4 .word 0x2400bdc4 0800fd20 : * when LWIP_TIMERS == 1 and NO_SYS == 1 * @param None * @retval Current Time value */ u32_t sys_now(void) { 800fd20: b580 push {r7, lr} 800fd22: af00 add r7, sp, #0 return HAL_GetTick(); 800fd24: f7f2 fb1e bl 8002364 800fd28: 4603 mov r3, r0 } 800fd2a: 4618 mov r0, r3 800fd2c: bd80 pop {r7, pc} ... 0800fd30 : * @param ethHandle: ETH handle * @retval None */ void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle) { 800fd30: b580 push {r7, lr} 800fd32: b08e sub sp, #56 ; 0x38 800fd34: af00 add r7, sp, #0 800fd36: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800fd38: f107 0324 add.w r3, r7, #36 ; 0x24 800fd3c: 2200 movs r2, #0 800fd3e: 601a str r2, [r3, #0] 800fd40: 605a str r2, [r3, #4] 800fd42: 609a str r2, [r3, #8] 800fd44: 60da str r2, [r3, #12] 800fd46: 611a str r2, [r3, #16] if(ethHandle->Instance==ETH) 800fd48: 687b ldr r3, [r7, #4] 800fd4a: 681b ldr r3, [r3, #0] 800fd4c: 4a4d ldr r2, [pc, #308] ; (800fe84 ) 800fd4e: 4293 cmp r3, r2 800fd50: f040 8093 bne.w 800fe7a { /* USER CODE BEGIN ETH_MspInit 0 */ /* USER CODE END ETH_MspInit 0 */ /* Enable Peripheral clock */ __HAL_RCC_ETH1MAC_CLK_ENABLE(); 800fd54: 4b4c ldr r3, [pc, #304] ; (800fe88 ) 800fd56: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 800fd5a: 4a4b ldr r2, [pc, #300] ; (800fe88 ) 800fd5c: f443 4300 orr.w r3, r3, #32768 ; 0x8000 800fd60: f8c2 30d8 str.w r3, [r2, #216] ; 0xd8 800fd64: 4b48 ldr r3, [pc, #288] ; (800fe88 ) 800fd66: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 800fd6a: f403 4300 and.w r3, r3, #32768 ; 0x8000 800fd6e: 623b str r3, [r7, #32] 800fd70: 6a3b ldr r3, [r7, #32] __HAL_RCC_ETH1TX_CLK_ENABLE(); 800fd72: 4b45 ldr r3, [pc, #276] ; (800fe88 ) 800fd74: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 800fd78: 4a43 ldr r2, [pc, #268] ; (800fe88 ) 800fd7a: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800fd7e: f8c2 30d8 str.w r3, [r2, #216] ; 0xd8 800fd82: 4b41 ldr r3, [pc, #260] ; (800fe88 ) 800fd84: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 800fd88: f403 3380 and.w r3, r3, #65536 ; 0x10000 800fd8c: 61fb str r3, [r7, #28] 800fd8e: 69fb ldr r3, [r7, #28] __HAL_RCC_ETH1RX_CLK_ENABLE(); 800fd90: 4b3d ldr r3, [pc, #244] ; (800fe88 ) 800fd92: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 800fd96: 4a3c ldr r2, [pc, #240] ; (800fe88 ) 800fd98: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800fd9c: f8c2 30d8 str.w r3, [r2, #216] ; 0xd8 800fda0: 4b39 ldr r3, [pc, #228] ; (800fe88 ) 800fda2: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 800fda6: f403 3300 and.w r3, r3, #131072 ; 0x20000 800fdaa: 61bb str r3, [r7, #24] 800fdac: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 800fdae: 4b36 ldr r3, [pc, #216] ; (800fe88 ) 800fdb0: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 800fdb4: 4a34 ldr r2, [pc, #208] ; (800fe88 ) 800fdb6: f043 0304 orr.w r3, r3, #4 800fdba: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 800fdbe: 4b32 ldr r3, [pc, #200] ; (800fe88 ) 800fdc0: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 800fdc4: f003 0304 and.w r3, r3, #4 800fdc8: 617b str r3, [r7, #20] 800fdca: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 800fdcc: 4b2e ldr r3, [pc, #184] ; (800fe88 ) 800fdce: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 800fdd2: 4a2d ldr r2, [pc, #180] ; (800fe88 ) 800fdd4: f043 0301 orr.w r3, r3, #1 800fdd8: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 800fddc: 4b2a ldr r3, [pc, #168] ; (800fe88 ) 800fdde: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 800fde2: f003 0301 and.w r3, r3, #1 800fde6: 613b str r3, [r7, #16] 800fde8: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 800fdea: 4b27 ldr r3, [pc, #156] ; (800fe88 ) 800fdec: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 800fdf0: 4a25 ldr r2, [pc, #148] ; (800fe88 ) 800fdf2: f043 0302 orr.w r3, r3, #2 800fdf6: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 800fdfa: 4b23 ldr r3, [pc, #140] ; (800fe88 ) 800fdfc: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 800fe00: f003 0302 and.w r3, r3, #2 800fe04: 60fb str r3, [r7, #12] 800fe06: 68fb ldr r3, [r7, #12] PB13 ------> ETH_TXD1 PA7 ------> ETH_CRS_DV PB11 ------> ETH_TX_EN PB12 ------> ETH_TXD0 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; 800fe08: 2332 movs r3, #50 ; 0x32 800fe0a: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800fe0c: 2302 movs r3, #2 800fe0e: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 800fe10: 2300 movs r3, #0 800fe12: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800fe14: 2303 movs r3, #3 800fe16: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 800fe18: 230b movs r3, #11 800fe1a: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800fe1c: f107 0324 add.w r3, r7, #36 ; 0x24 800fe20: 4619 mov r1, r3 800fe22: 481a ldr r0, [pc, #104] ; (800fe8c ) 800fe24: f7f6 fcc4 bl 80067b0 GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; 800fe28: 2386 movs r3, #134 ; 0x86 800fe2a: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800fe2c: 2302 movs r3, #2 800fe2e: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 800fe30: 2300 movs r3, #0 800fe32: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800fe34: 2303 movs r3, #3 800fe36: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 800fe38: 230b movs r3, #11 800fe3a: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800fe3c: f107 0324 add.w r3, r7, #36 ; 0x24 800fe40: 4619 mov r1, r3 800fe42: 4813 ldr r0, [pc, #76] ; (800fe90 ) 800fe44: f7f6 fcb4 bl 80067b0 GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_11|GPIO_PIN_12; 800fe48: f44f 5360 mov.w r3, #14336 ; 0x3800 800fe4c: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800fe4e: 2302 movs r3, #2 800fe50: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 800fe52: 2300 movs r3, #0 800fe54: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800fe56: 2303 movs r3, #3 800fe58: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 800fe5a: 230b movs r3, #11 800fe5c: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800fe5e: f107 0324 add.w r3, r7, #36 ; 0x24 800fe62: 4619 mov r1, r3 800fe64: 480b ldr r0, [pc, #44] ; (800fe94 ) 800fe66: f7f6 fca3 bl 80067b0 /* Peripheral interrupt init */ HAL_NVIC_SetPriority(ETH_IRQn, 5, 0); 800fe6a: 2200 movs r2, #0 800fe6c: 2105 movs r1, #5 800fe6e: 203d movs r0, #61 ; 0x3d 800fe70: f7f2 fb74 bl 800255c HAL_NVIC_EnableIRQ(ETH_IRQn); 800fe74: 203d movs r0, #61 ; 0x3d 800fe76: f7f2 fb8b bl 8002590 /* USER CODE BEGIN ETH_MspInit 1 */ /* USER CODE END ETH_MspInit 1 */ } } 800fe7a: bf00 nop 800fe7c: 3738 adds r7, #56 ; 0x38 800fe7e: 46bd mov sp, r7 800fe80: bd80 pop {r7, pc} 800fe82: bf00 nop 800fe84: 40028000 .word 0x40028000 800fe88: 58024400 .word 0x58024400 800fe8c: 58020800 .word 0x58020800 800fe90: 58020000 .word 0x58020000 800fe94: 58020400 .word 0x58020400 0800fe98 : * @brief Initializes the MDIO interface GPIO and clocks. * @param None * @retval 0 if OK, -1 if ERROR */ int32_t ETH_PHY_IO_Init(void) { 800fe98: b580 push {r7, lr} 800fe9a: af00 add r7, sp, #0 /* We assume that MDIO GPIO configuration is already done in the ETH_MspInit() else it should be done here */ /* Configure the MDIO Clock */ HAL_ETH_SetMDIOClockRange(&heth); 800fe9c: 4802 ldr r0, [pc, #8] ; (800fea8 ) 800fe9e: f7f5 f847 bl 8004f30 return 0; 800fea2: 2300 movs r3, #0 } 800fea4: 4618 mov r0, r3 800fea6: bd80 pop {r7, pc} 800fea8: 2400bdcc .word 0x2400bdcc 0800feac : * @brief De-Initializes the MDIO interface . * @param None * @retval 0 if OK, -1 if ERROR */ int32_t ETH_PHY_IO_DeInit (void) { 800feac: b480 push {r7} 800feae: af00 add r7, sp, #0 return 0; 800feb0: 2300 movs r3, #0 } 800feb2: 4618 mov r0, r3 800feb4: 46bd mov sp, r7 800feb6: f85d 7b04 ldr.w r7, [sp], #4 800feba: 4770 bx lr 0800febc : * @param RegAddr: PHY register address * @param pRegVal: pointer to hold the register value * @retval 0 if OK -1 if Error */ int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal) { 800febc: b580 push {r7, lr} 800febe: b084 sub sp, #16 800fec0: af00 add r7, sp, #0 800fec2: 60f8 str r0, [r7, #12] 800fec4: 60b9 str r1, [r7, #8] 800fec6: 607a str r2, [r7, #4] if(HAL_ETH_ReadPHYRegister(&heth, DevAddr, RegAddr, pRegVal) != HAL_OK) 800fec8: 687b ldr r3, [r7, #4] 800feca: 68ba ldr r2, [r7, #8] 800fecc: 68f9 ldr r1, [r7, #12] 800fece: 4807 ldr r0, [pc, #28] ; (800feec ) 800fed0: f7f4 fd98 bl 8004a04 800fed4: 4603 mov r3, r0 800fed6: 2b00 cmp r3, #0 800fed8: d002 beq.n 800fee0 { return -1; 800feda: f04f 33ff mov.w r3, #4294967295 800fede: e000 b.n 800fee2 } return 0; 800fee0: 2300 movs r3, #0 } 800fee2: 4618 mov r0, r3 800fee4: 3710 adds r7, #16 800fee6: 46bd mov sp, r7 800fee8: bd80 pop {r7, pc} 800feea: bf00 nop 800feec: 2400bdcc .word 0x2400bdcc 0800fef0 : * @param RegAddr: PHY register address * @param RegVal: Value to be written * @retval 0 if OK -1 if Error */ int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal) { 800fef0: b580 push {r7, lr} 800fef2: b084 sub sp, #16 800fef4: af00 add r7, sp, #0 800fef6: 60f8 str r0, [r7, #12] 800fef8: 60b9 str r1, [r7, #8] 800fefa: 607a str r2, [r7, #4] if(HAL_ETH_WritePHYRegister(&heth, DevAddr, RegAddr, RegVal) != HAL_OK) 800fefc: 687b ldr r3, [r7, #4] 800fefe: 68ba ldr r2, [r7, #8] 800ff00: 68f9 ldr r1, [r7, #12] 800ff02: 4807 ldr r0, [pc, #28] ; (800ff20 ) 800ff04: f7f4 fdd2 bl 8004aac 800ff08: 4603 mov r3, r0 800ff0a: 2b00 cmp r3, #0 800ff0c: d002 beq.n 800ff14 { return -1; 800ff0e: f04f 33ff mov.w r3, #4294967295 800ff12: e000 b.n 800ff16 } return 0; 800ff14: 2300 movs r3, #0 } 800ff16: 4618 mov r0, r3 800ff18: 3710 adds r7, #16 800ff1a: 46bd mov sp, r7 800ff1c: bd80 pop {r7, pc} 800ff1e: bf00 nop 800ff20: 2400bdcc .word 0x2400bdcc 0800ff24 : /** * @brief Get the time in millisecons used for internal PHY driver process. * @retval Time value */ int32_t ETH_PHY_IO_GetTick(void) { 800ff24: b580 push {r7, lr} 800ff26: af00 add r7, sp, #0 return HAL_GetTick(); 800ff28: f7f2 fa1c bl 8002364 800ff2c: 4603 mov r3, r0 } 800ff2e: 4618 mov r0, r3 800ff30: bd80 pop {r7, pc} ... 0800ff34 : * @brief Check the ETH link state then update ETH driver and netif link accordingly. * @retval None */ void ethernet_link_thread(void const * argument) { 800ff34: b580 push {r7, lr} 800ff36: b0a0 sub sp, #128 ; 0x80 800ff38: af00 add r7, sp, #0 800ff3a: 6078 str r0, [r7, #4] ETH_MACConfigTypeDef MACConf = {0}; 800ff3c: f107 0308 add.w r3, r7, #8 800ff40: 2264 movs r2, #100 ; 0x64 800ff42: 2100 movs r1, #0 800ff44: 4618 mov r0, r3 800ff46: f011 fecb bl 8021ce0 int32_t PHYLinkState = 0; 800ff4a: 2300 movs r3, #0 800ff4c: 673b str r3, [r7, #112] ; 0x70 uint32_t linkchanged = 0U, speed = 0U, duplex = 0U; 800ff4e: 2300 movs r3, #0 800ff50: 67fb str r3, [r7, #124] ; 0x7c 800ff52: 2300 movs r3, #0 800ff54: 67bb str r3, [r7, #120] ; 0x78 800ff56: 2300 movs r3, #0 800ff58: 677b str r3, [r7, #116] ; 0x74 struct netif *netif = (struct netif *) argument; 800ff5a: 687b ldr r3, [r7, #4] 800ff5c: 66fb str r3, [r7, #108] ; 0x6c /* USER CODE END ETH link init */ for(;;) { PHYLinkState = LAN8742_GetLinkState(&LAN8742); 800ff5e: 483a ldr r0, [pc, #232] ; (8010048 ) 800ff60: f7f2 f929 bl 80021b6 800ff64: 6738 str r0, [r7, #112] ; 0x70 if(netif_is_link_up(netif) && (PHYLinkState <= LAN8742_STATUS_LINK_DOWN)) 800ff66: 6efb ldr r3, [r7, #108] ; 0x6c 800ff68: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 800ff6c: 089b lsrs r3, r3, #2 800ff6e: f003 0301 and.w r3, r3, #1 800ff72: b2db uxtb r3, r3 800ff74: 2b00 cmp r3, #0 800ff76: d00c beq.n 800ff92 800ff78: 6f3b ldr r3, [r7, #112] ; 0x70 800ff7a: 2b01 cmp r3, #1 800ff7c: dc09 bgt.n 800ff92 { HAL_ETH_Stop_IT(&heth); 800ff7e: 4833 ldr r0, [pc, #204] ; (801004c ) 800ff80: f7f4 f9c0 bl 8004304 netif_set_down(netif); 800ff84: 6ef8 ldr r0, [r7, #108] ; 0x6c 800ff86: f007 f96f bl 8017268 netif_set_link_down(netif); 800ff8a: 6ef8 ldr r0, [r7, #108] ; 0x6c 800ff8c: f007 f9d2 bl 8017334 800ff90: e055 b.n 801003e } else if(!netif_is_link_up(netif) && (PHYLinkState > LAN8742_STATUS_LINK_DOWN)) 800ff92: 6efb ldr r3, [r7, #108] ; 0x6c 800ff94: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 800ff98: f003 0304 and.w r3, r3, #4 800ff9c: 2b00 cmp r3, #0 800ff9e: d14e bne.n 801003e 800ffa0: 6f3b ldr r3, [r7, #112] ; 0x70 800ffa2: 2b01 cmp r3, #1 800ffa4: dd4b ble.n 801003e { switch (PHYLinkState) 800ffa6: 6f3b ldr r3, [r7, #112] ; 0x70 800ffa8: 3b02 subs r3, #2 800ffaa: 2b03 cmp r3, #3 800ffac: d82a bhi.n 8010004 800ffae: a201 add r2, pc, #4 ; (adr r2, 800ffb4 ) 800ffb0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ffb4: 0800ffc5 .word 0x0800ffc5 800ffb8: 0800ffd7 .word 0x0800ffd7 800ffbc: 0800ffe7 .word 0x0800ffe7 800ffc0: 0800fff7 .word 0x0800fff7 { case LAN8742_STATUS_100MBITS_FULLDUPLEX: duplex = ETH_FULLDUPLEX_MODE; 800ffc4: f44f 5300 mov.w r3, #8192 ; 0x2000 800ffc8: 677b str r3, [r7, #116] ; 0x74 speed = ETH_SPEED_100M; 800ffca: f44f 4380 mov.w r3, #16384 ; 0x4000 800ffce: 67bb str r3, [r7, #120] ; 0x78 linkchanged = 1; 800ffd0: 2301 movs r3, #1 800ffd2: 67fb str r3, [r7, #124] ; 0x7c break; 800ffd4: e017 b.n 8010006 case LAN8742_STATUS_100MBITS_HALFDUPLEX: duplex = ETH_HALFDUPLEX_MODE; 800ffd6: 2300 movs r3, #0 800ffd8: 677b str r3, [r7, #116] ; 0x74 speed = ETH_SPEED_100M; 800ffda: f44f 4380 mov.w r3, #16384 ; 0x4000 800ffde: 67bb str r3, [r7, #120] ; 0x78 linkchanged = 1; 800ffe0: 2301 movs r3, #1 800ffe2: 67fb str r3, [r7, #124] ; 0x7c break; 800ffe4: e00f b.n 8010006 case LAN8742_STATUS_10MBITS_FULLDUPLEX: duplex = ETH_FULLDUPLEX_MODE; 800ffe6: f44f 5300 mov.w r3, #8192 ; 0x2000 800ffea: 677b str r3, [r7, #116] ; 0x74 speed = ETH_SPEED_10M; 800ffec: 2300 movs r3, #0 800ffee: 67bb str r3, [r7, #120] ; 0x78 linkchanged = 1; 800fff0: 2301 movs r3, #1 800fff2: 67fb str r3, [r7, #124] ; 0x7c break; 800fff4: e007 b.n 8010006 case LAN8742_STATUS_10MBITS_HALFDUPLEX: duplex = ETH_HALFDUPLEX_MODE; 800fff6: 2300 movs r3, #0 800fff8: 677b str r3, [r7, #116] ; 0x74 speed = ETH_SPEED_10M; 800fffa: 2300 movs r3, #0 800fffc: 67bb str r3, [r7, #120] ; 0x78 linkchanged = 1; 800fffe: 2301 movs r3, #1 8010000: 67fb str r3, [r7, #124] ; 0x7c break; 8010002: e000 b.n 8010006 default: break; 8010004: bf00 nop } if(linkchanged) 8010006: 6ffb ldr r3, [r7, #124] ; 0x7c 8010008: 2b00 cmp r3, #0 801000a: d018 beq.n 801003e { /* Get MAC Config MAC */ HAL_ETH_GetMACConfig(&heth, &MACConf); 801000c: f107 0308 add.w r3, r7, #8 8010010: 4619 mov r1, r3 8010012: 480e ldr r0, [pc, #56] ; (801004c ) 8010014: f7f4 fd9e bl 8004b54 MACConf.DuplexMode = duplex; 8010018: 6f7b ldr r3, [r7, #116] ; 0x74 801001a: 623b str r3, [r7, #32] MACConf.Speed = speed; 801001c: 6fbb ldr r3, [r7, #120] ; 0x78 801001e: 61fb str r3, [r7, #28] HAL_ETH_SetMACConfig(&heth, &MACConf); 8010020: f107 0308 add.w r3, r7, #8 8010024: 4619 mov r1, r3 8010026: 4809 ldr r0, [pc, #36] ; (801004c ) 8010028: f7f4 ff68 bl 8004efc HAL_ETH_Start_IT(&heth); 801002c: 4807 ldr r0, [pc, #28] ; (801004c ) 801002e: f7f4 f8dd bl 80041ec netif_set_up(netif); 8010032: 6ef8 ldr r0, [r7, #108] ; 0x6c 8010034: f007 f8ac bl 8017190 netif_set_link_up(netif); 8010038: 6ef8 ldr r0, [r7, #108] ; 0x6c 801003a: f007 f947 bl 80172cc /* USER CODE BEGIN ETH link Thread core code for User BSP */ /* USER CODE END ETH link Thread core code for User BSP */ osDelay(100); 801003e: 2064 movs r0, #100 ; 0x64 8010040: f000 f99e bl 8010380 PHYLinkState = LAN8742_GetLinkState(&LAN8742); 8010044: e78b b.n 800ff5e 8010046: bf00 nop 8010048: 2400beb4 .word 0x2400beb4 801004c: 2400bdcc .word 0x2400bdcc 08010050 : } } void HAL_ETH_RxAllocateCallback(uint8_t **buff) { 8010050: b580 push {r7, lr} 8010052: b086 sub sp, #24 8010054: af02 add r7, sp, #8 8010056: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL ETH RxAllocateCallback */ struct pbuf_custom *p = LWIP_MEMPOOL_ALLOC(RX_POOL); 8010058: 4812 ldr r0, [pc, #72] ; (80100a4 ) 801005a: f006 fd17 bl 8016a8c 801005e: 60f8 str r0, [r7, #12] if (p) 8010060: 68fb ldr r3, [r7, #12] 8010062: 2b00 cmp r3, #0 8010064: d014 beq.n 8010090 { /* Get the buff from the struct pbuf address. */ *buff = (uint8_t *)p + offsetof(RxBuff_t, buff); 8010066: 68fb ldr r3, [r7, #12] 8010068: f103 0220 add.w r2, r3, #32 801006c: 687b ldr r3, [r7, #4] 801006e: 601a str r2, [r3, #0] p->custom_free_function = pbuf_free_custom; 8010070: 68fb ldr r3, [r7, #12] 8010072: 4a0d ldr r2, [pc, #52] ; (80100a8 ) 8010074: 611a str r2, [r3, #16] /* Initialize the struct pbuf. * This must be performed whenever a buffer's allocated because it may be * changed by lwIP or the app, e.g., pbuf_free decrements ref. */ pbuf_alloced_custom(PBUF_RAW, 0, PBUF_REF, p, *buff, ETH_RX_BUFFER_SIZE); 8010076: 687b ldr r3, [r7, #4] 8010078: 681b ldr r3, [r3, #0] 801007a: f44f 62c0 mov.w r2, #1536 ; 0x600 801007e: 9201 str r2, [sp, #4] 8010080: 9300 str r3, [sp, #0] 8010082: 68fb ldr r3, [r7, #12] 8010084: 2241 movs r2, #65 ; 0x41 8010086: 2100 movs r1, #0 8010088: 2000 movs r0, #0 801008a: f007 fb7b bl 8017784 { RxAllocStatus = RX_ALLOC_ERROR; *buff = NULL; } /* USER CODE END HAL ETH RxAllocateCallback */ } 801008e: e005 b.n 801009c RxAllocStatus = RX_ALLOC_ERROR; 8010090: 4b06 ldr r3, [pc, #24] ; (80100ac ) 8010092: 2201 movs r2, #1 8010094: 701a strb r2, [r3, #0] *buff = NULL; 8010096: 687b ldr r3, [r7, #4] 8010098: 2200 movs r2, #0 801009a: 601a str r2, [r3, #0] } 801009c: bf00 nop 801009e: 3710 adds r7, #16 80100a0: 46bd mov sp, r7 80100a2: bd80 pop {r7, pc} 80100a4: 08026b94 .word 0x08026b94 80100a8: 0800fce1 .word 0x0800fce1 80100ac: 2400bdc0 .word 0x2400bdc0 080100b0 : void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) { 80100b0: b480 push {r7} 80100b2: b08d sub sp, #52 ; 0x34 80100b4: af00 add r7, sp, #0 80100b6: 60f8 str r0, [r7, #12] 80100b8: 60b9 str r1, [r7, #8] 80100ba: 607a str r2, [r7, #4] 80100bc: 807b strh r3, [r7, #2] /* USER CODE BEGIN HAL ETH RxLinkCallback */ struct pbuf **ppStart = (struct pbuf **)pStart; 80100be: 68fb ldr r3, [r7, #12] 80100c0: 62bb str r3, [r7, #40] ; 0x28 struct pbuf **ppEnd = (struct pbuf **)pEnd; 80100c2: 68bb ldr r3, [r7, #8] 80100c4: 627b str r3, [r7, #36] ; 0x24 struct pbuf *p = NULL; 80100c6: 2300 movs r3, #0 80100c8: 62fb str r3, [r7, #44] ; 0x2c /* Get the struct pbuf from the buff address. */ p = (struct pbuf *)(buff - offsetof(RxBuff_t, buff)); 80100ca: 687b ldr r3, [r7, #4] 80100cc: 3b20 subs r3, #32 80100ce: 62fb str r3, [r7, #44] ; 0x2c p->next = NULL; 80100d0: 6afb ldr r3, [r7, #44] ; 0x2c 80100d2: 2200 movs r2, #0 80100d4: 601a str r2, [r3, #0] p->tot_len = 0; 80100d6: 6afb ldr r3, [r7, #44] ; 0x2c 80100d8: 2200 movs r2, #0 80100da: 811a strh r2, [r3, #8] p->len = Length; 80100dc: 6afb ldr r3, [r7, #44] ; 0x2c 80100de: 887a ldrh r2, [r7, #2] 80100e0: 815a strh r2, [r3, #10] /* Chain the buffer. */ if (!*ppStart) 80100e2: 6abb ldr r3, [r7, #40] ; 0x28 80100e4: 681b ldr r3, [r3, #0] 80100e6: 2b00 cmp r3, #0 80100e8: d103 bne.n 80100f2 { /* The first buffer of the packet. */ *ppStart = p; 80100ea: 6abb ldr r3, [r7, #40] ; 0x28 80100ec: 6afa ldr r2, [r7, #44] ; 0x2c 80100ee: 601a str r2, [r3, #0] 80100f0: e003 b.n 80100fa } else { /* Chain the buffer to the end of the packet. */ (*ppEnd)->next = p; 80100f2: 6a7b ldr r3, [r7, #36] ; 0x24 80100f4: 681b ldr r3, [r3, #0] 80100f6: 6afa ldr r2, [r7, #44] ; 0x2c 80100f8: 601a str r2, [r3, #0] } *ppEnd = p; 80100fa: 6a7b ldr r3, [r7, #36] ; 0x24 80100fc: 6afa ldr r2, [r7, #44] ; 0x2c 80100fe: 601a str r2, [r3, #0] /* Update the total length of all the buffers of the chain. Each pbuf in the chain should have its tot_len * set to its own length, plus the length of all the following pbufs in the chain. */ for (p = *ppStart; p != NULL; p = p->next) 8010100: 6abb ldr r3, [r7, #40] ; 0x28 8010102: 681b ldr r3, [r3, #0] 8010104: 62fb str r3, [r7, #44] ; 0x2c 8010106: e009 b.n 801011c { p->tot_len += Length; 8010108: 6afb ldr r3, [r7, #44] ; 0x2c 801010a: 891a ldrh r2, [r3, #8] 801010c: 887b ldrh r3, [r7, #2] 801010e: 4413 add r3, r2 8010110: b29a uxth r2, r3 8010112: 6afb ldr r3, [r7, #44] ; 0x2c 8010114: 811a strh r2, [r3, #8] for (p = *ppStart; p != NULL; p = p->next) 8010116: 6afb ldr r3, [r7, #44] ; 0x2c 8010118: 681b ldr r3, [r3, #0] 801011a: 62fb str r3, [r7, #44] ; 0x2c 801011c: 6afb ldr r3, [r7, #44] ; 0x2c 801011e: 2b00 cmp r3, #0 8010120: d1f2 bne.n 8010108 } /* Invalidate data cache because Rx DMA's writing to physical memory makes it stale. */ SCB_InvalidateDCache_by_Addr((uint32_t *)buff, Length); 8010122: 887b ldrh r3, [r7, #2] 8010124: 687a ldr r2, [r7, #4] 8010126: 623a str r2, [r7, #32] 8010128: 61fb str r3, [r7, #28] if ( dsize > 0 ) { 801012a: 69fb ldr r3, [r7, #28] 801012c: 2b00 cmp r3, #0 801012e: dd1d ble.n 801016c int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 8010130: 6a3b ldr r3, [r7, #32] 8010132: f003 021f and.w r2, r3, #31 8010136: 69fb ldr r3, [r7, #28] 8010138: 4413 add r3, r2 801013a: 61bb str r3, [r7, #24] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 801013c: 6a3b ldr r3, [r7, #32] 801013e: 617b str r3, [r7, #20] __ASM volatile ("dsb 0xF":::"memory"); 8010140: f3bf 8f4f dsb sy } 8010144: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8010146: 4a0d ldr r2, [pc, #52] ; (801017c ) 8010148: 697b ldr r3, [r7, #20] 801014a: f8c2 325c str.w r3, [r2, #604] ; 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 801014e: 697b ldr r3, [r7, #20] 8010150: 3320 adds r3, #32 8010152: 617b str r3, [r7, #20] op_size -= __SCB_DCACHE_LINE_SIZE; 8010154: 69bb ldr r3, [r7, #24] 8010156: 3b20 subs r3, #32 8010158: 61bb str r3, [r7, #24] } while ( op_size > 0 ); 801015a: 69bb ldr r3, [r7, #24] 801015c: 2b00 cmp r3, #0 801015e: dcf2 bgt.n 8010146 __ASM volatile ("dsb 0xF":::"memory"); 8010160: f3bf 8f4f dsb sy } 8010164: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8010166: f3bf 8f6f isb sy } 801016a: bf00 nop } 801016c: bf00 nop /* USER CODE END HAL ETH RxLinkCallback */ } 801016e: bf00 nop 8010170: 3734 adds r7, #52 ; 0x34 8010172: 46bd mov sp, r7 8010174: f85d 7b04 ldr.w r7, [sp], #4 8010178: 4770 bx lr 801017a: bf00 nop 801017c: e000ed00 .word 0xe000ed00 08010180 : void HAL_ETH_TxFreeCallback(uint32_t * buff) { 8010180: b580 push {r7, lr} 8010182: b082 sub sp, #8 8010184: af00 add r7, sp, #0 8010186: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL ETH TxFreeCallback */ pbuf_free((struct pbuf *)buff); 8010188: 6878 ldr r0, [r7, #4] 801018a: f007 fcb5 bl 8017af8 /* USER CODE END HAL ETH TxFreeCallback */ } 801018e: bf00 nop 8010190: 3708 adds r7, #8 8010192: 46bd mov sp, r7 8010194: bd80 pop {r7, pc} ... 08010198 : * @param lun : only used for USB Key Disk to add multi-lun management else the parameter must be equal to 0 * @retval Returns 0 in case of success, otherwise 1. */ uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, uint8_t lun) { 8010198: b480 push {r7} 801019a: b087 sub sp, #28 801019c: af00 add r7, sp, #0 801019e: 60f8 str r0, [r7, #12] 80101a0: 60b9 str r1, [r7, #8] 80101a2: 4613 mov r3, r2 80101a4: 71fb strb r3, [r7, #7] uint8_t ret = 1; 80101a6: 2301 movs r3, #1 80101a8: 75fb strb r3, [r7, #23] uint8_t DiskNum = 0; 80101aa: 2300 movs r3, #0 80101ac: 75bb strb r3, [r7, #22] if(disk.nbr < _VOLUMES) 80101ae: 4b1f ldr r3, [pc, #124] ; (801022c ) 80101b0: 7a5b ldrb r3, [r3, #9] 80101b2: b2db uxtb r3, r3 80101b4: 2b00 cmp r3, #0 80101b6: d131 bne.n 801021c { disk.is_initialized[disk.nbr] = 0; 80101b8: 4b1c ldr r3, [pc, #112] ; (801022c ) 80101ba: 7a5b ldrb r3, [r3, #9] 80101bc: b2db uxtb r3, r3 80101be: 461a mov r2, r3 80101c0: 4b1a ldr r3, [pc, #104] ; (801022c ) 80101c2: 2100 movs r1, #0 80101c4: 5499 strb r1, [r3, r2] disk.drv[disk.nbr] = drv; 80101c6: 4b19 ldr r3, [pc, #100] ; (801022c ) 80101c8: 7a5b ldrb r3, [r3, #9] 80101ca: b2db uxtb r3, r3 80101cc: 4a17 ldr r2, [pc, #92] ; (801022c ) 80101ce: 009b lsls r3, r3, #2 80101d0: 4413 add r3, r2 80101d2: 68fa ldr r2, [r7, #12] 80101d4: 605a str r2, [r3, #4] disk.lun[disk.nbr] = lun; 80101d6: 4b15 ldr r3, [pc, #84] ; (801022c ) 80101d8: 7a5b ldrb r3, [r3, #9] 80101da: b2db uxtb r3, r3 80101dc: 461a mov r2, r3 80101de: 4b13 ldr r3, [pc, #76] ; (801022c ) 80101e0: 4413 add r3, r2 80101e2: 79fa ldrb r2, [r7, #7] 80101e4: 721a strb r2, [r3, #8] DiskNum = disk.nbr++; 80101e6: 4b11 ldr r3, [pc, #68] ; (801022c ) 80101e8: 7a5b ldrb r3, [r3, #9] 80101ea: b2db uxtb r3, r3 80101ec: 1c5a adds r2, r3, #1 80101ee: b2d1 uxtb r1, r2 80101f0: 4a0e ldr r2, [pc, #56] ; (801022c ) 80101f2: 7251 strb r1, [r2, #9] 80101f4: 75bb strb r3, [r7, #22] path[0] = DiskNum + '0'; 80101f6: 7dbb ldrb r3, [r7, #22] 80101f8: 3330 adds r3, #48 ; 0x30 80101fa: b2da uxtb r2, r3 80101fc: 68bb ldr r3, [r7, #8] 80101fe: 701a strb r2, [r3, #0] path[1] = ':'; 8010200: 68bb ldr r3, [r7, #8] 8010202: 3301 adds r3, #1 8010204: 223a movs r2, #58 ; 0x3a 8010206: 701a strb r2, [r3, #0] path[2] = '/'; 8010208: 68bb ldr r3, [r7, #8] 801020a: 3302 adds r3, #2 801020c: 222f movs r2, #47 ; 0x2f 801020e: 701a strb r2, [r3, #0] path[3] = 0; 8010210: 68bb ldr r3, [r7, #8] 8010212: 3303 adds r3, #3 8010214: 2200 movs r2, #0 8010216: 701a strb r2, [r3, #0] ret = 0; 8010218: 2300 movs r3, #0 801021a: 75fb strb r3, [r7, #23] } return ret; 801021c: 7dfb ldrb r3, [r7, #23] } 801021e: 4618 mov r0, r3 8010220: 371c adds r7, #28 8010222: 46bd mov sp, r7 8010224: f85d 7b04 ldr.w r7, [sp], #4 8010228: 4770 bx lr 801022a: bf00 nop 801022c: 2400bed4 .word 0x2400bed4 08010230 : * @param drv: pointer to the disk IO Driver structure * @param path: pointer to the logical drive path * @retval Returns 0 in case of success, otherwise 1. */ uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path) { 8010230: b580 push {r7, lr} 8010232: b082 sub sp, #8 8010234: af00 add r7, sp, #0 8010236: 6078 str r0, [r7, #4] 8010238: 6039 str r1, [r7, #0] return FATFS_LinkDriverEx(drv, path, 0); 801023a: 2200 movs r2, #0 801023c: 6839 ldr r1, [r7, #0] 801023e: 6878 ldr r0, [r7, #4] 8010240: f7ff ffaa bl 8010198 8010244: 4603 mov r3, r0 } 8010246: 4618 mov r0, r3 8010248: 3708 adds r7, #8 801024a: 46bd mov sp, r7 801024c: bd80 pop {r7, pc} 0801024e : extern void xPortSysTickHandler(void); /* Convert from CMSIS type osPriority to FreeRTOS priority number */ static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority) { 801024e: b480 push {r7} 8010250: b085 sub sp, #20 8010252: af00 add r7, sp, #0 8010254: 4603 mov r3, r0 8010256: 80fb strh r3, [r7, #6] unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY; 8010258: 2300 movs r3, #0 801025a: 60fb str r3, [r7, #12] if (priority != osPriorityError) { 801025c: f9b7 3006 ldrsh.w r3, [r7, #6] 8010260: 2b84 cmp r3, #132 ; 0x84 8010262: d005 beq.n 8010270 fpriority += (priority - osPriorityIdle); 8010264: f9b7 2006 ldrsh.w r2, [r7, #6] 8010268: 68fb ldr r3, [r7, #12] 801026a: 4413 add r3, r2 801026c: 3303 adds r3, #3 801026e: 60fb str r3, [r7, #12] } return fpriority; 8010270: 68fb ldr r3, [r7, #12] } 8010272: 4618 mov r0, r3 8010274: 3714 adds r7, #20 8010276: 46bd mov sp, r7 8010278: f85d 7b04 ldr.w r7, [sp], #4 801027c: 4770 bx lr 0801027e : #endif /* Determine whether we are in thread mode or handler mode. */ static int inHandlerMode (void) { 801027e: b480 push {r7} 8010280: b083 sub sp, #12 8010282: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8010284: f3ef 8305 mrs r3, IPSR 8010288: 607b str r3, [r7, #4] return(result); 801028a: 687b ldr r3, [r7, #4] return __get_IPSR() != 0; 801028c: 2b00 cmp r3, #0 801028e: bf14 ite ne 8010290: 2301 movne r3, #1 8010292: 2300 moveq r3, #0 8010294: b2db uxtb r3, r3 } 8010296: 4618 mov r0, r3 8010298: 370c adds r7, #12 801029a: 46bd mov sp, r7 801029c: f85d 7b04 ldr.w r7, [sp], #4 80102a0: 4770 bx lr 080102a2 : * @param argument pointer that is passed to the thread function as start argument. * @retval status code that indicates the execution status of the function * @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. */ osStatus osKernelStart (void) { 80102a2: b580 push {r7, lr} 80102a4: af00 add r7, sp, #0 vTaskStartScheduler(); 80102a6: f001 fd97 bl 8011dd8 return osOK; 80102aa: 2300 movs r3, #0 } 80102ac: 4618 mov r0, r3 80102ae: bd80 pop {r7, pc} 080102b0 : * (1) RTOS is started * (-1) if this feature is disabled in FreeRTOSConfig.h * @note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. */ int32_t osKernelRunning(void) { 80102b0: b580 push {r7, lr} 80102b2: af00 add r7, sp, #0 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) 80102b4: f002 fa28 bl 8012708 80102b8: 4603 mov r3, r0 80102ba: 2b01 cmp r3, #1 80102bc: d101 bne.n 80102c2 return 0; 80102be: 2300 movs r3, #0 80102c0: e000 b.n 80102c4 else return 1; 80102c2: 2301 movs r3, #1 #else return (-1); #endif } 80102c4: 4618 mov r0, r3 80102c6: bd80 pop {r7, pc} 080102c8 : * @param None * @retval None * @note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. */ uint32_t osKernelSysTick(void) { 80102c8: b580 push {r7, lr} 80102ca: af00 add r7, sp, #0 if (inHandlerMode()) { 80102cc: f7ff ffd7 bl 801027e 80102d0: 4603 mov r3, r0 80102d2: 2b00 cmp r3, #0 80102d4: d003 beq.n 80102de return xTaskGetTickCountFromISR(); 80102d6: f001 fe9f bl 8012018 80102da: 4603 mov r3, r0 80102dc: e002 b.n 80102e4 } else { return xTaskGetTickCount(); 80102de: f001 fe8b bl 8011ff8 80102e2: 4603 mov r3, r0 } } 80102e4: 4618 mov r0, r3 80102e6: bd80 pop {r7, pc} 080102e8 : * @param argument pointer that is passed to the thread function as start argument. * @retval thread ID for reference by other functions or NULL in case of error. * @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. */ osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) { 80102e8: b5f0 push {r4, r5, r6, r7, lr} 80102ea: b089 sub sp, #36 ; 0x24 80102ec: af04 add r7, sp, #16 80102ee: 6078 str r0, [r7, #4] 80102f0: 6039 str r1, [r7, #0] TaskHandle_t handle; #if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) { 80102f2: 687b ldr r3, [r7, #4] 80102f4: 695b ldr r3, [r3, #20] 80102f6: 2b00 cmp r3, #0 80102f8: d020 beq.n 801033c 80102fa: 687b ldr r3, [r7, #4] 80102fc: 699b ldr r3, [r3, #24] 80102fe: 2b00 cmp r3, #0 8010300: d01c beq.n 801033c handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, 8010302: 687b ldr r3, [r7, #4] 8010304: 685c ldr r4, [r3, #4] 8010306: 687b ldr r3, [r7, #4] 8010308: 681d ldr r5, [r3, #0] thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), 801030a: 687b ldr r3, [r7, #4] 801030c: 691e ldr r6, [r3, #16] 801030e: 687b ldr r3, [r7, #4] 8010310: f9b3 3008 ldrsh.w r3, [r3, #8] handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, 8010314: 4618 mov r0, r3 8010316: f7ff ff9a bl 801024e 801031a: 4601 mov r1, r0 thread_def->buffer, thread_def->controlblock); 801031c: 687b ldr r3, [r7, #4] 801031e: 695b ldr r3, [r3, #20] 8010320: 687a ldr r2, [r7, #4] 8010322: 6992 ldr r2, [r2, #24] handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, 8010324: 9202 str r2, [sp, #8] 8010326: 9301 str r3, [sp, #4] 8010328: 9100 str r1, [sp, #0] 801032a: 683b ldr r3, [r7, #0] 801032c: 4632 mov r2, r6 801032e: 4629 mov r1, r5 8010330: 4620 mov r0, r4 8010332: f001 fb81 bl 8011a38 8010336: 4603 mov r3, r0 8010338: 60fb str r3, [r7, #12] 801033a: e01c b.n 8010376 } else { if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, 801033c: 687b ldr r3, [r7, #4] 801033e: 685c ldr r4, [r3, #4] 8010340: 687b ldr r3, [r7, #4] 8010342: 681d ldr r5, [r3, #0] thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), 8010344: 687b ldr r3, [r7, #4] 8010346: 691b ldr r3, [r3, #16] if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, 8010348: b29e uxth r6, r3 thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), 801034a: 687b ldr r3, [r7, #4] 801034c: f9b3 3008 ldrsh.w r3, [r3, #8] if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, 8010350: 4618 mov r0, r3 8010352: f7ff ff7c bl 801024e 8010356: 4602 mov r2, r0 8010358: f107 030c add.w r3, r7, #12 801035c: 9301 str r3, [sp, #4] 801035e: 9200 str r2, [sp, #0] 8010360: 683b ldr r3, [r7, #0] 8010362: 4632 mov r2, r6 8010364: 4629 mov r1, r5 8010366: 4620 mov r0, r4 8010368: f001 fbc3 bl 8011af2 801036c: 4603 mov r3, r0 801036e: 2b01 cmp r3, #1 8010370: d001 beq.n 8010376 &handle) != pdPASS) { return NULL; 8010372: 2300 movs r3, #0 8010374: e000 b.n 8010378 &handle) != pdPASS) { return NULL; } #endif return handle; 8010376: 68fb ldr r3, [r7, #12] } 8010378: 4618 mov r0, r3 801037a: 3714 adds r7, #20 801037c: 46bd mov sp, r7 801037e: bdf0 pop {r4, r5, r6, r7, pc} 08010380 : * @brief Wait for Timeout (Time Delay) * @param millisec time delay value * @retval status code that indicates the execution status of the function. */ osStatus osDelay (uint32_t millisec) { 8010380: b580 push {r7, lr} 8010382: b084 sub sp, #16 8010384: af00 add r7, sp, #0 8010386: 6078 str r0, [r7, #4] #if INCLUDE_vTaskDelay TickType_t ticks = millisec / portTICK_PERIOD_MS; 8010388: 687b ldr r3, [r7, #4] 801038a: 60fb str r3, [r7, #12] vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */ 801038c: 68fb ldr r3, [r7, #12] 801038e: 2b00 cmp r3, #0 8010390: d001 beq.n 8010396 8010392: 68fb ldr r3, [r7, #12] 8010394: e000 b.n 8010398 8010396: 2301 movs r3, #1 8010398: 4618 mov r0, r3 801039a: f001 fce9 bl 8011d70 return osOK; 801039e: 2300 movs r3, #0 #else (void) millisec; return osErrorResource; #endif } 80103a0: 4618 mov r0, r3 80103a2: 3710 adds r7, #16 80103a4: 46bd mov sp, r7 80103a6: bd80 pop {r7, pc} 080103a8 : * @param mutex_def mutex definition referenced with \ref osMutex. * @retval mutex ID for reference by other functions or NULL in case of error. * @note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. */ osMutexId osMutexCreate (const osMutexDef_t *mutex_def) { 80103a8: b580 push {r7, lr} 80103aa: b082 sub sp, #8 80103ac: af00 add r7, sp, #0 80103ae: 6078 str r0, [r7, #4] #if ( configUSE_MUTEXES == 1) #if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) if (mutex_def->controlblock != NULL) { 80103b0: 687b ldr r3, [r7, #4] 80103b2: 685b ldr r3, [r3, #4] 80103b4: 2b00 cmp r3, #0 80103b6: d007 beq.n 80103c8 return xSemaphoreCreateMutexStatic( mutex_def->controlblock ); 80103b8: 687b ldr r3, [r7, #4] 80103ba: 685b ldr r3, [r3, #4] 80103bc: 4619 mov r1, r3 80103be: 2001 movs r0, #1 80103c0: f000 fc7d bl 8010cbe 80103c4: 4603 mov r3, r0 80103c6: e003 b.n 80103d0 } else { return xSemaphoreCreateMutex(); 80103c8: 2001 movs r0, #1 80103ca: f000 fc60 bl 8010c8e 80103ce: 4603 mov r3, r0 return xSemaphoreCreateMutex(); #endif #else return NULL; #endif } 80103d0: 4618 mov r0, r3 80103d2: 3708 adds r7, #8 80103d4: 46bd mov sp, r7 80103d6: bd80 pop {r7, pc} 080103d8 : * @param millisec timeout value or 0 in case of no time-out. * @retval status code that indicates the execution status of the function. * @note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. */ osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) { 80103d8: b580 push {r7, lr} 80103da: b084 sub sp, #16 80103dc: af00 add r7, sp, #0 80103de: 6078 str r0, [r7, #4] 80103e0: 6039 str r1, [r7, #0] TickType_t ticks; portBASE_TYPE taskWoken = pdFALSE; 80103e2: 2300 movs r3, #0 80103e4: 60bb str r3, [r7, #8] if (mutex_id == NULL) { 80103e6: 687b ldr r3, [r7, #4] 80103e8: 2b00 cmp r3, #0 80103ea: d101 bne.n 80103f0 return osErrorParameter; 80103ec: 2380 movs r3, #128 ; 0x80 80103ee: e03a b.n 8010466 } ticks = 0; 80103f0: 2300 movs r3, #0 80103f2: 60fb str r3, [r7, #12] if (millisec == osWaitForever) { 80103f4: 683b ldr r3, [r7, #0] 80103f6: f1b3 3fff cmp.w r3, #4294967295 80103fa: d103 bne.n 8010404 ticks = portMAX_DELAY; 80103fc: f04f 33ff mov.w r3, #4294967295 8010400: 60fb str r3, [r7, #12] 8010402: e009 b.n 8010418 } else if (millisec != 0) { 8010404: 683b ldr r3, [r7, #0] 8010406: 2b00 cmp r3, #0 8010408: d006 beq.n 8010418 ticks = millisec / portTICK_PERIOD_MS; 801040a: 683b ldr r3, [r7, #0] 801040c: 60fb str r3, [r7, #12] if (ticks == 0) { 801040e: 68fb ldr r3, [r7, #12] 8010410: 2b00 cmp r3, #0 8010412: d101 bne.n 8010418 ticks = 1; 8010414: 2301 movs r3, #1 8010416: 60fb str r3, [r7, #12] } } if (inHandlerMode()) { 8010418: f7ff ff31 bl 801027e 801041c: 4603 mov r3, r0 801041e: 2b00 cmp r3, #0 8010420: d017 beq.n 8010452 if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) { 8010422: f107 0308 add.w r3, r7, #8 8010426: 461a mov r2, r3 8010428: 2100 movs r1, #0 801042a: 6878 ldr r0, [r7, #4] 801042c: f001 f874 bl 8011518 8010430: 4603 mov r3, r0 8010432: 2b01 cmp r3, #1 8010434: d001 beq.n 801043a return osErrorOS; 8010436: 23ff movs r3, #255 ; 0xff 8010438: e015 b.n 8010466 } portEND_SWITCHING_ISR(taskWoken); 801043a: 68bb ldr r3, [r7, #8] 801043c: 2b00 cmp r3, #0 801043e: d011 beq.n 8010464 8010440: 4b0b ldr r3, [pc, #44] ; (8010470 ) 8010442: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8010446: 601a str r2, [r3, #0] 8010448: f3bf 8f4f dsb sy 801044c: f3bf 8f6f isb sy 8010450: e008 b.n 8010464 } else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) { 8010452: 68f9 ldr r1, [r7, #12] 8010454: 6878 ldr r0, [r7, #4] 8010456: f000 ff53 bl 8011300 801045a: 4603 mov r3, r0 801045c: 2b01 cmp r3, #1 801045e: d001 beq.n 8010464 return osErrorOS; 8010460: 23ff movs r3, #255 ; 0xff 8010462: e000 b.n 8010466 } return osOK; 8010464: 2300 movs r3, #0 } 8010466: 4618 mov r0, r3 8010468: 3710 adds r7, #16 801046a: 46bd mov sp, r7 801046c: bd80 pop {r7, pc} 801046e: bf00 nop 8010470: e000ed04 .word 0xe000ed04 08010474 : * @param mutex_id mutex ID obtained by \ref osMutexCreate. * @retval status code that indicates the execution status of the function. * @note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. */ osStatus osMutexRelease (osMutexId mutex_id) { 8010474: b580 push {r7, lr} 8010476: b084 sub sp, #16 8010478: af00 add r7, sp, #0 801047a: 6078 str r0, [r7, #4] osStatus result = osOK; 801047c: 2300 movs r3, #0 801047e: 60fb str r3, [r7, #12] portBASE_TYPE taskWoken = pdFALSE; 8010480: 2300 movs r3, #0 8010482: 60bb str r3, [r7, #8] if (inHandlerMode()) { 8010484: f7ff fefb bl 801027e 8010488: 4603 mov r3, r0 801048a: 2b00 cmp r3, #0 801048c: d016 beq.n 80104bc if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) { 801048e: f107 0308 add.w r3, r7, #8 8010492: 4619 mov r1, r3 8010494: 6878 ldr r0, [r7, #4] 8010496: f000 fdc6 bl 8011026 801049a: 4603 mov r3, r0 801049c: 2b01 cmp r3, #1 801049e: d001 beq.n 80104a4 return osErrorOS; 80104a0: 23ff movs r3, #255 ; 0xff 80104a2: e017 b.n 80104d4 } portEND_SWITCHING_ISR(taskWoken); 80104a4: 68bb ldr r3, [r7, #8] 80104a6: 2b00 cmp r3, #0 80104a8: d013 beq.n 80104d2 80104aa: 4b0c ldr r3, [pc, #48] ; (80104dc ) 80104ac: f04f 5280 mov.w r2, #268435456 ; 0x10000000 80104b0: 601a str r2, [r3, #0] 80104b2: f3bf 8f4f dsb sy 80104b6: f3bf 8f6f isb sy 80104ba: e00a b.n 80104d2 } else if (xSemaphoreGive(mutex_id) != pdTRUE) 80104bc: 2300 movs r3, #0 80104be: 2200 movs r2, #0 80104c0: 2100 movs r1, #0 80104c2: 6878 ldr r0, [r7, #4] 80104c4: f000 fc16 bl 8010cf4 80104c8: 4603 mov r3, r0 80104ca: 2b01 cmp r3, #1 80104cc: d001 beq.n 80104d2 { result = osErrorOS; 80104ce: 23ff movs r3, #255 ; 0xff 80104d0: 60fb str r3, [r7, #12] } return result; 80104d2: 68fb ldr r3, [r7, #12] } 80104d4: 4618 mov r0, r3 80104d6: 3710 adds r7, #16 80104d8: 46bd mov sp, r7 80104da: bd80 pop {r7, pc} 80104dc: e000ed04 .word 0xe000ed04 080104e0 : * @param count number of available resources. * @retval semaphore ID for reference by other functions or NULL in case of error. * @note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. */ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) { 80104e0: b580 push {r7, lr} 80104e2: b086 sub sp, #24 80104e4: af02 add r7, sp, #8 80104e6: 6078 str r0, [r7, #4] 80104e8: 6039 str r1, [r7, #0] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) osSemaphoreId sema; if (semaphore_def->controlblock != NULL){ 80104ea: 687b ldr r3, [r7, #4] 80104ec: 685b ldr r3, [r3, #4] 80104ee: 2b00 cmp r3, #0 80104f0: d00f beq.n 8010512 if (count == 1) { 80104f2: 683b ldr r3, [r7, #0] 80104f4: 2b01 cmp r3, #1 80104f6: d10a bne.n 801050e return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock ); 80104f8: 687b ldr r3, [r7, #4] 80104fa: 685b ldr r3, [r3, #4] 80104fc: 2203 movs r2, #3 80104fe: 9200 str r2, [sp, #0] 8010500: 2200 movs r2, #0 8010502: 2100 movs r1, #0 8010504: 2001 movs r0, #1 8010506: f000 fad7 bl 8010ab8 801050a: 4603 mov r3, r0 801050c: e016 b.n 801053c } else { #if (configUSE_COUNTING_SEMAPHORES == 1 ) return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock ); #else return NULL; 801050e: 2300 movs r3, #0 8010510: e014 b.n 801053c #endif } } else { if (count == 1) { 8010512: 683b ldr r3, [r7, #0] 8010514: 2b01 cmp r3, #1 8010516: d110 bne.n 801053a vSemaphoreCreateBinary(sema); 8010518: 2203 movs r2, #3 801051a: 2100 movs r1, #0 801051c: 2001 movs r0, #1 801051e: f000 fb43 bl 8010ba8 8010522: 60f8 str r0, [r7, #12] 8010524: 68fb ldr r3, [r7, #12] 8010526: 2b00 cmp r3, #0 8010528: d005 beq.n 8010536 801052a: 2300 movs r3, #0 801052c: 2200 movs r2, #0 801052e: 2100 movs r1, #0 8010530: 68f8 ldr r0, [r7, #12] 8010532: f000 fbdf bl 8010cf4 return sema; 8010536: 68fb ldr r3, [r7, #12] 8010538: e000 b.n 801053c } else { #if (configUSE_COUNTING_SEMAPHORES == 1 ) return xSemaphoreCreateCounting(count, count); #else return NULL; 801053a: 2300 movs r3, #0 #else return NULL; #endif } #endif } 801053c: 4618 mov r0, r3 801053e: 3710 adds r7, #16 8010540: 46bd mov sp, r7 8010542: bd80 pop {r7, pc} 08010544 : * @param millisec timeout value or 0 in case of no time-out. * @retval number of available tokens, or -1 in case of incorrect parameters. * @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. */ int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { 8010544: b580 push {r7, lr} 8010546: b084 sub sp, #16 8010548: af00 add r7, sp, #0 801054a: 6078 str r0, [r7, #4] 801054c: 6039 str r1, [r7, #0] TickType_t ticks; portBASE_TYPE taskWoken = pdFALSE; 801054e: 2300 movs r3, #0 8010550: 60bb str r3, [r7, #8] if (semaphore_id == NULL) { 8010552: 687b ldr r3, [r7, #4] 8010554: 2b00 cmp r3, #0 8010556: d101 bne.n 801055c return osErrorParameter; 8010558: 2380 movs r3, #128 ; 0x80 801055a: e03a b.n 80105d2 } ticks = 0; 801055c: 2300 movs r3, #0 801055e: 60fb str r3, [r7, #12] if (millisec == osWaitForever) { 8010560: 683b ldr r3, [r7, #0] 8010562: f1b3 3fff cmp.w r3, #4294967295 8010566: d103 bne.n 8010570 ticks = portMAX_DELAY; 8010568: f04f 33ff mov.w r3, #4294967295 801056c: 60fb str r3, [r7, #12] 801056e: e009 b.n 8010584 } else if (millisec != 0) { 8010570: 683b ldr r3, [r7, #0] 8010572: 2b00 cmp r3, #0 8010574: d006 beq.n 8010584 ticks = millisec / portTICK_PERIOD_MS; 8010576: 683b ldr r3, [r7, #0] 8010578: 60fb str r3, [r7, #12] if (ticks == 0) { 801057a: 68fb ldr r3, [r7, #12] 801057c: 2b00 cmp r3, #0 801057e: d101 bne.n 8010584 ticks = 1; 8010580: 2301 movs r3, #1 8010582: 60fb str r3, [r7, #12] } } if (inHandlerMode()) { 8010584: f7ff fe7b bl 801027e 8010588: 4603 mov r3, r0 801058a: 2b00 cmp r3, #0 801058c: d017 beq.n 80105be if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) { 801058e: f107 0308 add.w r3, r7, #8 8010592: 461a mov r2, r3 8010594: 2100 movs r1, #0 8010596: 6878 ldr r0, [r7, #4] 8010598: f000 ffbe bl 8011518 801059c: 4603 mov r3, r0 801059e: 2b01 cmp r3, #1 80105a0: d001 beq.n 80105a6 return osErrorOS; 80105a2: 23ff movs r3, #255 ; 0xff 80105a4: e015 b.n 80105d2 } portEND_SWITCHING_ISR(taskWoken); 80105a6: 68bb ldr r3, [r7, #8] 80105a8: 2b00 cmp r3, #0 80105aa: d011 beq.n 80105d0 80105ac: 4b0b ldr r3, [pc, #44] ; (80105dc ) 80105ae: f04f 5280 mov.w r2, #268435456 ; 0x10000000 80105b2: 601a str r2, [r3, #0] 80105b4: f3bf 8f4f dsb sy 80105b8: f3bf 8f6f isb sy 80105bc: e008 b.n 80105d0 } else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) { 80105be: 68f9 ldr r1, [r7, #12] 80105c0: 6878 ldr r0, [r7, #4] 80105c2: f000 fe9d bl 8011300 80105c6: 4603 mov r3, r0 80105c8: 2b01 cmp r3, #1 80105ca: d001 beq.n 80105d0 return osErrorOS; 80105cc: 23ff movs r3, #255 ; 0xff 80105ce: e000 b.n 80105d2 } return osOK; 80105d0: 2300 movs r3, #0 } 80105d2: 4618 mov r0, r3 80105d4: 3710 adds r7, #16 80105d6: 46bd mov sp, r7 80105d8: bd80 pop {r7, pc} 80105da: bf00 nop 80105dc: e000ed04 .word 0xe000ed04 080105e0 : * @param semaphore_id semaphore object referenced with \ref osSemaphore. * @retval status code that indicates the execution status of the function. * @note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. */ osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) { 80105e0: b580 push {r7, lr} 80105e2: b084 sub sp, #16 80105e4: af00 add r7, sp, #0 80105e6: 6078 str r0, [r7, #4] osStatus result = osOK; 80105e8: 2300 movs r3, #0 80105ea: 60fb str r3, [r7, #12] portBASE_TYPE taskWoken = pdFALSE; 80105ec: 2300 movs r3, #0 80105ee: 60bb str r3, [r7, #8] if (inHandlerMode()) { 80105f0: f7ff fe45 bl 801027e 80105f4: 4603 mov r3, r0 80105f6: 2b00 cmp r3, #0 80105f8: d016 beq.n 8010628 if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) { 80105fa: f107 0308 add.w r3, r7, #8 80105fe: 4619 mov r1, r3 8010600: 6878 ldr r0, [r7, #4] 8010602: f000 fd10 bl 8011026 8010606: 4603 mov r3, r0 8010608: 2b01 cmp r3, #1 801060a: d001 beq.n 8010610 return osErrorOS; 801060c: 23ff movs r3, #255 ; 0xff 801060e: e017 b.n 8010640 } portEND_SWITCHING_ISR(taskWoken); 8010610: 68bb ldr r3, [r7, #8] 8010612: 2b00 cmp r3, #0 8010614: d013 beq.n 801063e 8010616: 4b0c ldr r3, [pc, #48] ; (8010648 ) 8010618: f04f 5280 mov.w r2, #268435456 ; 0x10000000 801061c: 601a str r2, [r3, #0] 801061e: f3bf 8f4f dsb sy 8010622: f3bf 8f6f isb sy 8010626: e00a b.n 801063e } else { if (xSemaphoreGive(semaphore_id) != pdTRUE) { 8010628: 2300 movs r3, #0 801062a: 2200 movs r2, #0 801062c: 2100 movs r1, #0 801062e: 6878 ldr r0, [r7, #4] 8010630: f000 fb60 bl 8010cf4 8010634: 4603 mov r3, r0 8010636: 2b01 cmp r3, #1 8010638: d001 beq.n 801063e result = osErrorOS; 801063a: 23ff movs r3, #255 ; 0xff 801063c: 60fb str r3, [r7, #12] } } return result; 801063e: 68fb ldr r3, [r7, #12] } 8010640: 4618 mov r0, r3 8010642: 3710 adds r7, #16 8010644: 46bd mov sp, r7 8010646: bd80 pop {r7, pc} 8010648: e000ed04 .word 0xe000ed04 0801064c : * @param semaphore_id semaphore object referenced with \ref osSemaphore. * @retval status code that indicates the execution status of the function. * @note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. */ osStatus osSemaphoreDelete (osSemaphoreId semaphore_id) { 801064c: b580 push {r7, lr} 801064e: b082 sub sp, #8 8010650: af00 add r7, sp, #0 8010652: 6078 str r0, [r7, #4] if (inHandlerMode()) { 8010654: f7ff fe13 bl 801027e 8010658: 4603 mov r3, r0 801065a: 2b00 cmp r3, #0 801065c: d001 beq.n 8010662 return osErrorISR; 801065e: 2382 movs r3, #130 ; 0x82 8010660: e003 b.n 801066a } vSemaphoreDelete(semaphore_id); 8010662: 6878 ldr r0, [r7, #4] 8010664: f001 f814 bl 8011690 return osOK; 8010668: 2300 movs r3, #0 } 801066a: 4618 mov r0, r3 801066c: 3708 adds r7, #8 801066e: 46bd mov sp, r7 8010670: bd80 pop {r7, pc} 08010672 : * @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. * @retval message queue ID for reference by other functions or NULL in case of error. * @note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. */ osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { 8010672: b590 push {r4, r7, lr} 8010674: b085 sub sp, #20 8010676: af02 add r7, sp, #8 8010678: 6078 str r0, [r7, #4] 801067a: 6039 str r1, [r7, #0] (void) thread_id; #if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) { 801067c: 687b ldr r3, [r7, #4] 801067e: 689b ldr r3, [r3, #8] 8010680: 2b00 cmp r3, #0 8010682: d011 beq.n 80106a8 8010684: 687b ldr r3, [r7, #4] 8010686: 68db ldr r3, [r3, #12] 8010688: 2b00 cmp r3, #0 801068a: d00d beq.n 80106a8 return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock); 801068c: 687b ldr r3, [r7, #4] 801068e: 6818 ldr r0, [r3, #0] 8010690: 687b ldr r3, [r7, #4] 8010692: 6859 ldr r1, [r3, #4] 8010694: 687b ldr r3, [r7, #4] 8010696: 689a ldr r2, [r3, #8] 8010698: 687b ldr r3, [r7, #4] 801069a: 68db ldr r3, [r3, #12] 801069c: 2400 movs r4, #0 801069e: 9400 str r4, [sp, #0] 80106a0: f000 fa0a bl 8010ab8 80106a4: 4603 mov r3, r0 80106a6: e008 b.n 80106ba } else { return xQueueCreate(queue_def->queue_sz, queue_def->item_sz); 80106a8: 687b ldr r3, [r7, #4] 80106aa: 6818 ldr r0, [r3, #0] 80106ac: 687b ldr r3, [r7, #4] 80106ae: 685b ldr r3, [r3, #4] 80106b0: 2200 movs r2, #0 80106b2: 4619 mov r1, r3 80106b4: f000 fa78 bl 8010ba8 80106b8: 4603 mov r3, r0 #elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock); #else return xQueueCreate(queue_def->queue_sz, queue_def->item_sz); #endif } 80106ba: 4618 mov r0, r3 80106bc: 370c adds r7, #12 80106be: 46bd mov sp, r7 80106c0: bd90 pop {r4, r7, pc} ... 080106c4 : * @param millisec timeout value or 0 in case of no time-out. * @retval status code that indicates the execution status of the function. * @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. */ osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { 80106c4: b580 push {r7, lr} 80106c6: b086 sub sp, #24 80106c8: af00 add r7, sp, #0 80106ca: 60f8 str r0, [r7, #12] 80106cc: 60b9 str r1, [r7, #8] 80106ce: 607a str r2, [r7, #4] portBASE_TYPE taskWoken = pdFALSE; 80106d0: 2300 movs r3, #0 80106d2: 613b str r3, [r7, #16] TickType_t ticks; ticks = millisec / portTICK_PERIOD_MS; 80106d4: 687b ldr r3, [r7, #4] 80106d6: 617b str r3, [r7, #20] if (ticks == 0) { 80106d8: 697b ldr r3, [r7, #20] 80106da: 2b00 cmp r3, #0 80106dc: d101 bne.n 80106e2 ticks = 1; 80106de: 2301 movs r3, #1 80106e0: 617b str r3, [r7, #20] } if (inHandlerMode()) { 80106e2: f7ff fdcc bl 801027e 80106e6: 4603 mov r3, r0 80106e8: 2b00 cmp r3, #0 80106ea: d018 beq.n 801071e if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) { 80106ec: f107 0210 add.w r2, r7, #16 80106f0: f107 0108 add.w r1, r7, #8 80106f4: 2300 movs r3, #0 80106f6: 68f8 ldr r0, [r7, #12] 80106f8: f000 fbfa bl 8010ef0 80106fc: 4603 mov r3, r0 80106fe: 2b01 cmp r3, #1 8010700: d001 beq.n 8010706 return osErrorOS; 8010702: 23ff movs r3, #255 ; 0xff 8010704: e018 b.n 8010738 } portEND_SWITCHING_ISR(taskWoken); 8010706: 693b ldr r3, [r7, #16] 8010708: 2b00 cmp r3, #0 801070a: d014 beq.n 8010736 801070c: 4b0c ldr r3, [pc, #48] ; (8010740 ) 801070e: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8010712: 601a str r2, [r3, #0] 8010714: f3bf 8f4f dsb sy 8010718: f3bf 8f6f isb sy 801071c: e00b b.n 8010736 } else { if (xQueueSend(queue_id, &info, ticks) != pdTRUE) { 801071e: f107 0108 add.w r1, r7, #8 8010722: 2300 movs r3, #0 8010724: 697a ldr r2, [r7, #20] 8010726: 68f8 ldr r0, [r7, #12] 8010728: f000 fae4 bl 8010cf4 801072c: 4603 mov r3, r0 801072e: 2b01 cmp r3, #1 8010730: d001 beq.n 8010736 return osErrorOS; 8010732: 23ff movs r3, #255 ; 0xff 8010734: e000 b.n 8010738 } } return osOK; 8010736: 2300 movs r3, #0 } 8010738: 4618 mov r0, r3 801073a: 3718 adds r7, #24 801073c: 46bd mov sp, r7 801073e: bd80 pop {r7, pc} 8010740: e000ed04 .word 0xe000ed04 08010744 : * @param millisec timeout value or 0 in case of no time-out. * @retval event information that includes status code. * @note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. */ osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) { 8010744: b590 push {r4, r7, lr} 8010746: b08b sub sp, #44 ; 0x2c 8010748: af00 add r7, sp, #0 801074a: 60f8 str r0, [r7, #12] 801074c: 60b9 str r1, [r7, #8] 801074e: 607a str r2, [r7, #4] portBASE_TYPE taskWoken; TickType_t ticks; osEvent event; event.def.message_id = queue_id; 8010750: 68bb ldr r3, [r7, #8] 8010752: 61fb str r3, [r7, #28] event.value.v = 0; 8010754: 2300 movs r3, #0 8010756: 61bb str r3, [r7, #24] if (queue_id == NULL) { 8010758: 68bb ldr r3, [r7, #8] 801075a: 2b00 cmp r3, #0 801075c: d10a bne.n 8010774 event.status = osErrorParameter; 801075e: 2380 movs r3, #128 ; 0x80 8010760: 617b str r3, [r7, #20] return event; 8010762: 68fb ldr r3, [r7, #12] 8010764: 461c mov r4, r3 8010766: f107 0314 add.w r3, r7, #20 801076a: e893 0007 ldmia.w r3, {r0, r1, r2} 801076e: e884 0007 stmia.w r4, {r0, r1, r2} 8010772: e054 b.n 801081e } taskWoken = pdFALSE; 8010774: 2300 movs r3, #0 8010776: 623b str r3, [r7, #32] ticks = 0; 8010778: 2300 movs r3, #0 801077a: 627b str r3, [r7, #36] ; 0x24 if (millisec == osWaitForever) { 801077c: 687b ldr r3, [r7, #4] 801077e: f1b3 3fff cmp.w r3, #4294967295 8010782: d103 bne.n 801078c ticks = portMAX_DELAY; 8010784: f04f 33ff mov.w r3, #4294967295 8010788: 627b str r3, [r7, #36] ; 0x24 801078a: e009 b.n 80107a0 } else if (millisec != 0) { 801078c: 687b ldr r3, [r7, #4] 801078e: 2b00 cmp r3, #0 8010790: d006 beq.n 80107a0 ticks = millisec / portTICK_PERIOD_MS; 8010792: 687b ldr r3, [r7, #4] 8010794: 627b str r3, [r7, #36] ; 0x24 if (ticks == 0) { 8010796: 6a7b ldr r3, [r7, #36] ; 0x24 8010798: 2b00 cmp r3, #0 801079a: d101 bne.n 80107a0 ticks = 1; 801079c: 2301 movs r3, #1 801079e: 627b str r3, [r7, #36] ; 0x24 } } if (inHandlerMode()) { 80107a0: f7ff fd6d bl 801027e 80107a4: 4603 mov r3, r0 80107a6: 2b00 cmp r3, #0 80107a8: d01c beq.n 80107e4 if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) { 80107aa: f107 0220 add.w r2, r7, #32 80107ae: f107 0314 add.w r3, r7, #20 80107b2: 3304 adds r3, #4 80107b4: 4619 mov r1, r3 80107b6: 68b8 ldr r0, [r7, #8] 80107b8: f000 feae bl 8011518 80107bc: 4603 mov r3, r0 80107be: 2b01 cmp r3, #1 80107c0: d102 bne.n 80107c8 /* We have mail */ event.status = osEventMessage; 80107c2: 2310 movs r3, #16 80107c4: 617b str r3, [r7, #20] 80107c6: e001 b.n 80107cc } else { event.status = osOK; 80107c8: 2300 movs r3, #0 80107ca: 617b str r3, [r7, #20] } portEND_SWITCHING_ISR(taskWoken); 80107cc: 6a3b ldr r3, [r7, #32] 80107ce: 2b00 cmp r3, #0 80107d0: d01d beq.n 801080e 80107d2: 4b15 ldr r3, [pc, #84] ; (8010828 ) 80107d4: f04f 5280 mov.w r2, #268435456 ; 0x10000000 80107d8: 601a str r2, [r3, #0] 80107da: f3bf 8f4f dsb sy 80107de: f3bf 8f6f isb sy 80107e2: e014 b.n 801080e } else { if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) { 80107e4: f107 0314 add.w r3, r7, #20 80107e8: 3304 adds r3, #4 80107ea: 6a7a ldr r2, [r7, #36] ; 0x24 80107ec: 4619 mov r1, r3 80107ee: 68b8 ldr r0, [r7, #8] 80107f0: f000 fca6 bl 8011140 80107f4: 4603 mov r3, r0 80107f6: 2b01 cmp r3, #1 80107f8: d102 bne.n 8010800 /* We have mail */ event.status = osEventMessage; 80107fa: 2310 movs r3, #16 80107fc: 617b str r3, [r7, #20] 80107fe: e006 b.n 801080e } else { event.status = (ticks == 0) ? osOK : osEventTimeout; 8010800: 6a7b ldr r3, [r7, #36] ; 0x24 8010802: 2b00 cmp r3, #0 8010804: d101 bne.n 801080a 8010806: 2300 movs r3, #0 8010808: e000 b.n 801080c 801080a: 2340 movs r3, #64 ; 0x40 801080c: 617b str r3, [r7, #20] } } return event; 801080e: 68fb ldr r3, [r7, #12] 8010810: 461c mov r4, r3 8010812: f107 0314 add.w r3, r7, #20 8010816: e893 0007 ldmia.w r3, {r0, r1, r2} 801081a: e884 0007 stmia.w r4, {r0, r1, r2} } 801081e: 68f8 ldr r0, [r7, #12] 8010820: 372c adds r7, #44 ; 0x2c 8010822: 46bd mov sp, r7 8010824: bd90 pop {r4, r7, pc} 8010826: bf00 nop 8010828: e000ed04 .word 0xe000ed04 0801082c : * @brief Get the number of messaged stored in a queue. * @param queue_id message queue ID obtained with \ref osMessageCreate. * @retval number of messages stored in a queue. */ uint32_t osMessageWaiting(osMessageQId queue_id) { 801082c: b580 push {r7, lr} 801082e: b082 sub sp, #8 8010830: af00 add r7, sp, #0 8010832: 6078 str r0, [r7, #4] if (inHandlerMode()) { 8010834: f7ff fd23 bl 801027e 8010838: 4603 mov r3, r0 801083a: 2b00 cmp r3, #0 801083c: d004 beq.n 8010848 return uxQueueMessagesWaitingFromISR(queue_id); 801083e: 6878 ldr r0, [r7, #4] 8010840: f000 ff08 bl 8011654 8010844: 4603 mov r3, r0 8010846: e003 b.n 8010850 } else { return uxQueueMessagesWaiting(queue_id); 8010848: 6878 ldr r0, [r7, #4] 801084a: f000 fee5 bl 8011618 801084e: 4603 mov r3, r0 } } 8010850: 4618 mov r0, r3 8010852: 3708 adds r7, #8 8010854: 46bd mov sp, r7 8010856: bd80 pop {r7, pc} 08010858 : * @brief Delete a Message Queue * @param queue_id message queue ID obtained with \ref osMessageCreate. * @retval status code that indicates the execution status of the function. */ osStatus osMessageDelete (osMessageQId queue_id) { 8010858: b580 push {r7, lr} 801085a: b082 sub sp, #8 801085c: af00 add r7, sp, #0 801085e: 6078 str r0, [r7, #4] if (inHandlerMode()) { 8010860: f7ff fd0d bl 801027e 8010864: 4603 mov r3, r0 8010866: 2b00 cmp r3, #0 8010868: d001 beq.n 801086e return osErrorISR; 801086a: 2382 movs r3, #130 ; 0x82 801086c: e003 b.n 8010876 } vQueueDelete(queue_id); 801086e: 6878 ldr r0, [r7, #4] 8010870: f000 ff0e bl 8011690 return osOK; 8010874: 2300 movs r3, #0 } 8010876: 4618 mov r0, r3 8010878: 3708 adds r7, #8 801087a: 46bd mov sp, r7 801087c: bd80 pop {r7, pc} 0801087e : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 801087e: b480 push {r7} 8010880: b083 sub sp, #12 8010882: af00 add r7, sp, #0 8010884: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8010886: 687b ldr r3, [r7, #4] 8010888: f103 0208 add.w r2, r3, #8 801088c: 687b ldr r3, [r7, #4] 801088e: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 8010890: 687b ldr r3, [r7, #4] 8010892: f04f 32ff mov.w r2, #4294967295 8010896: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8010898: 687b ldr r3, [r7, #4] 801089a: f103 0208 add.w r2, r3, #8 801089e: 687b ldr r3, [r7, #4] 80108a0: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 80108a2: 687b ldr r3, [r7, #4] 80108a4: f103 0208 add.w r2, r3, #8 80108a8: 687b ldr r3, [r7, #4] 80108aa: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 80108ac: 687b ldr r3, [r7, #4] 80108ae: 2200 movs r2, #0 80108b0: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 80108b2: bf00 nop 80108b4: 370c adds r7, #12 80108b6: 46bd mov sp, r7 80108b8: f85d 7b04 ldr.w r7, [sp], #4 80108bc: 4770 bx lr 080108be : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 80108be: b480 push {r7} 80108c0: b083 sub sp, #12 80108c2: af00 add r7, sp, #0 80108c4: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 80108c6: 687b ldr r3, [r7, #4] 80108c8: 2200 movs r2, #0 80108ca: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 80108cc: bf00 nop 80108ce: 370c adds r7, #12 80108d0: 46bd mov sp, r7 80108d2: f85d 7b04 ldr.w r7, [sp], #4 80108d6: 4770 bx lr 080108d8 : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 80108d8: b480 push {r7} 80108da: b085 sub sp, #20 80108dc: af00 add r7, sp, #0 80108de: 6078 str r0, [r7, #4] 80108e0: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 80108e2: 687b ldr r3, [r7, #4] 80108e4: 685b ldr r3, [r3, #4] 80108e6: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 80108e8: 683b ldr r3, [r7, #0] 80108ea: 68fa ldr r2, [r7, #12] 80108ec: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 80108ee: 68fb ldr r3, [r7, #12] 80108f0: 689a ldr r2, [r3, #8] 80108f2: 683b ldr r3, [r7, #0] 80108f4: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 80108f6: 68fb ldr r3, [r7, #12] 80108f8: 689b ldr r3, [r3, #8] 80108fa: 683a ldr r2, [r7, #0] 80108fc: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 80108fe: 68fb ldr r3, [r7, #12] 8010900: 683a ldr r2, [r7, #0] 8010902: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 8010904: 683b ldr r3, [r7, #0] 8010906: 687a ldr r2, [r7, #4] 8010908: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 801090a: 687b ldr r3, [r7, #4] 801090c: 681b ldr r3, [r3, #0] 801090e: 1c5a adds r2, r3, #1 8010910: 687b ldr r3, [r7, #4] 8010912: 601a str r2, [r3, #0] } 8010914: bf00 nop 8010916: 3714 adds r7, #20 8010918: 46bd mov sp, r7 801091a: f85d 7b04 ldr.w r7, [sp], #4 801091e: 4770 bx lr 08010920 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8010920: b480 push {r7} 8010922: b085 sub sp, #20 8010924: af00 add r7, sp, #0 8010926: 6078 str r0, [r7, #4] 8010928: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 801092a: 683b ldr r3, [r7, #0] 801092c: 681b ldr r3, [r3, #0] 801092e: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8010930: 68bb ldr r3, [r7, #8] 8010932: f1b3 3fff cmp.w r3, #4294967295 8010936: d103 bne.n 8010940 { pxIterator = pxList->xListEnd.pxPrevious; 8010938: 687b ldr r3, [r7, #4] 801093a: 691b ldr r3, [r3, #16] 801093c: 60fb str r3, [r7, #12] 801093e: e00c b.n 801095a 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8010940: 687b ldr r3, [r7, #4] 8010942: 3308 adds r3, #8 8010944: 60fb str r3, [r7, #12] 8010946: e002 b.n 801094e 8010948: 68fb ldr r3, [r7, #12] 801094a: 685b ldr r3, [r3, #4] 801094c: 60fb str r3, [r7, #12] 801094e: 68fb ldr r3, [r7, #12] 8010950: 685b ldr r3, [r3, #4] 8010952: 681b ldr r3, [r3, #0] 8010954: 68ba ldr r2, [r7, #8] 8010956: 429a cmp r2, r3 8010958: d2f6 bcs.n 8010948 /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 801095a: 68fb ldr r3, [r7, #12] 801095c: 685a ldr r2, [r3, #4] 801095e: 683b ldr r3, [r7, #0] 8010960: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8010962: 683b ldr r3, [r7, #0] 8010964: 685b ldr r3, [r3, #4] 8010966: 683a ldr r2, [r7, #0] 8010968: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 801096a: 683b ldr r3, [r7, #0] 801096c: 68fa ldr r2, [r7, #12] 801096e: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8010970: 68fb ldr r3, [r7, #12] 8010972: 683a ldr r2, [r7, #0] 8010974: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8010976: 683b ldr r3, [r7, #0] 8010978: 687a ldr r2, [r7, #4] 801097a: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 801097c: 687b ldr r3, [r7, #4] 801097e: 681b ldr r3, [r3, #0] 8010980: 1c5a adds r2, r3, #1 8010982: 687b ldr r3, [r7, #4] 8010984: 601a str r2, [r3, #0] } 8010986: bf00 nop 8010988: 3714 adds r7, #20 801098a: 46bd mov sp, r7 801098c: f85d 7b04 ldr.w r7, [sp], #4 8010990: 4770 bx lr 08010992 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8010992: b480 push {r7} 8010994: b085 sub sp, #20 8010996: af00 add r7, sp, #0 8010998: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 801099a: 687b ldr r3, [r7, #4] 801099c: 691b ldr r3, [r3, #16] 801099e: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 80109a0: 687b ldr r3, [r7, #4] 80109a2: 685b ldr r3, [r3, #4] 80109a4: 687a ldr r2, [r7, #4] 80109a6: 6892 ldr r2, [r2, #8] 80109a8: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 80109aa: 687b ldr r3, [r7, #4] 80109ac: 689b ldr r3, [r3, #8] 80109ae: 687a ldr r2, [r7, #4] 80109b0: 6852 ldr r2, [r2, #4] 80109b2: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 80109b4: 68fb ldr r3, [r7, #12] 80109b6: 685b ldr r3, [r3, #4] 80109b8: 687a ldr r2, [r7, #4] 80109ba: 429a cmp r2, r3 80109bc: d103 bne.n 80109c6 { pxList->pxIndex = pxItemToRemove->pxPrevious; 80109be: 687b ldr r3, [r7, #4] 80109c0: 689a ldr r2, [r3, #8] 80109c2: 68fb ldr r3, [r7, #12] 80109c4: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 80109c6: 687b ldr r3, [r7, #4] 80109c8: 2200 movs r2, #0 80109ca: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 80109cc: 68fb ldr r3, [r7, #12] 80109ce: 681b ldr r3, [r3, #0] 80109d0: 1e5a subs r2, r3, #1 80109d2: 68fb ldr r3, [r7, #12] 80109d4: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 80109d6: 68fb ldr r3, [r7, #12] 80109d8: 681b ldr r3, [r3, #0] } 80109da: 4618 mov r0, r3 80109dc: 3714 adds r7, #20 80109de: 46bd mov sp, r7 80109e0: f85d 7b04 ldr.w r7, [sp], #4 80109e4: 4770 bx lr ... 080109e8 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 80109e8: b580 push {r7, lr} 80109ea: b084 sub sp, #16 80109ec: af00 add r7, sp, #0 80109ee: 6078 str r0, [r7, #4] 80109f0: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 80109f2: 687b ldr r3, [r7, #4] 80109f4: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 80109f6: 68fb ldr r3, [r7, #12] 80109f8: 2b00 cmp r3, #0 80109fa: d10a bne.n 8010a12 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 80109fc: f04f 0350 mov.w r3, #80 ; 0x50 8010a00: f383 8811 msr BASEPRI, r3 8010a04: f3bf 8f6f isb sy 8010a08: f3bf 8f4f dsb sy 8010a0c: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8010a0e: bf00 nop 8010a10: e7fe b.n 8010a10 taskENTER_CRITICAL(); 8010a12: f002 fcf7 bl 8013404 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8010a16: 68fb ldr r3, [r7, #12] 8010a18: 681a ldr r2, [r3, #0] 8010a1a: 68fb ldr r3, [r7, #12] 8010a1c: 6bdb ldr r3, [r3, #60] ; 0x3c 8010a1e: 68f9 ldr r1, [r7, #12] 8010a20: 6c09 ldr r1, [r1, #64] ; 0x40 8010a22: fb01 f303 mul.w r3, r1, r3 8010a26: 441a add r2, r3 8010a28: 68fb ldr r3, [r7, #12] 8010a2a: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 8010a2c: 68fb ldr r3, [r7, #12] 8010a2e: 2200 movs r2, #0 8010a30: 639a str r2, [r3, #56] ; 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8010a32: 68fb ldr r3, [r7, #12] 8010a34: 681a ldr r2, [r3, #0] 8010a36: 68fb ldr r3, [r7, #12] 8010a38: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8010a3a: 68fb ldr r3, [r7, #12] 8010a3c: 681a ldr r2, [r3, #0] 8010a3e: 68fb ldr r3, [r7, #12] 8010a40: 6bdb ldr r3, [r3, #60] ; 0x3c 8010a42: 3b01 subs r3, #1 8010a44: 68f9 ldr r1, [r7, #12] 8010a46: 6c09 ldr r1, [r1, #64] ; 0x40 8010a48: fb01 f303 mul.w r3, r1, r3 8010a4c: 441a add r2, r3 8010a4e: 68fb ldr r3, [r7, #12] 8010a50: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8010a52: 68fb ldr r3, [r7, #12] 8010a54: 22ff movs r2, #255 ; 0xff 8010a56: f883 2044 strb.w r2, [r3, #68] ; 0x44 pxQueue->cTxLock = queueUNLOCKED; 8010a5a: 68fb ldr r3, [r7, #12] 8010a5c: 22ff movs r2, #255 ; 0xff 8010a5e: f883 2045 strb.w r2, [r3, #69] ; 0x45 if( xNewQueue == pdFALSE ) 8010a62: 683b ldr r3, [r7, #0] 8010a64: 2b00 cmp r3, #0 8010a66: d114 bne.n 8010a92 /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8010a68: 68fb ldr r3, [r7, #12] 8010a6a: 691b ldr r3, [r3, #16] 8010a6c: 2b00 cmp r3, #0 8010a6e: d01a beq.n 8010aa6 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8010a70: 68fb ldr r3, [r7, #12] 8010a72: 3310 adds r3, #16 8010a74: 4618 mov r0, r3 8010a76: f001 fc53 bl 8012320 8010a7a: 4603 mov r3, r0 8010a7c: 2b00 cmp r3, #0 8010a7e: d012 beq.n 8010aa6 { queueYIELD_IF_USING_PREEMPTION(); 8010a80: 4b0c ldr r3, [pc, #48] ; (8010ab4 ) 8010a82: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8010a86: 601a str r2, [r3, #0] 8010a88: f3bf 8f4f dsb sy 8010a8c: f3bf 8f6f isb sy 8010a90: e009 b.n 8010aa6 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8010a92: 68fb ldr r3, [r7, #12] 8010a94: 3310 adds r3, #16 8010a96: 4618 mov r0, r3 8010a98: f7ff fef1 bl 801087e vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 8010a9c: 68fb ldr r3, [r7, #12] 8010a9e: 3324 adds r3, #36 ; 0x24 8010aa0: 4618 mov r0, r3 8010aa2: f7ff feec bl 801087e } } taskEXIT_CRITICAL(); 8010aa6: f002 fcdd bl 8013464 /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 8010aaa: 2301 movs r3, #1 } 8010aac: 4618 mov r0, r3 8010aae: 3710 adds r7, #16 8010ab0: 46bd mov sp, r7 8010ab2: bd80 pop {r7, pc} 8010ab4: e000ed04 .word 0xe000ed04 08010ab8 : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 8010ab8: b580 push {r7, lr} 8010aba: b08e sub sp, #56 ; 0x38 8010abc: af02 add r7, sp, #8 8010abe: 60f8 str r0, [r7, #12] 8010ac0: 60b9 str r1, [r7, #8] 8010ac2: 607a str r2, [r7, #4] 8010ac4: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8010ac6: 68fb ldr r3, [r7, #12] 8010ac8: 2b00 cmp r3, #0 8010aca: d10a bne.n 8010ae2 __asm volatile 8010acc: f04f 0350 mov.w r3, #80 ; 0x50 8010ad0: f383 8811 msr BASEPRI, r3 8010ad4: f3bf 8f6f isb sy 8010ad8: f3bf 8f4f dsb sy 8010adc: 62bb str r3, [r7, #40] ; 0x28 } 8010ade: bf00 nop 8010ae0: e7fe b.n 8010ae0 /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 8010ae2: 683b ldr r3, [r7, #0] 8010ae4: 2b00 cmp r3, #0 8010ae6: d10a bne.n 8010afe __asm volatile 8010ae8: f04f 0350 mov.w r3, #80 ; 0x50 8010aec: f383 8811 msr BASEPRI, r3 8010af0: f3bf 8f6f isb sy 8010af4: f3bf 8f4f dsb sy 8010af8: 627b str r3, [r7, #36] ; 0x24 } 8010afa: bf00 nop 8010afc: e7fe b.n 8010afc /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 8010afe: 687b ldr r3, [r7, #4] 8010b00: 2b00 cmp r3, #0 8010b02: d002 beq.n 8010b0a 8010b04: 68bb ldr r3, [r7, #8] 8010b06: 2b00 cmp r3, #0 8010b08: d001 beq.n 8010b0e 8010b0a: 2301 movs r3, #1 8010b0c: e000 b.n 8010b10 8010b0e: 2300 movs r3, #0 8010b10: 2b00 cmp r3, #0 8010b12: d10a bne.n 8010b2a __asm volatile 8010b14: f04f 0350 mov.w r3, #80 ; 0x50 8010b18: f383 8811 msr BASEPRI, r3 8010b1c: f3bf 8f6f isb sy 8010b20: f3bf 8f4f dsb sy 8010b24: 623b str r3, [r7, #32] } 8010b26: bf00 nop 8010b28: e7fe b.n 8010b28 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 8010b2a: 687b ldr r3, [r7, #4] 8010b2c: 2b00 cmp r3, #0 8010b2e: d102 bne.n 8010b36 8010b30: 68bb ldr r3, [r7, #8] 8010b32: 2b00 cmp r3, #0 8010b34: d101 bne.n 8010b3a 8010b36: 2301 movs r3, #1 8010b38: e000 b.n 8010b3c 8010b3a: 2300 movs r3, #0 8010b3c: 2b00 cmp r3, #0 8010b3e: d10a bne.n 8010b56 __asm volatile 8010b40: f04f 0350 mov.w r3, #80 ; 0x50 8010b44: f383 8811 msr BASEPRI, r3 8010b48: f3bf 8f6f isb sy 8010b4c: f3bf 8f4f dsb sy 8010b50: 61fb str r3, [r7, #28] } 8010b52: bf00 nop 8010b54: e7fe b.n 8010b54 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 8010b56: 2348 movs r3, #72 ; 0x48 8010b58: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 8010b5a: 697b ldr r3, [r7, #20] 8010b5c: 2b48 cmp r3, #72 ; 0x48 8010b5e: d00a beq.n 8010b76 __asm volatile 8010b60: f04f 0350 mov.w r3, #80 ; 0x50 8010b64: f383 8811 msr BASEPRI, r3 8010b68: f3bf 8f6f isb sy 8010b6c: f3bf 8f4f dsb sy 8010b70: 61bb str r3, [r7, #24] } 8010b72: bf00 nop 8010b74: e7fe b.n 8010b74 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8010b76: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8010b78: 683b ldr r3, [r7, #0] 8010b7a: 62fb str r3, [r7, #44] ; 0x2c if( pxNewQueue != NULL ) 8010b7c: 6afb ldr r3, [r7, #44] ; 0x2c 8010b7e: 2b00 cmp r3, #0 8010b80: d00d beq.n 8010b9e #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 8010b82: 6afb ldr r3, [r7, #44] ; 0x2c 8010b84: 2201 movs r2, #1 8010b86: f883 2046 strb.w r2, [r3, #70] ; 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8010b8a: f897 2038 ldrb.w r2, [r7, #56] ; 0x38 8010b8e: 6afb ldr r3, [r7, #44] ; 0x2c 8010b90: 9300 str r3, [sp, #0] 8010b92: 4613 mov r3, r2 8010b94: 687a ldr r2, [r7, #4] 8010b96: 68b9 ldr r1, [r7, #8] 8010b98: 68f8 ldr r0, [r7, #12] 8010b9a: f000 f83f bl 8010c1c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8010b9e: 6afb ldr r3, [r7, #44] ; 0x2c } 8010ba0: 4618 mov r0, r3 8010ba2: 3730 adds r7, #48 ; 0x30 8010ba4: 46bd mov sp, r7 8010ba6: bd80 pop {r7, pc} 08010ba8 : /*-----------------------------------------------------------*/ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 8010ba8: b580 push {r7, lr} 8010baa: b08a sub sp, #40 ; 0x28 8010bac: af02 add r7, sp, #8 8010bae: 60f8 str r0, [r7, #12] 8010bb0: 60b9 str r1, [r7, #8] 8010bb2: 4613 mov r3, r2 8010bb4: 71fb strb r3, [r7, #7] Queue_t *pxNewQueue; size_t xQueueSizeInBytes; uint8_t *pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8010bb6: 68fb ldr r3, [r7, #12] 8010bb8: 2b00 cmp r3, #0 8010bba: d10a bne.n 8010bd2 __asm volatile 8010bbc: f04f 0350 mov.w r3, #80 ; 0x50 8010bc0: f383 8811 msr BASEPRI, r3 8010bc4: f3bf 8f6f isb sy 8010bc8: f3bf 8f4f dsb sy 8010bcc: 613b str r3, [r7, #16] } 8010bce: bf00 nop 8010bd0: e7fe b.n 8010bd0 /* Allocate enough space to hold the maximum number of items that can be in the queue at any time. It is valid for uxItemSize to be zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8010bd2: 68fb ldr r3, [r7, #12] 8010bd4: 68ba ldr r2, [r7, #8] 8010bd6: fb02 f303 mul.w r3, r2, r3 8010bda: 61fb str r3, [r7, #28] alignment requirements of the Queue_t structure - which in this case is an int8_t *. Therefore, whenever the stack alignment requirements are greater than or equal to the pointer to char requirements the cast is safe. In other cases alignment requirements are not strict (one or two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 8010bdc: 69fb ldr r3, [r7, #28] 8010bde: 3348 adds r3, #72 ; 0x48 8010be0: 4618 mov r0, r3 8010be2: f002 fd31 bl 8013648 8010be6: 61b8 str r0, [r7, #24] if( pxNewQueue != NULL ) 8010be8: 69bb ldr r3, [r7, #24] 8010bea: 2b00 cmp r3, #0 8010bec: d011 beq.n 8010c12 { /* Jump past the queue structure to find the location of the queue storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 8010bee: 69bb ldr r3, [r7, #24] 8010bf0: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8010bf2: 697b ldr r3, [r7, #20] 8010bf4: 3348 adds r3, #72 ; 0x48 8010bf6: 617b str r3, [r7, #20] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 8010bf8: 69bb ldr r3, [r7, #24] 8010bfa: 2200 movs r2, #0 8010bfc: f883 2046 strb.w r2, [r3, #70] ; 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8010c00: 79fa ldrb r2, [r7, #7] 8010c02: 69bb ldr r3, [r7, #24] 8010c04: 9300 str r3, [sp, #0] 8010c06: 4613 mov r3, r2 8010c08: 697a ldr r2, [r7, #20] 8010c0a: 68b9 ldr r1, [r7, #8] 8010c0c: 68f8 ldr r0, [r7, #12] 8010c0e: f000 f805 bl 8010c1c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8010c12: 69bb ldr r3, [r7, #24] } 8010c14: 4618 mov r0, r3 8010c16: 3720 adds r7, #32 8010c18: 46bd mov sp, r7 8010c1a: bd80 pop {r7, pc} 08010c1c : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 8010c1c: b580 push {r7, lr} 8010c1e: b084 sub sp, #16 8010c20: af00 add r7, sp, #0 8010c22: 60f8 str r0, [r7, #12] 8010c24: 60b9 str r1, [r7, #8] 8010c26: 607a str r2, [r7, #4] 8010c28: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 8010c2a: 68bb ldr r3, [r7, #8] 8010c2c: 2b00 cmp r3, #0 8010c2e: d103 bne.n 8010c38 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 8010c30: 69bb ldr r3, [r7, #24] 8010c32: 69ba ldr r2, [r7, #24] 8010c34: 601a str r2, [r3, #0] 8010c36: e002 b.n 8010c3e } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 8010c38: 69bb ldr r3, [r7, #24] 8010c3a: 687a ldr r2, [r7, #4] 8010c3c: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 8010c3e: 69bb ldr r3, [r7, #24] 8010c40: 68fa ldr r2, [r7, #12] 8010c42: 63da str r2, [r3, #60] ; 0x3c pxNewQueue->uxItemSize = uxItemSize; 8010c44: 69bb ldr r3, [r7, #24] 8010c46: 68ba ldr r2, [r7, #8] 8010c48: 641a str r2, [r3, #64] ; 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 8010c4a: 2101 movs r1, #1 8010c4c: 69b8 ldr r0, [r7, #24] 8010c4e: f7ff fecb bl 80109e8 pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 8010c52: bf00 nop 8010c54: 3710 adds r7, #16 8010c56: 46bd mov sp, r7 8010c58: bd80 pop {r7, pc} 08010c5a : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t *pxNewQueue ) { 8010c5a: b580 push {r7, lr} 8010c5c: b082 sub sp, #8 8010c5e: af00 add r7, sp, #0 8010c60: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 8010c62: 687b ldr r3, [r7, #4] 8010c64: 2b00 cmp r3, #0 8010c66: d00e beq.n 8010c86 { /* The queue create function will set all the queue structure members correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 8010c68: 687b ldr r3, [r7, #4] 8010c6a: 2200 movs r2, #0 8010c6c: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 8010c6e: 687b ldr r3, [r7, #4] 8010c70: 2200 movs r2, #0 8010c72: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 8010c74: 687b ldr r3, [r7, #4] 8010c76: 2200 movs r2, #0 8010c78: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 8010c7a: 2300 movs r3, #0 8010c7c: 2200 movs r2, #0 8010c7e: 2100 movs r1, #0 8010c80: 6878 ldr r0, [r7, #4] 8010c82: f000 f837 bl 8010cf4 } else { traceCREATE_MUTEX_FAILED(); } } 8010c86: bf00 nop 8010c88: 3708 adds r7, #8 8010c8a: 46bd mov sp, r7 8010c8c: bd80 pop {r7, pc} 08010c8e : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 8010c8e: b580 push {r7, lr} 8010c90: b086 sub sp, #24 8010c92: af00 add r7, sp, #0 8010c94: 4603 mov r3, r0 8010c96: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8010c98: 2301 movs r3, #1 8010c9a: 617b str r3, [r7, #20] 8010c9c: 2300 movs r3, #0 8010c9e: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 8010ca0: 79fb ldrb r3, [r7, #7] 8010ca2: 461a mov r2, r3 8010ca4: 6939 ldr r1, [r7, #16] 8010ca6: 6978 ldr r0, [r7, #20] 8010ca8: f7ff ff7e bl 8010ba8 8010cac: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8010cae: 68f8 ldr r0, [r7, #12] 8010cb0: f7ff ffd3 bl 8010c5a return xNewQueue; 8010cb4: 68fb ldr r3, [r7, #12] } 8010cb6: 4618 mov r0, r3 8010cb8: 3718 adds r7, #24 8010cba: 46bd mov sp, r7 8010cbc: bd80 pop {r7, pc} 08010cbe : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { 8010cbe: b580 push {r7, lr} 8010cc0: b088 sub sp, #32 8010cc2: af02 add r7, sp, #8 8010cc4: 4603 mov r3, r0 8010cc6: 6039 str r1, [r7, #0] 8010cc8: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8010cca: 2301 movs r3, #1 8010ccc: 617b str r3, [r7, #20] 8010cce: 2300 movs r3, #0 8010cd0: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 8010cd2: 79fb ldrb r3, [r7, #7] 8010cd4: 9300 str r3, [sp, #0] 8010cd6: 683b ldr r3, [r7, #0] 8010cd8: 2200 movs r2, #0 8010cda: 6939 ldr r1, [r7, #16] 8010cdc: 6978 ldr r0, [r7, #20] 8010cde: f7ff feeb bl 8010ab8 8010ce2: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8010ce4: 68f8 ldr r0, [r7, #12] 8010ce6: f7ff ffb8 bl 8010c5a return xNewQueue; 8010cea: 68fb ldr r3, [r7, #12] } 8010cec: 4618 mov r0, r3 8010cee: 3718 adds r7, #24 8010cf0: 46bd mov sp, r7 8010cf2: bd80 pop {r7, pc} 08010cf4 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8010cf4: b580 push {r7, lr} 8010cf6: b08e sub sp, #56 ; 0x38 8010cf8: af00 add r7, sp, #0 8010cfa: 60f8 str r0, [r7, #12] 8010cfc: 60b9 str r1, [r7, #8] 8010cfe: 607a str r2, [r7, #4] 8010d00: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8010d02: 2300 movs r3, #0 8010d04: 637b str r3, [r7, #52] ; 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8010d06: 68fb ldr r3, [r7, #12] 8010d08: 633b str r3, [r7, #48] ; 0x30 configASSERT( pxQueue ); 8010d0a: 6b3b ldr r3, [r7, #48] ; 0x30 8010d0c: 2b00 cmp r3, #0 8010d0e: d10a bne.n 8010d26 __asm volatile 8010d10: f04f 0350 mov.w r3, #80 ; 0x50 8010d14: f383 8811 msr BASEPRI, r3 8010d18: f3bf 8f6f isb sy 8010d1c: f3bf 8f4f dsb sy 8010d20: 62bb str r3, [r7, #40] ; 0x28 } 8010d22: bf00 nop 8010d24: e7fe b.n 8010d24 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8010d26: 68bb ldr r3, [r7, #8] 8010d28: 2b00 cmp r3, #0 8010d2a: d103 bne.n 8010d34 8010d2c: 6b3b ldr r3, [r7, #48] ; 0x30 8010d2e: 6c1b ldr r3, [r3, #64] ; 0x40 8010d30: 2b00 cmp r3, #0 8010d32: d101 bne.n 8010d38 8010d34: 2301 movs r3, #1 8010d36: e000 b.n 8010d3a 8010d38: 2300 movs r3, #0 8010d3a: 2b00 cmp r3, #0 8010d3c: d10a bne.n 8010d54 __asm volatile 8010d3e: f04f 0350 mov.w r3, #80 ; 0x50 8010d42: f383 8811 msr BASEPRI, r3 8010d46: f3bf 8f6f isb sy 8010d4a: f3bf 8f4f dsb sy 8010d4e: 627b str r3, [r7, #36] ; 0x24 } 8010d50: bf00 nop 8010d52: e7fe b.n 8010d52 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8010d54: 683b ldr r3, [r7, #0] 8010d56: 2b02 cmp r3, #2 8010d58: d103 bne.n 8010d62 8010d5a: 6b3b ldr r3, [r7, #48] ; 0x30 8010d5c: 6bdb ldr r3, [r3, #60] ; 0x3c 8010d5e: 2b01 cmp r3, #1 8010d60: d101 bne.n 8010d66 8010d62: 2301 movs r3, #1 8010d64: e000 b.n 8010d68 8010d66: 2300 movs r3, #0 8010d68: 2b00 cmp r3, #0 8010d6a: d10a bne.n 8010d82 __asm volatile 8010d6c: f04f 0350 mov.w r3, #80 ; 0x50 8010d70: f383 8811 msr BASEPRI, r3 8010d74: f3bf 8f6f isb sy 8010d78: f3bf 8f4f dsb sy 8010d7c: 623b str r3, [r7, #32] } 8010d7e: bf00 nop 8010d80: e7fe b.n 8010d80 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8010d82: f001 fcc1 bl 8012708 8010d86: 4603 mov r3, r0 8010d88: 2b00 cmp r3, #0 8010d8a: d102 bne.n 8010d92 8010d8c: 687b ldr r3, [r7, #4] 8010d8e: 2b00 cmp r3, #0 8010d90: d101 bne.n 8010d96 8010d92: 2301 movs r3, #1 8010d94: e000 b.n 8010d98 8010d96: 2300 movs r3, #0 8010d98: 2b00 cmp r3, #0 8010d9a: d10a bne.n 8010db2 __asm volatile 8010d9c: f04f 0350 mov.w r3, #80 ; 0x50 8010da0: f383 8811 msr BASEPRI, r3 8010da4: f3bf 8f6f isb sy 8010da8: f3bf 8f4f dsb sy 8010dac: 61fb str r3, [r7, #28] } 8010dae: bf00 nop 8010db0: e7fe b.n 8010db0 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8010db2: f002 fb27 bl 8013404 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8010db6: 6b3b ldr r3, [r7, #48] ; 0x30 8010db8: 6b9a ldr r2, [r3, #56] ; 0x38 8010dba: 6b3b ldr r3, [r7, #48] ; 0x30 8010dbc: 6bdb ldr r3, [r3, #60] ; 0x3c 8010dbe: 429a cmp r2, r3 8010dc0: d302 bcc.n 8010dc8 8010dc2: 683b ldr r3, [r7, #0] 8010dc4: 2b02 cmp r3, #2 8010dc6: d129 bne.n 8010e1c } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8010dc8: 683a ldr r2, [r7, #0] 8010dca: 68b9 ldr r1, [r7, #8] 8010dcc: 6b38 ldr r0, [r7, #48] ; 0x30 8010dce: f000 fc9a bl 8011706 8010dd2: 62f8 str r0, [r7, #44] ; 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8010dd4: 6b3b ldr r3, [r7, #48] ; 0x30 8010dd6: 6a5b ldr r3, [r3, #36] ; 0x24 8010dd8: 2b00 cmp r3, #0 8010dda: d010 beq.n 8010dfe { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8010ddc: 6b3b ldr r3, [r7, #48] ; 0x30 8010dde: 3324 adds r3, #36 ; 0x24 8010de0: 4618 mov r0, r3 8010de2: f001 fa9d bl 8012320 8010de6: 4603 mov r3, r0 8010de8: 2b00 cmp r3, #0 8010dea: d013 beq.n 8010e14 { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8010dec: 4b3f ldr r3, [pc, #252] ; (8010eec ) 8010dee: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8010df2: 601a str r2, [r3, #0] 8010df4: f3bf 8f4f dsb sy 8010df8: f3bf 8f6f isb sy 8010dfc: e00a b.n 8010e14 else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8010dfe: 6afb ldr r3, [r7, #44] ; 0x2c 8010e00: 2b00 cmp r3, #0 8010e02: d007 beq.n 8010e14 { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 8010e04: 4b39 ldr r3, [pc, #228] ; (8010eec ) 8010e06: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8010e0a: 601a str r2, [r3, #0] 8010e0c: f3bf 8f4f dsb sy 8010e10: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 8010e14: f002 fb26 bl 8013464 return pdPASS; 8010e18: 2301 movs r3, #1 8010e1a: e063 b.n 8010ee4 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8010e1c: 687b ldr r3, [r7, #4] 8010e1e: 2b00 cmp r3, #0 8010e20: d103 bne.n 8010e2a { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8010e22: f002 fb1f bl 8013464 /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8010e26: 2300 movs r3, #0 8010e28: e05c b.n 8010ee4 } else if( xEntryTimeSet == pdFALSE ) 8010e2a: 6b7b ldr r3, [r7, #52] ; 0x34 8010e2c: 2b00 cmp r3, #0 8010e2e: d106 bne.n 8010e3e { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8010e30: f107 0314 add.w r3, r7, #20 8010e34: 4618 mov r0, r3 8010e36: f001 fad5 bl 80123e4 xEntryTimeSet = pdTRUE; 8010e3a: 2301 movs r3, #1 8010e3c: 637b str r3, [r7, #52] ; 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8010e3e: f002 fb11 bl 8013464 /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8010e42: f001 f82f bl 8011ea4 prvLockQueue( pxQueue ); 8010e46: f002 fadd bl 8013404 8010e4a: 6b3b ldr r3, [r7, #48] ; 0x30 8010e4c: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 8010e50: b25b sxtb r3, r3 8010e52: f1b3 3fff cmp.w r3, #4294967295 8010e56: d103 bne.n 8010e60 8010e58: 6b3b ldr r3, [r7, #48] ; 0x30 8010e5a: 2200 movs r2, #0 8010e5c: f883 2044 strb.w r2, [r3, #68] ; 0x44 8010e60: 6b3b ldr r3, [r7, #48] ; 0x30 8010e62: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 8010e66: b25b sxtb r3, r3 8010e68: f1b3 3fff cmp.w r3, #4294967295 8010e6c: d103 bne.n 8010e76 8010e6e: 6b3b ldr r3, [r7, #48] ; 0x30 8010e70: 2200 movs r2, #0 8010e72: f883 2045 strb.w r2, [r3, #69] ; 0x45 8010e76: f002 faf5 bl 8013464 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8010e7a: 1d3a adds r2, r7, #4 8010e7c: f107 0314 add.w r3, r7, #20 8010e80: 4611 mov r1, r2 8010e82: 4618 mov r0, r3 8010e84: f001 fac4 bl 8012410 8010e88: 4603 mov r3, r0 8010e8a: 2b00 cmp r3, #0 8010e8c: d124 bne.n 8010ed8 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 8010e8e: 6b38 ldr r0, [r7, #48] ; 0x30 8010e90: f000 fd31 bl 80118f6 8010e94: 4603 mov r3, r0 8010e96: 2b00 cmp r3, #0 8010e98: d018 beq.n 8010ecc { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 8010e9a: 6b3b ldr r3, [r7, #48] ; 0x30 8010e9c: 3310 adds r3, #16 8010e9e: 687a ldr r2, [r7, #4] 8010ea0: 4611 mov r1, r2 8010ea2: 4618 mov r0, r3 8010ea4: f001 f9ec bl 8012280 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 8010ea8: 6b38 ldr r0, [r7, #48] ; 0x30 8010eaa: f000 fcbc bl 8011826 /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 8010eae: f001 f807 bl 8011ec0 8010eb2: 4603 mov r3, r0 8010eb4: 2b00 cmp r3, #0 8010eb6: f47f af7c bne.w 8010db2 { portYIELD_WITHIN_API(); 8010eba: 4b0c ldr r3, [pc, #48] ; (8010eec ) 8010ebc: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8010ec0: 601a str r2, [r3, #0] 8010ec2: f3bf 8f4f dsb sy 8010ec6: f3bf 8f6f isb sy 8010eca: e772 b.n 8010db2 } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 8010ecc: 6b38 ldr r0, [r7, #48] ; 0x30 8010ece: f000 fcaa bl 8011826 ( void ) xTaskResumeAll(); 8010ed2: f000 fff5 bl 8011ec0 8010ed6: e76c b.n 8010db2 } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8010ed8: 6b38 ldr r0, [r7, #48] ; 0x30 8010eda: f000 fca4 bl 8011826 ( void ) xTaskResumeAll(); 8010ede: f000 ffef bl 8011ec0 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8010ee2: 2300 movs r3, #0 } } /*lint -restore */ } 8010ee4: 4618 mov r0, r3 8010ee6: 3738 adds r7, #56 ; 0x38 8010ee8: 46bd mov sp, r7 8010eea: bd80 pop {r7, pc} 8010eec: e000ed04 .word 0xe000ed04 08010ef0 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8010ef0: b580 push {r7, lr} 8010ef2: b090 sub sp, #64 ; 0x40 8010ef4: af00 add r7, sp, #0 8010ef6: 60f8 str r0, [r7, #12] 8010ef8: 60b9 str r1, [r7, #8] 8010efa: 607a str r2, [r7, #4] 8010efc: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8010efe: 68fb ldr r3, [r7, #12] 8010f00: 63bb str r3, [r7, #56] ; 0x38 configASSERT( pxQueue ); 8010f02: 6bbb ldr r3, [r7, #56] ; 0x38 8010f04: 2b00 cmp r3, #0 8010f06: d10a bne.n 8010f1e __asm volatile 8010f08: f04f 0350 mov.w r3, #80 ; 0x50 8010f0c: f383 8811 msr BASEPRI, r3 8010f10: f3bf 8f6f isb sy 8010f14: f3bf 8f4f dsb sy 8010f18: 62bb str r3, [r7, #40] ; 0x28 } 8010f1a: bf00 nop 8010f1c: e7fe b.n 8010f1c configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8010f1e: 68bb ldr r3, [r7, #8] 8010f20: 2b00 cmp r3, #0 8010f22: d103 bne.n 8010f2c 8010f24: 6bbb ldr r3, [r7, #56] ; 0x38 8010f26: 6c1b ldr r3, [r3, #64] ; 0x40 8010f28: 2b00 cmp r3, #0 8010f2a: d101 bne.n 8010f30 8010f2c: 2301 movs r3, #1 8010f2e: e000 b.n 8010f32 8010f30: 2300 movs r3, #0 8010f32: 2b00 cmp r3, #0 8010f34: d10a bne.n 8010f4c __asm volatile 8010f36: f04f 0350 mov.w r3, #80 ; 0x50 8010f3a: f383 8811 msr BASEPRI, r3 8010f3e: f3bf 8f6f isb sy 8010f42: f3bf 8f4f dsb sy 8010f46: 627b str r3, [r7, #36] ; 0x24 } 8010f48: bf00 nop 8010f4a: e7fe b.n 8010f4a configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8010f4c: 683b ldr r3, [r7, #0] 8010f4e: 2b02 cmp r3, #2 8010f50: d103 bne.n 8010f5a 8010f52: 6bbb ldr r3, [r7, #56] ; 0x38 8010f54: 6bdb ldr r3, [r3, #60] ; 0x3c 8010f56: 2b01 cmp r3, #1 8010f58: d101 bne.n 8010f5e 8010f5a: 2301 movs r3, #1 8010f5c: e000 b.n 8010f60 8010f5e: 2300 movs r3, #0 8010f60: 2b00 cmp r3, #0 8010f62: d10a bne.n 8010f7a __asm volatile 8010f64: f04f 0350 mov.w r3, #80 ; 0x50 8010f68: f383 8811 msr BASEPRI, r3 8010f6c: f3bf 8f6f isb sy 8010f70: f3bf 8f4f dsb sy 8010f74: 623b str r3, [r7, #32] } 8010f76: bf00 nop 8010f78: e7fe b.n 8010f78 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8010f7a: f002 fb25 bl 80135c8 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 8010f7e: f3ef 8211 mrs r2, BASEPRI 8010f82: f04f 0350 mov.w r3, #80 ; 0x50 8010f86: f383 8811 msr BASEPRI, r3 8010f8a: f3bf 8f6f isb sy 8010f8e: f3bf 8f4f dsb sy 8010f92: 61fa str r2, [r7, #28] 8010f94: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 8010f96: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8010f98: 637b str r3, [r7, #52] ; 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8010f9a: 6bbb ldr r3, [r7, #56] ; 0x38 8010f9c: 6b9a ldr r2, [r3, #56] ; 0x38 8010f9e: 6bbb ldr r3, [r7, #56] ; 0x38 8010fa0: 6bdb ldr r3, [r3, #60] ; 0x3c 8010fa2: 429a cmp r2, r3 8010fa4: d302 bcc.n 8010fac 8010fa6: 683b ldr r3, [r7, #0] 8010fa8: 2b02 cmp r3, #2 8010faa: d12f bne.n 801100c { const int8_t cTxLock = pxQueue->cTxLock; 8010fac: 6bbb ldr r3, [r7, #56] ; 0x38 8010fae: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 8010fb2: f887 3033 strb.w r3, [r7, #51] ; 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 8010fb6: 6bbb ldr r3, [r7, #56] ; 0x38 8010fb8: 6b9b ldr r3, [r3, #56] ; 0x38 8010fba: 62fb str r3, [r7, #44] ; 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8010fbc: 683a ldr r2, [r7, #0] 8010fbe: 68b9 ldr r1, [r7, #8] 8010fc0: 6bb8 ldr r0, [r7, #56] ; 0x38 8010fc2: f000 fba0 bl 8011706 /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 8010fc6: f997 3033 ldrsb.w r3, [r7, #51] ; 0x33 8010fca: f1b3 3fff cmp.w r3, #4294967295 8010fce: d112 bne.n 8010ff6 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8010fd0: 6bbb ldr r3, [r7, #56] ; 0x38 8010fd2: 6a5b ldr r3, [r3, #36] ; 0x24 8010fd4: 2b00 cmp r3, #0 8010fd6: d016 beq.n 8011006 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8010fd8: 6bbb ldr r3, [r7, #56] ; 0x38 8010fda: 3324 adds r3, #36 ; 0x24 8010fdc: 4618 mov r0, r3 8010fde: f001 f99f bl 8012320 8010fe2: 4603 mov r3, r0 8010fe4: 2b00 cmp r3, #0 8010fe6: d00e beq.n 8011006 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 8010fe8: 687b ldr r3, [r7, #4] 8010fea: 2b00 cmp r3, #0 8010fec: d00b beq.n 8011006 { *pxHigherPriorityTaskWoken = pdTRUE; 8010fee: 687b ldr r3, [r7, #4] 8010ff0: 2201 movs r2, #1 8010ff2: 601a str r2, [r3, #0] 8010ff4: e007 b.n 8011006 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 8010ff6: f897 3033 ldrb.w r3, [r7, #51] ; 0x33 8010ffa: 3301 adds r3, #1 8010ffc: b2db uxtb r3, r3 8010ffe: b25a sxtb r2, r3 8011000: 6bbb ldr r3, [r7, #56] ; 0x38 8011002: f883 2045 strb.w r2, [r3, #69] ; 0x45 } xReturn = pdPASS; 8011006: 2301 movs r3, #1 8011008: 63fb str r3, [r7, #60] ; 0x3c { 801100a: e001 b.n 8011010 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 801100c: 2300 movs r3, #0 801100e: 63fb str r3, [r7, #60] ; 0x3c 8011010: 6b7b ldr r3, [r7, #52] ; 0x34 8011012: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 8011014: 697b ldr r3, [r7, #20] 8011016: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 801101a: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801101c: 6bfb ldr r3, [r7, #60] ; 0x3c } 801101e: 4618 mov r0, r3 8011020: 3740 adds r7, #64 ; 0x40 8011022: 46bd mov sp, r7 8011024: bd80 pop {r7, pc} 08011026 : /*-----------------------------------------------------------*/ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) { 8011026: b580 push {r7, lr} 8011028: b08e sub sp, #56 ; 0x38 801102a: af00 add r7, sp, #0 801102c: 6078 str r0, [r7, #4] 801102e: 6039 str r1, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8011030: 687b ldr r3, [r7, #4] 8011032: 633b str r3, [r7, #48] ; 0x30 item size is 0. Don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ configASSERT( pxQueue ); 8011034: 6b3b ldr r3, [r7, #48] ; 0x30 8011036: 2b00 cmp r3, #0 8011038: d10a bne.n 8011050 __asm volatile 801103a: f04f 0350 mov.w r3, #80 ; 0x50 801103e: f383 8811 msr BASEPRI, r3 8011042: f3bf 8f6f isb sy 8011046: f3bf 8f4f dsb sy 801104a: 623b str r3, [r7, #32] } 801104c: bf00 nop 801104e: e7fe b.n 801104e /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR() if the item size is not 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 8011050: 6b3b ldr r3, [r7, #48] ; 0x30 8011052: 6c1b ldr r3, [r3, #64] ; 0x40 8011054: 2b00 cmp r3, #0 8011056: d00a beq.n 801106e __asm volatile 8011058: f04f 0350 mov.w r3, #80 ; 0x50 801105c: f383 8811 msr BASEPRI, r3 8011060: f3bf 8f6f isb sy 8011064: f3bf 8f4f dsb sy 8011068: 61fb str r3, [r7, #28] } 801106a: bf00 nop 801106c: e7fe b.n 801106c /* Normally a mutex would not be given from an interrupt, especially if there is a mutex holder, as priority inheritance makes no sense for an interrupts, only tasks. */ configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); 801106e: 6b3b ldr r3, [r7, #48] ; 0x30 8011070: 681b ldr r3, [r3, #0] 8011072: 2b00 cmp r3, #0 8011074: d103 bne.n 801107e 8011076: 6b3b ldr r3, [r7, #48] ; 0x30 8011078: 689b ldr r3, [r3, #8] 801107a: 2b00 cmp r3, #0 801107c: d101 bne.n 8011082 801107e: 2301 movs r3, #1 8011080: e000 b.n 8011084 8011082: 2300 movs r3, #0 8011084: 2b00 cmp r3, #0 8011086: d10a bne.n 801109e __asm volatile 8011088: f04f 0350 mov.w r3, #80 ; 0x50 801108c: f383 8811 msr BASEPRI, r3 8011090: f3bf 8f6f isb sy 8011094: f3bf 8f4f dsb sy 8011098: 61bb str r3, [r7, #24] } 801109a: bf00 nop 801109c: e7fe b.n 801109c that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 801109e: f002 fa93 bl 80135c8 __asm volatile 80110a2: f3ef 8211 mrs r2, BASEPRI 80110a6: f04f 0350 mov.w r3, #80 ; 0x50 80110aa: f383 8811 msr BASEPRI, r3 80110ae: f3bf 8f6f isb sy 80110b2: f3bf 8f4f dsb sy 80110b6: 617a str r2, [r7, #20] 80110b8: 613b str r3, [r7, #16] return ulOriginalBASEPRI; 80110ba: 697b ldr r3, [r7, #20] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80110bc: 62fb str r3, [r7, #44] ; 0x2c { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80110be: 6b3b ldr r3, [r7, #48] ; 0x30 80110c0: 6b9b ldr r3, [r3, #56] ; 0x38 80110c2: 62bb str r3, [r7, #40] ; 0x28 /* When the queue is used to implement a semaphore no data is ever moved through the queue but it is still valid to see if the queue 'has space'. */ if( uxMessagesWaiting < pxQueue->uxLength ) 80110c4: 6b3b ldr r3, [r7, #48] ; 0x30 80110c6: 6bdb ldr r3, [r3, #60] ; 0x3c 80110c8: 6aba ldr r2, [r7, #40] ; 0x28 80110ca: 429a cmp r2, r3 80110cc: d22b bcs.n 8011126 { const int8_t cTxLock = pxQueue->cTxLock; 80110ce: 6b3b ldr r3, [r7, #48] ; 0x30 80110d0: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 80110d4: f887 3027 strb.w r3, [r7, #39] ; 0x27 holder - and if there is a mutex holder then the mutex cannot be given from an ISR. As this is the ISR version of the function it can be assumed there is no mutex holder and no need to determine if priority disinheritance is needed. Simply increase the count of messages (semaphores) available. */ pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 80110d8: 6abb ldr r3, [r7, #40] ; 0x28 80110da: 1c5a adds r2, r3, #1 80110dc: 6b3b ldr r3, [r7, #48] ; 0x30 80110de: 639a str r2, [r3, #56] ; 0x38 /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80110e0: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 80110e4: f1b3 3fff cmp.w r3, #4294967295 80110e8: d112 bne.n 8011110 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80110ea: 6b3b ldr r3, [r7, #48] ; 0x30 80110ec: 6a5b ldr r3, [r3, #36] ; 0x24 80110ee: 2b00 cmp r3, #0 80110f0: d016 beq.n 8011120 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80110f2: 6b3b ldr r3, [r7, #48] ; 0x30 80110f4: 3324 adds r3, #36 ; 0x24 80110f6: 4618 mov r0, r3 80110f8: f001 f912 bl 8012320 80110fc: 4603 mov r3, r0 80110fe: 2b00 cmp r3, #0 8011100: d00e beq.n 8011120 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 8011102: 683b ldr r3, [r7, #0] 8011104: 2b00 cmp r3, #0 8011106: d00b beq.n 8011120 { *pxHigherPriorityTaskWoken = pdTRUE; 8011108: 683b ldr r3, [r7, #0] 801110a: 2201 movs r2, #1 801110c: 601a str r2, [r3, #0] 801110e: e007 b.n 8011120 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 8011110: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8011114: 3301 adds r3, #1 8011116: b2db uxtb r3, r3 8011118: b25a sxtb r2, r3 801111a: 6b3b ldr r3, [r7, #48] ; 0x30 801111c: f883 2045 strb.w r2, [r3, #69] ; 0x45 } xReturn = pdPASS; 8011120: 2301 movs r3, #1 8011122: 637b str r3, [r7, #52] ; 0x34 8011124: e001 b.n 801112a } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 8011126: 2300 movs r3, #0 8011128: 637b str r3, [r7, #52] ; 0x34 801112a: 6afb ldr r3, [r7, #44] ; 0x2c 801112c: 60fb str r3, [r7, #12] __asm volatile 801112e: 68fb ldr r3, [r7, #12] 8011130: f383 8811 msr BASEPRI, r3 } 8011134: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8011136: 6b7b ldr r3, [r7, #52] ; 0x34 } 8011138: 4618 mov r0, r3 801113a: 3738 adds r7, #56 ; 0x38 801113c: 46bd mov sp, r7 801113e: bd80 pop {r7, pc} 08011140 : /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 8011140: b580 push {r7, lr} 8011142: b08c sub sp, #48 ; 0x30 8011144: af00 add r7, sp, #0 8011146: 60f8 str r0, [r7, #12] 8011148: 60b9 str r1, [r7, #8] 801114a: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 801114c: 2300 movs r3, #0 801114e: 62fb str r3, [r7, #44] ; 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8011150: 68fb ldr r3, [r7, #12] 8011152: 62bb str r3, [r7, #40] ; 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8011154: 6abb ldr r3, [r7, #40] ; 0x28 8011156: 2b00 cmp r3, #0 8011158: d10a bne.n 8011170 __asm volatile 801115a: f04f 0350 mov.w r3, #80 ; 0x50 801115e: f383 8811 msr BASEPRI, r3 8011162: f3bf 8f6f isb sy 8011166: f3bf 8f4f dsb sy 801116a: 623b str r3, [r7, #32] } 801116c: bf00 nop 801116e: e7fe b.n 801116e /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8011170: 68bb ldr r3, [r7, #8] 8011172: 2b00 cmp r3, #0 8011174: d103 bne.n 801117e 8011176: 6abb ldr r3, [r7, #40] ; 0x28 8011178: 6c1b ldr r3, [r3, #64] ; 0x40 801117a: 2b00 cmp r3, #0 801117c: d101 bne.n 8011182 801117e: 2301 movs r3, #1 8011180: e000 b.n 8011184 8011182: 2300 movs r3, #0 8011184: 2b00 cmp r3, #0 8011186: d10a bne.n 801119e __asm volatile 8011188: f04f 0350 mov.w r3, #80 ; 0x50 801118c: f383 8811 msr BASEPRI, r3 8011190: f3bf 8f6f isb sy 8011194: f3bf 8f4f dsb sy 8011198: 61fb str r3, [r7, #28] } 801119a: bf00 nop 801119c: e7fe b.n 801119c /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 801119e: f001 fab3 bl 8012708 80111a2: 4603 mov r3, r0 80111a4: 2b00 cmp r3, #0 80111a6: d102 bne.n 80111ae 80111a8: 687b ldr r3, [r7, #4] 80111aa: 2b00 cmp r3, #0 80111ac: d101 bne.n 80111b2 80111ae: 2301 movs r3, #1 80111b0: e000 b.n 80111b4 80111b2: 2300 movs r3, #0 80111b4: 2b00 cmp r3, #0 80111b6: d10a bne.n 80111ce __asm volatile 80111b8: f04f 0350 mov.w r3, #80 ; 0x50 80111bc: f383 8811 msr BASEPRI, r3 80111c0: f3bf 8f6f isb sy 80111c4: f3bf 8f4f dsb sy 80111c8: 61bb str r3, [r7, #24] } 80111ca: bf00 nop 80111cc: e7fe b.n 80111cc /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80111ce: f002 f919 bl 8013404 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80111d2: 6abb ldr r3, [r7, #40] ; 0x28 80111d4: 6b9b ldr r3, [r3, #56] ; 0x38 80111d6: 627b str r3, [r7, #36] ; 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80111d8: 6a7b ldr r3, [r7, #36] ; 0x24 80111da: 2b00 cmp r3, #0 80111dc: d01f beq.n 801121e { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 80111de: 68b9 ldr r1, [r7, #8] 80111e0: 6ab8 ldr r0, [r7, #40] ; 0x28 80111e2: f000 fafa bl 80117da traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80111e6: 6a7b ldr r3, [r7, #36] ; 0x24 80111e8: 1e5a subs r2, r3, #1 80111ea: 6abb ldr r3, [r7, #40] ; 0x28 80111ec: 639a str r2, [r3, #56] ; 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80111ee: 6abb ldr r3, [r7, #40] ; 0x28 80111f0: 691b ldr r3, [r3, #16] 80111f2: 2b00 cmp r3, #0 80111f4: d00f beq.n 8011216 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80111f6: 6abb ldr r3, [r7, #40] ; 0x28 80111f8: 3310 adds r3, #16 80111fa: 4618 mov r0, r3 80111fc: f001 f890 bl 8012320 8011200: 4603 mov r3, r0 8011202: 2b00 cmp r3, #0 8011204: d007 beq.n 8011216 { queueYIELD_IF_USING_PREEMPTION(); 8011206: 4b3d ldr r3, [pc, #244] ; (80112fc ) 8011208: f04f 5280 mov.w r2, #268435456 ; 0x10000000 801120c: 601a str r2, [r3, #0] 801120e: f3bf 8f4f dsb sy 8011212: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8011216: f002 f925 bl 8013464 return pdPASS; 801121a: 2301 movs r3, #1 801121c: e069 b.n 80112f2 } else { if( xTicksToWait == ( TickType_t ) 0 ) 801121e: 687b ldr r3, [r7, #4] 8011220: 2b00 cmp r3, #0 8011222: d103 bne.n 801122c { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8011224: f002 f91e bl 8013464 traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8011228: 2300 movs r3, #0 801122a: e062 b.n 80112f2 } else if( xEntryTimeSet == pdFALSE ) 801122c: 6afb ldr r3, [r7, #44] ; 0x2c 801122e: 2b00 cmp r3, #0 8011230: d106 bne.n 8011240 { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8011232: f107 0310 add.w r3, r7, #16 8011236: 4618 mov r0, r3 8011238: f001 f8d4 bl 80123e4 xEntryTimeSet = pdTRUE; 801123c: 2301 movs r3, #1 801123e: 62fb str r3, [r7, #44] ; 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8011240: f002 f910 bl 8013464 /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8011244: f000 fe2e bl 8011ea4 prvLockQueue( pxQueue ); 8011248: f002 f8dc bl 8013404 801124c: 6abb ldr r3, [r7, #40] ; 0x28 801124e: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 8011252: b25b sxtb r3, r3 8011254: f1b3 3fff cmp.w r3, #4294967295 8011258: d103 bne.n 8011262 801125a: 6abb ldr r3, [r7, #40] ; 0x28 801125c: 2200 movs r2, #0 801125e: f883 2044 strb.w r2, [r3, #68] ; 0x44 8011262: 6abb ldr r3, [r7, #40] ; 0x28 8011264: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 8011268: b25b sxtb r3, r3 801126a: f1b3 3fff cmp.w r3, #4294967295 801126e: d103 bne.n 8011278 8011270: 6abb ldr r3, [r7, #40] ; 0x28 8011272: 2200 movs r2, #0 8011274: f883 2045 strb.w r2, [r3, #69] ; 0x45 8011278: f002 f8f4 bl 8013464 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 801127c: 1d3a adds r2, r7, #4 801127e: f107 0310 add.w r3, r7, #16 8011282: 4611 mov r1, r2 8011284: 4618 mov r0, r3 8011286: f001 f8c3 bl 8012410 801128a: 4603 mov r3, r0 801128c: 2b00 cmp r3, #0 801128e: d123 bne.n 80112d8 { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8011290: 6ab8 ldr r0, [r7, #40] ; 0x28 8011292: f000 fb1a bl 80118ca 8011296: 4603 mov r3, r0 8011298: 2b00 cmp r3, #0 801129a: d017 beq.n 80112cc { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 801129c: 6abb ldr r3, [r7, #40] ; 0x28 801129e: 3324 adds r3, #36 ; 0x24 80112a0: 687a ldr r2, [r7, #4] 80112a2: 4611 mov r1, r2 80112a4: 4618 mov r0, r3 80112a6: f000 ffeb bl 8012280 prvUnlockQueue( pxQueue ); 80112aa: 6ab8 ldr r0, [r7, #40] ; 0x28 80112ac: f000 fabb bl 8011826 if( xTaskResumeAll() == pdFALSE ) 80112b0: f000 fe06 bl 8011ec0 80112b4: 4603 mov r3, r0 80112b6: 2b00 cmp r3, #0 80112b8: d189 bne.n 80111ce { portYIELD_WITHIN_API(); 80112ba: 4b10 ldr r3, [pc, #64] ; (80112fc ) 80112bc: f04f 5280 mov.w r2, #268435456 ; 0x10000000 80112c0: 601a str r2, [r3, #0] 80112c2: f3bf 8f4f dsb sy 80112c6: f3bf 8f6f isb sy 80112ca: e780 b.n 80111ce } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 80112cc: 6ab8 ldr r0, [r7, #40] ; 0x28 80112ce: f000 faaa bl 8011826 ( void ) xTaskResumeAll(); 80112d2: f000 fdf5 bl 8011ec0 80112d6: e77a b.n 80111ce } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 80112d8: 6ab8 ldr r0, [r7, #40] ; 0x28 80112da: f000 faa4 bl 8011826 ( void ) xTaskResumeAll(); 80112de: f000 fdef bl 8011ec0 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80112e2: 6ab8 ldr r0, [r7, #40] ; 0x28 80112e4: f000 faf1 bl 80118ca 80112e8: 4603 mov r3, r0 80112ea: 2b00 cmp r3, #0 80112ec: f43f af6f beq.w 80111ce { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 80112f0: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 80112f2: 4618 mov r0, r3 80112f4: 3730 adds r7, #48 ; 0x30 80112f6: 46bd mov sp, r7 80112f8: bd80 pop {r7, pc} 80112fa: bf00 nop 80112fc: e000ed04 .word 0xe000ed04 08011300 : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 8011300: b580 push {r7, lr} 8011302: b08e sub sp, #56 ; 0x38 8011304: af00 add r7, sp, #0 8011306: 6078 str r0, [r7, #4] 8011308: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 801130a: 2300 movs r3, #0 801130c: 637b str r3, [r7, #52] ; 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 801130e: 687b ldr r3, [r7, #4] 8011310: 62fb str r3, [r7, #44] ; 0x2c #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 8011312: 2300 movs r3, #0 8011314: 633b str r3, [r7, #48] ; 0x30 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8011316: 6afb ldr r3, [r7, #44] ; 0x2c 8011318: 2b00 cmp r3, #0 801131a: d10a bne.n 8011332 __asm volatile 801131c: f04f 0350 mov.w r3, #80 ; 0x50 8011320: f383 8811 msr BASEPRI, r3 8011324: f3bf 8f6f isb sy 8011328: f3bf 8f4f dsb sy 801132c: 623b str r3, [r7, #32] } 801132e: bf00 nop 8011330: e7fe b.n 8011330 /* Check this really is a semaphore, in which case the item size will be 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 8011332: 6afb ldr r3, [r7, #44] ; 0x2c 8011334: 6c1b ldr r3, [r3, #64] ; 0x40 8011336: 2b00 cmp r3, #0 8011338: d00a beq.n 8011350 __asm volatile 801133a: f04f 0350 mov.w r3, #80 ; 0x50 801133e: f383 8811 msr BASEPRI, r3 8011342: f3bf 8f6f isb sy 8011346: f3bf 8f4f dsb sy 801134a: 61fb str r3, [r7, #28] } 801134c: bf00 nop 801134e: e7fe b.n 801134e /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8011350: f001 f9da bl 8012708 8011354: 4603 mov r3, r0 8011356: 2b00 cmp r3, #0 8011358: d102 bne.n 8011360 801135a: 683b ldr r3, [r7, #0] 801135c: 2b00 cmp r3, #0 801135e: d101 bne.n 8011364 8011360: 2301 movs r3, #1 8011362: e000 b.n 8011366 8011364: 2300 movs r3, #0 8011366: 2b00 cmp r3, #0 8011368: d10a bne.n 8011380 __asm volatile 801136a: f04f 0350 mov.w r3, #80 ; 0x50 801136e: f383 8811 msr BASEPRI, r3 8011372: f3bf 8f6f isb sy 8011376: f3bf 8f4f dsb sy 801137a: 61bb str r3, [r7, #24] } 801137c: bf00 nop 801137e: e7fe b.n 801137e /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8011380: f002 f840 bl 8013404 { /* Semaphores are queues with an item size of 0, and where the number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 8011384: 6afb ldr r3, [r7, #44] ; 0x2c 8011386: 6b9b ldr r3, [r3, #56] ; 0x38 8011388: 62bb str r3, [r7, #40] ; 0x28 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 801138a: 6abb ldr r3, [r7, #40] ; 0x28 801138c: 2b00 cmp r3, #0 801138e: d024 beq.n 80113da { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 8011390: 6abb ldr r3, [r7, #40] ; 0x28 8011392: 1e5a subs r2, r3, #1 8011394: 6afb ldr r3, [r7, #44] ; 0x2c 8011396: 639a str r2, [r3, #56] ; 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8011398: 6afb ldr r3, [r7, #44] ; 0x2c 801139a: 681b ldr r3, [r3, #0] 801139c: 2b00 cmp r3, #0 801139e: d104 bne.n 80113aa { /* Record the information required to implement priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 80113a0: f001 fb5a bl 8012a58 80113a4: 4602 mov r2, r0 80113a6: 6afb ldr r3, [r7, #44] ; 0x2c 80113a8: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80113aa: 6afb ldr r3, [r7, #44] ; 0x2c 80113ac: 691b ldr r3, [r3, #16] 80113ae: 2b00 cmp r3, #0 80113b0: d00f beq.n 80113d2 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80113b2: 6afb ldr r3, [r7, #44] ; 0x2c 80113b4: 3310 adds r3, #16 80113b6: 4618 mov r0, r3 80113b8: f000 ffb2 bl 8012320 80113bc: 4603 mov r3, r0 80113be: 2b00 cmp r3, #0 80113c0: d007 beq.n 80113d2 { queueYIELD_IF_USING_PREEMPTION(); 80113c2: 4b54 ldr r3, [pc, #336] ; (8011514 ) 80113c4: f04f 5280 mov.w r2, #268435456 ; 0x10000000 80113c8: 601a str r2, [r3, #0] 80113ca: f3bf 8f4f dsb sy 80113ce: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 80113d2: f002 f847 bl 8013464 return pdPASS; 80113d6: 2301 movs r3, #1 80113d8: e097 b.n 801150a } else { if( xTicksToWait == ( TickType_t ) 0 ) 80113da: 683b ldr r3, [r7, #0] 80113dc: 2b00 cmp r3, #0 80113de: d111 bne.n 8011404 /* For inheritance to have occurred there must have been an initial timeout, and an adjusted timeout cannot become 0, as if it were 0 the function would have exited. */ #if( configUSE_MUTEXES == 1 ) { configASSERT( xInheritanceOccurred == pdFALSE ); 80113e0: 6b3b ldr r3, [r7, #48] ; 0x30 80113e2: 2b00 cmp r3, #0 80113e4: d00a beq.n 80113fc __asm volatile 80113e6: f04f 0350 mov.w r3, #80 ; 0x50 80113ea: f383 8811 msr BASEPRI, r3 80113ee: f3bf 8f6f isb sy 80113f2: f3bf 8f4f dsb sy 80113f6: 617b str r3, [r7, #20] } 80113f8: bf00 nop 80113fa: e7fe b.n 80113fa } #endif /* configUSE_MUTEXES */ /* The semaphore count was 0 and no block time is specified (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 80113fc: f002 f832 bl 8013464 traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8011400: 2300 movs r3, #0 8011402: e082 b.n 801150a } else if( xEntryTimeSet == pdFALSE ) 8011404: 6b7b ldr r3, [r7, #52] ; 0x34 8011406: 2b00 cmp r3, #0 8011408: d106 bne.n 8011418 { /* The semaphore count was 0 and a block time was specified so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 801140a: f107 030c add.w r3, r7, #12 801140e: 4618 mov r0, r3 8011410: f000 ffe8 bl 80123e4 xEntryTimeSet = pdTRUE; 8011414: 2301 movs r3, #1 8011416: 637b str r3, [r7, #52] ; 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8011418: f002 f824 bl 8013464 /* Interrupts and other tasks can give to and take from the semaphore now the critical section has been exited. */ vTaskSuspendAll(); 801141c: f000 fd42 bl 8011ea4 prvLockQueue( pxQueue ); 8011420: f001 fff0 bl 8013404 8011424: 6afb ldr r3, [r7, #44] ; 0x2c 8011426: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 801142a: b25b sxtb r3, r3 801142c: f1b3 3fff cmp.w r3, #4294967295 8011430: d103 bne.n 801143a 8011432: 6afb ldr r3, [r7, #44] ; 0x2c 8011434: 2200 movs r2, #0 8011436: f883 2044 strb.w r2, [r3, #68] ; 0x44 801143a: 6afb ldr r3, [r7, #44] ; 0x2c 801143c: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 8011440: b25b sxtb r3, r3 8011442: f1b3 3fff cmp.w r3, #4294967295 8011446: d103 bne.n 8011450 8011448: 6afb ldr r3, [r7, #44] ; 0x2c 801144a: 2200 movs r2, #0 801144c: f883 2045 strb.w r2, [r3, #69] ; 0x45 8011450: f002 f808 bl 8013464 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8011454: 463a mov r2, r7 8011456: f107 030c add.w r3, r7, #12 801145a: 4611 mov r1, r2 801145c: 4618 mov r0, r3 801145e: f000 ffd7 bl 8012410 8011462: 4603 mov r3, r0 8011464: 2b00 cmp r3, #0 8011466: d132 bne.n 80114ce { /* A block time is specified and not expired. If the semaphore count is 0 then enter the Blocked state to wait for a semaphore to become available. As semaphores are implemented with queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8011468: 6af8 ldr r0, [r7, #44] ; 0x2c 801146a: f000 fa2e bl 80118ca 801146e: 4603 mov r3, r0 8011470: 2b00 cmp r3, #0 8011472: d026 beq.n 80114c2 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8011474: 6afb ldr r3, [r7, #44] ; 0x2c 8011476: 681b ldr r3, [r3, #0] 8011478: 2b00 cmp r3, #0 801147a: d109 bne.n 8011490 { taskENTER_CRITICAL(); 801147c: f001 ffc2 bl 8013404 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 8011480: 6afb ldr r3, [r7, #44] ; 0x2c 8011482: 689b ldr r3, [r3, #8] 8011484: 4618 mov r0, r3 8011486: f001 f95d bl 8012744 801148a: 6338 str r0, [r7, #48] ; 0x30 } taskEXIT_CRITICAL(); 801148c: f001 ffea bl 8013464 mtCOVERAGE_TEST_MARKER(); } } #endif vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8011490: 6afb ldr r3, [r7, #44] ; 0x2c 8011492: 3324 adds r3, #36 ; 0x24 8011494: 683a ldr r2, [r7, #0] 8011496: 4611 mov r1, r2 8011498: 4618 mov r0, r3 801149a: f000 fef1 bl 8012280 prvUnlockQueue( pxQueue ); 801149e: 6af8 ldr r0, [r7, #44] ; 0x2c 80114a0: f000 f9c1 bl 8011826 if( xTaskResumeAll() == pdFALSE ) 80114a4: f000 fd0c bl 8011ec0 80114a8: 4603 mov r3, r0 80114aa: 2b00 cmp r3, #0 80114ac: f47f af68 bne.w 8011380 { portYIELD_WITHIN_API(); 80114b0: 4b18 ldr r3, [pc, #96] ; (8011514 ) 80114b2: f04f 5280 mov.w r2, #268435456 ; 0x10000000 80114b6: 601a str r2, [r3, #0] 80114b8: f3bf 8f4f dsb sy 80114bc: f3bf 8f6f isb sy 80114c0: e75e b.n 8011380 } else { /* There was no timeout and the semaphore count was not 0, so attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 80114c2: 6af8 ldr r0, [r7, #44] ; 0x2c 80114c4: f000 f9af bl 8011826 ( void ) xTaskResumeAll(); 80114c8: f000 fcfa bl 8011ec0 80114cc: e758 b.n 8011380 } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 80114ce: 6af8 ldr r0, [r7, #44] ; 0x2c 80114d0: f000 f9a9 bl 8011826 ( void ) xTaskResumeAll(); 80114d4: f000 fcf4 bl 8011ec0 /* If the semaphore count is 0 exit now as the timeout has expired. Otherwise return to attempt to take the semaphore that is known to be available. As semaphores are implemented by queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80114d8: 6af8 ldr r0, [r7, #44] ; 0x2c 80114da: f000 f9f6 bl 80118ca 80114de: 4603 mov r3, r0 80114e0: 2b00 cmp r3, #0 80114e2: f43f af4d beq.w 8011380 #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 80114e6: 6b3b ldr r3, [r7, #48] ; 0x30 80114e8: 2b00 cmp r3, #0 80114ea: d00d beq.n 8011508 { taskENTER_CRITICAL(); 80114ec: f001 ff8a bl 8013404 /* This task blocking on the mutex caused another task to inherit this task's priority. Now this task has timed out the priority should be disinherited again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 80114f0: 6af8 ldr r0, [r7, #44] ; 0x2c 80114f2: f000 f8f0 bl 80116d6 80114f6: 6278 str r0, [r7, #36] ; 0x24 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 80114f8: 6afb ldr r3, [r7, #44] ; 0x2c 80114fa: 689b ldr r3, [r3, #8] 80114fc: 6a79 ldr r1, [r7, #36] ; 0x24 80114fe: 4618 mov r0, r3 8011500: f001 fa1c bl 801293c } taskEXIT_CRITICAL(); 8011504: f001 ffae bl 8013464 } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8011508: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 801150a: 4618 mov r0, r3 801150c: 3738 adds r7, #56 ; 0x38 801150e: 46bd mov sp, r7 8011510: bd80 pop {r7, pc} 8011512: bf00 nop 8011514: e000ed04 .word 0xe000ed04 08011518 : } /*lint -restore */ } /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 8011518: b580 push {r7, lr} 801151a: b08e sub sp, #56 ; 0x38 801151c: af00 add r7, sp, #0 801151e: 60f8 str r0, [r7, #12] 8011520: 60b9 str r1, [r7, #8] 8011522: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8011524: 68fb ldr r3, [r7, #12] 8011526: 633b str r3, [r7, #48] ; 0x30 configASSERT( pxQueue ); 8011528: 6b3b ldr r3, [r7, #48] ; 0x30 801152a: 2b00 cmp r3, #0 801152c: d10a bne.n 8011544 __asm volatile 801152e: f04f 0350 mov.w r3, #80 ; 0x50 8011532: f383 8811 msr BASEPRI, r3 8011536: f3bf 8f6f isb sy 801153a: f3bf 8f4f dsb sy 801153e: 623b str r3, [r7, #32] } 8011540: bf00 nop 8011542: e7fe b.n 8011542 configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8011544: 68bb ldr r3, [r7, #8] 8011546: 2b00 cmp r3, #0 8011548: d103 bne.n 8011552 801154a: 6b3b ldr r3, [r7, #48] ; 0x30 801154c: 6c1b ldr r3, [r3, #64] ; 0x40 801154e: 2b00 cmp r3, #0 8011550: d101 bne.n 8011556 8011552: 2301 movs r3, #1 8011554: e000 b.n 8011558 8011556: 2300 movs r3, #0 8011558: 2b00 cmp r3, #0 801155a: d10a bne.n 8011572 __asm volatile 801155c: f04f 0350 mov.w r3, #80 ; 0x50 8011560: f383 8811 msr BASEPRI, r3 8011564: f3bf 8f6f isb sy 8011568: f3bf 8f4f dsb sy 801156c: 61fb str r3, [r7, #28] } 801156e: bf00 nop 8011570: e7fe b.n 8011570 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8011572: f002 f829 bl 80135c8 __asm volatile 8011576: f3ef 8211 mrs r2, BASEPRI 801157a: f04f 0350 mov.w r3, #80 ; 0x50 801157e: f383 8811 msr BASEPRI, r3 8011582: f3bf 8f6f isb sy 8011586: f3bf 8f4f dsb sy 801158a: 61ba str r2, [r7, #24] 801158c: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 801158e: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8011590: 62fb str r3, [r7, #44] ; 0x2c { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8011592: 6b3b ldr r3, [r7, #48] ; 0x30 8011594: 6b9b ldr r3, [r3, #56] ; 0x38 8011596: 62bb str r3, [r7, #40] ; 0x28 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8011598: 6abb ldr r3, [r7, #40] ; 0x28 801159a: 2b00 cmp r3, #0 801159c: d02f beq.n 80115fe { const int8_t cRxLock = pxQueue->cRxLock; 801159e: 6b3b ldr r3, [r7, #48] ; 0x30 80115a0: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 80115a4: f887 3027 strb.w r3, [r7, #39] ; 0x27 traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 80115a8: 68b9 ldr r1, [r7, #8] 80115aa: 6b38 ldr r0, [r7, #48] ; 0x30 80115ac: f000 f915 bl 80117da pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80115b0: 6abb ldr r3, [r7, #40] ; 0x28 80115b2: 1e5a subs r2, r3, #1 80115b4: 6b3b ldr r3, [r7, #48] ; 0x30 80115b6: 639a str r2, [r3, #56] ; 0x38 /* If the queue is locked the event list will not be modified. Instead update the lock count so the task that unlocks the queue will know that an ISR has removed data while the queue was locked. */ if( cRxLock == queueUNLOCKED ) 80115b8: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 80115bc: f1b3 3fff cmp.w r3, #4294967295 80115c0: d112 bne.n 80115e8 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80115c2: 6b3b ldr r3, [r7, #48] ; 0x30 80115c4: 691b ldr r3, [r3, #16] 80115c6: 2b00 cmp r3, #0 80115c8: d016 beq.n 80115f8 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80115ca: 6b3b ldr r3, [r7, #48] ; 0x30 80115cc: 3310 adds r3, #16 80115ce: 4618 mov r0, r3 80115d0: f000 fea6 bl 8012320 80115d4: 4603 mov r3, r0 80115d6: 2b00 cmp r3, #0 80115d8: d00e beq.n 80115f8 { /* The task waiting has a higher priority than us so force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 80115da: 687b ldr r3, [r7, #4] 80115dc: 2b00 cmp r3, #0 80115de: d00b beq.n 80115f8 { *pxHigherPriorityTaskWoken = pdTRUE; 80115e0: 687b ldr r3, [r7, #4] 80115e2: 2201 movs r2, #1 80115e4: 601a str r2, [r3, #0] 80115e6: e007 b.n 80115f8 } else { /* Increment the lock count so the task that unlocks the queue knows that data was removed while it was locked. */ pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); 80115e8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 80115ec: 3301 adds r3, #1 80115ee: b2db uxtb r3, r3 80115f0: b25a sxtb r2, r3 80115f2: 6b3b ldr r3, [r7, #48] ; 0x30 80115f4: f883 2044 strb.w r2, [r3, #68] ; 0x44 } xReturn = pdPASS; 80115f8: 2301 movs r3, #1 80115fa: 637b str r3, [r7, #52] ; 0x34 80115fc: e001 b.n 8011602 } else { xReturn = pdFAIL; 80115fe: 2300 movs r3, #0 8011600: 637b str r3, [r7, #52] ; 0x34 8011602: 6afb ldr r3, [r7, #44] ; 0x2c 8011604: 613b str r3, [r7, #16] __asm volatile 8011606: 693b ldr r3, [r7, #16] 8011608: f383 8811 msr BASEPRI, r3 } 801160c: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801160e: 6b7b ldr r3, [r7, #52] ; 0x34 } 8011610: 4618 mov r0, r3 8011612: 3738 adds r7, #56 ; 0x38 8011614: 46bd mov sp, r7 8011616: bd80 pop {r7, pc} 08011618 : return xReturn; } /*-----------------------------------------------------------*/ UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) { 8011618: b580 push {r7, lr} 801161a: b084 sub sp, #16 801161c: af00 add r7, sp, #0 801161e: 6078 str r0, [r7, #4] UBaseType_t uxReturn; configASSERT( xQueue ); 8011620: 687b ldr r3, [r7, #4] 8011622: 2b00 cmp r3, #0 8011624: d10a bne.n 801163c __asm volatile 8011626: f04f 0350 mov.w r3, #80 ; 0x50 801162a: f383 8811 msr BASEPRI, r3 801162e: f3bf 8f6f isb sy 8011632: f3bf 8f4f dsb sy 8011636: 60bb str r3, [r7, #8] } 8011638: bf00 nop 801163a: e7fe b.n 801163a taskENTER_CRITICAL(); 801163c: f001 fee2 bl 8013404 { uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting; 8011640: 687b ldr r3, [r7, #4] 8011642: 6b9b ldr r3, [r3, #56] ; 0x38 8011644: 60fb str r3, [r7, #12] } taskEXIT_CRITICAL(); 8011646: f001 ff0d bl 8013464 return uxReturn; 801164a: 68fb ldr r3, [r7, #12] } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ 801164c: 4618 mov r0, r3 801164e: 3710 adds r7, #16 8011650: 46bd mov sp, r7 8011652: bd80 pop {r7, pc} 08011654 : return uxReturn; } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ /*-----------------------------------------------------------*/ UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) { 8011654: b480 push {r7} 8011656: b087 sub sp, #28 8011658: af00 add r7, sp, #0 801165a: 6078 str r0, [r7, #4] UBaseType_t uxReturn; Queue_t * const pxQueue = xQueue; 801165c: 687b ldr r3, [r7, #4] 801165e: 617b str r3, [r7, #20] configASSERT( pxQueue ); 8011660: 697b ldr r3, [r7, #20] 8011662: 2b00 cmp r3, #0 8011664: d10a bne.n 801167c __asm volatile 8011666: f04f 0350 mov.w r3, #80 ; 0x50 801166a: f383 8811 msr BASEPRI, r3 801166e: f3bf 8f6f isb sy 8011672: f3bf 8f4f dsb sy 8011676: 60fb str r3, [r7, #12] } 8011678: bf00 nop 801167a: e7fe b.n 801167a uxReturn = pxQueue->uxMessagesWaiting; 801167c: 697b ldr r3, [r7, #20] 801167e: 6b9b ldr r3, [r3, #56] ; 0x38 8011680: 613b str r3, [r7, #16] return uxReturn; 8011682: 693b ldr r3, [r7, #16] } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ 8011684: 4618 mov r0, r3 8011686: 371c adds r7, #28 8011688: 46bd mov sp, r7 801168a: f85d 7b04 ldr.w r7, [sp], #4 801168e: 4770 bx lr 08011690 : /*-----------------------------------------------------------*/ void vQueueDelete( QueueHandle_t xQueue ) { 8011690: b580 push {r7, lr} 8011692: b084 sub sp, #16 8011694: af00 add r7, sp, #0 8011696: 6078 str r0, [r7, #4] Queue_t * const pxQueue = xQueue; 8011698: 687b ldr r3, [r7, #4] 801169a: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 801169c: 68fb ldr r3, [r7, #12] 801169e: 2b00 cmp r3, #0 80116a0: d10a bne.n 80116b8 __asm volatile 80116a2: f04f 0350 mov.w r3, #80 ; 0x50 80116a6: f383 8811 msr BASEPRI, r3 80116aa: f3bf 8f6f isb sy 80116ae: f3bf 8f4f dsb sy 80116b2: 60bb str r3, [r7, #8] } 80116b4: bf00 nop 80116b6: e7fe b.n 80116b6 traceQUEUE_DELETE( pxQueue ); #if ( configQUEUE_REGISTRY_SIZE > 0 ) { vQueueUnregisterQueue( pxQueue ); 80116b8: 68f8 ldr r0, [r7, #12] 80116ba: f000 f95f bl 801197c } #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) { /* The queue could have been allocated statically or dynamically, so check before attempting to free the memory. */ if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) 80116be: 68fb ldr r3, [r7, #12] 80116c0: f893 3046 ldrb.w r3, [r3, #70] ; 0x46 80116c4: 2b00 cmp r3, #0 80116c6: d102 bne.n 80116ce { vPortFree( pxQueue ); 80116c8: 68f8 ldr r0, [r7, #12] 80116ca: f002 f889 bl 80137e0 /* The queue must have been statically allocated, so is not going to be deleted. Avoid compiler warnings about the unused parameter. */ ( void ) pxQueue; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 80116ce: bf00 nop 80116d0: 3710 adds r7, #16 80116d2: 46bd mov sp, r7 80116d4: bd80 pop {r7, pc} 080116d6 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 80116d6: b480 push {r7} 80116d8: b085 sub sp, #20 80116da: af00 add r7, sp, #0 80116dc: 6078 str r0, [r7, #4] priority, but the waiting task times out, then the holder should disinherit the priority - but only down to the highest priority of any other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 80116de: 687b ldr r3, [r7, #4] 80116e0: 6a5b ldr r3, [r3, #36] ; 0x24 80116e2: 2b00 cmp r3, #0 80116e4: d006 beq.n 80116f4 { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 80116e6: 687b ldr r3, [r7, #4] 80116e8: 6b1b ldr r3, [r3, #48] ; 0x30 80116ea: 681b ldr r3, [r3, #0] 80116ec: f1c3 0307 rsb r3, r3, #7 80116f0: 60fb str r3, [r7, #12] 80116f2: e001 b.n 80116f8 } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 80116f4: 2300 movs r3, #0 80116f6: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 80116f8: 68fb ldr r3, [r7, #12] } 80116fa: 4618 mov r0, r3 80116fc: 3714 adds r7, #20 80116fe: 46bd mov sp, r7 8011700: f85d 7b04 ldr.w r7, [sp], #4 8011704: 4770 bx lr 08011706 : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 8011706: b580 push {r7, lr} 8011708: b086 sub sp, #24 801170a: af00 add r7, sp, #0 801170c: 60f8 str r0, [r7, #12] 801170e: 60b9 str r1, [r7, #8] 8011710: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8011712: 2300 movs r3, #0 8011714: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8011716: 68fb ldr r3, [r7, #12] 8011718: 6b9b ldr r3, [r3, #56] ; 0x38 801171a: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 801171c: 68fb ldr r3, [r7, #12] 801171e: 6c1b ldr r3, [r3, #64] ; 0x40 8011720: 2b00 cmp r3, #0 8011722: d10d bne.n 8011740 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8011724: 68fb ldr r3, [r7, #12] 8011726: 681b ldr r3, [r3, #0] 8011728: 2b00 cmp r3, #0 801172a: d14d bne.n 80117c8 { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 801172c: 68fb ldr r3, [r7, #12] 801172e: 689b ldr r3, [r3, #8] 8011730: 4618 mov r0, r3 8011732: f001 f87d bl 8012830 8011736: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 8011738: 68fb ldr r3, [r7, #12] 801173a: 2200 movs r2, #0 801173c: 609a str r2, [r3, #8] 801173e: e043 b.n 80117c8 mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 8011740: 687b ldr r3, [r7, #4] 8011742: 2b00 cmp r3, #0 8011744: d119 bne.n 801177a { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8011746: 68fb ldr r3, [r7, #12] 8011748: 6858 ldr r0, [r3, #4] 801174a: 68fb ldr r3, [r7, #12] 801174c: 6c1b ldr r3, [r3, #64] ; 0x40 801174e: 461a mov r2, r3 8011750: 68b9 ldr r1, [r7, #8] 8011752: f010 fb48 bl 8021de6 pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8011756: 68fb ldr r3, [r7, #12] 8011758: 685a ldr r2, [r3, #4] 801175a: 68fb ldr r3, [r7, #12] 801175c: 6c1b ldr r3, [r3, #64] ; 0x40 801175e: 441a add r2, r3 8011760: 68fb ldr r3, [r7, #12] 8011762: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8011764: 68fb ldr r3, [r7, #12] 8011766: 685a ldr r2, [r3, #4] 8011768: 68fb ldr r3, [r7, #12] 801176a: 689b ldr r3, [r3, #8] 801176c: 429a cmp r2, r3 801176e: d32b bcc.n 80117c8 { pxQueue->pcWriteTo = pxQueue->pcHead; 8011770: 68fb ldr r3, [r7, #12] 8011772: 681a ldr r2, [r3, #0] 8011774: 68fb ldr r3, [r7, #12] 8011776: 605a str r2, [r3, #4] 8011778: e026 b.n 80117c8 mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 801177a: 68fb ldr r3, [r7, #12] 801177c: 68d8 ldr r0, [r3, #12] 801177e: 68fb ldr r3, [r7, #12] 8011780: 6c1b ldr r3, [r3, #64] ; 0x40 8011782: 461a mov r2, r3 8011784: 68b9 ldr r1, [r7, #8] 8011786: f010 fb2e bl 8021de6 pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 801178a: 68fb ldr r3, [r7, #12] 801178c: 68da ldr r2, [r3, #12] 801178e: 68fb ldr r3, [r7, #12] 8011790: 6c1b ldr r3, [r3, #64] ; 0x40 8011792: 425b negs r3, r3 8011794: 441a add r2, r3 8011796: 68fb ldr r3, [r7, #12] 8011798: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 801179a: 68fb ldr r3, [r7, #12] 801179c: 68da ldr r2, [r3, #12] 801179e: 68fb ldr r3, [r7, #12] 80117a0: 681b ldr r3, [r3, #0] 80117a2: 429a cmp r2, r3 80117a4: d207 bcs.n 80117b6 { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 80117a6: 68fb ldr r3, [r7, #12] 80117a8: 689a ldr r2, [r3, #8] 80117aa: 68fb ldr r3, [r7, #12] 80117ac: 6c1b ldr r3, [r3, #64] ; 0x40 80117ae: 425b negs r3, r3 80117b0: 441a add r2, r3 80117b2: 68fb ldr r3, [r7, #12] 80117b4: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 80117b6: 687b ldr r3, [r7, #4] 80117b8: 2b02 cmp r3, #2 80117ba: d105 bne.n 80117c8 { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80117bc: 693b ldr r3, [r7, #16] 80117be: 2b00 cmp r3, #0 80117c0: d002 beq.n 80117c8 { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 80117c2: 693b ldr r3, [r7, #16] 80117c4: 3b01 subs r3, #1 80117c6: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 80117c8: 693b ldr r3, [r7, #16] 80117ca: 1c5a adds r2, r3, #1 80117cc: 68fb ldr r3, [r7, #12] 80117ce: 639a str r2, [r3, #56] ; 0x38 return xReturn; 80117d0: 697b ldr r3, [r7, #20] } 80117d2: 4618 mov r0, r3 80117d4: 3718 adds r7, #24 80117d6: 46bd mov sp, r7 80117d8: bd80 pop {r7, pc} 080117da : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 80117da: b580 push {r7, lr} 80117dc: b082 sub sp, #8 80117de: af00 add r7, sp, #0 80117e0: 6078 str r0, [r7, #4] 80117e2: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 80117e4: 687b ldr r3, [r7, #4] 80117e6: 6c1b ldr r3, [r3, #64] ; 0x40 80117e8: 2b00 cmp r3, #0 80117ea: d018 beq.n 801181e { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 80117ec: 687b ldr r3, [r7, #4] 80117ee: 68da ldr r2, [r3, #12] 80117f0: 687b ldr r3, [r7, #4] 80117f2: 6c1b ldr r3, [r3, #64] ; 0x40 80117f4: 441a add r2, r3 80117f6: 687b ldr r3, [r7, #4] 80117f8: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 80117fa: 687b ldr r3, [r7, #4] 80117fc: 68da ldr r2, [r3, #12] 80117fe: 687b ldr r3, [r7, #4] 8011800: 689b ldr r3, [r3, #8] 8011802: 429a cmp r2, r3 8011804: d303 bcc.n 801180e { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 8011806: 687b ldr r3, [r7, #4] 8011808: 681a ldr r2, [r3, #0] 801180a: 687b ldr r3, [r7, #4] 801180c: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 801180e: 687b ldr r3, [r7, #4] 8011810: 68d9 ldr r1, [r3, #12] 8011812: 687b ldr r3, [r7, #4] 8011814: 6c1b ldr r3, [r3, #64] ; 0x40 8011816: 461a mov r2, r3 8011818: 6838 ldr r0, [r7, #0] 801181a: f010 fae4 bl 8021de6 } } 801181e: bf00 nop 8011820: 3708 adds r7, #8 8011822: 46bd mov sp, r7 8011824: bd80 pop {r7, pc} 08011826 : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 8011826: b580 push {r7, lr} 8011828: b084 sub sp, #16 801182a: af00 add r7, sp, #0 801182c: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 801182e: f001 fde9 bl 8013404 { int8_t cTxLock = pxQueue->cTxLock; 8011832: 687b ldr r3, [r7, #4] 8011834: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 8011838: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 801183a: e011 b.n 8011860 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 801183c: 687b ldr r3, [r7, #4] 801183e: 6a5b ldr r3, [r3, #36] ; 0x24 8011840: 2b00 cmp r3, #0 8011842: d012 beq.n 801186a { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8011844: 687b ldr r3, [r7, #4] 8011846: 3324 adds r3, #36 ; 0x24 8011848: 4618 mov r0, r3 801184a: f000 fd69 bl 8012320 801184e: 4603 mov r3, r0 8011850: 2b00 cmp r3, #0 8011852: d001 beq.n 8011858 { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 8011854: f000 fe3e bl 80124d4 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 8011858: 7bfb ldrb r3, [r7, #15] 801185a: 3b01 subs r3, #1 801185c: b2db uxtb r3, r3 801185e: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 8011860: f997 300f ldrsb.w r3, [r7, #15] 8011864: 2b00 cmp r3, #0 8011866: dce9 bgt.n 801183c 8011868: e000 b.n 801186c break; 801186a: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 801186c: 687b ldr r3, [r7, #4] 801186e: 22ff movs r2, #255 ; 0xff 8011870: f883 2045 strb.w r2, [r3, #69] ; 0x45 } taskEXIT_CRITICAL(); 8011874: f001 fdf6 bl 8013464 /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 8011878: f001 fdc4 bl 8013404 { int8_t cRxLock = pxQueue->cRxLock; 801187c: 687b ldr r3, [r7, #4] 801187e: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 8011882: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8011884: e011 b.n 80118aa { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8011886: 687b ldr r3, [r7, #4] 8011888: 691b ldr r3, [r3, #16] 801188a: 2b00 cmp r3, #0 801188c: d012 beq.n 80118b4 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 801188e: 687b ldr r3, [r7, #4] 8011890: 3310 adds r3, #16 8011892: 4618 mov r0, r3 8011894: f000 fd44 bl 8012320 8011898: 4603 mov r3, r0 801189a: 2b00 cmp r3, #0 801189c: d001 beq.n 80118a2 { vTaskMissedYield(); 801189e: f000 fe19 bl 80124d4 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 80118a2: 7bbb ldrb r3, [r7, #14] 80118a4: 3b01 subs r3, #1 80118a6: b2db uxtb r3, r3 80118a8: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80118aa: f997 300e ldrsb.w r3, [r7, #14] 80118ae: 2b00 cmp r3, #0 80118b0: dce9 bgt.n 8011886 80118b2: e000 b.n 80118b6 } else { break; 80118b4: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 80118b6: 687b ldr r3, [r7, #4] 80118b8: 22ff movs r2, #255 ; 0xff 80118ba: f883 2044 strb.w r2, [r3, #68] ; 0x44 } taskEXIT_CRITICAL(); 80118be: f001 fdd1 bl 8013464 } 80118c2: bf00 nop 80118c4: 3710 adds r7, #16 80118c6: 46bd mov sp, r7 80118c8: bd80 pop {r7, pc} 080118ca : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 80118ca: b580 push {r7, lr} 80118cc: b084 sub sp, #16 80118ce: af00 add r7, sp, #0 80118d0: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 80118d2: f001 fd97 bl 8013404 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 80118d6: 687b ldr r3, [r7, #4] 80118d8: 6b9b ldr r3, [r3, #56] ; 0x38 80118da: 2b00 cmp r3, #0 80118dc: d102 bne.n 80118e4 { xReturn = pdTRUE; 80118de: 2301 movs r3, #1 80118e0: 60fb str r3, [r7, #12] 80118e2: e001 b.n 80118e8 } else { xReturn = pdFALSE; 80118e4: 2300 movs r3, #0 80118e6: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 80118e8: f001 fdbc bl 8013464 return xReturn; 80118ec: 68fb ldr r3, [r7, #12] } 80118ee: 4618 mov r0, r3 80118f0: 3710 adds r7, #16 80118f2: 46bd mov sp, r7 80118f4: bd80 pop {r7, pc} 080118f6 : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 80118f6: b580 push {r7, lr} 80118f8: b084 sub sp, #16 80118fa: af00 add r7, sp, #0 80118fc: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 80118fe: f001 fd81 bl 8013404 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8011902: 687b ldr r3, [r7, #4] 8011904: 6b9a ldr r2, [r3, #56] ; 0x38 8011906: 687b ldr r3, [r7, #4] 8011908: 6bdb ldr r3, [r3, #60] ; 0x3c 801190a: 429a cmp r2, r3 801190c: d102 bne.n 8011914 { xReturn = pdTRUE; 801190e: 2301 movs r3, #1 8011910: 60fb str r3, [r7, #12] 8011912: e001 b.n 8011918 } else { xReturn = pdFALSE; 8011914: 2300 movs r3, #0 8011916: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8011918: f001 fda4 bl 8013464 return xReturn; 801191c: 68fb ldr r3, [r7, #12] } 801191e: 4618 mov r0, r3 8011920: 3710 adds r7, #16 8011922: 46bd mov sp, r7 8011924: bd80 pop {r7, pc} ... 08011928 : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 8011928: b480 push {r7} 801192a: b085 sub sp, #20 801192c: af00 add r7, sp, #0 801192e: 6078 str r0, [r7, #4] 8011930: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8011932: 2300 movs r3, #0 8011934: 60fb str r3, [r7, #12] 8011936: e014 b.n 8011962 { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 8011938: 4a0f ldr r2, [pc, #60] ; (8011978 ) 801193a: 68fb ldr r3, [r7, #12] 801193c: f852 3033 ldr.w r3, [r2, r3, lsl #3] 8011940: 2b00 cmp r3, #0 8011942: d10b bne.n 801195c { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 8011944: 490c ldr r1, [pc, #48] ; (8011978 ) 8011946: 68fb ldr r3, [r7, #12] 8011948: 683a ldr r2, [r7, #0] 801194a: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 801194e: 4a0a ldr r2, [pc, #40] ; (8011978 ) 8011950: 68fb ldr r3, [r7, #12] 8011952: 00db lsls r3, r3, #3 8011954: 4413 add r3, r2 8011956: 687a ldr r2, [r7, #4] 8011958: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 801195a: e006 b.n 801196a for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 801195c: 68fb ldr r3, [r7, #12] 801195e: 3301 adds r3, #1 8011960: 60fb str r3, [r7, #12] 8011962: 68fb ldr r3, [r7, #12] 8011964: 2b07 cmp r3, #7 8011966: d9e7 bls.n 8011938 else { mtCOVERAGE_TEST_MARKER(); } } } 8011968: bf00 nop 801196a: bf00 nop 801196c: 3714 adds r7, #20 801196e: 46bd mov sp, r7 8011970: f85d 7b04 ldr.w r7, [sp], #4 8011974: 4770 bx lr 8011976: bf00 nop 8011978: 2400bee0 .word 0x2400bee0 0801197c : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueUnregisterQueue( QueueHandle_t xQueue ) { 801197c: b480 push {r7} 801197e: b085 sub sp, #20 8011980: af00 add r7, sp, #0 8011982: 6078 str r0, [r7, #4] UBaseType_t ux; /* See if the handle of the queue being unregistered in actually in the registry. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8011984: 2300 movs r3, #0 8011986: 60fb str r3, [r7, #12] 8011988: e016 b.n 80119b8 { if( xQueueRegistry[ ux ].xHandle == xQueue ) 801198a: 4a10 ldr r2, [pc, #64] ; (80119cc ) 801198c: 68fb ldr r3, [r7, #12] 801198e: 00db lsls r3, r3, #3 8011990: 4413 add r3, r2 8011992: 685b ldr r3, [r3, #4] 8011994: 687a ldr r2, [r7, #4] 8011996: 429a cmp r2, r3 8011998: d10b bne.n 80119b2 { /* Set the name to NULL to show that this slot if free again. */ xQueueRegistry[ ux ].pcQueueName = NULL; 801199a: 4a0c ldr r2, [pc, #48] ; (80119cc ) 801199c: 68fb ldr r3, [r7, #12] 801199e: 2100 movs r1, #0 80119a0: f842 1033 str.w r1, [r2, r3, lsl #3] /* Set the handle to NULL to ensure the same queue handle cannot appear in the registry twice if it is added, removed, then added again. */ xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0; 80119a4: 4a09 ldr r2, [pc, #36] ; (80119cc ) 80119a6: 68fb ldr r3, [r7, #12] 80119a8: 00db lsls r3, r3, #3 80119aa: 4413 add r3, r2 80119ac: 2200 movs r2, #0 80119ae: 605a str r2, [r3, #4] break; 80119b0: e006 b.n 80119c0 for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 80119b2: 68fb ldr r3, [r7, #12] 80119b4: 3301 adds r3, #1 80119b6: 60fb str r3, [r7, #12] 80119b8: 68fb ldr r3, [r7, #12] 80119ba: 2b07 cmp r3, #7 80119bc: d9e5 bls.n 801198a { mtCOVERAGE_TEST_MARKER(); } } } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ 80119be: bf00 nop 80119c0: bf00 nop 80119c2: 3714 adds r7, #20 80119c4: 46bd mov sp, r7 80119c6: f85d 7b04 ldr.w r7, [sp], #4 80119ca: 4770 bx lr 80119cc: 2400bee0 .word 0x2400bee0 080119d0 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 80119d0: b580 push {r7, lr} 80119d2: b086 sub sp, #24 80119d4: af00 add r7, sp, #0 80119d6: 60f8 str r0, [r7, #12] 80119d8: 60b9 str r1, [r7, #8] 80119da: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 80119dc: 68fb ldr r3, [r7, #12] 80119de: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 80119e0: f001 fd10 bl 8013404 80119e4: 697b ldr r3, [r7, #20] 80119e6: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 80119ea: b25b sxtb r3, r3 80119ec: f1b3 3fff cmp.w r3, #4294967295 80119f0: d103 bne.n 80119fa 80119f2: 697b ldr r3, [r7, #20] 80119f4: 2200 movs r2, #0 80119f6: f883 2044 strb.w r2, [r3, #68] ; 0x44 80119fa: 697b ldr r3, [r7, #20] 80119fc: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 8011a00: b25b sxtb r3, r3 8011a02: f1b3 3fff cmp.w r3, #4294967295 8011a06: d103 bne.n 8011a10 8011a08: 697b ldr r3, [r7, #20] 8011a0a: 2200 movs r2, #0 8011a0c: f883 2045 strb.w r2, [r3, #69] ; 0x45 8011a10: f001 fd28 bl 8013464 if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 8011a14: 697b ldr r3, [r7, #20] 8011a16: 6b9b ldr r3, [r3, #56] ; 0x38 8011a18: 2b00 cmp r3, #0 8011a1a: d106 bne.n 8011a2a { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 8011a1c: 697b ldr r3, [r7, #20] 8011a1e: 3324 adds r3, #36 ; 0x24 8011a20: 687a ldr r2, [r7, #4] 8011a22: 68b9 ldr r1, [r7, #8] 8011a24: 4618 mov r0, r3 8011a26: f000 fc4f bl 80122c8 } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 8011a2a: 6978 ldr r0, [r7, #20] 8011a2c: f7ff fefb bl 8011826 } 8011a30: bf00 nop 8011a32: 3718 adds r7, #24 8011a34: 46bd mov sp, r7 8011a36: bd80 pop {r7, pc} 08011a38 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 8011a38: b580 push {r7, lr} 8011a3a: b08e sub sp, #56 ; 0x38 8011a3c: af04 add r7, sp, #16 8011a3e: 60f8 str r0, [r7, #12] 8011a40: 60b9 str r1, [r7, #8] 8011a42: 607a str r2, [r7, #4] 8011a44: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 8011a46: 6b7b ldr r3, [r7, #52] ; 0x34 8011a48: 2b00 cmp r3, #0 8011a4a: d10a bne.n 8011a62 __asm volatile 8011a4c: f04f 0350 mov.w r3, #80 ; 0x50 8011a50: f383 8811 msr BASEPRI, r3 8011a54: f3bf 8f6f isb sy 8011a58: f3bf 8f4f dsb sy 8011a5c: 623b str r3, [r7, #32] } 8011a5e: bf00 nop 8011a60: e7fe b.n 8011a60 configASSERT( pxTaskBuffer != NULL ); 8011a62: 6bbb ldr r3, [r7, #56] ; 0x38 8011a64: 2b00 cmp r3, #0 8011a66: d10a bne.n 8011a7e __asm volatile 8011a68: f04f 0350 mov.w r3, #80 ; 0x50 8011a6c: f383 8811 msr BASEPRI, r3 8011a70: f3bf 8f6f isb sy 8011a74: f3bf 8f4f dsb sy 8011a78: 61fb str r3, [r7, #28] } 8011a7a: bf00 nop 8011a7c: e7fe b.n 8011a7c #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 8011a7e: 2354 movs r3, #84 ; 0x54 8011a80: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8011a82: 693b ldr r3, [r7, #16] 8011a84: 2b54 cmp r3, #84 ; 0x54 8011a86: d00a beq.n 8011a9e __asm volatile 8011a88: f04f 0350 mov.w r3, #80 ; 0x50 8011a8c: f383 8811 msr BASEPRI, r3 8011a90: f3bf 8f6f isb sy 8011a94: f3bf 8f4f dsb sy 8011a98: 61bb str r3, [r7, #24] } 8011a9a: bf00 nop 8011a9c: e7fe b.n 8011a9c ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8011a9e: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8011aa0: 6bbb ldr r3, [r7, #56] ; 0x38 8011aa2: 2b00 cmp r3, #0 8011aa4: d01e beq.n 8011ae4 8011aa6: 6b7b ldr r3, [r7, #52] ; 0x34 8011aa8: 2b00 cmp r3, #0 8011aaa: d01b beq.n 8011ae4 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8011aac: 6bbb ldr r3, [r7, #56] ; 0x38 8011aae: 627b str r3, [r7, #36] ; 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8011ab0: 6a7b ldr r3, [r7, #36] ; 0x24 8011ab2: 6b7a ldr r2, [r7, #52] ; 0x34 8011ab4: 631a str r2, [r3, #48] ; 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 8011ab6: 6a7b ldr r3, [r7, #36] ; 0x24 8011ab8: 2202 movs r2, #2 8011aba: f883 2051 strb.w r2, [r3, #81] ; 0x51 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 8011abe: 2300 movs r3, #0 8011ac0: 9303 str r3, [sp, #12] 8011ac2: 6a7b ldr r3, [r7, #36] ; 0x24 8011ac4: 9302 str r3, [sp, #8] 8011ac6: f107 0314 add.w r3, r7, #20 8011aca: 9301 str r3, [sp, #4] 8011acc: 6b3b ldr r3, [r7, #48] ; 0x30 8011ace: 9300 str r3, [sp, #0] 8011ad0: 683b ldr r3, [r7, #0] 8011ad2: 687a ldr r2, [r7, #4] 8011ad4: 68b9 ldr r1, [r7, #8] 8011ad6: 68f8 ldr r0, [r7, #12] 8011ad8: f000 f850 bl 8011b7c prvAddNewTaskToReadyList( pxNewTCB ); 8011adc: 6a78 ldr r0, [r7, #36] ; 0x24 8011ade: f000 f8dd bl 8011c9c 8011ae2: e001 b.n 8011ae8 } else { xReturn = NULL; 8011ae4: 2300 movs r3, #0 8011ae6: 617b str r3, [r7, #20] } return xReturn; 8011ae8: 697b ldr r3, [r7, #20] } 8011aea: 4618 mov r0, r3 8011aec: 3728 adds r7, #40 ; 0x28 8011aee: 46bd mov sp, r7 8011af0: bd80 pop {r7, pc} 08011af2 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 8011af2: b580 push {r7, lr} 8011af4: b08c sub sp, #48 ; 0x30 8011af6: af04 add r7, sp, #16 8011af8: 60f8 str r0, [r7, #12] 8011afa: 60b9 str r1, [r7, #8] 8011afc: 603b str r3, [r7, #0] 8011afe: 4613 mov r3, r2 8011b00: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 8011b02: 88fb ldrh r3, [r7, #6] 8011b04: 009b lsls r3, r3, #2 8011b06: 4618 mov r0, r3 8011b08: f001 fd9e bl 8013648 8011b0c: 6178 str r0, [r7, #20] if( pxStack != NULL ) 8011b0e: 697b ldr r3, [r7, #20] 8011b10: 2b00 cmp r3, #0 8011b12: d00e beq.n 8011b32 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 8011b14: 2054 movs r0, #84 ; 0x54 8011b16: f001 fd97 bl 8013648 8011b1a: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8011b1c: 69fb ldr r3, [r7, #28] 8011b1e: 2b00 cmp r3, #0 8011b20: d003 beq.n 8011b2a { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 8011b22: 69fb ldr r3, [r7, #28] 8011b24: 697a ldr r2, [r7, #20] 8011b26: 631a str r2, [r3, #48] ; 0x30 8011b28: e005 b.n 8011b36 } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 8011b2a: 6978 ldr r0, [r7, #20] 8011b2c: f001 fe58 bl 80137e0 8011b30: e001 b.n 8011b36 } } else { pxNewTCB = NULL; 8011b32: 2300 movs r3, #0 8011b34: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 8011b36: 69fb ldr r3, [r7, #28] 8011b38: 2b00 cmp r3, #0 8011b3a: d017 beq.n 8011b6c { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 8011b3c: 69fb ldr r3, [r7, #28] 8011b3e: 2200 movs r2, #0 8011b40: f883 2051 strb.w r2, [r3, #81] ; 0x51 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 8011b44: 88fa ldrh r2, [r7, #6] 8011b46: 2300 movs r3, #0 8011b48: 9303 str r3, [sp, #12] 8011b4a: 69fb ldr r3, [r7, #28] 8011b4c: 9302 str r3, [sp, #8] 8011b4e: 6afb ldr r3, [r7, #44] ; 0x2c 8011b50: 9301 str r3, [sp, #4] 8011b52: 6abb ldr r3, [r7, #40] ; 0x28 8011b54: 9300 str r3, [sp, #0] 8011b56: 683b ldr r3, [r7, #0] 8011b58: 68b9 ldr r1, [r7, #8] 8011b5a: 68f8 ldr r0, [r7, #12] 8011b5c: f000 f80e bl 8011b7c prvAddNewTaskToReadyList( pxNewTCB ); 8011b60: 69f8 ldr r0, [r7, #28] 8011b62: f000 f89b bl 8011c9c xReturn = pdPASS; 8011b66: 2301 movs r3, #1 8011b68: 61bb str r3, [r7, #24] 8011b6a: e002 b.n 8011b72 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8011b6c: f04f 33ff mov.w r3, #4294967295 8011b70: 61bb str r3, [r7, #24] } return xReturn; 8011b72: 69bb ldr r3, [r7, #24] } 8011b74: 4618 mov r0, r3 8011b76: 3720 adds r7, #32 8011b78: 46bd mov sp, r7 8011b7a: bd80 pop {r7, pc} 08011b7c : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 8011b7c: b580 push {r7, lr} 8011b7e: b088 sub sp, #32 8011b80: af00 add r7, sp, #0 8011b82: 60f8 str r0, [r7, #12] 8011b84: 60b9 str r1, [r7, #8] 8011b86: 607a str r2, [r7, #4] 8011b88: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 8011b8a: 6b3b ldr r3, [r7, #48] ; 0x30 8011b8c: 6b18 ldr r0, [r3, #48] ; 0x30 8011b8e: 687b ldr r3, [r7, #4] 8011b90: 009b lsls r3, r3, #2 8011b92: 461a mov r2, r3 8011b94: 21a5 movs r1, #165 ; 0xa5 8011b96: f010 f8a3 bl 8021ce0 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 8011b9a: 6b3b ldr r3, [r7, #48] ; 0x30 8011b9c: 6b1a ldr r2, [r3, #48] ; 0x30 8011b9e: 6879 ldr r1, [r7, #4] 8011ba0: f06f 4340 mvn.w r3, #3221225472 ; 0xc0000000 8011ba4: 440b add r3, r1 8011ba6: 009b lsls r3, r3, #2 8011ba8: 4413 add r3, r2 8011baa: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8011bac: 69bb ldr r3, [r7, #24] 8011bae: f023 0307 bic.w r3, r3, #7 8011bb2: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 8011bb4: 69bb ldr r3, [r7, #24] 8011bb6: f003 0307 and.w r3, r3, #7 8011bba: 2b00 cmp r3, #0 8011bbc: d00a beq.n 8011bd4 __asm volatile 8011bbe: f04f 0350 mov.w r3, #80 ; 0x50 8011bc2: f383 8811 msr BASEPRI, r3 8011bc6: f3bf 8f6f isb sy 8011bca: f3bf 8f4f dsb sy 8011bce: 617b str r3, [r7, #20] } 8011bd0: bf00 nop 8011bd2: e7fe b.n 8011bd2 pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 8011bd4: 68bb ldr r3, [r7, #8] 8011bd6: 2b00 cmp r3, #0 8011bd8: d01f beq.n 8011c1a { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8011bda: 2300 movs r3, #0 8011bdc: 61fb str r3, [r7, #28] 8011bde: e012 b.n 8011c06 { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 8011be0: 68ba ldr r2, [r7, #8] 8011be2: 69fb ldr r3, [r7, #28] 8011be4: 4413 add r3, r2 8011be6: 7819 ldrb r1, [r3, #0] 8011be8: 6b3a ldr r2, [r7, #48] ; 0x30 8011bea: 69fb ldr r3, [r7, #28] 8011bec: 4413 add r3, r2 8011bee: 3334 adds r3, #52 ; 0x34 8011bf0: 460a mov r2, r1 8011bf2: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 8011bf4: 68ba ldr r2, [r7, #8] 8011bf6: 69fb ldr r3, [r7, #28] 8011bf8: 4413 add r3, r2 8011bfa: 781b ldrb r3, [r3, #0] 8011bfc: 2b00 cmp r3, #0 8011bfe: d006 beq.n 8011c0e for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8011c00: 69fb ldr r3, [r7, #28] 8011c02: 3301 adds r3, #1 8011c04: 61fb str r3, [r7, #28] 8011c06: 69fb ldr r3, [r7, #28] 8011c08: 2b0f cmp r3, #15 8011c0a: d9e9 bls.n 8011be0 8011c0c: e000 b.n 8011c10 { break; 8011c0e: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 8011c10: 6b3b ldr r3, [r7, #48] ; 0x30 8011c12: 2200 movs r2, #0 8011c14: f883 2043 strb.w r2, [r3, #67] ; 0x43 8011c18: e003 b.n 8011c22 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 8011c1a: 6b3b ldr r3, [r7, #48] ; 0x30 8011c1c: 2200 movs r2, #0 8011c1e: f883 2034 strb.w r2, [r3, #52] ; 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 8011c22: 6abb ldr r3, [r7, #40] ; 0x28 8011c24: 2b06 cmp r3, #6 8011c26: d901 bls.n 8011c2c { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 8011c28: 2306 movs r3, #6 8011c2a: 62bb str r3, [r7, #40] ; 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 8011c2c: 6b3b ldr r3, [r7, #48] ; 0x30 8011c2e: 6aba ldr r2, [r7, #40] ; 0x28 8011c30: 62da str r2, [r3, #44] ; 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 8011c32: 6b3b ldr r3, [r7, #48] ; 0x30 8011c34: 6aba ldr r2, [r7, #40] ; 0x28 8011c36: 645a str r2, [r3, #68] ; 0x44 pxNewTCB->uxMutexesHeld = 0; 8011c38: 6b3b ldr r3, [r7, #48] ; 0x30 8011c3a: 2200 movs r2, #0 8011c3c: 649a str r2, [r3, #72] ; 0x48 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 8011c3e: 6b3b ldr r3, [r7, #48] ; 0x30 8011c40: 3304 adds r3, #4 8011c42: 4618 mov r0, r3 8011c44: f7fe fe3b bl 80108be vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 8011c48: 6b3b ldr r3, [r7, #48] ; 0x30 8011c4a: 3318 adds r3, #24 8011c4c: 4618 mov r0, r3 8011c4e: f7fe fe36 bl 80108be /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 8011c52: 6b3b ldr r3, [r7, #48] ; 0x30 8011c54: 6b3a ldr r2, [r7, #48] ; 0x30 8011c56: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8011c58: 6abb ldr r3, [r7, #40] ; 0x28 8011c5a: f1c3 0207 rsb r2, r3, #7 8011c5e: 6b3b ldr r3, [r7, #48] ; 0x30 8011c60: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 8011c62: 6b3b ldr r3, [r7, #48] ; 0x30 8011c64: 6b3a ldr r2, [r7, #48] ; 0x30 8011c66: 625a str r2, [r3, #36] ; 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 8011c68: 6b3b ldr r3, [r7, #48] ; 0x30 8011c6a: 2200 movs r2, #0 8011c6c: 64da str r2, [r3, #76] ; 0x4c pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8011c6e: 6b3b ldr r3, [r7, #48] ; 0x30 8011c70: 2200 movs r2, #0 8011c72: f883 2050 strb.w r2, [r3, #80] ; 0x50 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 8011c76: 683a ldr r2, [r7, #0] 8011c78: 68f9 ldr r1, [r7, #12] 8011c7a: 69b8 ldr r0, [r7, #24] 8011c7c: f001 fa98 bl 80131b0 8011c80: 4602 mov r2, r0 8011c82: 6b3b ldr r3, [r7, #48] ; 0x30 8011c84: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 8011c86: 6afb ldr r3, [r7, #44] ; 0x2c 8011c88: 2b00 cmp r3, #0 8011c8a: d002 beq.n 8011c92 { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8011c8c: 6afb ldr r3, [r7, #44] ; 0x2c 8011c8e: 6b3a ldr r2, [r7, #48] ; 0x30 8011c90: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8011c92: bf00 nop 8011c94: 3720 adds r7, #32 8011c96: 46bd mov sp, r7 8011c98: bd80 pop {r7, pc} ... 08011c9c : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 8011c9c: b580 push {r7, lr} 8011c9e: b082 sub sp, #8 8011ca0: af00 add r7, sp, #0 8011ca2: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 8011ca4: f001 fbae bl 8013404 { uxCurrentNumberOfTasks++; 8011ca8: 4b2a ldr r3, [pc, #168] ; (8011d54 ) 8011caa: 681b ldr r3, [r3, #0] 8011cac: 3301 adds r3, #1 8011cae: 4a29 ldr r2, [pc, #164] ; (8011d54 ) 8011cb0: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 8011cb2: 4b29 ldr r3, [pc, #164] ; (8011d58 ) 8011cb4: 681b ldr r3, [r3, #0] 8011cb6: 2b00 cmp r3, #0 8011cb8: d109 bne.n 8011cce { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 8011cba: 4a27 ldr r2, [pc, #156] ; (8011d58 ) 8011cbc: 687b ldr r3, [r7, #4] 8011cbe: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 8011cc0: 4b24 ldr r3, [pc, #144] ; (8011d54 ) 8011cc2: 681b ldr r3, [r3, #0] 8011cc4: 2b01 cmp r3, #1 8011cc6: d110 bne.n 8011cea { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 8011cc8: f000 fc28 bl 801251c 8011ccc: e00d b.n 8011cea else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 8011cce: 4b23 ldr r3, [pc, #140] ; (8011d5c ) 8011cd0: 681b ldr r3, [r3, #0] 8011cd2: 2b00 cmp r3, #0 8011cd4: d109 bne.n 8011cea { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 8011cd6: 4b20 ldr r3, [pc, #128] ; (8011d58 ) 8011cd8: 681b ldr r3, [r3, #0] 8011cda: 6ada ldr r2, [r3, #44] ; 0x2c 8011cdc: 687b ldr r3, [r7, #4] 8011cde: 6adb ldr r3, [r3, #44] ; 0x2c 8011ce0: 429a cmp r2, r3 8011ce2: d802 bhi.n 8011cea { pxCurrentTCB = pxNewTCB; 8011ce4: 4a1c ldr r2, [pc, #112] ; (8011d58 ) 8011ce6: 687b ldr r3, [r7, #4] 8011ce8: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 8011cea: 4b1d ldr r3, [pc, #116] ; (8011d60 ) 8011cec: 681b ldr r3, [r3, #0] 8011cee: 3301 adds r3, #1 8011cf0: 4a1b ldr r2, [pc, #108] ; (8011d60 ) 8011cf2: 6013 str r3, [r2, #0] pxNewTCB->uxTCBNumber = uxTaskNumber; } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 8011cf4: 687b ldr r3, [r7, #4] 8011cf6: 6adb ldr r3, [r3, #44] ; 0x2c 8011cf8: 2201 movs r2, #1 8011cfa: 409a lsls r2, r3 8011cfc: 4b19 ldr r3, [pc, #100] ; (8011d64 ) 8011cfe: 681b ldr r3, [r3, #0] 8011d00: 4313 orrs r3, r2 8011d02: 4a18 ldr r2, [pc, #96] ; (8011d64 ) 8011d04: 6013 str r3, [r2, #0] 8011d06: 687b ldr r3, [r7, #4] 8011d08: 6ada ldr r2, [r3, #44] ; 0x2c 8011d0a: 4613 mov r3, r2 8011d0c: 009b lsls r3, r3, #2 8011d0e: 4413 add r3, r2 8011d10: 009b lsls r3, r3, #2 8011d12: 4a15 ldr r2, [pc, #84] ; (8011d68 ) 8011d14: 441a add r2, r3 8011d16: 687b ldr r3, [r7, #4] 8011d18: 3304 adds r3, #4 8011d1a: 4619 mov r1, r3 8011d1c: 4610 mov r0, r2 8011d1e: f7fe fddb bl 80108d8 portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 8011d22: f001 fb9f bl 8013464 if( xSchedulerRunning != pdFALSE ) 8011d26: 4b0d ldr r3, [pc, #52] ; (8011d5c ) 8011d28: 681b ldr r3, [r3, #0] 8011d2a: 2b00 cmp r3, #0 8011d2c: d00e beq.n 8011d4c { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 8011d2e: 4b0a ldr r3, [pc, #40] ; (8011d58 ) 8011d30: 681b ldr r3, [r3, #0] 8011d32: 6ada ldr r2, [r3, #44] ; 0x2c 8011d34: 687b ldr r3, [r7, #4] 8011d36: 6adb ldr r3, [r3, #44] ; 0x2c 8011d38: 429a cmp r2, r3 8011d3a: d207 bcs.n 8011d4c { taskYIELD_IF_USING_PREEMPTION(); 8011d3c: 4b0b ldr r3, [pc, #44] ; (8011d6c ) 8011d3e: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8011d42: 601a str r2, [r3, #0] 8011d44: f3bf 8f4f dsb sy 8011d48: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8011d4c: bf00 nop 8011d4e: 3708 adds r7, #8 8011d50: 46bd mov sp, r7 8011d52: bd80 pop {r7, pc} 8011d54: 2400c020 .word 0x2400c020 8011d58: 2400bf20 .word 0x2400bf20 8011d5c: 2400c02c .word 0x2400c02c 8011d60: 2400c03c .word 0x2400c03c 8011d64: 2400c028 .word 0x2400c028 8011d68: 2400bf24 .word 0x2400bf24 8011d6c: e000ed04 .word 0xe000ed04 08011d70 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 8011d70: b580 push {r7, lr} 8011d72: b084 sub sp, #16 8011d74: af00 add r7, sp, #0 8011d76: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 8011d78: 2300 movs r3, #0 8011d7a: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 8011d7c: 687b ldr r3, [r7, #4] 8011d7e: 2b00 cmp r3, #0 8011d80: d017 beq.n 8011db2 { configASSERT( uxSchedulerSuspended == 0 ); 8011d82: 4b13 ldr r3, [pc, #76] ; (8011dd0 ) 8011d84: 681b ldr r3, [r3, #0] 8011d86: 2b00 cmp r3, #0 8011d88: d00a beq.n 8011da0 __asm volatile 8011d8a: f04f 0350 mov.w r3, #80 ; 0x50 8011d8e: f383 8811 msr BASEPRI, r3 8011d92: f3bf 8f6f isb sy 8011d96: f3bf 8f4f dsb sy 8011d9a: 60bb str r3, [r7, #8] } 8011d9c: bf00 nop 8011d9e: e7fe b.n 8011d9e vTaskSuspendAll(); 8011da0: f000 f880 bl 8011ea4 list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 8011da4: 2100 movs r1, #0 8011da6: 6878 ldr r0, [r7, #4] 8011da8: f000 fe6a bl 8012a80 } xAlreadyYielded = xTaskResumeAll(); 8011dac: f000 f888 bl 8011ec0 8011db0: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 8011db2: 68fb ldr r3, [r7, #12] 8011db4: 2b00 cmp r3, #0 8011db6: d107 bne.n 8011dc8 { portYIELD_WITHIN_API(); 8011db8: 4b06 ldr r3, [pc, #24] ; (8011dd4 ) 8011dba: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8011dbe: 601a str r2, [r3, #0] 8011dc0: f3bf 8f4f dsb sy 8011dc4: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8011dc8: bf00 nop 8011dca: 3710 adds r7, #16 8011dcc: 46bd mov sp, r7 8011dce: bd80 pop {r7, pc} 8011dd0: 2400c048 .word 0x2400c048 8011dd4: e000ed04 .word 0xe000ed04 08011dd8 : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 8011dd8: b580 push {r7, lr} 8011dda: b08a sub sp, #40 ; 0x28 8011ddc: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 8011dde: 2300 movs r3, #0 8011de0: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 8011de2: 2300 movs r3, #0 8011de4: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 8011de6: 463a mov r2, r7 8011de8: 1d39 adds r1, r7, #4 8011dea: f107 0308 add.w r3, r7, #8 8011dee: 4618 mov r0, r3 8011df0: f7ee fc80 bl 80006f4 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 8011df4: 6839 ldr r1, [r7, #0] 8011df6: 687b ldr r3, [r7, #4] 8011df8: 68ba ldr r2, [r7, #8] 8011dfa: 9202 str r2, [sp, #8] 8011dfc: 9301 str r3, [sp, #4] 8011dfe: 2300 movs r3, #0 8011e00: 9300 str r3, [sp, #0] 8011e02: 2300 movs r3, #0 8011e04: 460a mov r2, r1 8011e06: 4921 ldr r1, [pc, #132] ; (8011e8c ) 8011e08: 4821 ldr r0, [pc, #132] ; (8011e90 ) 8011e0a: f7ff fe15 bl 8011a38 8011e0e: 4603 mov r3, r0 8011e10: 4a20 ldr r2, [pc, #128] ; (8011e94 ) 8011e12: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 8011e14: 4b1f ldr r3, [pc, #124] ; (8011e94 ) 8011e16: 681b ldr r3, [r3, #0] 8011e18: 2b00 cmp r3, #0 8011e1a: d002 beq.n 8011e22 { xReturn = pdPASS; 8011e1c: 2301 movs r3, #1 8011e1e: 617b str r3, [r7, #20] 8011e20: e001 b.n 8011e26 } else { xReturn = pdFAIL; 8011e22: 2300 movs r3, #0 8011e24: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 8011e26: 697b ldr r3, [r7, #20] 8011e28: 2b01 cmp r3, #1 8011e2a: d102 bne.n 8011e32 { xReturn = xTimerCreateTimerTask(); 8011e2c: f000 fe8e bl 8012b4c 8011e30: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 8011e32: 697b ldr r3, [r7, #20] 8011e34: 2b01 cmp r3, #1 8011e36: d116 bne.n 8011e66 __asm volatile 8011e38: f04f 0350 mov.w r3, #80 ; 0x50 8011e3c: f383 8811 msr BASEPRI, r3 8011e40: f3bf 8f6f isb sy 8011e44: f3bf 8f4f dsb sy 8011e48: 613b str r3, [r7, #16] } 8011e4a: bf00 nop for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 8011e4c: 4b12 ldr r3, [pc, #72] ; (8011e98 ) 8011e4e: f04f 32ff mov.w r2, #4294967295 8011e52: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 8011e54: 4b11 ldr r3, [pc, #68] ; (8011e9c ) 8011e56: 2201 movs r2, #1 8011e58: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 8011e5a: 4b11 ldr r3, [pc, #68] ; (8011ea0 ) 8011e5c: 2200 movs r2, #0 8011e5e: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 8011e60: f001 fa2e bl 80132c0 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 8011e64: e00e b.n 8011e84 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 8011e66: 697b ldr r3, [r7, #20] 8011e68: f1b3 3fff cmp.w r3, #4294967295 8011e6c: d10a bne.n 8011e84 __asm volatile 8011e6e: f04f 0350 mov.w r3, #80 ; 0x50 8011e72: f383 8811 msr BASEPRI, r3 8011e76: f3bf 8f6f isb sy 8011e7a: f3bf 8f4f dsb sy 8011e7e: 60fb str r3, [r7, #12] } 8011e80: bf00 nop 8011e82: e7fe b.n 8011e82 } 8011e84: bf00 nop 8011e86: 3718 adds r7, #24 8011e88: 46bd mov sp, r7 8011e8a: bd80 pop {r7, pc} 8011e8c: 080232b4 .word 0x080232b4 8011e90: 080124ed .word 0x080124ed 8011e94: 2400c044 .word 0x2400c044 8011e98: 2400c040 .word 0x2400c040 8011e9c: 2400c02c .word 0x2400c02c 8011ea0: 2400c024 .word 0x2400c024 08011ea4 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 8011ea4: b480 push {r7} 8011ea6: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8011ea8: 4b04 ldr r3, [pc, #16] ; (8011ebc ) 8011eaa: 681b ldr r3, [r3, #0] 8011eac: 3301 adds r3, #1 8011eae: 4a03 ldr r2, [pc, #12] ; (8011ebc ) 8011eb0: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 8011eb2: bf00 nop 8011eb4: 46bd mov sp, r7 8011eb6: f85d 7b04 ldr.w r7, [sp], #4 8011eba: 4770 bx lr 8011ebc: 2400c048 .word 0x2400c048 08011ec0 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 8011ec0: b580 push {r7, lr} 8011ec2: b084 sub sp, #16 8011ec4: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 8011ec6: 2300 movs r3, #0 8011ec8: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 8011eca: 2300 movs r3, #0 8011ecc: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 8011ece: 4b41 ldr r3, [pc, #260] ; (8011fd4 ) 8011ed0: 681b ldr r3, [r3, #0] 8011ed2: 2b00 cmp r3, #0 8011ed4: d10a bne.n 8011eec __asm volatile 8011ed6: f04f 0350 mov.w r3, #80 ; 0x50 8011eda: f383 8811 msr BASEPRI, r3 8011ede: f3bf 8f6f isb sy 8011ee2: f3bf 8f4f dsb sy 8011ee6: 603b str r3, [r7, #0] } 8011ee8: bf00 nop 8011eea: e7fe b.n 8011eea /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 8011eec: f001 fa8a bl 8013404 { --uxSchedulerSuspended; 8011ef0: 4b38 ldr r3, [pc, #224] ; (8011fd4 ) 8011ef2: 681b ldr r3, [r3, #0] 8011ef4: 3b01 subs r3, #1 8011ef6: 4a37 ldr r2, [pc, #220] ; (8011fd4 ) 8011ef8: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8011efa: 4b36 ldr r3, [pc, #216] ; (8011fd4 ) 8011efc: 681b ldr r3, [r3, #0] 8011efe: 2b00 cmp r3, #0 8011f00: d161 bne.n 8011fc6 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 8011f02: 4b35 ldr r3, [pc, #212] ; (8011fd8 ) 8011f04: 681b ldr r3, [r3, #0] 8011f06: 2b00 cmp r3, #0 8011f08: d05d beq.n 8011fc6 { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8011f0a: e02e b.n 8011f6a { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8011f0c: 4b33 ldr r3, [pc, #204] ; (8011fdc ) 8011f0e: 68db ldr r3, [r3, #12] 8011f10: 68db ldr r3, [r3, #12] 8011f12: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 8011f14: 68fb ldr r3, [r7, #12] 8011f16: 3318 adds r3, #24 8011f18: 4618 mov r0, r3 8011f1a: f7fe fd3a bl 8010992 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8011f1e: 68fb ldr r3, [r7, #12] 8011f20: 3304 adds r3, #4 8011f22: 4618 mov r0, r3 8011f24: f7fe fd35 bl 8010992 prvAddTaskToReadyList( pxTCB ); 8011f28: 68fb ldr r3, [r7, #12] 8011f2a: 6adb ldr r3, [r3, #44] ; 0x2c 8011f2c: 2201 movs r2, #1 8011f2e: 409a lsls r2, r3 8011f30: 4b2b ldr r3, [pc, #172] ; (8011fe0 ) 8011f32: 681b ldr r3, [r3, #0] 8011f34: 4313 orrs r3, r2 8011f36: 4a2a ldr r2, [pc, #168] ; (8011fe0 ) 8011f38: 6013 str r3, [r2, #0] 8011f3a: 68fb ldr r3, [r7, #12] 8011f3c: 6ada ldr r2, [r3, #44] ; 0x2c 8011f3e: 4613 mov r3, r2 8011f40: 009b lsls r3, r3, #2 8011f42: 4413 add r3, r2 8011f44: 009b lsls r3, r3, #2 8011f46: 4a27 ldr r2, [pc, #156] ; (8011fe4 ) 8011f48: 441a add r2, r3 8011f4a: 68fb ldr r3, [r7, #12] 8011f4c: 3304 adds r3, #4 8011f4e: 4619 mov r1, r3 8011f50: 4610 mov r0, r2 8011f52: f7fe fcc1 bl 80108d8 /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8011f56: 68fb ldr r3, [r7, #12] 8011f58: 6ada ldr r2, [r3, #44] ; 0x2c 8011f5a: 4b23 ldr r3, [pc, #140] ; (8011fe8 ) 8011f5c: 681b ldr r3, [r3, #0] 8011f5e: 6adb ldr r3, [r3, #44] ; 0x2c 8011f60: 429a cmp r2, r3 8011f62: d302 bcc.n 8011f6a { xYieldPending = pdTRUE; 8011f64: 4b21 ldr r3, [pc, #132] ; (8011fec ) 8011f66: 2201 movs r2, #1 8011f68: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8011f6a: 4b1c ldr r3, [pc, #112] ; (8011fdc ) 8011f6c: 681b ldr r3, [r3, #0] 8011f6e: 2b00 cmp r3, #0 8011f70: d1cc bne.n 8011f0c { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 8011f72: 68fb ldr r3, [r7, #12] 8011f74: 2b00 cmp r3, #0 8011f76: d001 beq.n 8011f7c which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 8011f78: f000 fba6 bl 80126c8 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 8011f7c: 4b1c ldr r3, [pc, #112] ; (8011ff0 ) 8011f7e: 681b ldr r3, [r3, #0] 8011f80: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 8011f82: 687b ldr r3, [r7, #4] 8011f84: 2b00 cmp r3, #0 8011f86: d010 beq.n 8011faa { do { if( xTaskIncrementTick() != pdFALSE ) 8011f88: f000 f858 bl 801203c 8011f8c: 4603 mov r3, r0 8011f8e: 2b00 cmp r3, #0 8011f90: d002 beq.n 8011f98 { xYieldPending = pdTRUE; 8011f92: 4b16 ldr r3, [pc, #88] ; (8011fec ) 8011f94: 2201 movs r2, #1 8011f96: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 8011f98: 687b ldr r3, [r7, #4] 8011f9a: 3b01 subs r3, #1 8011f9c: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 8011f9e: 687b ldr r3, [r7, #4] 8011fa0: 2b00 cmp r3, #0 8011fa2: d1f1 bne.n 8011f88 xPendedTicks = 0; 8011fa4: 4b12 ldr r3, [pc, #72] ; (8011ff0 ) 8011fa6: 2200 movs r2, #0 8011fa8: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 8011faa: 4b10 ldr r3, [pc, #64] ; (8011fec ) 8011fac: 681b ldr r3, [r3, #0] 8011fae: 2b00 cmp r3, #0 8011fb0: d009 beq.n 8011fc6 { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 8011fb2: 2301 movs r3, #1 8011fb4: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 8011fb6: 4b0f ldr r3, [pc, #60] ; (8011ff4 ) 8011fb8: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8011fbc: 601a str r2, [r3, #0] 8011fbe: f3bf 8f4f dsb sy 8011fc2: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8011fc6: f001 fa4d bl 8013464 return xAlreadyYielded; 8011fca: 68bb ldr r3, [r7, #8] } 8011fcc: 4618 mov r0, r3 8011fce: 3710 adds r7, #16 8011fd0: 46bd mov sp, r7 8011fd2: bd80 pop {r7, pc} 8011fd4: 2400c048 .word 0x2400c048 8011fd8: 2400c020 .word 0x2400c020 8011fdc: 2400bfe0 .word 0x2400bfe0 8011fe0: 2400c028 .word 0x2400c028 8011fe4: 2400bf24 .word 0x2400bf24 8011fe8: 2400bf20 .word 0x2400bf20 8011fec: 2400c034 .word 0x2400c034 8011ff0: 2400c030 .word 0x2400c030 8011ff4: e000ed04 .word 0xe000ed04 08011ff8 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 8011ff8: b480 push {r7} 8011ffa: b083 sub sp, #12 8011ffc: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 8011ffe: 4b05 ldr r3, [pc, #20] ; (8012014 ) 8012000: 681b ldr r3, [r3, #0] 8012002: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 8012004: 687b ldr r3, [r7, #4] } 8012006: 4618 mov r0, r3 8012008: 370c adds r7, #12 801200a: 46bd mov sp, r7 801200c: f85d 7b04 ldr.w r7, [sp], #4 8012010: 4770 bx lr 8012012: bf00 nop 8012014: 2400c024 .word 0x2400c024 08012018 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCountFromISR( void ) { 8012018: b580 push {r7, lr} 801201a: b082 sub sp, #8 801201c: af00 add r7, sp, #0 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 801201e: f001 fad3 bl 80135c8 uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR(); 8012022: 2300 movs r3, #0 8012024: 607b str r3, [r7, #4] { xReturn = xTickCount; 8012026: 4b04 ldr r3, [pc, #16] ; (8012038 ) 8012028: 681b ldr r3, [r3, #0] 801202a: 603b str r3, [r7, #0] } portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801202c: 683b ldr r3, [r7, #0] } 801202e: 4618 mov r0, r3 8012030: 3708 adds r7, #8 8012032: 46bd mov sp, r7 8012034: bd80 pop {r7, pc} 8012036: bf00 nop 8012038: 2400c024 .word 0x2400c024 0801203c : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 801203c: b580 push {r7, lr} 801203e: b086 sub sp, #24 8012040: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 8012042: 2300 movs r3, #0 8012044: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8012046: 4b4e ldr r3, [pc, #312] ; (8012180 ) 8012048: 681b ldr r3, [r3, #0] 801204a: 2b00 cmp r3, #0 801204c: f040 808e bne.w 801216c { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 8012050: 4b4c ldr r3, [pc, #304] ; (8012184 ) 8012052: 681b ldr r3, [r3, #0] 8012054: 3301 adds r3, #1 8012056: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8012058: 4a4a ldr r2, [pc, #296] ; (8012184 ) 801205a: 693b ldr r3, [r7, #16] 801205c: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 801205e: 693b ldr r3, [r7, #16] 8012060: 2b00 cmp r3, #0 8012062: d120 bne.n 80120a6 { taskSWITCH_DELAYED_LISTS(); 8012064: 4b48 ldr r3, [pc, #288] ; (8012188 ) 8012066: 681b ldr r3, [r3, #0] 8012068: 681b ldr r3, [r3, #0] 801206a: 2b00 cmp r3, #0 801206c: d00a beq.n 8012084 __asm volatile 801206e: f04f 0350 mov.w r3, #80 ; 0x50 8012072: f383 8811 msr BASEPRI, r3 8012076: f3bf 8f6f isb sy 801207a: f3bf 8f4f dsb sy 801207e: 603b str r3, [r7, #0] } 8012080: bf00 nop 8012082: e7fe b.n 8012082 8012084: 4b40 ldr r3, [pc, #256] ; (8012188 ) 8012086: 681b ldr r3, [r3, #0] 8012088: 60fb str r3, [r7, #12] 801208a: 4b40 ldr r3, [pc, #256] ; (801218c ) 801208c: 681b ldr r3, [r3, #0] 801208e: 4a3e ldr r2, [pc, #248] ; (8012188 ) 8012090: 6013 str r3, [r2, #0] 8012092: 4a3e ldr r2, [pc, #248] ; (801218c ) 8012094: 68fb ldr r3, [r7, #12] 8012096: 6013 str r3, [r2, #0] 8012098: 4b3d ldr r3, [pc, #244] ; (8012190 ) 801209a: 681b ldr r3, [r3, #0] 801209c: 3301 adds r3, #1 801209e: 4a3c ldr r2, [pc, #240] ; (8012190 ) 80120a0: 6013 str r3, [r2, #0] 80120a2: f000 fb11 bl 80126c8 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 80120a6: 4b3b ldr r3, [pc, #236] ; (8012194 ) 80120a8: 681b ldr r3, [r3, #0] 80120aa: 693a ldr r2, [r7, #16] 80120ac: 429a cmp r2, r3 80120ae: d348 bcc.n 8012142 { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80120b0: 4b35 ldr r3, [pc, #212] ; (8012188 ) 80120b2: 681b ldr r3, [r3, #0] 80120b4: 681b ldr r3, [r3, #0] 80120b6: 2b00 cmp r3, #0 80120b8: d104 bne.n 80120c4 /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80120ba: 4b36 ldr r3, [pc, #216] ; (8012194 ) 80120bc: f04f 32ff mov.w r2, #4294967295 80120c0: 601a str r2, [r3, #0] break; 80120c2: e03e b.n 8012142 { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80120c4: 4b30 ldr r3, [pc, #192] ; (8012188 ) 80120c6: 681b ldr r3, [r3, #0] 80120c8: 68db ldr r3, [r3, #12] 80120ca: 68db ldr r3, [r3, #12] 80120cc: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 80120ce: 68bb ldr r3, [r7, #8] 80120d0: 685b ldr r3, [r3, #4] 80120d2: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 80120d4: 693a ldr r2, [r7, #16] 80120d6: 687b ldr r3, [r7, #4] 80120d8: 429a cmp r2, r3 80120da: d203 bcs.n 80120e4 /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 80120dc: 4a2d ldr r2, [pc, #180] ; (8012194 ) 80120de: 687b ldr r3, [r7, #4] 80120e0: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 80120e2: e02e b.n 8012142 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80120e4: 68bb ldr r3, [r7, #8] 80120e6: 3304 adds r3, #4 80120e8: 4618 mov r0, r3 80120ea: f7fe fc52 bl 8010992 /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 80120ee: 68bb ldr r3, [r7, #8] 80120f0: 6a9b ldr r3, [r3, #40] ; 0x28 80120f2: 2b00 cmp r3, #0 80120f4: d004 beq.n 8012100 { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80120f6: 68bb ldr r3, [r7, #8] 80120f8: 3318 adds r3, #24 80120fa: 4618 mov r0, r3 80120fc: f7fe fc49 bl 8010992 mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 8012100: 68bb ldr r3, [r7, #8] 8012102: 6adb ldr r3, [r3, #44] ; 0x2c 8012104: 2201 movs r2, #1 8012106: 409a lsls r2, r3 8012108: 4b23 ldr r3, [pc, #140] ; (8012198 ) 801210a: 681b ldr r3, [r3, #0] 801210c: 4313 orrs r3, r2 801210e: 4a22 ldr r2, [pc, #136] ; (8012198 ) 8012110: 6013 str r3, [r2, #0] 8012112: 68bb ldr r3, [r7, #8] 8012114: 6ada ldr r2, [r3, #44] ; 0x2c 8012116: 4613 mov r3, r2 8012118: 009b lsls r3, r3, #2 801211a: 4413 add r3, r2 801211c: 009b lsls r3, r3, #2 801211e: 4a1f ldr r2, [pc, #124] ; (801219c ) 8012120: 441a add r2, r3 8012122: 68bb ldr r3, [r7, #8] 8012124: 3304 adds r3, #4 8012126: 4619 mov r1, r3 8012128: 4610 mov r0, r2 801212a: f7fe fbd5 bl 80108d8 { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 801212e: 68bb ldr r3, [r7, #8] 8012130: 6ada ldr r2, [r3, #44] ; 0x2c 8012132: 4b1b ldr r3, [pc, #108] ; (80121a0 ) 8012134: 681b ldr r3, [r3, #0] 8012136: 6adb ldr r3, [r3, #44] ; 0x2c 8012138: 429a cmp r2, r3 801213a: d3b9 bcc.n 80120b0 { xSwitchRequired = pdTRUE; 801213c: 2301 movs r3, #1 801213e: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8012140: e7b6 b.n 80120b0 /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 8012142: 4b17 ldr r3, [pc, #92] ; (80121a0 ) 8012144: 681b ldr r3, [r3, #0] 8012146: 6ada ldr r2, [r3, #44] ; 0x2c 8012148: 4914 ldr r1, [pc, #80] ; (801219c ) 801214a: 4613 mov r3, r2 801214c: 009b lsls r3, r3, #2 801214e: 4413 add r3, r2 8012150: 009b lsls r3, r3, #2 8012152: 440b add r3, r1 8012154: 681b ldr r3, [r3, #0] 8012156: 2b01 cmp r3, #1 8012158: d901 bls.n 801215e { xSwitchRequired = pdTRUE; 801215a: 2301 movs r3, #1 801215c: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 801215e: 4b11 ldr r3, [pc, #68] ; (80121a4 ) 8012160: 681b ldr r3, [r3, #0] 8012162: 2b00 cmp r3, #0 8012164: d007 beq.n 8012176 { xSwitchRequired = pdTRUE; 8012166: 2301 movs r3, #1 8012168: 617b str r3, [r7, #20] 801216a: e004 b.n 8012176 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 801216c: 4b0e ldr r3, [pc, #56] ; (80121a8 ) 801216e: 681b ldr r3, [r3, #0] 8012170: 3301 adds r3, #1 8012172: 4a0d ldr r2, [pc, #52] ; (80121a8 ) 8012174: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 8012176: 697b ldr r3, [r7, #20] } 8012178: 4618 mov r0, r3 801217a: 3718 adds r7, #24 801217c: 46bd mov sp, r7 801217e: bd80 pop {r7, pc} 8012180: 2400c048 .word 0x2400c048 8012184: 2400c024 .word 0x2400c024 8012188: 2400bfd8 .word 0x2400bfd8 801218c: 2400bfdc .word 0x2400bfdc 8012190: 2400c038 .word 0x2400c038 8012194: 2400c040 .word 0x2400c040 8012198: 2400c028 .word 0x2400c028 801219c: 2400bf24 .word 0x2400bf24 80121a0: 2400bf20 .word 0x2400bf20 80121a4: 2400c034 .word 0x2400c034 80121a8: 2400c030 .word 0x2400c030 080121ac : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 80121ac: b580 push {r7, lr} 80121ae: b086 sub sp, #24 80121b0: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 80121b2: 4b2e ldr r3, [pc, #184] ; (801226c ) 80121b4: 681b ldr r3, [r3, #0] 80121b6: 2b00 cmp r3, #0 80121b8: d003 beq.n 80121c2 { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 80121ba: 4b2d ldr r3, [pc, #180] ; (8012270 ) 80121bc: 2201 movs r2, #1 80121be: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 80121c0: e050 b.n 8012264 xYieldPending = pdFALSE; 80121c2: 4b2b ldr r3, [pc, #172] ; (8012270 ) 80121c4: 2200 movs r2, #0 80121c6: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 80121c8: 4b2a ldr r3, [pc, #168] ; (8012274 ) 80121ca: 681b ldr r3, [r3, #0] 80121cc: 681a ldr r2, [r3, #0] 80121ce: 4b29 ldr r3, [pc, #164] ; (8012274 ) 80121d0: 681b ldr r3, [r3, #0] 80121d2: 6b1b ldr r3, [r3, #48] ; 0x30 80121d4: 429a cmp r2, r3 80121d6: d808 bhi.n 80121ea 80121d8: 4b26 ldr r3, [pc, #152] ; (8012274 ) 80121da: 681a ldr r2, [r3, #0] 80121dc: 4b25 ldr r3, [pc, #148] ; (8012274 ) 80121de: 681b ldr r3, [r3, #0] 80121e0: 3334 adds r3, #52 ; 0x34 80121e2: 4619 mov r1, r3 80121e4: 4610 mov r0, r2 80121e6: f7ee fa79 bl 80006dc taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80121ea: 4b23 ldr r3, [pc, #140] ; (8012278 ) 80121ec: 681b ldr r3, [r3, #0] 80121ee: 60fb str r3, [r7, #12] __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); 80121f0: 68fb ldr r3, [r7, #12] 80121f2: fab3 f383 clz r3, r3 80121f6: 72fb strb r3, [r7, #11] return ucReturn; 80121f8: 7afb ldrb r3, [r7, #11] 80121fa: f1c3 031f rsb r3, r3, #31 80121fe: 617b str r3, [r7, #20] 8012200: 491e ldr r1, [pc, #120] ; (801227c ) 8012202: 697a ldr r2, [r7, #20] 8012204: 4613 mov r3, r2 8012206: 009b lsls r3, r3, #2 8012208: 4413 add r3, r2 801220a: 009b lsls r3, r3, #2 801220c: 440b add r3, r1 801220e: 681b ldr r3, [r3, #0] 8012210: 2b00 cmp r3, #0 8012212: d10a bne.n 801222a __asm volatile 8012214: f04f 0350 mov.w r3, #80 ; 0x50 8012218: f383 8811 msr BASEPRI, r3 801221c: f3bf 8f6f isb sy 8012220: f3bf 8f4f dsb sy 8012224: 607b str r3, [r7, #4] } 8012226: bf00 nop 8012228: e7fe b.n 8012228 801222a: 697a ldr r2, [r7, #20] 801222c: 4613 mov r3, r2 801222e: 009b lsls r3, r3, #2 8012230: 4413 add r3, r2 8012232: 009b lsls r3, r3, #2 8012234: 4a11 ldr r2, [pc, #68] ; (801227c ) 8012236: 4413 add r3, r2 8012238: 613b str r3, [r7, #16] 801223a: 693b ldr r3, [r7, #16] 801223c: 685b ldr r3, [r3, #4] 801223e: 685a ldr r2, [r3, #4] 8012240: 693b ldr r3, [r7, #16] 8012242: 605a str r2, [r3, #4] 8012244: 693b ldr r3, [r7, #16] 8012246: 685a ldr r2, [r3, #4] 8012248: 693b ldr r3, [r7, #16] 801224a: 3308 adds r3, #8 801224c: 429a cmp r2, r3 801224e: d104 bne.n 801225a 8012250: 693b ldr r3, [r7, #16] 8012252: 685b ldr r3, [r3, #4] 8012254: 685a ldr r2, [r3, #4] 8012256: 693b ldr r3, [r7, #16] 8012258: 605a str r2, [r3, #4] 801225a: 693b ldr r3, [r7, #16] 801225c: 685b ldr r3, [r3, #4] 801225e: 68db ldr r3, [r3, #12] 8012260: 4a04 ldr r2, [pc, #16] ; (8012274 ) 8012262: 6013 str r3, [r2, #0] } 8012264: bf00 nop 8012266: 3718 adds r7, #24 8012268: 46bd mov sp, r7 801226a: bd80 pop {r7, pc} 801226c: 2400c048 .word 0x2400c048 8012270: 2400c034 .word 0x2400c034 8012274: 2400bf20 .word 0x2400bf20 8012278: 2400c028 .word 0x2400c028 801227c: 2400bf24 .word 0x2400bf24 08012280 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 8012280: b580 push {r7, lr} 8012282: b084 sub sp, #16 8012284: af00 add r7, sp, #0 8012286: 6078 str r0, [r7, #4] 8012288: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 801228a: 687b ldr r3, [r7, #4] 801228c: 2b00 cmp r3, #0 801228e: d10a bne.n 80122a6 __asm volatile 8012290: f04f 0350 mov.w r3, #80 ; 0x50 8012294: f383 8811 msr BASEPRI, r3 8012298: f3bf 8f6f isb sy 801229c: f3bf 8f4f dsb sy 80122a0: 60fb str r3, [r7, #12] } 80122a2: bf00 nop 80122a4: e7fe b.n 80122a4 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 80122a6: 4b07 ldr r3, [pc, #28] ; (80122c4 ) 80122a8: 681b ldr r3, [r3, #0] 80122aa: 3318 adds r3, #24 80122ac: 4619 mov r1, r3 80122ae: 6878 ldr r0, [r7, #4] 80122b0: f7fe fb36 bl 8010920 prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 80122b4: 2101 movs r1, #1 80122b6: 6838 ldr r0, [r7, #0] 80122b8: f000 fbe2 bl 8012a80 } 80122bc: bf00 nop 80122be: 3710 adds r7, #16 80122c0: 46bd mov sp, r7 80122c2: bd80 pop {r7, pc} 80122c4: 2400bf20 .word 0x2400bf20 080122c8 : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 80122c8: b580 push {r7, lr} 80122ca: b086 sub sp, #24 80122cc: af00 add r7, sp, #0 80122ce: 60f8 str r0, [r7, #12] 80122d0: 60b9 str r1, [r7, #8] 80122d2: 607a str r2, [r7, #4] configASSERT( pxEventList ); 80122d4: 68fb ldr r3, [r7, #12] 80122d6: 2b00 cmp r3, #0 80122d8: d10a bne.n 80122f0 __asm volatile 80122da: f04f 0350 mov.w r3, #80 ; 0x50 80122de: f383 8811 msr BASEPRI, r3 80122e2: f3bf 8f6f isb sy 80122e6: f3bf 8f4f dsb sy 80122ea: 617b str r3, [r7, #20] } 80122ec: bf00 nop 80122ee: e7fe b.n 80122ee /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 80122f0: 4b0a ldr r3, [pc, #40] ; (801231c ) 80122f2: 681b ldr r3, [r3, #0] 80122f4: 3318 adds r3, #24 80122f6: 4619 mov r1, r3 80122f8: 68f8 ldr r0, [r7, #12] 80122fa: f7fe faed bl 80108d8 /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 80122fe: 687b ldr r3, [r7, #4] 8012300: 2b00 cmp r3, #0 8012302: d002 beq.n 801230a { xTicksToWait = portMAX_DELAY; 8012304: f04f 33ff mov.w r3, #4294967295 8012308: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 801230a: 6879 ldr r1, [r7, #4] 801230c: 68b8 ldr r0, [r7, #8] 801230e: f000 fbb7 bl 8012a80 } 8012312: bf00 nop 8012314: 3718 adds r7, #24 8012316: 46bd mov sp, r7 8012318: bd80 pop {r7, pc} 801231a: bf00 nop 801231c: 2400bf20 .word 0x2400bf20 08012320 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 8012320: b580 push {r7, lr} 8012322: b086 sub sp, #24 8012324: af00 add r7, sp, #0 8012326: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8012328: 687b ldr r3, [r7, #4] 801232a: 68db ldr r3, [r3, #12] 801232c: 68db ldr r3, [r3, #12] 801232e: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 8012330: 693b ldr r3, [r7, #16] 8012332: 2b00 cmp r3, #0 8012334: d10a bne.n 801234c __asm volatile 8012336: f04f 0350 mov.w r3, #80 ; 0x50 801233a: f383 8811 msr BASEPRI, r3 801233e: f3bf 8f6f isb sy 8012342: f3bf 8f4f dsb sy 8012346: 60fb str r3, [r7, #12] } 8012348: bf00 nop 801234a: e7fe b.n 801234a ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 801234c: 693b ldr r3, [r7, #16] 801234e: 3318 adds r3, #24 8012350: 4618 mov r0, r3 8012352: f7fe fb1e bl 8010992 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8012356: 4b1d ldr r3, [pc, #116] ; (80123cc ) 8012358: 681b ldr r3, [r3, #0] 801235a: 2b00 cmp r3, #0 801235c: d11c bne.n 8012398 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 801235e: 693b ldr r3, [r7, #16] 8012360: 3304 adds r3, #4 8012362: 4618 mov r0, r3 8012364: f7fe fb15 bl 8010992 prvAddTaskToReadyList( pxUnblockedTCB ); 8012368: 693b ldr r3, [r7, #16] 801236a: 6adb ldr r3, [r3, #44] ; 0x2c 801236c: 2201 movs r2, #1 801236e: 409a lsls r2, r3 8012370: 4b17 ldr r3, [pc, #92] ; (80123d0 ) 8012372: 681b ldr r3, [r3, #0] 8012374: 4313 orrs r3, r2 8012376: 4a16 ldr r2, [pc, #88] ; (80123d0 ) 8012378: 6013 str r3, [r2, #0] 801237a: 693b ldr r3, [r7, #16] 801237c: 6ada ldr r2, [r3, #44] ; 0x2c 801237e: 4613 mov r3, r2 8012380: 009b lsls r3, r3, #2 8012382: 4413 add r3, r2 8012384: 009b lsls r3, r3, #2 8012386: 4a13 ldr r2, [pc, #76] ; (80123d4 ) 8012388: 441a add r2, r3 801238a: 693b ldr r3, [r7, #16] 801238c: 3304 adds r3, #4 801238e: 4619 mov r1, r3 8012390: 4610 mov r0, r2 8012392: f7fe faa1 bl 80108d8 8012396: e005 b.n 80123a4 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 8012398: 693b ldr r3, [r7, #16] 801239a: 3318 adds r3, #24 801239c: 4619 mov r1, r3 801239e: 480e ldr r0, [pc, #56] ; (80123d8 ) 80123a0: f7fe fa9a bl 80108d8 } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 80123a4: 693b ldr r3, [r7, #16] 80123a6: 6ada ldr r2, [r3, #44] ; 0x2c 80123a8: 4b0c ldr r3, [pc, #48] ; (80123dc ) 80123aa: 681b ldr r3, [r3, #0] 80123ac: 6adb ldr r3, [r3, #44] ; 0x2c 80123ae: 429a cmp r2, r3 80123b0: d905 bls.n 80123be { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 80123b2: 2301 movs r3, #1 80123b4: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 80123b6: 4b0a ldr r3, [pc, #40] ; (80123e0 ) 80123b8: 2201 movs r2, #1 80123ba: 601a str r2, [r3, #0] 80123bc: e001 b.n 80123c2 } else { xReturn = pdFALSE; 80123be: 2300 movs r3, #0 80123c0: 617b str r3, [r7, #20] } return xReturn; 80123c2: 697b ldr r3, [r7, #20] } 80123c4: 4618 mov r0, r3 80123c6: 3718 adds r7, #24 80123c8: 46bd mov sp, r7 80123ca: bd80 pop {r7, pc} 80123cc: 2400c048 .word 0x2400c048 80123d0: 2400c028 .word 0x2400c028 80123d4: 2400bf24 .word 0x2400bf24 80123d8: 2400bfe0 .word 0x2400bfe0 80123dc: 2400bf20 .word 0x2400bf20 80123e0: 2400c034 .word 0x2400c034 080123e4 : taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 80123e4: b480 push {r7} 80123e6: b083 sub sp, #12 80123e8: af00 add r7, sp, #0 80123ea: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 80123ec: 4b06 ldr r3, [pc, #24] ; (8012408 ) 80123ee: 681a ldr r2, [r3, #0] 80123f0: 687b ldr r3, [r7, #4] 80123f2: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 80123f4: 4b05 ldr r3, [pc, #20] ; (801240c ) 80123f6: 681a ldr r2, [r3, #0] 80123f8: 687b ldr r3, [r7, #4] 80123fa: 605a str r2, [r3, #4] } 80123fc: bf00 nop 80123fe: 370c adds r7, #12 8012400: 46bd mov sp, r7 8012402: f85d 7b04 ldr.w r7, [sp], #4 8012406: 4770 bx lr 8012408: 2400c038 .word 0x2400c038 801240c: 2400c024 .word 0x2400c024 08012410 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8012410: b580 push {r7, lr} 8012412: b088 sub sp, #32 8012414: af00 add r7, sp, #0 8012416: 6078 str r0, [r7, #4] 8012418: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 801241a: 687b ldr r3, [r7, #4] 801241c: 2b00 cmp r3, #0 801241e: d10a bne.n 8012436 __asm volatile 8012420: f04f 0350 mov.w r3, #80 ; 0x50 8012424: f383 8811 msr BASEPRI, r3 8012428: f3bf 8f6f isb sy 801242c: f3bf 8f4f dsb sy 8012430: 613b str r3, [r7, #16] } 8012432: bf00 nop 8012434: e7fe b.n 8012434 configASSERT( pxTicksToWait ); 8012436: 683b ldr r3, [r7, #0] 8012438: 2b00 cmp r3, #0 801243a: d10a bne.n 8012452 __asm volatile 801243c: f04f 0350 mov.w r3, #80 ; 0x50 8012440: f383 8811 msr BASEPRI, r3 8012444: f3bf 8f6f isb sy 8012448: f3bf 8f4f dsb sy 801244c: 60fb str r3, [r7, #12] } 801244e: bf00 nop 8012450: e7fe b.n 8012450 taskENTER_CRITICAL(); 8012452: f000 ffd7 bl 8013404 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 8012456: 4b1d ldr r3, [pc, #116] ; (80124cc ) 8012458: 681b ldr r3, [r3, #0] 801245a: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 801245c: 687b ldr r3, [r7, #4] 801245e: 685b ldr r3, [r3, #4] 8012460: 69ba ldr r2, [r7, #24] 8012462: 1ad3 subs r3, r2, r3 8012464: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 8012466: 683b ldr r3, [r7, #0] 8012468: 681b ldr r3, [r3, #0] 801246a: f1b3 3fff cmp.w r3, #4294967295 801246e: d102 bne.n 8012476 { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 8012470: 2300 movs r3, #0 8012472: 61fb str r3, [r7, #28] 8012474: e023 b.n 80124be } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 8012476: 687b ldr r3, [r7, #4] 8012478: 681a ldr r2, [r3, #0] 801247a: 4b15 ldr r3, [pc, #84] ; (80124d0 ) 801247c: 681b ldr r3, [r3, #0] 801247e: 429a cmp r2, r3 8012480: d007 beq.n 8012492 8012482: 687b ldr r3, [r7, #4] 8012484: 685b ldr r3, [r3, #4] 8012486: 69ba ldr r2, [r7, #24] 8012488: 429a cmp r2, r3 801248a: d302 bcc.n 8012492 /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 801248c: 2301 movs r3, #1 801248e: 61fb str r3, [r7, #28] 8012490: e015 b.n 80124be } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 8012492: 683b ldr r3, [r7, #0] 8012494: 681b ldr r3, [r3, #0] 8012496: 697a ldr r2, [r7, #20] 8012498: 429a cmp r2, r3 801249a: d20b bcs.n 80124b4 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 801249c: 683b ldr r3, [r7, #0] 801249e: 681a ldr r2, [r3, #0] 80124a0: 697b ldr r3, [r7, #20] 80124a2: 1ad2 subs r2, r2, r3 80124a4: 683b ldr r3, [r7, #0] 80124a6: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 80124a8: 6878 ldr r0, [r7, #4] 80124aa: f7ff ff9b bl 80123e4 xReturn = pdFALSE; 80124ae: 2300 movs r3, #0 80124b0: 61fb str r3, [r7, #28] 80124b2: e004 b.n 80124be } else { *pxTicksToWait = 0; 80124b4: 683b ldr r3, [r7, #0] 80124b6: 2200 movs r2, #0 80124b8: 601a str r2, [r3, #0] xReturn = pdTRUE; 80124ba: 2301 movs r3, #1 80124bc: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 80124be: f000 ffd1 bl 8013464 return xReturn; 80124c2: 69fb ldr r3, [r7, #28] } 80124c4: 4618 mov r0, r3 80124c6: 3720 adds r7, #32 80124c8: 46bd mov sp, r7 80124ca: bd80 pop {r7, pc} 80124cc: 2400c024 .word 0x2400c024 80124d0: 2400c038 .word 0x2400c038 080124d4 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 80124d4: b480 push {r7} 80124d6: af00 add r7, sp, #0 xYieldPending = pdTRUE; 80124d8: 4b03 ldr r3, [pc, #12] ; (80124e8 ) 80124da: 2201 movs r2, #1 80124dc: 601a str r2, [r3, #0] } 80124de: bf00 nop 80124e0: 46bd mov sp, r7 80124e2: f85d 7b04 ldr.w r7, [sp], #4 80124e6: 4770 bx lr 80124e8: 2400c034 .word 0x2400c034 080124ec : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 80124ec: b580 push {r7, lr} 80124ee: b082 sub sp, #8 80124f0: af00 add r7, sp, #0 80124f2: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 80124f4: f000 f852 bl 801259c A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 80124f8: 4b06 ldr r3, [pc, #24] ; (8012514 ) 80124fa: 681b ldr r3, [r3, #0] 80124fc: 2b01 cmp r3, #1 80124fe: d9f9 bls.n 80124f4 { taskYIELD(); 8012500: 4b05 ldr r3, [pc, #20] ; (8012518 ) 8012502: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8012506: 601a str r2, [r3, #0] 8012508: f3bf 8f4f dsb sy 801250c: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 8012510: e7f0 b.n 80124f4 8012512: bf00 nop 8012514: 2400bf24 .word 0x2400bf24 8012518: e000ed04 .word 0xe000ed04 0801251c : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 801251c: b580 push {r7, lr} 801251e: b082 sub sp, #8 8012520: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8012522: 2300 movs r3, #0 8012524: 607b str r3, [r7, #4] 8012526: e00c b.n 8012542 { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 8012528: 687a ldr r2, [r7, #4] 801252a: 4613 mov r3, r2 801252c: 009b lsls r3, r3, #2 801252e: 4413 add r3, r2 8012530: 009b lsls r3, r3, #2 8012532: 4a12 ldr r2, [pc, #72] ; (801257c ) 8012534: 4413 add r3, r2 8012536: 4618 mov r0, r3 8012538: f7fe f9a1 bl 801087e for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 801253c: 687b ldr r3, [r7, #4] 801253e: 3301 adds r3, #1 8012540: 607b str r3, [r7, #4] 8012542: 687b ldr r3, [r7, #4] 8012544: 2b06 cmp r3, #6 8012546: d9ef bls.n 8012528 } vListInitialise( &xDelayedTaskList1 ); 8012548: 480d ldr r0, [pc, #52] ; (8012580 ) 801254a: f7fe f998 bl 801087e vListInitialise( &xDelayedTaskList2 ); 801254e: 480d ldr r0, [pc, #52] ; (8012584 ) 8012550: f7fe f995 bl 801087e vListInitialise( &xPendingReadyList ); 8012554: 480c ldr r0, [pc, #48] ; (8012588 ) 8012556: f7fe f992 bl 801087e #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 801255a: 480c ldr r0, [pc, #48] ; (801258c ) 801255c: f7fe f98f bl 801087e } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 8012560: 480b ldr r0, [pc, #44] ; (8012590 ) 8012562: f7fe f98c bl 801087e } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 8012566: 4b0b ldr r3, [pc, #44] ; (8012594 ) 8012568: 4a05 ldr r2, [pc, #20] ; (8012580 ) 801256a: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 801256c: 4b0a ldr r3, [pc, #40] ; (8012598 ) 801256e: 4a05 ldr r2, [pc, #20] ; (8012584 ) 8012570: 601a str r2, [r3, #0] } 8012572: bf00 nop 8012574: 3708 adds r7, #8 8012576: 46bd mov sp, r7 8012578: bd80 pop {r7, pc} 801257a: bf00 nop 801257c: 2400bf24 .word 0x2400bf24 8012580: 2400bfb0 .word 0x2400bfb0 8012584: 2400bfc4 .word 0x2400bfc4 8012588: 2400bfe0 .word 0x2400bfe0 801258c: 2400bff4 .word 0x2400bff4 8012590: 2400c00c .word 0x2400c00c 8012594: 2400bfd8 .word 0x2400bfd8 8012598: 2400bfdc .word 0x2400bfdc 0801259c : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 801259c: b580 push {r7, lr} 801259e: b082 sub sp, #8 80125a0: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 80125a2: e019 b.n 80125d8 { taskENTER_CRITICAL(); 80125a4: f000 ff2e bl 8013404 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80125a8: 4b10 ldr r3, [pc, #64] ; (80125ec ) 80125aa: 68db ldr r3, [r3, #12] 80125ac: 68db ldr r3, [r3, #12] 80125ae: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80125b0: 687b ldr r3, [r7, #4] 80125b2: 3304 adds r3, #4 80125b4: 4618 mov r0, r3 80125b6: f7fe f9ec bl 8010992 --uxCurrentNumberOfTasks; 80125ba: 4b0d ldr r3, [pc, #52] ; (80125f0 ) 80125bc: 681b ldr r3, [r3, #0] 80125be: 3b01 subs r3, #1 80125c0: 4a0b ldr r2, [pc, #44] ; (80125f0 ) 80125c2: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 80125c4: 4b0b ldr r3, [pc, #44] ; (80125f4 ) 80125c6: 681b ldr r3, [r3, #0] 80125c8: 3b01 subs r3, #1 80125ca: 4a0a ldr r2, [pc, #40] ; (80125f4 ) 80125cc: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 80125ce: f000 ff49 bl 8013464 prvDeleteTCB( pxTCB ); 80125d2: 6878 ldr r0, [r7, #4] 80125d4: f000 f848 bl 8012668 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 80125d8: 4b06 ldr r3, [pc, #24] ; (80125f4 ) 80125da: 681b ldr r3, [r3, #0] 80125dc: 2b00 cmp r3, #0 80125de: d1e1 bne.n 80125a4 } } #endif /* INCLUDE_vTaskDelete */ } 80125e0: bf00 nop 80125e2: bf00 nop 80125e4: 3708 adds r7, #8 80125e6: 46bd mov sp, r7 80125e8: bd80 pop {r7, pc} 80125ea: bf00 nop 80125ec: 2400bff4 .word 0x2400bff4 80125f0: 2400c020 .word 0x2400c020 80125f4: 2400c008 .word 0x2400c008 080125f8 : /*-----------------------------------------------------------*/ #if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) { 80125f8: b480 push {r7} 80125fa: b085 sub sp, #20 80125fc: af00 add r7, sp, #0 80125fe: 6078 str r0, [r7, #4] uint32_t ulCount = 0U; 8012600: 2300 movs r3, #0 8012602: 60fb str r3, [r7, #12] while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE ) 8012604: e005 b.n 8012612 { pucStackByte -= portSTACK_GROWTH; 8012606: 687b ldr r3, [r7, #4] 8012608: 3301 adds r3, #1 801260a: 607b str r3, [r7, #4] ulCount++; 801260c: 68fb ldr r3, [r7, #12] 801260e: 3301 adds r3, #1 8012610: 60fb str r3, [r7, #12] while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE ) 8012612: 687b ldr r3, [r7, #4] 8012614: 781b ldrb r3, [r3, #0] 8012616: 2ba5 cmp r3, #165 ; 0xa5 8012618: d0f5 beq.n 8012606 } ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */ 801261a: 68fb ldr r3, [r7, #12] 801261c: 089b lsrs r3, r3, #2 801261e: 60fb str r3, [r7, #12] return ( configSTACK_DEPTH_TYPE ) ulCount; 8012620: 68fb ldr r3, [r7, #12] 8012622: b29b uxth r3, r3 } 8012624: 4618 mov r0, r3 8012626: 3714 adds r7, #20 8012628: 46bd mov sp, r7 801262a: f85d 7b04 ldr.w r7, [sp], #4 801262e: 4770 bx lr 08012630 : /*-----------------------------------------------------------*/ #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) { 8012630: b580 push {r7, lr} 8012632: b086 sub sp, #24 8012634: af00 add r7, sp, #0 8012636: 6078 str r0, [r7, #4] TCB_t *pxTCB; uint8_t *pucEndOfStack; UBaseType_t uxReturn; pxTCB = prvGetTCBFromHandle( xTask ); 8012638: 687b ldr r3, [r7, #4] 801263a: 2b00 cmp r3, #0 801263c: d102 bne.n 8012644 801263e: 4b09 ldr r3, [pc, #36] ; (8012664 ) 8012640: 681b ldr r3, [r3, #0] 8012642: e000 b.n 8012646 8012644: 687b ldr r3, [r7, #4] 8012646: 617b str r3, [r7, #20] #if portSTACK_GROWTH < 0 { pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; 8012648: 697b ldr r3, [r7, #20] 801264a: 6b1b ldr r3, [r3, #48] ; 0x30 801264c: 613b str r3, [r7, #16] { pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; } #endif uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack ); 801264e: 6938 ldr r0, [r7, #16] 8012650: f7ff ffd2 bl 80125f8 8012654: 4603 mov r3, r0 8012656: 60fb str r3, [r7, #12] return uxReturn; 8012658: 68fb ldr r3, [r7, #12] } 801265a: 4618 mov r0, r3 801265c: 3718 adds r7, #24 801265e: 46bd mov sp, r7 8012660: bd80 pop {r7, pc} 8012662: bf00 nop 8012664: 2400bf20 .word 0x2400bf20 08012668 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 8012668: b580 push {r7, lr} 801266a: b084 sub sp, #16 801266c: af00 add r7, sp, #0 801266e: 6078 str r0, [r7, #4] #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 8012670: 687b ldr r3, [r7, #4] 8012672: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8012676: 2b00 cmp r3, #0 8012678: d108 bne.n 801268c { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 801267a: 687b ldr r3, [r7, #4] 801267c: 6b1b ldr r3, [r3, #48] ; 0x30 801267e: 4618 mov r0, r3 8012680: f001 f8ae bl 80137e0 vPortFree( pxTCB ); 8012684: 6878 ldr r0, [r7, #4] 8012686: f001 f8ab bl 80137e0 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 801268a: e018 b.n 80126be else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 801268c: 687b ldr r3, [r7, #4] 801268e: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8012692: 2b01 cmp r3, #1 8012694: d103 bne.n 801269e vPortFree( pxTCB ); 8012696: 6878 ldr r0, [r7, #4] 8012698: f001 f8a2 bl 80137e0 } 801269c: e00f b.n 80126be configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 801269e: 687b ldr r3, [r7, #4] 80126a0: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 80126a4: 2b02 cmp r3, #2 80126a6: d00a beq.n 80126be __asm volatile 80126a8: f04f 0350 mov.w r3, #80 ; 0x50 80126ac: f383 8811 msr BASEPRI, r3 80126b0: f3bf 8f6f isb sy 80126b4: f3bf 8f4f dsb sy 80126b8: 60fb str r3, [r7, #12] } 80126ba: bf00 nop 80126bc: e7fe b.n 80126bc } 80126be: bf00 nop 80126c0: 3710 adds r7, #16 80126c2: 46bd mov sp, r7 80126c4: bd80 pop {r7, pc} ... 080126c8 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 80126c8: b480 push {r7} 80126ca: b083 sub sp, #12 80126cc: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80126ce: 4b0c ldr r3, [pc, #48] ; (8012700 ) 80126d0: 681b ldr r3, [r3, #0] 80126d2: 681b ldr r3, [r3, #0] 80126d4: 2b00 cmp r3, #0 80126d6: d104 bne.n 80126e2 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 80126d8: 4b0a ldr r3, [pc, #40] ; (8012704 ) 80126da: f04f 32ff mov.w r2, #4294967295 80126de: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 80126e0: e008 b.n 80126f4 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80126e2: 4b07 ldr r3, [pc, #28] ; (8012700 ) 80126e4: 681b ldr r3, [r3, #0] 80126e6: 68db ldr r3, [r3, #12] 80126e8: 68db ldr r3, [r3, #12] 80126ea: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 80126ec: 687b ldr r3, [r7, #4] 80126ee: 685b ldr r3, [r3, #4] 80126f0: 4a04 ldr r2, [pc, #16] ; (8012704 ) 80126f2: 6013 str r3, [r2, #0] } 80126f4: bf00 nop 80126f6: 370c adds r7, #12 80126f8: 46bd mov sp, r7 80126fa: f85d 7b04 ldr.w r7, [sp], #4 80126fe: 4770 bx lr 8012700: 2400bfd8 .word 0x2400bfd8 8012704: 2400c040 .word 0x2400c040 08012708 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 8012708: b480 push {r7} 801270a: b083 sub sp, #12 801270c: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 801270e: 4b0b ldr r3, [pc, #44] ; (801273c ) 8012710: 681b ldr r3, [r3, #0] 8012712: 2b00 cmp r3, #0 8012714: d102 bne.n 801271c { xReturn = taskSCHEDULER_NOT_STARTED; 8012716: 2301 movs r3, #1 8012718: 607b str r3, [r7, #4] 801271a: e008 b.n 801272e } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801271c: 4b08 ldr r3, [pc, #32] ; (8012740 ) 801271e: 681b ldr r3, [r3, #0] 8012720: 2b00 cmp r3, #0 8012722: d102 bne.n 801272a { xReturn = taskSCHEDULER_RUNNING; 8012724: 2302 movs r3, #2 8012726: 607b str r3, [r7, #4] 8012728: e001 b.n 801272e } else { xReturn = taskSCHEDULER_SUSPENDED; 801272a: 2300 movs r3, #0 801272c: 607b str r3, [r7, #4] } } return xReturn; 801272e: 687b ldr r3, [r7, #4] } 8012730: 4618 mov r0, r3 8012732: 370c adds r7, #12 8012734: 46bd mov sp, r7 8012736: f85d 7b04 ldr.w r7, [sp], #4 801273a: 4770 bx lr 801273c: 2400c02c .word 0x2400c02c 8012740: 2400c048 .word 0x2400c048 08012744 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 8012744: b580 push {r7, lr} 8012746: b084 sub sp, #16 8012748: af00 add r7, sp, #0 801274a: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 801274c: 687b ldr r3, [r7, #4] 801274e: 60bb str r3, [r7, #8] BaseType_t xReturn = pdFALSE; 8012750: 2300 movs r3, #0 8012752: 60fb str r3, [r7, #12] /* If the mutex was given back by an interrupt while the queue was locked then the mutex holder might now be NULL. _RB_ Is this still needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 8012754: 687b ldr r3, [r7, #4] 8012756: 2b00 cmp r3, #0 8012758: d05e beq.n 8012818 { /* If the holder of the mutex has a priority below the priority of the task attempting to obtain the mutex then it will temporarily inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 801275a: 68bb ldr r3, [r7, #8] 801275c: 6ada ldr r2, [r3, #44] ; 0x2c 801275e: 4b31 ldr r3, [pc, #196] ; (8012824 ) 8012760: 681b ldr r3, [r3, #0] 8012762: 6adb ldr r3, [r3, #44] ; 0x2c 8012764: 429a cmp r2, r3 8012766: d24e bcs.n 8012806 { /* Adjust the mutex holder state to account for its new priority. Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8012768: 68bb ldr r3, [r7, #8] 801276a: 699b ldr r3, [r3, #24] 801276c: 2b00 cmp r3, #0 801276e: db06 blt.n 801277e { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8012770: 4b2c ldr r3, [pc, #176] ; (8012824 ) 8012772: 681b ldr r3, [r3, #0] 8012774: 6adb ldr r3, [r3, #44] ; 0x2c 8012776: f1c3 0207 rsb r2, r3, #7 801277a: 68bb ldr r3, [r7, #8] 801277c: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 801277e: 68bb ldr r3, [r7, #8] 8012780: 6959 ldr r1, [r3, #20] 8012782: 68bb ldr r3, [r7, #8] 8012784: 6ada ldr r2, [r3, #44] ; 0x2c 8012786: 4613 mov r3, r2 8012788: 009b lsls r3, r3, #2 801278a: 4413 add r3, r2 801278c: 009b lsls r3, r3, #2 801278e: 4a26 ldr r2, [pc, #152] ; (8012828 ) 8012790: 4413 add r3, r2 8012792: 4299 cmp r1, r3 8012794: d12f bne.n 80127f6 { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8012796: 68bb ldr r3, [r7, #8] 8012798: 3304 adds r3, #4 801279a: 4618 mov r0, r3 801279c: f7fe f8f9 bl 8010992 80127a0: 4603 mov r3, r0 80127a2: 2b00 cmp r3, #0 80127a4: d10a bne.n 80127bc { /* It is known that the task is in its ready list so there is no need to check again and the port level reset macro can be called directly. */ portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority ); 80127a6: 68bb ldr r3, [r7, #8] 80127a8: 6adb ldr r3, [r3, #44] ; 0x2c 80127aa: 2201 movs r2, #1 80127ac: fa02 f303 lsl.w r3, r2, r3 80127b0: 43da mvns r2, r3 80127b2: 4b1e ldr r3, [pc, #120] ; (801282c ) 80127b4: 681b ldr r3, [r3, #0] 80127b6: 4013 ands r3, r2 80127b8: 4a1c ldr r2, [pc, #112] ; (801282c ) 80127ba: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 80127bc: 4b19 ldr r3, [pc, #100] ; (8012824 ) 80127be: 681b ldr r3, [r3, #0] 80127c0: 6ada ldr r2, [r3, #44] ; 0x2c 80127c2: 68bb ldr r3, [r7, #8] 80127c4: 62da str r2, [r3, #44] ; 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 80127c6: 68bb ldr r3, [r7, #8] 80127c8: 6adb ldr r3, [r3, #44] ; 0x2c 80127ca: 2201 movs r2, #1 80127cc: 409a lsls r2, r3 80127ce: 4b17 ldr r3, [pc, #92] ; (801282c ) 80127d0: 681b ldr r3, [r3, #0] 80127d2: 4313 orrs r3, r2 80127d4: 4a15 ldr r2, [pc, #84] ; (801282c ) 80127d6: 6013 str r3, [r2, #0] 80127d8: 68bb ldr r3, [r7, #8] 80127da: 6ada ldr r2, [r3, #44] ; 0x2c 80127dc: 4613 mov r3, r2 80127de: 009b lsls r3, r3, #2 80127e0: 4413 add r3, r2 80127e2: 009b lsls r3, r3, #2 80127e4: 4a10 ldr r2, [pc, #64] ; (8012828 ) 80127e6: 441a add r2, r3 80127e8: 68bb ldr r3, [r7, #8] 80127ea: 3304 adds r3, #4 80127ec: 4619 mov r1, r3 80127ee: 4610 mov r0, r2 80127f0: f7fe f872 bl 80108d8 80127f4: e004 b.n 8012800 } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 80127f6: 4b0b ldr r3, [pc, #44] ; (8012824 ) 80127f8: 681b ldr r3, [r3, #0] 80127fa: 6ada ldr r2, [r3, #44] ; 0x2c 80127fc: 68bb ldr r3, [r7, #8] 80127fe: 62da str r2, [r3, #44] ; 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 8012800: 2301 movs r3, #1 8012802: 60fb str r3, [r7, #12] 8012804: e008 b.n 8012818 } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 8012806: 68bb ldr r3, [r7, #8] 8012808: 6c5a ldr r2, [r3, #68] ; 0x44 801280a: 4b06 ldr r3, [pc, #24] ; (8012824 ) 801280c: 681b ldr r3, [r3, #0] 801280e: 6adb ldr r3, [r3, #44] ; 0x2c 8012810: 429a cmp r2, r3 8012812: d201 bcs.n 8012818 current priority of the mutex holder is not lower than the priority of the task attempting to take the mutex. Therefore the mutex holder must have already inherited a priority, but inheritance would have occurred if that had not been the case. */ xReturn = pdTRUE; 8012814: 2301 movs r3, #1 8012816: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8012818: 68fb ldr r3, [r7, #12] } 801281a: 4618 mov r0, r3 801281c: 3710 adds r7, #16 801281e: 46bd mov sp, r7 8012820: bd80 pop {r7, pc} 8012822: bf00 nop 8012824: 2400bf20 .word 0x2400bf20 8012828: 2400bf24 .word 0x2400bf24 801282c: 2400c028 .word 0x2400c028 08012830 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8012830: b580 push {r7, lr} 8012832: b086 sub sp, #24 8012834: af00 add r7, sp, #0 8012836: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8012838: 687b ldr r3, [r7, #4] 801283a: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 801283c: 2300 movs r3, #0 801283e: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8012840: 687b ldr r3, [r7, #4] 8012842: 2b00 cmp r3, #0 8012844: d06e beq.n 8012924 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8012846: 4b3a ldr r3, [pc, #232] ; (8012930 ) 8012848: 681b ldr r3, [r3, #0] 801284a: 693a ldr r2, [r7, #16] 801284c: 429a cmp r2, r3 801284e: d00a beq.n 8012866 __asm volatile 8012850: f04f 0350 mov.w r3, #80 ; 0x50 8012854: f383 8811 msr BASEPRI, r3 8012858: f3bf 8f6f isb sy 801285c: f3bf 8f4f dsb sy 8012860: 60fb str r3, [r7, #12] } 8012862: bf00 nop 8012864: e7fe b.n 8012864 configASSERT( pxTCB->uxMutexesHeld ); 8012866: 693b ldr r3, [r7, #16] 8012868: 6c9b ldr r3, [r3, #72] ; 0x48 801286a: 2b00 cmp r3, #0 801286c: d10a bne.n 8012884 __asm volatile 801286e: f04f 0350 mov.w r3, #80 ; 0x50 8012872: f383 8811 msr BASEPRI, r3 8012876: f3bf 8f6f isb sy 801287a: f3bf 8f4f dsb sy 801287e: 60bb str r3, [r7, #8] } 8012880: bf00 nop 8012882: e7fe b.n 8012882 ( pxTCB->uxMutexesHeld )--; 8012884: 693b ldr r3, [r7, #16] 8012886: 6c9b ldr r3, [r3, #72] ; 0x48 8012888: 1e5a subs r2, r3, #1 801288a: 693b ldr r3, [r7, #16] 801288c: 649a str r2, [r3, #72] ; 0x48 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 801288e: 693b ldr r3, [r7, #16] 8012890: 6ada ldr r2, [r3, #44] ; 0x2c 8012892: 693b ldr r3, [r7, #16] 8012894: 6c5b ldr r3, [r3, #68] ; 0x44 8012896: 429a cmp r2, r3 8012898: d044 beq.n 8012924 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 801289a: 693b ldr r3, [r7, #16] 801289c: 6c9b ldr r3, [r3, #72] ; 0x48 801289e: 2b00 cmp r3, #0 80128a0: d140 bne.n 8012924 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 80128a2: 693b ldr r3, [r7, #16] 80128a4: 3304 adds r3, #4 80128a6: 4618 mov r0, r3 80128a8: f7fe f873 bl 8010992 80128ac: 4603 mov r3, r0 80128ae: 2b00 cmp r3, #0 80128b0: d115 bne.n 80128de { taskRESET_READY_PRIORITY( pxTCB->uxPriority ); 80128b2: 693b ldr r3, [r7, #16] 80128b4: 6ada ldr r2, [r3, #44] ; 0x2c 80128b6: 491f ldr r1, [pc, #124] ; (8012934 ) 80128b8: 4613 mov r3, r2 80128ba: 009b lsls r3, r3, #2 80128bc: 4413 add r3, r2 80128be: 009b lsls r3, r3, #2 80128c0: 440b add r3, r1 80128c2: 681b ldr r3, [r3, #0] 80128c4: 2b00 cmp r3, #0 80128c6: d10a bne.n 80128de 80128c8: 693b ldr r3, [r7, #16] 80128ca: 6adb ldr r3, [r3, #44] ; 0x2c 80128cc: 2201 movs r2, #1 80128ce: fa02 f303 lsl.w r3, r2, r3 80128d2: 43da mvns r2, r3 80128d4: 4b18 ldr r3, [pc, #96] ; (8012938 ) 80128d6: 681b ldr r3, [r3, #0] 80128d8: 4013 ands r3, r2 80128da: 4a17 ldr r2, [pc, #92] ; (8012938 ) 80128dc: 6013 str r3, [r2, #0] } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 80128de: 693b ldr r3, [r7, #16] 80128e0: 6c5a ldr r2, [r3, #68] ; 0x44 80128e2: 693b ldr r3, [r7, #16] 80128e4: 62da str r2, [r3, #44] ; 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80128e6: 693b ldr r3, [r7, #16] 80128e8: 6adb ldr r3, [r3, #44] ; 0x2c 80128ea: f1c3 0207 rsb r2, r3, #7 80128ee: 693b ldr r3, [r7, #16] 80128f0: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 80128f2: 693b ldr r3, [r7, #16] 80128f4: 6adb ldr r3, [r3, #44] ; 0x2c 80128f6: 2201 movs r2, #1 80128f8: 409a lsls r2, r3 80128fa: 4b0f ldr r3, [pc, #60] ; (8012938 ) 80128fc: 681b ldr r3, [r3, #0] 80128fe: 4313 orrs r3, r2 8012900: 4a0d ldr r2, [pc, #52] ; (8012938 ) 8012902: 6013 str r3, [r2, #0] 8012904: 693b ldr r3, [r7, #16] 8012906: 6ada ldr r2, [r3, #44] ; 0x2c 8012908: 4613 mov r3, r2 801290a: 009b lsls r3, r3, #2 801290c: 4413 add r3, r2 801290e: 009b lsls r3, r3, #2 8012910: 4a08 ldr r2, [pc, #32] ; (8012934 ) 8012912: 441a add r2, r3 8012914: 693b ldr r3, [r7, #16] 8012916: 3304 adds r3, #4 8012918: 4619 mov r1, r3 801291a: 4610 mov r0, r2 801291c: f7fd ffdc bl 80108d8 in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 8012920: 2301 movs r3, #1 8012922: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8012924: 697b ldr r3, [r7, #20] } 8012926: 4618 mov r0, r3 8012928: 3718 adds r7, #24 801292a: 46bd mov sp, r7 801292c: bd80 pop {r7, pc} 801292e: bf00 nop 8012930: 2400bf20 .word 0x2400bf20 8012934: 2400bf24 .word 0x2400bf24 8012938: 2400c028 .word 0x2400c028 0801293c : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 801293c: b580 push {r7, lr} 801293e: b088 sub sp, #32 8012940: af00 add r7, sp, #0 8012942: 6078 str r0, [r7, #4] 8012944: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 8012946: 687b ldr r3, [r7, #4] 8012948: 61bb str r3, [r7, #24] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 801294a: 2301 movs r3, #1 801294c: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 801294e: 687b ldr r3, [r7, #4] 8012950: 2b00 cmp r3, #0 8012952: d077 beq.n 8012a44 { /* If pxMutexHolder is not NULL then the holder must hold at least one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 8012954: 69bb ldr r3, [r7, #24] 8012956: 6c9b ldr r3, [r3, #72] ; 0x48 8012958: 2b00 cmp r3, #0 801295a: d10a bne.n 8012972 __asm volatile 801295c: f04f 0350 mov.w r3, #80 ; 0x50 8012960: f383 8811 msr BASEPRI, r3 8012964: f3bf 8f6f isb sy 8012968: f3bf 8f4f dsb sy 801296c: 60fb str r3, [r7, #12] } 801296e: bf00 nop 8012970: e7fe b.n 8012970 /* Determine the priority to which the priority of the task that holds the mutex should be set. This will be the greater of the holding task's base priority and the priority of the highest priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 8012972: 69bb ldr r3, [r7, #24] 8012974: 6c5b ldr r3, [r3, #68] ; 0x44 8012976: 683a ldr r2, [r7, #0] 8012978: 429a cmp r2, r3 801297a: d902 bls.n 8012982 { uxPriorityToUse = uxHighestPriorityWaitingTask; 801297c: 683b ldr r3, [r7, #0] 801297e: 61fb str r3, [r7, #28] 8012980: e002 b.n 8012988 } else { uxPriorityToUse = pxTCB->uxBasePriority; 8012982: 69bb ldr r3, [r7, #24] 8012984: 6c5b ldr r3, [r3, #68] ; 0x44 8012986: 61fb str r3, [r7, #28] } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 8012988: 69bb ldr r3, [r7, #24] 801298a: 6adb ldr r3, [r3, #44] ; 0x2c 801298c: 69fa ldr r2, [r7, #28] 801298e: 429a cmp r2, r3 8012990: d058 beq.n 8012a44 { /* Only disinherit if no other mutexes are held. This is a simplification in the priority inheritance implementation. If the task that holds the mutex is also holding other mutexes then the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 8012992: 69bb ldr r3, [r7, #24] 8012994: 6c9b ldr r3, [r3, #72] ; 0x48 8012996: 697a ldr r2, [r7, #20] 8012998: 429a cmp r2, r3 801299a: d153 bne.n 8012a44 { /* If a task has timed out because it already holds the mutex it was trying to obtain then it cannot of inherited its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 801299c: 4b2b ldr r3, [pc, #172] ; (8012a4c ) 801299e: 681b ldr r3, [r3, #0] 80129a0: 69ba ldr r2, [r7, #24] 80129a2: 429a cmp r2, r3 80129a4: d10a bne.n 80129bc __asm volatile 80129a6: f04f 0350 mov.w r3, #80 ; 0x50 80129aa: f383 8811 msr BASEPRI, r3 80129ae: f3bf 8f6f isb sy 80129b2: f3bf 8f4f dsb sy 80129b6: 60bb str r3, [r7, #8] } 80129b8: bf00 nop 80129ba: e7fe b.n 80129ba /* Disinherit the priority, remembering the previous priority to facilitate determining the subject task's state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 80129bc: 69bb ldr r3, [r7, #24] 80129be: 6adb ldr r3, [r3, #44] ; 0x2c 80129c0: 613b str r3, [r7, #16] pxTCB->uxPriority = uxPriorityToUse; 80129c2: 69bb ldr r3, [r7, #24] 80129c4: 69fa ldr r2, [r7, #28] 80129c6: 62da str r2, [r3, #44] ; 0x2c /* Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 80129c8: 69bb ldr r3, [r7, #24] 80129ca: 699b ldr r3, [r3, #24] 80129cc: 2b00 cmp r3, #0 80129ce: db04 blt.n 80129da { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80129d0: 69fb ldr r3, [r7, #28] 80129d2: f1c3 0207 rsb r2, r3, #7 80129d6: 69bb ldr r3, [r7, #24] 80129d8: 619a str r2, [r3, #24] then the task that holds the mutex could be in either the Ready, Blocked or Suspended states. Only remove the task from its current state list if it is in the Ready state as the task's priority is going to change and there is one Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 80129da: 69bb ldr r3, [r7, #24] 80129dc: 6959 ldr r1, [r3, #20] 80129de: 693a ldr r2, [r7, #16] 80129e0: 4613 mov r3, r2 80129e2: 009b lsls r3, r3, #2 80129e4: 4413 add r3, r2 80129e6: 009b lsls r3, r3, #2 80129e8: 4a19 ldr r2, [pc, #100] ; (8012a50 ) 80129ea: 4413 add r3, r2 80129ec: 4299 cmp r1, r3 80129ee: d129 bne.n 8012a44 { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 80129f0: 69bb ldr r3, [r7, #24] 80129f2: 3304 adds r3, #4 80129f4: 4618 mov r0, r3 80129f6: f7fd ffcc bl 8010992 80129fa: 4603 mov r3, r0 80129fc: 2b00 cmp r3, #0 80129fe: d10a bne.n 8012a16 { /* It is known that the task is in its ready list so there is no need to check again and the port level reset macro can be called directly. */ portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority ); 8012a00: 69bb ldr r3, [r7, #24] 8012a02: 6adb ldr r3, [r3, #44] ; 0x2c 8012a04: 2201 movs r2, #1 8012a06: fa02 f303 lsl.w r3, r2, r3 8012a0a: 43da mvns r2, r3 8012a0c: 4b11 ldr r3, [pc, #68] ; (8012a54 ) 8012a0e: 681b ldr r3, [r3, #0] 8012a10: 4013 ands r3, r2 8012a12: 4a10 ldr r2, [pc, #64] ; (8012a54 ) 8012a14: 6013 str r3, [r2, #0] else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 8012a16: 69bb ldr r3, [r7, #24] 8012a18: 6adb ldr r3, [r3, #44] ; 0x2c 8012a1a: 2201 movs r2, #1 8012a1c: 409a lsls r2, r3 8012a1e: 4b0d ldr r3, [pc, #52] ; (8012a54 ) 8012a20: 681b ldr r3, [r3, #0] 8012a22: 4313 orrs r3, r2 8012a24: 4a0b ldr r2, [pc, #44] ; (8012a54 ) 8012a26: 6013 str r3, [r2, #0] 8012a28: 69bb ldr r3, [r7, #24] 8012a2a: 6ada ldr r2, [r3, #44] ; 0x2c 8012a2c: 4613 mov r3, r2 8012a2e: 009b lsls r3, r3, #2 8012a30: 4413 add r3, r2 8012a32: 009b lsls r3, r3, #2 8012a34: 4a06 ldr r2, [pc, #24] ; (8012a50 ) 8012a36: 441a add r2, r3 8012a38: 69bb ldr r3, [r7, #24] 8012a3a: 3304 adds r3, #4 8012a3c: 4619 mov r1, r3 8012a3e: 4610 mov r0, r2 8012a40: f7fd ff4a bl 80108d8 } else { mtCOVERAGE_TEST_MARKER(); } } 8012a44: bf00 nop 8012a46: 3720 adds r7, #32 8012a48: 46bd mov sp, r7 8012a4a: bd80 pop {r7, pc} 8012a4c: 2400bf20 .word 0x2400bf20 8012a50: 2400bf24 .word 0x2400bf24 8012a54: 2400c028 .word 0x2400c028 08012a58 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 8012a58: b480 push {r7} 8012a5a: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 8012a5c: 4b07 ldr r3, [pc, #28] ; (8012a7c ) 8012a5e: 681b ldr r3, [r3, #0] 8012a60: 2b00 cmp r3, #0 8012a62: d004 beq.n 8012a6e { ( pxCurrentTCB->uxMutexesHeld )++; 8012a64: 4b05 ldr r3, [pc, #20] ; (8012a7c ) 8012a66: 681b ldr r3, [r3, #0] 8012a68: 6c9a ldr r2, [r3, #72] ; 0x48 8012a6a: 3201 adds r2, #1 8012a6c: 649a str r2, [r3, #72] ; 0x48 } return pxCurrentTCB; 8012a6e: 4b03 ldr r3, [pc, #12] ; (8012a7c ) 8012a70: 681b ldr r3, [r3, #0] } 8012a72: 4618 mov r0, r3 8012a74: 46bd mov sp, r7 8012a76: f85d 7b04 ldr.w r7, [sp], #4 8012a7a: 4770 bx lr 8012a7c: 2400bf20 .word 0x2400bf20 08012a80 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8012a80: b580 push {r7, lr} 8012a82: b084 sub sp, #16 8012a84: af00 add r7, sp, #0 8012a86: 6078 str r0, [r7, #4] 8012a88: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8012a8a: 4b29 ldr r3, [pc, #164] ; (8012b30 ) 8012a8c: 681b ldr r3, [r3, #0] 8012a8e: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8012a90: 4b28 ldr r3, [pc, #160] ; (8012b34 ) 8012a92: 681b ldr r3, [r3, #0] 8012a94: 3304 adds r3, #4 8012a96: 4618 mov r0, r3 8012a98: f7fd ff7b bl 8010992 8012a9c: 4603 mov r3, r0 8012a9e: 2b00 cmp r3, #0 8012aa0: d10b bne.n 8012aba { /* The current task must be in a ready list, so there is no need to check, and the port reset macro can be called directly. */ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ 8012aa2: 4b24 ldr r3, [pc, #144] ; (8012b34 ) 8012aa4: 681b ldr r3, [r3, #0] 8012aa6: 6adb ldr r3, [r3, #44] ; 0x2c 8012aa8: 2201 movs r2, #1 8012aaa: fa02 f303 lsl.w r3, r2, r3 8012aae: 43da mvns r2, r3 8012ab0: 4b21 ldr r3, [pc, #132] ; (8012b38 ) 8012ab2: 681b ldr r3, [r3, #0] 8012ab4: 4013 ands r3, r2 8012ab6: 4a20 ldr r2, [pc, #128] ; (8012b38 ) 8012ab8: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8012aba: 687b ldr r3, [r7, #4] 8012abc: f1b3 3fff cmp.w r3, #4294967295 8012ac0: d10a bne.n 8012ad8 8012ac2: 683b ldr r3, [r7, #0] 8012ac4: 2b00 cmp r3, #0 8012ac6: d007 beq.n 8012ad8 { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8012ac8: 4b1a ldr r3, [pc, #104] ; (8012b34 ) 8012aca: 681b ldr r3, [r3, #0] 8012acc: 3304 adds r3, #4 8012ace: 4619 mov r1, r3 8012ad0: 481a ldr r0, [pc, #104] ; (8012b3c ) 8012ad2: f7fd ff01 bl 80108d8 /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8012ad6: e026 b.n 8012b26 xTimeToWake = xConstTickCount + xTicksToWait; 8012ad8: 68fa ldr r2, [r7, #12] 8012ada: 687b ldr r3, [r7, #4] 8012adc: 4413 add r3, r2 8012ade: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 8012ae0: 4b14 ldr r3, [pc, #80] ; (8012b34 ) 8012ae2: 681b ldr r3, [r3, #0] 8012ae4: 68ba ldr r2, [r7, #8] 8012ae6: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 8012ae8: 68ba ldr r2, [r7, #8] 8012aea: 68fb ldr r3, [r7, #12] 8012aec: 429a cmp r2, r3 8012aee: d209 bcs.n 8012b04 vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8012af0: 4b13 ldr r3, [pc, #76] ; (8012b40 ) 8012af2: 681a ldr r2, [r3, #0] 8012af4: 4b0f ldr r3, [pc, #60] ; (8012b34 ) 8012af6: 681b ldr r3, [r3, #0] 8012af8: 3304 adds r3, #4 8012afa: 4619 mov r1, r3 8012afc: 4610 mov r0, r2 8012afe: f7fd ff0f bl 8010920 } 8012b02: e010 b.n 8012b26 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8012b04: 4b0f ldr r3, [pc, #60] ; (8012b44 ) 8012b06: 681a ldr r2, [r3, #0] 8012b08: 4b0a ldr r3, [pc, #40] ; (8012b34 ) 8012b0a: 681b ldr r3, [r3, #0] 8012b0c: 3304 adds r3, #4 8012b0e: 4619 mov r1, r3 8012b10: 4610 mov r0, r2 8012b12: f7fd ff05 bl 8010920 if( xTimeToWake < xNextTaskUnblockTime ) 8012b16: 4b0c ldr r3, [pc, #48] ; (8012b48 ) 8012b18: 681b ldr r3, [r3, #0] 8012b1a: 68ba ldr r2, [r7, #8] 8012b1c: 429a cmp r2, r3 8012b1e: d202 bcs.n 8012b26 xNextTaskUnblockTime = xTimeToWake; 8012b20: 4a09 ldr r2, [pc, #36] ; (8012b48 ) 8012b22: 68bb ldr r3, [r7, #8] 8012b24: 6013 str r3, [r2, #0] } 8012b26: bf00 nop 8012b28: 3710 adds r7, #16 8012b2a: 46bd mov sp, r7 8012b2c: bd80 pop {r7, pc} 8012b2e: bf00 nop 8012b30: 2400c024 .word 0x2400c024 8012b34: 2400bf20 .word 0x2400bf20 8012b38: 2400c028 .word 0x2400c028 8012b3c: 2400c00c .word 0x2400c00c 8012b40: 2400bfdc .word 0x2400bfdc 8012b44: 2400bfd8 .word 0x2400bfd8 8012b48: 2400c040 .word 0x2400c040 08012b4c : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 8012b4c: b580 push {r7, lr} 8012b4e: b08a sub sp, #40 ; 0x28 8012b50: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 8012b52: 2300 movs r3, #0 8012b54: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 8012b56: f000 faeb bl 8013130 if( xTimerQueue != NULL ) 8012b5a: 4b1c ldr r3, [pc, #112] ; (8012bcc ) 8012b5c: 681b ldr r3, [r3, #0] 8012b5e: 2b00 cmp r3, #0 8012b60: d021 beq.n 8012ba6 { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 8012b62: 2300 movs r3, #0 8012b64: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 8012b66: 2300 movs r3, #0 8012b68: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 8012b6a: 1d3a adds r2, r7, #4 8012b6c: f107 0108 add.w r1, r7, #8 8012b70: f107 030c add.w r3, r7, #12 8012b74: 4618 mov r0, r3 8012b76: f7ed fdd7 bl 8000728 xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 8012b7a: 6879 ldr r1, [r7, #4] 8012b7c: 68bb ldr r3, [r7, #8] 8012b7e: 68fa ldr r2, [r7, #12] 8012b80: 9202 str r2, [sp, #8] 8012b82: 9301 str r3, [sp, #4] 8012b84: 2302 movs r3, #2 8012b86: 9300 str r3, [sp, #0] 8012b88: 2300 movs r3, #0 8012b8a: 460a mov r2, r1 8012b8c: 4910 ldr r1, [pc, #64] ; (8012bd0 ) 8012b8e: 4811 ldr r0, [pc, #68] ; (8012bd4 ) 8012b90: f7fe ff52 bl 8011a38 8012b94: 4603 mov r3, r0 8012b96: 4a10 ldr r2, [pc, #64] ; (8012bd8 ) 8012b98: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 8012b9a: 4b0f ldr r3, [pc, #60] ; (8012bd8 ) 8012b9c: 681b ldr r3, [r3, #0] 8012b9e: 2b00 cmp r3, #0 8012ba0: d001 beq.n 8012ba6 { xReturn = pdPASS; 8012ba2: 2301 movs r3, #1 8012ba4: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 8012ba6: 697b ldr r3, [r7, #20] 8012ba8: 2b00 cmp r3, #0 8012baa: d10a bne.n 8012bc2 __asm volatile 8012bac: f04f 0350 mov.w r3, #80 ; 0x50 8012bb0: f383 8811 msr BASEPRI, r3 8012bb4: f3bf 8f6f isb sy 8012bb8: f3bf 8f4f dsb sy 8012bbc: 613b str r3, [r7, #16] } 8012bbe: bf00 nop 8012bc0: e7fe b.n 8012bc0 return xReturn; 8012bc2: 697b ldr r3, [r7, #20] } 8012bc4: 4618 mov r0, r3 8012bc6: 3718 adds r7, #24 8012bc8: 46bd mov sp, r7 8012bca: bd80 pop {r7, pc} 8012bcc: 2400c07c .word 0x2400c07c 8012bd0: 080232bc .word 0x080232bc 8012bd4: 08012d11 .word 0x08012d11 8012bd8: 2400c080 .word 0x2400c080 08012bdc : } } /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 8012bdc: b580 push {r7, lr} 8012bde: b08a sub sp, #40 ; 0x28 8012be0: af00 add r7, sp, #0 8012be2: 60f8 str r0, [r7, #12] 8012be4: 60b9 str r1, [r7, #8] 8012be6: 607a str r2, [r7, #4] 8012be8: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 8012bea: 2300 movs r3, #0 8012bec: 627b str r3, [r7, #36] ; 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 8012bee: 68fb ldr r3, [r7, #12] 8012bf0: 2b00 cmp r3, #0 8012bf2: d10a bne.n 8012c0a __asm volatile 8012bf4: f04f 0350 mov.w r3, #80 ; 0x50 8012bf8: f383 8811 msr BASEPRI, r3 8012bfc: f3bf 8f6f isb sy 8012c00: f3bf 8f4f dsb sy 8012c04: 623b str r3, [r7, #32] } 8012c06: bf00 nop 8012c08: e7fe b.n 8012c08 /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 8012c0a: 4b1a ldr r3, [pc, #104] ; (8012c74 ) 8012c0c: 681b ldr r3, [r3, #0] 8012c0e: 2b00 cmp r3, #0 8012c10: d02a beq.n 8012c68 { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 8012c12: 68bb ldr r3, [r7, #8] 8012c14: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 8012c16: 687b ldr r3, [r7, #4] 8012c18: 61bb str r3, [r7, #24] xMessage.u.xTimerParameters.pxTimer = xTimer; 8012c1a: 68fb ldr r3, [r7, #12] 8012c1c: 61fb str r3, [r7, #28] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 8012c1e: 68bb ldr r3, [r7, #8] 8012c20: 2b05 cmp r3, #5 8012c22: dc18 bgt.n 8012c56 { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 8012c24: f7ff fd70 bl 8012708 8012c28: 4603 mov r3, r0 8012c2a: 2b02 cmp r3, #2 8012c2c: d109 bne.n 8012c42 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 8012c2e: 4b11 ldr r3, [pc, #68] ; (8012c74 ) 8012c30: 6818 ldr r0, [r3, #0] 8012c32: f107 0114 add.w r1, r7, #20 8012c36: 2300 movs r3, #0 8012c38: 6b3a ldr r2, [r7, #48] ; 0x30 8012c3a: f7fe f85b bl 8010cf4 8012c3e: 6278 str r0, [r7, #36] ; 0x24 8012c40: e012 b.n 8012c68 } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 8012c42: 4b0c ldr r3, [pc, #48] ; (8012c74 ) 8012c44: 6818 ldr r0, [r3, #0] 8012c46: f107 0114 add.w r1, r7, #20 8012c4a: 2300 movs r3, #0 8012c4c: 2200 movs r2, #0 8012c4e: f7fe f851 bl 8010cf4 8012c52: 6278 str r0, [r7, #36] ; 0x24 8012c54: e008 b.n 8012c68 } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 8012c56: 4b07 ldr r3, [pc, #28] ; (8012c74 ) 8012c58: 6818 ldr r0, [r3, #0] 8012c5a: f107 0114 add.w r1, r7, #20 8012c5e: 2300 movs r3, #0 8012c60: 683a ldr r2, [r7, #0] 8012c62: f7fe f945 bl 8010ef0 8012c66: 6278 str r0, [r7, #36] ; 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8012c68: 6a7b ldr r3, [r7, #36] ; 0x24 } 8012c6a: 4618 mov r0, r3 8012c6c: 3728 adds r7, #40 ; 0x28 8012c6e: 46bd mov sp, r7 8012c70: bd80 pop {r7, pc} 8012c72: bf00 nop 8012c74: 2400c07c .word 0x2400c07c 08012c78 : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 8012c78: b580 push {r7, lr} 8012c7a: b088 sub sp, #32 8012c7c: af02 add r7, sp, #8 8012c7e: 6078 str r0, [r7, #4] 8012c80: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8012c82: 4b22 ldr r3, [pc, #136] ; (8012d0c ) 8012c84: 681b ldr r3, [r3, #0] 8012c86: 68db ldr r3, [r3, #12] 8012c88: 68db ldr r3, [r3, #12] 8012c8a: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8012c8c: 697b ldr r3, [r7, #20] 8012c8e: 3304 adds r3, #4 8012c90: 4618 mov r0, r3 8012c92: f7fd fe7e bl 8010992 traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8012c96: 697b ldr r3, [r7, #20] 8012c98: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8012c9c: f003 0304 and.w r3, r3, #4 8012ca0: 2b00 cmp r3, #0 8012ca2: d022 beq.n 8012cea { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 8012ca4: 697b ldr r3, [r7, #20] 8012ca6: 699a ldr r2, [r3, #24] 8012ca8: 687b ldr r3, [r7, #4] 8012caa: 18d1 adds r1, r2, r3 8012cac: 687b ldr r3, [r7, #4] 8012cae: 683a ldr r2, [r7, #0] 8012cb0: 6978 ldr r0, [r7, #20] 8012cb2: f000 f8d1 bl 8012e58 8012cb6: 4603 mov r3, r0 8012cb8: 2b00 cmp r3, #0 8012cba: d01f beq.n 8012cfc { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8012cbc: 2300 movs r3, #0 8012cbe: 9300 str r3, [sp, #0] 8012cc0: 2300 movs r3, #0 8012cc2: 687a ldr r2, [r7, #4] 8012cc4: 2100 movs r1, #0 8012cc6: 6978 ldr r0, [r7, #20] 8012cc8: f7ff ff88 bl 8012bdc 8012ccc: 6138 str r0, [r7, #16] configASSERT( xResult ); 8012cce: 693b ldr r3, [r7, #16] 8012cd0: 2b00 cmp r3, #0 8012cd2: d113 bne.n 8012cfc __asm volatile 8012cd4: f04f 0350 mov.w r3, #80 ; 0x50 8012cd8: f383 8811 msr BASEPRI, r3 8012cdc: f3bf 8f6f isb sy 8012ce0: f3bf 8f4f dsb sy 8012ce4: 60fb str r3, [r7, #12] } 8012ce6: bf00 nop 8012ce8: e7fe b.n 8012ce8 mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8012cea: 697b ldr r3, [r7, #20] 8012cec: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8012cf0: f023 0301 bic.w r3, r3, #1 8012cf4: b2da uxtb r2, r3 8012cf6: 697b ldr r3, [r7, #20] 8012cf8: f883 2024 strb.w r2, [r3, #36] ; 0x24 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8012cfc: 697b ldr r3, [r7, #20] 8012cfe: 6a1b ldr r3, [r3, #32] 8012d00: 6978 ldr r0, [r7, #20] 8012d02: 4798 blx r3 } 8012d04: bf00 nop 8012d06: 3718 adds r7, #24 8012d08: 46bd mov sp, r7 8012d0a: bd80 pop {r7, pc} 8012d0c: 2400c074 .word 0x2400c074 08012d10 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8012d10: b580 push {r7, lr} 8012d12: b084 sub sp, #16 8012d14: af00 add r7, sp, #0 8012d16: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8012d18: f107 0308 add.w r3, r7, #8 8012d1c: 4618 mov r0, r3 8012d1e: f000 f857 bl 8012dd0 8012d22: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 8012d24: 68bb ldr r3, [r7, #8] 8012d26: 4619 mov r1, r3 8012d28: 68f8 ldr r0, [r7, #12] 8012d2a: f000 f803 bl 8012d34 /* Empty the command queue. */ prvProcessReceivedCommands(); 8012d2e: f000 f8d5 bl 8012edc xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8012d32: e7f1 b.n 8012d18 08012d34 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8012d34: b580 push {r7, lr} 8012d36: b084 sub sp, #16 8012d38: af00 add r7, sp, #0 8012d3a: 6078 str r0, [r7, #4] 8012d3c: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 8012d3e: f7ff f8b1 bl 8011ea4 /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8012d42: f107 0308 add.w r3, r7, #8 8012d46: 4618 mov r0, r3 8012d48: f000 f866 bl 8012e18 8012d4c: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 8012d4e: 68bb ldr r3, [r7, #8] 8012d50: 2b00 cmp r3, #0 8012d52: d130 bne.n 8012db6 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8012d54: 683b ldr r3, [r7, #0] 8012d56: 2b00 cmp r3, #0 8012d58: d10a bne.n 8012d70 8012d5a: 687a ldr r2, [r7, #4] 8012d5c: 68fb ldr r3, [r7, #12] 8012d5e: 429a cmp r2, r3 8012d60: d806 bhi.n 8012d70 { ( void ) xTaskResumeAll(); 8012d62: f7ff f8ad bl 8011ec0 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 8012d66: 68f9 ldr r1, [r7, #12] 8012d68: 6878 ldr r0, [r7, #4] 8012d6a: f7ff ff85 bl 8012c78 else { ( void ) xTaskResumeAll(); } } } 8012d6e: e024 b.n 8012dba if( xListWasEmpty != pdFALSE ) 8012d70: 683b ldr r3, [r7, #0] 8012d72: 2b00 cmp r3, #0 8012d74: d008 beq.n 8012d88 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 8012d76: 4b13 ldr r3, [pc, #76] ; (8012dc4 ) 8012d78: 681b ldr r3, [r3, #0] 8012d7a: 681b ldr r3, [r3, #0] 8012d7c: 2b00 cmp r3, #0 8012d7e: d101 bne.n 8012d84 8012d80: 2301 movs r3, #1 8012d82: e000 b.n 8012d86 8012d84: 2300 movs r3, #0 8012d86: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 8012d88: 4b0f ldr r3, [pc, #60] ; (8012dc8 ) 8012d8a: 6818 ldr r0, [r3, #0] 8012d8c: 687a ldr r2, [r7, #4] 8012d8e: 68fb ldr r3, [r7, #12] 8012d90: 1ad3 subs r3, r2, r3 8012d92: 683a ldr r2, [r7, #0] 8012d94: 4619 mov r1, r3 8012d96: f7fe fe1b bl 80119d0 if( xTaskResumeAll() == pdFALSE ) 8012d9a: f7ff f891 bl 8011ec0 8012d9e: 4603 mov r3, r0 8012da0: 2b00 cmp r3, #0 8012da2: d10a bne.n 8012dba portYIELD_WITHIN_API(); 8012da4: 4b09 ldr r3, [pc, #36] ; (8012dcc ) 8012da6: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8012daa: 601a str r2, [r3, #0] 8012dac: f3bf 8f4f dsb sy 8012db0: f3bf 8f6f isb sy } 8012db4: e001 b.n 8012dba ( void ) xTaskResumeAll(); 8012db6: f7ff f883 bl 8011ec0 } 8012dba: bf00 nop 8012dbc: 3710 adds r7, #16 8012dbe: 46bd mov sp, r7 8012dc0: bd80 pop {r7, pc} 8012dc2: bf00 nop 8012dc4: 2400c078 .word 0x2400c078 8012dc8: 2400c07c .word 0x2400c07c 8012dcc: e000ed04 .word 0xe000ed04 08012dd0 : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 8012dd0: b480 push {r7} 8012dd2: b085 sub sp, #20 8012dd4: af00 add r7, sp, #0 8012dd6: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 8012dd8: 4b0e ldr r3, [pc, #56] ; (8012e14 ) 8012dda: 681b ldr r3, [r3, #0] 8012ddc: 681b ldr r3, [r3, #0] 8012dde: 2b00 cmp r3, #0 8012de0: d101 bne.n 8012de6 8012de2: 2201 movs r2, #1 8012de4: e000 b.n 8012de8 8012de6: 2200 movs r2, #0 8012de8: 687b ldr r3, [r7, #4] 8012dea: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 8012dec: 687b ldr r3, [r7, #4] 8012dee: 681b ldr r3, [r3, #0] 8012df0: 2b00 cmp r3, #0 8012df2: d105 bne.n 8012e00 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8012df4: 4b07 ldr r3, [pc, #28] ; (8012e14 ) 8012df6: 681b ldr r3, [r3, #0] 8012df8: 68db ldr r3, [r3, #12] 8012dfa: 681b ldr r3, [r3, #0] 8012dfc: 60fb str r3, [r7, #12] 8012dfe: e001 b.n 8012e04 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 8012e00: 2300 movs r3, #0 8012e02: 60fb str r3, [r7, #12] } return xNextExpireTime; 8012e04: 68fb ldr r3, [r7, #12] } 8012e06: 4618 mov r0, r3 8012e08: 3714 adds r7, #20 8012e0a: 46bd mov sp, r7 8012e0c: f85d 7b04 ldr.w r7, [sp], #4 8012e10: 4770 bx lr 8012e12: bf00 nop 8012e14: 2400c074 .word 0x2400c074 08012e18 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 8012e18: b580 push {r7, lr} 8012e1a: b084 sub sp, #16 8012e1c: af00 add r7, sp, #0 8012e1e: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 8012e20: f7ff f8ea bl 8011ff8 8012e24: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 8012e26: 4b0b ldr r3, [pc, #44] ; (8012e54 ) 8012e28: 681b ldr r3, [r3, #0] 8012e2a: 68fa ldr r2, [r7, #12] 8012e2c: 429a cmp r2, r3 8012e2e: d205 bcs.n 8012e3c { prvSwitchTimerLists(); 8012e30: f000 f91a bl 8013068 *pxTimerListsWereSwitched = pdTRUE; 8012e34: 687b ldr r3, [r7, #4] 8012e36: 2201 movs r2, #1 8012e38: 601a str r2, [r3, #0] 8012e3a: e002 b.n 8012e42 } else { *pxTimerListsWereSwitched = pdFALSE; 8012e3c: 687b ldr r3, [r7, #4] 8012e3e: 2200 movs r2, #0 8012e40: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 8012e42: 4a04 ldr r2, [pc, #16] ; (8012e54 ) 8012e44: 68fb ldr r3, [r7, #12] 8012e46: 6013 str r3, [r2, #0] return xTimeNow; 8012e48: 68fb ldr r3, [r7, #12] } 8012e4a: 4618 mov r0, r3 8012e4c: 3710 adds r7, #16 8012e4e: 46bd mov sp, r7 8012e50: bd80 pop {r7, pc} 8012e52: bf00 nop 8012e54: 2400c084 .word 0x2400c084 08012e58 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 8012e58: b580 push {r7, lr} 8012e5a: b086 sub sp, #24 8012e5c: af00 add r7, sp, #0 8012e5e: 60f8 str r0, [r7, #12] 8012e60: 60b9 str r1, [r7, #8] 8012e62: 607a str r2, [r7, #4] 8012e64: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 8012e66: 2300 movs r3, #0 8012e68: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 8012e6a: 68fb ldr r3, [r7, #12] 8012e6c: 68ba ldr r2, [r7, #8] 8012e6e: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8012e70: 68fb ldr r3, [r7, #12] 8012e72: 68fa ldr r2, [r7, #12] 8012e74: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 8012e76: 68ba ldr r2, [r7, #8] 8012e78: 687b ldr r3, [r7, #4] 8012e7a: 429a cmp r2, r3 8012e7c: d812 bhi.n 8012ea4 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8012e7e: 687a ldr r2, [r7, #4] 8012e80: 683b ldr r3, [r7, #0] 8012e82: 1ad2 subs r2, r2, r3 8012e84: 68fb ldr r3, [r7, #12] 8012e86: 699b ldr r3, [r3, #24] 8012e88: 429a cmp r2, r3 8012e8a: d302 bcc.n 8012e92 { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 8012e8c: 2301 movs r3, #1 8012e8e: 617b str r3, [r7, #20] 8012e90: e01b b.n 8012eca } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 8012e92: 4b10 ldr r3, [pc, #64] ; (8012ed4 ) 8012e94: 681a ldr r2, [r3, #0] 8012e96: 68fb ldr r3, [r7, #12] 8012e98: 3304 adds r3, #4 8012e9a: 4619 mov r1, r3 8012e9c: 4610 mov r0, r2 8012e9e: f7fd fd3f bl 8010920 8012ea2: e012 b.n 8012eca } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 8012ea4: 687a ldr r2, [r7, #4] 8012ea6: 683b ldr r3, [r7, #0] 8012ea8: 429a cmp r2, r3 8012eaa: d206 bcs.n 8012eba 8012eac: 68ba ldr r2, [r7, #8] 8012eae: 683b ldr r3, [r7, #0] 8012eb0: 429a cmp r2, r3 8012eb2: d302 bcc.n 8012eba { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 8012eb4: 2301 movs r3, #1 8012eb6: 617b str r3, [r7, #20] 8012eb8: e007 b.n 8012eca } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8012eba: 4b07 ldr r3, [pc, #28] ; (8012ed8 ) 8012ebc: 681a ldr r2, [r3, #0] 8012ebe: 68fb ldr r3, [r7, #12] 8012ec0: 3304 adds r3, #4 8012ec2: 4619 mov r1, r3 8012ec4: 4610 mov r0, r2 8012ec6: f7fd fd2b bl 8010920 } } return xProcessTimerNow; 8012eca: 697b ldr r3, [r7, #20] } 8012ecc: 4618 mov r0, r3 8012ece: 3718 adds r7, #24 8012ed0: 46bd mov sp, r7 8012ed2: bd80 pop {r7, pc} 8012ed4: 2400c078 .word 0x2400c078 8012ed8: 2400c074 .word 0x2400c074 08012edc : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 8012edc: b580 push {r7, lr} 8012ede: b08c sub sp, #48 ; 0x30 8012ee0: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8012ee2: e0ae b.n 8013042 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 8012ee4: 68bb ldr r3, [r7, #8] 8012ee6: 2b00 cmp r3, #0 8012ee8: f2c0 80ab blt.w 8013042 { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 8012eec: 693b ldr r3, [r7, #16] 8012eee: 627b str r3, [r7, #36] ; 0x24 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 8012ef0: 6a7b ldr r3, [r7, #36] ; 0x24 8012ef2: 695b ldr r3, [r3, #20] 8012ef4: 2b00 cmp r3, #0 8012ef6: d004 beq.n 8012f02 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8012ef8: 6a7b ldr r3, [r7, #36] ; 0x24 8012efa: 3304 adds r3, #4 8012efc: 4618 mov r0, r3 8012efe: f7fd fd48 bl 8010992 it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8012f02: 1d3b adds r3, r7, #4 8012f04: 4618 mov r0, r3 8012f06: f7ff ff87 bl 8012e18 8012f0a: 6238 str r0, [r7, #32] switch( xMessage.xMessageID ) 8012f0c: 68bb ldr r3, [r7, #8] 8012f0e: 2b09 cmp r3, #9 8012f10: f200 8096 bhi.w 8013040 8012f14: a201 add r2, pc, #4 ; (adr r2, 8012f1c ) 8012f16: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012f1a: bf00 nop 8012f1c: 08012f45 .word 0x08012f45 8012f20: 08012f45 .word 0x08012f45 8012f24: 08012f45 .word 0x08012f45 8012f28: 08012fb9 .word 0x08012fb9 8012f2c: 08012fcd .word 0x08012fcd 8012f30: 08013017 .word 0x08013017 8012f34: 08012f45 .word 0x08012f45 8012f38: 08012f45 .word 0x08012f45 8012f3c: 08012fb9 .word 0x08012fb9 8012f40: 08012fcd .word 0x08012fcd case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8012f44: 6a7b ldr r3, [r7, #36] ; 0x24 8012f46: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8012f4a: f043 0301 orr.w r3, r3, #1 8012f4e: b2da uxtb r2, r3 8012f50: 6a7b ldr r3, [r7, #36] ; 0x24 8012f52: f883 2024 strb.w r2, [r3, #36] ; 0x24 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 8012f56: 68fa ldr r2, [r7, #12] 8012f58: 6a7b ldr r3, [r7, #36] ; 0x24 8012f5a: 699b ldr r3, [r3, #24] 8012f5c: 18d1 adds r1, r2, r3 8012f5e: 68fb ldr r3, [r7, #12] 8012f60: 6a3a ldr r2, [r7, #32] 8012f62: 6a78 ldr r0, [r7, #36] ; 0x24 8012f64: f7ff ff78 bl 8012e58 8012f68: 4603 mov r3, r0 8012f6a: 2b00 cmp r3, #0 8012f6c: d069 beq.n 8013042 { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8012f6e: 6a7b ldr r3, [r7, #36] ; 0x24 8012f70: 6a1b ldr r3, [r3, #32] 8012f72: 6a78 ldr r0, [r7, #36] ; 0x24 8012f74: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8012f76: 6a7b ldr r3, [r7, #36] ; 0x24 8012f78: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8012f7c: f003 0304 and.w r3, r3, #4 8012f80: 2b00 cmp r3, #0 8012f82: d05e beq.n 8013042 { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 8012f84: 68fa ldr r2, [r7, #12] 8012f86: 6a7b ldr r3, [r7, #36] ; 0x24 8012f88: 699b ldr r3, [r3, #24] 8012f8a: 441a add r2, r3 8012f8c: 2300 movs r3, #0 8012f8e: 9300 str r3, [sp, #0] 8012f90: 2300 movs r3, #0 8012f92: 2100 movs r1, #0 8012f94: 6a78 ldr r0, [r7, #36] ; 0x24 8012f96: f7ff fe21 bl 8012bdc 8012f9a: 61f8 str r0, [r7, #28] configASSERT( xResult ); 8012f9c: 69fb ldr r3, [r7, #28] 8012f9e: 2b00 cmp r3, #0 8012fa0: d14f bne.n 8013042 __asm volatile 8012fa2: f04f 0350 mov.w r3, #80 ; 0x50 8012fa6: f383 8811 msr BASEPRI, r3 8012faa: f3bf 8f6f isb sy 8012fae: f3bf 8f4f dsb sy 8012fb2: 61bb str r3, [r7, #24] } 8012fb4: bf00 nop 8012fb6: e7fe b.n 8012fb6 break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8012fb8: 6a7b ldr r3, [r7, #36] ; 0x24 8012fba: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8012fbe: f023 0301 bic.w r3, r3, #1 8012fc2: b2da uxtb r2, r3 8012fc4: 6a7b ldr r3, [r7, #36] ; 0x24 8012fc6: f883 2024 strb.w r2, [r3, #36] ; 0x24 break; 8012fca: e03a b.n 8013042 case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8012fcc: 6a7b ldr r3, [r7, #36] ; 0x24 8012fce: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8012fd2: f043 0301 orr.w r3, r3, #1 8012fd6: b2da uxtb r2, r3 8012fd8: 6a7b ldr r3, [r7, #36] ; 0x24 8012fda: f883 2024 strb.w r2, [r3, #36] ; 0x24 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 8012fde: 68fa ldr r2, [r7, #12] 8012fe0: 6a7b ldr r3, [r7, #36] ; 0x24 8012fe2: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 8012fe4: 6a7b ldr r3, [r7, #36] ; 0x24 8012fe6: 699b ldr r3, [r3, #24] 8012fe8: 2b00 cmp r3, #0 8012fea: d10a bne.n 8013002 __asm volatile 8012fec: f04f 0350 mov.w r3, #80 ; 0x50 8012ff0: f383 8811 msr BASEPRI, r3 8012ff4: f3bf 8f6f isb sy 8012ff8: f3bf 8f4f dsb sy 8012ffc: 617b str r3, [r7, #20] } 8012ffe: bf00 nop 8013000: e7fe b.n 8013000 be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 8013002: 6a7b ldr r3, [r7, #36] ; 0x24 8013004: 699a ldr r2, [r3, #24] 8013006: 6a3b ldr r3, [r7, #32] 8013008: 18d1 adds r1, r2, r3 801300a: 6a3b ldr r3, [r7, #32] 801300c: 6a3a ldr r2, [r7, #32] 801300e: 6a78 ldr r0, [r7, #36] ; 0x24 8013010: f7ff ff22 bl 8012e58 break; 8013014: e015 b.n 8013042 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 8013016: 6a7b ldr r3, [r7, #36] ; 0x24 8013018: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 801301c: f003 0302 and.w r3, r3, #2 8013020: 2b00 cmp r3, #0 8013022: d103 bne.n 801302c { vPortFree( pxTimer ); 8013024: 6a78 ldr r0, [r7, #36] ; 0x24 8013026: f000 fbdb bl 80137e0 801302a: e00a b.n 8013042 } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 801302c: 6a7b ldr r3, [r7, #36] ; 0x24 801302e: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8013032: f023 0301 bic.w r3, r3, #1 8013036: b2da uxtb r2, r3 8013038: 6a7b ldr r3, [r7, #36] ; 0x24 801303a: f883 2024 strb.w r2, [r3, #36] ; 0x24 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 801303e: e000 b.n 8013042 default : /* Don't expect to get here. */ break; 8013040: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8013042: 4b08 ldr r3, [pc, #32] ; (8013064 ) 8013044: 681b ldr r3, [r3, #0] 8013046: f107 0108 add.w r1, r7, #8 801304a: 2200 movs r2, #0 801304c: 4618 mov r0, r3 801304e: f7fe f877 bl 8011140 8013052: 4603 mov r3, r0 8013054: 2b00 cmp r3, #0 8013056: f47f af45 bne.w 8012ee4 } } } } 801305a: bf00 nop 801305c: bf00 nop 801305e: 3728 adds r7, #40 ; 0x28 8013060: 46bd mov sp, r7 8013062: bd80 pop {r7, pc} 8013064: 2400c07c .word 0x2400c07c 08013068 : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 8013068: b580 push {r7, lr} 801306a: b088 sub sp, #32 801306c: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 801306e: e048 b.n 8013102 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8013070: 4b2d ldr r3, [pc, #180] ; (8013128 ) 8013072: 681b ldr r3, [r3, #0] 8013074: 68db ldr r3, [r3, #12] 8013076: 681b ldr r3, [r3, #0] 8013078: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801307a: 4b2b ldr r3, [pc, #172] ; (8013128 ) 801307c: 681b ldr r3, [r3, #0] 801307e: 68db ldr r3, [r3, #12] 8013080: 68db ldr r3, [r3, #12] 8013082: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8013084: 68fb ldr r3, [r7, #12] 8013086: 3304 adds r3, #4 8013088: 4618 mov r0, r3 801308a: f7fd fc82 bl 8010992 traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 801308e: 68fb ldr r3, [r7, #12] 8013090: 6a1b ldr r3, [r3, #32] 8013092: 68f8 ldr r0, [r7, #12] 8013094: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8013096: 68fb ldr r3, [r7, #12] 8013098: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 801309c: f003 0304 and.w r3, r3, #4 80130a0: 2b00 cmp r3, #0 80130a2: d02e beq.n 8013102 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 80130a4: 68fb ldr r3, [r7, #12] 80130a6: 699b ldr r3, [r3, #24] 80130a8: 693a ldr r2, [r7, #16] 80130aa: 4413 add r3, r2 80130ac: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 80130ae: 68ba ldr r2, [r7, #8] 80130b0: 693b ldr r3, [r7, #16] 80130b2: 429a cmp r2, r3 80130b4: d90e bls.n 80130d4 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 80130b6: 68fb ldr r3, [r7, #12] 80130b8: 68ba ldr r2, [r7, #8] 80130ba: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 80130bc: 68fb ldr r3, [r7, #12] 80130be: 68fa ldr r2, [r7, #12] 80130c0: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 80130c2: 4b19 ldr r3, [pc, #100] ; (8013128 ) 80130c4: 681a ldr r2, [r3, #0] 80130c6: 68fb ldr r3, [r7, #12] 80130c8: 3304 adds r3, #4 80130ca: 4619 mov r1, r3 80130cc: 4610 mov r0, r2 80130ce: f7fd fc27 bl 8010920 80130d2: e016 b.n 8013102 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 80130d4: 2300 movs r3, #0 80130d6: 9300 str r3, [sp, #0] 80130d8: 2300 movs r3, #0 80130da: 693a ldr r2, [r7, #16] 80130dc: 2100 movs r1, #0 80130de: 68f8 ldr r0, [r7, #12] 80130e0: f7ff fd7c bl 8012bdc 80130e4: 6078 str r0, [r7, #4] configASSERT( xResult ); 80130e6: 687b ldr r3, [r7, #4] 80130e8: 2b00 cmp r3, #0 80130ea: d10a bne.n 8013102 __asm volatile 80130ec: f04f 0350 mov.w r3, #80 ; 0x50 80130f0: f383 8811 msr BASEPRI, r3 80130f4: f3bf 8f6f isb sy 80130f8: f3bf 8f4f dsb sy 80130fc: 603b str r3, [r7, #0] } 80130fe: bf00 nop 8013100: e7fe b.n 8013100 while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8013102: 4b09 ldr r3, [pc, #36] ; (8013128 ) 8013104: 681b ldr r3, [r3, #0] 8013106: 681b ldr r3, [r3, #0] 8013108: 2b00 cmp r3, #0 801310a: d1b1 bne.n 8013070 { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 801310c: 4b06 ldr r3, [pc, #24] ; (8013128 ) 801310e: 681b ldr r3, [r3, #0] 8013110: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 8013112: 4b06 ldr r3, [pc, #24] ; (801312c ) 8013114: 681b ldr r3, [r3, #0] 8013116: 4a04 ldr r2, [pc, #16] ; (8013128 ) 8013118: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 801311a: 4a04 ldr r2, [pc, #16] ; (801312c ) 801311c: 697b ldr r3, [r7, #20] 801311e: 6013 str r3, [r2, #0] } 8013120: bf00 nop 8013122: 3718 adds r7, #24 8013124: 46bd mov sp, r7 8013126: bd80 pop {r7, pc} 8013128: 2400c074 .word 0x2400c074 801312c: 2400c078 .word 0x2400c078 08013130 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 8013130: b580 push {r7, lr} 8013132: b082 sub sp, #8 8013134: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 8013136: f000 f965 bl 8013404 { if( xTimerQueue == NULL ) 801313a: 4b15 ldr r3, [pc, #84] ; (8013190 ) 801313c: 681b ldr r3, [r3, #0] 801313e: 2b00 cmp r3, #0 8013140: d120 bne.n 8013184 { vListInitialise( &xActiveTimerList1 ); 8013142: 4814 ldr r0, [pc, #80] ; (8013194 ) 8013144: f7fd fb9b bl 801087e vListInitialise( &xActiveTimerList2 ); 8013148: 4813 ldr r0, [pc, #76] ; (8013198 ) 801314a: f7fd fb98 bl 801087e pxCurrentTimerList = &xActiveTimerList1; 801314e: 4b13 ldr r3, [pc, #76] ; (801319c ) 8013150: 4a10 ldr r2, [pc, #64] ; (8013194 ) 8013152: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 8013154: 4b12 ldr r3, [pc, #72] ; (80131a0 ) 8013156: 4a10 ldr r2, [pc, #64] ; (8013198 ) 8013158: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 801315a: 2300 movs r3, #0 801315c: 9300 str r3, [sp, #0] 801315e: 4b11 ldr r3, [pc, #68] ; (80131a4 ) 8013160: 4a11 ldr r2, [pc, #68] ; (80131a8 ) 8013162: 210c movs r1, #12 8013164: 200a movs r0, #10 8013166: f7fd fca7 bl 8010ab8 801316a: 4603 mov r3, r0 801316c: 4a08 ldr r2, [pc, #32] ; (8013190 ) 801316e: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 8013170: 4b07 ldr r3, [pc, #28] ; (8013190 ) 8013172: 681b ldr r3, [r3, #0] 8013174: 2b00 cmp r3, #0 8013176: d005 beq.n 8013184 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 8013178: 4b05 ldr r3, [pc, #20] ; (8013190 ) 801317a: 681b ldr r3, [r3, #0] 801317c: 490b ldr r1, [pc, #44] ; (80131ac ) 801317e: 4618 mov r0, r3 8013180: f7fe fbd2 bl 8011928 else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8013184: f000 f96e bl 8013464 } 8013188: bf00 nop 801318a: 46bd mov sp, r7 801318c: bd80 pop {r7, pc} 801318e: bf00 nop 8013190: 2400c07c .word 0x2400c07c 8013194: 2400c04c .word 0x2400c04c 8013198: 2400c060 .word 0x2400c060 801319c: 2400c074 .word 0x2400c074 80131a0: 2400c078 .word 0x2400c078 80131a4: 2400c100 .word 0x2400c100 80131a8: 2400c088 .word 0x2400c088 80131ac: 080232c4 .word 0x080232c4 080131b0 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 80131b0: b480 push {r7} 80131b2: b085 sub sp, #20 80131b4: af00 add r7, sp, #0 80131b6: 60f8 str r0, [r7, #12] 80131b8: 60b9 str r1, [r7, #8] 80131ba: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 80131bc: 68fb ldr r3, [r7, #12] 80131be: 3b04 subs r3, #4 80131c0: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 80131c2: 68fb ldr r3, [r7, #12] 80131c4: f04f 7280 mov.w r2, #16777216 ; 0x1000000 80131c8: 601a str r2, [r3, #0] pxTopOfStack--; 80131ca: 68fb ldr r3, [r7, #12] 80131cc: 3b04 subs r3, #4 80131ce: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 80131d0: 68bb ldr r3, [r7, #8] 80131d2: f023 0201 bic.w r2, r3, #1 80131d6: 68fb ldr r3, [r7, #12] 80131d8: 601a str r2, [r3, #0] pxTopOfStack--; 80131da: 68fb ldr r3, [r7, #12] 80131dc: 3b04 subs r3, #4 80131de: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 80131e0: 4a0c ldr r2, [pc, #48] ; (8013214 ) 80131e2: 68fb ldr r3, [r7, #12] 80131e4: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 80131e6: 68fb ldr r3, [r7, #12] 80131e8: 3b14 subs r3, #20 80131ea: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 80131ec: 687a ldr r2, [r7, #4] 80131ee: 68fb ldr r3, [r7, #12] 80131f0: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 80131f2: 68fb ldr r3, [r7, #12] 80131f4: 3b04 subs r3, #4 80131f6: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 80131f8: 68fb ldr r3, [r7, #12] 80131fa: f06f 0202 mvn.w r2, #2 80131fe: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 8013200: 68fb ldr r3, [r7, #12] 8013202: 3b20 subs r3, #32 8013204: 60fb str r3, [r7, #12] return pxTopOfStack; 8013206: 68fb ldr r3, [r7, #12] } 8013208: 4618 mov r0, r3 801320a: 3714 adds r7, #20 801320c: 46bd mov sp, r7 801320e: f85d 7b04 ldr.w r7, [sp], #4 8013212: 4770 bx lr 8013214: 08013219 .word 0x08013219 08013218 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8013218: b480 push {r7} 801321a: b085 sub sp, #20 801321c: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 801321e: 2300 movs r3, #0 8013220: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 8013222: 4b12 ldr r3, [pc, #72] ; (801326c ) 8013224: 681b ldr r3, [r3, #0] 8013226: f1b3 3fff cmp.w r3, #4294967295 801322a: d00a beq.n 8013242 __asm volatile 801322c: f04f 0350 mov.w r3, #80 ; 0x50 8013230: f383 8811 msr BASEPRI, r3 8013234: f3bf 8f6f isb sy 8013238: f3bf 8f4f dsb sy 801323c: 60fb str r3, [r7, #12] } 801323e: bf00 nop 8013240: e7fe b.n 8013240 __asm volatile 8013242: f04f 0350 mov.w r3, #80 ; 0x50 8013246: f383 8811 msr BASEPRI, r3 801324a: f3bf 8f6f isb sy 801324e: f3bf 8f4f dsb sy 8013252: 60bb str r3, [r7, #8] } 8013254: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8013256: bf00 nop 8013258: 687b ldr r3, [r7, #4] 801325a: 2b00 cmp r3, #0 801325c: d0fc beq.n 8013258 about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 801325e: bf00 nop 8013260: bf00 nop 8013262: 3714 adds r7, #20 8013264: 46bd mov sp, r7 8013266: f85d 7b04 ldr.w r7, [sp], #4 801326a: 4770 bx lr 801326c: 24000038 .word 0x24000038 08013270 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8013270: 4b07 ldr r3, [pc, #28] ; (8013290 ) 8013272: 6819 ldr r1, [r3, #0] 8013274: 6808 ldr r0, [r1, #0] 8013276: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801327a: f380 8809 msr PSP, r0 801327e: f3bf 8f6f isb sy 8013282: f04f 0000 mov.w r0, #0 8013286: f380 8811 msr BASEPRI, r0 801328a: 4770 bx lr 801328c: f3af 8000 nop.w 08013290 : 8013290: 2400bf20 .word 0x2400bf20 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8013294: bf00 nop 8013296: bf00 nop 08013298 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 8013298: 4808 ldr r0, [pc, #32] ; (80132bc ) 801329a: 6800 ldr r0, [r0, #0] 801329c: 6800 ldr r0, [r0, #0] 801329e: f380 8808 msr MSP, r0 80132a2: f04f 0000 mov.w r0, #0 80132a6: f380 8814 msr CONTROL, r0 80132aa: b662 cpsie i 80132ac: b661 cpsie f 80132ae: f3bf 8f4f dsb sy 80132b2: f3bf 8f6f isb sy 80132b6: df00 svc 0 80132b8: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 80132ba: bf00 nop 80132bc: e000ed08 .word 0xe000ed08 080132c0 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 80132c0: b580 push {r7, lr} 80132c2: b086 sub sp, #24 80132c4: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 80132c6: 4b46 ldr r3, [pc, #280] ; (80133e0 ) 80132c8: 681b ldr r3, [r3, #0] 80132ca: 4a46 ldr r2, [pc, #280] ; (80133e4 ) 80132cc: 4293 cmp r3, r2 80132ce: d10a bne.n 80132e6 __asm volatile 80132d0: f04f 0350 mov.w r3, #80 ; 0x50 80132d4: f383 8811 msr BASEPRI, r3 80132d8: f3bf 8f6f isb sy 80132dc: f3bf 8f4f dsb sy 80132e0: 613b str r3, [r7, #16] } 80132e2: bf00 nop 80132e4: e7fe b.n 80132e4 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 80132e6: 4b3e ldr r3, [pc, #248] ; (80133e0 ) 80132e8: 681b ldr r3, [r3, #0] 80132ea: 4a3f ldr r2, [pc, #252] ; (80133e8 ) 80132ec: 4293 cmp r3, r2 80132ee: d10a bne.n 8013306 __asm volatile 80132f0: f04f 0350 mov.w r3, #80 ; 0x50 80132f4: f383 8811 msr BASEPRI, r3 80132f8: f3bf 8f6f isb sy 80132fc: f3bf 8f4f dsb sy 8013300: 60fb str r3, [r7, #12] } 8013302: bf00 nop 8013304: e7fe b.n 8013304 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 8013306: 4b39 ldr r3, [pc, #228] ; (80133ec ) 8013308: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 801330a: 697b ldr r3, [r7, #20] 801330c: 781b ldrb r3, [r3, #0] 801330e: b2db uxtb r3, r3 8013310: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 8013312: 697b ldr r3, [r7, #20] 8013314: 22ff movs r2, #255 ; 0xff 8013316: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 8013318: 697b ldr r3, [r7, #20] 801331a: 781b ldrb r3, [r3, #0] 801331c: b2db uxtb r3, r3 801331e: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8013320: 78fb ldrb r3, [r7, #3] 8013322: b2db uxtb r3, r3 8013324: f003 0350 and.w r3, r3, #80 ; 0x50 8013328: b2da uxtb r2, r3 801332a: 4b31 ldr r3, [pc, #196] ; (80133f0 ) 801332c: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 801332e: 4b31 ldr r3, [pc, #196] ; (80133f4 ) 8013330: 2207 movs r2, #7 8013332: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8013334: e009 b.n 801334a { ulMaxPRIGROUPValue--; 8013336: 4b2f ldr r3, [pc, #188] ; (80133f4 ) 8013338: 681b ldr r3, [r3, #0] 801333a: 3b01 subs r3, #1 801333c: 4a2d ldr r2, [pc, #180] ; (80133f4 ) 801333e: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8013340: 78fb ldrb r3, [r7, #3] 8013342: b2db uxtb r3, r3 8013344: 005b lsls r3, r3, #1 8013346: b2db uxtb r3, r3 8013348: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 801334a: 78fb ldrb r3, [r7, #3] 801334c: b2db uxtb r3, r3 801334e: f003 0380 and.w r3, r3, #128 ; 0x80 8013352: 2b80 cmp r3, #128 ; 0x80 8013354: d0ef beq.n 8013336 #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 8013356: 4b27 ldr r3, [pc, #156] ; (80133f4 ) 8013358: 681b ldr r3, [r3, #0] 801335a: f1c3 0307 rsb r3, r3, #7 801335e: 2b04 cmp r3, #4 8013360: d00a beq.n 8013378 __asm volatile 8013362: f04f 0350 mov.w r3, #80 ; 0x50 8013366: f383 8811 msr BASEPRI, r3 801336a: f3bf 8f6f isb sy 801336e: f3bf 8f4f dsb sy 8013372: 60bb str r3, [r7, #8] } 8013374: bf00 nop 8013376: e7fe b.n 8013376 } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 8013378: 4b1e ldr r3, [pc, #120] ; (80133f4 ) 801337a: 681b ldr r3, [r3, #0] 801337c: 021b lsls r3, r3, #8 801337e: 4a1d ldr r2, [pc, #116] ; (80133f4 ) 8013380: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 8013382: 4b1c ldr r3, [pc, #112] ; (80133f4 ) 8013384: 681b ldr r3, [r3, #0] 8013386: f403 63e0 and.w r3, r3, #1792 ; 0x700 801338a: 4a1a ldr r2, [pc, #104] ; (80133f4 ) 801338c: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 801338e: 687b ldr r3, [r7, #4] 8013390: b2da uxtb r2, r3 8013392: 697b ldr r3, [r7, #20] 8013394: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 8013396: 4b18 ldr r3, [pc, #96] ; (80133f8 ) 8013398: 681b ldr r3, [r3, #0] 801339a: 4a17 ldr r2, [pc, #92] ; (80133f8 ) 801339c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 80133a0: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 80133a2: 4b15 ldr r3, [pc, #84] ; (80133f8 ) 80133a4: 681b ldr r3, [r3, #0] 80133a6: 4a14 ldr r2, [pc, #80] ; (80133f8 ) 80133a8: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000 80133ac: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 80133ae: f000 f8dd bl 801356c /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 80133b2: 4b12 ldr r3, [pc, #72] ; (80133fc ) 80133b4: 2200 movs r2, #0 80133b6: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 80133b8: f000 f8fc bl 80135b4 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 80133bc: 4b10 ldr r3, [pc, #64] ; (8013400 ) 80133be: 681b ldr r3, [r3, #0] 80133c0: 4a0f ldr r2, [pc, #60] ; (8013400 ) 80133c2: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000 80133c6: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 80133c8: f7ff ff66 bl 8013298 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 80133cc: f7fe feee bl 80121ac prvTaskExitError(); 80133d0: f7ff ff22 bl 8013218 /* Should not get here! */ return 0; 80133d4: 2300 movs r3, #0 } 80133d6: 4618 mov r0, r3 80133d8: 3718 adds r7, #24 80133da: 46bd mov sp, r7 80133dc: bd80 pop {r7, pc} 80133de: bf00 nop 80133e0: e000ed00 .word 0xe000ed00 80133e4: 410fc271 .word 0x410fc271 80133e8: 410fc270 .word 0x410fc270 80133ec: e000e400 .word 0xe000e400 80133f0: 2400c148 .word 0x2400c148 80133f4: 2400c14c .word 0x2400c14c 80133f8: e000ed20 .word 0xe000ed20 80133fc: 24000038 .word 0x24000038 8013400: e000ef34 .word 0xe000ef34 08013404 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8013404: b480 push {r7} 8013406: b083 sub sp, #12 8013408: af00 add r7, sp, #0 __asm volatile 801340a: f04f 0350 mov.w r3, #80 ; 0x50 801340e: f383 8811 msr BASEPRI, r3 8013412: f3bf 8f6f isb sy 8013416: f3bf 8f4f dsb sy 801341a: 607b str r3, [r7, #4] } 801341c: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 801341e: 4b0f ldr r3, [pc, #60] ; (801345c ) 8013420: 681b ldr r3, [r3, #0] 8013422: 3301 adds r3, #1 8013424: 4a0d ldr r2, [pc, #52] ; (801345c ) 8013426: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 8013428: 4b0c ldr r3, [pc, #48] ; (801345c ) 801342a: 681b ldr r3, [r3, #0] 801342c: 2b01 cmp r3, #1 801342e: d10f bne.n 8013450 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8013430: 4b0b ldr r3, [pc, #44] ; (8013460 ) 8013432: 681b ldr r3, [r3, #0] 8013434: b2db uxtb r3, r3 8013436: 2b00 cmp r3, #0 8013438: d00a beq.n 8013450 __asm volatile 801343a: f04f 0350 mov.w r3, #80 ; 0x50 801343e: f383 8811 msr BASEPRI, r3 8013442: f3bf 8f6f isb sy 8013446: f3bf 8f4f dsb sy 801344a: 603b str r3, [r7, #0] } 801344c: bf00 nop 801344e: e7fe b.n 801344e } } 8013450: bf00 nop 8013452: 370c adds r7, #12 8013454: 46bd mov sp, r7 8013456: f85d 7b04 ldr.w r7, [sp], #4 801345a: 4770 bx lr 801345c: 24000038 .word 0x24000038 8013460: e000ed04 .word 0xe000ed04 08013464 : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 8013464: b480 push {r7} 8013466: b083 sub sp, #12 8013468: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 801346a: 4b12 ldr r3, [pc, #72] ; (80134b4 ) 801346c: 681b ldr r3, [r3, #0] 801346e: 2b00 cmp r3, #0 8013470: d10a bne.n 8013488 __asm volatile 8013472: f04f 0350 mov.w r3, #80 ; 0x50 8013476: f383 8811 msr BASEPRI, r3 801347a: f3bf 8f6f isb sy 801347e: f3bf 8f4f dsb sy 8013482: 607b str r3, [r7, #4] } 8013484: bf00 nop 8013486: e7fe b.n 8013486 uxCriticalNesting--; 8013488: 4b0a ldr r3, [pc, #40] ; (80134b4 ) 801348a: 681b ldr r3, [r3, #0] 801348c: 3b01 subs r3, #1 801348e: 4a09 ldr r2, [pc, #36] ; (80134b4 ) 8013490: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 8013492: 4b08 ldr r3, [pc, #32] ; (80134b4 ) 8013494: 681b ldr r3, [r3, #0] 8013496: 2b00 cmp r3, #0 8013498: d105 bne.n 80134a6 801349a: 2300 movs r3, #0 801349c: 603b str r3, [r7, #0] __asm volatile 801349e: 683b ldr r3, [r7, #0] 80134a0: f383 8811 msr BASEPRI, r3 } 80134a4: bf00 nop { portENABLE_INTERRUPTS(); } } 80134a6: bf00 nop 80134a8: 370c adds r7, #12 80134aa: 46bd mov sp, r7 80134ac: f85d 7b04 ldr.w r7, [sp], #4 80134b0: 4770 bx lr 80134b2: bf00 nop 80134b4: 24000038 .word 0x24000038 ... 080134c0 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 80134c0: f3ef 8009 mrs r0, PSP 80134c4: f3bf 8f6f isb sy 80134c8: 4b15 ldr r3, [pc, #84] ; (8013520 ) 80134ca: 681a ldr r2, [r3, #0] 80134cc: f01e 0f10 tst.w lr, #16 80134d0: bf08 it eq 80134d2: ed20 8a10 vstmdbeq r0!, {s16-s31} 80134d6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80134da: 6010 str r0, [r2, #0] 80134dc: e92d 0009 stmdb sp!, {r0, r3} 80134e0: f04f 0050 mov.w r0, #80 ; 0x50 80134e4: f380 8811 msr BASEPRI, r0 80134e8: f3bf 8f4f dsb sy 80134ec: f3bf 8f6f isb sy 80134f0: f7fe fe5c bl 80121ac 80134f4: f04f 0000 mov.w r0, #0 80134f8: f380 8811 msr BASEPRI, r0 80134fc: bc09 pop {r0, r3} 80134fe: 6819 ldr r1, [r3, #0] 8013500: 6808 ldr r0, [r1, #0] 8013502: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8013506: f01e 0f10 tst.w lr, #16 801350a: bf08 it eq 801350c: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8013510: f380 8809 msr PSP, r0 8013514: f3bf 8f6f isb sy 8013518: 4770 bx lr 801351a: bf00 nop 801351c: f3af 8000 nop.w 08013520 : 8013520: 2400bf20 .word 0x2400bf20 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8013524: bf00 nop 8013526: bf00 nop 08013528 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8013528: b580 push {r7, lr} 801352a: b082 sub sp, #8 801352c: af00 add r7, sp, #0 __asm volatile 801352e: f04f 0350 mov.w r3, #80 ; 0x50 8013532: f383 8811 msr BASEPRI, r3 8013536: f3bf 8f6f isb sy 801353a: f3bf 8f4f dsb sy 801353e: 607b str r3, [r7, #4] } 8013540: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8013542: f7fe fd7b bl 801203c 8013546: 4603 mov r3, r0 8013548: 2b00 cmp r3, #0 801354a: d003 beq.n 8013554 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 801354c: 4b06 ldr r3, [pc, #24] ; (8013568 ) 801354e: f04f 5280 mov.w r2, #268435456 ; 0x10000000 8013552: 601a str r2, [r3, #0] 8013554: 2300 movs r3, #0 8013556: 603b str r3, [r7, #0] __asm volatile 8013558: 683b ldr r3, [r7, #0] 801355a: f383 8811 msr BASEPRI, r3 } 801355e: bf00 nop } } portENABLE_INTERRUPTS(); } 8013560: bf00 nop 8013562: 3708 adds r7, #8 8013564: 46bd mov sp, r7 8013566: bd80 pop {r7, pc} 8013568: e000ed04 .word 0xe000ed04 0801356c : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 801356c: b480 push {r7} 801356e: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 8013570: 4b0b ldr r3, [pc, #44] ; (80135a0 ) 8013572: 2200 movs r2, #0 8013574: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 8013576: 4b0b ldr r3, [pc, #44] ; (80135a4 ) 8013578: 2200 movs r2, #0 801357a: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 801357c: 4b0a ldr r3, [pc, #40] ; (80135a8 ) 801357e: 681b ldr r3, [r3, #0] 8013580: 4a0a ldr r2, [pc, #40] ; (80135ac ) 8013582: fba2 2303 umull r2, r3, r2, r3 8013586: 099b lsrs r3, r3, #6 8013588: 4a09 ldr r2, [pc, #36] ; (80135b0 ) 801358a: 3b01 subs r3, #1 801358c: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 801358e: 4b04 ldr r3, [pc, #16] ; (80135a0 ) 8013590: 2207 movs r2, #7 8013592: 601a str r2, [r3, #0] } 8013594: bf00 nop 8013596: 46bd mov sp, r7 8013598: f85d 7b04 ldr.w r7, [sp], #4 801359c: 4770 bx lr 801359e: bf00 nop 80135a0: e000e010 .word 0xe000e010 80135a4: e000e018 .word 0xe000e018 80135a8: 24000014 .word 0x24000014 80135ac: 10624dd3 .word 0x10624dd3 80135b0: e000e014 .word 0xe000e014 080135b4 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 80135b4: f8df 000c ldr.w r0, [pc, #12] ; 80135c4 80135b8: 6801 ldr r1, [r0, #0] 80135ba: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80135be: 6001 str r1, [r0, #0] 80135c0: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 80135c2: bf00 nop 80135c4: e000ed88 .word 0xe000ed88 080135c8 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 80135c8: b480 push {r7} 80135ca: b085 sub sp, #20 80135cc: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 80135ce: f3ef 8305 mrs r3, IPSR 80135d2: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 80135d4: 68fb ldr r3, [r7, #12] 80135d6: 2b0f cmp r3, #15 80135d8: d914 bls.n 8013604 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 80135da: 4a17 ldr r2, [pc, #92] ; (8013638 ) 80135dc: 68fb ldr r3, [r7, #12] 80135de: 4413 add r3, r2 80135e0: 781b ldrb r3, [r3, #0] 80135e2: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 80135e4: 4b15 ldr r3, [pc, #84] ; (801363c ) 80135e6: 781b ldrb r3, [r3, #0] 80135e8: 7afa ldrb r2, [r7, #11] 80135ea: 429a cmp r2, r3 80135ec: d20a bcs.n 8013604 __asm volatile 80135ee: f04f 0350 mov.w r3, #80 ; 0x50 80135f2: f383 8811 msr BASEPRI, r3 80135f6: f3bf 8f6f isb sy 80135fa: f3bf 8f4f dsb sy 80135fe: 607b str r3, [r7, #4] } 8013600: bf00 nop 8013602: e7fe b.n 8013602 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8013604: 4b0e ldr r3, [pc, #56] ; (8013640 ) 8013606: 681b ldr r3, [r3, #0] 8013608: f403 62e0 and.w r2, r3, #1792 ; 0x700 801360c: 4b0d ldr r3, [pc, #52] ; (8013644 ) 801360e: 681b ldr r3, [r3, #0] 8013610: 429a cmp r2, r3 8013612: d90a bls.n 801362a __asm volatile 8013614: f04f 0350 mov.w r3, #80 ; 0x50 8013618: f383 8811 msr BASEPRI, r3 801361c: f3bf 8f6f isb sy 8013620: f3bf 8f4f dsb sy 8013624: 603b str r3, [r7, #0] } 8013626: bf00 nop 8013628: e7fe b.n 8013628 } 801362a: bf00 nop 801362c: 3714 adds r7, #20 801362e: 46bd mov sp, r7 8013630: f85d 7b04 ldr.w r7, [sp], #4 8013634: 4770 bx lr 8013636: bf00 nop 8013638: e000e3f0 .word 0xe000e3f0 801363c: 2400c148 .word 0x2400c148 8013640: e000ed0c .word 0xe000ed0c 8013644: 2400c14c .word 0x2400c14c 08013648 : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 8013648: b580 push {r7, lr} 801364a: b08a sub sp, #40 ; 0x28 801364c: af00 add r7, sp, #0 801364e: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 8013650: 2300 movs r3, #0 8013652: 61fb str r3, [r7, #28] vTaskSuspendAll(); 8013654: f7fe fc26 bl 8011ea4 { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 8013658: 4b5b ldr r3, [pc, #364] ; (80137c8 ) 801365a: 681b ldr r3, [r3, #0] 801365c: 2b00 cmp r3, #0 801365e: d101 bne.n 8013664 { prvHeapInit(); 8013660: f000 f920 bl 80138a4 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 8013664: 4b59 ldr r3, [pc, #356] ; (80137cc ) 8013666: 681a ldr r2, [r3, #0] 8013668: 687b ldr r3, [r7, #4] 801366a: 4013 ands r3, r2 801366c: 2b00 cmp r3, #0 801366e: f040 8093 bne.w 8013798 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 8013672: 687b ldr r3, [r7, #4] 8013674: 2b00 cmp r3, #0 8013676: d01d beq.n 80136b4 { xWantedSize += xHeapStructSize; 8013678: 2208 movs r2, #8 801367a: 687b ldr r3, [r7, #4] 801367c: 4413 add r3, r2 801367e: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 8013680: 687b ldr r3, [r7, #4] 8013682: f003 0307 and.w r3, r3, #7 8013686: 2b00 cmp r3, #0 8013688: d014 beq.n 80136b4 { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 801368a: 687b ldr r3, [r7, #4] 801368c: f023 0307 bic.w r3, r3, #7 8013690: 3308 adds r3, #8 8013692: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 8013694: 687b ldr r3, [r7, #4] 8013696: f003 0307 and.w r3, r3, #7 801369a: 2b00 cmp r3, #0 801369c: d00a beq.n 80136b4 __asm volatile 801369e: f04f 0350 mov.w r3, #80 ; 0x50 80136a2: f383 8811 msr BASEPRI, r3 80136a6: f3bf 8f6f isb sy 80136aa: f3bf 8f4f dsb sy 80136ae: 617b str r3, [r7, #20] } 80136b0: bf00 nop 80136b2: e7fe b.n 80136b2 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 80136b4: 687b ldr r3, [r7, #4] 80136b6: 2b00 cmp r3, #0 80136b8: d06e beq.n 8013798 80136ba: 4b45 ldr r3, [pc, #276] ; (80137d0 ) 80136bc: 681b ldr r3, [r3, #0] 80136be: 687a ldr r2, [r7, #4] 80136c0: 429a cmp r2, r3 80136c2: d869 bhi.n 8013798 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 80136c4: 4b43 ldr r3, [pc, #268] ; (80137d4 ) 80136c6: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 80136c8: 4b42 ldr r3, [pc, #264] ; (80137d4 ) 80136ca: 681b ldr r3, [r3, #0] 80136cc: 627b str r3, [r7, #36] ; 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 80136ce: e004 b.n 80136da { pxPreviousBlock = pxBlock; 80136d0: 6a7b ldr r3, [r7, #36] ; 0x24 80136d2: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 80136d4: 6a7b ldr r3, [r7, #36] ; 0x24 80136d6: 681b ldr r3, [r3, #0] 80136d8: 627b str r3, [r7, #36] ; 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 80136da: 6a7b ldr r3, [r7, #36] ; 0x24 80136dc: 685b ldr r3, [r3, #4] 80136de: 687a ldr r2, [r7, #4] 80136e0: 429a cmp r2, r3 80136e2: d903 bls.n 80136ec 80136e4: 6a7b ldr r3, [r7, #36] ; 0x24 80136e6: 681b ldr r3, [r3, #0] 80136e8: 2b00 cmp r3, #0 80136ea: d1f1 bne.n 80136d0 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 80136ec: 4b36 ldr r3, [pc, #216] ; (80137c8 ) 80136ee: 681b ldr r3, [r3, #0] 80136f0: 6a7a ldr r2, [r7, #36] ; 0x24 80136f2: 429a cmp r2, r3 80136f4: d050 beq.n 8013798 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 80136f6: 6a3b ldr r3, [r7, #32] 80136f8: 681b ldr r3, [r3, #0] 80136fa: 2208 movs r2, #8 80136fc: 4413 add r3, r2 80136fe: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 8013700: 6a7b ldr r3, [r7, #36] ; 0x24 8013702: 681a ldr r2, [r3, #0] 8013704: 6a3b ldr r3, [r7, #32] 8013706: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 8013708: 6a7b ldr r3, [r7, #36] ; 0x24 801370a: 685a ldr r2, [r3, #4] 801370c: 687b ldr r3, [r7, #4] 801370e: 1ad2 subs r2, r2, r3 8013710: 2308 movs r3, #8 8013712: 005b lsls r3, r3, #1 8013714: 429a cmp r2, r3 8013716: d91f bls.n 8013758 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 8013718: 6a7a ldr r2, [r7, #36] ; 0x24 801371a: 687b ldr r3, [r7, #4] 801371c: 4413 add r3, r2 801371e: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 8013720: 69bb ldr r3, [r7, #24] 8013722: f003 0307 and.w r3, r3, #7 8013726: 2b00 cmp r3, #0 8013728: d00a beq.n 8013740 __asm volatile 801372a: f04f 0350 mov.w r3, #80 ; 0x50 801372e: f383 8811 msr BASEPRI, r3 8013732: f3bf 8f6f isb sy 8013736: f3bf 8f4f dsb sy 801373a: 613b str r3, [r7, #16] } 801373c: bf00 nop 801373e: e7fe b.n 801373e /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 8013740: 6a7b ldr r3, [r7, #36] ; 0x24 8013742: 685a ldr r2, [r3, #4] 8013744: 687b ldr r3, [r7, #4] 8013746: 1ad2 subs r2, r2, r3 8013748: 69bb ldr r3, [r7, #24] 801374a: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 801374c: 6a7b ldr r3, [r7, #36] ; 0x24 801374e: 687a ldr r2, [r7, #4] 8013750: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 8013752: 69b8 ldr r0, [r7, #24] 8013754: f000 f908 bl 8013968 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 8013758: 4b1d ldr r3, [pc, #116] ; (80137d0 ) 801375a: 681a ldr r2, [r3, #0] 801375c: 6a7b ldr r3, [r7, #36] ; 0x24 801375e: 685b ldr r3, [r3, #4] 8013760: 1ad3 subs r3, r2, r3 8013762: 4a1b ldr r2, [pc, #108] ; (80137d0 ) 8013764: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 8013766: 4b1a ldr r3, [pc, #104] ; (80137d0 ) 8013768: 681a ldr r2, [r3, #0] 801376a: 4b1b ldr r3, [pc, #108] ; (80137d8 ) 801376c: 681b ldr r3, [r3, #0] 801376e: 429a cmp r2, r3 8013770: d203 bcs.n 801377a { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 8013772: 4b17 ldr r3, [pc, #92] ; (80137d0 ) 8013774: 681b ldr r3, [r3, #0] 8013776: 4a18 ldr r2, [pc, #96] ; (80137d8 ) 8013778: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 801377a: 6a7b ldr r3, [r7, #36] ; 0x24 801377c: 685a ldr r2, [r3, #4] 801377e: 4b13 ldr r3, [pc, #76] ; (80137cc ) 8013780: 681b ldr r3, [r3, #0] 8013782: 431a orrs r2, r3 8013784: 6a7b ldr r3, [r7, #36] ; 0x24 8013786: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 8013788: 6a7b ldr r3, [r7, #36] ; 0x24 801378a: 2200 movs r2, #0 801378c: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 801378e: 4b13 ldr r3, [pc, #76] ; (80137dc ) 8013790: 681b ldr r3, [r3, #0] 8013792: 3301 adds r3, #1 8013794: 4a11 ldr r2, [pc, #68] ; (80137dc ) 8013796: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 8013798: f7fe fb92 bl 8011ec0 mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 801379c: 69fb ldr r3, [r7, #28] 801379e: f003 0307 and.w r3, r3, #7 80137a2: 2b00 cmp r3, #0 80137a4: d00a beq.n 80137bc __asm volatile 80137a6: f04f 0350 mov.w r3, #80 ; 0x50 80137aa: f383 8811 msr BASEPRI, r3 80137ae: f3bf 8f6f isb sy 80137b2: f3bf 8f4f dsb sy 80137b6: 60fb str r3, [r7, #12] } 80137b8: bf00 nop 80137ba: e7fe b.n 80137ba return pvReturn; 80137bc: 69fb ldr r3, [r7, #28] } 80137be: 4618 mov r0, r3 80137c0: 3728 adds r7, #40 ; 0x28 80137c2: 46bd mov sp, r7 80137c4: bd80 pop {r7, pc} 80137c6: bf00 nop 80137c8: 24013958 .word 0x24013958 80137cc: 2401396c .word 0x2401396c 80137d0: 2401395c .word 0x2401395c 80137d4: 24013950 .word 0x24013950 80137d8: 24013960 .word 0x24013960 80137dc: 24013964 .word 0x24013964 080137e0 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 80137e0: b580 push {r7, lr} 80137e2: b086 sub sp, #24 80137e4: af00 add r7, sp, #0 80137e6: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 80137e8: 687b ldr r3, [r7, #4] 80137ea: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 80137ec: 687b ldr r3, [r7, #4] 80137ee: 2b00 cmp r3, #0 80137f0: d04d beq.n 801388e { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 80137f2: 2308 movs r3, #8 80137f4: 425b negs r3, r3 80137f6: 697a ldr r2, [r7, #20] 80137f8: 4413 add r3, r2 80137fa: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 80137fc: 697b ldr r3, [r7, #20] 80137fe: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 8013800: 693b ldr r3, [r7, #16] 8013802: 685a ldr r2, [r3, #4] 8013804: 4b24 ldr r3, [pc, #144] ; (8013898 ) 8013806: 681b ldr r3, [r3, #0] 8013808: 4013 ands r3, r2 801380a: 2b00 cmp r3, #0 801380c: d10a bne.n 8013824 __asm volatile 801380e: f04f 0350 mov.w r3, #80 ; 0x50 8013812: f383 8811 msr BASEPRI, r3 8013816: f3bf 8f6f isb sy 801381a: f3bf 8f4f dsb sy 801381e: 60fb str r3, [r7, #12] } 8013820: bf00 nop 8013822: e7fe b.n 8013822 configASSERT( pxLink->pxNextFreeBlock == NULL ); 8013824: 693b ldr r3, [r7, #16] 8013826: 681b ldr r3, [r3, #0] 8013828: 2b00 cmp r3, #0 801382a: d00a beq.n 8013842 __asm volatile 801382c: f04f 0350 mov.w r3, #80 ; 0x50 8013830: f383 8811 msr BASEPRI, r3 8013834: f3bf 8f6f isb sy 8013838: f3bf 8f4f dsb sy 801383c: 60bb str r3, [r7, #8] } 801383e: bf00 nop 8013840: e7fe b.n 8013840 if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 8013842: 693b ldr r3, [r7, #16] 8013844: 685a ldr r2, [r3, #4] 8013846: 4b14 ldr r3, [pc, #80] ; (8013898 ) 8013848: 681b ldr r3, [r3, #0] 801384a: 4013 ands r3, r2 801384c: 2b00 cmp r3, #0 801384e: d01e beq.n 801388e { if( pxLink->pxNextFreeBlock == NULL ) 8013850: 693b ldr r3, [r7, #16] 8013852: 681b ldr r3, [r3, #0] 8013854: 2b00 cmp r3, #0 8013856: d11a bne.n 801388e { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 8013858: 693b ldr r3, [r7, #16] 801385a: 685a ldr r2, [r3, #4] 801385c: 4b0e ldr r3, [pc, #56] ; (8013898 ) 801385e: 681b ldr r3, [r3, #0] 8013860: 43db mvns r3, r3 8013862: 401a ands r2, r3 8013864: 693b ldr r3, [r7, #16] 8013866: 605a str r2, [r3, #4] vTaskSuspendAll(); 8013868: f7fe fb1c bl 8011ea4 { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 801386c: 693b ldr r3, [r7, #16] 801386e: 685a ldr r2, [r3, #4] 8013870: 4b0a ldr r3, [pc, #40] ; (801389c ) 8013872: 681b ldr r3, [r3, #0] 8013874: 4413 add r3, r2 8013876: 4a09 ldr r2, [pc, #36] ; (801389c ) 8013878: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 801387a: 6938 ldr r0, [r7, #16] 801387c: f000 f874 bl 8013968 xNumberOfSuccessfulFrees++; 8013880: 4b07 ldr r3, [pc, #28] ; (80138a0 ) 8013882: 681b ldr r3, [r3, #0] 8013884: 3301 adds r3, #1 8013886: 4a06 ldr r2, [pc, #24] ; (80138a0 ) 8013888: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 801388a: f7fe fb19 bl 8011ec0 else { mtCOVERAGE_TEST_MARKER(); } } } 801388e: bf00 nop 8013890: 3718 adds r7, #24 8013892: 46bd mov sp, r7 8013894: bd80 pop {r7, pc} 8013896: bf00 nop 8013898: 2401396c .word 0x2401396c 801389c: 2401395c .word 0x2401395c 80138a0: 24013968 .word 0x24013968 080138a4 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 80138a4: b480 push {r7} 80138a6: b085 sub sp, #20 80138a8: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 80138aa: f44f 43f0 mov.w r3, #30720 ; 0x7800 80138ae: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 80138b0: 4b27 ldr r3, [pc, #156] ; (8013950 ) 80138b2: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 80138b4: 68fb ldr r3, [r7, #12] 80138b6: f003 0307 and.w r3, r3, #7 80138ba: 2b00 cmp r3, #0 80138bc: d00c beq.n 80138d8 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 80138be: 68fb ldr r3, [r7, #12] 80138c0: 3307 adds r3, #7 80138c2: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80138c4: 68fb ldr r3, [r7, #12] 80138c6: f023 0307 bic.w r3, r3, #7 80138ca: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 80138cc: 68ba ldr r2, [r7, #8] 80138ce: 68fb ldr r3, [r7, #12] 80138d0: 1ad3 subs r3, r2, r3 80138d2: 4a1f ldr r2, [pc, #124] ; (8013950 ) 80138d4: 4413 add r3, r2 80138d6: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 80138d8: 68fb ldr r3, [r7, #12] 80138da: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 80138dc: 4a1d ldr r2, [pc, #116] ; (8013954 ) 80138de: 687b ldr r3, [r7, #4] 80138e0: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 80138e2: 4b1c ldr r3, [pc, #112] ; (8013954 ) 80138e4: 2200 movs r2, #0 80138e6: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 80138e8: 687b ldr r3, [r7, #4] 80138ea: 68ba ldr r2, [r7, #8] 80138ec: 4413 add r3, r2 80138ee: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 80138f0: 2208 movs r2, #8 80138f2: 68fb ldr r3, [r7, #12] 80138f4: 1a9b subs r3, r3, r2 80138f6: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80138f8: 68fb ldr r3, [r7, #12] 80138fa: f023 0307 bic.w r3, r3, #7 80138fe: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 8013900: 68fb ldr r3, [r7, #12] 8013902: 4a15 ldr r2, [pc, #84] ; (8013958 ) 8013904: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 8013906: 4b14 ldr r3, [pc, #80] ; (8013958 ) 8013908: 681b ldr r3, [r3, #0] 801390a: 2200 movs r2, #0 801390c: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 801390e: 4b12 ldr r3, [pc, #72] ; (8013958 ) 8013910: 681b ldr r3, [r3, #0] 8013912: 2200 movs r2, #0 8013914: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 8013916: 687b ldr r3, [r7, #4] 8013918: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 801391a: 683b ldr r3, [r7, #0] 801391c: 68fa ldr r2, [r7, #12] 801391e: 1ad2 subs r2, r2, r3 8013920: 683b ldr r3, [r7, #0] 8013922: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 8013924: 4b0c ldr r3, [pc, #48] ; (8013958 ) 8013926: 681a ldr r2, [r3, #0] 8013928: 683b ldr r3, [r7, #0] 801392a: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 801392c: 683b ldr r3, [r7, #0] 801392e: 685b ldr r3, [r3, #4] 8013930: 4a0a ldr r2, [pc, #40] ; (801395c ) 8013932: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8013934: 683b ldr r3, [r7, #0] 8013936: 685b ldr r3, [r3, #4] 8013938: 4a09 ldr r2, [pc, #36] ; (8013960 ) 801393a: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 801393c: 4b09 ldr r3, [pc, #36] ; (8013964 ) 801393e: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 8013942: 601a str r2, [r3, #0] } 8013944: bf00 nop 8013946: 3714 adds r7, #20 8013948: 46bd mov sp, r7 801394a: f85d 7b04 ldr.w r7, [sp], #4 801394e: 4770 bx lr 8013950: 2400c150 .word 0x2400c150 8013954: 24013950 .word 0x24013950 8013958: 24013958 .word 0x24013958 801395c: 24013960 .word 0x24013960 8013960: 2401395c .word 0x2401395c 8013964: 2401396c .word 0x2401396c 08013968 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 8013968: b480 push {r7} 801396a: b085 sub sp, #20 801396c: af00 add r7, sp, #0 801396e: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 8013970: 4b28 ldr r3, [pc, #160] ; (8013a14 ) 8013972: 60fb str r3, [r7, #12] 8013974: e002 b.n 801397c 8013976: 68fb ldr r3, [r7, #12] 8013978: 681b ldr r3, [r3, #0] 801397a: 60fb str r3, [r7, #12] 801397c: 68fb ldr r3, [r7, #12] 801397e: 681b ldr r3, [r3, #0] 8013980: 687a ldr r2, [r7, #4] 8013982: 429a cmp r2, r3 8013984: d8f7 bhi.n 8013976 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 8013986: 68fb ldr r3, [r7, #12] 8013988: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 801398a: 68fb ldr r3, [r7, #12] 801398c: 685b ldr r3, [r3, #4] 801398e: 68ba ldr r2, [r7, #8] 8013990: 4413 add r3, r2 8013992: 687a ldr r2, [r7, #4] 8013994: 429a cmp r2, r3 8013996: d108 bne.n 80139aa { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 8013998: 68fb ldr r3, [r7, #12] 801399a: 685a ldr r2, [r3, #4] 801399c: 687b ldr r3, [r7, #4] 801399e: 685b ldr r3, [r3, #4] 80139a0: 441a add r2, r3 80139a2: 68fb ldr r3, [r7, #12] 80139a4: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 80139a6: 68fb ldr r3, [r7, #12] 80139a8: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 80139aa: 687b ldr r3, [r7, #4] 80139ac: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 80139ae: 687b ldr r3, [r7, #4] 80139b0: 685b ldr r3, [r3, #4] 80139b2: 68ba ldr r2, [r7, #8] 80139b4: 441a add r2, r3 80139b6: 68fb ldr r3, [r7, #12] 80139b8: 681b ldr r3, [r3, #0] 80139ba: 429a cmp r2, r3 80139bc: d118 bne.n 80139f0 { if( pxIterator->pxNextFreeBlock != pxEnd ) 80139be: 68fb ldr r3, [r7, #12] 80139c0: 681a ldr r2, [r3, #0] 80139c2: 4b15 ldr r3, [pc, #84] ; (8013a18 ) 80139c4: 681b ldr r3, [r3, #0] 80139c6: 429a cmp r2, r3 80139c8: d00d beq.n 80139e6 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 80139ca: 687b ldr r3, [r7, #4] 80139cc: 685a ldr r2, [r3, #4] 80139ce: 68fb ldr r3, [r7, #12] 80139d0: 681b ldr r3, [r3, #0] 80139d2: 685b ldr r3, [r3, #4] 80139d4: 441a add r2, r3 80139d6: 687b ldr r3, [r7, #4] 80139d8: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 80139da: 68fb ldr r3, [r7, #12] 80139dc: 681b ldr r3, [r3, #0] 80139de: 681a ldr r2, [r3, #0] 80139e0: 687b ldr r3, [r7, #4] 80139e2: 601a str r2, [r3, #0] 80139e4: e008 b.n 80139f8 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 80139e6: 4b0c ldr r3, [pc, #48] ; (8013a18 ) 80139e8: 681a ldr r2, [r3, #0] 80139ea: 687b ldr r3, [r7, #4] 80139ec: 601a str r2, [r3, #0] 80139ee: e003 b.n 80139f8 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 80139f0: 68fb ldr r3, [r7, #12] 80139f2: 681a ldr r2, [r3, #0] 80139f4: 687b ldr r3, [r7, #4] 80139f6: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 80139f8: 68fa ldr r2, [r7, #12] 80139fa: 687b ldr r3, [r7, #4] 80139fc: 429a cmp r2, r3 80139fe: d002 beq.n 8013a06 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 8013a00: 68fb ldr r3, [r7, #12] 8013a02: 687a ldr r2, [r7, #4] 8013a04: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8013a06: bf00 nop 8013a08: 3714 adds r7, #20 8013a0a: 46bd mov sp, r7 8013a0c: f85d 7b04 ldr.w r7, [sp], #4 8013a10: 4770 bx lr 8013a12: bf00 nop 8013a14: 24013950 .word 0x24013950 8013a18: 24013958 .word 0x24013958 08013a1c : * @param apimsg a struct containing the function to call and its parameters * @return ERR_OK if the function was called, another err_t if not */ static err_t netconn_apimsg(tcpip_callback_fn fn, struct api_msg *apimsg) { 8013a1c: b580 push {r7, lr} 8013a1e: b084 sub sp, #16 8013a20: af00 add r7, sp, #0 8013a22: 6078 str r0, [r7, #4] 8013a24: 6039 str r1, [r7, #0] err_t err; #ifdef LWIP_DEBUG /* catch functions that don't set err */ apimsg->err = ERR_VAL; 8013a26: 683b ldr r3, [r7, #0] 8013a28: 22fa movs r2, #250 ; 0xfa 8013a2a: 711a strb r2, [r3, #4] #if LWIP_NETCONN_SEM_PER_THREAD apimsg->op_completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); #endif /* LWIP_NETCONN_SEM_PER_THREAD */ err = tcpip_send_msg_wait_sem(fn, apimsg, LWIP_API_MSG_SEM(apimsg)); 8013a2c: 683b ldr r3, [r7, #0] 8013a2e: 681b ldr r3, [r3, #0] 8013a30: 330c adds r3, #12 8013a32: 461a mov r2, r3 8013a34: 6839 ldr r1, [r7, #0] 8013a36: 6878 ldr r0, [r7, #4] 8013a38: f002 fa22 bl 8015e80 8013a3c: 4603 mov r3, r0 8013a3e: 73fb strb r3, [r7, #15] if (err == ERR_OK) { 8013a40: f997 300f ldrsb.w r3, [r7, #15] 8013a44: 2b00 cmp r3, #0 8013a46: d103 bne.n 8013a50 return apimsg->err; 8013a48: 683b ldr r3, [r7, #0] 8013a4a: f993 3004 ldrsb.w r3, [r3, #4] 8013a4e: e001 b.n 8013a54 } return err; 8013a50: f997 300f ldrsb.w r3, [r7, #15] } 8013a54: 4618 mov r0, r3 8013a56: 3710 adds r7, #16 8013a58: 46bd mov sp, r7 8013a5a: bd80 pop {r7, pc} 08013a5c : * @return a newly allocated struct netconn or * NULL on memory error */ struct netconn * netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, netconn_callback callback) { 8013a5c: b580 push {r7, lr} 8013a5e: b08c sub sp, #48 ; 0x30 8013a60: af00 add r7, sp, #0 8013a62: 4603 mov r3, r0 8013a64: 603a str r2, [r7, #0] 8013a66: 71fb strb r3, [r7, #7] 8013a68: 460b mov r3, r1 8013a6a: 71bb strb r3, [r7, #6] struct netconn *conn; API_MSG_VAR_DECLARE(msg); API_MSG_VAR_ALLOC_RETURN_NULL(msg); conn = netconn_alloc(t, callback); 8013a6c: 79fb ldrb r3, [r7, #7] 8013a6e: 6839 ldr r1, [r7, #0] 8013a70: 4618 mov r0, r3 8013a72: f000 ffeb bl 8014a4c 8013a76: 62f8 str r0, [r7, #44] ; 0x2c if (conn != NULL) { 8013a78: 6afb ldr r3, [r7, #44] ; 0x2c 8013a7a: 2b00 cmp r3, #0 8013a7c: d054 beq.n 8013b28 err_t err; API_MSG_VAR_REF(msg).msg.n.proto = proto; 8013a7e: 79bb ldrb r3, [r7, #6] 8013a80: 743b strb r3, [r7, #16] API_MSG_VAR_REF(msg).conn = conn; 8013a82: 6afb ldr r3, [r7, #44] ; 0x2c 8013a84: 60bb str r3, [r7, #8] err = netconn_apimsg(lwip_netconn_do_newconn, &API_MSG_VAR_REF(msg)); 8013a86: f107 0308 add.w r3, r7, #8 8013a8a: 4619 mov r1, r3 8013a8c: 4829 ldr r0, [pc, #164] ; (8013b34 ) 8013a8e: f7ff ffc5 bl 8013a1c 8013a92: 4603 mov r3, r0 8013a94: f887 302b strb.w r3, [r7, #43] ; 0x2b if (err != ERR_OK) { 8013a98: f997 302b ldrsb.w r3, [r7, #43] ; 0x2b 8013a9c: 2b00 cmp r3, #0 8013a9e: d043 beq.n 8013b28 LWIP_ASSERT("freeing conn without freeing pcb", conn->pcb.tcp == NULL); 8013aa0: 6afb ldr r3, [r7, #44] ; 0x2c 8013aa2: 685b ldr r3, [r3, #4] 8013aa4: 2b00 cmp r3, #0 8013aa6: d005 beq.n 8013ab4 8013aa8: 4b23 ldr r3, [pc, #140] ; (8013b38 ) 8013aaa: 22a3 movs r2, #163 ; 0xa3 8013aac: 4923 ldr r1, [pc, #140] ; (8013b3c ) 8013aae: 4824 ldr r0, [pc, #144] ; (8013b40 ) 8013ab0: f00d ff6a bl 8021988 LWIP_ASSERT("conn has no recvmbox", sys_mbox_valid(&conn->recvmbox)); 8013ab4: 6afb ldr r3, [r7, #44] ; 0x2c 8013ab6: 3310 adds r3, #16 8013ab8: 4618 mov r0, r3 8013aba: f00d fcb0 bl 802141e 8013abe: 4603 mov r3, r0 8013ac0: 2b00 cmp r3, #0 8013ac2: d105 bne.n 8013ad0 8013ac4: 4b1c ldr r3, [pc, #112] ; (8013b38 ) 8013ac6: 22a4 movs r2, #164 ; 0xa4 8013ac8: 491e ldr r1, [pc, #120] ; (8013b44 ) 8013aca: 481d ldr r0, [pc, #116] ; (8013b40 ) 8013acc: f00d ff5c bl 8021988 #if LWIP_TCP LWIP_ASSERT("conn->acceptmbox shouldn't exist", !sys_mbox_valid(&conn->acceptmbox)); 8013ad0: 6afb ldr r3, [r7, #44] ; 0x2c 8013ad2: 3314 adds r3, #20 8013ad4: 4618 mov r0, r3 8013ad6: f00d fca2 bl 802141e 8013ada: 4603 mov r3, r0 8013adc: 2b00 cmp r3, #0 8013ade: d005 beq.n 8013aec 8013ae0: 4b15 ldr r3, [pc, #84] ; (8013b38 ) 8013ae2: 22a6 movs r2, #166 ; 0xa6 8013ae4: 4918 ldr r1, [pc, #96] ; (8013b48 ) 8013ae6: 4816 ldr r0, [pc, #88] ; (8013b40 ) 8013ae8: f00d ff4e bl 8021988 #endif /* LWIP_TCP */ #if !LWIP_NETCONN_SEM_PER_THREAD LWIP_ASSERT("conn has no op_completed", sys_sem_valid(&conn->op_completed)); 8013aec: 6afb ldr r3, [r7, #44] ; 0x2c 8013aee: 330c adds r3, #12 8013af0: 4618 mov r0, r3 8013af2: f00d fd25 bl 8021540 8013af6: 4603 mov r3, r0 8013af8: 2b00 cmp r3, #0 8013afa: d105 bne.n 8013b08 8013afc: 4b0e ldr r3, [pc, #56] ; (8013b38 ) 8013afe: 22a9 movs r2, #169 ; 0xa9 8013b00: 4912 ldr r1, [pc, #72] ; (8013b4c ) 8013b02: 480f ldr r0, [pc, #60] ; (8013b40 ) 8013b04: f00d ff40 bl 8021988 sys_sem_free(&conn->op_completed); 8013b08: 6afb ldr r3, [r7, #44] ; 0x2c 8013b0a: 330c adds r3, #12 8013b0c: 4618 mov r0, r3 8013b0e: f00d fd0a bl 8021526 #endif /* !LWIP_NETCONN_SEM_PER_THREAD */ sys_mbox_free(&conn->recvmbox); 8013b12: 6afb ldr r3, [r7, #44] ; 0x2c 8013b14: 3310 adds r3, #16 8013b16: 4618 mov r0, r3 8013b18: f00d fbfa bl 8021310 memp_free(MEMP_NETCONN, conn); 8013b1c: 6af9 ldr r1, [r7, #44] ; 0x2c 8013b1e: 2007 movs r0, #7 8013b20: f003 f84c bl 8016bbc API_MSG_VAR_FREE(msg); return NULL; 8013b24: 2300 movs r3, #0 8013b26: e000 b.n 8013b2a } } API_MSG_VAR_FREE(msg); return conn; 8013b28: 6afb ldr r3, [r7, #44] ; 0x2c } 8013b2a: 4618 mov r0, r3 8013b2c: 3730 adds r7, #48 ; 0x30 8013b2e: 46bd mov sp, r7 8013b30: bd80 pop {r7, pc} 8013b32: bf00 nop 8013b34: 08014a21 .word 0x08014a21 8013b38: 080232cc .word 0x080232cc 8013b3c: 08023300 .word 0x08023300 8013b40: 08023324 .word 0x08023324 8013b44: 0802334c .word 0x0802334c 8013b48: 08023364 .word 0x08023364 8013b4c: 08023388 .word 0x08023388 08013b50 : * @param conn the netconn to delete * @return ERR_OK if the connection was deleted */ err_t netconn_prepare_delete(struct netconn *conn) { 8013b50: b580 push {r7, lr} 8013b52: b08c sub sp, #48 ; 0x30 8013b54: af00 add r7, sp, #0 8013b56: 6078 str r0, [r7, #4] err_t err; API_MSG_VAR_DECLARE(msg); /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */ if (conn == NULL) { 8013b58: 687b ldr r3, [r7, #4] 8013b5a: 2b00 cmp r3, #0 8013b5c: d101 bne.n 8013b62 return ERR_OK; 8013b5e: 2300 movs r3, #0 8013b60: e014 b.n 8013b8c } API_MSG_VAR_ALLOC(msg); API_MSG_VAR_REF(msg).conn = conn; 8013b62: 687b ldr r3, [r7, #4] 8013b64: 60fb str r3, [r7, #12] /* get the time we started, which is later compared to sys_now() + conn->send_timeout */ API_MSG_VAR_REF(msg).msg.sd.time_started = sys_now(); #else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ #if LWIP_TCP API_MSG_VAR_REF(msg).msg.sd.polls_left = 8013b66: 2329 movs r3, #41 ; 0x29 8013b68: 757b strb r3, [r7, #21] ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1; #endif /* LWIP_TCP */ #endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ err = netconn_apimsg(lwip_netconn_do_delconn, &API_MSG_VAR_REF(msg)); 8013b6a: f107 030c add.w r3, r7, #12 8013b6e: 4619 mov r1, r3 8013b70: 4808 ldr r0, [pc, #32] ; (8013b94 ) 8013b72: f7ff ff53 bl 8013a1c 8013b76: 4603 mov r3, r0 8013b78: f887 302f strb.w r3, [r7, #47] ; 0x2f API_MSG_VAR_FREE(msg); if (err != ERR_OK) { 8013b7c: f997 302f ldrsb.w r3, [r7, #47] ; 0x2f 8013b80: 2b00 cmp r3, #0 8013b82: d002 beq.n 8013b8a return err; 8013b84: f997 302f ldrsb.w r3, [r7, #47] ; 0x2f 8013b88: e000 b.n 8013b8c } return ERR_OK; 8013b8a: 2300 movs r3, #0 } 8013b8c: 4618 mov r0, r3 8013b8e: 3730 adds r7, #48 ; 0x30 8013b90: 46bd mov sp, r7 8013b92: bd80 pop {r7, pc} 8013b94: 08014f8d .word 0x08014f8d 08013b98 : * @param conn the netconn to delete * @return ERR_OK if the connection was deleted */ err_t netconn_delete(struct netconn *conn) { 8013b98: b580 push {r7, lr} 8013b9a: b084 sub sp, #16 8013b9c: af00 add r7, sp, #0 8013b9e: 6078 str r0, [r7, #4] err_t err; /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */ if (conn == NULL) { 8013ba0: 687b ldr r3, [r7, #4] 8013ba2: 2b00 cmp r3, #0 8013ba4: d101 bne.n 8013baa return ERR_OK; 8013ba6: 2300 movs r3, #0 8013ba8: e00d b.n 8013bc6 /* Already called netconn_prepare_delete() before */ err = ERR_OK; } else #endif /* LWIP_NETCONN_FULLDUPLEX */ { err = netconn_prepare_delete(conn); 8013baa: 6878 ldr r0, [r7, #4] 8013bac: f7ff ffd0 bl 8013b50 8013bb0: 4603 mov r3, r0 8013bb2: 73fb strb r3, [r7, #15] } if (err == ERR_OK) { 8013bb4: f997 300f ldrsb.w r3, [r7, #15] 8013bb8: 2b00 cmp r3, #0 8013bba: d102 bne.n 8013bc2 netconn_free(conn); 8013bbc: 6878 ldr r0, [r7, #4] 8013bbe: f000 ffb3 bl 8014b28 } return err; 8013bc2: f997 300f ldrsb.w r3, [r7, #15] } 8013bc6: 4618 mov r0, r3 8013bc8: 3710 adds r7, #16 8013bca: 46bd mov sp, r7 8013bcc: bd80 pop {r7, pc} ... 08013bd0 : * @param port the local port to bind the netconn to (not used for RAW) * @return ERR_OK if bound, any other err_t on failure */ err_t netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port) { 8013bd0: b580 push {r7, lr} 8013bd2: b08e sub sp, #56 ; 0x38 8013bd4: af00 add r7, sp, #0 8013bd6: 60f8 str r0, [r7, #12] 8013bd8: 60b9 str r1, [r7, #8] 8013bda: 4613 mov r3, r2 8013bdc: 80fb strh r3, [r7, #6] API_MSG_VAR_DECLARE(msg); err_t err; LWIP_ERROR("netconn_bind: invalid conn", (conn != NULL), return ERR_ARG;); 8013bde: 68fb ldr r3, [r7, #12] 8013be0: 2b00 cmp r3, #0 8013be2: d109 bne.n 8013bf8 8013be4: 4b11 ldr r3, [pc, #68] ; (8013c2c ) 8013be6: f44f 729c mov.w r2, #312 ; 0x138 8013bea: 4911 ldr r1, [pc, #68] ; (8013c30 ) 8013bec: 4811 ldr r0, [pc, #68] ; (8013c34 ) 8013bee: f00d fecb bl 8021988 8013bf2: f06f 030f mvn.w r3, #15 8013bf6: e015 b.n 8013c24 #if LWIP_IPV4 /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */ if (addr == NULL) { 8013bf8: 68bb ldr r3, [r7, #8] 8013bfa: 2b00 cmp r3, #0 8013bfc: d101 bne.n 8013c02 addr = IP4_ADDR_ANY; 8013bfe: 4b0e ldr r3, [pc, #56] ; (8013c38 ) 8013c00: 60bb str r3, [r7, #8] addr = IP_ANY_TYPE; } #endif /* LWIP_IPV4 && LWIP_IPV6 */ API_MSG_VAR_ALLOC(msg); API_MSG_VAR_REF(msg).conn = conn; 8013c02: 68fb ldr r3, [r7, #12] 8013c04: 617b str r3, [r7, #20] API_MSG_VAR_REF(msg).msg.bc.ipaddr = API_MSG_VAR_REF(addr); 8013c06: 68bb ldr r3, [r7, #8] 8013c08: 61fb str r3, [r7, #28] API_MSG_VAR_REF(msg).msg.bc.port = port; 8013c0a: 88fb ldrh r3, [r7, #6] 8013c0c: 843b strh r3, [r7, #32] err = netconn_apimsg(lwip_netconn_do_bind, &API_MSG_VAR_REF(msg)); 8013c0e: f107 0314 add.w r3, r7, #20 8013c12: 4619 mov r1, r3 8013c14: 4809 ldr r0, [pc, #36] ; (8013c3c ) 8013c16: f7ff ff01 bl 8013a1c 8013c1a: 4603 mov r3, r0 8013c1c: f887 3037 strb.w r3, [r7, #55] ; 0x37 API_MSG_VAR_FREE(msg); return err; 8013c20: f997 3037 ldrsb.w r3, [r7, #55] ; 0x37 } 8013c24: 4618 mov r0, r3 8013c26: 3738 adds r7, #56 ; 0x38 8013c28: 46bd mov sp, r7 8013c2a: bd80 pop {r7, pc} 8013c2c: 080232cc .word 0x080232cc 8013c30: 08023404 .word 0x08023404 8013c34: 08023324 .word 0x08023324 8013c38: 08026cec .word 0x08026cec 8013c3c: 08015155 .word 0x08015155 08013c40 : * @param port the remote port to connect to (no used for RAW) * @return ERR_OK if connected, return value of tcp_/udp_/raw_connect otherwise */ err_t netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port) { 8013c40: b580 push {r7, lr} 8013c42: b08e sub sp, #56 ; 0x38 8013c44: af00 add r7, sp, #0 8013c46: 60f8 str r0, [r7, #12] 8013c48: 60b9 str r1, [r7, #8] 8013c4a: 4613 mov r3, r2 8013c4c: 80fb strh r3, [r7, #6] API_MSG_VAR_DECLARE(msg); err_t err; LWIP_ERROR("netconn_connect: invalid conn", (conn != NULL), return ERR_ARG;); 8013c4e: 68fb ldr r3, [r7, #12] 8013c50: 2b00 cmp r3, #0 8013c52: d109 bne.n 8013c68 8013c54: 4b11 ldr r3, [pc, #68] ; (8013c9c ) 8013c56: f44f 72bf mov.w r2, #382 ; 0x17e 8013c5a: 4911 ldr r1, [pc, #68] ; (8013ca0 ) 8013c5c: 4811 ldr r0, [pc, #68] ; (8013ca4 ) 8013c5e: f00d fe93 bl 8021988 8013c62: f06f 030f mvn.w r3, #15 8013c66: e015 b.n 8013c94 #if LWIP_IPV4 /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */ if (addr == NULL) { 8013c68: 68bb ldr r3, [r7, #8] 8013c6a: 2b00 cmp r3, #0 8013c6c: d101 bne.n 8013c72 addr = IP4_ADDR_ANY; 8013c6e: 4b0e ldr r3, [pc, #56] ; (8013ca8 ) 8013c70: 60bb str r3, [r7, #8] } #endif /* LWIP_IPV4 */ API_MSG_VAR_ALLOC(msg); API_MSG_VAR_REF(msg).conn = conn; 8013c72: 68fb ldr r3, [r7, #12] 8013c74: 617b str r3, [r7, #20] API_MSG_VAR_REF(msg).msg.bc.ipaddr = API_MSG_VAR_REF(addr); 8013c76: 68bb ldr r3, [r7, #8] 8013c78: 61fb str r3, [r7, #28] API_MSG_VAR_REF(msg).msg.bc.port = port; 8013c7a: 88fb ldrh r3, [r7, #6] 8013c7c: 843b strh r3, [r7, #32] err = netconn_apimsg(lwip_netconn_do_connect, &API_MSG_VAR_REF(msg)); 8013c7e: f107 0314 add.w r3, r7, #20 8013c82: 4619 mov r1, r3 8013c84: 4809 ldr r0, [pc, #36] ; (8013cac ) 8013c86: f7ff fec9 bl 8013a1c 8013c8a: 4603 mov r3, r0 8013c8c: f887 3037 strb.w r3, [r7, #55] ; 0x37 API_MSG_VAR_FREE(msg); return err; 8013c90: f997 3037 ldrsb.w r3, [r7, #55] ; 0x37 } 8013c94: 4618 mov r0, r3 8013c96: 3738 adds r7, #56 ; 0x38 8013c98: 46bd mov sp, r7 8013c9a: bd80 pop {r7, pc} 8013c9c: 080232cc .word 0x080232cc 8013ca0: 08023440 .word 0x08023440 8013ca4: 08023324 .word 0x08023324 8013ca8: 08026cec .word 0x08026cec 8013cac: 080152e9 .word 0x080152e9 08013cb0 : * ERR_WOULDBLOCK if the netconn is nonblocking but would block to wait for data * ERR_TIMEOUT if the netconn has a receive timeout and no data was received */ static err_t netconn_recv_data(struct netconn *conn, void **new_buf, u8_t apiflags) { 8013cb0: b580 push {r7, lr} 8013cb2: b088 sub sp, #32 8013cb4: af00 add r7, sp, #0 8013cb6: 60f8 str r0, [r7, #12] 8013cb8: 60b9 str r1, [r7, #8] 8013cba: 4613 mov r3, r2 8013cbc: 71fb strb r3, [r7, #7] void *buf = NULL; 8013cbe: 2300 movs r3, #0 8013cc0: 61bb str r3, [r7, #24] u16_t len; LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;); 8013cc2: 68bb ldr r3, [r7, #8] 8013cc4: 2b00 cmp r3, #0 8013cc6: d109 bne.n 8013cdc 8013cc8: 4b58 ldr r3, [pc, #352] ; (8013e2c ) 8013cca: f44f 7212 mov.w r2, #584 ; 0x248 8013cce: 4958 ldr r1, [pc, #352] ; (8013e30 ) 8013cd0: 4858 ldr r0, [pc, #352] ; (8013e34 ) 8013cd2: f00d fe59 bl 8021988 8013cd6: f06f 030f mvn.w r3, #15 8013cda: e0a2 b.n 8013e22 *new_buf = NULL; 8013cdc: 68bb ldr r3, [r7, #8] 8013cde: 2200 movs r2, #0 8013ce0: 601a str r2, [r3, #0] LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL), return ERR_ARG;); 8013ce2: 68fb ldr r3, [r7, #12] 8013ce4: 2b00 cmp r3, #0 8013ce6: d109 bne.n 8013cfc 8013ce8: 4b50 ldr r3, [pc, #320] ; (8013e2c ) 8013cea: f240 224a movw r2, #586 ; 0x24a 8013cee: 4952 ldr r1, [pc, #328] ; (8013e38 ) 8013cf0: 4850 ldr r0, [pc, #320] ; (8013e34 ) 8013cf2: f00d fe49 bl 8021988 8013cf6: f06f 030f mvn.w r3, #15 8013cfa: e092 b.n 8013e22 if (!NETCONN_RECVMBOX_WAITABLE(conn)) { 8013cfc: 68fb ldr r3, [r7, #12] 8013cfe: 3310 adds r3, #16 8013d00: 4618 mov r0, r3 8013d02: f00d fb8c bl 802141e 8013d06: 4603 mov r3, r0 8013d08: 2b00 cmp r3, #0 8013d0a: d10e bne.n 8013d2a err_t err = netconn_err(conn); 8013d0c: 68f8 ldr r0, [r7, #12] 8013d0e: f000 fad4 bl 80142ba 8013d12: 4603 mov r3, r0 8013d14: 773b strb r3, [r7, #28] if (err != ERR_OK) { 8013d16: f997 301c ldrsb.w r3, [r7, #28] 8013d1a: 2b00 cmp r3, #0 8013d1c: d002 beq.n 8013d24 /* return pending error */ return err; 8013d1e: f997 301c ldrsb.w r3, [r7, #28] 8013d22: e07e b.n 8013e22 } return ERR_CONN; 8013d24: f06f 030a mvn.w r3, #10 8013d28: e07b b.n 8013e22 } NETCONN_MBOX_WAITING_INC(conn); if (netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK) || 8013d2a: 68fb ldr r3, [r7, #12] 8013d2c: 7f1b ldrb r3, [r3, #28] 8013d2e: f003 0302 and.w r3, r3, #2 8013d32: 2b00 cmp r3, #0 8013d34: d10f bne.n 8013d56 8013d36: 79fb ldrb r3, [r7, #7] 8013d38: f003 0304 and.w r3, r3, #4 8013d3c: 2b00 cmp r3, #0 8013d3e: d10a bne.n 8013d56 (conn->flags & NETCONN_FLAG_MBOXCLOSED) || (conn->pending_err != ERR_OK)) { 8013d40: 68fb ldr r3, [r7, #12] 8013d42: 7f1b ldrb r3, [r3, #28] 8013d44: f003 0301 and.w r3, r3, #1 if (netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK) || 8013d48: 2b00 cmp r3, #0 8013d4a: d104 bne.n 8013d56 (conn->flags & NETCONN_FLAG_MBOXCLOSED) || (conn->pending_err != ERR_OK)) { 8013d4c: 68fb ldr r3, [r7, #12] 8013d4e: f993 3008 ldrsb.w r3, [r3, #8] 8013d52: 2b00 cmp r3, #0 8013d54: d023 beq.n 8013d9e if (sys_arch_mbox_tryfetch(&conn->recvmbox, &buf) == SYS_ARCH_TIMEOUT) { 8013d56: 68fb ldr r3, [r7, #12] 8013d58: 3310 adds r3, #16 8013d5a: f107 0218 add.w r2, r7, #24 8013d5e: 4611 mov r1, r2 8013d60: 4618 mov r0, r3 8013d62: f00d fb40 bl 80213e6 8013d66: 4603 mov r3, r0 8013d68: f1b3 3fff cmp.w r3, #4294967295 8013d6c: d11f bne.n 8013dae err_t err; NETCONN_MBOX_WAITING_DEC(conn); err = netconn_err(conn); 8013d6e: 68f8 ldr r0, [r7, #12] 8013d70: f000 faa3 bl 80142ba 8013d74: 4603 mov r3, r0 8013d76: 777b strb r3, [r7, #29] if (err != ERR_OK) { 8013d78: f997 301d ldrsb.w r3, [r7, #29] 8013d7c: 2b00 cmp r3, #0 8013d7e: d002 beq.n 8013d86 /* return pending error */ return err; 8013d80: f997 301d ldrsb.w r3, [r7, #29] 8013d84: e04d b.n 8013e22 } if (conn->flags & NETCONN_FLAG_MBOXCLOSED) { 8013d86: 68fb ldr r3, [r7, #12] 8013d88: 7f1b ldrb r3, [r3, #28] 8013d8a: f003 0301 and.w r3, r3, #1 8013d8e: 2b00 cmp r3, #0 8013d90: d002 beq.n 8013d98 return ERR_CONN; 8013d92: f06f 030a mvn.w r3, #10 8013d96: e044 b.n 8013e22 } return ERR_WOULDBLOCK; 8013d98: f06f 0306 mvn.w r3, #6 8013d9c: e041 b.n 8013e22 if (sys_arch_mbox_fetch(&conn->recvmbox, &buf, conn->recv_timeout) == SYS_ARCH_TIMEOUT) { NETCONN_MBOX_WAITING_DEC(conn); return ERR_TIMEOUT; } #else sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0); 8013d9e: 68fb ldr r3, [r7, #12] 8013da0: 3310 adds r3, #16 8013da2: f107 0118 add.w r1, r7, #24 8013da6: 2200 movs r2, #0 8013da8: 4618 mov r0, r3 8013daa: f00d fadd bl 8021368 } #endif #if LWIP_TCP #if (LWIP_UDP || LWIP_RAW) if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) 8013dae: 68fb ldr r3, [r7, #12] 8013db0: 781b ldrb r3, [r3, #0] 8013db2: f003 03f0 and.w r3, r3, #240 ; 0xf0 8013db6: 2b10 cmp r3, #16 8013db8: d117 bne.n 8013dea #endif /* (LWIP_UDP || LWIP_RAW) */ { err_t err; /* Check if this is an error message or a pbuf */ if (lwip_netconn_is_err_msg(buf, &err)) { 8013dba: 69bb ldr r3, [r7, #24] 8013dbc: f107 0217 add.w r2, r7, #23 8013dc0: 4611 mov r1, r2 8013dc2: 4618 mov r0, r3 8013dc4: f000 faca bl 801435c 8013dc8: 4603 mov r3, r0 8013dca: 2b00 cmp r3, #0 8013dcc: d009 beq.n 8013de2 /* new_buf has been zeroed above already */ if (err == ERR_CLSD) { 8013dce: f997 3017 ldrsb.w r3, [r7, #23] 8013dd2: f113 0f0f cmn.w r3, #15 8013dd6: d101 bne.n 8013ddc /* connection closed translates to ERR_OK with *new_buf == NULL */ return ERR_OK; 8013dd8: 2300 movs r3, #0 8013dda: e022 b.n 8013e22 } return err; 8013ddc: f997 3017 ldrsb.w r3, [r7, #23] 8013de0: e01f b.n 8013e22 } len = ((struct pbuf *)buf)->tot_len; 8013de2: 69bb ldr r3, [r7, #24] 8013de4: 891b ldrh r3, [r3, #8] 8013de6: 83fb strh r3, [r7, #30] 8013de8: e00d b.n 8013e06 #if LWIP_TCP && (LWIP_UDP || LWIP_RAW) else #endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */ #if (LWIP_UDP || LWIP_RAW) { LWIP_ASSERT("buf != NULL", buf != NULL); 8013dea: 69bb ldr r3, [r7, #24] 8013dec: 2b00 cmp r3, #0 8013dee: d106 bne.n 8013dfe 8013df0: 4b0e ldr r3, [pc, #56] ; (8013e2c ) 8013df2: f240 2291 movw r2, #657 ; 0x291 8013df6: 4911 ldr r1, [pc, #68] ; (8013e3c ) 8013df8: 480e ldr r0, [pc, #56] ; (8013e34 ) 8013dfa: f00d fdc5 bl 8021988 len = netbuf_len((struct netbuf *)buf); 8013dfe: 69bb ldr r3, [r7, #24] 8013e00: 681b ldr r3, [r3, #0] 8013e02: 891b ldrh r3, [r3, #8] 8013e04: 83fb strh r3, [r7, #30] #if LWIP_SO_RCVBUF SYS_ARCH_DEC(conn->recv_avail, len); #endif /* LWIP_SO_RCVBUF */ /* Register event with callback */ API_EVENT(conn, NETCONN_EVT_RCVMINUS, len); 8013e06: 68fb ldr r3, [r7, #12] 8013e08: 6a5b ldr r3, [r3, #36] ; 0x24 8013e0a: 2b00 cmp r3, #0 8013e0c: d005 beq.n 8013e1a 8013e0e: 68fb ldr r3, [r7, #12] 8013e10: 6a5b ldr r3, [r3, #36] ; 0x24 8013e12: 8bfa ldrh r2, [r7, #30] 8013e14: 2101 movs r1, #1 8013e16: 68f8 ldr r0, [r7, #12] 8013e18: 4798 blx r3 LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv_data: received %p, len=%"U16_F"\n", buf, len)); *new_buf = buf; 8013e1a: 69ba ldr r2, [r7, #24] 8013e1c: 68bb ldr r3, [r7, #8] 8013e1e: 601a str r2, [r3, #0] /* don't set conn->last_err: it's only ERR_OK, anyway */ return ERR_OK; 8013e20: 2300 movs r3, #0 } 8013e22: 4618 mov r0, r3 8013e24: 3720 adds r7, #32 8013e26: 46bd mov sp, r7 8013e28: bd80 pop {r7, pc} 8013e2a: bf00 nop 8013e2c: 080232cc .word 0x080232cc 8013e30: 080234e4 .word 0x080234e4 8013e34: 08023324 .word 0x08023324 8013e38: 08023504 .word 0x08023504 8013e3c: 08023520 .word 0x08023520 08013e40 : #if LWIP_TCP static err_t netconn_tcp_recvd_msg(struct netconn *conn, size_t len, struct api_msg *msg) { 8013e40: b580 push {r7, lr} 8013e42: b084 sub sp, #16 8013e44: af00 add r7, sp, #0 8013e46: 60f8 str r0, [r7, #12] 8013e48: 60b9 str r1, [r7, #8] 8013e4a: 607a str r2, [r7, #4] LWIP_ERROR("netconn_recv_tcp_pbuf: invalid conn", (conn != NULL) && 8013e4c: 68fb ldr r3, [r7, #12] 8013e4e: 2b00 cmp r3, #0 8013e50: d005 beq.n 8013e5e 8013e52: 68fb ldr r3, [r7, #12] 8013e54: 781b ldrb r3, [r3, #0] 8013e56: f003 03f0 and.w r3, r3, #240 ; 0xf0 8013e5a: 2b10 cmp r3, #16 8013e5c: d009 beq.n 8013e72 8013e5e: 4b0c ldr r3, [pc, #48] ; (8013e90 ) 8013e60: f240 22a7 movw r2, #679 ; 0x2a7 8013e64: 490b ldr r1, [pc, #44] ; (8013e94 ) 8013e66: 480c ldr r0, [pc, #48] ; (8013e98 ) 8013e68: f00d fd8e bl 8021988 8013e6c: f06f 030f mvn.w r3, #15 8013e70: e00a b.n 8013e88 NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;); msg->conn = conn; 8013e72: 687b ldr r3, [r7, #4] 8013e74: 68fa ldr r2, [r7, #12] 8013e76: 601a str r2, [r3, #0] msg->msg.r.len = len; 8013e78: 687b ldr r3, [r7, #4] 8013e7a: 68ba ldr r2, [r7, #8] 8013e7c: 609a str r2, [r3, #8] return netconn_apimsg(lwip_netconn_do_recv, msg); 8013e7e: 6879 ldr r1, [r7, #4] 8013e80: 4806 ldr r0, [pc, #24] ; (8013e9c ) 8013e82: f7ff fdcb bl 8013a1c 8013e86: 4603 mov r3, r0 } 8013e88: 4618 mov r0, r3 8013e8a: 3710 adds r7, #16 8013e8c: 46bd mov sp, r7 8013e8e: bd80 pop {r7, pc} 8013e90: 080232cc .word 0x080232cc 8013e94: 0802352c .word 0x0802352c 8013e98: 08023324 .word 0x08023324 8013e9c: 08015465 .word 0x08015465 08013ea0 : return err; } static err_t netconn_recv_data_tcp(struct netconn *conn, struct pbuf **new_buf, u8_t apiflags) { 8013ea0: b580 push {r7, lr} 8013ea2: b090 sub sp, #64 ; 0x40 8013ea4: af00 add r7, sp, #0 8013ea6: 60f8 str r0, [r7, #12] 8013ea8: 60b9 str r1, [r7, #8] 8013eaa: 4613 mov r3, r2 8013eac: 71fb strb r3, [r7, #7] API_MSG_VAR_DECLARE(msg); #if LWIP_MPU_COMPATIBLE msg = NULL; #endif if (!NETCONN_RECVMBOX_WAITABLE(conn)) { 8013eae: 68fb ldr r3, [r7, #12] 8013eb0: 3310 adds r3, #16 8013eb2: 4618 mov r0, r3 8013eb4: f00d fab3 bl 802141e 8013eb8: 4603 mov r3, r0 8013eba: 2b00 cmp r3, #0 8013ebc: d102 bne.n 8013ec4 /* This only happens when calling this function more than once *after* receiving FIN */ return ERR_CONN; 8013ebe: f06f 030a mvn.w r3, #10 8013ec2: e06d b.n 8013fa0 } if (netconn_is_flag_set(conn, NETCONN_FIN_RX_PENDING)) { 8013ec4: 68fb ldr r3, [r7, #12] 8013ec6: 7f1b ldrb r3, [r3, #28] 8013ec8: b25b sxtb r3, r3 8013eca: 2b00 cmp r3, #0 8013ecc: da07 bge.n 8013ede netconn_clear_flags(conn, NETCONN_FIN_RX_PENDING); 8013ece: 68fb ldr r3, [r7, #12] 8013ed0: 7f1b ldrb r3, [r3, #28] 8013ed2: f003 037f and.w r3, r3, #127 ; 0x7f 8013ed6: b2da uxtb r2, r3 8013ed8: 68fb ldr r3, [r7, #12] 8013eda: 771a strb r2, [r3, #28] goto handle_fin; 8013edc: e039 b.n 8013f52 /* need to allocate API message here so empty message pool does not result in event loss * see bug #47512: MPU_COMPATIBLE may fail on empty pool */ API_MSG_VAR_ALLOC(msg); } err = netconn_recv_data(conn, (void **)new_buf, apiflags); 8013ede: 79fb ldrb r3, [r7, #7] 8013ee0: 461a mov r2, r3 8013ee2: 68b9 ldr r1, [r7, #8] 8013ee4: 68f8 ldr r0, [r7, #12] 8013ee6: f7ff fee3 bl 8013cb0 8013eea: 4603 mov r3, r0 8013eec: f887 303f strb.w r3, [r7, #63] ; 0x3f if (err != ERR_OK) { 8013ef0: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f 8013ef4: 2b00 cmp r3, #0 8013ef6: d002 beq.n 8013efe if (!(apiflags & NETCONN_NOAUTORCVD)) { API_MSG_VAR_FREE(msg); } return err; 8013ef8: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f 8013efc: e050 b.n 8013fa0 } buf = *new_buf; 8013efe: 68bb ldr r3, [r7, #8] 8013f00: 681b ldr r3, [r3, #0] 8013f02: 63bb str r3, [r7, #56] ; 0x38 if (!(apiflags & NETCONN_NOAUTORCVD)) { 8013f04: 79fb ldrb r3, [r7, #7] 8013f06: f003 0308 and.w r3, r3, #8 8013f0a: 2b00 cmp r3, #0 8013f0c: d10e bne.n 8013f2c /* Let the stack know that we have taken the data. */ u16_t len = buf ? buf->tot_len : 1; 8013f0e: 6bbb ldr r3, [r7, #56] ; 0x38 8013f10: 2b00 cmp r3, #0 8013f12: d002 beq.n 8013f1a 8013f14: 6bbb ldr r3, [r7, #56] ; 0x38 8013f16: 891b ldrh r3, [r3, #8] 8013f18: e000 b.n 8013f1c 8013f1a: 2301 movs r3, #1 8013f1c: 86fb strh r3, [r7, #54] ; 0x36 /* don't care for the return value of lwip_netconn_do_recv */ /* @todo: this should really be fixed, e.g. by retrying in poll on error */ netconn_tcp_recvd_msg(conn, len, &API_VAR_REF(msg)); 8013f1e: 8efb ldrh r3, [r7, #54] ; 0x36 8013f20: f107 0214 add.w r2, r7, #20 8013f24: 4619 mov r1, r3 8013f26: 68f8 ldr r0, [r7, #12] 8013f28: f7ff ff8a bl 8013e40 API_MSG_VAR_FREE(msg); } /* If we are closed, we indicate that we no longer wish to use the socket */ if (buf == NULL) { 8013f2c: 6bbb ldr r3, [r7, #56] ; 0x38 8013f2e: 2b00 cmp r3, #0 8013f30: d134 bne.n 8013f9c if (apiflags & NETCONN_NOFIN) { 8013f32: 79fb ldrb r3, [r7, #7] 8013f34: f003 0310 and.w r3, r3, #16 8013f38: 2b00 cmp r3, #0 8013f3a: d009 beq.n 8013f50 /* received a FIN but the caller cannot handle it right now: re-enqueue it and return "no data" */ netconn_set_flags(conn, NETCONN_FIN_RX_PENDING); 8013f3c: 68fb ldr r3, [r7, #12] 8013f3e: 7f1b ldrb r3, [r3, #28] 8013f40: f063 037f orn r3, r3, #127 ; 0x7f 8013f44: b2da uxtb r2, r3 8013f46: 68fb ldr r3, [r7, #12] 8013f48: 771a strb r2, [r3, #28] return ERR_WOULDBLOCK; 8013f4a: f06f 0306 mvn.w r3, #6 8013f4e: e027 b.n 8013fa0 } else { handle_fin: 8013f50: bf00 nop API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0); 8013f52: 68fb ldr r3, [r7, #12] 8013f54: 6a5b ldr r3, [r3, #36] ; 0x24 8013f56: 2b00 cmp r3, #0 8013f58: d005 beq.n 8013f66 8013f5a: 68fb ldr r3, [r7, #12] 8013f5c: 6a5b ldr r3, [r3, #36] ; 0x24 8013f5e: 2200 movs r2, #0 8013f60: 2101 movs r1, #1 8013f62: 68f8 ldr r0, [r7, #12] 8013f64: 4798 blx r3 if (conn->pcb.ip == NULL) { 8013f66: 68fb ldr r3, [r7, #12] 8013f68: 685b ldr r3, [r3, #4] 8013f6a: 2b00 cmp r3, #0 8013f6c: d10f bne.n 8013f8e /* race condition: RST during recv */ err = netconn_err(conn); 8013f6e: 68f8 ldr r0, [r7, #12] 8013f70: f000 f9a3 bl 80142ba 8013f74: 4603 mov r3, r0 8013f76: f887 303f strb.w r3, [r7, #63] ; 0x3f if (err != ERR_OK) { 8013f7a: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f 8013f7e: 2b00 cmp r3, #0 8013f80: d002 beq.n 8013f88 return err; 8013f82: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f 8013f86: e00b b.n 8013fa0 } return ERR_RST; 8013f88: f06f 030d mvn.w r3, #13 8013f8c: e008 b.n 8013fa0 } /* RX side is closed, so deallocate the recvmbox */ netconn_close_shutdown(conn, NETCONN_SHUT_RD); 8013f8e: 2101 movs r1, #1 8013f90: 68f8 ldr r0, [r7, #12] 8013f92: f000 f955 bl 8014240 /* Don' store ERR_CLSD as conn->err since we are only half-closed */ return ERR_CLSD; 8013f96: f06f 030e mvn.w r3, #14 8013f9a: e001 b.n 8013fa0 } } return err; 8013f9c: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f } 8013fa0: 4618 mov r0, r3 8013fa2: 3740 adds r7, #64 ; 0x40 8013fa4: 46bd mov sp, r7 8013fa6: bd80 pop {r7, pc} 08013fa8 : * @return ERR_OK if data has been received, an error code otherwise (timeout, * memory error or another error) */ err_t netconn_recv(struct netconn *conn, struct netbuf **new_buf) { 8013fa8: b580 push {r7, lr} 8013faa: b086 sub sp, #24 8013fac: af00 add r7, sp, #0 8013fae: 6078 str r0, [r7, #4] 8013fb0: 6039 str r1, [r7, #0] #if LWIP_TCP struct netbuf *buf = NULL; 8013fb2: 2300 movs r3, #0 8013fb4: 617b str r3, [r7, #20] err_t err; #endif /* LWIP_TCP */ LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;); 8013fb6: 683b ldr r3, [r7, #0] 8013fb8: 2b00 cmp r3, #0 8013fba: d109 bne.n 8013fd0 8013fbc: 4b32 ldr r3, [pc, #200] ; (8014088 ) 8013fbe: f240 3263 movw r2, #867 ; 0x363 8013fc2: 4932 ldr r1, [pc, #200] ; (801408c ) 8013fc4: 4832 ldr r0, [pc, #200] ; (8014090 ) 8013fc6: f00d fcdf bl 8021988 8013fca: f06f 030f mvn.w r3, #15 8013fce: e056 b.n 801407e *new_buf = NULL; 8013fd0: 683b ldr r3, [r7, #0] 8013fd2: 2200 movs r2, #0 8013fd4: 601a str r2, [r3, #0] LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL), return ERR_ARG;); 8013fd6: 687b ldr r3, [r7, #4] 8013fd8: 2b00 cmp r3, #0 8013fda: d109 bne.n 8013ff0 8013fdc: 4b2a ldr r3, [pc, #168] ; (8014088 ) 8013fde: f240 3265 movw r2, #869 ; 0x365 8013fe2: 492c ldr r1, [pc, #176] ; (8014094 ) 8013fe4: 482a ldr r0, [pc, #168] ; (8014090 ) 8013fe6: f00d fccf bl 8021988 8013fea: f06f 030f mvn.w r3, #15 8013fee: e046 b.n 801407e #if LWIP_TCP #if (LWIP_UDP || LWIP_RAW) if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) 8013ff0: 687b ldr r3, [r7, #4] 8013ff2: 781b ldrb r3, [r3, #0] 8013ff4: f003 03f0 and.w r3, r3, #240 ; 0xf0 8013ff8: 2b10 cmp r3, #16 8013ffa: d13a bne.n 8014072 #endif /* (LWIP_UDP || LWIP_RAW) */ { struct pbuf *p = NULL; 8013ffc: 2300 movs r3, #0 8013ffe: 60fb str r3, [r7, #12] /* This is not a listening netconn, since recvmbox is set */ buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); 8014000: 2006 movs r0, #6 8014002: f002 fd65 bl 8016ad0 8014006: 6178 str r0, [r7, #20] if (buf == NULL) { 8014008: 697b ldr r3, [r7, #20] 801400a: 2b00 cmp r3, #0 801400c: d102 bne.n 8014014 return ERR_MEM; 801400e: f04f 33ff mov.w r3, #4294967295 8014012: e034 b.n 801407e } err = netconn_recv_data_tcp(conn, &p, 0); 8014014: f107 030c add.w r3, r7, #12 8014018: 2200 movs r2, #0 801401a: 4619 mov r1, r3 801401c: 6878 ldr r0, [r7, #4] 801401e: f7ff ff3f bl 8013ea0 8014022: 4603 mov r3, r0 8014024: 74fb strb r3, [r7, #19] if (err != ERR_OK) { 8014026: f997 3013 ldrsb.w r3, [r7, #19] 801402a: 2b00 cmp r3, #0 801402c: d006 beq.n 801403c memp_free(MEMP_NETBUF, buf); 801402e: 6979 ldr r1, [r7, #20] 8014030: 2006 movs r0, #6 8014032: f002 fdc3 bl 8016bbc return err; 8014036: f997 3013 ldrsb.w r3, [r7, #19] 801403a: e020 b.n 801407e } LWIP_ASSERT("p != NULL", p != NULL); 801403c: 68fb ldr r3, [r7, #12] 801403e: 2b00 cmp r3, #0 8014040: d106 bne.n 8014050 8014042: 4b11 ldr r3, [pc, #68] ; (8014088 ) 8014044: f240 3279 movw r2, #889 ; 0x379 8014048: 4913 ldr r1, [pc, #76] ; (8014098 ) 801404a: 4811 ldr r0, [pc, #68] ; (8014090 ) 801404c: f00d fc9c bl 8021988 buf->p = p; 8014050: 68fa ldr r2, [r7, #12] 8014052: 697b ldr r3, [r7, #20] 8014054: 601a str r2, [r3, #0] buf->ptr = p; 8014056: 68fa ldr r2, [r7, #12] 8014058: 697b ldr r3, [r7, #20] 801405a: 605a str r2, [r3, #4] buf->port = 0; 801405c: 697b ldr r3, [r7, #20] 801405e: 2200 movs r2, #0 8014060: 819a strh r2, [r3, #12] ip_addr_set_zero(&buf->addr); 8014062: 697b ldr r3, [r7, #20] 8014064: 2200 movs r2, #0 8014066: 609a str r2, [r3, #8] *new_buf = buf; 8014068: 683b ldr r3, [r7, #0] 801406a: 697a ldr r2, [r7, #20] 801406c: 601a str r2, [r3, #0] /* don't set conn->last_err: it's only ERR_OK, anyway */ return ERR_OK; 801406e: 2300 movs r3, #0 8014070: e005 b.n 801407e #if LWIP_TCP && (LWIP_UDP || LWIP_RAW) else #endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */ { #if (LWIP_UDP || LWIP_RAW) return netconn_recv_data(conn, (void **)new_buf, 0); 8014072: 2200 movs r2, #0 8014074: 6839 ldr r1, [r7, #0] 8014076: 6878 ldr r0, [r7, #4] 8014078: f7ff fe1a bl 8013cb0 801407c: 4603 mov r3, r0 #endif /* (LWIP_UDP || LWIP_RAW) */ } } 801407e: 4618 mov r0, r3 8014080: 3718 adds r7, #24 8014082: 46bd mov sp, r7 8014084: bd80 pop {r7, pc} 8014086: bf00 nop 8014088: 080232cc .word 0x080232cc 801408c: 080234e4 .word 0x080234e4 8014090: 08023324 .word 0x08023324 8014094: 08023504 .word 0x08023504 8014098: 0802357c .word 0x0802357c 0801409c : * @return ERR_OK if data was sent, any other err_t on error */ err_t netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size, u8_t apiflags, size_t *bytes_written) { 801409c: b580 push {r7, lr} 801409e: b088 sub sp, #32 80140a0: af02 add r7, sp, #8 80140a2: 60f8 str r0, [r7, #12] 80140a4: 60b9 str r1, [r7, #8] 80140a6: 607a str r2, [r7, #4] 80140a8: 70fb strb r3, [r7, #3] struct netvector vector; vector.ptr = dataptr; 80140aa: 68bb ldr r3, [r7, #8] 80140ac: 613b str r3, [r7, #16] vector.len = size; 80140ae: 687b ldr r3, [r7, #4] 80140b0: 617b str r3, [r7, #20] return netconn_write_vectors_partly(conn, &vector, 1, apiflags, bytes_written); 80140b2: 78fa ldrb r2, [r7, #3] 80140b4: f107 0110 add.w r1, r7, #16 80140b8: 6a3b ldr r3, [r7, #32] 80140ba: 9300 str r3, [sp, #0] 80140bc: 4613 mov r3, r2 80140be: 2201 movs r2, #1 80140c0: 68f8 ldr r0, [r7, #12] 80140c2: f000 f805 bl 80140d0 80140c6: 4603 mov r3, r0 } 80140c8: 4618 mov r0, r3 80140ca: 3718 adds r7, #24 80140cc: 46bd mov sp, r7 80140ce: bd80 pop {r7, pc} 080140d0 : * @return ERR_OK if data was sent, any other err_t on error */ err_t netconn_write_vectors_partly(struct netconn *conn, struct netvector *vectors, u16_t vectorcnt, u8_t apiflags, size_t *bytes_written) { 80140d0: b580 push {r7, lr} 80140d2: b092 sub sp, #72 ; 0x48 80140d4: af00 add r7, sp, #0 80140d6: 60f8 str r0, [r7, #12] 80140d8: 60b9 str r1, [r7, #8] 80140da: 4611 mov r1, r2 80140dc: 461a mov r2, r3 80140de: 460b mov r3, r1 80140e0: 80fb strh r3, [r7, #6] 80140e2: 4613 mov r3, r2 80140e4: 717b strb r3, [r7, #5] err_t err; u8_t dontblock; size_t size; int i; LWIP_ERROR("netconn_write: invalid conn", (conn != NULL), return ERR_ARG;); 80140e6: 68fb ldr r3, [r7, #12] 80140e8: 2b00 cmp r3, #0 80140ea: d109 bne.n 8014100 80140ec: 4b4e ldr r3, [pc, #312] ; (8014228 ) 80140ee: f240 32ee movw r2, #1006 ; 0x3ee 80140f2: 494e ldr r1, [pc, #312] ; (801422c ) 80140f4: 484e ldr r0, [pc, #312] ; (8014230 ) 80140f6: f00d fc47 bl 8021988 80140fa: f06f 030f mvn.w r3, #15 80140fe: e08e b.n 801421e LWIP_ERROR("netconn_write: invalid conn->type", (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP), return ERR_VAL;); 8014100: 68fb ldr r3, [r7, #12] 8014102: 781b ldrb r3, [r3, #0] 8014104: f003 03f0 and.w r3, r3, #240 ; 0xf0 8014108: 2b10 cmp r3, #16 801410a: d009 beq.n 8014120 801410c: 4b46 ldr r3, [pc, #280] ; (8014228 ) 801410e: f240 32ef movw r2, #1007 ; 0x3ef 8014112: 4948 ldr r1, [pc, #288] ; (8014234 ) 8014114: 4846 ldr r0, [pc, #280] ; (8014230 ) 8014116: f00d fc37 bl 8021988 801411a: f06f 0305 mvn.w r3, #5 801411e: e07e b.n 801421e dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK); 8014120: 68fb ldr r3, [r7, #12] 8014122: 7f1b ldrb r3, [r3, #28] 8014124: f003 0302 and.w r3, r3, #2 8014128: 2b00 cmp r3, #0 801412a: d104 bne.n 8014136 801412c: 797b ldrb r3, [r7, #5] 801412e: f003 0304 and.w r3, r3, #4 8014132: 2b00 cmp r3, #0 8014134: d001 beq.n 801413a 8014136: 2301 movs r3, #1 8014138: e000 b.n 801413c 801413a: 2300 movs r3, #0 801413c: f887 303f strb.w r3, [r7, #63] ; 0x3f #if LWIP_SO_SNDTIMEO if (conn->send_timeout != 0) { dontblock = 1; } #endif /* LWIP_SO_SNDTIMEO */ if (dontblock && !bytes_written) { 8014140: f897 303f ldrb.w r3, [r7, #63] ; 0x3f 8014144: 2b00 cmp r3, #0 8014146: d005 beq.n 8014154 8014148: 6d3b ldr r3, [r7, #80] ; 0x50 801414a: 2b00 cmp r3, #0 801414c: d102 bne.n 8014154 /* This implies netconn_write() cannot be used for non-blocking send, since it has no way to return the number of bytes written. */ return ERR_VAL; 801414e: f06f 0305 mvn.w r3, #5 8014152: e064 b.n 801421e } /* sum up the total size */ size = 0; 8014154: 2300 movs r3, #0 8014156: 647b str r3, [r7, #68] ; 0x44 for (i = 0; i < vectorcnt; i++) { 8014158: 2300 movs r3, #0 801415a: 643b str r3, [r7, #64] ; 0x40 801415c: e015 b.n 801418a size += vectors[i].len; 801415e: 6c3b ldr r3, [r7, #64] ; 0x40 8014160: 00db lsls r3, r3, #3 8014162: 68ba ldr r2, [r7, #8] 8014164: 4413 add r3, r2 8014166: 685b ldr r3, [r3, #4] 8014168: 6c7a ldr r2, [r7, #68] ; 0x44 801416a: 4413 add r3, r2 801416c: 647b str r3, [r7, #68] ; 0x44 if (size < vectors[i].len) { 801416e: 6c3b ldr r3, [r7, #64] ; 0x40 8014170: 00db lsls r3, r3, #3 8014172: 68ba ldr r2, [r7, #8] 8014174: 4413 add r3, r2 8014176: 685b ldr r3, [r3, #4] 8014178: 6c7a ldr r2, [r7, #68] ; 0x44 801417a: 429a cmp r2, r3 801417c: d202 bcs.n 8014184 /* overflow */ return ERR_VAL; 801417e: f06f 0305 mvn.w r3, #5 8014182: e04c b.n 801421e for (i = 0; i < vectorcnt; i++) { 8014184: 6c3b ldr r3, [r7, #64] ; 0x40 8014186: 3301 adds r3, #1 8014188: 643b str r3, [r7, #64] ; 0x40 801418a: 88fb ldrh r3, [r7, #6] 801418c: 6c3a ldr r2, [r7, #64] ; 0x40 801418e: 429a cmp r2, r3 8014190: dbe5 blt.n 801415e } } if (size == 0) { 8014192: 6c7b ldr r3, [r7, #68] ; 0x44 8014194: 2b00 cmp r3, #0 8014196: d101 bne.n 801419c return ERR_OK; 8014198: 2300 movs r3, #0 801419a: e040 b.n 801421e } else if (size > SSIZE_MAX) { 801419c: 6c7b ldr r3, [r7, #68] ; 0x44 801419e: 2b00 cmp r3, #0 80141a0: da0a bge.n 80141b8 ssize_t limited; /* this is required by the socket layer (cannot send full size_t range) */ if (!bytes_written) { 80141a2: 6d3b ldr r3, [r7, #80] ; 0x50 80141a4: 2b00 cmp r3, #0 80141a6: d102 bne.n 80141ae return ERR_VAL; 80141a8: f06f 0305 mvn.w r3, #5 80141ac: e037 b.n 801421e } /* limit the amount of data to send */ limited = SSIZE_MAX; 80141ae: f06f 4300 mvn.w r3, #2147483648 ; 0x80000000 80141b2: 63bb str r3, [r7, #56] ; 0x38 size = (size_t)limited; 80141b4: 6bbb ldr r3, [r7, #56] ; 0x38 80141b6: 647b str r3, [r7, #68] ; 0x44 } API_MSG_VAR_ALLOC(msg); /* non-blocking write sends as much */ API_MSG_VAR_REF(msg).conn = conn; 80141b8: 68fb ldr r3, [r7, #12] 80141ba: 617b str r3, [r7, #20] API_MSG_VAR_REF(msg).msg.w.vector = vectors; 80141bc: 68bb ldr r3, [r7, #8] 80141be: 61fb str r3, [r7, #28] API_MSG_VAR_REF(msg).msg.w.vector_cnt = vectorcnt; 80141c0: 88fb ldrh r3, [r7, #6] 80141c2: 843b strh r3, [r7, #32] API_MSG_VAR_REF(msg).msg.w.vector_off = 0; 80141c4: 2300 movs r3, #0 80141c6: 627b str r3, [r7, #36] ; 0x24 API_MSG_VAR_REF(msg).msg.w.apiflags = apiflags; 80141c8: 797b ldrb r3, [r7, #5] 80141ca: f887 3030 strb.w r3, [r7, #48] ; 0x30 API_MSG_VAR_REF(msg).msg.w.len = size; 80141ce: 6c7b ldr r3, [r7, #68] ; 0x44 80141d0: 62bb str r3, [r7, #40] ; 0x28 API_MSG_VAR_REF(msg).msg.w.offset = 0; 80141d2: 2300 movs r3, #0 80141d4: 62fb str r3, [r7, #44] ; 0x2c #endif /* LWIP_SO_SNDTIMEO */ /* For locking the core: this _can_ be delayed on low memory/low send buffer, but if it is, this is done inside api_msg.c:do_write(), so we can use the non-blocking version here. */ err = netconn_apimsg(lwip_netconn_do_write, &API_MSG_VAR_REF(msg)); 80141d6: f107 0314 add.w r3, r7, #20 80141da: 4619 mov r1, r3 80141dc: 4816 ldr r0, [pc, #88] ; (8014238 ) 80141de: f7ff fc1d bl 8013a1c 80141e2: 4603 mov r3, r0 80141e4: f887 3037 strb.w r3, [r7, #55] ; 0x37 if (err == ERR_OK) { 80141e8: f997 3037 ldrsb.w r3, [r7, #55] ; 0x37 80141ec: 2b00 cmp r3, #0 80141ee: d114 bne.n 801421a if (bytes_written != NULL) { 80141f0: 6d3b ldr r3, [r7, #80] ; 0x50 80141f2: 2b00 cmp r3, #0 80141f4: d002 beq.n 80141fc *bytes_written = API_MSG_VAR_REF(msg).msg.w.offset; 80141f6: 6afa ldr r2, [r7, #44] ; 0x2c 80141f8: 6d3b ldr r3, [r7, #80] ; 0x50 80141fa: 601a str r2, [r3, #0] } /* for blocking, check all requested bytes were written, NOTE: send_timeout is treated as dontblock (see dontblock assignment above) */ if (!dontblock) { 80141fc: f897 303f ldrb.w r3, [r7, #63] ; 0x3f 8014200: 2b00 cmp r3, #0 8014202: d10a bne.n 801421a LWIP_ASSERT("do_write failed to write all bytes", API_MSG_VAR_REF(msg).msg.w.offset == size); 8014204: 6afb ldr r3, [r7, #44] ; 0x2c 8014206: 6c7a ldr r2, [r7, #68] ; 0x44 8014208: 429a cmp r2, r3 801420a: d006 beq.n 801421a 801420c: 4b06 ldr r3, [pc, #24] ; (8014228 ) 801420e: f44f 6286 mov.w r2, #1072 ; 0x430 8014212: 490a ldr r1, [pc, #40] ; (801423c ) 8014214: 4806 ldr r0, [pc, #24] ; (8014230 ) 8014216: f00d fbb7 bl 8021988 } } API_MSG_VAR_FREE(msg); return err; 801421a: f997 3037 ldrsb.w r3, [r7, #55] ; 0x37 } 801421e: 4618 mov r0, r3 8014220: 3748 adds r7, #72 ; 0x48 8014222: 46bd mov sp, r7 8014224: bd80 pop {r7, pc} 8014226: bf00 nop 8014228: 080232cc .word 0x080232cc 801422c: 080235a4 .word 0x080235a4 8014230: 08023324 .word 0x08023324 8014234: 080235c0 .word 0x080235c0 8014238: 0801586d .word 0x0801586d 801423c: 080235e4 .word 0x080235e4 08014240 : * @param how fully close or only shutdown one side? * @return ERR_OK if the netconn was closed, any other err_t on error */ static err_t netconn_close_shutdown(struct netconn *conn, u8_t how) { 8014240: b580 push {r7, lr} 8014242: b08c sub sp, #48 ; 0x30 8014244: af00 add r7, sp, #0 8014246: 6078 str r0, [r7, #4] 8014248: 460b mov r3, r1 801424a: 70fb strb r3, [r7, #3] API_MSG_VAR_DECLARE(msg); err_t err; LWIP_UNUSED_ARG(how); LWIP_ERROR("netconn_close: invalid conn", (conn != NULL), return ERR_ARG;); 801424c: 687b ldr r3, [r7, #4] 801424e: 2b00 cmp r3, #0 8014250: d109 bne.n 8014266 8014252: 4b0f ldr r3, [pc, #60] ; (8014290 ) 8014254: f240 4247 movw r2, #1095 ; 0x447 8014258: 490e ldr r1, [pc, #56] ; (8014294 ) 801425a: 480f ldr r0, [pc, #60] ; (8014298 ) 801425c: f00d fb94 bl 8021988 8014260: f06f 030f mvn.w r3, #15 8014264: e010 b.n 8014288 API_MSG_VAR_ALLOC(msg); API_MSG_VAR_REF(msg).conn = conn; 8014266: 687b ldr r3, [r7, #4] 8014268: 60fb str r3, [r7, #12] #if LWIP_TCP /* shutting down both ends is the same as closing */ API_MSG_VAR_REF(msg).msg.sd.shut = how; 801426a: 78fb ldrb r3, [r7, #3] 801426c: 753b strb r3, [r7, #20] #if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER /* get the time we started, which is later compared to sys_now() + conn->send_timeout */ API_MSG_VAR_REF(msg).msg.sd.time_started = sys_now(); #else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ API_MSG_VAR_REF(msg).msg.sd.polls_left = 801426e: 2329 movs r3, #41 ; 0x29 8014270: 757b strb r3, [r7, #21] ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1; #endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ #endif /* LWIP_TCP */ err = netconn_apimsg(lwip_netconn_do_close, &API_MSG_VAR_REF(msg)); 8014272: f107 030c add.w r3, r7, #12 8014276: 4619 mov r1, r3 8014278: 4808 ldr r0, [pc, #32] ; (801429c ) 801427a: f7ff fbcf bl 8013a1c 801427e: 4603 mov r3, r0 8014280: f887 302f strb.w r3, [r7, #47] ; 0x2f API_MSG_VAR_FREE(msg); return err; 8014284: f997 302f ldrsb.w r3, [r7, #47] ; 0x2f } 8014288: 4618 mov r0, r3 801428a: 3730 adds r7, #48 ; 0x30 801428c: 46bd mov sp, r7 801428e: bd80 pop {r7, pc} 8014290: 080232cc .word 0x080232cc 8014294: 08023608 .word 0x08023608 8014298: 08023324 .word 0x08023324 801429c: 08015985 .word 0x08015985 080142a0 : * @param conn the TCP netconn to close * @return ERR_OK if the netconn was closed, any other err_t on error */ err_t netconn_close(struct netconn *conn) { 80142a0: b580 push {r7, lr} 80142a2: b082 sub sp, #8 80142a4: af00 add r7, sp, #0 80142a6: 6078 str r0, [r7, #4] /* shutting down both ends is the same as closing */ return netconn_close_shutdown(conn, NETCONN_SHUT_RDWR); 80142a8: 2103 movs r1, #3 80142aa: 6878 ldr r0, [r7, #4] 80142ac: f7ff ffc8 bl 8014240 80142b0: 4603 mov r3, r0 } 80142b2: 4618 mov r0, r3 80142b4: 3708 adds r7, #8 80142b6: 46bd mov sp, r7 80142b8: bd80 pop {r7, pc} 080142ba : * @param conn the netconn to get the error from * @return and pending error or ERR_OK if no error was pending */ err_t netconn_err(struct netconn *conn) { 80142ba: b580 push {r7, lr} 80142bc: b084 sub sp, #16 80142be: af00 add r7, sp, #0 80142c0: 6078 str r0, [r7, #4] err_t err; SYS_ARCH_DECL_PROTECT(lev); if (conn == NULL) { 80142c2: 687b ldr r3, [r7, #4] 80142c4: 2b00 cmp r3, #0 80142c6: d101 bne.n 80142cc return ERR_OK; 80142c8: 2300 movs r3, #0 80142ca: e00d b.n 80142e8 } SYS_ARCH_PROTECT(lev); 80142cc: f00d f9c2 bl 8021654 80142d0: 60f8 str r0, [r7, #12] err = conn->pending_err; 80142d2: 687b ldr r3, [r7, #4] 80142d4: 7a1b ldrb r3, [r3, #8] 80142d6: 72fb strb r3, [r7, #11] conn->pending_err = ERR_OK; 80142d8: 687b ldr r3, [r7, #4] 80142da: 2200 movs r2, #0 80142dc: 721a strb r2, [r3, #8] SYS_ARCH_UNPROTECT(lev); 80142de: 68f8 ldr r0, [r7, #12] 80142e0: f00d f9c6 bl 8021670 return err; 80142e4: f997 300b ldrsb.w r3, [r7, #11] } 80142e8: 4618 mov r0, r3 80142ea: 3710 adds r7, #16 80142ec: 46bd mov sp, r7 80142ee: bd80 pop {r7, pc} 080142f0 : const u8_t netconn_closed = 0; /** Translate an error to a unique void* passed via an mbox */ static void * lwip_netconn_err_to_msg(err_t err) { 80142f0: b580 push {r7, lr} 80142f2: b082 sub sp, #8 80142f4: af00 add r7, sp, #0 80142f6: 4603 mov r3, r0 80142f8: 71fb strb r3, [r7, #7] switch (err) { 80142fa: f997 3007 ldrsb.w r3, [r7, #7] 80142fe: f113 0f0d cmn.w r3, #13 8014302: d009 beq.n 8014318 8014304: f113 0f0d cmn.w r3, #13 8014308: dc0c bgt.n 8014324 801430a: f113 0f0f cmn.w r3, #15 801430e: d007 beq.n 8014320 8014310: f113 0f0e cmn.w r3, #14 8014314: d002 beq.n 801431c 8014316: e005 b.n 8014324 case ERR_ABRT: return LWIP_CONST_CAST(void *, &netconn_aborted); 8014318: 4b0a ldr r3, [pc, #40] ; (8014344 ) 801431a: e00e b.n 801433a case ERR_RST: return LWIP_CONST_CAST(void *, &netconn_reset); 801431c: 4b0a ldr r3, [pc, #40] ; (8014348 ) 801431e: e00c b.n 801433a case ERR_CLSD: return LWIP_CONST_CAST(void *, &netconn_closed); 8014320: 4b0a ldr r3, [pc, #40] ; (801434c ) 8014322: e00a b.n 801433a default: LWIP_ASSERT("unhandled error", err == ERR_OK); 8014324: f997 3007 ldrsb.w r3, [r7, #7] 8014328: 2b00 cmp r3, #0 801432a: d005 beq.n 8014338 801432c: 4b08 ldr r3, [pc, #32] ; (8014350 ) 801432e: 227d movs r2, #125 ; 0x7d 8014330: 4908 ldr r1, [pc, #32] ; (8014354 ) 8014332: 4809 ldr r0, [pc, #36] ; (8014358 ) 8014334: f00d fb28 bl 8021988 return NULL; 8014338: 2300 movs r3, #0 } } 801433a: 4618 mov r0, r3 801433c: 3708 adds r7, #8 801433e: 46bd mov sp, r7 8014340: bd80 pop {r7, pc} 8014342: bf00 nop 8014344: 08026ba4 .word 0x08026ba4 8014348: 08026ba5 .word 0x08026ba5 801434c: 08026ba6 .word 0x08026ba6 8014350: 08023624 .word 0x08023624 8014354: 08023658 .word 0x08023658 8014358: 08023668 .word 0x08023668 0801435c : int lwip_netconn_is_err_msg(void *msg, err_t *err) { 801435c: b580 push {r7, lr} 801435e: b082 sub sp, #8 8014360: af00 add r7, sp, #0 8014362: 6078 str r0, [r7, #4] 8014364: 6039 str r1, [r7, #0] LWIP_ASSERT("err != NULL", err != NULL); 8014366: 683b ldr r3, [r7, #0] 8014368: 2b00 cmp r3, #0 801436a: d105 bne.n 8014378 801436c: 4b12 ldr r3, [pc, #72] ; (80143b8 ) 801436e: 2285 movs r2, #133 ; 0x85 8014370: 4912 ldr r1, [pc, #72] ; (80143bc ) 8014372: 4813 ldr r0, [pc, #76] ; (80143c0 ) 8014374: f00d fb08 bl 8021988 if (msg == &netconn_aborted) { 8014378: 687b ldr r3, [r7, #4] 801437a: 4a12 ldr r2, [pc, #72] ; (80143c4 ) 801437c: 4293 cmp r3, r2 801437e: d104 bne.n 801438a *err = ERR_ABRT; 8014380: 683b ldr r3, [r7, #0] 8014382: 22f3 movs r2, #243 ; 0xf3 8014384: 701a strb r2, [r3, #0] return 1; 8014386: 2301 movs r3, #1 8014388: e012 b.n 80143b0 } else if (msg == &netconn_reset) { 801438a: 687b ldr r3, [r7, #4] 801438c: 4a0e ldr r2, [pc, #56] ; (80143c8 ) 801438e: 4293 cmp r3, r2 8014390: d104 bne.n 801439c *err = ERR_RST; 8014392: 683b ldr r3, [r7, #0] 8014394: 22f2 movs r2, #242 ; 0xf2 8014396: 701a strb r2, [r3, #0] return 1; 8014398: 2301 movs r3, #1 801439a: e009 b.n 80143b0 } else if (msg == &netconn_closed) { 801439c: 687b ldr r3, [r7, #4] 801439e: 4a0b ldr r2, [pc, #44] ; (80143cc ) 80143a0: 4293 cmp r3, r2 80143a2: d104 bne.n 80143ae *err = ERR_CLSD; 80143a4: 683b ldr r3, [r7, #0] 80143a6: 22f1 movs r2, #241 ; 0xf1 80143a8: 701a strb r2, [r3, #0] return 1; 80143aa: 2301 movs r3, #1 80143ac: e000 b.n 80143b0 } return 0; 80143ae: 2300 movs r3, #0 } 80143b0: 4618 mov r0, r3 80143b2: 3708 adds r7, #8 80143b4: 46bd mov sp, r7 80143b6: bd80 pop {r7, pc} 80143b8: 08023624 .word 0x08023624 80143bc: 08023690 .word 0x08023690 80143c0: 08023668 .word 0x08023668 80143c4: 08026ba4 .word 0x08026ba4 80143c8: 08026ba5 .word 0x08026ba5 80143cc: 08026ba6 .word 0x08026ba6 080143d0 : * @see udp.h (struct udp_pcb.recv) for parameters */ static void recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) { 80143d0: b580 push {r7, lr} 80143d2: b088 sub sp, #32 80143d4: af00 add r7, sp, #0 80143d6: 60f8 str r0, [r7, #12] 80143d8: 60b9 str r1, [r7, #8] 80143da: 607a str r2, [r7, #4] 80143dc: 603b str r3, [r7, #0] #if LWIP_SO_RCVBUF int recv_avail; #endif /* LWIP_SO_RCVBUF */ LWIP_UNUSED_ARG(pcb); /* only used for asserts... */ LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL); 80143de: 68bb ldr r3, [r7, #8] 80143e0: 2b00 cmp r3, #0 80143e2: d105 bne.n 80143f0 80143e4: 4b34 ldr r3, [pc, #208] ; (80144b8 ) 80143e6: 22e5 movs r2, #229 ; 0xe5 80143e8: 4934 ldr r1, [pc, #208] ; (80144bc ) 80143ea: 4835 ldr r0, [pc, #212] ; (80144c0 ) 80143ec: f00d facc bl 8021988 LWIP_ASSERT("recv_udp must have an argument", arg != NULL); 80143f0: 68fb ldr r3, [r7, #12] 80143f2: 2b00 cmp r3, #0 80143f4: d105 bne.n 8014402 80143f6: 4b30 ldr r3, [pc, #192] ; (80144b8 ) 80143f8: 22e6 movs r2, #230 ; 0xe6 80143fa: 4932 ldr r1, [pc, #200] ; (80144c4 ) 80143fc: 4830 ldr r0, [pc, #192] ; (80144c0 ) 80143fe: f00d fac3 bl 8021988 conn = (struct netconn *)arg; 8014402: 68fb ldr r3, [r7, #12] 8014404: 61fb str r3, [r7, #28] if (conn == NULL) { 8014406: 69fb ldr r3, [r7, #28] 8014408: 2b00 cmp r3, #0 801440a: d103 bne.n 8014414 pbuf_free(p); 801440c: 6878 ldr r0, [r7, #4] 801440e: f003 fb73 bl 8017af8 return; 8014412: e04d b.n 80144b0 } LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb); 8014414: 69fb ldr r3, [r7, #28] 8014416: 685b ldr r3, [r3, #4] 8014418: 68ba ldr r2, [r7, #8] 801441a: 429a cmp r2, r3 801441c: d005 beq.n 801442a 801441e: 4b26 ldr r3, [pc, #152] ; (80144b8 ) 8014420: 22ee movs r2, #238 ; 0xee 8014422: 4929 ldr r1, [pc, #164] ; (80144c8 ) 8014424: 4826 ldr r0, [pc, #152] ; (80144c0 ) 8014426: f00d faaf bl 8021988 #if LWIP_SO_RCVBUF SYS_ARCH_GET(conn->recv_avail, recv_avail); if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox) || ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) { #else /* LWIP_SO_RCVBUF */ if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox)) { 801442a: 69fb ldr r3, [r7, #28] 801442c: 3310 adds r3, #16 801442e: 4618 mov r0, r3 8014430: f00c fff5 bl 802141e 8014434: 4603 mov r3, r0 8014436: 2b00 cmp r3, #0 8014438: d103 bne.n 8014442 #endif /* LWIP_SO_RCVBUF */ pbuf_free(p); 801443a: 6878 ldr r0, [r7, #4] 801443c: f003 fb5c bl 8017af8 return; 8014440: e036 b.n 80144b0 } buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); 8014442: 2006 movs r0, #6 8014444: f002 fb44 bl 8016ad0 8014448: 61b8 str r0, [r7, #24] if (buf == NULL) { 801444a: 69bb ldr r3, [r7, #24] 801444c: 2b00 cmp r3, #0 801444e: d103 bne.n 8014458 pbuf_free(p); 8014450: 6878 ldr r0, [r7, #4] 8014452: f003 fb51 bl 8017af8 return; 8014456: e02b b.n 80144b0 } else { buf->p = p; 8014458: 69bb ldr r3, [r7, #24] 801445a: 687a ldr r2, [r7, #4] 801445c: 601a str r2, [r3, #0] buf->ptr = p; 801445e: 69bb ldr r3, [r7, #24] 8014460: 687a ldr r2, [r7, #4] 8014462: 605a str r2, [r3, #4] ip_addr_set(&buf->addr, addr); 8014464: 683b ldr r3, [r7, #0] 8014466: 2b00 cmp r3, #0 8014468: d002 beq.n 8014470 801446a: 683b ldr r3, [r7, #0] 801446c: 681b ldr r3, [r3, #0] 801446e: e000 b.n 8014472 8014470: 2300 movs r3, #0 8014472: 69ba ldr r2, [r7, #24] 8014474: 6093 str r3, [r2, #8] buf->port = port; 8014476: 69bb ldr r3, [r7, #24] 8014478: 8d3a ldrh r2, [r7, #40] ; 0x28 801447a: 819a strh r2, [r3, #12] buf->toport_chksum = udphdr->dest; } #endif /* LWIP_NETBUF_RECVINFO */ } len = p->tot_len; 801447c: 687b ldr r3, [r7, #4] 801447e: 891b ldrh r3, [r3, #8] 8014480: 82fb strh r3, [r7, #22] if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { 8014482: 69fb ldr r3, [r7, #28] 8014484: 3310 adds r3, #16 8014486: 69b9 ldr r1, [r7, #24] 8014488: 4618 mov r0, r3 801448a: f00c ff53 bl 8021334 801448e: 4603 mov r3, r0 8014490: 2b00 cmp r3, #0 8014492: d003 beq.n 801449c netbuf_delete(buf); 8014494: 69b8 ldr r0, [r7, #24] 8014496: f001 fb01 bl 8015a9c return; 801449a: e009 b.n 80144b0 } else { #if LWIP_SO_RCVBUF SYS_ARCH_INC(conn->recv_avail, len); #endif /* LWIP_SO_RCVBUF */ /* Register event with callback */ API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); 801449c: 69fb ldr r3, [r7, #28] 801449e: 6a5b ldr r3, [r3, #36] ; 0x24 80144a0: 2b00 cmp r3, #0 80144a2: d005 beq.n 80144b0 80144a4: 69fb ldr r3, [r7, #28] 80144a6: 6a5b ldr r3, [r3, #36] ; 0x24 80144a8: 8afa ldrh r2, [r7, #22] 80144aa: 2100 movs r1, #0 80144ac: 69f8 ldr r0, [r7, #28] 80144ae: 4798 blx r3 } } 80144b0: 3720 adds r7, #32 80144b2: 46bd mov sp, r7 80144b4: bd80 pop {r7, pc} 80144b6: bf00 nop 80144b8: 08023624 .word 0x08023624 80144bc: 0802369c .word 0x0802369c 80144c0: 08023668 .word 0x08023668 80144c4: 080236c0 .word 0x080236c0 80144c8: 080236e0 .word 0x080236e0 080144cc : * * @see tcp.h (struct tcp_pcb.recv) for parameters and return value */ static err_t recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) { 80144cc: b580 push {r7, lr} 80144ce: b088 sub sp, #32 80144d0: af00 add r7, sp, #0 80144d2: 60f8 str r0, [r7, #12] 80144d4: 60b9 str r1, [r7, #8] 80144d6: 607a str r2, [r7, #4] 80144d8: 70fb strb r3, [r7, #3] struct netconn *conn; u16_t len; void *msg; LWIP_UNUSED_ARG(pcb); LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL); 80144da: 68bb ldr r3, [r7, #8] 80144dc: 2b00 cmp r3, #0 80144de: d106 bne.n 80144ee 80144e0: 4b36 ldr r3, [pc, #216] ; (80145bc ) 80144e2: f44f 7296 mov.w r2, #300 ; 0x12c 80144e6: 4936 ldr r1, [pc, #216] ; (80145c0 ) 80144e8: 4836 ldr r0, [pc, #216] ; (80145c4 ) 80144ea: f00d fa4d bl 8021988 LWIP_ASSERT("recv_tcp must have an argument", arg != NULL); 80144ee: 68fb ldr r3, [r7, #12] 80144f0: 2b00 cmp r3, #0 80144f2: d106 bne.n 8014502 80144f4: 4b31 ldr r3, [pc, #196] ; (80145bc ) 80144f6: f240 122d movw r2, #301 ; 0x12d 80144fa: 4933 ldr r1, [pc, #204] ; (80145c8 ) 80144fc: 4831 ldr r0, [pc, #196] ; (80145c4 ) 80144fe: f00d fa43 bl 8021988 LWIP_ASSERT("err != ERR_OK unhandled", err == ERR_OK); 8014502: f997 3003 ldrsb.w r3, [r7, #3] 8014506: 2b00 cmp r3, #0 8014508: d006 beq.n 8014518 801450a: 4b2c ldr r3, [pc, #176] ; (80145bc ) 801450c: f44f 7297 mov.w r2, #302 ; 0x12e 8014510: 492e ldr r1, [pc, #184] ; (80145cc ) 8014512: 482c ldr r0, [pc, #176] ; (80145c4 ) 8014514: f00d fa38 bl 8021988 LWIP_UNUSED_ARG(err); /* for LWIP_NOASSERT */ conn = (struct netconn *)arg; 8014518: 68fb ldr r3, [r7, #12] 801451a: 617b str r3, [r7, #20] if (conn == NULL) { 801451c: 697b ldr r3, [r7, #20] 801451e: 2b00 cmp r3, #0 8014520: d102 bne.n 8014528 return ERR_VAL; 8014522: f06f 0305 mvn.w r3, #5 8014526: e045 b.n 80145b4 } LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb); 8014528: 697b ldr r3, [r7, #20] 801452a: 685b ldr r3, [r3, #4] 801452c: 68ba ldr r2, [r7, #8] 801452e: 429a cmp r2, r3 8014530: d006 beq.n 8014540 8014532: 4b22 ldr r3, [pc, #136] ; (80145bc ) 8014534: f240 1235 movw r2, #309 ; 0x135 8014538: 4925 ldr r1, [pc, #148] ; (80145d0 ) 801453a: 4822 ldr r0, [pc, #136] ; (80145c4 ) 801453c: f00d fa24 bl 8021988 if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox)) { 8014540: 697b ldr r3, [r7, #20] 8014542: 3310 adds r3, #16 8014544: 4618 mov r0, r3 8014546: f00c ff6a bl 802141e 801454a: 4603 mov r3, r0 801454c: 2b00 cmp r3, #0 801454e: d10d bne.n 801456c /* recvmbox already deleted */ if (p != NULL) { 8014550: 687b ldr r3, [r7, #4] 8014552: 2b00 cmp r3, #0 8014554: d008 beq.n 8014568 tcp_recved(pcb, p->tot_len); 8014556: 687b ldr r3, [r7, #4] 8014558: 891b ldrh r3, [r3, #8] 801455a: 4619 mov r1, r3 801455c: 68b8 ldr r0, [r7, #8] 801455e: f004 f9b9 bl 80188d4 pbuf_free(p); 8014562: 6878 ldr r0, [r7, #4] 8014564: f003 fac8 bl 8017af8 } return ERR_OK; 8014568: 2300 movs r3, #0 801456a: e023 b.n 80145b4 } /* Unlike for UDP or RAW pcbs, don't check for available space using recv_avail since that could break the connection (data is already ACKed) */ if (p != NULL) { 801456c: 687b ldr r3, [r7, #4] 801456e: 2b00 cmp r3, #0 8014570: d005 beq.n 801457e msg = p; 8014572: 687b ldr r3, [r7, #4] 8014574: 61bb str r3, [r7, #24] len = p->tot_len; 8014576: 687b ldr r3, [r7, #4] 8014578: 891b ldrh r3, [r3, #8] 801457a: 83fb strh r3, [r7, #30] 801457c: e003 b.n 8014586 } else { msg = LWIP_CONST_CAST(void *, &netconn_closed); 801457e: 4b15 ldr r3, [pc, #84] ; (80145d4 ) 8014580: 61bb str r3, [r7, #24] len = 0; 8014582: 2300 movs r3, #0 8014584: 83fb strh r3, [r7, #30] } if (sys_mbox_trypost(&conn->recvmbox, msg) != ERR_OK) { 8014586: 697b ldr r3, [r7, #20] 8014588: 3310 adds r3, #16 801458a: 69b9 ldr r1, [r7, #24] 801458c: 4618 mov r0, r3 801458e: f00c fed1 bl 8021334 8014592: 4603 mov r3, r0 8014594: 2b00 cmp r3, #0 8014596: d002 beq.n 801459e /* don't deallocate p: it is presented to us later again from tcp_fasttmr! */ return ERR_MEM; 8014598: f04f 33ff mov.w r3, #4294967295 801459c: e00a b.n 80145b4 } else { #if LWIP_SO_RCVBUF SYS_ARCH_INC(conn->recv_avail, len); #endif /* LWIP_SO_RCVBUF */ /* Register event with callback */ API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); 801459e: 697b ldr r3, [r7, #20] 80145a0: 6a5b ldr r3, [r3, #36] ; 0x24 80145a2: 2b00 cmp r3, #0 80145a4: d005 beq.n 80145b2 80145a6: 697b ldr r3, [r7, #20] 80145a8: 6a5b ldr r3, [r3, #36] ; 0x24 80145aa: 8bfa ldrh r2, [r7, #30] 80145ac: 2100 movs r1, #0 80145ae: 6978 ldr r0, [r7, #20] 80145b0: 4798 blx r3 } return ERR_OK; 80145b2: 2300 movs r3, #0 } 80145b4: 4618 mov r0, r3 80145b6: 3720 adds r7, #32 80145b8: 46bd mov sp, r7 80145ba: bd80 pop {r7, pc} 80145bc: 08023624 .word 0x08023624 80145c0: 08023700 .word 0x08023700 80145c4: 08023668 .word 0x08023668 80145c8: 08023724 .word 0x08023724 80145cc: 08023744 .word 0x08023744 80145d0: 0802375c .word 0x0802375c 80145d4: 08026ba6 .word 0x08026ba6 080145d8 : * * @see tcp.h (struct tcp_pcb.poll) for parameters and return value */ static err_t poll_tcp(void *arg, struct tcp_pcb *pcb) { 80145d8: b580 push {r7, lr} 80145da: b084 sub sp, #16 80145dc: af00 add r7, sp, #0 80145de: 6078 str r0, [r7, #4] 80145e0: 6039 str r1, [r7, #0] struct netconn *conn = (struct netconn *)arg; 80145e2: 687b ldr r3, [r7, #4] 80145e4: 60fb str r3, [r7, #12] LWIP_UNUSED_ARG(pcb); LWIP_ASSERT("conn != NULL", (conn != NULL)); 80145e6: 68fb ldr r3, [r7, #12] 80145e8: 2b00 cmp r3, #0 80145ea: d106 bne.n 80145fa 80145ec: 4b2a ldr r3, [pc, #168] ; (8014698 ) 80145ee: f44f 72b5 mov.w r2, #362 ; 0x16a 80145f2: 492a ldr r1, [pc, #168] ; (801469c ) 80145f4: 482a ldr r0, [pc, #168] ; (80146a0 ) 80145f6: f00d f9c7 bl 8021988 if (conn->state == NETCONN_WRITE) { 80145fa: 68fb ldr r3, [r7, #12] 80145fc: 785b ldrb r3, [r3, #1] 80145fe: 2b01 cmp r3, #1 8014600: d104 bne.n 801460c lwip_netconn_do_writemore(conn WRITE_DELAYED); 8014602: 2101 movs r1, #1 8014604: 68f8 ldr r0, [r7, #12] 8014606: f000 ff63 bl 80154d0 801460a: e016 b.n 801463a } else if (conn->state == NETCONN_CLOSE) { 801460c: 68fb ldr r3, [r7, #12] 801460e: 785b ldrb r3, [r3, #1] 8014610: 2b04 cmp r3, #4 8014612: d112 bne.n 801463a #if !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER if (conn->current_msg && conn->current_msg->msg.sd.polls_left) { 8014614: 68fb ldr r3, [r7, #12] 8014616: 6a1b ldr r3, [r3, #32] 8014618: 2b00 cmp r3, #0 801461a: d00a beq.n 8014632 801461c: 68fb ldr r3, [r7, #12] 801461e: 6a1b ldr r3, [r3, #32] 8014620: 7a5b ldrb r3, [r3, #9] 8014622: 2b00 cmp r3, #0 8014624: d005 beq.n 8014632 conn->current_msg->msg.sd.polls_left--; 8014626: 68fb ldr r3, [r7, #12] 8014628: 6a1b ldr r3, [r3, #32] 801462a: 7a5a ldrb r2, [r3, #9] 801462c: 3a01 subs r2, #1 801462e: b2d2 uxtb r2, r2 8014630: 725a strb r2, [r3, #9] } #endif /* !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER */ lwip_netconn_do_close_internal(conn WRITE_DELAYED); 8014632: 2101 movs r1, #1 8014634: 68f8 ldr r0, [r7, #12] 8014636: f000 fb3f bl 8014cb8 } /* @todo: implement connect timeout here? */ /* Did a nonblocking write fail before? Then check available write-space. */ if (conn->flags & NETCONN_FLAG_CHECK_WRITESPACE) { 801463a: 68fb ldr r3, [r7, #12] 801463c: 7f1b ldrb r3, [r3, #28] 801463e: f003 0310 and.w r3, r3, #16 8014642: 2b00 cmp r3, #0 8014644: d022 beq.n 801468c /* If the queued byte- or pbuf-count drops below the configured low-water limit, let select mark this pcb as writable again. */ if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && 8014646: 68fb ldr r3, [r7, #12] 8014648: 685b ldr r3, [r3, #4] 801464a: 2b00 cmp r3, #0 801464c: d01e beq.n 801468c 801464e: 68fb ldr r3, [r7, #12] 8014650: 685b ldr r3, [r3, #4] 8014652: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64 8014656: f640 3269 movw r2, #2921 ; 0xb69 801465a: 4293 cmp r3, r2 801465c: d916 bls.n 801468c (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { 801465e: 68fb ldr r3, [r7, #12] 8014660: 685b ldr r3, [r3, #4] 8014662: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && 8014666: 2b07 cmp r3, #7 8014668: d810 bhi.n 801468c netconn_clear_flags(conn, NETCONN_FLAG_CHECK_WRITESPACE); 801466a: 68fb ldr r3, [r7, #12] 801466c: 7f1b ldrb r3, [r3, #28] 801466e: f023 0310 bic.w r3, r3, #16 8014672: b2da uxtb r2, r3 8014674: 68fb ldr r3, [r7, #12] 8014676: 771a strb r2, [r3, #28] API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); 8014678: 68fb ldr r3, [r7, #12] 801467a: 6a5b ldr r3, [r3, #36] ; 0x24 801467c: 2b00 cmp r3, #0 801467e: d005 beq.n 801468c 8014680: 68fb ldr r3, [r7, #12] 8014682: 6a5b ldr r3, [r3, #36] ; 0x24 8014684: 2200 movs r2, #0 8014686: 2102 movs r1, #2 8014688: 68f8 ldr r0, [r7, #12] 801468a: 4798 blx r3 } } return ERR_OK; 801468c: 2300 movs r3, #0 } 801468e: 4618 mov r0, r3 8014690: 3710 adds r7, #16 8014692: 46bd mov sp, r7 8014694: bd80 pop {r7, pc} 8014696: bf00 nop 8014698: 08023624 .word 0x08023624 801469c: 0802377c .word 0x0802377c 80146a0: 08023668 .word 0x08023668 080146a4 : * * @see tcp.h (struct tcp_pcb.sent) for parameters and return value */ static err_t sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) { 80146a4: b580 push {r7, lr} 80146a6: b086 sub sp, #24 80146a8: af00 add r7, sp, #0 80146aa: 60f8 str r0, [r7, #12] 80146ac: 60b9 str r1, [r7, #8] 80146ae: 4613 mov r3, r2 80146b0: 80fb strh r3, [r7, #6] struct netconn *conn = (struct netconn *)arg; 80146b2: 68fb ldr r3, [r7, #12] 80146b4: 617b str r3, [r7, #20] LWIP_UNUSED_ARG(pcb); LWIP_ASSERT("conn != NULL", (conn != NULL)); 80146b6: 697b ldr r3, [r7, #20] 80146b8: 2b00 cmp r3, #0 80146ba: d106 bne.n 80146ca 80146bc: 4b21 ldr r3, [pc, #132] ; (8014744 ) 80146be: f240 1293 movw r2, #403 ; 0x193 80146c2: 4921 ldr r1, [pc, #132] ; (8014748 ) 80146c4: 4821 ldr r0, [pc, #132] ; (801474c ) 80146c6: f00d f95f bl 8021988 if (conn) { 80146ca: 697b ldr r3, [r7, #20] 80146cc: 2b00 cmp r3, #0 80146ce: d033 beq.n 8014738 if (conn->state == NETCONN_WRITE) { 80146d0: 697b ldr r3, [r7, #20] 80146d2: 785b ldrb r3, [r3, #1] 80146d4: 2b01 cmp r3, #1 80146d6: d104 bne.n 80146e2 lwip_netconn_do_writemore(conn WRITE_DELAYED); 80146d8: 2101 movs r1, #1 80146da: 6978 ldr r0, [r7, #20] 80146dc: f000 fef8 bl 80154d0 80146e0: e007 b.n 80146f2 } else if (conn->state == NETCONN_CLOSE) { 80146e2: 697b ldr r3, [r7, #20] 80146e4: 785b ldrb r3, [r3, #1] 80146e6: 2b04 cmp r3, #4 80146e8: d103 bne.n 80146f2 lwip_netconn_do_close_internal(conn WRITE_DELAYED); 80146ea: 2101 movs r1, #1 80146ec: 6978 ldr r0, [r7, #20] 80146ee: f000 fae3 bl 8014cb8 } /* If the queued byte- or pbuf-count drops below the configured low-water limit, let select mark this pcb as writable again. */ if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && 80146f2: 697b ldr r3, [r7, #20] 80146f4: 685b ldr r3, [r3, #4] 80146f6: 2b00 cmp r3, #0 80146f8: d01e beq.n 8014738 80146fa: 697b ldr r3, [r7, #20] 80146fc: 685b ldr r3, [r3, #4] 80146fe: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64 8014702: f640 3269 movw r2, #2921 ; 0xb69 8014706: 4293 cmp r3, r2 8014708: d916 bls.n 8014738 (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { 801470a: 697b ldr r3, [r7, #20] 801470c: 685b ldr r3, [r3, #4] 801470e: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && 8014712: 2b07 cmp r3, #7 8014714: d810 bhi.n 8014738 netconn_clear_flags(conn, NETCONN_FLAG_CHECK_WRITESPACE); 8014716: 697b ldr r3, [r7, #20] 8014718: 7f1b ldrb r3, [r3, #28] 801471a: f023 0310 bic.w r3, r3, #16 801471e: b2da uxtb r2, r3 8014720: 697b ldr r3, [r7, #20] 8014722: 771a strb r2, [r3, #28] API_EVENT(conn, NETCONN_EVT_SENDPLUS, len); 8014724: 697b ldr r3, [r7, #20] 8014726: 6a5b ldr r3, [r3, #36] ; 0x24 8014728: 2b00 cmp r3, #0 801472a: d005 beq.n 8014738 801472c: 697b ldr r3, [r7, #20] 801472e: 6a5b ldr r3, [r3, #36] ; 0x24 8014730: 88fa ldrh r2, [r7, #6] 8014732: 2102 movs r1, #2 8014734: 6978 ldr r0, [r7, #20] 8014736: 4798 blx r3 } } return ERR_OK; 8014738: 2300 movs r3, #0 } 801473a: 4618 mov r0, r3 801473c: 3718 adds r7, #24 801473e: 46bd mov sp, r7 8014740: bd80 pop {r7, pc} 8014742: bf00 nop 8014744: 08023624 .word 0x08023624 8014748: 0802377c .word 0x0802377c 801474c: 08023668 .word 0x08023668 08014750 : * * @see tcp.h (struct tcp_pcb.err) for parameters */ static void err_tcp(void *arg, err_t err) { 8014750: b580 push {r7, lr} 8014752: b088 sub sp, #32 8014754: af00 add r7, sp, #0 8014756: 6078 str r0, [r7, #4] 8014758: 460b mov r3, r1 801475a: 70fb strb r3, [r7, #3] struct netconn *conn; enum netconn_state old_state; void *mbox_msg; SYS_ARCH_DECL_PROTECT(lev); conn = (struct netconn *)arg; 801475c: 687b ldr r3, [r7, #4] 801475e: 61fb str r3, [r7, #28] LWIP_ASSERT("conn != NULL", (conn != NULL)); 8014760: 69fb ldr r3, [r7, #28] 8014762: 2b00 cmp r3, #0 8014764: d106 bne.n 8014774 8014766: 4b5f ldr r3, [pc, #380] ; (80148e4 ) 8014768: f44f 72dc mov.w r2, #440 ; 0x1b8 801476c: 495e ldr r1, [pc, #376] ; (80148e8 ) 801476e: 485f ldr r0, [pc, #380] ; (80148ec ) 8014770: f00d f90a bl 8021988 SYS_ARCH_PROTECT(lev); 8014774: f00c ff6e bl 8021654 8014778: 61b8 str r0, [r7, #24] /* when err is called, the pcb is deallocated, so delete the reference */ conn->pcb.tcp = NULL; 801477a: 69fb ldr r3, [r7, #28] 801477c: 2200 movs r2, #0 801477e: 605a str r2, [r3, #4] /* store pending error */ conn->pending_err = err; 8014780: 69fb ldr r3, [r7, #28] 8014782: 78fa ldrb r2, [r7, #3] 8014784: 721a strb r2, [r3, #8] /* prevent application threads from blocking on 'recvmbox'/'acceptmbox' */ conn->flags |= NETCONN_FLAG_MBOXCLOSED; 8014786: 69fb ldr r3, [r7, #28] 8014788: 7f1b ldrb r3, [r3, #28] 801478a: f043 0301 orr.w r3, r3, #1 801478e: b2da uxtb r2, r3 8014790: 69fb ldr r3, [r7, #28] 8014792: 771a strb r2, [r3, #28] /* reset conn->state now before waking up other threads */ old_state = conn->state; 8014794: 69fb ldr r3, [r7, #28] 8014796: 785b ldrb r3, [r3, #1] 8014798: 75fb strb r3, [r7, #23] conn->state = NETCONN_NONE; 801479a: 69fb ldr r3, [r7, #28] 801479c: 2200 movs r2, #0 801479e: 705a strb r2, [r3, #1] SYS_ARCH_UNPROTECT(lev); 80147a0: 69b8 ldr r0, [r7, #24] 80147a2: f00c ff65 bl 8021670 /* Notify the user layer about a connection error. Used to signal select. */ API_EVENT(conn, NETCONN_EVT_ERROR, 0); 80147a6: 69fb ldr r3, [r7, #28] 80147a8: 6a5b ldr r3, [r3, #36] ; 0x24 80147aa: 2b00 cmp r3, #0 80147ac: d005 beq.n 80147ba 80147ae: 69fb ldr r3, [r7, #28] 80147b0: 6a5b ldr r3, [r3, #36] ; 0x24 80147b2: 2200 movs r2, #0 80147b4: 2104 movs r1, #4 80147b6: 69f8 ldr r0, [r7, #28] 80147b8: 4798 blx r3 /* Try to release selects pending on 'read' or 'write', too. They will get an error if they actually try to read or write. */ API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); 80147ba: 69fb ldr r3, [r7, #28] 80147bc: 6a5b ldr r3, [r3, #36] ; 0x24 80147be: 2b00 cmp r3, #0 80147c0: d005 beq.n 80147ce 80147c2: 69fb ldr r3, [r7, #28] 80147c4: 6a5b ldr r3, [r3, #36] ; 0x24 80147c6: 2200 movs r2, #0 80147c8: 2100 movs r1, #0 80147ca: 69f8 ldr r0, [r7, #28] 80147cc: 4798 blx r3 API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); 80147ce: 69fb ldr r3, [r7, #28] 80147d0: 6a5b ldr r3, [r3, #36] ; 0x24 80147d2: 2b00 cmp r3, #0 80147d4: d005 beq.n 80147e2 80147d6: 69fb ldr r3, [r7, #28] 80147d8: 6a5b ldr r3, [r3, #36] ; 0x24 80147da: 2200 movs r2, #0 80147dc: 2102 movs r1, #2 80147de: 69f8 ldr r0, [r7, #28] 80147e0: 4798 blx r3 mbox_msg = lwip_netconn_err_to_msg(err); 80147e2: f997 3003 ldrsb.w r3, [r7, #3] 80147e6: 4618 mov r0, r3 80147e8: f7ff fd82 bl 80142f0 80147ec: 6138 str r0, [r7, #16] /* pass error message to recvmbox to wake up pending recv */ if (NETCONN_MBOX_VALID(conn, &conn->recvmbox)) { 80147ee: 69fb ldr r3, [r7, #28] 80147f0: 3310 adds r3, #16 80147f2: 4618 mov r0, r3 80147f4: f00c fe13 bl 802141e 80147f8: 4603 mov r3, r0 80147fa: 2b00 cmp r3, #0 80147fc: d005 beq.n 801480a /* use trypost to prevent deadlock */ sys_mbox_trypost(&conn->recvmbox, mbox_msg); 80147fe: 69fb ldr r3, [r7, #28] 8014800: 3310 adds r3, #16 8014802: 6939 ldr r1, [r7, #16] 8014804: 4618 mov r0, r3 8014806: f00c fd95 bl 8021334 } /* pass error message to acceptmbox to wake up pending accept */ if (NETCONN_MBOX_VALID(conn, &conn->acceptmbox)) { 801480a: 69fb ldr r3, [r7, #28] 801480c: 3314 adds r3, #20 801480e: 4618 mov r0, r3 8014810: f00c fe05 bl 802141e 8014814: 4603 mov r3, r0 8014816: 2b00 cmp r3, #0 8014818: d005 beq.n 8014826 /* use trypost to preven deadlock */ sys_mbox_trypost(&conn->acceptmbox, mbox_msg); 801481a: 69fb ldr r3, [r7, #28] 801481c: 3314 adds r3, #20 801481e: 6939 ldr r1, [r7, #16] 8014820: 4618 mov r0, r3 8014822: f00c fd87 bl 8021334 } if ((old_state == NETCONN_WRITE) || (old_state == NETCONN_CLOSE) || 8014826: 7dfb ldrb r3, [r7, #23] 8014828: 2b01 cmp r3, #1 801482a: d005 beq.n 8014838 801482c: 7dfb ldrb r3, [r7, #23] 801482e: 2b04 cmp r3, #4 8014830: d002 beq.n 8014838 8014832: 7dfb ldrb r3, [r7, #23] 8014834: 2b03 cmp r3, #3 8014836: d143 bne.n 80148c0 (old_state == NETCONN_CONNECT)) { /* calling lwip_netconn_do_writemore/lwip_netconn_do_close_internal is not necessary since the pcb has already been deleted! */ int was_nonblocking_connect = IN_NONBLOCKING_CONNECT(conn); 8014838: 69fb ldr r3, [r7, #28] 801483a: 7f1b ldrb r3, [r3, #28] 801483c: f003 0304 and.w r3, r3, #4 8014840: 2b00 cmp r3, #0 8014842: bf14 ite ne 8014844: 2301 movne r3, #1 8014846: 2300 moveq r3, #0 8014848: b2db uxtb r3, r3 801484a: 60fb str r3, [r7, #12] SET_NONBLOCKING_CONNECT(conn, 0); 801484c: 69fb ldr r3, [r7, #28] 801484e: 7f1b ldrb r3, [r3, #28] 8014850: f023 0304 bic.w r3, r3, #4 8014854: b2da uxtb r2, r3 8014856: 69fb ldr r3, [r7, #28] 8014858: 771a strb r2, [r3, #28] if (!was_nonblocking_connect) { 801485a: 68fb ldr r3, [r7, #12] 801485c: 2b00 cmp r3, #0 801485e: d13b bne.n 80148d8 sys_sem_t *op_completed_sem; /* set error return code */ LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); 8014860: 69fb ldr r3, [r7, #28] 8014862: 6a1b ldr r3, [r3, #32] 8014864: 2b00 cmp r3, #0 8014866: d106 bne.n 8014876 8014868: 4b1e ldr r3, [pc, #120] ; (80148e4 ) 801486a: f44f 72f3 mov.w r2, #486 ; 0x1e6 801486e: 4920 ldr r1, [pc, #128] ; (80148f0 ) 8014870: 481e ldr r0, [pc, #120] ; (80148ec ) 8014872: f00d f889 bl 8021988 if (old_state == NETCONN_CLOSE) { 8014876: 7dfb ldrb r3, [r7, #23] 8014878: 2b04 cmp r3, #4 801487a: d104 bne.n 8014886 /* let close succeed: the connection is closed after all... */ conn->current_msg->err = ERR_OK; 801487c: 69fb ldr r3, [r7, #28] 801487e: 6a1b ldr r3, [r3, #32] 8014880: 2200 movs r2, #0 8014882: 711a strb r2, [r3, #4] 8014884: e003 b.n 801488e } else { /* Write and connect fail */ conn->current_msg->err = err; 8014886: 69fb ldr r3, [r7, #28] 8014888: 6a1b ldr r3, [r3, #32] 801488a: 78fa ldrb r2, [r7, #3] 801488c: 711a strb r2, [r3, #4] } op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); 801488e: 69fb ldr r3, [r7, #28] 8014890: 6a1b ldr r3, [r3, #32] 8014892: 681b ldr r3, [r3, #0] 8014894: 330c adds r3, #12 8014896: 60bb str r3, [r7, #8] LWIP_ASSERT("inavlid op_completed_sem", sys_sem_valid(op_completed_sem)); 8014898: 68b8 ldr r0, [r7, #8] 801489a: f00c fe51 bl 8021540 801489e: 4603 mov r3, r0 80148a0: 2b00 cmp r3, #0 80148a2: d106 bne.n 80148b2 80148a4: 4b0f ldr r3, [pc, #60] ; (80148e4 ) 80148a6: f240 12ef movw r2, #495 ; 0x1ef 80148aa: 4912 ldr r1, [pc, #72] ; (80148f4 ) 80148ac: 480f ldr r0, [pc, #60] ; (80148ec ) 80148ae: f00d f86b bl 8021988 conn->current_msg = NULL; 80148b2: 69fb ldr r3, [r7, #28] 80148b4: 2200 movs r2, #0 80148b6: 621a str r2, [r3, #32] /* wake up the waiting task */ sys_sem_signal(op_completed_sem); 80148b8: 68b8 ldr r0, [r7, #8] 80148ba: f00c fe27 bl 802150c (old_state == NETCONN_CONNECT)) { 80148be: e00b b.n 80148d8 } else { /* @todo: test what happens for error on nonblocking connect */ } } else { LWIP_ASSERT("conn->current_msg == NULL", conn->current_msg == NULL); 80148c0: 69fb ldr r3, [r7, #28] 80148c2: 6a1b ldr r3, [r3, #32] 80148c4: 2b00 cmp r3, #0 80148c6: d008 beq.n 80148da 80148c8: 4b06 ldr r3, [pc, #24] ; (80148e4 ) 80148ca: f240 12f7 movw r2, #503 ; 0x1f7 80148ce: 490a ldr r1, [pc, #40] ; (80148f8 ) 80148d0: 4806 ldr r0, [pc, #24] ; (80148ec ) 80148d2: f00d f859 bl 8021988 } } 80148d6: e000 b.n 80148da (old_state == NETCONN_CONNECT)) { 80148d8: bf00 nop } 80148da: bf00 nop 80148dc: 3720 adds r7, #32 80148de: 46bd mov sp, r7 80148e0: bd80 pop {r7, pc} 80148e2: bf00 nop 80148e4: 08023624 .word 0x08023624 80148e8: 0802377c .word 0x0802377c 80148ec: 08023668 .word 0x08023668 80148f0: 0802378c .word 0x0802378c 80148f4: 080237a8 .word 0x080237a8 80148f8: 080237c4 .word 0x080237c4 080148fc : * * @param conn the TCP netconn to setup */ static void setup_tcp(struct netconn *conn) { 80148fc: b580 push {r7, lr} 80148fe: b084 sub sp, #16 8014900: af00 add r7, sp, #0 8014902: 6078 str r0, [r7, #4] struct tcp_pcb *pcb; pcb = conn->pcb.tcp; 8014904: 687b ldr r3, [r7, #4] 8014906: 685b ldr r3, [r3, #4] 8014908: 60fb str r3, [r7, #12] tcp_arg(pcb, conn); 801490a: 6879 ldr r1, [r7, #4] 801490c: 68f8 ldr r0, [r7, #12] 801490e: f004 ffc3 bl 8019898 tcp_recv(pcb, recv_tcp); 8014912: 490a ldr r1, [pc, #40] ; (801493c ) 8014914: 68f8 ldr r0, [r7, #12] 8014916: f004 ffd1 bl 80198bc tcp_sent(pcb, sent_tcp); 801491a: 4909 ldr r1, [pc, #36] ; (8014940 ) 801491c: 68f8 ldr r0, [r7, #12] 801491e: f004 ffef bl 8019900 tcp_poll(pcb, poll_tcp, NETCONN_TCP_POLL_INTERVAL); 8014922: 2202 movs r2, #2 8014924: 4907 ldr r1, [pc, #28] ; (8014944 ) 8014926: 68f8 ldr r0, [r7, #12] 8014928: f005 f846 bl 80199b8 tcp_err(pcb, err_tcp); 801492c: 4906 ldr r1, [pc, #24] ; (8014948 ) 801492e: 68f8 ldr r0, [r7, #12] 8014930: f005 f808 bl 8019944 } 8014934: bf00 nop 8014936: 3710 adds r7, #16 8014938: 46bd mov sp, r7 801493a: bd80 pop {r7, pc} 801493c: 080144cd .word 0x080144cd 8014940: 080146a5 .word 0x080146a5 8014944: 080145d9 .word 0x080145d9 8014948: 08014751 .word 0x08014751 0801494c : * * @param msg the api_msg describing the connection type */ static void pcb_new(struct api_msg *msg) { 801494c: b590 push {r4, r7, lr} 801494e: b085 sub sp, #20 8014950: af00 add r7, sp, #0 8014952: 6078 str r0, [r7, #4] enum lwip_ip_addr_type iptype = IPADDR_TYPE_V4; 8014954: 2300 movs r3, #0 8014956: 73fb strb r3, [r7, #15] LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL); 8014958: 687b ldr r3, [r7, #4] 801495a: 681b ldr r3, [r3, #0] 801495c: 685b ldr r3, [r3, #4] 801495e: 2b00 cmp r3, #0 8014960: d006 beq.n 8014970 8014962: 4b2b ldr r3, [pc, #172] ; (8014a10 ) 8014964: f240 2265 movw r2, #613 ; 0x265 8014968: 492a ldr r1, [pc, #168] ; (8014a14 ) 801496a: 482b ldr r0, [pc, #172] ; (8014a18 ) 801496c: f00d f80c bl 8021988 iptype = IPADDR_TYPE_ANY; } #endif /* Allocate a PCB for this connection */ switch (NETCONNTYPE_GROUP(msg->conn->type)) { 8014970: 687b ldr r3, [r7, #4] 8014972: 681b ldr r3, [r3, #0] 8014974: 781b ldrb r3, [r3, #0] 8014976: f003 03f0 and.w r3, r3, #240 ; 0xf0 801497a: 2b10 cmp r3, #16 801497c: d022 beq.n 80149c4 801497e: 2b20 cmp r3, #32 8014980: d133 bne.n 80149ea } break; #endif /* LWIP_RAW */ #if LWIP_UDP case NETCONN_UDP: msg->conn->pcb.udp = udp_new_ip_type(iptype); 8014982: 687b ldr r3, [r7, #4] 8014984: 681c ldr r4, [r3, #0] 8014986: 7bfb ldrb r3, [r7, #15] 8014988: 4618 mov r0, r3 801498a: f00a f944 bl 801ec16 801498e: 4603 mov r3, r0 8014990: 6063 str r3, [r4, #4] if (msg->conn->pcb.udp != NULL) { 8014992: 687b ldr r3, [r7, #4] 8014994: 681b ldr r3, [r3, #0] 8014996: 685b ldr r3, [r3, #4] 8014998: 2b00 cmp r3, #0 801499a: d02a beq.n 80149f2 #if LWIP_UDPLITE if (NETCONNTYPE_ISUDPLITE(msg->conn->type)) { udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); } #endif /* LWIP_UDPLITE */ if (NETCONNTYPE_ISUDPNOCHKSUM(msg->conn->type)) { 801499c: 687b ldr r3, [r7, #4] 801499e: 681b ldr r3, [r3, #0] 80149a0: 781b ldrb r3, [r3, #0] 80149a2: 2b22 cmp r3, #34 ; 0x22 80149a4: d104 bne.n 80149b0 udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); 80149a6: 687b ldr r3, [r7, #4] 80149a8: 681b ldr r3, [r3, #0] 80149aa: 685b ldr r3, [r3, #4] 80149ac: 2201 movs r2, #1 80149ae: 741a strb r2, [r3, #16] } udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); 80149b0: 687b ldr r3, [r7, #4] 80149b2: 681b ldr r3, [r3, #0] 80149b4: 6858 ldr r0, [r3, #4] 80149b6: 687b ldr r3, [r7, #4] 80149b8: 681b ldr r3, [r3, #0] 80149ba: 461a mov r2, r3 80149bc: 4917 ldr r1, [pc, #92] ; (8014a1c ) 80149be: f00a f8b1 bl 801eb24 } break; 80149c2: e016 b.n 80149f2 #endif /* LWIP_UDP */ #if LWIP_TCP case NETCONN_TCP: msg->conn->pcb.tcp = tcp_new_ip_type(iptype); 80149c4: 687b ldr r3, [r7, #4] 80149c6: 681c ldr r4, [r3, #0] 80149c8: 7bfb ldrb r3, [r7, #15] 80149ca: 4618 mov r0, r3 80149cc: f004 ff56 bl 801987c 80149d0: 4603 mov r3, r0 80149d2: 6063 str r3, [r4, #4] if (msg->conn->pcb.tcp != NULL) { 80149d4: 687b ldr r3, [r7, #4] 80149d6: 681b ldr r3, [r3, #0] 80149d8: 685b ldr r3, [r3, #4] 80149da: 2b00 cmp r3, #0 80149dc: d00b beq.n 80149f6 setup_tcp(msg->conn); 80149de: 687b ldr r3, [r7, #4] 80149e0: 681b ldr r3, [r3, #0] 80149e2: 4618 mov r0, r3 80149e4: f7ff ff8a bl 80148fc } break; 80149e8: e005 b.n 80149f6 #endif /* LWIP_TCP */ default: /* Unsupported netconn type, e.g. protocol disabled */ msg->err = ERR_VAL; 80149ea: 687b ldr r3, [r7, #4] 80149ec: 22fa movs r2, #250 ; 0xfa 80149ee: 711a strb r2, [r3, #4] return; 80149f0: e00a b.n 8014a08 break; 80149f2: bf00 nop 80149f4: e000 b.n 80149f8 break; 80149f6: bf00 nop } if (msg->conn->pcb.ip == NULL) { 80149f8: 687b ldr r3, [r7, #4] 80149fa: 681b ldr r3, [r3, #0] 80149fc: 685b ldr r3, [r3, #4] 80149fe: 2b00 cmp r3, #0 8014a00: d102 bne.n 8014a08 msg->err = ERR_MEM; 8014a02: 687b ldr r3, [r7, #4] 8014a04: 22ff movs r2, #255 ; 0xff 8014a06: 711a strb r2, [r3, #4] } } 8014a08: 3714 adds r7, #20 8014a0a: 46bd mov sp, r7 8014a0c: bd90 pop {r4, r7, pc} 8014a0e: bf00 nop 8014a10: 08023624 .word 0x08023624 8014a14: 08023808 .word 0x08023808 8014a18: 08023668 .word 0x08023668 8014a1c: 080143d1 .word 0x080143d1 08014a20 : * * @param m the api_msg describing the connection type */ void lwip_netconn_do_newconn(void *m) { 8014a20: b580 push {r7, lr} 8014a22: b084 sub sp, #16 8014a24: af00 add r7, sp, #0 8014a26: 6078 str r0, [r7, #4] struct api_msg *msg = (struct api_msg *)m; 8014a28: 687b ldr r3, [r7, #4] 8014a2a: 60fb str r3, [r7, #12] msg->err = ERR_OK; 8014a2c: 68fb ldr r3, [r7, #12] 8014a2e: 2200 movs r2, #0 8014a30: 711a strb r2, [r3, #4] if (msg->conn->pcb.tcp == NULL) { 8014a32: 68fb ldr r3, [r7, #12] 8014a34: 681b ldr r3, [r3, #0] 8014a36: 685b ldr r3, [r3, #4] 8014a38: 2b00 cmp r3, #0 8014a3a: d102 bne.n 8014a42 pcb_new(msg); 8014a3c: 68f8 ldr r0, [r7, #12] 8014a3e: f7ff ff85 bl 801494c /* Else? This "new" connection already has a PCB allocated. */ /* Is this an error condition? Should it be deleted? */ /* We currently just are happy and return. */ TCPIP_APIMSG_ACK(msg); } 8014a42: bf00 nop 8014a44: 3710 adds r7, #16 8014a46: 46bd mov sp, r7 8014a48: bd80 pop {r7, pc} ... 08014a4c : * @return a newly allocated struct netconn or * NULL on memory error */ struct netconn * netconn_alloc(enum netconn_type t, netconn_callback callback) { 8014a4c: b580 push {r7, lr} 8014a4e: b086 sub sp, #24 8014a50: af00 add r7, sp, #0 8014a52: 4603 mov r3, r0 8014a54: 6039 str r1, [r7, #0] 8014a56: 71fb strb r3, [r7, #7] struct netconn *conn; int size; u8_t init_flags = 0; 8014a58: 2300 movs r3, #0 8014a5a: 74fb strb r3, [r7, #19] conn = (struct netconn *)memp_malloc(MEMP_NETCONN); 8014a5c: 2007 movs r0, #7 8014a5e: f002 f837 bl 8016ad0 8014a62: 60f8 str r0, [r7, #12] if (conn == NULL) { 8014a64: 68fb ldr r3, [r7, #12] 8014a66: 2b00 cmp r3, #0 8014a68: d101 bne.n 8014a6e return NULL; 8014a6a: 2300 movs r3, #0 8014a6c: e052 b.n 8014b14 } conn->pending_err = ERR_OK; 8014a6e: 68fb ldr r3, [r7, #12] 8014a70: 2200 movs r2, #0 8014a72: 721a strb r2, [r3, #8] conn->type = t; 8014a74: 68fb ldr r3, [r7, #12] 8014a76: 79fa ldrb r2, [r7, #7] 8014a78: 701a strb r2, [r3, #0] conn->pcb.tcp = NULL; 8014a7a: 68fb ldr r3, [r7, #12] 8014a7c: 2200 movs r2, #0 8014a7e: 605a str r2, [r3, #4] /* If all sizes are the same, every compiler should optimize this switch to nothing */ switch (NETCONNTYPE_GROUP(t)) { 8014a80: 79fb ldrb r3, [r7, #7] 8014a82: f003 03f0 and.w r3, r3, #240 ; 0xf0 8014a86: 2b10 cmp r3, #16 8014a88: d004 beq.n 8014a94 8014a8a: 2b20 cmp r3, #32 8014a8c: d105 bne.n 8014a9a size = DEFAULT_RAW_RECVMBOX_SIZE; break; #endif /* LWIP_RAW */ #if LWIP_UDP case NETCONN_UDP: size = DEFAULT_UDP_RECVMBOX_SIZE; 8014a8e: 2306 movs r3, #6 8014a90: 617b str r3, [r7, #20] #if LWIP_NETBUF_RECVINFO init_flags |= NETCONN_FLAG_PKTINFO; #endif /* LWIP_NETBUF_RECVINFO */ break; 8014a92: e00a b.n 8014aaa #endif /* LWIP_UDP */ #if LWIP_TCP case NETCONN_TCP: size = DEFAULT_TCP_RECVMBOX_SIZE; 8014a94: 2306 movs r3, #6 8014a96: 617b str r3, [r7, #20] break; 8014a98: e007 b.n 8014aaa #endif /* LWIP_TCP */ default: LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0); 8014a9a: 4b20 ldr r3, [pc, #128] ; (8014b1c ) 8014a9c: f240 22e5 movw r2, #741 ; 0x2e5 8014aa0: 491f ldr r1, [pc, #124] ; (8014b20 ) 8014aa2: 4820 ldr r0, [pc, #128] ; (8014b24 ) 8014aa4: f00c ff70 bl 8021988 goto free_and_return; 8014aa8: e02f b.n 8014b0a } if (sys_mbox_new(&conn->recvmbox, size) != ERR_OK) { 8014aaa: 68fb ldr r3, [r7, #12] 8014aac: 3310 adds r3, #16 8014aae: 6979 ldr r1, [r7, #20] 8014ab0: 4618 mov r0, r3 8014ab2: f00c fc0b bl 80212cc 8014ab6: 4603 mov r3, r0 8014ab8: 2b00 cmp r3, #0 8014aba: d125 bne.n 8014b08 goto free_and_return; } #if !LWIP_NETCONN_SEM_PER_THREAD if (sys_sem_new(&conn->op_completed, 0) != ERR_OK) { 8014abc: 68fb ldr r3, [r7, #12] 8014abe: 330c adds r3, #12 8014ac0: 2100 movs r1, #0 8014ac2: 4618 mov r0, r3 8014ac4: f00c fcc9 bl 802145a 8014ac8: 4603 mov r3, r0 8014aca: 2b00 cmp r3, #0 8014acc: d005 beq.n 8014ada sys_mbox_free(&conn->recvmbox); 8014ace: 68fb ldr r3, [r7, #12] 8014ad0: 3310 adds r3, #16 8014ad2: 4618 mov r0, r3 8014ad4: f00c fc1c bl 8021310 goto free_and_return; 8014ad8: e017 b.n 8014b0a } #endif #if LWIP_TCP sys_mbox_set_invalid(&conn->acceptmbox); 8014ada: 68fb ldr r3, [r7, #12] 8014adc: 3314 adds r3, #20 8014ade: 4618 mov r0, r3 8014ae0: f00c fcae bl 8021440 #endif conn->state = NETCONN_NONE; 8014ae4: 68fb ldr r3, [r7, #12] 8014ae6: 2200 movs r2, #0 8014ae8: 705a strb r2, [r3, #1] #if LWIP_SOCKET /* initialize socket to -1 since 0 is a valid socket */ conn->socket = -1; 8014aea: 68fb ldr r3, [r7, #12] 8014aec: f04f 32ff mov.w r2, #4294967295 8014af0: 619a str r2, [r3, #24] #endif /* LWIP_SOCKET */ conn->callback = callback; 8014af2: 68fb ldr r3, [r7, #12] 8014af4: 683a ldr r2, [r7, #0] 8014af6: 625a str r2, [r3, #36] ; 0x24 #if LWIP_TCP conn->current_msg = NULL; 8014af8: 68fb ldr r3, [r7, #12] 8014afa: 2200 movs r2, #0 8014afc: 621a str r2, [r3, #32] conn->recv_avail = 0; #endif /* LWIP_SO_RCVBUF */ #if LWIP_SO_LINGER conn->linger = -1; #endif /* LWIP_SO_LINGER */ conn->flags = init_flags; 8014afe: 68fb ldr r3, [r7, #12] 8014b00: 7cfa ldrb r2, [r7, #19] 8014b02: 771a strb r2, [r3, #28] return conn; 8014b04: 68fb ldr r3, [r7, #12] 8014b06: e005 b.n 8014b14 goto free_and_return; 8014b08: bf00 nop free_and_return: memp_free(MEMP_NETCONN, conn); 8014b0a: 68f9 ldr r1, [r7, #12] 8014b0c: 2007 movs r0, #7 8014b0e: f002 f855 bl 8016bbc return NULL; 8014b12: 2300 movs r3, #0 } 8014b14: 4618 mov r0, r3 8014b16: 3718 adds r7, #24 8014b18: 46bd mov sp, r7 8014b1a: bd80 pop {r7, pc} 8014b1c: 08023624 .word 0x08023624 8014b20: 08023828 .word 0x08023828 8014b24: 08023668 .word 0x08023668 08014b28 : * * @param conn the netconn to free */ void netconn_free(struct netconn *conn) { 8014b28: b580 push {r7, lr} 8014b2a: b082 sub sp, #8 8014b2c: af00 add r7, sp, #0 8014b2e: 6078 str r0, [r7, #4] LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL); 8014b30: 687b ldr r3, [r7, #4] 8014b32: 685b ldr r3, [r3, #4] 8014b34: 2b00 cmp r3, #0 8014b36: d006 beq.n 8014b46 8014b38: 4b1b ldr r3, [pc, #108] ; (8014ba8 ) 8014b3a: f44f 7247 mov.w r2, #796 ; 0x31c 8014b3e: 491b ldr r1, [pc, #108] ; (8014bac ) 8014b40: 481b ldr r0, [pc, #108] ; (8014bb0 ) 8014b42: f00c ff21 bl 8021988 #if LWIP_NETCONN_FULLDUPLEX /* in fullduplex, netconn is drained here */ netconn_drain(conn); #endif /* LWIP_NETCONN_FULLDUPLEX */ LWIP_ASSERT("recvmbox must be deallocated before calling this function", 8014b46: 687b ldr r3, [r7, #4] 8014b48: 3310 adds r3, #16 8014b4a: 4618 mov r0, r3 8014b4c: f00c fc67 bl 802141e 8014b50: 4603 mov r3, r0 8014b52: 2b00 cmp r3, #0 8014b54: d006 beq.n 8014b64 8014b56: 4b14 ldr r3, [pc, #80] ; (8014ba8 ) 8014b58: f240 3223 movw r2, #803 ; 0x323 8014b5c: 4915 ldr r1, [pc, #84] ; (8014bb4 ) 8014b5e: 4814 ldr r0, [pc, #80] ; (8014bb0 ) 8014b60: f00c ff12 bl 8021988 !sys_mbox_valid(&conn->recvmbox)); #if LWIP_TCP LWIP_ASSERT("acceptmbox must be deallocated before calling this function", 8014b64: 687b ldr r3, [r7, #4] 8014b66: 3314 adds r3, #20 8014b68: 4618 mov r0, r3 8014b6a: f00c fc58 bl 802141e 8014b6e: 4603 mov r3, r0 8014b70: 2b00 cmp r3, #0 8014b72: d006 beq.n 8014b82 8014b74: 4b0c ldr r3, [pc, #48] ; (8014ba8 ) 8014b76: f240 3226 movw r2, #806 ; 0x326 8014b7a: 490f ldr r1, [pc, #60] ; (8014bb8 ) 8014b7c: 480c ldr r0, [pc, #48] ; (8014bb0 ) 8014b7e: f00c ff03 bl 8021988 !sys_mbox_valid(&conn->acceptmbox)); #endif /* LWIP_TCP */ #if !LWIP_NETCONN_SEM_PER_THREAD sys_sem_free(&conn->op_completed); 8014b82: 687b ldr r3, [r7, #4] 8014b84: 330c adds r3, #12 8014b86: 4618 mov r0, r3 8014b88: f00c fccd bl 8021526 sys_sem_set_invalid(&conn->op_completed); 8014b8c: 687b ldr r3, [r7, #4] 8014b8e: 330c adds r3, #12 8014b90: 4618 mov r0, r3 8014b92: f00c fce6 bl 8021562 #endif memp_free(MEMP_NETCONN, conn); 8014b96: 6879 ldr r1, [r7, #4] 8014b98: 2007 movs r0, #7 8014b9a: f002 f80f bl 8016bbc } 8014b9e: bf00 nop 8014ba0: 3708 adds r7, #8 8014ba2: 46bd mov sp, r7 8014ba4: bd80 pop {r7, pc} 8014ba6: bf00 nop 8014ba8: 08023624 .word 0x08023624 8014bac: 08023850 .word 0x08023850 8014bb0: 08023668 .word 0x08023668 8014bb4: 08023880 .word 0x08023880 8014bb8: 080238bc .word 0x080238bc 08014bbc : * @bytes_drained bytes drained from recvmbox * @accepts_drained pending connections drained from acceptmbox */ static void netconn_drain(struct netconn *conn) { 8014bbc: b580 push {r7, lr} 8014bbe: b086 sub sp, #24 8014bc0: af00 add r7, sp, #0 8014bc2: 6078 str r0, [r7, #4] #if LWIP_NETCONN_FULLDUPLEX LWIP_ASSERT("netconn marked closed", conn->flags & NETCONN_FLAG_MBOXINVALID); #endif /* LWIP_NETCONN_FULLDUPLEX */ /* Delete and drain the recvmbox. */ if (sys_mbox_valid(&conn->recvmbox)) { 8014bc4: 687b ldr r3, [r7, #4] 8014bc6: 3310 adds r3, #16 8014bc8: 4618 mov r0, r3 8014bca: f00c fc28 bl 802141e 8014bce: 4603 mov r3, r0 8014bd0: 2b00 cmp r3, #0 8014bd2: d02f beq.n 8014c34 while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) { 8014bd4: e018 b.n 8014c08 #if LWIP_NETCONN_FULLDUPLEX if (!lwip_netconn_is_deallocated_msg(mem)) #endif /* LWIP_NETCONN_FULLDUPLEX */ { #if LWIP_TCP if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) { 8014bd6: 687b ldr r3, [r7, #4] 8014bd8: 781b ldrb r3, [r3, #0] 8014bda: f003 03f0 and.w r3, r3, #240 ; 0xf0 8014bde: 2b10 cmp r3, #16 8014be0: d10e bne.n 8014c00 err_t err; if (!lwip_netconn_is_err_msg(mem, &err)) { 8014be2: 693b ldr r3, [r7, #16] 8014be4: f107 020f add.w r2, r7, #15 8014be8: 4611 mov r1, r2 8014bea: 4618 mov r0, r3 8014bec: f7ff fbb6 bl 801435c 8014bf0: 4603 mov r3, r0 8014bf2: 2b00 cmp r3, #0 8014bf4: d108 bne.n 8014c08 pbuf_free((struct pbuf *)mem); 8014bf6: 693b ldr r3, [r7, #16] 8014bf8: 4618 mov r0, r3 8014bfa: f002 ff7d bl 8017af8 8014bfe: e003 b.n 8014c08 } } else #endif /* LWIP_TCP */ { netbuf_delete((struct netbuf *)mem); 8014c00: 693b ldr r3, [r7, #16] 8014c02: 4618 mov r0, r3 8014c04: f000 ff4a bl 8015a9c while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) { 8014c08: 687b ldr r3, [r7, #4] 8014c0a: 3310 adds r3, #16 8014c0c: f107 0210 add.w r2, r7, #16 8014c10: 4611 mov r1, r2 8014c12: 4618 mov r0, r3 8014c14: f00c fbe7 bl 80213e6 8014c18: 4603 mov r3, r0 8014c1a: f1b3 3fff cmp.w r3, #4294967295 8014c1e: d1da bne.n 8014bd6 } } } sys_mbox_free(&conn->recvmbox); 8014c20: 687b ldr r3, [r7, #4] 8014c22: 3310 adds r3, #16 8014c24: 4618 mov r0, r3 8014c26: f00c fb73 bl 8021310 sys_mbox_set_invalid(&conn->recvmbox); 8014c2a: 687b ldr r3, [r7, #4] 8014c2c: 3310 adds r3, #16 8014c2e: 4618 mov r0, r3 8014c30: f00c fc06 bl 8021440 } /* Delete and drain the acceptmbox. */ #if LWIP_TCP if (sys_mbox_valid(&conn->acceptmbox)) { 8014c34: 687b ldr r3, [r7, #4] 8014c36: 3314 adds r3, #20 8014c38: 4618 mov r0, r3 8014c3a: f00c fbf0 bl 802141e 8014c3e: 4603 mov r3, r0 8014c40: 2b00 cmp r3, #0 8014c42: d034 beq.n 8014cae while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) { 8014c44: e01d b.n 8014c82 #if LWIP_NETCONN_FULLDUPLEX if (!lwip_netconn_is_deallocated_msg(mem)) #endif /* LWIP_NETCONN_FULLDUPLEX */ { err_t err; if (!lwip_netconn_is_err_msg(mem, &err)) { 8014c46: 693b ldr r3, [r7, #16] 8014c48: f107 020e add.w r2, r7, #14 8014c4c: 4611 mov r1, r2 8014c4e: 4618 mov r0, r3 8014c50: f7ff fb84 bl 801435c 8014c54: 4603 mov r3, r0 8014c56: 2b00 cmp r3, #0 8014c58: d113 bne.n 8014c82 struct netconn *newconn = (struct netconn *)mem; 8014c5a: 693b ldr r3, [r7, #16] 8014c5c: 617b str r3, [r7, #20] /* Only tcp pcbs have an acceptmbox, so no need to check conn->type */ /* pcb might be set to NULL already by err_tcp() */ /* drain recvmbox */ netconn_drain(newconn); 8014c5e: 6978 ldr r0, [r7, #20] 8014c60: f7ff ffac bl 8014bbc if (newconn->pcb.tcp != NULL) { 8014c64: 697b ldr r3, [r7, #20] 8014c66: 685b ldr r3, [r3, #4] 8014c68: 2b00 cmp r3, #0 8014c6a: d007 beq.n 8014c7c tcp_abort(newconn->pcb.tcp); 8014c6c: 697b ldr r3, [r7, #20] 8014c6e: 685b ldr r3, [r3, #4] 8014c70: 4618 mov r0, r3 8014c72: f003 fd31 bl 80186d8 newconn->pcb.tcp = NULL; 8014c76: 697b ldr r3, [r7, #20] 8014c78: 2200 movs r2, #0 8014c7a: 605a str r2, [r3, #4] } netconn_free(newconn); 8014c7c: 6978 ldr r0, [r7, #20] 8014c7e: f7ff ff53 bl 8014b28 while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) { 8014c82: 687b ldr r3, [r7, #4] 8014c84: 3314 adds r3, #20 8014c86: f107 0210 add.w r2, r7, #16 8014c8a: 4611 mov r1, r2 8014c8c: 4618 mov r0, r3 8014c8e: f00c fbaa bl 80213e6 8014c92: 4603 mov r3, r0 8014c94: f1b3 3fff cmp.w r3, #4294967295 8014c98: d1d5 bne.n 8014c46 } } } sys_mbox_free(&conn->acceptmbox); 8014c9a: 687b ldr r3, [r7, #4] 8014c9c: 3314 adds r3, #20 8014c9e: 4618 mov r0, r3 8014ca0: f00c fb36 bl 8021310 sys_mbox_set_invalid(&conn->acceptmbox); 8014ca4: 687b ldr r3, [r7, #4] 8014ca6: 3314 adds r3, #20 8014ca8: 4618 mov r0, r3 8014caa: f00c fbc9 bl 8021440 } #endif /* LWIP_TCP */ } 8014cae: bf00 nop 8014cb0: 3718 adds r7, #24 8014cb2: 46bd mov sp, r7 8014cb4: bd80 pop {r7, pc} ... 08014cb8 : * * @param conn the TCP netconn to close */ static err_t lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM) { 8014cb8: b580 push {r7, lr} 8014cba: b086 sub sp, #24 8014cbc: af00 add r7, sp, #0 8014cbe: 6078 str r0, [r7, #4] 8014cc0: 460b mov r3, r1 8014cc2: 70fb strb r3, [r7, #3] err_t err; u8_t shut, shut_rx, shut_tx, shut_close; u8_t close_finished = 0; 8014cc4: 2300 movs r3, #0 8014cc6: 757b strb r3, [r7, #21] struct tcp_pcb *tpcb; #if LWIP_SO_LINGER u8_t linger_wait_required = 0; #endif /* LWIP_SO_LINGER */ LWIP_ASSERT("invalid conn", (conn != NULL)); 8014cc8: 687b ldr r3, [r7, #4] 8014cca: 2b00 cmp r3, #0 8014ccc: d106 bne.n 8014cdc 8014cce: 4b87 ldr r3, [pc, #540] ; (8014eec ) 8014cd0: f240 32a2 movw r2, #930 ; 0x3a2 8014cd4: 4986 ldr r1, [pc, #536] ; (8014ef0 ) 8014cd6: 4887 ldr r0, [pc, #540] ; (8014ef4 ) 8014cd8: f00c fe56 bl 8021988 LWIP_ASSERT("this is for tcp netconns only", (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP)); 8014cdc: 687b ldr r3, [r7, #4] 8014cde: 781b ldrb r3, [r3, #0] 8014ce0: f003 03f0 and.w r3, r3, #240 ; 0xf0 8014ce4: 2b10 cmp r3, #16 8014ce6: d006 beq.n 8014cf6 8014ce8: 4b80 ldr r3, [pc, #512] ; (8014eec ) 8014cea: f240 32a3 movw r2, #931 ; 0x3a3 8014cee: 4982 ldr r1, [pc, #520] ; (8014ef8 ) 8014cf0: 4880 ldr r0, [pc, #512] ; (8014ef4 ) 8014cf2: f00c fe49 bl 8021988 LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE)); 8014cf6: 687b ldr r3, [r7, #4] 8014cf8: 785b ldrb r3, [r3, #1] 8014cfa: 2b04 cmp r3, #4 8014cfc: d006 beq.n 8014d0c 8014cfe: 4b7b ldr r3, [pc, #492] ; (8014eec ) 8014d00: f44f 7269 mov.w r2, #932 ; 0x3a4 8014d04: 497d ldr r1, [pc, #500] ; (8014efc ) 8014d06: 487b ldr r0, [pc, #492] ; (8014ef4 ) 8014d08: f00c fe3e bl 8021988 LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL)); 8014d0c: 687b ldr r3, [r7, #4] 8014d0e: 685b ldr r3, [r3, #4] 8014d10: 2b00 cmp r3, #0 8014d12: d106 bne.n 8014d22 8014d14: 4b75 ldr r3, [pc, #468] ; (8014eec ) 8014d16: f240 32a5 movw r2, #933 ; 0x3a5 8014d1a: 4979 ldr r1, [pc, #484] ; (8014f00 ) 8014d1c: 4875 ldr r0, [pc, #468] ; (8014ef4 ) 8014d1e: f00c fe33 bl 8021988 LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); 8014d22: 687b ldr r3, [r7, #4] 8014d24: 6a1b ldr r3, [r3, #32] 8014d26: 2b00 cmp r3, #0 8014d28: d106 bne.n 8014d38 8014d2a: 4b70 ldr r3, [pc, #448] ; (8014eec ) 8014d2c: f240 32a6 movw r2, #934 ; 0x3a6 8014d30: 4974 ldr r1, [pc, #464] ; (8014f04 ) 8014d32: 4870 ldr r0, [pc, #448] ; (8014ef4 ) 8014d34: f00c fe28 bl 8021988 tpcb = conn->pcb.tcp; 8014d38: 687b ldr r3, [r7, #4] 8014d3a: 685b ldr r3, [r3, #4] 8014d3c: 613b str r3, [r7, #16] shut = conn->current_msg->msg.sd.shut; 8014d3e: 687b ldr r3, [r7, #4] 8014d40: 6a1b ldr r3, [r3, #32] 8014d42: 7a1b ldrb r3, [r3, #8] 8014d44: 73fb strb r3, [r7, #15] shut_rx = shut & NETCONN_SHUT_RD; 8014d46: 7bfb ldrb r3, [r7, #15] 8014d48: f003 0301 and.w r3, r3, #1 8014d4c: 73bb strb r3, [r7, #14] shut_tx = shut & NETCONN_SHUT_WR; 8014d4e: 7bfb ldrb r3, [r7, #15] 8014d50: f003 0302 and.w r3, r3, #2 8014d54: 737b strb r3, [r7, #13] /* shutting down both ends is the same as closing (also if RD or WR side was shut down before already) */ if (shut == NETCONN_SHUT_RDWR) { 8014d56: 7bfb ldrb r3, [r7, #15] 8014d58: 2b03 cmp r3, #3 8014d5a: d102 bne.n 8014d62 shut_close = 1; 8014d5c: 2301 movs r3, #1 8014d5e: 75bb strb r3, [r7, #22] 8014d60: e01f b.n 8014da2 } else if (shut_rx && 8014d62: 7bbb ldrb r3, [r7, #14] 8014d64: 2b00 cmp r3, #0 8014d66: d00e beq.n 8014d86 ((tpcb->state == FIN_WAIT_1) || 8014d68: 693b ldr r3, [r7, #16] 8014d6a: 7d1b ldrb r3, [r3, #20] } else if (shut_rx && 8014d6c: 2b05 cmp r3, #5 8014d6e: d007 beq.n 8014d80 (tpcb->state == FIN_WAIT_2) || 8014d70: 693b ldr r3, [r7, #16] 8014d72: 7d1b ldrb r3, [r3, #20] ((tpcb->state == FIN_WAIT_1) || 8014d74: 2b06 cmp r3, #6 8014d76: d003 beq.n 8014d80 (tpcb->state == CLOSING))) { 8014d78: 693b ldr r3, [r7, #16] 8014d7a: 7d1b ldrb r3, [r3, #20] (tpcb->state == FIN_WAIT_2) || 8014d7c: 2b08 cmp r3, #8 8014d7e: d102 bne.n 8014d86 shut_close = 1; 8014d80: 2301 movs r3, #1 8014d82: 75bb strb r3, [r7, #22] 8014d84: e00d b.n 8014da2 } else if (shut_tx && ((tpcb->flags & TF_RXCLOSED) != 0)) { 8014d86: 7b7b ldrb r3, [r7, #13] 8014d88: 2b00 cmp r3, #0 8014d8a: d008 beq.n 8014d9e 8014d8c: 693b ldr r3, [r7, #16] 8014d8e: 8b5b ldrh r3, [r3, #26] 8014d90: f003 0310 and.w r3, r3, #16 8014d94: 2b00 cmp r3, #0 8014d96: d002 beq.n 8014d9e shut_close = 1; 8014d98: 2301 movs r3, #1 8014d9a: 75bb strb r3, [r7, #22] 8014d9c: e001 b.n 8014da2 } else { shut_close = 0; 8014d9e: 2300 movs r3, #0 8014da0: 75bb strb r3, [r7, #22] } /* Set back some callback pointers */ if (shut_close) { 8014da2: 7dbb ldrb r3, [r7, #22] 8014da4: 2b00 cmp r3, #0 8014da6: d003 beq.n 8014db0 tcp_arg(tpcb, NULL); 8014da8: 2100 movs r1, #0 8014daa: 6938 ldr r0, [r7, #16] 8014dac: f004 fd74 bl 8019898 } if (tpcb->state == LISTEN) { 8014db0: 693b ldr r3, [r7, #16] 8014db2: 7d1b ldrb r3, [r3, #20] 8014db4: 2b01 cmp r3, #1 8014db6: d104 bne.n 8014dc2 tcp_accept(tpcb, NULL); 8014db8: 2100 movs r1, #0 8014dba: 6938 ldr r0, [r7, #16] 8014dbc: f004 fde4 bl 8019988 8014dc0: e01d b.n 8014dfe } else { /* some callbacks have to be reset if tcp_close is not successful */ if (shut_rx) { 8014dc2: 7bbb ldrb r3, [r7, #14] 8014dc4: 2b00 cmp r3, #0 8014dc6: d007 beq.n 8014dd8 tcp_recv(tpcb, NULL); 8014dc8: 2100 movs r1, #0 8014dca: 6938 ldr r0, [r7, #16] 8014dcc: f004 fd76 bl 80198bc tcp_accept(tpcb, NULL); 8014dd0: 2100 movs r1, #0 8014dd2: 6938 ldr r0, [r7, #16] 8014dd4: f004 fdd8 bl 8019988 } if (shut_tx) { 8014dd8: 7b7b ldrb r3, [r7, #13] 8014dda: 2b00 cmp r3, #0 8014ddc: d003 beq.n 8014de6 tcp_sent(tpcb, NULL); 8014dde: 2100 movs r1, #0 8014de0: 6938 ldr r0, [r7, #16] 8014de2: f004 fd8d bl 8019900 } if (shut_close) { 8014de6: 7dbb ldrb r3, [r7, #22] 8014de8: 2b00 cmp r3, #0 8014dea: d008 beq.n 8014dfe tcp_poll(tpcb, NULL, 0); 8014dec: 2200 movs r2, #0 8014dee: 2100 movs r1, #0 8014df0: 6938 ldr r0, [r7, #16] 8014df2: f004 fde1 bl 80199b8 tcp_err(tpcb, NULL); 8014df6: 2100 movs r1, #0 8014df8: 6938 ldr r0, [r7, #16] 8014dfa: f004 fda3 bl 8019944 } } /* Try to close the connection */ if (shut_close) { 8014dfe: 7dbb ldrb r3, [r7, #22] 8014e00: 2b00 cmp r3, #0 8014e02: d005 beq.n 8014e10 } } if ((err == ERR_OK) && (tpcb != NULL)) #endif /* LWIP_SO_LINGER */ { err = tcp_close(tpcb); 8014e04: 6938 ldr r0, [r7, #16] 8014e06: f003 fb21 bl 801844c 8014e0a: 4603 mov r3, r0 8014e0c: 75fb strb r3, [r7, #23] 8014e0e: e007 b.n 8014e20 } } else { err = tcp_shutdown(tpcb, shut_rx, shut_tx); 8014e10: 7bbb ldrb r3, [r7, #14] 8014e12: 7b7a ldrb r2, [r7, #13] 8014e14: 4619 mov r1, r3 8014e16: 6938 ldr r0, [r7, #16] 8014e18: f003 fb44 bl 80184a4 8014e1c: 4603 mov r3, r0 8014e1e: 75fb strb r3, [r7, #23] } if (err == ERR_OK) { 8014e20: f997 3017 ldrsb.w r3, [r7, #23] 8014e24: 2b00 cmp r3, #0 8014e26: d102 bne.n 8014e2e close_finished = 1; 8014e28: 2301 movs r3, #1 8014e2a: 757b strb r3, [r7, #21] 8014e2c: e016 b.n 8014e5c close_finished = 0; err = ERR_INPROGRESS; } #endif /* LWIP_SO_LINGER */ } else { if (err == ERR_MEM) { 8014e2e: f997 3017 ldrsb.w r3, [r7, #23] 8014e32: f1b3 3fff cmp.w r3, #4294967295 8014e36: d10f bne.n 8014e58 close_timeout = conn->linger * 1000U; } #endif if ((s32_t)(sys_now() - conn->current_msg->msg.sd.time_started) >= close_timeout) { #else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ if (conn->current_msg->msg.sd.polls_left == 0) { 8014e38: 687b ldr r3, [r7, #4] 8014e3a: 6a1b ldr r3, [r3, #32] 8014e3c: 7a5b ldrb r3, [r3, #9] 8014e3e: 2b00 cmp r3, #0 8014e40: d10c bne.n 8014e5c #endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ close_finished = 1; 8014e42: 2301 movs r3, #1 8014e44: 757b strb r3, [r7, #21] if (shut_close) { 8014e46: 7dbb ldrb r3, [r7, #22] 8014e48: 2b00 cmp r3, #0 8014e4a: d007 beq.n 8014e5c /* in this case, we want to RST the connection */ tcp_abort(tpcb); 8014e4c: 6938 ldr r0, [r7, #16] 8014e4e: f003 fc43 bl 80186d8 err = ERR_OK; 8014e52: 2300 movs r3, #0 8014e54: 75fb strb r3, [r7, #23] 8014e56: e001 b.n 8014e5c } } } else { /* Closing failed for a non-memory error: give up */ close_finished = 1; 8014e58: 2301 movs r3, #1 8014e5a: 757b strb r3, [r7, #21] } } if (close_finished) { 8014e5c: 7d7b ldrb r3, [r7, #21] 8014e5e: 2b00 cmp r3, #0 8014e60: d052 beq.n 8014f08 /* Closing done (succeeded, non-memory error, nonblocking error or timeout) */ sys_sem_t *op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); 8014e62: 687b ldr r3, [r7, #4] 8014e64: 6a1b ldr r3, [r3, #32] 8014e66: 681b ldr r3, [r3, #0] 8014e68: 330c adds r3, #12 8014e6a: 60bb str r3, [r7, #8] conn->current_msg->err = err; 8014e6c: 687b ldr r3, [r7, #4] 8014e6e: 6a1b ldr r3, [r3, #32] 8014e70: 7dfa ldrb r2, [r7, #23] 8014e72: 711a strb r2, [r3, #4] conn->current_msg = NULL; 8014e74: 687b ldr r3, [r7, #4] 8014e76: 2200 movs r2, #0 8014e78: 621a str r2, [r3, #32] conn->state = NETCONN_NONE; 8014e7a: 687b ldr r3, [r7, #4] 8014e7c: 2200 movs r2, #0 8014e7e: 705a strb r2, [r3, #1] if (err == ERR_OK) { 8014e80: f997 3017 ldrsb.w r3, [r7, #23] 8014e84: 2b00 cmp r3, #0 8014e86: d129 bne.n 8014edc if (shut_close) { 8014e88: 7dbb ldrb r3, [r7, #22] 8014e8a: 2b00 cmp r3, #0 8014e8c: d00c beq.n 8014ea8 /* Set back some callback pointers as conn is going away */ conn->pcb.tcp = NULL; 8014e8e: 687b ldr r3, [r7, #4] 8014e90: 2200 movs r2, #0 8014e92: 605a str r2, [r3, #4] /* Trigger select() in socket layer. Make sure everybody notices activity on the connection, error first! */ API_EVENT(conn, NETCONN_EVT_ERROR, 0); 8014e94: 687b ldr r3, [r7, #4] 8014e96: 6a5b ldr r3, [r3, #36] ; 0x24 8014e98: 2b00 cmp r3, #0 8014e9a: d005 beq.n 8014ea8 8014e9c: 687b ldr r3, [r7, #4] 8014e9e: 6a5b ldr r3, [r3, #36] ; 0x24 8014ea0: 2200 movs r2, #0 8014ea2: 2104 movs r1, #4 8014ea4: 6878 ldr r0, [r7, #4] 8014ea6: 4798 blx r3 } if (shut_rx) { 8014ea8: 7bbb ldrb r3, [r7, #14] 8014eaa: 2b00 cmp r3, #0 8014eac: d009 beq.n 8014ec2 API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); 8014eae: 687b ldr r3, [r7, #4] 8014eb0: 6a5b ldr r3, [r3, #36] ; 0x24 8014eb2: 2b00 cmp r3, #0 8014eb4: d005 beq.n 8014ec2 8014eb6: 687b ldr r3, [r7, #4] 8014eb8: 6a5b ldr r3, [r3, #36] ; 0x24 8014eba: 2200 movs r2, #0 8014ebc: 2100 movs r1, #0 8014ebe: 6878 ldr r0, [r7, #4] 8014ec0: 4798 blx r3 } if (shut_tx) { 8014ec2: 7b7b ldrb r3, [r7, #13] 8014ec4: 2b00 cmp r3, #0 8014ec6: d009 beq.n 8014edc API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); 8014ec8: 687b ldr r3, [r7, #4] 8014eca: 6a5b ldr r3, [r3, #36] ; 0x24 8014ecc: 2b00 cmp r3, #0 8014ece: d005 beq.n 8014edc 8014ed0: 687b ldr r3, [r7, #4] 8014ed2: 6a5b ldr r3, [r3, #36] ; 0x24 8014ed4: 2200 movs r2, #0 8014ed6: 2102 movs r1, #2 8014ed8: 6878 ldr r0, [r7, #4] 8014eda: 4798 blx r3 } } #if LWIP_TCPIP_CORE_LOCKING if (delayed) 8014edc: 78fb ldrb r3, [r7, #3] 8014ede: 2b00 cmp r3, #0 8014ee0: d002 beq.n 8014ee8 #endif { /* wake up the application task */ sys_sem_signal(op_completed_sem); 8014ee2: 68b8 ldr r0, [r7, #8] 8014ee4: f00c fb12 bl 802150c } return ERR_OK; 8014ee8: 2300 movs r3, #0 8014eea: e03c b.n 8014f66 8014eec: 08023624 .word 0x08023624 8014ef0: 080238f8 .word 0x080238f8 8014ef4: 08023668 .word 0x08023668 8014ef8: 08023908 .word 0x08023908 8014efc: 08023928 .word 0x08023928 8014f00: 0802394c .word 0x0802394c 8014f04: 0802378c .word 0x0802378c } if (!close_finished) { 8014f08: 7d7b ldrb r3, [r7, #21] 8014f0a: 2b00 cmp r3, #0 8014f0c: d11e bne.n 8014f4c /* Closing failed and we want to wait: restore some of the callbacks */ /* Closing of listen pcb will never fail! */ LWIP_ASSERT("Closing a listen pcb may not fail!", (tpcb->state != LISTEN)); 8014f0e: 693b ldr r3, [r7, #16] 8014f10: 7d1b ldrb r3, [r3, #20] 8014f12: 2b01 cmp r3, #1 8014f14: d106 bne.n 8014f24 8014f16: 4b16 ldr r3, [pc, #88] ; (8014f70 ) 8014f18: f240 4241 movw r2, #1089 ; 0x441 8014f1c: 4915 ldr r1, [pc, #84] ; (8014f74 ) 8014f1e: 4816 ldr r0, [pc, #88] ; (8014f78 ) 8014f20: f00c fd32 bl 8021988 if (shut_tx) { 8014f24: 7b7b ldrb r3, [r7, #13] 8014f26: 2b00 cmp r3, #0 8014f28: d003 beq.n 8014f32 tcp_sent(tpcb, sent_tcp); 8014f2a: 4914 ldr r1, [pc, #80] ; (8014f7c ) 8014f2c: 6938 ldr r0, [r7, #16] 8014f2e: f004 fce7 bl 8019900 } /* when waiting for close, set up poll interval to 500ms */ tcp_poll(tpcb, poll_tcp, 1); 8014f32: 2201 movs r2, #1 8014f34: 4912 ldr r1, [pc, #72] ; (8014f80 ) 8014f36: 6938 ldr r0, [r7, #16] 8014f38: f004 fd3e bl 80199b8 tcp_err(tpcb, err_tcp); 8014f3c: 4911 ldr r1, [pc, #68] ; (8014f84 ) 8014f3e: 6938 ldr r0, [r7, #16] 8014f40: f004 fd00 bl 8019944 tcp_arg(tpcb, conn); 8014f44: 6879 ldr r1, [r7, #4] 8014f46: 6938 ldr r0, [r7, #16] 8014f48: f004 fca6 bl 8019898 /* don't restore recv callback: we don't want to receive any more data */ } /* If closing didn't succeed, we get called again either from poll_tcp or from sent_tcp */ LWIP_ASSERT("err != ERR_OK", err != ERR_OK); 8014f4c: f997 3017 ldrsb.w r3, [r7, #23] 8014f50: 2b00 cmp r3, #0 8014f52: d106 bne.n 8014f62 8014f54: 4b06 ldr r3, [pc, #24] ; (8014f70 ) 8014f56: f240 424d movw r2, #1101 ; 0x44d 8014f5a: 490b ldr r1, [pc, #44] ; (8014f88 ) 8014f5c: 4806 ldr r0, [pc, #24] ; (8014f78 ) 8014f5e: f00c fd13 bl 8021988 return err; 8014f62: f997 3017 ldrsb.w r3, [r7, #23] } 8014f66: 4618 mov r0, r3 8014f68: 3718 adds r7, #24 8014f6a: 46bd mov sp, r7 8014f6c: bd80 pop {r7, pc} 8014f6e: bf00 nop 8014f70: 08023624 .word 0x08023624 8014f74: 08023960 .word 0x08023960 8014f78: 08023668 .word 0x08023668 8014f7c: 080146a5 .word 0x080146a5 8014f80: 080145d9 .word 0x080145d9 8014f84: 08014751 .word 0x08014751 8014f88: 08023984 .word 0x08023984 08014f8c : * * @param m the api_msg pointing to the connection */ void lwip_netconn_do_delconn(void *m) { 8014f8c: b580 push {r7, lr} 8014f8e: b084 sub sp, #16 8014f90: af00 add r7, sp, #0 8014f92: 6078 str r0, [r7, #4] struct api_msg *msg = (struct api_msg *)m; 8014f94: 687b ldr r3, [r7, #4] 8014f96: 60fb str r3, [r7, #12] enum netconn_state state = msg->conn->state; 8014f98: 68fb ldr r3, [r7, #12] 8014f9a: 681b ldr r3, [r3, #0] 8014f9c: 785b ldrb r3, [r3, #1] 8014f9e: 72fb strb r3, [r7, #11] LWIP_ASSERT("netconn state error", /* this only happens for TCP netconns */ 8014fa0: 7afb ldrb r3, [r7, #11] 8014fa2: 2b00 cmp r3, #0 8014fa4: d00d beq.n 8014fc2 8014fa6: 68fb ldr r3, [r7, #12] 8014fa8: 681b ldr r3, [r3, #0] 8014faa: 781b ldrb r3, [r3, #0] 8014fac: f003 03f0 and.w r3, r3, #240 ; 0xf0 8014fb0: 2b10 cmp r3, #16 8014fb2: d006 beq.n 8014fc2 8014fb4: 4b60 ldr r3, [pc, #384] ; (8015138 ) 8014fb6: f240 425e movw r2, #1118 ; 0x45e 8014fba: 4960 ldr r1, [pc, #384] ; (801513c ) 8014fbc: 4860 ldr r0, [pc, #384] ; (8015140 ) 8014fbe: f00c fce3 bl 8021988 msg->conn->state = NETCONN_NONE; sys_sem_signal(op_completed_sem); } } #else /* LWIP_NETCONN_FULLDUPLEX */ if (((state != NETCONN_NONE) && 8014fc2: 7afb ldrb r3, [r7, #11] 8014fc4: 2b00 cmp r3, #0 8014fc6: d005 beq.n 8014fd4 8014fc8: 7afb ldrb r3, [r7, #11] 8014fca: 2b02 cmp r3, #2 8014fcc: d002 beq.n 8014fd4 (state != NETCONN_LISTEN) && 8014fce: 7afb ldrb r3, [r7, #11] 8014fd0: 2b03 cmp r3, #3 8014fd2: d109 bne.n 8014fe8 (state != NETCONN_CONNECT)) || 8014fd4: 7afb ldrb r3, [r7, #11] 8014fd6: 2b03 cmp r3, #3 8014fd8: d10a bne.n 8014ff0 ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) { 8014fda: 68fb ldr r3, [r7, #12] 8014fdc: 681b ldr r3, [r3, #0] 8014fde: 7f1b ldrb r3, [r3, #28] 8014fe0: f003 0304 and.w r3, r3, #4 8014fe4: 2b00 cmp r3, #0 8014fe6: d103 bne.n 8014ff0 /* This means either a blocking write or blocking connect is running (nonblocking write returns and sets state to NONE) */ msg->err = ERR_INPROGRESS; 8014fe8: 68fb ldr r3, [r7, #12] 8014fea: 22fb movs r2, #251 ; 0xfb 8014fec: 711a strb r2, [r3, #4] 8014fee: e097 b.n 8015120 } else #endif /* LWIP_NETCONN_FULLDUPLEX */ { LWIP_ASSERT("blocking connect in progress", 8014ff0: 7afb ldrb r3, [r7, #11] 8014ff2: 2b03 cmp r3, #3 8014ff4: d10d bne.n 8015012 8014ff6: 68fb ldr r3, [r7, #12] 8014ff8: 681b ldr r3, [r3, #0] 8014ffa: 7f1b ldrb r3, [r3, #28] 8014ffc: f003 0304 and.w r3, r3, #4 8015000: 2b00 cmp r3, #0 8015002: d106 bne.n 8015012 8015004: 4b4c ldr r3, [pc, #304] ; (8015138 ) 8015006: f240 427a movw r2, #1146 ; 0x47a 801500a: 494e ldr r1, [pc, #312] ; (8015144 ) 801500c: 484c ldr r0, [pc, #304] ; (8015140 ) 801500e: f00c fcbb bl 8021988 (state != NETCONN_CONNECT) || IN_NONBLOCKING_CONNECT(msg->conn)); msg->err = ERR_OK; 8015012: 68fb ldr r3, [r7, #12] 8015014: 2200 movs r2, #0 8015016: 711a strb r2, [r3, #4] #if LWIP_NETCONN_FULLDUPLEX /* Mark mboxes invalid */ netconn_mark_mbox_invalid(msg->conn); #else /* LWIP_NETCONN_FULLDUPLEX */ netconn_drain(msg->conn); 8015018: 68fb ldr r3, [r7, #12] 801501a: 681b ldr r3, [r3, #0] 801501c: 4618 mov r0, r3 801501e: f7ff fdcd bl 8014bbc #endif /* LWIP_NETCONN_FULLDUPLEX */ if (msg->conn->pcb.tcp != NULL) { 8015022: 68fb ldr r3, [r7, #12] 8015024: 681b ldr r3, [r3, #0] 8015026: 685b ldr r3, [r3, #4] 8015028: 2b00 cmp r3, #0 801502a: d05f beq.n 80150ec switch (NETCONNTYPE_GROUP(msg->conn->type)) { 801502c: 68fb ldr r3, [r7, #12] 801502e: 681b ldr r3, [r3, #0] 8015030: 781b ldrb r3, [r3, #0] 8015032: f003 03f0 and.w r3, r3, #240 ; 0xf0 8015036: 2b10 cmp r3, #16 8015038: d00d beq.n 8015056 801503a: 2b20 cmp r3, #32 801503c: d151 bne.n 80150e2 raw_remove(msg->conn->pcb.raw); break; #endif /* LWIP_RAW */ #if LWIP_UDP case NETCONN_UDP: msg->conn->pcb.udp->recv_arg = NULL; 801503e: 68fb ldr r3, [r7, #12] 8015040: 681b ldr r3, [r3, #0] 8015042: 685b ldr r3, [r3, #4] 8015044: 2200 movs r2, #0 8015046: 61da str r2, [r3, #28] udp_remove(msg->conn->pcb.udp); 8015048: 68fb ldr r3, [r7, #12] 801504a: 681b ldr r3, [r3, #0] 801504c: 685b ldr r3, [r3, #4] 801504e: 4618 mov r0, r3 8015050: f009 fd88 bl 801eb64 break; 8015054: e046 b.n 80150e4 #endif /* LWIP_UDP */ #if LWIP_TCP case NETCONN_TCP: LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL); 8015056: 68fb ldr r3, [r7, #12] 8015058: 681b ldr r3, [r3, #0] 801505a: 6a1b ldr r3, [r3, #32] 801505c: 2b00 cmp r3, #0 801505e: d006 beq.n 801506e 8015060: 4b35 ldr r3, [pc, #212] ; (8015138 ) 8015062: f240 4294 movw r2, #1172 ; 0x494 8015066: 4938 ldr r1, [pc, #224] ; (8015148 ) 8015068: 4835 ldr r0, [pc, #212] ; (8015140 ) 801506a: f00c fc8d bl 8021988 msg->conn->state = NETCONN_CLOSE; 801506e: 68fb ldr r3, [r7, #12] 8015070: 681b ldr r3, [r3, #0] 8015072: 2204 movs r2, #4 8015074: 705a strb r2, [r3, #1] msg->msg.sd.shut = NETCONN_SHUT_RDWR; 8015076: 68fb ldr r3, [r7, #12] 8015078: 2203 movs r2, #3 801507a: 721a strb r2, [r3, #8] msg->conn->current_msg = msg; 801507c: 68fb ldr r3, [r7, #12] 801507e: 681b ldr r3, [r3, #0] 8015080: 68fa ldr r2, [r7, #12] 8015082: 621a str r2, [r3, #32] #if LWIP_TCPIP_CORE_LOCKING if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) { 8015084: 68fb ldr r3, [r7, #12] 8015086: 681b ldr r3, [r3, #0] 8015088: 2100 movs r1, #0 801508a: 4618 mov r0, r3 801508c: f7ff fe14 bl 8014cb8 8015090: 4603 mov r3, r0 8015092: 2b00 cmp r3, #0 8015094: d04b beq.n 801512e LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE); 8015096: 68fb ldr r3, [r7, #12] 8015098: 681b ldr r3, [r3, #0] 801509a: 785b ldrb r3, [r3, #1] 801509c: 2b04 cmp r3, #4 801509e: d006 beq.n 80150ae 80150a0: 4b25 ldr r3, [pc, #148] ; (8015138 ) 80150a2: f240 429a movw r2, #1178 ; 0x49a 80150a6: 4929 ldr r1, [pc, #164] ; (801514c ) 80150a8: 4825 ldr r0, [pc, #148] ; (8015140 ) 80150aa: f00c fc6d bl 8021988 UNLOCK_TCPIP_CORE(); 80150ae: 4828 ldr r0, [pc, #160] ; (8015150 ) 80150b0: f00c fa9d bl 80215ee sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); 80150b4: 68fb ldr r3, [r7, #12] 80150b6: 681b ldr r3, [r3, #0] 80150b8: 330c adds r3, #12 80150ba: 2100 movs r1, #0 80150bc: 4618 mov r0, r3 80150be: f00c f9f4 bl 80214aa LOCK_TCPIP_CORE(); 80150c2: 4823 ldr r0, [pc, #140] ; (8015150 ) 80150c4: f00c fa84 bl 80215d0 LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); 80150c8: 68fb ldr r3, [r7, #12] 80150ca: 681b ldr r3, [r3, #0] 80150cc: 785b ldrb r3, [r3, #1] 80150ce: 2b00 cmp r3, #0 80150d0: d02d beq.n 801512e 80150d2: 4b19 ldr r3, [pc, #100] ; (8015138 ) 80150d4: f240 429e movw r2, #1182 ; 0x49e 80150d8: 491c ldr r1, [pc, #112] ; (801514c ) 80150da: 4819 ldr r0, [pc, #100] ; (8015140 ) 80150dc: f00c fc54 bl 8021988 #else /* LWIP_TCPIP_CORE_LOCKING */ lwip_netconn_do_close_internal(msg->conn); #endif /* LWIP_TCPIP_CORE_LOCKING */ /* API_EVENT is called inside lwip_netconn_do_close_internal, before releasing the application thread, so we can return at this point! */ return; 80150e0: e025 b.n 801512e #endif /* LWIP_TCP */ default: break; 80150e2: bf00 nop } msg->conn->pcb.tcp = NULL; 80150e4: 68fb ldr r3, [r7, #12] 80150e6: 681b ldr r3, [r3, #0] 80150e8: 2200 movs r2, #0 80150ea: 605a str r2, [r3, #4] } /* tcp netconns don't come here! */ /* @todo: this lets select make the socket readable and writable, which is wrong! errfd instead? */ API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0); 80150ec: 68fb ldr r3, [r7, #12] 80150ee: 681b ldr r3, [r3, #0] 80150f0: 6a5b ldr r3, [r3, #36] ; 0x24 80150f2: 2b00 cmp r3, #0 80150f4: d007 beq.n 8015106 80150f6: 68fb ldr r3, [r7, #12] 80150f8: 681b ldr r3, [r3, #0] 80150fa: 6a5b ldr r3, [r3, #36] ; 0x24 80150fc: 68fa ldr r2, [r7, #12] 80150fe: 6810 ldr r0, [r2, #0] 8015100: 2200 movs r2, #0 8015102: 2100 movs r1, #0 8015104: 4798 blx r3 API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0); 8015106: 68fb ldr r3, [r7, #12] 8015108: 681b ldr r3, [r3, #0] 801510a: 6a5b ldr r3, [r3, #36] ; 0x24 801510c: 2b00 cmp r3, #0 801510e: d007 beq.n 8015120 8015110: 68fb ldr r3, [r7, #12] 8015112: 681b ldr r3, [r3, #0] 8015114: 6a5b ldr r3, [r3, #36] ; 0x24 8015116: 68fa ldr r2, [r7, #12] 8015118: 6810 ldr r0, [r2, #0] 801511a: 2200 movs r2, #0 801511c: 2102 movs r1, #2 801511e: 4798 blx r3 } if (sys_sem_valid(LWIP_API_MSG_SEM(msg))) { 8015120: 68fb ldr r3, [r7, #12] 8015122: 681b ldr r3, [r3, #0] 8015124: 330c adds r3, #12 8015126: 4618 mov r0, r3 8015128: f00c fa0a bl 8021540 801512c: e000 b.n 8015130 return; 801512e: bf00 nop TCPIP_APIMSG_ACK(msg); } } 8015130: 3710 adds r7, #16 8015132: 46bd mov sp, r7 8015134: bd80 pop {r7, pc} 8015136: bf00 nop 8015138: 08023624 .word 0x08023624 801513c: 08023994 .word 0x08023994 8015140: 08023668 .word 0x08023668 8015144: 080239a8 .word 0x080239a8 8015148: 080239c8 .word 0x080239c8 801514c: 080239e4 .word 0x080239e4 8015150: 2401397c .word 0x2401397c 08015154 : * @param m the api_msg pointing to the connection and containing * the IP address and port to bind to */ void lwip_netconn_do_bind(void *m) { 8015154: b580 push {r7, lr} 8015156: b084 sub sp, #16 8015158: af00 add r7, sp, #0 801515a: 6078 str r0, [r7, #4] struct api_msg *msg = (struct api_msg *)m; 801515c: 687b ldr r3, [r7, #4] 801515e: 60bb str r3, [r7, #8] err_t err; if (msg->conn->pcb.tcp != NULL) { 8015160: 68bb ldr r3, [r7, #8] 8015162: 681b ldr r3, [r3, #0] 8015164: 685b ldr r3, [r3, #4] 8015166: 2b00 cmp r3, #0 8015168: d025 beq.n 80151b6 switch (NETCONNTYPE_GROUP(msg->conn->type)) { 801516a: 68bb ldr r3, [r7, #8] 801516c: 681b ldr r3, [r3, #0] 801516e: 781b ldrb r3, [r3, #0] 8015170: f003 03f0 and.w r3, r3, #240 ; 0xf0 8015174: 2b10 cmp r3, #16 8015176: d00e beq.n 8015196 8015178: 2b20 cmp r3, #32 801517a: d119 bne.n 80151b0 err = raw_bind(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr)); break; #endif /* LWIP_RAW */ #if LWIP_UDP case NETCONN_UDP: err = udp_bind(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); 801517c: 68bb ldr r3, [r7, #8] 801517e: 681b ldr r3, [r3, #0] 8015180: 6858 ldr r0, [r3, #4] 8015182: 68bb ldr r3, [r7, #8] 8015184: 6899 ldr r1, [r3, #8] 8015186: 68bb ldr r3, [r7, #8] 8015188: 899b ldrh r3, [r3, #12] 801518a: 461a mov r2, r3 801518c: f009 fbd4 bl 801e938 8015190: 4603 mov r3, r0 8015192: 73fb strb r3, [r7, #15] break; 8015194: e011 b.n 80151ba #endif /* LWIP_UDP */ #if LWIP_TCP case NETCONN_TCP: err = tcp_bind(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); 8015196: 68bb ldr r3, [r7, #8] 8015198: 681b ldr r3, [r3, #0] 801519a: 6858 ldr r0, [r3, #4] 801519c: 68bb ldr r3, [r7, #8] 801519e: 6899 ldr r1, [r3, #8] 80151a0: 68bb ldr r3, [r7, #8] 80151a2: 899b ldrh r3, [r3, #12] 80151a4: 461a mov r2, r3 80151a6: f003 faa3 bl 80186f0 80151aa: 4603 mov r3, r0 80151ac: 73fb strb r3, [r7, #15] break; 80151ae: e004 b.n 80151ba #endif /* LWIP_TCP */ default: err = ERR_VAL; 80151b0: 23fa movs r3, #250 ; 0xfa 80151b2: 73fb strb r3, [r7, #15] break; 80151b4: e001 b.n 80151ba } } else { err = ERR_VAL; 80151b6: 23fa movs r3, #250 ; 0xfa 80151b8: 73fb strb r3, [r7, #15] } msg->err = err; 80151ba: 68bb ldr r3, [r7, #8] 80151bc: 7bfa ldrb r2, [r7, #15] 80151be: 711a strb r2, [r3, #4] TCPIP_APIMSG_ACK(msg); } 80151c0: bf00 nop 80151c2: 3710 adds r7, #16 80151c4: 46bd mov sp, r7 80151c6: bd80 pop {r7, pc} 080151c8 : * * @see tcp.h (struct tcp_pcb.connected) for parameters and return values */ static err_t lwip_netconn_do_connected(void *arg, struct tcp_pcb *pcb, err_t err) { 80151c8: b580 push {r7, lr} 80151ca: b088 sub sp, #32 80151cc: af00 add r7, sp, #0 80151ce: 60f8 str r0, [r7, #12] 80151d0: 60b9 str r1, [r7, #8] 80151d2: 4613 mov r3, r2 80151d4: 71fb strb r3, [r7, #7] struct netconn *conn; int was_blocking; sys_sem_t *op_completed_sem = NULL; 80151d6: 2300 movs r3, #0 80151d8: 61fb str r3, [r7, #28] LWIP_UNUSED_ARG(pcb); conn = (struct netconn *)arg; 80151da: 68fb ldr r3, [r7, #12] 80151dc: 61bb str r3, [r7, #24] if (conn == NULL) { 80151de: 69bb ldr r3, [r7, #24] 80151e0: 2b00 cmp r3, #0 80151e2: d102 bne.n 80151ea return ERR_VAL; 80151e4: f06f 0305 mvn.w r3, #5 80151e8: e070 b.n 80152cc } LWIP_ASSERT("conn->state == NETCONN_CONNECT", conn->state == NETCONN_CONNECT); 80151ea: 69bb ldr r3, [r7, #24] 80151ec: 785b ldrb r3, [r3, #1] 80151ee: 2b03 cmp r3, #3 80151f0: d006 beq.n 8015200 80151f2: 4b38 ldr r3, [pc, #224] ; (80152d4 ) 80151f4: f240 5223 movw r2, #1315 ; 0x523 80151f8: 4937 ldr r1, [pc, #220] ; (80152d8 ) 80151fa: 4838 ldr r0, [pc, #224] ; (80152dc ) 80151fc: f00c fbc4 bl 8021988 LWIP_ASSERT("(conn->current_msg != NULL) || conn->in_non_blocking_connect", 8015200: 69bb ldr r3, [r7, #24] 8015202: 6a1b ldr r3, [r3, #32] 8015204: 2b00 cmp r3, #0 8015206: d10c bne.n 8015222 8015208: 69bb ldr r3, [r7, #24] 801520a: 7f1b ldrb r3, [r3, #28] 801520c: f003 0304 and.w r3, r3, #4 8015210: 2b00 cmp r3, #0 8015212: d106 bne.n 8015222 8015214: 4b2f ldr r3, [pc, #188] ; (80152d4 ) 8015216: f240 5224 movw r2, #1316 ; 0x524 801521a: 4931 ldr r1, [pc, #196] ; (80152e0 ) 801521c: 482f ldr r0, [pc, #188] ; (80152dc ) 801521e: f00c fbb3 bl 8021988 (conn->current_msg != NULL) || IN_NONBLOCKING_CONNECT(conn)); if (conn->current_msg != NULL) { 8015222: 69bb ldr r3, [r7, #24] 8015224: 6a1b ldr r3, [r3, #32] 8015226: 2b00 cmp r3, #0 8015228: d008 beq.n 801523c conn->current_msg->err = err; 801522a: 69bb ldr r3, [r7, #24] 801522c: 6a1b ldr r3, [r3, #32] 801522e: 79fa ldrb r2, [r7, #7] 8015230: 711a strb r2, [r3, #4] op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); 8015232: 69bb ldr r3, [r7, #24] 8015234: 6a1b ldr r3, [r3, #32] 8015236: 681b ldr r3, [r3, #0] 8015238: 330c adds r3, #12 801523a: 61fb str r3, [r7, #28] } if ((NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) && (err == ERR_OK)) { 801523c: 69bb ldr r3, [r7, #24] 801523e: 781b ldrb r3, [r3, #0] 8015240: f003 03f0 and.w r3, r3, #240 ; 0xf0 8015244: 2b10 cmp r3, #16 8015246: d106 bne.n 8015256 8015248: f997 3007 ldrsb.w r3, [r7, #7] 801524c: 2b00 cmp r3, #0 801524e: d102 bne.n 8015256 setup_tcp(conn); 8015250: 69b8 ldr r0, [r7, #24] 8015252: f7ff fb53 bl 80148fc } was_blocking = !IN_NONBLOCKING_CONNECT(conn); 8015256: 69bb ldr r3, [r7, #24] 8015258: 7f1b ldrb r3, [r3, #28] 801525a: f003 0304 and.w r3, r3, #4 801525e: 2b00 cmp r3, #0 8015260: bf0c ite eq 8015262: 2301 moveq r3, #1 8015264: 2300 movne r3, #0 8015266: b2db uxtb r3, r3 8015268: 617b str r3, [r7, #20] SET_NONBLOCKING_CONNECT(conn, 0); 801526a: 69bb ldr r3, [r7, #24] 801526c: 7f1b ldrb r3, [r3, #28] 801526e: f023 0304 bic.w r3, r3, #4 8015272: b2da uxtb r2, r3 8015274: 69bb ldr r3, [r7, #24] 8015276: 771a strb r2, [r3, #28] LWIP_ASSERT("blocking connect state error", 8015278: 697b ldr r3, [r7, #20] 801527a: 2b00 cmp r3, #0 801527c: d002 beq.n 8015284 801527e: 69fb ldr r3, [r7, #28] 8015280: 2b00 cmp r3, #0 8015282: d10c bne.n 801529e 8015284: 697b ldr r3, [r7, #20] 8015286: 2b00 cmp r3, #0 8015288: d102 bne.n 8015290 801528a: 69fb ldr r3, [r7, #28] 801528c: 2b00 cmp r3, #0 801528e: d006 beq.n 801529e 8015290: 4b10 ldr r3, [pc, #64] ; (80152d4 ) 8015292: f44f 62a6 mov.w r2, #1328 ; 0x530 8015296: 4913 ldr r1, [pc, #76] ; (80152e4 ) 8015298: 4810 ldr r0, [pc, #64] ; (80152dc ) 801529a: f00c fb75 bl 8021988 (was_blocking && op_completed_sem != NULL) || (!was_blocking && op_completed_sem == NULL)); conn->current_msg = NULL; 801529e: 69bb ldr r3, [r7, #24] 80152a0: 2200 movs r2, #0 80152a2: 621a str r2, [r3, #32] conn->state = NETCONN_NONE; 80152a4: 69bb ldr r3, [r7, #24] 80152a6: 2200 movs r2, #0 80152a8: 705a strb r2, [r3, #1] API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); 80152aa: 69bb ldr r3, [r7, #24] 80152ac: 6a5b ldr r3, [r3, #36] ; 0x24 80152ae: 2b00 cmp r3, #0 80152b0: d005 beq.n 80152be 80152b2: 69bb ldr r3, [r7, #24] 80152b4: 6a5b ldr r3, [r3, #36] ; 0x24 80152b6: 2200 movs r2, #0 80152b8: 2102 movs r1, #2 80152ba: 69b8 ldr r0, [r7, #24] 80152bc: 4798 blx r3 if (was_blocking) { 80152be: 697b ldr r3, [r7, #20] 80152c0: 2b00 cmp r3, #0 80152c2: d002 beq.n 80152ca sys_sem_signal(op_completed_sem); 80152c4: 69f8 ldr r0, [r7, #28] 80152c6: f00c f921 bl 802150c } return ERR_OK; 80152ca: 2300 movs r3, #0 } 80152cc: 4618 mov r0, r3 80152ce: 3720 adds r7, #32 80152d0: 46bd mov sp, r7 80152d2: bd80 pop {r7, pc} 80152d4: 08023624 .word 0x08023624 80152d8: 080239ec .word 0x080239ec 80152dc: 08023668 .word 0x08023668 80152e0: 08023a0c .word 0x08023a0c 80152e4: 08023a4c .word 0x08023a4c 080152e8 : * @param m the api_msg pointing to the connection and containing * the IP address and port to connect to */ void lwip_netconn_do_connect(void *m) { 80152e8: b580 push {r7, lr} 80152ea: b086 sub sp, #24 80152ec: af00 add r7, sp, #0 80152ee: 6078 str r0, [r7, #4] struct api_msg *msg = (struct api_msg *)m; 80152f0: 687b ldr r3, [r7, #4] 80152f2: 613b str r3, [r7, #16] err_t err; if (msg->conn->pcb.tcp == NULL) { 80152f4: 693b ldr r3, [r7, #16] 80152f6: 681b ldr r3, [r3, #0] 80152f8: 685b ldr r3, [r3, #4] 80152fa: 2b00 cmp r3, #0 80152fc: d102 bne.n 8015304 /* This may happen when calling netconn_connect() a second time */ err = ERR_CLSD; 80152fe: 23f1 movs r3, #241 ; 0xf1 8015300: 75fb strb r3, [r7, #23] 8015302: e09b b.n 801543c } else { switch (NETCONNTYPE_GROUP(msg->conn->type)) { 8015304: 693b ldr r3, [r7, #16] 8015306: 681b ldr r3, [r3, #0] 8015308: 781b ldrb r3, [r3, #0] 801530a: f003 03f0 and.w r3, r3, #240 ; 0xf0 801530e: 2b10 cmp r3, #16 8015310: d00f beq.n 8015332 8015312: 2b20 cmp r3, #32 8015314: f040 8087 bne.w 8015426 err = raw_connect(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr)); break; #endif /* LWIP_RAW */ #if LWIP_UDP case NETCONN_UDP: err = udp_connect(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); 8015318: 693b ldr r3, [r7, #16] 801531a: 681b ldr r3, [r3, #0] 801531c: 6858 ldr r0, [r3, #4] 801531e: 693b ldr r3, [r7, #16] 8015320: 6899 ldr r1, [r3, #8] 8015322: 693b ldr r3, [r7, #16] 8015324: 899b ldrh r3, [r3, #12] 8015326: 461a mov r2, r3 8015328: f009 fb8e bl 801ea48 801532c: 4603 mov r3, r0 801532e: 75fb strb r3, [r7, #23] break; 8015330: e084 b.n 801543c #endif /* LWIP_UDP */ #if LWIP_TCP case NETCONN_TCP: /* Prevent connect while doing any other action. */ if (msg->conn->state == NETCONN_CONNECT) { 8015332: 693b ldr r3, [r7, #16] 8015334: 681b ldr r3, [r3, #0] 8015336: 785b ldrb r3, [r3, #1] 8015338: 2b03 cmp r3, #3 801533a: d102 bne.n 8015342 err = ERR_ALREADY; 801533c: 23f7 movs r3, #247 ; 0xf7 801533e: 75fb strb r3, [r7, #23] #endif /* LWIP_TCPIP_CORE_LOCKING */ return; } } } break; 8015340: e07b b.n 801543a } else if (msg->conn->state != NETCONN_NONE) { 8015342: 693b ldr r3, [r7, #16] 8015344: 681b ldr r3, [r3, #0] 8015346: 785b ldrb r3, [r3, #1] 8015348: 2b00 cmp r3, #0 801534a: d002 beq.n 8015352 err = ERR_ISCONN; 801534c: 23f6 movs r3, #246 ; 0xf6 801534e: 75fb strb r3, [r7, #23] break; 8015350: e073 b.n 801543a setup_tcp(msg->conn); 8015352: 693b ldr r3, [r7, #16] 8015354: 681b ldr r3, [r3, #0] 8015356: 4618 mov r0, r3 8015358: f7ff fad0 bl 80148fc err = tcp_connect(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), 801535c: 693b ldr r3, [r7, #16] 801535e: 681b ldr r3, [r3, #0] 8015360: 6858 ldr r0, [r3, #4] 8015362: 693b ldr r3, [r7, #16] 8015364: 6899 ldr r1, [r3, #8] 8015366: 693b ldr r3, [r7, #16] 8015368: 899a ldrh r2, [r3, #12] 801536a: 4b38 ldr r3, [pc, #224] ; (801544c ) 801536c: f003 fb4a bl 8018a04 8015370: 4603 mov r3, r0 8015372: 75fb strb r3, [r7, #23] if (err == ERR_OK) { 8015374: f997 3017 ldrsb.w r3, [r7, #23] 8015378: 2b00 cmp r3, #0 801537a: d15e bne.n 801543a u8_t non_blocking = netconn_is_nonblocking(msg->conn); 801537c: 693b ldr r3, [r7, #16] 801537e: 681b ldr r3, [r3, #0] 8015380: 7f1b ldrb r3, [r3, #28] 8015382: f003 0302 and.w r3, r3, #2 8015386: 2b00 cmp r3, #0 8015388: bf14 ite ne 801538a: 2301 movne r3, #1 801538c: 2300 moveq r3, #0 801538e: b2db uxtb r3, r3 8015390: 73fb strb r3, [r7, #15] msg->conn->state = NETCONN_CONNECT; 8015392: 693b ldr r3, [r7, #16] 8015394: 681b ldr r3, [r3, #0] 8015396: 2203 movs r2, #3 8015398: 705a strb r2, [r3, #1] SET_NONBLOCKING_CONNECT(msg->conn, non_blocking); 801539a: 7bfb ldrb r3, [r7, #15] 801539c: 2b00 cmp r3, #0 801539e: d009 beq.n 80153b4 80153a0: 693b ldr r3, [r7, #16] 80153a2: 681b ldr r3, [r3, #0] 80153a4: 7f1a ldrb r2, [r3, #28] 80153a6: 693b ldr r3, [r7, #16] 80153a8: 681b ldr r3, [r3, #0] 80153aa: f042 0204 orr.w r2, r2, #4 80153ae: b2d2 uxtb r2, r2 80153b0: 771a strb r2, [r3, #28] 80153b2: e008 b.n 80153c6 80153b4: 693b ldr r3, [r7, #16] 80153b6: 681b ldr r3, [r3, #0] 80153b8: 7f1a ldrb r2, [r3, #28] 80153ba: 693b ldr r3, [r7, #16] 80153bc: 681b ldr r3, [r3, #0] 80153be: f022 0204 bic.w r2, r2, #4 80153c2: b2d2 uxtb r2, r2 80153c4: 771a strb r2, [r3, #28] if (non_blocking) { 80153c6: 7bfb ldrb r3, [r7, #15] 80153c8: 2b00 cmp r3, #0 80153ca: d002 beq.n 80153d2 err = ERR_INPROGRESS; 80153cc: 23fb movs r3, #251 ; 0xfb 80153ce: 75fb strb r3, [r7, #23] break; 80153d0: e033 b.n 801543a msg->conn->current_msg = msg; 80153d2: 693b ldr r3, [r7, #16] 80153d4: 681b ldr r3, [r3, #0] 80153d6: 693a ldr r2, [r7, #16] 80153d8: 621a str r2, [r3, #32] LWIP_ASSERT("state!", msg->conn->state == NETCONN_CONNECT); 80153da: 693b ldr r3, [r7, #16] 80153dc: 681b ldr r3, [r3, #0] 80153de: 785b ldrb r3, [r3, #1] 80153e0: 2b03 cmp r3, #3 80153e2: d006 beq.n 80153f2 80153e4: 4b1a ldr r3, [pc, #104] ; (8015450 ) 80153e6: f44f 62ae mov.w r2, #1392 ; 0x570 80153ea: 491a ldr r1, [pc, #104] ; (8015454 ) 80153ec: 481a ldr r0, [pc, #104] ; (8015458 ) 80153ee: f00c facb bl 8021988 UNLOCK_TCPIP_CORE(); 80153f2: 481a ldr r0, [pc, #104] ; (801545c ) 80153f4: f00c f8fb bl 80215ee sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); 80153f8: 693b ldr r3, [r7, #16] 80153fa: 681b ldr r3, [r3, #0] 80153fc: 330c adds r3, #12 80153fe: 2100 movs r1, #0 8015400: 4618 mov r0, r3 8015402: f00c f852 bl 80214aa LOCK_TCPIP_CORE(); 8015406: 4815 ldr r0, [pc, #84] ; (801545c ) 8015408: f00c f8e2 bl 80215d0 LWIP_ASSERT("state!", msg->conn->state != NETCONN_CONNECT); 801540c: 693b ldr r3, [r7, #16] 801540e: 681b ldr r3, [r3, #0] 8015410: 785b ldrb r3, [r3, #1] 8015412: 2b03 cmp r3, #3 8015414: d116 bne.n 8015444 8015416: 4b0e ldr r3, [pc, #56] ; (8015450 ) 8015418: f240 5274 movw r2, #1396 ; 0x574 801541c: 490d ldr r1, [pc, #52] ; (8015454 ) 801541e: 480e ldr r0, [pc, #56] ; (8015458 ) 8015420: f00c fab2 bl 8021988 return; 8015424: e00e b.n 8015444 #endif /* LWIP_TCP */ default: LWIP_ERROR("Invalid netconn type", 0, do { 8015426: 4b0a ldr r3, [pc, #40] ; (8015450 ) 8015428: f240 527d movw r2, #1405 ; 0x57d 801542c: 490c ldr r1, [pc, #48] ; (8015460 ) 801542e: 480a ldr r0, [pc, #40] ; (8015458 ) 8015430: f00c faaa bl 8021988 8015434: 23fa movs r3, #250 ; 0xfa 8015436: 75fb strb r3, [r7, #23] err = ERR_VAL; } while (0)); break; 8015438: e000 b.n 801543c break; 801543a: bf00 nop } } msg->err = err; 801543c: 693b ldr r3, [r7, #16] 801543e: 7dfa ldrb r2, [r7, #23] 8015440: 711a strb r2, [r3, #4] 8015442: e000 b.n 8015446 return; 8015444: bf00 nop /* For all other protocols, netconn_connect() calls netconn_apimsg(), so use TCPIP_APIMSG_ACK() here. */ TCPIP_APIMSG_ACK(msg); } 8015446: 3718 adds r7, #24 8015448: 46bd mov sp, r7 801544a: bd80 pop {r7, pc} 801544c: 080151c9 .word 0x080151c9 8015450: 08023624 .word 0x08023624 8015454: 080239e4 .word 0x080239e4 8015458: 08023668 .word 0x08023668 801545c: 2401397c .word 0x2401397c 8015460: 08023a6c .word 0x08023a6c 08015464 : * * @param m the api_msg pointing to the connection */ void lwip_netconn_do_recv(void *m) { 8015464: b580 push {r7, lr} 8015466: b086 sub sp, #24 8015468: af00 add r7, sp, #0 801546a: 6078 str r0, [r7, #4] struct api_msg *msg = (struct api_msg *)m; 801546c: 687b ldr r3, [r7, #4] 801546e: 613b str r3, [r7, #16] msg->err = ERR_OK; 8015470: 693b ldr r3, [r7, #16] 8015472: 2200 movs r2, #0 8015474: 711a strb r2, [r3, #4] if (msg->conn->pcb.tcp != NULL) { 8015476: 693b ldr r3, [r7, #16] 8015478: 681b ldr r3, [r3, #0] 801547a: 685b ldr r3, [r3, #4] 801547c: 2b00 cmp r3, #0 801547e: d022 beq.n 80154c6 if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { 8015480: 693b ldr r3, [r7, #16] 8015482: 681b ldr r3, [r3, #0] 8015484: 781b ldrb r3, [r3, #0] 8015486: f003 03f0 and.w r3, r3, #240 ; 0xf0 801548a: 2b10 cmp r3, #16 801548c: d11b bne.n 80154c6 size_t remaining = msg->msg.r.len; 801548e: 693b ldr r3, [r7, #16] 8015490: 689b ldr r3, [r3, #8] 8015492: 617b str r3, [r7, #20] do { u16_t recved = (u16_t)((remaining > 0xffff) ? 0xffff : remaining); 8015494: 697b ldr r3, [r7, #20] 8015496: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 801549a: d202 bcs.n 80154a2 801549c: 697b ldr r3, [r7, #20] 801549e: b29b uxth r3, r3 80154a0: e001 b.n 80154a6 80154a2: f64f 73ff movw r3, #65535 ; 0xffff 80154a6: 81fb strh r3, [r7, #14] tcp_recved(msg->conn->pcb.tcp, recved); 80154a8: 693b ldr r3, [r7, #16] 80154aa: 681b ldr r3, [r3, #0] 80154ac: 685b ldr r3, [r3, #4] 80154ae: 89fa ldrh r2, [r7, #14] 80154b0: 4611 mov r1, r2 80154b2: 4618 mov r0, r3 80154b4: f003 fa0e bl 80188d4 remaining -= recved; 80154b8: 89fb ldrh r3, [r7, #14] 80154ba: 697a ldr r2, [r7, #20] 80154bc: 1ad3 subs r3, r2, r3 80154be: 617b str r3, [r7, #20] } while (remaining != 0); 80154c0: 697b ldr r3, [r7, #20] 80154c2: 2b00 cmp r3, #0 80154c4: d1e6 bne.n 8015494 } } TCPIP_APIMSG_ACK(msg); } 80154c6: bf00 nop 80154c8: 3718 adds r7, #24 80154ca: 46bd mov sp, r7 80154cc: bd80 pop {r7, pc} ... 080154d0 : * @return ERR_OK * ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished */ static err_t lwip_netconn_do_writemore(struct netconn *conn WRITE_DELAYED_PARAM) { 80154d0: b580 push {r7, lr} 80154d2: b088 sub sp, #32 80154d4: af00 add r7, sp, #0 80154d6: 6078 str r0, [r7, #4] 80154d8: 460b mov r3, r1 80154da: 70fb strb r3, [r7, #3] err_t err; const void *dataptr; u16_t len, available; u8_t write_finished = 0; 80154dc: 2300 movs r3, #0 80154de: 76fb strb r3, [r7, #27] size_t diff; u8_t dontblock; u8_t apiflags; u8_t write_more; LWIP_ASSERT("conn != NULL", conn != NULL); 80154e0: 687b ldr r3, [r7, #4] 80154e2: 2b00 cmp r3, #0 80154e4: d106 bne.n 80154f4 80154e6: 4b96 ldr r3, [pc, #600] ; (8015740 ) 80154e8: f240 6273 movw r2, #1651 ; 0x673 80154ec: 4995 ldr r1, [pc, #596] ; (8015744 ) 80154ee: 4896 ldr r0, [pc, #600] ; (8015748 ) 80154f0: f00c fa4a bl 8021988 LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE)); 80154f4: 687b ldr r3, [r7, #4] 80154f6: 785b ldrb r3, [r3, #1] 80154f8: 2b01 cmp r3, #1 80154fa: d006 beq.n 801550a 80154fc: 4b90 ldr r3, [pc, #576] ; (8015740 ) 80154fe: f240 6274 movw r2, #1652 ; 0x674 8015502: 4992 ldr r1, [pc, #584] ; (801574c ) 8015504: 4890 ldr r0, [pc, #576] ; (8015748 ) 8015506: f00c fa3f bl 8021988 LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); 801550a: 687b ldr r3, [r7, #4] 801550c: 6a1b ldr r3, [r3, #32] 801550e: 2b00 cmp r3, #0 8015510: d106 bne.n 8015520 8015512: 4b8b ldr r3, [pc, #556] ; (8015740 ) 8015514: f240 6275 movw r2, #1653 ; 0x675 8015518: 498d ldr r1, [pc, #564] ; (8015750 ) 801551a: 488b ldr r0, [pc, #556] ; (8015748 ) 801551c: f00c fa34 bl 8021988 LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL); 8015520: 687b ldr r3, [r7, #4] 8015522: 685b ldr r3, [r3, #4] 8015524: 2b00 cmp r3, #0 8015526: d106 bne.n 8015536 8015528: 4b85 ldr r3, [pc, #532] ; (8015740 ) 801552a: f240 6276 movw r2, #1654 ; 0x676 801552e: 4989 ldr r1, [pc, #548] ; (8015754 ) 8015530: 4885 ldr r0, [pc, #532] ; (8015748 ) 8015532: f00c fa29 bl 8021988 LWIP_ASSERT("conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len", 8015536: 687b ldr r3, [r7, #4] 8015538: 6a1b ldr r3, [r3, #32] 801553a: 699a ldr r2, [r3, #24] 801553c: 687b ldr r3, [r7, #4] 801553e: 6a1b ldr r3, [r3, #32] 8015540: 695b ldr r3, [r3, #20] 8015542: 429a cmp r2, r3 8015544: d306 bcc.n 8015554 8015546: 4b7e ldr r3, [pc, #504] ; (8015740 ) 8015548: f240 6277 movw r2, #1655 ; 0x677 801554c: 4982 ldr r1, [pc, #520] ; (8015758 ) 801554e: 487e ldr r0, [pc, #504] ; (8015748 ) 8015550: f00c fa1a bl 8021988 conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len); LWIP_ASSERT("conn->current_msg->msg.w.vector_cnt > 0", conn->current_msg->msg.w.vector_cnt > 0); 8015554: 687b ldr r3, [r7, #4] 8015556: 6a1b ldr r3, [r3, #32] 8015558: 899b ldrh r3, [r3, #12] 801555a: 2b00 cmp r3, #0 801555c: d106 bne.n 801556c 801555e: 4b78 ldr r3, [pc, #480] ; (8015740 ) 8015560: f240 6279 movw r2, #1657 ; 0x679 8015564: 497d ldr r1, [pc, #500] ; (801575c ) 8015566: 4878 ldr r0, [pc, #480] ; (8015748 ) 8015568: f00c fa0e bl 8021988 apiflags = conn->current_msg->msg.w.apiflags; 801556c: 687b ldr r3, [r7, #4] 801556e: 6a1b ldr r3, [r3, #32] 8015570: 7f1b ldrb r3, [r3, #28] 8015572: 76bb strb r3, [r7, #26] dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK); 8015574: 687b ldr r3, [r7, #4] 8015576: 7f1b ldrb r3, [r3, #28] 8015578: f003 0302 and.w r3, r3, #2 801557c: 2b00 cmp r3, #0 801557e: d104 bne.n 801558a 8015580: 7ebb ldrb r3, [r7, #26] 8015582: f003 0304 and.w r3, r3, #4 8015586: 2b00 cmp r3, #0 8015588: d001 beq.n 801558e 801558a: 2301 movs r3, #1 801558c: e000 b.n 8015590 801558e: 2300 movs r3, #0 8015590: 763b strb r3, [r7, #24] } } else #endif /* LWIP_SO_SNDTIMEO */ { do { dataptr = (const u8_t *)conn->current_msg->msg.w.vector->ptr + conn->current_msg->msg.w.vector_off; 8015592: 687b ldr r3, [r7, #4] 8015594: 6a1b ldr r3, [r3, #32] 8015596: 689b ldr r3, [r3, #8] 8015598: 681a ldr r2, [r3, #0] 801559a: 687b ldr r3, [r7, #4] 801559c: 6a1b ldr r3, [r3, #32] 801559e: 691b ldr r3, [r3, #16] 80155a0: 4413 add r3, r2 80155a2: 617b str r3, [r7, #20] diff = conn->current_msg->msg.w.vector->len - conn->current_msg->msg.w.vector_off; 80155a4: 687b ldr r3, [r7, #4] 80155a6: 6a1b ldr r3, [r3, #32] 80155a8: 689b ldr r3, [r3, #8] 80155aa: 685a ldr r2, [r3, #4] 80155ac: 687b ldr r3, [r7, #4] 80155ae: 6a1b ldr r3, [r3, #32] 80155b0: 691b ldr r3, [r3, #16] 80155b2: 1ad3 subs r3, r2, r3 80155b4: 613b str r3, [r7, #16] if (diff > 0xffffUL) { /* max_u16_t */ 80155b6: 693b ldr r3, [r7, #16] 80155b8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80155bc: d307 bcc.n 80155ce len = 0xffff; 80155be: f64f 73ff movw r3, #65535 ; 0xffff 80155c2: 83bb strh r3, [r7, #28] apiflags |= TCP_WRITE_FLAG_MORE; 80155c4: 7ebb ldrb r3, [r7, #26] 80155c6: f043 0302 orr.w r3, r3, #2 80155ca: 76bb strb r3, [r7, #26] 80155cc: e001 b.n 80155d2 } else { len = (u16_t)diff; 80155ce: 693b ldr r3, [r7, #16] 80155d0: 83bb strh r3, [r7, #28] } available = tcp_sndbuf(conn->pcb.tcp); 80155d2: 687b ldr r3, [r7, #4] 80155d4: 685b ldr r3, [r3, #4] 80155d6: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64 80155da: 81fb strh r3, [r7, #14] if (available < len) { 80155dc: 89fa ldrh r2, [r7, #14] 80155de: 8bbb ldrh r3, [r7, #28] 80155e0: 429a cmp r2, r3 80155e2: d216 bcs.n 8015612 /* don't try to write more than sendbuf */ len = available; 80155e4: 89fb ldrh r3, [r7, #14] 80155e6: 83bb strh r3, [r7, #28] if (dontblock) { 80155e8: 7e3b ldrb r3, [r7, #24] 80155ea: 2b00 cmp r3, #0 80155ec: d00d beq.n 801560a if (!len) { 80155ee: 8bbb ldrh r3, [r7, #28] 80155f0: 2b00 cmp r3, #0 80155f2: d10e bne.n 8015612 /* set error according to partial write or not */ err = (conn->current_msg->msg.w.offset == 0) ? ERR_WOULDBLOCK : ERR_OK; 80155f4: 687b ldr r3, [r7, #4] 80155f6: 6a1b ldr r3, [r3, #32] 80155f8: 699b ldr r3, [r3, #24] 80155fa: 2b00 cmp r3, #0 80155fc: d102 bne.n 8015604 80155fe: f06f 0306 mvn.w r3, #6 8015602: e000 b.n 8015606 8015604: 2300 movs r3, #0 8015606: 77fb strb r3, [r7, #31] goto err_mem; 8015608: e07d b.n 8015706 } } else { apiflags |= TCP_WRITE_FLAG_MORE; 801560a: 7ebb ldrb r3, [r7, #26] 801560c: f043 0302 orr.w r3, r3, #2 8015610: 76bb strb r3, [r7, #26] } } LWIP_ASSERT("lwip_netconn_do_writemore: invalid length!", 8015612: 687b ldr r3, [r7, #4] 8015614: 6a1b ldr r3, [r3, #32] 8015616: 691a ldr r2, [r3, #16] 8015618: 8bbb ldrh r3, [r7, #28] 801561a: 441a add r2, r3 801561c: 687b ldr r3, [r7, #4] 801561e: 6a1b ldr r3, [r3, #32] 8015620: 689b ldr r3, [r3, #8] 8015622: 685b ldr r3, [r3, #4] 8015624: 429a cmp r2, r3 8015626: d906 bls.n 8015636 8015628: 4b45 ldr r3, [pc, #276] ; (8015740 ) 801562a: f240 62a3 movw r2, #1699 ; 0x6a3 801562e: 494c ldr r1, [pc, #304] ; (8015760 ) 8015630: 4845 ldr r0, [pc, #276] ; (8015748 ) 8015632: f00c f9a9 bl 8021988 ((conn->current_msg->msg.w.vector_off + len) <= conn->current_msg->msg.w.vector->len)); /* we should loop around for more sending in the following cases: 1) We couldn't finish the current vector because of 16-bit size limitations. tcp_write() and tcp_sndbuf() both are limited to 16-bit sizes 2) We are sending the remainder of the current vector and have more */ if ((len == 0xffff && diff > 0xffffUL) || 8015636: 8bbb ldrh r3, [r7, #28] 8015638: f64f 72ff movw r2, #65535 ; 0xffff 801563c: 4293 cmp r3, r2 801563e: d103 bne.n 8015648 8015640: 693b ldr r3, [r7, #16] 8015642: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8015646: d209 bcs.n 801565c (len == (u16_t)diff && conn->current_msg->msg.w.vector_cnt > 1)) { 8015648: 693b ldr r3, [r7, #16] 801564a: b29b uxth r3, r3 if ((len == 0xffff && diff > 0xffffUL) || 801564c: 8bba ldrh r2, [r7, #28] 801564e: 429a cmp r2, r3 8015650: d10b bne.n 801566a (len == (u16_t)diff && conn->current_msg->msg.w.vector_cnt > 1)) { 8015652: 687b ldr r3, [r7, #4] 8015654: 6a1b ldr r3, [r3, #32] 8015656: 899b ldrh r3, [r3, #12] 8015658: 2b01 cmp r3, #1 801565a: d906 bls.n 801566a write_more = 1; 801565c: 2301 movs r3, #1 801565e: 767b strb r3, [r7, #25] apiflags |= TCP_WRITE_FLAG_MORE; 8015660: 7ebb ldrb r3, [r7, #26] 8015662: f043 0302 orr.w r3, r3, #2 8015666: 76bb strb r3, [r7, #26] 8015668: e001 b.n 801566e } else { write_more = 0; 801566a: 2300 movs r3, #0 801566c: 767b strb r3, [r7, #25] } err = tcp_write(conn->pcb.tcp, dataptr, len, apiflags); 801566e: 687b ldr r3, [r7, #4] 8015670: 6858 ldr r0, [r3, #4] 8015672: 7ebb ldrb r3, [r7, #26] 8015674: 8bba ldrh r2, [r7, #28] 8015676: 6979 ldr r1, [r7, #20] 8015678: f007 f858 bl 801c72c 801567c: 4603 mov r3, r0 801567e: 77fb strb r3, [r7, #31] if (err == ERR_OK) { 8015680: f997 301f ldrsb.w r3, [r7, #31] 8015684: 2b00 cmp r3, #0 8015686: d12c bne.n 80156e2 conn->current_msg->msg.w.offset += len; 8015688: 687b ldr r3, [r7, #4] 801568a: 6a1b ldr r3, [r3, #32] 801568c: 6999 ldr r1, [r3, #24] 801568e: 8bba ldrh r2, [r7, #28] 8015690: 687b ldr r3, [r7, #4] 8015692: 6a1b ldr r3, [r3, #32] 8015694: 440a add r2, r1 8015696: 619a str r2, [r3, #24] conn->current_msg->msg.w.vector_off += len; 8015698: 687b ldr r3, [r7, #4] 801569a: 6a1b ldr r3, [r3, #32] 801569c: 6919 ldr r1, [r3, #16] 801569e: 8bba ldrh r2, [r7, #28] 80156a0: 687b ldr r3, [r7, #4] 80156a2: 6a1b ldr r3, [r3, #32] 80156a4: 440a add r2, r1 80156a6: 611a str r2, [r3, #16] /* check if current vector is finished */ if (conn->current_msg->msg.w.vector_off == conn->current_msg->msg.w.vector->len) { 80156a8: 687b ldr r3, [r7, #4] 80156aa: 6a1b ldr r3, [r3, #32] 80156ac: 691a ldr r2, [r3, #16] 80156ae: 687b ldr r3, [r7, #4] 80156b0: 6a1b ldr r3, [r3, #32] 80156b2: 689b ldr r3, [r3, #8] 80156b4: 685b ldr r3, [r3, #4] 80156b6: 429a cmp r2, r3 80156b8: d113 bne.n 80156e2 conn->current_msg->msg.w.vector_cnt--; 80156ba: 687b ldr r3, [r7, #4] 80156bc: 6a1b ldr r3, [r3, #32] 80156be: 899a ldrh r2, [r3, #12] 80156c0: 3a01 subs r2, #1 80156c2: b292 uxth r2, r2 80156c4: 819a strh r2, [r3, #12] /* if we have additional vectors, move on to them */ if (conn->current_msg->msg.w.vector_cnt > 0) { 80156c6: 687b ldr r3, [r7, #4] 80156c8: 6a1b ldr r3, [r3, #32] 80156ca: 899b ldrh r3, [r3, #12] 80156cc: 2b00 cmp r3, #0 80156ce: d008 beq.n 80156e2 conn->current_msg->msg.w.vector++; 80156d0: 687b ldr r3, [r7, #4] 80156d2: 6a1b ldr r3, [r3, #32] 80156d4: 689a ldr r2, [r3, #8] 80156d6: 3208 adds r2, #8 80156d8: 609a str r2, [r3, #8] conn->current_msg->msg.w.vector_off = 0; 80156da: 687b ldr r3, [r7, #4] 80156dc: 6a1b ldr r3, [r3, #32] 80156de: 2200 movs r2, #0 80156e0: 611a str r2, [r3, #16] } } } } while (write_more && err == ERR_OK); 80156e2: 7e7b ldrb r3, [r7, #25] 80156e4: 2b00 cmp r3, #0 80156e6: d004 beq.n 80156f2 80156e8: f997 301f ldrsb.w r3, [r7, #31] 80156ec: 2b00 cmp r3, #0 80156ee: f43f af50 beq.w 8015592 /* if OK or memory error, check available space */ if ((err == ERR_OK) || (err == ERR_MEM)) { 80156f2: f997 301f ldrsb.w r3, [r7, #31] 80156f6: 2b00 cmp r3, #0 80156f8: d004 beq.n 8015704 80156fa: f997 301f ldrsb.w r3, [r7, #31] 80156fe: f1b3 3fff cmp.w r3, #4294967295 8015702: d147 bne.n 8015794 err_mem: 8015704: bf00 nop if (dontblock && (conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len)) { 8015706: 7e3b ldrb r3, [r7, #24] 8015708: 2b00 cmp r3, #0 801570a: d02b beq.n 8015764 801570c: 687b ldr r3, [r7, #4] 801570e: 6a1b ldr r3, [r3, #32] 8015710: 699a ldr r2, [r3, #24] 8015712: 687b ldr r3, [r7, #4] 8015714: 6a1b ldr r3, [r3, #32] 8015716: 695b ldr r3, [r3, #20] 8015718: 429a cmp r2, r3 801571a: d223 bcs.n 8015764 /* non-blocking write did not write everything: mark the pcb non-writable and let poll_tcp check writable space to mark the pcb writable again */ API_EVENT(conn, NETCONN_EVT_SENDMINUS, 0); 801571c: 687b ldr r3, [r7, #4] 801571e: 6a5b ldr r3, [r3, #36] ; 0x24 8015720: 2b00 cmp r3, #0 8015722: d005 beq.n 8015730 8015724: 687b ldr r3, [r7, #4] 8015726: 6a5b ldr r3, [r3, #36] ; 0x24 8015728: 2200 movs r2, #0 801572a: 2103 movs r1, #3 801572c: 6878 ldr r0, [r7, #4] 801572e: 4798 blx r3 conn->flags |= NETCONN_FLAG_CHECK_WRITESPACE; 8015730: 687b ldr r3, [r7, #4] 8015732: 7f1b ldrb r3, [r3, #28] 8015734: f043 0310 orr.w r3, r3, #16 8015738: b2da uxtb r2, r3 801573a: 687b ldr r3, [r7, #4] 801573c: 771a strb r2, [r3, #28] 801573e: e029 b.n 8015794 8015740: 08023624 .word 0x08023624 8015744: 0802377c .word 0x0802377c 8015748: 08023668 .word 0x08023668 801574c: 08023a84 .word 0x08023a84 8015750: 0802378c .word 0x0802378c 8015754: 08023aa4 .word 0x08023aa4 8015758: 08023abc .word 0x08023abc 801575c: 08023afc .word 0x08023afc 8015760: 08023b24 .word 0x08023b24 } else if ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) || 8015764: 687b ldr r3, [r7, #4] 8015766: 685b ldr r3, [r3, #4] 8015768: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64 801576c: f640 3269 movw r2, #2921 ; 0xb69 8015770: 4293 cmp r3, r2 8015772: d905 bls.n 8015780 (tcp_sndqueuelen(conn->pcb.tcp) >= TCP_SNDQUEUELOWAT)) { 8015774: 687b ldr r3, [r7, #4] 8015776: 685b ldr r3, [r3, #4] 8015778: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 } else if ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) || 801577c: 2b07 cmp r3, #7 801577e: d909 bls.n 8015794 /* The queued byte- or pbuf-count exceeds the configured low-water limit, let select mark this pcb as non-writable. */ API_EVENT(conn, NETCONN_EVT_SENDMINUS, 0); 8015780: 687b ldr r3, [r7, #4] 8015782: 6a5b ldr r3, [r3, #36] ; 0x24 8015784: 2b00 cmp r3, #0 8015786: d005 beq.n 8015794 8015788: 687b ldr r3, [r7, #4] 801578a: 6a5b ldr r3, [r3, #36] ; 0x24 801578c: 2200 movs r2, #0 801578e: 2103 movs r1, #3 8015790: 6878 ldr r0, [r7, #4] 8015792: 4798 blx r3 } } if (err == ERR_OK) { 8015794: f997 301f ldrsb.w r3, [r7, #31] 8015798: 2b00 cmp r3, #0 801579a: d11d bne.n 80157d8 err_t out_err; if ((conn->current_msg->msg.w.offset == conn->current_msg->msg.w.len) || dontblock) { 801579c: 687b ldr r3, [r7, #4] 801579e: 6a1b ldr r3, [r3, #32] 80157a0: 699a ldr r2, [r3, #24] 80157a2: 687b ldr r3, [r7, #4] 80157a4: 6a1b ldr r3, [r3, #32] 80157a6: 695b ldr r3, [r3, #20] 80157a8: 429a cmp r2, r3 80157aa: d002 beq.n 80157b2 80157ac: 7e3b ldrb r3, [r7, #24] 80157ae: 2b00 cmp r3, #0 80157b0: d001 beq.n 80157b6 /* return sent length (caller reads length from msg.w.offset) */ write_finished = 1; 80157b2: 2301 movs r3, #1 80157b4: 76fb strb r3, [r7, #27] } out_err = tcp_output(conn->pcb.tcp); 80157b6: 687b ldr r3, [r7, #4] 80157b8: 685b ldr r3, [r3, #4] 80157ba: 4618 mov r0, r3 80157bc: f007 fdfe bl 801d3bc 80157c0: 4603 mov r3, r0 80157c2: 733b strb r3, [r7, #12] if (out_err == ERR_RTE) { 80157c4: f997 300c ldrsb.w r3, [r7, #12] 80157c8: f113 0f04 cmn.w r3, #4 80157cc: d12c bne.n 8015828 /* If tcp_output fails because no route is found, don't try writing any more but return the error to the application thread. */ err = out_err; 80157ce: 7b3b ldrb r3, [r7, #12] 80157d0: 77fb strb r3, [r7, #31] write_finished = 1; 80157d2: 2301 movs r3, #1 80157d4: 76fb strb r3, [r7, #27] 80157d6: e027 b.n 8015828 } } else if (err == ERR_MEM) { 80157d8: f997 301f ldrsb.w r3, [r7, #31] 80157dc: f1b3 3fff cmp.w r3, #4294967295 80157e0: d120 bne.n 8015824 For blocking sockets, we do NOT return to the application thread, since ERR_MEM is only a temporary error! Non-blocking will remain non-writable until sent_tcp/poll_tcp is called */ /* tcp_write returned ERR_MEM, try tcp_output anyway */ err_t out_err = tcp_output(conn->pcb.tcp); 80157e2: 687b ldr r3, [r7, #4] 80157e4: 685b ldr r3, [r3, #4] 80157e6: 4618 mov r0, r3 80157e8: f007 fde8 bl 801d3bc 80157ec: 4603 mov r3, r0 80157ee: 737b strb r3, [r7, #13] if (out_err == ERR_RTE) { 80157f0: f997 300d ldrsb.w r3, [r7, #13] 80157f4: f113 0f04 cmn.w r3, #4 80157f8: d104 bne.n 8015804 /* If tcp_output fails because no route is found, don't try writing any more but return the error to the application thread. */ err = out_err; 80157fa: 7b7b ldrb r3, [r7, #13] 80157fc: 77fb strb r3, [r7, #31] write_finished = 1; 80157fe: 2301 movs r3, #1 8015800: 76fb strb r3, [r7, #27] 8015802: e011 b.n 8015828 } else if (dontblock) { 8015804: 7e3b ldrb r3, [r7, #24] 8015806: 2b00 cmp r3, #0 8015808: d00e beq.n 8015828 /* non-blocking write is done on ERR_MEM, set error according to partial write or not */ err = (conn->current_msg->msg.w.offset == 0) ? ERR_WOULDBLOCK : ERR_OK; 801580a: 687b ldr r3, [r7, #4] 801580c: 6a1b ldr r3, [r3, #32] 801580e: 699b ldr r3, [r3, #24] 8015810: 2b00 cmp r3, #0 8015812: d102 bne.n 801581a 8015814: f06f 0306 mvn.w r3, #6 8015818: e000 b.n 801581c 801581a: 2300 movs r3, #0 801581c: 77fb strb r3, [r7, #31] write_finished = 1; 801581e: 2301 movs r3, #1 8015820: 76fb strb r3, [r7, #27] 8015822: e001 b.n 8015828 } } else { /* On errors != ERR_MEM, we don't try writing any more but return the error to the application thread. */ write_finished = 1; 8015824: 2301 movs r3, #1 8015826: 76fb strb r3, [r7, #27] } } if (write_finished) { 8015828: 7efb ldrb r3, [r7, #27] 801582a: 2b00 cmp r3, #0 801582c: d015 beq.n 801585a /* everything was written: set back connection state and back to application task */ sys_sem_t *op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); 801582e: 687b ldr r3, [r7, #4] 8015830: 6a1b ldr r3, [r3, #32] 8015832: 681b ldr r3, [r3, #0] 8015834: 330c adds r3, #12 8015836: 60bb str r3, [r7, #8] conn->current_msg->err = err; 8015838: 687b ldr r3, [r7, #4] 801583a: 6a1b ldr r3, [r3, #32] 801583c: 7ffa ldrb r2, [r7, #31] 801583e: 711a strb r2, [r3, #4] conn->current_msg = NULL; 8015840: 687b ldr r3, [r7, #4] 8015842: 2200 movs r2, #0 8015844: 621a str r2, [r3, #32] conn->state = NETCONN_NONE; 8015846: 687b ldr r3, [r7, #4] 8015848: 2200 movs r2, #0 801584a: 705a strb r2, [r3, #1] #if LWIP_TCPIP_CORE_LOCKING if (delayed) 801584c: 78fb ldrb r3, [r7, #3] 801584e: 2b00 cmp r3, #0 8015850: d006 beq.n 8015860 #endif { sys_sem_signal(op_completed_sem); 8015852: 68b8 ldr r0, [r7, #8] 8015854: f00b fe5a bl 802150c 8015858: e002 b.n 8015860 } } #if LWIP_TCPIP_CORE_LOCKING else { return ERR_MEM; 801585a: f04f 33ff mov.w r3, #4294967295 801585e: e000 b.n 8015862 } #endif return ERR_OK; 8015860: 2300 movs r3, #0 } 8015862: 4618 mov r0, r3 8015864: 3720 adds r7, #32 8015866: 46bd mov sp, r7 8015868: bd80 pop {r7, pc} 801586a: bf00 nop 0801586c : * * @param m the api_msg pointing to the connection */ void lwip_netconn_do_write(void *m) { 801586c: b580 push {r7, lr} 801586e: b084 sub sp, #16 8015870: af00 add r7, sp, #0 8015872: 6078 str r0, [r7, #4] struct api_msg *msg = (struct api_msg *)m; 8015874: 687b ldr r3, [r7, #4] 8015876: 60bb str r3, [r7, #8] err_t err = netconn_err(msg->conn); 8015878: 68bb ldr r3, [r7, #8] 801587a: 681b ldr r3, [r3, #0] 801587c: 4618 mov r0, r3 801587e: f7fe fd1c bl 80142ba 8015882: 4603 mov r3, r0 8015884: 73fb strb r3, [r7, #15] if (err == ERR_OK) { 8015886: f997 300f ldrsb.w r3, [r7, #15] 801588a: 2b00 cmp r3, #0 801588c: d166 bne.n 801595c if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { 801588e: 68bb ldr r3, [r7, #8] 8015890: 681b ldr r3, [r3, #0] 8015892: 781b ldrb r3, [r3, #0] 8015894: f003 03f0 and.w r3, r3, #240 ; 0xf0 8015898: 2b10 cmp r3, #16 801589a: d15d bne.n 8015958 #if LWIP_TCP if (msg->conn->state != NETCONN_NONE) { 801589c: 68bb ldr r3, [r7, #8] 801589e: 681b ldr r3, [r3, #0] 80158a0: 785b ldrb r3, [r3, #1] 80158a2: 2b00 cmp r3, #0 80158a4: d002 beq.n 80158ac /* netconn is connecting, closing or in blocking write */ err = ERR_INPROGRESS; 80158a6: 23fb movs r3, #251 ; 0xfb 80158a8: 73fb strb r3, [r7, #15] 80158aa: e057 b.n 801595c } else if (msg->conn->pcb.tcp != NULL) { 80158ac: 68bb ldr r3, [r7, #8] 80158ae: 681b ldr r3, [r3, #0] 80158b0: 685b ldr r3, [r3, #4] 80158b2: 2b00 cmp r3, #0 80158b4: d04d beq.n 8015952 msg->conn->state = NETCONN_WRITE; 80158b6: 68bb ldr r3, [r7, #8] 80158b8: 681b ldr r3, [r3, #0] 80158ba: 2201 movs r2, #1 80158bc: 705a strb r2, [r3, #1] /* set all the variables used by lwip_netconn_do_writemore */ LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL); 80158be: 68bb ldr r3, [r7, #8] 80158c0: 681b ldr r3, [r3, #0] 80158c2: 6a1b ldr r3, [r3, #32] 80158c4: 2b00 cmp r3, #0 80158c6: d006 beq.n 80158d6 80158c8: 4b28 ldr r3, [pc, #160] ; (801596c ) 80158ca: f240 7223 movw r2, #1827 ; 0x723 80158ce: 4928 ldr r1, [pc, #160] ; (8015970 ) 80158d0: 4828 ldr r0, [pc, #160] ; (8015974 ) 80158d2: f00c f859 bl 8021988 LWIP_ASSERT("msg->msg.w.len != 0", msg->msg.w.len != 0); 80158d6: 68bb ldr r3, [r7, #8] 80158d8: 695b ldr r3, [r3, #20] 80158da: 2b00 cmp r3, #0 80158dc: d106 bne.n 80158ec 80158de: 4b23 ldr r3, [pc, #140] ; (801596c ) 80158e0: f240 7224 movw r2, #1828 ; 0x724 80158e4: 4924 ldr r1, [pc, #144] ; (8015978 ) 80158e6: 4823 ldr r0, [pc, #140] ; (8015974 ) 80158e8: f00c f84e bl 8021988 msg->conn->current_msg = msg; 80158ec: 68bb ldr r3, [r7, #8] 80158ee: 681b ldr r3, [r3, #0] 80158f0: 68ba ldr r2, [r7, #8] 80158f2: 621a str r2, [r3, #32] #if LWIP_TCPIP_CORE_LOCKING if (lwip_netconn_do_writemore(msg->conn, 0) != ERR_OK) { 80158f4: 68bb ldr r3, [r7, #8] 80158f6: 681b ldr r3, [r3, #0] 80158f8: 2100 movs r1, #0 80158fa: 4618 mov r0, r3 80158fc: f7ff fde8 bl 80154d0 8015900: 4603 mov r3, r0 8015902: 2b00 cmp r3, #0 8015904: d02e beq.n 8015964 LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE); 8015906: 68bb ldr r3, [r7, #8] 8015908: 681b ldr r3, [r3, #0] 801590a: 785b ldrb r3, [r3, #1] 801590c: 2b01 cmp r3, #1 801590e: d006 beq.n 801591e 8015910: 4b16 ldr r3, [pc, #88] ; (801596c ) 8015912: f44f 62e5 mov.w r2, #1832 ; 0x728 8015916: 4919 ldr r1, [pc, #100] ; (801597c ) 8015918: 4816 ldr r0, [pc, #88] ; (8015974 ) 801591a: f00c f835 bl 8021988 UNLOCK_TCPIP_CORE(); 801591e: 4818 ldr r0, [pc, #96] ; (8015980 ) 8015920: f00b fe65 bl 80215ee sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); 8015924: 68bb ldr r3, [r7, #8] 8015926: 681b ldr r3, [r3, #0] 8015928: 330c adds r3, #12 801592a: 2100 movs r1, #0 801592c: 4618 mov r0, r3 801592e: f00b fdbc bl 80214aa LOCK_TCPIP_CORE(); 8015932: 4813 ldr r0, [pc, #76] ; (8015980 ) 8015934: f00b fe4c bl 80215d0 LWIP_ASSERT("state!", msg->conn->state != NETCONN_WRITE); 8015938: 68bb ldr r3, [r7, #8] 801593a: 681b ldr r3, [r3, #0] 801593c: 785b ldrb r3, [r3, #1] 801593e: 2b01 cmp r3, #1 8015940: d110 bne.n 8015964 8015942: 4b0a ldr r3, [pc, #40] ; (801596c ) 8015944: f240 722c movw r2, #1836 ; 0x72c 8015948: 490c ldr r1, [pc, #48] ; (801597c ) 801594a: 480a ldr r0, [pc, #40] ; (8015974 ) 801594c: f00c f81c bl 8021988 #else /* LWIP_TCPIP_CORE_LOCKING */ lwip_netconn_do_writemore(msg->conn); #endif /* LWIP_TCPIP_CORE_LOCKING */ /* for both cases: if lwip_netconn_do_writemore was called, don't ACK the APIMSG since lwip_netconn_do_writemore ACKs it! */ return; 8015950: e008 b.n 8015964 } else { err = ERR_CONN; 8015952: 23f5 movs r3, #245 ; 0xf5 8015954: 73fb strb r3, [r7, #15] 8015956: e001 b.n 801595c #else /* LWIP_TCP */ err = ERR_VAL; #endif /* LWIP_TCP */ #if (LWIP_UDP || LWIP_RAW) } else { err = ERR_VAL; 8015958: 23fa movs r3, #250 ; 0xfa 801595a: 73fb strb r3, [r7, #15] #endif /* (LWIP_UDP || LWIP_RAW) */ } } msg->err = err; 801595c: 68bb ldr r3, [r7, #8] 801595e: 7bfa ldrb r2, [r7, #15] 8015960: 711a strb r2, [r3, #4] 8015962: e000 b.n 8015966 return; 8015964: bf00 nop TCPIP_APIMSG_ACK(msg); } 8015966: 3710 adds r7, #16 8015968: 46bd mov sp, r7 801596a: bd80 pop {r7, pc} 801596c: 08023624 .word 0x08023624 8015970: 080239c8 .word 0x080239c8 8015974: 08023668 .word 0x08023668 8015978: 08023b50 .word 0x08023b50 801597c: 080239e4 .word 0x080239e4 8015980: 2401397c .word 0x2401397c 08015984 : * * @param m the api_msg pointing to the connection */ void lwip_netconn_do_close(void *m) { 8015984: b580 push {r7, lr} 8015986: b084 sub sp, #16 8015988: af00 add r7, sp, #0 801598a: 6078 str r0, [r7, #4] struct api_msg *msg = (struct api_msg *)m; 801598c: 687b ldr r3, [r7, #4] 801598e: 60fb str r3, [r7, #12] #if LWIP_TCP enum netconn_state state = msg->conn->state; 8015990: 68fb ldr r3, [r7, #12] 8015992: 681b ldr r3, [r3, #0] 8015994: 785b ldrb r3, [r3, #1] 8015996: 72fb strb r3, [r7, #11] /* First check if this is a TCP netconn and if it is in a correct state (LISTEN doesn't support half shutdown) */ if ((msg->conn->pcb.tcp != NULL) && 8015998: 68fb ldr r3, [r7, #12] 801599a: 681b ldr r3, [r3, #0] 801599c: 685b ldr r3, [r3, #4] 801599e: 2b00 cmp r3, #0 80159a0: d069 beq.n 8015a76 (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) && 80159a2: 68fb ldr r3, [r7, #12] 80159a4: 681b ldr r3, [r3, #0] 80159a6: 781b ldrb r3, [r3, #0] 80159a8: f003 03f0 and.w r3, r3, #240 ; 0xf0 if ((msg->conn->pcb.tcp != NULL) && 80159ac: 2b10 cmp r3, #16 80159ae: d162 bne.n 8015a76 ((msg->msg.sd.shut == NETCONN_SHUT_RDWR) || (state != NETCONN_LISTEN))) { 80159b0: 68fb ldr r3, [r7, #12] 80159b2: 7a1b ldrb r3, [r3, #8] (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) && 80159b4: 2b03 cmp r3, #3 80159b6: d002 beq.n 80159be ((msg->msg.sd.shut == NETCONN_SHUT_RDWR) || (state != NETCONN_LISTEN))) { 80159b8: 7afb ldrb r3, [r7, #11] 80159ba: 2b02 cmp r3, #2 80159bc: d05b beq.n 8015a76 /* Check if we are in a connected state */ if (state == NETCONN_CONNECT) { 80159be: 7afb ldrb r3, [r7, #11] 80159c0: 2b03 cmp r3, #3 80159c2: d103 bne.n 80159cc /* TCP connect in progress: cannot shutdown */ msg->err = ERR_CONN; 80159c4: 68fb ldr r3, [r7, #12] 80159c6: 22f5 movs r2, #245 ; 0xf5 80159c8: 711a strb r2, [r3, #4] if (state == NETCONN_CONNECT) { 80159ca: e059 b.n 8015a80 } else if (state == NETCONN_WRITE) { 80159cc: 7afb ldrb r3, [r7, #11] 80159ce: 2b01 cmp r3, #1 80159d0: d103 bne.n 80159da msg->err = tcp_shutdown(msg->conn->pcb.tcp, 1, 0); } } if (state == NETCONN_NONE) { #else /* LWIP_NETCONN_FULLDUPLEX */ msg->err = ERR_INPROGRESS; 80159d2: 68fb ldr r3, [r7, #12] 80159d4: 22fb movs r2, #251 ; 0xfb 80159d6: 711a strb r2, [r3, #4] if (state == NETCONN_CONNECT) { 80159d8: e052 b.n 8015a80 } else { #endif /* LWIP_NETCONN_FULLDUPLEX */ if (msg->msg.sd.shut & NETCONN_SHUT_RD) { 80159da: 68fb ldr r3, [r7, #12] 80159dc: 7a1b ldrb r3, [r3, #8] 80159de: f003 0301 and.w r3, r3, #1 80159e2: 2b00 cmp r3, #0 80159e4: d004 beq.n 80159f0 #if LWIP_NETCONN_FULLDUPLEX /* Mark mboxes invalid */ netconn_mark_mbox_invalid(msg->conn); #else /* LWIP_NETCONN_FULLDUPLEX */ netconn_drain(msg->conn); 80159e6: 68fb ldr r3, [r7, #12] 80159e8: 681b ldr r3, [r3, #0] 80159ea: 4618 mov r0, r3 80159ec: f7ff f8e6 bl 8014bbc #endif /* LWIP_NETCONN_FULLDUPLEX */ } LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL); 80159f0: 68fb ldr r3, [r7, #12] 80159f2: 681b ldr r3, [r3, #0] 80159f4: 6a1b ldr r3, [r3, #32] 80159f6: 2b00 cmp r3, #0 80159f8: d006 beq.n 8015a08 80159fa: 4b23 ldr r3, [pc, #140] ; (8015a88 ) 80159fc: f240 72bd movw r2, #1981 ; 0x7bd 8015a00: 4922 ldr r1, [pc, #136] ; (8015a8c ) 8015a02: 4823 ldr r0, [pc, #140] ; (8015a90 ) 8015a04: f00b ffc0 bl 8021988 msg->conn->state = NETCONN_CLOSE; 8015a08: 68fb ldr r3, [r7, #12] 8015a0a: 681b ldr r3, [r3, #0] 8015a0c: 2204 movs r2, #4 8015a0e: 705a strb r2, [r3, #1] msg->conn->current_msg = msg; 8015a10: 68fb ldr r3, [r7, #12] 8015a12: 681b ldr r3, [r3, #0] 8015a14: 68fa ldr r2, [r7, #12] 8015a16: 621a str r2, [r3, #32] #if LWIP_TCPIP_CORE_LOCKING if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) { 8015a18: 68fb ldr r3, [r7, #12] 8015a1a: 681b ldr r3, [r3, #0] 8015a1c: 2100 movs r1, #0 8015a1e: 4618 mov r0, r3 8015a20: f7ff f94a bl 8014cb8 8015a24: 4603 mov r3, r0 8015a26: 2b00 cmp r3, #0 8015a28: d029 beq.n 8015a7e LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE); 8015a2a: 68fb ldr r3, [r7, #12] 8015a2c: 681b ldr r3, [r3, #0] 8015a2e: 785b ldrb r3, [r3, #1] 8015a30: 2b04 cmp r3, #4 8015a32: d006 beq.n 8015a42 8015a34: 4b14 ldr r3, [pc, #80] ; (8015a88 ) 8015a36: f240 72c2 movw r2, #1986 ; 0x7c2 8015a3a: 4916 ldr r1, [pc, #88] ; (8015a94 ) 8015a3c: 4814 ldr r0, [pc, #80] ; (8015a90 ) 8015a3e: f00b ffa3 bl 8021988 UNLOCK_TCPIP_CORE(); 8015a42: 4815 ldr r0, [pc, #84] ; (8015a98 ) 8015a44: f00b fdd3 bl 80215ee sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); 8015a48: 68fb ldr r3, [r7, #12] 8015a4a: 681b ldr r3, [r3, #0] 8015a4c: 330c adds r3, #12 8015a4e: 2100 movs r1, #0 8015a50: 4618 mov r0, r3 8015a52: f00b fd2a bl 80214aa LOCK_TCPIP_CORE(); 8015a56: 4810 ldr r0, [pc, #64] ; (8015a98 ) 8015a58: f00b fdba bl 80215d0 LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); 8015a5c: 68fb ldr r3, [r7, #12] 8015a5e: 681b ldr r3, [r3, #0] 8015a60: 785b ldrb r3, [r3, #1] 8015a62: 2b00 cmp r3, #0 8015a64: d00b beq.n 8015a7e 8015a66: 4b08 ldr r3, [pc, #32] ; (8015a88 ) 8015a68: f240 72c6 movw r2, #1990 ; 0x7c6 8015a6c: 4909 ldr r1, [pc, #36] ; (8015a94 ) 8015a6e: 4808 ldr r0, [pc, #32] ; (8015a90 ) 8015a70: f00b ff8a bl 8021988 } #else /* LWIP_TCPIP_CORE_LOCKING */ lwip_netconn_do_close_internal(msg->conn); #endif /* LWIP_TCPIP_CORE_LOCKING */ /* for tcp netconns, lwip_netconn_do_close_internal ACKs the message */ return; 8015a74: e003 b.n 8015a7e } } else #endif /* LWIP_TCP */ { msg->err = ERR_CONN; 8015a76: 68fb ldr r3, [r7, #12] 8015a78: 22f5 movs r2, #245 ; 0xf5 8015a7a: 711a strb r2, [r3, #4] 8015a7c: e000 b.n 8015a80 return; 8015a7e: bf00 nop } TCPIP_APIMSG_ACK(msg); } 8015a80: 3710 adds r7, #16 8015a82: 46bd mov sp, r7 8015a84: bd80 pop {r7, pc} 8015a86: bf00 nop 8015a88: 08023624 .word 0x08023624 8015a8c: 080239c8 .word 0x080239c8 8015a90: 08023668 .word 0x08023668 8015a94: 080239e4 .word 0x080239e4 8015a98: 2401397c .word 0x2401397c 08015a9c : * * @param buf pointer to a netbuf allocated by netbuf_new() */ void netbuf_delete(struct netbuf *buf) { 8015a9c: b580 push {r7, lr} 8015a9e: b082 sub sp, #8 8015aa0: af00 add r7, sp, #0 8015aa2: 6078 str r0, [r7, #4] if (buf != NULL) { 8015aa4: 687b ldr r3, [r7, #4] 8015aa6: 2b00 cmp r3, #0 8015aa8: d013 beq.n 8015ad2 if (buf->p != NULL) { 8015aaa: 687b ldr r3, [r7, #4] 8015aac: 681b ldr r3, [r3, #0] 8015aae: 2b00 cmp r3, #0 8015ab0: d00b beq.n 8015aca pbuf_free(buf->p); 8015ab2: 687b ldr r3, [r7, #4] 8015ab4: 681b ldr r3, [r3, #0] 8015ab6: 4618 mov r0, r3 8015ab8: f002 f81e bl 8017af8 buf->p = buf->ptr = NULL; 8015abc: 687b ldr r3, [r7, #4] 8015abe: 2200 movs r2, #0 8015ac0: 605a str r2, [r3, #4] 8015ac2: 687b ldr r3, [r7, #4] 8015ac4: 685a ldr r2, [r3, #4] 8015ac6: 687b ldr r3, [r7, #4] 8015ac8: 601a str r2, [r3, #0] } memp_free(MEMP_NETBUF, buf); 8015aca: 6879 ldr r1, [r7, #4] 8015acc: 2006 movs r0, #6 8015ace: f001 f875 bl 8016bbc } } 8015ad2: bf00 nop 8015ad4: 3708 adds r7, #8 8015ad6: 46bd mov sp, r7 8015ad8: bd80 pop {r7, pc} ... 08015adc : * @return ERR_OK if the information was retrieved, * ERR_BUF on error. */ err_t netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len) { 8015adc: b580 push {r7, lr} 8015ade: b084 sub sp, #16 8015ae0: af00 add r7, sp, #0 8015ae2: 60f8 str r0, [r7, #12] 8015ae4: 60b9 str r1, [r7, #8] 8015ae6: 607a str r2, [r7, #4] LWIP_ERROR("netbuf_data: invalid buf", (buf != NULL), return ERR_ARG;); 8015ae8: 68fb ldr r3, [r7, #12] 8015aea: 2b00 cmp r3, #0 8015aec: d108 bne.n 8015b00 8015aee: 4b1b ldr r3, [pc, #108] ; (8015b5c ) 8015af0: 22c6 movs r2, #198 ; 0xc6 8015af2: 491b ldr r1, [pc, #108] ; (8015b60 ) 8015af4: 481b ldr r0, [pc, #108] ; (8015b64 ) 8015af6: f00b ff47 bl 8021988 8015afa: f06f 030f mvn.w r3, #15 8015afe: e029 b.n 8015b54 LWIP_ERROR("netbuf_data: invalid dataptr", (dataptr != NULL), return ERR_ARG;); 8015b00: 68bb ldr r3, [r7, #8] 8015b02: 2b00 cmp r3, #0 8015b04: d108 bne.n 8015b18 8015b06: 4b15 ldr r3, [pc, #84] ; (8015b5c ) 8015b08: 22c7 movs r2, #199 ; 0xc7 8015b0a: 4917 ldr r1, [pc, #92] ; (8015b68 ) 8015b0c: 4815 ldr r0, [pc, #84] ; (8015b64 ) 8015b0e: f00b ff3b bl 8021988 8015b12: f06f 030f mvn.w r3, #15 8015b16: e01d b.n 8015b54 LWIP_ERROR("netbuf_data: invalid len", (len != NULL), return ERR_ARG;); 8015b18: 687b ldr r3, [r7, #4] 8015b1a: 2b00 cmp r3, #0 8015b1c: d108 bne.n 8015b30 8015b1e: 4b0f ldr r3, [pc, #60] ; (8015b5c ) 8015b20: 22c8 movs r2, #200 ; 0xc8 8015b22: 4912 ldr r1, [pc, #72] ; (8015b6c ) 8015b24: 480f ldr r0, [pc, #60] ; (8015b64 ) 8015b26: f00b ff2f bl 8021988 8015b2a: f06f 030f mvn.w r3, #15 8015b2e: e011 b.n 8015b54 if (buf->ptr == NULL) { 8015b30: 68fb ldr r3, [r7, #12] 8015b32: 685b ldr r3, [r3, #4] 8015b34: 2b00 cmp r3, #0 8015b36: d102 bne.n 8015b3e return ERR_BUF; 8015b38: f06f 0301 mvn.w r3, #1 8015b3c: e00a b.n 8015b54 } *dataptr = buf->ptr->payload; 8015b3e: 68fb ldr r3, [r7, #12] 8015b40: 685b ldr r3, [r3, #4] 8015b42: 685a ldr r2, [r3, #4] 8015b44: 68bb ldr r3, [r7, #8] 8015b46: 601a str r2, [r3, #0] *len = buf->ptr->len; 8015b48: 68fb ldr r3, [r7, #12] 8015b4a: 685b ldr r3, [r3, #4] 8015b4c: 895a ldrh r2, [r3, #10] 8015b4e: 687b ldr r3, [r7, #4] 8015b50: 801a strh r2, [r3, #0] return ERR_OK; 8015b52: 2300 movs r3, #0 } 8015b54: 4618 mov r0, r3 8015b56: 3710 adds r7, #16 8015b58: 46bd mov sp, r7 8015b5a: bd80 pop {r7, pc} 8015b5c: 08023b7c .word 0x08023b7c 8015b60: 08023c84 .word 0x08023c84 8015b64: 08023bcc .word 0x08023bcc 8015b68: 08023ca0 .word 0x08023ca0 8015b6c: 08023cc0 .word 0x08023cc0 08015b70 : * 1 if moved to the next part but now there is no next part * 0 if moved to the next part and there are still more parts */ s8_t netbuf_next(struct netbuf *buf) { 8015b70: b580 push {r7, lr} 8015b72: b082 sub sp, #8 8015b74: af00 add r7, sp, #0 8015b76: 6078 str r0, [r7, #4] LWIP_ERROR("netbuf_next: invalid buf", (buf != NULL), return -1;); 8015b78: 687b ldr r3, [r7, #4] 8015b7a: 2b00 cmp r3, #0 8015b7c: d108 bne.n 8015b90 8015b7e: 4b11 ldr r3, [pc, #68] ; (8015bc4 ) 8015b80: 22e0 movs r2, #224 ; 0xe0 8015b82: 4911 ldr r1, [pc, #68] ; (8015bc8 ) 8015b84: 4811 ldr r0, [pc, #68] ; (8015bcc ) 8015b86: f00b feff bl 8021988 8015b8a: f04f 33ff mov.w r3, #4294967295 8015b8e: e014 b.n 8015bba if (buf->ptr->next == NULL) { 8015b90: 687b ldr r3, [r7, #4] 8015b92: 685b ldr r3, [r3, #4] 8015b94: 681b ldr r3, [r3, #0] 8015b96: 2b00 cmp r3, #0 8015b98: d102 bne.n 8015ba0 return -1; 8015b9a: f04f 33ff mov.w r3, #4294967295 8015b9e: e00c b.n 8015bba } buf->ptr = buf->ptr->next; 8015ba0: 687b ldr r3, [r7, #4] 8015ba2: 685b ldr r3, [r3, #4] 8015ba4: 681a ldr r2, [r3, #0] 8015ba6: 687b ldr r3, [r7, #4] 8015ba8: 605a str r2, [r3, #4] if (buf->ptr->next == NULL) { 8015baa: 687b ldr r3, [r7, #4] 8015bac: 685b ldr r3, [r3, #4] 8015bae: 681b ldr r3, [r3, #0] 8015bb0: 2b00 cmp r3, #0 8015bb2: d101 bne.n 8015bb8 return 1; 8015bb4: 2301 movs r3, #1 8015bb6: e000 b.n 8015bba } return 0; 8015bb8: 2300 movs r3, #0 } 8015bba: 4618 mov r0, r3 8015bbc: 3708 adds r7, #8 8015bbe: 46bd mov sp, r7 8015bc0: bd80 pop {r7, pc} 8015bc2: bf00 nop 8015bc4: 08023b7c .word 0x08023b7c 8015bc8: 08023cdc .word 0x08023cdc 8015bcc: 08023bcc .word 0x08023bcc 08015bd0 : * @param mbox the mbox to fetch the message from * @param msg the place to store the message */ static void tcpip_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg) { 8015bd0: b580 push {r7, lr} 8015bd2: b084 sub sp, #16 8015bd4: af00 add r7, sp, #0 8015bd6: 6078 str r0, [r7, #4] 8015bd8: 6039 str r1, [r7, #0] u32_t sleeptime, res; again: LWIP_ASSERT_CORE_LOCKED(); sleeptime = sys_timeouts_sleeptime(); 8015bda: f008 fcb3 bl 801e544 8015bde: 60f8 str r0, [r7, #12] if (sleeptime == SYS_TIMEOUTS_SLEEPTIME_INFINITE) { 8015be0: 68fb ldr r3, [r7, #12] 8015be2: f1b3 3fff cmp.w r3, #4294967295 8015be6: d10b bne.n 8015c00 UNLOCK_TCPIP_CORE(); 8015be8: 4813 ldr r0, [pc, #76] ; (8015c38 ) 8015bea: f00b fd00 bl 80215ee sys_arch_mbox_fetch(mbox, msg, 0); 8015bee: 2200 movs r2, #0 8015bf0: 6839 ldr r1, [r7, #0] 8015bf2: 6878 ldr r0, [r7, #4] 8015bf4: f00b fbb8 bl 8021368 LOCK_TCPIP_CORE(); 8015bf8: 480f ldr r0, [pc, #60] ; (8015c38 ) 8015bfa: f00b fce9 bl 80215d0 return; 8015bfe: e018 b.n 8015c32 } else if (sleeptime == 0) { 8015c00: 68fb ldr r3, [r7, #12] 8015c02: 2b00 cmp r3, #0 8015c04: d102 bne.n 8015c0c sys_check_timeouts(); 8015c06: f008 fc63 bl 801e4d0 /* We try again to fetch a message from the mbox. */ goto again; 8015c0a: e7e6 b.n 8015bda } UNLOCK_TCPIP_CORE(); 8015c0c: 480a ldr r0, [pc, #40] ; (8015c38 ) 8015c0e: f00b fcee bl 80215ee res = sys_arch_mbox_fetch(mbox, msg, sleeptime); 8015c12: 68fa ldr r2, [r7, #12] 8015c14: 6839 ldr r1, [r7, #0] 8015c16: 6878 ldr r0, [r7, #4] 8015c18: f00b fba6 bl 8021368 8015c1c: 60b8 str r0, [r7, #8] LOCK_TCPIP_CORE(); 8015c1e: 4806 ldr r0, [pc, #24] ; (8015c38 ) 8015c20: f00b fcd6 bl 80215d0 if (res == SYS_ARCH_TIMEOUT) { 8015c24: 68bb ldr r3, [r7, #8] 8015c26: f1b3 3fff cmp.w r3, #4294967295 8015c2a: d102 bne.n 8015c32 /* If a SYS_ARCH_TIMEOUT value is returned, a timeout occurred before a message could be fetched. */ sys_check_timeouts(); 8015c2c: f008 fc50 bl 801e4d0 /* We try again to fetch a message from the mbox. */ goto again; 8015c30: e7d3 b.n 8015bda } } 8015c32: 3710 adds r7, #16 8015c34: 46bd mov sp, r7 8015c36: bd80 pop {r7, pc} 8015c38: 2401397c .word 0x2401397c 08015c3c : * * @param arg unused argument */ static void tcpip_thread(void *arg) { 8015c3c: b580 push {r7, lr} 8015c3e: b084 sub sp, #16 8015c40: af00 add r7, sp, #0 8015c42: 6078 str r0, [r7, #4] struct tcpip_msg *msg; LWIP_UNUSED_ARG(arg); LWIP_MARK_TCPIP_THREAD(); LOCK_TCPIP_CORE(); 8015c44: 4810 ldr r0, [pc, #64] ; (8015c88 ) 8015c46: f00b fcc3 bl 80215d0 if (tcpip_init_done != NULL) { 8015c4a: 4b10 ldr r3, [pc, #64] ; (8015c8c ) 8015c4c: 681b ldr r3, [r3, #0] 8015c4e: 2b00 cmp r3, #0 8015c50: d005 beq.n 8015c5e tcpip_init_done(tcpip_init_done_arg); 8015c52: 4b0e ldr r3, [pc, #56] ; (8015c8c ) 8015c54: 681b ldr r3, [r3, #0] 8015c56: 4a0e ldr r2, [pc, #56] ; (8015c90 ) 8015c58: 6812 ldr r2, [r2, #0] 8015c5a: 4610 mov r0, r2 8015c5c: 4798 blx r3 } while (1) { /* MAIN Loop */ LWIP_TCPIP_THREAD_ALIVE(); /* wait for a message, timeouts are processed while waiting */ TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg); 8015c5e: f107 030c add.w r3, r7, #12 8015c62: 4619 mov r1, r3 8015c64: 480b ldr r0, [pc, #44] ; (8015c94 ) 8015c66: f7ff ffb3 bl 8015bd0 if (msg == NULL) { 8015c6a: 68fb ldr r3, [r7, #12] 8015c6c: 2b00 cmp r3, #0 8015c6e: d106 bne.n 8015c7e LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: NULL\n")); LWIP_ASSERT("tcpip_thread: invalid message", 0); 8015c70: 4b09 ldr r3, [pc, #36] ; (8015c98 ) 8015c72: 2291 movs r2, #145 ; 0x91 8015c74: 4909 ldr r1, [pc, #36] ; (8015c9c ) 8015c76: 480a ldr r0, [pc, #40] ; (8015ca0 ) 8015c78: f00b fe86 bl 8021988 continue; 8015c7c: e003 b.n 8015c86 } tcpip_thread_handle_msg(msg); 8015c7e: 68fb ldr r3, [r7, #12] 8015c80: 4618 mov r0, r3 8015c82: f000 f80f bl 8015ca4 TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg); 8015c86: e7ea b.n 8015c5e 8015c88: 2401397c .word 0x2401397c 8015c8c: 24013970 .word 0x24013970 8015c90: 24013974 .word 0x24013974 8015c94: 24013978 .word 0x24013978 8015c98: 08023d14 .word 0x08023d14 8015c9c: 08023d44 .word 0x08023d44 8015ca0: 08023d64 .word 0x08023d64 08015ca4 : /* Handle a single tcpip_msg * This is in its own function for access by tests only. */ static void tcpip_thread_handle_msg(struct tcpip_msg *msg) { 8015ca4: b580 push {r7, lr} 8015ca6: b082 sub sp, #8 8015ca8: af00 add r7, sp, #0 8015caa: 6078 str r0, [r7, #4] switch (msg->type) { 8015cac: 687b ldr r3, [r7, #4] 8015cae: 781b ldrb r3, [r3, #0] 8015cb0: 2b02 cmp r3, #2 8015cb2: d026 beq.n 8015d02 8015cb4: 2b02 cmp r3, #2 8015cb6: dc2b bgt.n 8015d10 8015cb8: 2b00 cmp r3, #0 8015cba: d002 beq.n 8015cc2 8015cbc: 2b01 cmp r3, #1 8015cbe: d015 beq.n 8015cec 8015cc0: e026 b.n 8015d10 #endif /* !LWIP_TCPIP_CORE_LOCKING */ #if !LWIP_TCPIP_CORE_LOCKING_INPUT case TCPIP_MSG_INPKT: LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg)); if (msg->msg.inp.input_fn(msg->msg.inp.p, msg->msg.inp.netif) != ERR_OK) { 8015cc2: 687b ldr r3, [r7, #4] 8015cc4: 68db ldr r3, [r3, #12] 8015cc6: 687a ldr r2, [r7, #4] 8015cc8: 6850 ldr r0, [r2, #4] 8015cca: 687a ldr r2, [r7, #4] 8015ccc: 6892 ldr r2, [r2, #8] 8015cce: 4611 mov r1, r2 8015cd0: 4798 blx r3 8015cd2: 4603 mov r3, r0 8015cd4: 2b00 cmp r3, #0 8015cd6: d004 beq.n 8015ce2 pbuf_free(msg->msg.inp.p); 8015cd8: 687b ldr r3, [r7, #4] 8015cda: 685b ldr r3, [r3, #4] 8015cdc: 4618 mov r0, r3 8015cde: f001 ff0b bl 8017af8 } memp_free(MEMP_TCPIP_MSG_INPKT, msg); 8015ce2: 6879 ldr r1, [r7, #4] 8015ce4: 2009 movs r0, #9 8015ce6: f000 ff69 bl 8016bbc break; 8015cea: e018 b.n 8015d1e break; #endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ case TCPIP_MSG_CALLBACK: LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg)); msg->msg.cb.function(msg->msg.cb.ctx); 8015cec: 687b ldr r3, [r7, #4] 8015cee: 685b ldr r3, [r3, #4] 8015cf0: 687a ldr r2, [r7, #4] 8015cf2: 6892 ldr r2, [r2, #8] 8015cf4: 4610 mov r0, r2 8015cf6: 4798 blx r3 memp_free(MEMP_TCPIP_MSG_API, msg); 8015cf8: 6879 ldr r1, [r7, #4] 8015cfa: 2008 movs r0, #8 8015cfc: f000 ff5e bl 8016bbc break; 8015d00: e00d b.n 8015d1e case TCPIP_MSG_CALLBACK_STATIC: LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK_STATIC %p\n", (void *)msg)); msg->msg.cb.function(msg->msg.cb.ctx); 8015d02: 687b ldr r3, [r7, #4] 8015d04: 685b ldr r3, [r3, #4] 8015d06: 687a ldr r2, [r7, #4] 8015d08: 6892 ldr r2, [r2, #8] 8015d0a: 4610 mov r0, r2 8015d0c: 4798 blx r3 break; 8015d0e: e006 b.n 8015d1e default: LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type)); LWIP_ASSERT("tcpip_thread: invalid message", 0); 8015d10: 4b05 ldr r3, [pc, #20] ; (8015d28 ) 8015d12: 22cf movs r2, #207 ; 0xcf 8015d14: 4905 ldr r1, [pc, #20] ; (8015d2c ) 8015d16: 4806 ldr r0, [pc, #24] ; (8015d30 ) 8015d18: f00b fe36 bl 8021988 break; 8015d1c: bf00 nop } } 8015d1e: bf00 nop 8015d20: 3708 adds r7, #8 8015d22: 46bd mov sp, r7 8015d24: bd80 pop {r7, pc} 8015d26: bf00 nop 8015d28: 08023d14 .word 0x08023d14 8015d2c: 08023d44 .word 0x08023d44 8015d30: 08023d64 .word 0x08023d64 08015d34 : * @param inp the network interface on which the packet was received * @param input_fn input function to call */ err_t tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn) { 8015d34: b580 push {r7, lr} 8015d36: b086 sub sp, #24 8015d38: af00 add r7, sp, #0 8015d3a: 60f8 str r0, [r7, #12] 8015d3c: 60b9 str r1, [r7, #8] 8015d3e: 607a str r2, [r7, #4] UNLOCK_TCPIP_CORE(); return ret; #else /* LWIP_TCPIP_CORE_LOCKING_INPUT */ struct tcpip_msg *msg; LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); 8015d40: 481a ldr r0, [pc, #104] ; (8015dac ) 8015d42: f00b fb6c bl 802141e 8015d46: 4603 mov r3, r0 8015d48: 2b00 cmp r3, #0 8015d4a: d105 bne.n 8015d58 8015d4c: 4b18 ldr r3, [pc, #96] ; (8015db0 ) 8015d4e: 22fc movs r2, #252 ; 0xfc 8015d50: 4918 ldr r1, [pc, #96] ; (8015db4 ) 8015d52: 4819 ldr r0, [pc, #100] ; (8015db8 ) 8015d54: f00b fe18 bl 8021988 msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT); 8015d58: 2009 movs r0, #9 8015d5a: f000 feb9 bl 8016ad0 8015d5e: 6178 str r0, [r7, #20] if (msg == NULL) { 8015d60: 697b ldr r3, [r7, #20] 8015d62: 2b00 cmp r3, #0 8015d64: d102 bne.n 8015d6c return ERR_MEM; 8015d66: f04f 33ff mov.w r3, #4294967295 8015d6a: e01a b.n 8015da2 } msg->type = TCPIP_MSG_INPKT; 8015d6c: 697b ldr r3, [r7, #20] 8015d6e: 2200 movs r2, #0 8015d70: 701a strb r2, [r3, #0] msg->msg.inp.p = p; 8015d72: 697b ldr r3, [r7, #20] 8015d74: 68fa ldr r2, [r7, #12] 8015d76: 605a str r2, [r3, #4] msg->msg.inp.netif = inp; 8015d78: 697b ldr r3, [r7, #20] 8015d7a: 68ba ldr r2, [r7, #8] 8015d7c: 609a str r2, [r3, #8] msg->msg.inp.input_fn = input_fn; 8015d7e: 697b ldr r3, [r7, #20] 8015d80: 687a ldr r2, [r7, #4] 8015d82: 60da str r2, [r3, #12] if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) { 8015d84: 6979 ldr r1, [r7, #20] 8015d86: 4809 ldr r0, [pc, #36] ; (8015dac ) 8015d88: f00b fad4 bl 8021334 8015d8c: 4603 mov r3, r0 8015d8e: 2b00 cmp r3, #0 8015d90: d006 beq.n 8015da0 memp_free(MEMP_TCPIP_MSG_INPKT, msg); 8015d92: 6979 ldr r1, [r7, #20] 8015d94: 2009 movs r0, #9 8015d96: f000 ff11 bl 8016bbc return ERR_MEM; 8015d9a: f04f 33ff mov.w r3, #4294967295 8015d9e: e000 b.n 8015da2 } return ERR_OK; 8015da0: 2300 movs r3, #0 #endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */ } 8015da2: 4618 mov r0, r3 8015da4: 3718 adds r7, #24 8015da6: 46bd mov sp, r7 8015da8: bd80 pop {r7, pc} 8015daa: bf00 nop 8015dac: 24013978 .word 0x24013978 8015db0: 08023d14 .word 0x08023d14 8015db4: 08023d8c .word 0x08023d8c 8015db8: 08023d64 .word 0x08023d64 08015dbc : * NETIF_FLAG_ETHERNET flags) * @param inp the network interface on which the packet was received */ err_t tcpip_input(struct pbuf *p, struct netif *inp) { 8015dbc: b580 push {r7, lr} 8015dbe: b082 sub sp, #8 8015dc0: af00 add r7, sp, #0 8015dc2: 6078 str r0, [r7, #4] 8015dc4: 6039 str r1, [r7, #0] #if LWIP_ETHERNET if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) { 8015dc6: 683b ldr r3, [r7, #0] 8015dc8: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 8015dcc: f003 0318 and.w r3, r3, #24 8015dd0: 2b00 cmp r3, #0 8015dd2: d006 beq.n 8015de2 return tcpip_inpkt(p, inp, ethernet_input); 8015dd4: 4a08 ldr r2, [pc, #32] ; (8015df8 ) 8015dd6: 6839 ldr r1, [r7, #0] 8015dd8: 6878 ldr r0, [r7, #4] 8015dda: f7ff ffab bl 8015d34 8015dde: 4603 mov r3, r0 8015de0: e005 b.n 8015dee } else #endif /* LWIP_ETHERNET */ return tcpip_inpkt(p, inp, ip_input); 8015de2: 4a06 ldr r2, [pc, #24] ; (8015dfc ) 8015de4: 6839 ldr r1, [r7, #0] 8015de6: 6878 ldr r0, [r7, #4] 8015de8: f7ff ffa4 bl 8015d34 8015dec: 4603 mov r3, r0 } 8015dee: 4618 mov r0, r3 8015df0: 3708 adds r7, #8 8015df2: 46bd mov sp, r7 8015df4: bd80 pop {r7, pc} 8015df6: bf00 nop 8015df8: 08021121 .word 0x08021121 8015dfc: 08020029 .word 0x08020029 08015e00 : * * @see tcpip_callback */ err_t tcpip_try_callback(tcpip_callback_fn function, void *ctx) { 8015e00: b580 push {r7, lr} 8015e02: b084 sub sp, #16 8015e04: af00 add r7, sp, #0 8015e06: 6078 str r0, [r7, #4] 8015e08: 6039 str r1, [r7, #0] struct tcpip_msg *msg; LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); 8015e0a: 4819 ldr r0, [pc, #100] ; (8015e70 ) 8015e0c: f00b fb07 bl 802141e 8015e10: 4603 mov r3, r0 8015e12: 2b00 cmp r3, #0 8015e14: d106 bne.n 8015e24 8015e16: 4b17 ldr r3, [pc, #92] ; (8015e74 ) 8015e18: f240 125d movw r2, #349 ; 0x15d 8015e1c: 4916 ldr r1, [pc, #88] ; (8015e78 ) 8015e1e: 4817 ldr r0, [pc, #92] ; (8015e7c ) 8015e20: f00b fdb2 bl 8021988 msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); 8015e24: 2008 movs r0, #8 8015e26: f000 fe53 bl 8016ad0 8015e2a: 60f8 str r0, [r7, #12] if (msg == NULL) { 8015e2c: 68fb ldr r3, [r7, #12] 8015e2e: 2b00 cmp r3, #0 8015e30: d102 bne.n 8015e38 return ERR_MEM; 8015e32: f04f 33ff mov.w r3, #4294967295 8015e36: e017 b.n 8015e68 } msg->type = TCPIP_MSG_CALLBACK; 8015e38: 68fb ldr r3, [r7, #12] 8015e3a: 2201 movs r2, #1 8015e3c: 701a strb r2, [r3, #0] msg->msg.cb.function = function; 8015e3e: 68fb ldr r3, [r7, #12] 8015e40: 687a ldr r2, [r7, #4] 8015e42: 605a str r2, [r3, #4] msg->msg.cb.ctx = ctx; 8015e44: 68fb ldr r3, [r7, #12] 8015e46: 683a ldr r2, [r7, #0] 8015e48: 609a str r2, [r3, #8] if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) { 8015e4a: 68f9 ldr r1, [r7, #12] 8015e4c: 4808 ldr r0, [pc, #32] ; (8015e70 ) 8015e4e: f00b fa71 bl 8021334 8015e52: 4603 mov r3, r0 8015e54: 2b00 cmp r3, #0 8015e56: d006 beq.n 8015e66 memp_free(MEMP_TCPIP_MSG_API, msg); 8015e58: 68f9 ldr r1, [r7, #12] 8015e5a: 2008 movs r0, #8 8015e5c: f000 feae bl 8016bbc return ERR_MEM; 8015e60: f04f 33ff mov.w r3, #4294967295 8015e64: e000 b.n 8015e68 } return ERR_OK; 8015e66: 2300 movs r3, #0 } 8015e68: 4618 mov r0, r3 8015e6a: 3710 adds r7, #16 8015e6c: 46bd mov sp, r7 8015e6e: bd80 pop {r7, pc} 8015e70: 24013978 .word 0x24013978 8015e74: 08023d14 .word 0x08023d14 8015e78: 08023d8c .word 0x08023d8c 8015e7c: 08023d64 .word 0x08023d64 08015e80 : * @param sem semaphore to wait on * @return ERR_OK if the function was called, another err_t if not */ err_t tcpip_send_msg_wait_sem(tcpip_callback_fn fn, void *apimsg, sys_sem_t *sem) { 8015e80: b580 push {r7, lr} 8015e82: b084 sub sp, #16 8015e84: af00 add r7, sp, #0 8015e86: 60f8 str r0, [r7, #12] 8015e88: 60b9 str r1, [r7, #8] 8015e8a: 607a str r2, [r7, #4] #if LWIP_TCPIP_CORE_LOCKING LWIP_UNUSED_ARG(sem); LOCK_TCPIP_CORE(); 8015e8c: 4806 ldr r0, [pc, #24] ; (8015ea8 ) 8015e8e: f00b fb9f bl 80215d0 fn(apimsg); 8015e92: 68fb ldr r3, [r7, #12] 8015e94: 68b8 ldr r0, [r7, #8] 8015e96: 4798 blx r3 UNLOCK_TCPIP_CORE(); 8015e98: 4803 ldr r0, [pc, #12] ; (8015ea8 ) 8015e9a: f00b fba8 bl 80215ee return ERR_OK; 8015e9e: 2300 movs r3, #0 sys_mbox_post(&tcpip_mbox, &TCPIP_MSG_VAR_REF(msg)); sys_arch_sem_wait(sem, 0); TCPIP_MSG_VAR_FREE(msg); return ERR_OK; #endif /* LWIP_TCPIP_CORE_LOCKING */ } 8015ea0: 4618 mov r0, r3 8015ea2: 3710 adds r7, #16 8015ea4: 46bd mov sp, r7 8015ea6: bd80 pop {r7, pc} 8015ea8: 2401397c .word 0x2401397c 08015eac : * @param initfunc a function to call when tcpip_thread is running and finished initializing * @param arg argument to pass to initfunc */ void tcpip_init(tcpip_init_done_fn initfunc, void *arg) { 8015eac: b580 push {r7, lr} 8015eae: b084 sub sp, #16 8015eb0: af02 add r7, sp, #8 8015eb2: 6078 str r0, [r7, #4] 8015eb4: 6039 str r1, [r7, #0] lwip_init(); 8015eb6: f000 f92d bl 8016114 tcpip_init_done = initfunc; 8015eba: 4a17 ldr r2, [pc, #92] ; (8015f18 ) 8015ebc: 687b ldr r3, [r7, #4] 8015ebe: 6013 str r3, [r2, #0] tcpip_init_done_arg = arg; 8015ec0: 4a16 ldr r2, [pc, #88] ; (8015f1c ) 8015ec2: 683b ldr r3, [r7, #0] 8015ec4: 6013 str r3, [r2, #0] if (sys_mbox_new(&tcpip_mbox, TCPIP_MBOX_SIZE) != ERR_OK) { 8015ec6: 2106 movs r1, #6 8015ec8: 4815 ldr r0, [pc, #84] ; (8015f20 ) 8015eca: f00b f9ff bl 80212cc 8015ece: 4603 mov r3, r0 8015ed0: 2b00 cmp r3, #0 8015ed2: d006 beq.n 8015ee2 LWIP_ASSERT("failed to create tcpip_thread mbox", 0); 8015ed4: 4b13 ldr r3, [pc, #76] ; (8015f24 ) 8015ed6: f240 2261 movw r2, #609 ; 0x261 8015eda: 4913 ldr r1, [pc, #76] ; (8015f28 ) 8015edc: 4813 ldr r0, [pc, #76] ; (8015f2c ) 8015ede: f00b fd53 bl 8021988 } #if LWIP_TCPIP_CORE_LOCKING if (sys_mutex_new(&lock_tcpip_core) != ERR_OK) { 8015ee2: 4813 ldr r0, [pc, #76] ; (8015f30 ) 8015ee4: f00b fb58 bl 8021598 8015ee8: 4603 mov r3, r0 8015eea: 2b00 cmp r3, #0 8015eec: d006 beq.n 8015efc LWIP_ASSERT("failed to create lock_tcpip_core", 0); 8015eee: 4b0d ldr r3, [pc, #52] ; (8015f24 ) 8015ef0: f240 2265 movw r2, #613 ; 0x265 8015ef4: 490f ldr r1, [pc, #60] ; (8015f34 ) 8015ef6: 480d ldr r0, [pc, #52] ; (8015f2c ) 8015ef8: f00b fd46 bl 8021988 } #endif /* LWIP_TCPIP_CORE_LOCKING */ sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO); 8015efc: 2300 movs r3, #0 8015efe: 9300 str r3, [sp, #0] 8015f00: f44f 6380 mov.w r3, #1024 ; 0x400 8015f04: 2200 movs r2, #0 8015f06: 490c ldr r1, [pc, #48] ; (8015f38 ) 8015f08: 480c ldr r0, [pc, #48] ; (8015f3c ) 8015f0a: f00b fb7d bl 8021608 } 8015f0e: bf00 nop 8015f10: 3708 adds r7, #8 8015f12: 46bd mov sp, r7 8015f14: bd80 pop {r7, pc} 8015f16: bf00 nop 8015f18: 24013970 .word 0x24013970 8015f1c: 24013974 .word 0x24013974 8015f20: 24013978 .word 0x24013978 8015f24: 08023d14 .word 0x08023d14 8015f28: 08023d9c .word 0x08023d9c 8015f2c: 08023d64 .word 0x08023d64 8015f30: 2401397c .word 0x2401397c 8015f34: 08023dc0 .word 0x08023dc0 8015f38: 08015c3d .word 0x08015c3d 8015f3c: 08023de4 .word 0x08023de4 08015f40 : * @param n u16_t in host byte order * @return n in network byte order */ u16_t lwip_htons(u16_t n) { 8015f40: b480 push {r7} 8015f42: b083 sub sp, #12 8015f44: af00 add r7, sp, #0 8015f46: 4603 mov r3, r0 8015f48: 80fb strh r3, [r7, #6] return PP_HTONS(n); 8015f4a: 88fb ldrh r3, [r7, #6] 8015f4c: 021b lsls r3, r3, #8 8015f4e: b21a sxth r2, r3 8015f50: 88fb ldrh r3, [r7, #6] 8015f52: 0a1b lsrs r3, r3, #8 8015f54: b29b uxth r3, r3 8015f56: b21b sxth r3, r3 8015f58: 4313 orrs r3, r2 8015f5a: b21b sxth r3, r3 8015f5c: b29b uxth r3, r3 } 8015f5e: 4618 mov r0, r3 8015f60: 370c adds r7, #12 8015f62: 46bd mov sp, r7 8015f64: f85d 7b04 ldr.w r7, [sp], #4 8015f68: 4770 bx lr 08015f6a : * @param n u32_t in host byte order * @return n in network byte order */ u32_t lwip_htonl(u32_t n) { 8015f6a: b480 push {r7} 8015f6c: b083 sub sp, #12 8015f6e: af00 add r7, sp, #0 8015f70: 6078 str r0, [r7, #4] return PP_HTONL(n); 8015f72: 687b ldr r3, [r7, #4] 8015f74: 061a lsls r2, r3, #24 8015f76: 687b ldr r3, [r7, #4] 8015f78: 021b lsls r3, r3, #8 8015f7a: f403 037f and.w r3, r3, #16711680 ; 0xff0000 8015f7e: 431a orrs r2, r3 8015f80: 687b ldr r3, [r7, #4] 8015f82: 0a1b lsrs r3, r3, #8 8015f84: f403 437f and.w r3, r3, #65280 ; 0xff00 8015f88: 431a orrs r2, r3 8015f8a: 687b ldr r3, [r7, #4] 8015f8c: 0e1b lsrs r3, r3, #24 8015f8e: 4313 orrs r3, r2 } 8015f90: 4618 mov r0, r3 8015f92: 370c adds r7, #12 8015f94: 46bd mov sp, r7 8015f96: f85d 7b04 ldr.w r7, [sp], #4 8015f9a: 4770 bx lr 08015f9c : * @param len length of data to be summed * @return host order (!) lwip checksum (non-inverted Internet sum) */ u16_t lwip_standard_chksum(const void *dataptr, int len) { 8015f9c: b480 push {r7} 8015f9e: b089 sub sp, #36 ; 0x24 8015fa0: af00 add r7, sp, #0 8015fa2: 6078 str r0, [r7, #4] 8015fa4: 6039 str r1, [r7, #0] const u8_t *pb = (const u8_t *)dataptr; 8015fa6: 687b ldr r3, [r7, #4] 8015fa8: 61fb str r3, [r7, #28] const u16_t *ps; u16_t t = 0; 8015faa: 2300 movs r3, #0 8015fac: 81fb strh r3, [r7, #14] u32_t sum = 0; 8015fae: 2300 movs r3, #0 8015fb0: 617b str r3, [r7, #20] int odd = ((mem_ptr_t)pb & 1); 8015fb2: 69fb ldr r3, [r7, #28] 8015fb4: f003 0301 and.w r3, r3, #1 8015fb8: 613b str r3, [r7, #16] /* Get aligned to u16_t */ if (odd && len > 0) { 8015fba: 693b ldr r3, [r7, #16] 8015fbc: 2b00 cmp r3, #0 8015fbe: d00d beq.n 8015fdc 8015fc0: 683b ldr r3, [r7, #0] 8015fc2: 2b00 cmp r3, #0 8015fc4: dd0a ble.n 8015fdc ((u8_t *)&t)[1] = *pb++; 8015fc6: 69fa ldr r2, [r7, #28] 8015fc8: 1c53 adds r3, r2, #1 8015fca: 61fb str r3, [r7, #28] 8015fcc: f107 030e add.w r3, r7, #14 8015fd0: 3301 adds r3, #1 8015fd2: 7812 ldrb r2, [r2, #0] 8015fd4: 701a strb r2, [r3, #0] len--; 8015fd6: 683b ldr r3, [r7, #0] 8015fd8: 3b01 subs r3, #1 8015fda: 603b str r3, [r7, #0] } /* Add the bulk of the data */ ps = (const u16_t *)(const void *)pb; 8015fdc: 69fb ldr r3, [r7, #28] 8015fde: 61bb str r3, [r7, #24] while (len > 1) { 8015fe0: e00a b.n 8015ff8 sum += *ps++; 8015fe2: 69bb ldr r3, [r7, #24] 8015fe4: 1c9a adds r2, r3, #2 8015fe6: 61ba str r2, [r7, #24] 8015fe8: 881b ldrh r3, [r3, #0] 8015fea: 461a mov r2, r3 8015fec: 697b ldr r3, [r7, #20] 8015fee: 4413 add r3, r2 8015ff0: 617b str r3, [r7, #20] len -= 2; 8015ff2: 683b ldr r3, [r7, #0] 8015ff4: 3b02 subs r3, #2 8015ff6: 603b str r3, [r7, #0] while (len > 1) { 8015ff8: 683b ldr r3, [r7, #0] 8015ffa: 2b01 cmp r3, #1 8015ffc: dcf1 bgt.n 8015fe2 } /* Consume left-over byte, if any */ if (len > 0) { 8015ffe: 683b ldr r3, [r7, #0] 8016000: 2b00 cmp r3, #0 8016002: dd04 ble.n 801600e ((u8_t *)&t)[0] = *(const u8_t *)ps; 8016004: f107 030e add.w r3, r7, #14 8016008: 69ba ldr r2, [r7, #24] 801600a: 7812 ldrb r2, [r2, #0] 801600c: 701a strb r2, [r3, #0] } /* Add end bytes */ sum += t; 801600e: 89fb ldrh r3, [r7, #14] 8016010: 461a mov r2, r3 8016012: 697b ldr r3, [r7, #20] 8016014: 4413 add r3, r2 8016016: 617b str r3, [r7, #20] /* Fold 32-bit sum to 16 bits calling this twice is probably faster than if statements... */ sum = FOLD_U32T(sum); 8016018: 697b ldr r3, [r7, #20] 801601a: 0c1a lsrs r2, r3, #16 801601c: 697b ldr r3, [r7, #20] 801601e: b29b uxth r3, r3 8016020: 4413 add r3, r2 8016022: 617b str r3, [r7, #20] sum = FOLD_U32T(sum); 8016024: 697b ldr r3, [r7, #20] 8016026: 0c1a lsrs r2, r3, #16 8016028: 697b ldr r3, [r7, #20] 801602a: b29b uxth r3, r3 801602c: 4413 add r3, r2 801602e: 617b str r3, [r7, #20] /* Swap if alignment was odd */ if (odd) { 8016030: 693b ldr r3, [r7, #16] 8016032: 2b00 cmp r3, #0 8016034: d007 beq.n 8016046 sum = SWAP_BYTES_IN_WORD(sum); 8016036: 697b ldr r3, [r7, #20] 8016038: 021b lsls r3, r3, #8 801603a: b29a uxth r2, r3 801603c: 697b ldr r3, [r7, #20] 801603e: 0a1b lsrs r3, r3, #8 8016040: b2db uxtb r3, r3 8016042: 4313 orrs r3, r2 8016044: 617b str r3, [r7, #20] } return (u16_t)sum; 8016046: 697b ldr r3, [r7, #20] 8016048: b29b uxth r3, r3 } 801604a: 4618 mov r0, r3 801604c: 3724 adds r7, #36 ; 0x24 801604e: 46bd mov sp, r7 8016050: f85d 7b04 ldr.w r7, [sp], #4 8016054: 4770 bx lr 08016056 : * @return checksum (as u16_t) to be saved directly in the protocol header */ u16_t inet_chksum(const void *dataptr, u16_t len) { 8016056: b580 push {r7, lr} 8016058: b082 sub sp, #8 801605a: af00 add r7, sp, #0 801605c: 6078 str r0, [r7, #4] 801605e: 460b mov r3, r1 8016060: 807b strh r3, [r7, #2] return (u16_t)~(unsigned int)LWIP_CHKSUM(dataptr, len); 8016062: 887b ldrh r3, [r7, #2] 8016064: 4619 mov r1, r3 8016066: 6878 ldr r0, [r7, #4] 8016068: f7ff ff98 bl 8015f9c 801606c: 4603 mov r3, r0 801606e: 43db mvns r3, r3 8016070: b29b uxth r3, r3 } 8016072: 4618 mov r0, r3 8016074: 3708 adds r7, #8 8016076: 46bd mov sp, r7 8016078: bd80 pop {r7, pc} 0801607a : * @param p pbuf chain over that the checksum should be calculated * @return checksum (as u16_t) to be saved directly in the protocol header */ u16_t inet_chksum_pbuf(struct pbuf *p) { 801607a: b580 push {r7, lr} 801607c: b086 sub sp, #24 801607e: af00 add r7, sp, #0 8016080: 6078 str r0, [r7, #4] u32_t acc; struct pbuf *q; int swapped = 0; 8016082: 2300 movs r3, #0 8016084: 60fb str r3, [r7, #12] acc = 0; 8016086: 2300 movs r3, #0 8016088: 617b str r3, [r7, #20] for (q = p; q != NULL; q = q->next) { 801608a: 687b ldr r3, [r7, #4] 801608c: 613b str r3, [r7, #16] 801608e: e02b b.n 80160e8 acc += LWIP_CHKSUM(q->payload, q->len); 8016090: 693b ldr r3, [r7, #16] 8016092: 685a ldr r2, [r3, #4] 8016094: 693b ldr r3, [r7, #16] 8016096: 895b ldrh r3, [r3, #10] 8016098: 4619 mov r1, r3 801609a: 4610 mov r0, r2 801609c: f7ff ff7e bl 8015f9c 80160a0: 4603 mov r3, r0 80160a2: 461a mov r2, r3 80160a4: 697b ldr r3, [r7, #20] 80160a6: 4413 add r3, r2 80160a8: 617b str r3, [r7, #20] acc = FOLD_U32T(acc); 80160aa: 697b ldr r3, [r7, #20] 80160ac: 0c1a lsrs r2, r3, #16 80160ae: 697b ldr r3, [r7, #20] 80160b0: b29b uxth r3, r3 80160b2: 4413 add r3, r2 80160b4: 617b str r3, [r7, #20] if (q->len % 2 != 0) { 80160b6: 693b ldr r3, [r7, #16] 80160b8: 895b ldrh r3, [r3, #10] 80160ba: f003 0301 and.w r3, r3, #1 80160be: b29b uxth r3, r3 80160c0: 2b00 cmp r3, #0 80160c2: d00e beq.n 80160e2 swapped = !swapped; 80160c4: 68fb ldr r3, [r7, #12] 80160c6: 2b00 cmp r3, #0 80160c8: bf0c ite eq 80160ca: 2301 moveq r3, #1 80160cc: 2300 movne r3, #0 80160ce: b2db uxtb r3, r3 80160d0: 60fb str r3, [r7, #12] acc = SWAP_BYTES_IN_WORD(acc); 80160d2: 697b ldr r3, [r7, #20] 80160d4: 021b lsls r3, r3, #8 80160d6: b29a uxth r2, r3 80160d8: 697b ldr r3, [r7, #20] 80160da: 0a1b lsrs r3, r3, #8 80160dc: b2db uxtb r3, r3 80160de: 4313 orrs r3, r2 80160e0: 617b str r3, [r7, #20] for (q = p; q != NULL; q = q->next) { 80160e2: 693b ldr r3, [r7, #16] 80160e4: 681b ldr r3, [r3, #0] 80160e6: 613b str r3, [r7, #16] 80160e8: 693b ldr r3, [r7, #16] 80160ea: 2b00 cmp r3, #0 80160ec: d1d0 bne.n 8016090 } } if (swapped) { 80160ee: 68fb ldr r3, [r7, #12] 80160f0: 2b00 cmp r3, #0 80160f2: d007 beq.n 8016104 acc = SWAP_BYTES_IN_WORD(acc); 80160f4: 697b ldr r3, [r7, #20] 80160f6: 021b lsls r3, r3, #8 80160f8: b29a uxth r2, r3 80160fa: 697b ldr r3, [r7, #20] 80160fc: 0a1b lsrs r3, r3, #8 80160fe: b2db uxtb r3, r3 8016100: 4313 orrs r3, r2 8016102: 617b str r3, [r7, #20] } return (u16_t)~(acc & 0xffffUL); 8016104: 697b ldr r3, [r7, #20] 8016106: b29b uxth r3, r3 8016108: 43db mvns r3, r3 801610a: b29b uxth r3, r3 } 801610c: 4618 mov r0, r3 801610e: 3718 adds r7, #24 8016110: 46bd mov sp, r7 8016112: bd80 pop {r7, pc} 08016114 : * Initialize all modules. * Use this in NO_SYS mode. Use tcpip_init() otherwise. */ void lwip_init(void) { 8016114: b580 push {r7, lr} 8016116: b082 sub sp, #8 8016118: af00 add r7, sp, #0 #ifndef LWIP_SKIP_CONST_CHECK int a = 0; 801611a: 2300 movs r3, #0 801611c: 607b str r3, [r7, #4] #endif /* Modules initialization */ stats_init(); #if !NO_SYS sys_init(); 801611e: f00b fa2d bl 802157c #endif /* !NO_SYS */ mem_init(); 8016122: f000 f8d9 bl 80162d8 memp_init(); 8016126: f000 fc5d bl 80169e4 pbuf_init(); netif_init(); 801612a: f000 fd71 bl 8016c10 #endif /* LWIP_IPV4 */ #if LWIP_RAW raw_init(); #endif /* LWIP_RAW */ #if LWIP_UDP udp_init(); 801612e: f008 fa41 bl 801e5b4 #endif /* LWIP_UDP */ #if LWIP_TCP tcp_init(); 8016132: f001 ff7b bl 801802c #if PPP_SUPPORT ppp_init(); #endif #if LWIP_TIMERS sys_timeouts_init(); 8016136: f008 f983 bl 801e440 #endif /* LWIP_TIMERS */ } 801613a: bf00 nop 801613c: 3708 adds r7, #8 801613e: 46bd mov sp, r7 8016140: bd80 pop {r7, pc} ... 08016144 : #define mem_overflow_check_element(mem) #endif /* MEM_OVERFLOW_CHECK */ static struct mem * ptr_to_mem(mem_size_t ptr) { 8016144: b480 push {r7} 8016146: b083 sub sp, #12 8016148: af00 add r7, sp, #0 801614a: 4603 mov r3, r0 801614c: 80fb strh r3, [r7, #6] return (struct mem *)(void *)&ram[ptr]; 801614e: 4b05 ldr r3, [pc, #20] ; (8016164 ) 8016150: 681a ldr r2, [r3, #0] 8016152: 88fb ldrh r3, [r7, #6] 8016154: 4413 add r3, r2 } 8016156: 4618 mov r0, r3 8016158: 370c adds r7, #12 801615a: 46bd mov sp, r7 801615c: f85d 7b04 ldr.w r7, [sp], #4 8016160: 4770 bx lr 8016162: bf00 nop 8016164: 24013998 .word 0x24013998 08016168 : static mem_size_t mem_to_ptr(void *mem) { 8016168: b480 push {r7} 801616a: b083 sub sp, #12 801616c: af00 add r7, sp, #0 801616e: 6078 str r0, [r7, #4] return (mem_size_t)((u8_t *)mem - ram); 8016170: 4b05 ldr r3, [pc, #20] ; (8016188 ) 8016172: 681b ldr r3, [r3, #0] 8016174: 687a ldr r2, [r7, #4] 8016176: 1ad3 subs r3, r2, r3 8016178: b29b uxth r3, r3 } 801617a: 4618 mov r0, r3 801617c: 370c adds r7, #12 801617e: 46bd mov sp, r7 8016180: f85d 7b04 ldr.w r7, [sp], #4 8016184: 4770 bx lr 8016186: bf00 nop 8016188: 24013998 .word 0x24013998 0801618c : * This assumes access to the heap is protected by the calling function * already. */ static void plug_holes(struct mem *mem) { 801618c: b590 push {r4, r7, lr} 801618e: b085 sub sp, #20 8016190: af00 add r7, sp, #0 8016192: 6078 str r0, [r7, #4] struct mem *nmem; struct mem *pmem; LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); 8016194: 4b47 ldr r3, [pc, #284] ; (80162b4 ) 8016196: 681b ldr r3, [r3, #0] 8016198: 687a ldr r2, [r7, #4] 801619a: 429a cmp r2, r3 801619c: d206 bcs.n 80161ac 801619e: 4b46 ldr r3, [pc, #280] ; (80162b8 ) 80161a0: f240 12df movw r2, #479 ; 0x1df 80161a4: 4945 ldr r1, [pc, #276] ; (80162bc ) 80161a6: 4846 ldr r0, [pc, #280] ; (80162c0 ) 80161a8: f00b fbee bl 8021988 LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); 80161ac: 4b45 ldr r3, [pc, #276] ; (80162c4 ) 80161ae: 681b ldr r3, [r3, #0] 80161b0: 687a ldr r2, [r7, #4] 80161b2: 429a cmp r2, r3 80161b4: d306 bcc.n 80161c4 80161b6: 4b40 ldr r3, [pc, #256] ; (80162b8 ) 80161b8: f44f 72f0 mov.w r2, #480 ; 0x1e0 80161bc: 4942 ldr r1, [pc, #264] ; (80162c8 ) 80161be: 4840 ldr r0, [pc, #256] ; (80162c0 ) 80161c0: f00b fbe2 bl 8021988 LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); 80161c4: 687b ldr r3, [r7, #4] 80161c6: 791b ldrb r3, [r3, #4] 80161c8: 2b00 cmp r3, #0 80161ca: d006 beq.n 80161da 80161cc: 4b3a ldr r3, [pc, #232] ; (80162b8 ) 80161ce: f240 12e1 movw r2, #481 ; 0x1e1 80161d2: 493e ldr r1, [pc, #248] ; (80162cc ) 80161d4: 483a ldr r0, [pc, #232] ; (80162c0 ) 80161d6: f00b fbd7 bl 8021988 /* plug hole forward */ LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED); 80161da: 687b ldr r3, [r7, #4] 80161dc: 881b ldrh r3, [r3, #0] 80161de: f647 52e8 movw r2, #32232 ; 0x7de8 80161e2: 4293 cmp r3, r2 80161e4: d906 bls.n 80161f4 80161e6: 4b34 ldr r3, [pc, #208] ; (80162b8 ) 80161e8: f44f 72f2 mov.w r2, #484 ; 0x1e4 80161ec: 4938 ldr r1, [pc, #224] ; (80162d0 ) 80161ee: 4834 ldr r0, [pc, #208] ; (80162c0 ) 80161f0: f00b fbca bl 8021988 nmem = ptr_to_mem(mem->next); 80161f4: 687b ldr r3, [r7, #4] 80161f6: 881b ldrh r3, [r3, #0] 80161f8: 4618 mov r0, r3 80161fa: f7ff ffa3 bl 8016144 80161fe: 60f8 str r0, [r7, #12] if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { 8016200: 687a ldr r2, [r7, #4] 8016202: 68fb ldr r3, [r7, #12] 8016204: 429a cmp r2, r3 8016206: d025 beq.n 8016254 8016208: 68fb ldr r3, [r7, #12] 801620a: 791b ldrb r3, [r3, #4] 801620c: 2b00 cmp r3, #0 801620e: d121 bne.n 8016254 8016210: 4b2c ldr r3, [pc, #176] ; (80162c4 ) 8016212: 681b ldr r3, [r3, #0] 8016214: 68fa ldr r2, [r7, #12] 8016216: 429a cmp r2, r3 8016218: d01c beq.n 8016254 /* if mem->next is unused and not end of ram, combine mem and mem->next */ if (lfree == nmem) { 801621a: 4b2e ldr r3, [pc, #184] ; (80162d4 ) 801621c: 681b ldr r3, [r3, #0] 801621e: 68fa ldr r2, [r7, #12] 8016220: 429a cmp r2, r3 8016222: d102 bne.n 801622a lfree = mem; 8016224: 4a2b ldr r2, [pc, #172] ; (80162d4 ) 8016226: 687b ldr r3, [r7, #4] 8016228: 6013 str r3, [r2, #0] } mem->next = nmem->next; 801622a: 68fb ldr r3, [r7, #12] 801622c: 881a ldrh r2, [r3, #0] 801622e: 687b ldr r3, [r7, #4] 8016230: 801a strh r2, [r3, #0] if (nmem->next != MEM_SIZE_ALIGNED) { 8016232: 68fb ldr r3, [r7, #12] 8016234: 881b ldrh r3, [r3, #0] 8016236: f647 52e8 movw r2, #32232 ; 0x7de8 801623a: 4293 cmp r3, r2 801623c: d00a beq.n 8016254 ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem); 801623e: 68fb ldr r3, [r7, #12] 8016240: 881b ldrh r3, [r3, #0] 8016242: 4618 mov r0, r3 8016244: f7ff ff7e bl 8016144 8016248: 4604 mov r4, r0 801624a: 6878 ldr r0, [r7, #4] 801624c: f7ff ff8c bl 8016168 8016250: 4603 mov r3, r0 8016252: 8063 strh r3, [r4, #2] } } /* plug hole backward */ pmem = ptr_to_mem(mem->prev); 8016254: 687b ldr r3, [r7, #4] 8016256: 885b ldrh r3, [r3, #2] 8016258: 4618 mov r0, r3 801625a: f7ff ff73 bl 8016144 801625e: 60b8 str r0, [r7, #8] if (pmem != mem && pmem->used == 0) { 8016260: 68ba ldr r2, [r7, #8] 8016262: 687b ldr r3, [r7, #4] 8016264: 429a cmp r2, r3 8016266: d020 beq.n 80162aa 8016268: 68bb ldr r3, [r7, #8] 801626a: 791b ldrb r3, [r3, #4] 801626c: 2b00 cmp r3, #0 801626e: d11c bne.n 80162aa /* if mem->prev is unused, combine mem and mem->prev */ if (lfree == mem) { 8016270: 4b18 ldr r3, [pc, #96] ; (80162d4 ) 8016272: 681b ldr r3, [r3, #0] 8016274: 687a ldr r2, [r7, #4] 8016276: 429a cmp r2, r3 8016278: d102 bne.n 8016280 lfree = pmem; 801627a: 4a16 ldr r2, [pc, #88] ; (80162d4 ) 801627c: 68bb ldr r3, [r7, #8] 801627e: 6013 str r3, [r2, #0] } pmem->next = mem->next; 8016280: 687b ldr r3, [r7, #4] 8016282: 881a ldrh r2, [r3, #0] 8016284: 68bb ldr r3, [r7, #8] 8016286: 801a strh r2, [r3, #0] if (mem->next != MEM_SIZE_ALIGNED) { 8016288: 687b ldr r3, [r7, #4] 801628a: 881b ldrh r3, [r3, #0] 801628c: f647 52e8 movw r2, #32232 ; 0x7de8 8016290: 4293 cmp r3, r2 8016292: d00a beq.n 80162aa ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem); 8016294: 687b ldr r3, [r7, #4] 8016296: 881b ldrh r3, [r3, #0] 8016298: 4618 mov r0, r3 801629a: f7ff ff53 bl 8016144 801629e: 4604 mov r4, r0 80162a0: 68b8 ldr r0, [r7, #8] 80162a2: f7ff ff61 bl 8016168 80162a6: 4603 mov r3, r0 80162a8: 8063 strh r3, [r4, #2] } } } 80162aa: bf00 nop 80162ac: 3714 adds r7, #20 80162ae: 46bd mov sp, r7 80162b0: bd90 pop {r4, r7, pc} 80162b2: bf00 nop 80162b4: 24013998 .word 0x24013998 80162b8: 08023df4 .word 0x08023df4 80162bc: 08023e24 .word 0x08023e24 80162c0: 08023e3c .word 0x08023e3c 80162c4: 2401399c .word 0x2401399c 80162c8: 08023e64 .word 0x08023e64 80162cc: 08023e80 .word 0x08023e80 80162d0: 08023e9c .word 0x08023e9c 80162d4: 240139a4 .word 0x240139a4 080162d8 : /** * Zero the heap and initialize start, end and lowest-free */ void mem_init(void) { 80162d8: b580 push {r7, lr} 80162da: b082 sub sp, #8 80162dc: af00 add r7, sp, #0 LWIP_ASSERT("Sanity check alignment", (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0); /* align the heap */ ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER); 80162de: 4b1d ldr r3, [pc, #116] ; (8016354 ) 80162e0: 4a1d ldr r2, [pc, #116] ; (8016358 ) 80162e2: 601a str r2, [r3, #0] /* initialize the start of the heap */ mem = (struct mem *)(void *)ram; 80162e4: 4b1b ldr r3, [pc, #108] ; (8016354 ) 80162e6: 681b ldr r3, [r3, #0] 80162e8: 607b str r3, [r7, #4] mem->next = MEM_SIZE_ALIGNED; 80162ea: 687b ldr r3, [r7, #4] 80162ec: f647 52e8 movw r2, #32232 ; 0x7de8 80162f0: 801a strh r2, [r3, #0] mem->prev = 0; 80162f2: 687b ldr r3, [r7, #4] 80162f4: 2200 movs r2, #0 80162f6: 805a strh r2, [r3, #2] mem->used = 0; 80162f8: 687b ldr r3, [r7, #4] 80162fa: 2200 movs r2, #0 80162fc: 711a strb r2, [r3, #4] /* initialize the end of the heap */ ram_end = ptr_to_mem(MEM_SIZE_ALIGNED); 80162fe: f647 50e8 movw r0, #32232 ; 0x7de8 8016302: f7ff ff1f bl 8016144 8016306: 4603 mov r3, r0 8016308: 4a14 ldr r2, [pc, #80] ; (801635c ) 801630a: 6013 str r3, [r2, #0] ram_end->used = 1; 801630c: 4b13 ldr r3, [pc, #76] ; (801635c ) 801630e: 681b ldr r3, [r3, #0] 8016310: 2201 movs r2, #1 8016312: 711a strb r2, [r3, #4] ram_end->next = MEM_SIZE_ALIGNED; 8016314: 4b11 ldr r3, [pc, #68] ; (801635c ) 8016316: 681b ldr r3, [r3, #0] 8016318: f647 52e8 movw r2, #32232 ; 0x7de8 801631c: 801a strh r2, [r3, #0] ram_end->prev = MEM_SIZE_ALIGNED; 801631e: 4b0f ldr r3, [pc, #60] ; (801635c ) 8016320: 681b ldr r3, [r3, #0] 8016322: f647 52e8 movw r2, #32232 ; 0x7de8 8016326: 805a strh r2, [r3, #2] MEM_SANITY(); /* initialize the lowest-free pointer to the start of the heap */ lfree = (struct mem *)(void *)ram; 8016328: 4b0a ldr r3, [pc, #40] ; (8016354 ) 801632a: 681b ldr r3, [r3, #0] 801632c: 4a0c ldr r2, [pc, #48] ; (8016360 ) 801632e: 6013 str r3, [r2, #0] MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED); if (sys_mutex_new(&mem_mutex) != ERR_OK) { 8016330: 480c ldr r0, [pc, #48] ; (8016364 ) 8016332: f00b f931 bl 8021598 8016336: 4603 mov r3, r0 8016338: 2b00 cmp r3, #0 801633a: d006 beq.n 801634a LWIP_ASSERT("failed to create mem_mutex", 0); 801633c: 4b0a ldr r3, [pc, #40] ; (8016368 ) 801633e: f240 221f movw r2, #543 ; 0x21f 8016342: 490a ldr r1, [pc, #40] ; (801636c ) 8016344: 480a ldr r0, [pc, #40] ; (8016370 ) 8016346: f00b fb1f bl 8021988 } } 801634a: bf00 nop 801634c: 3708 adds r7, #8 801634e: 46bd mov sp, r7 8016350: bd80 pop {r7, pc} 8016352: bf00 nop 8016354: 24013998 .word 0x24013998 8016358: 30000200 .word 0x30000200 801635c: 2401399c .word 0x2401399c 8016360: 240139a4 .word 0x240139a4 8016364: 240139a0 .word 0x240139a0 8016368: 08023df4 .word 0x08023df4 801636c: 08023ec8 .word 0x08023ec8 8016370: 08023e3c .word 0x08023e3c 08016374 : /* Check if a struct mem is correctly linked. * If not, double-free is a possible reason. */ static int mem_link_valid(struct mem *mem) { 8016374: b580 push {r7, lr} 8016376: b086 sub sp, #24 8016378: af00 add r7, sp, #0 801637a: 6078 str r0, [r7, #4] struct mem *nmem, *pmem; mem_size_t rmem_idx; rmem_idx = mem_to_ptr(mem); 801637c: 6878 ldr r0, [r7, #4] 801637e: f7ff fef3 bl 8016168 8016382: 4603 mov r3, r0 8016384: 82fb strh r3, [r7, #22] nmem = ptr_to_mem(mem->next); 8016386: 687b ldr r3, [r7, #4] 8016388: 881b ldrh r3, [r3, #0] 801638a: 4618 mov r0, r3 801638c: f7ff feda bl 8016144 8016390: 6138 str r0, [r7, #16] pmem = ptr_to_mem(mem->prev); 8016392: 687b ldr r3, [r7, #4] 8016394: 885b ldrh r3, [r3, #2] 8016396: 4618 mov r0, r3 8016398: f7ff fed4 bl 8016144 801639c: 60f8 str r0, [r7, #12] if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) || 801639e: 687b ldr r3, [r7, #4] 80163a0: 881b ldrh r3, [r3, #0] 80163a2: f647 52e8 movw r2, #32232 ; 0x7de8 80163a6: 4293 cmp r3, r2 80163a8: d819 bhi.n 80163de 80163aa: 687b ldr r3, [r7, #4] 80163ac: 885b ldrh r3, [r3, #2] 80163ae: f647 52e8 movw r2, #32232 ; 0x7de8 80163b2: 4293 cmp r3, r2 80163b4: d813 bhi.n 80163de ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) || 80163b6: 687b ldr r3, [r7, #4] 80163b8: 885b ldrh r3, [r3, #2] if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) || 80163ba: 8afa ldrh r2, [r7, #22] 80163bc: 429a cmp r2, r3 80163be: d004 beq.n 80163ca ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) || 80163c0: 68fb ldr r3, [r7, #12] 80163c2: 881b ldrh r3, [r3, #0] 80163c4: 8afa ldrh r2, [r7, #22] 80163c6: 429a cmp r2, r3 80163c8: d109 bne.n 80163de ((nmem != ram_end) && (nmem->prev != rmem_idx))) { 80163ca: 4b08 ldr r3, [pc, #32] ; (80163ec ) 80163cc: 681b ldr r3, [r3, #0] ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) || 80163ce: 693a ldr r2, [r7, #16] 80163d0: 429a cmp r2, r3 80163d2: d006 beq.n 80163e2 ((nmem != ram_end) && (nmem->prev != rmem_idx))) { 80163d4: 693b ldr r3, [r7, #16] 80163d6: 885b ldrh r3, [r3, #2] 80163d8: 8afa ldrh r2, [r7, #22] 80163da: 429a cmp r2, r3 80163dc: d001 beq.n 80163e2 return 0; 80163de: 2300 movs r3, #0 80163e0: e000 b.n 80163e4 } return 1; 80163e2: 2301 movs r3, #1 } 80163e4: 4618 mov r0, r3 80163e6: 3718 adds r7, #24 80163e8: 46bd mov sp, r7 80163ea: bd80 pop {r7, pc} 80163ec: 2401399c .word 0x2401399c 080163f0 : * @param rmem is the data portion of a struct mem as returned by a previous * call to mem_malloc() */ void mem_free(void *rmem) { 80163f0: b580 push {r7, lr} 80163f2: b088 sub sp, #32 80163f4: af00 add r7, sp, #0 80163f6: 6078 str r0, [r7, #4] struct mem *mem; LWIP_MEM_FREE_DECL_PROTECT(); if (rmem == NULL) { 80163f8: 687b ldr r3, [r7, #4] 80163fa: 2b00 cmp r3, #0 80163fc: d103 bne.n 8016406 LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n")); 80163fe: 4841 ldr r0, [pc, #260] ; (8016504 ) 8016400: f00b fb30 bl 8021a64 return; 8016404: e07b b.n 80164fe } if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) { 8016406: 687b ldr r3, [r7, #4] 8016408: f003 0303 and.w r3, r3, #3 801640c: 2b00 cmp r3, #0 801640e: d010 beq.n 8016432 LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment"); 8016410: 4b3d ldr r3, [pc, #244] ; (8016508 ) 8016412: f240 2273 movw r2, #627 ; 0x273 8016416: 493d ldr r1, [pc, #244] ; (801650c ) 8016418: 483d ldr r0, [pc, #244] ; (8016510 ) 801641a: f00b fab5 bl 8021988 LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n")); 801641e: 483b ldr r0, [pc, #236] ; (801650c ) 8016420: f00b fb20 bl 8021a64 /* protect mem stats from concurrent access */ MEM_STATS_INC_LOCKED(illegal); 8016424: f00b f916 bl 8021654 8016428: 60f8 str r0, [r7, #12] 801642a: 68f8 ldr r0, [r7, #12] 801642c: f00b f920 bl 8021670 return; 8016430: e065 b.n 80164fe } /* Get the corresponding struct mem: */ /* cast through void* to get rid of alignment warnings */ mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET)); 8016432: 687b ldr r3, [r7, #4] 8016434: 3b08 subs r3, #8 8016436: 61fb str r3, [r7, #28] if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) { 8016438: 4b36 ldr r3, [pc, #216] ; (8016514 ) 801643a: 681b ldr r3, [r3, #0] 801643c: 69fa ldr r2, [r7, #28] 801643e: 429a cmp r2, r3 8016440: d306 bcc.n 8016450 8016442: 687b ldr r3, [r7, #4] 8016444: f103 020c add.w r2, r3, #12 8016448: 4b33 ldr r3, [pc, #204] ; (8016518 ) 801644a: 681b ldr r3, [r3, #0] 801644c: 429a cmp r2, r3 801644e: d910 bls.n 8016472 LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory"); 8016450: 4b2d ldr r3, [pc, #180] ; (8016508 ) 8016452: f240 227f movw r2, #639 ; 0x27f 8016456: 4931 ldr r1, [pc, #196] ; (801651c ) 8016458: 482d ldr r0, [pc, #180] ; (8016510 ) 801645a: f00b fa95 bl 8021988 LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n")); 801645e: 482f ldr r0, [pc, #188] ; (801651c ) 8016460: f00b fb00 bl 8021a64 /* protect mem stats from concurrent access */ MEM_STATS_INC_LOCKED(illegal); 8016464: f00b f8f6 bl 8021654 8016468: 6138 str r0, [r7, #16] 801646a: 6938 ldr r0, [r7, #16] 801646c: f00b f900 bl 8021670 return; 8016470: e045 b.n 80164fe } #if MEM_OVERFLOW_CHECK mem_overflow_check_element(mem); #endif /* protect the heap from concurrent access */ LWIP_MEM_FREE_PROTECT(); 8016472: 482b ldr r0, [pc, #172] ; (8016520 ) 8016474: f00b f8ac bl 80215d0 /* mem has to be in a used state */ if (!mem->used) { 8016478: 69fb ldr r3, [r7, #28] 801647a: 791b ldrb r3, [r3, #4] 801647c: 2b00 cmp r3, #0 801647e: d113 bne.n 80164a8 LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free"); 8016480: 4b21 ldr r3, [pc, #132] ; (8016508 ) 8016482: f44f 7223 mov.w r2, #652 ; 0x28c 8016486: 4927 ldr r1, [pc, #156] ; (8016524 ) 8016488: 4821 ldr r0, [pc, #132] ; (8016510 ) 801648a: f00b fa7d bl 8021988 LWIP_MEM_FREE_UNPROTECT(); 801648e: 4824 ldr r0, [pc, #144] ; (8016520 ) 8016490: f00b f8ad bl 80215ee LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n")); 8016494: 4824 ldr r0, [pc, #144] ; (8016528 ) 8016496: f00b fae5 bl 8021a64 /* protect mem stats from concurrent access */ MEM_STATS_INC_LOCKED(illegal); 801649a: f00b f8db bl 8021654 801649e: 6178 str r0, [r7, #20] 80164a0: 6978 ldr r0, [r7, #20] 80164a2: f00b f8e5 bl 8021670 return; 80164a6: e02a b.n 80164fe } if (!mem_link_valid(mem)) { 80164a8: 69f8 ldr r0, [r7, #28] 80164aa: f7ff ff63 bl 8016374 80164ae: 4603 mov r3, r0 80164b0: 2b00 cmp r3, #0 80164b2: d113 bne.n 80164dc LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free"); 80164b4: 4b14 ldr r3, [pc, #80] ; (8016508 ) 80164b6: f240 2295 movw r2, #661 ; 0x295 80164ba: 491c ldr r1, [pc, #112] ; (801652c ) 80164bc: 4814 ldr r0, [pc, #80] ; (8016510 ) 80164be: f00b fa63 bl 8021988 LWIP_MEM_FREE_UNPROTECT(); 80164c2: 4817 ldr r0, [pc, #92] ; (8016520 ) 80164c4: f00b f893 bl 80215ee LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n")); 80164c8: 4819 ldr r0, [pc, #100] ; (8016530 ) 80164ca: f00b facb bl 8021a64 /* protect mem stats from concurrent access */ MEM_STATS_INC_LOCKED(illegal); 80164ce: f00b f8c1 bl 8021654 80164d2: 61b8 str r0, [r7, #24] 80164d4: 69b8 ldr r0, [r7, #24] 80164d6: f00b f8cb bl 8021670 return; 80164da: e010 b.n 80164fe } /* mem is now unused. */ mem->used = 0; 80164dc: 69fb ldr r3, [r7, #28] 80164de: 2200 movs r2, #0 80164e0: 711a strb r2, [r3, #4] if (mem < lfree) { 80164e2: 4b14 ldr r3, [pc, #80] ; (8016534 ) 80164e4: 681b ldr r3, [r3, #0] 80164e6: 69fa ldr r2, [r7, #28] 80164e8: 429a cmp r2, r3 80164ea: d202 bcs.n 80164f2 /* the newly freed struct is now the lowest */ lfree = mem; 80164ec: 4a11 ldr r2, [pc, #68] ; (8016534 ) 80164ee: 69fb ldr r3, [r7, #28] 80164f0: 6013 str r3, [r2, #0] } MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram))); /* finally, see if prev or next are free also */ plug_holes(mem); 80164f2: 69f8 ldr r0, [r7, #28] 80164f4: f7ff fe4a bl 801618c MEM_SANITY(); #if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT mem_free_count = 1; #endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ LWIP_MEM_FREE_UNPROTECT(); 80164f8: 4809 ldr r0, [pc, #36] ; (8016520 ) 80164fa: f00b f878 bl 80215ee } 80164fe: 3720 adds r7, #32 8016500: 46bd mov sp, r7 8016502: bd80 pop {r7, pc} 8016504: 08023ee4 .word 0x08023ee4 8016508: 08023df4 .word 0x08023df4 801650c: 08023f04 .word 0x08023f04 8016510: 08023e3c .word 0x08023e3c 8016514: 24013998 .word 0x24013998 8016518: 2401399c .word 0x2401399c 801651c: 08023f28 .word 0x08023f28 8016520: 240139a0 .word 0x240139a0 8016524: 08023f44 .word 0x08023f44 8016528: 08023f6c .word 0x08023f6c 801652c: 08023f94 .word 0x08023f94 8016530: 08023fc8 .word 0x08023fc8 8016534: 240139a4 .word 0x240139a4 08016538 : * or NULL if newsize is > old size, in which case rmem is NOT touched * or freed! */ void * mem_trim(void *rmem, mem_size_t new_size) { 8016538: b580 push {r7, lr} 801653a: b088 sub sp, #32 801653c: af00 add r7, sp, #0 801653e: 6078 str r0, [r7, #4] 8016540: 460b mov r3, r1 8016542: 807b strh r3, [r7, #2] /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */ LWIP_MEM_FREE_DECL_PROTECT(); /* Expand the size of the allocated memory region so that we can adjust for alignment. */ newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size); 8016544: 887b ldrh r3, [r7, #2] 8016546: 3303 adds r3, #3 8016548: b29b uxth r3, r3 801654a: f023 0303 bic.w r3, r3, #3 801654e: 83fb strh r3, [r7, #30] if (newsize < MIN_SIZE_ALIGNED) { 8016550: 8bfb ldrh r3, [r7, #30] 8016552: 2b0b cmp r3, #11 8016554: d801 bhi.n 801655a /* every data block must be at least MIN_SIZE_ALIGNED long */ newsize = MIN_SIZE_ALIGNED; 8016556: 230c movs r3, #12 8016558: 83fb strh r3, [r7, #30] } #if MEM_OVERFLOW_CHECK newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED; #endif if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) { 801655a: 8bfb ldrh r3, [r7, #30] 801655c: f647 52e8 movw r2, #32232 ; 0x7de8 8016560: 4293 cmp r3, r2 8016562: d803 bhi.n 801656c 8016564: 8bfa ldrh r2, [r7, #30] 8016566: 887b ldrh r3, [r7, #2] 8016568: 429a cmp r2, r3 801656a: d201 bcs.n 8016570 return NULL; 801656c: 2300 movs r3, #0 801656e: e0df b.n 8016730 } LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram && 8016570: 4b71 ldr r3, [pc, #452] ; (8016738 ) 8016572: 681b ldr r3, [r3, #0] 8016574: 687a ldr r2, [r7, #4] 8016576: 429a cmp r2, r3 8016578: d304 bcc.n 8016584 801657a: 4b70 ldr r3, [pc, #448] ; (801673c ) 801657c: 681b ldr r3, [r3, #0] 801657e: 687a ldr r2, [r7, #4] 8016580: 429a cmp r2, r3 8016582: d306 bcc.n 8016592 8016584: 4b6e ldr r3, [pc, #440] ; (8016740 ) 8016586: f240 22d1 movw r2, #721 ; 0x2d1 801658a: 496e ldr r1, [pc, #440] ; (8016744 ) 801658c: 486e ldr r0, [pc, #440] ; (8016748 ) 801658e: f00b f9fb bl 8021988 (u8_t *)rmem < (u8_t *)ram_end); if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { 8016592: 4b69 ldr r3, [pc, #420] ; (8016738 ) 8016594: 681b ldr r3, [r3, #0] 8016596: 687a ldr r2, [r7, #4] 8016598: 429a cmp r2, r3 801659a: d304 bcc.n 80165a6 801659c: 4b67 ldr r3, [pc, #412] ; (801673c ) 801659e: 681b ldr r3, [r3, #0] 80165a0: 687a ldr r2, [r7, #4] 80165a2: 429a cmp r2, r3 80165a4: d30a bcc.n 80165bc LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n")); 80165a6: 4869 ldr r0, [pc, #420] ; (801674c ) 80165a8: f00b fa5c bl 8021a64 /* protect mem stats from concurrent access */ MEM_STATS_INC_LOCKED(illegal); 80165ac: f00b f852 bl 8021654 80165b0: 60b8 str r0, [r7, #8] 80165b2: 68b8 ldr r0, [r7, #8] 80165b4: f00b f85c bl 8021670 return rmem; 80165b8: 687b ldr r3, [r7, #4] 80165ba: e0b9 b.n 8016730 } /* Get the corresponding struct mem ... */ /* cast through void* to get rid of alignment warnings */ mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET)); 80165bc: 687b ldr r3, [r7, #4] 80165be: 3b08 subs r3, #8 80165c0: 61bb str r3, [r7, #24] #if MEM_OVERFLOW_CHECK mem_overflow_check_element(mem); #endif /* ... and its offset pointer */ ptr = mem_to_ptr(mem); 80165c2: 69b8 ldr r0, [r7, #24] 80165c4: f7ff fdd0 bl 8016168 80165c8: 4603 mov r3, r0 80165ca: 82fb strh r3, [r7, #22] size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD)); 80165cc: 69bb ldr r3, [r7, #24] 80165ce: 881a ldrh r2, [r3, #0] 80165d0: 8afb ldrh r3, [r7, #22] 80165d2: 1ad3 subs r3, r2, r3 80165d4: b29b uxth r3, r3 80165d6: 3b08 subs r3, #8 80165d8: 82bb strh r3, [r7, #20] LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size); 80165da: 8bfa ldrh r2, [r7, #30] 80165dc: 8abb ldrh r3, [r7, #20] 80165de: 429a cmp r2, r3 80165e0: d906 bls.n 80165f0 80165e2: 4b57 ldr r3, [pc, #348] ; (8016740 ) 80165e4: f44f 7239 mov.w r2, #740 ; 0x2e4 80165e8: 4959 ldr r1, [pc, #356] ; (8016750 ) 80165ea: 4857 ldr r0, [pc, #348] ; (8016748 ) 80165ec: f00b f9cc bl 8021988 if (newsize > size) { 80165f0: 8bfa ldrh r2, [r7, #30] 80165f2: 8abb ldrh r3, [r7, #20] 80165f4: 429a cmp r2, r3 80165f6: d901 bls.n 80165fc /* not supported */ return NULL; 80165f8: 2300 movs r3, #0 80165fa: e099 b.n 8016730 } if (newsize == size) { 80165fc: 8bfa ldrh r2, [r7, #30] 80165fe: 8abb ldrh r3, [r7, #20] 8016600: 429a cmp r2, r3 8016602: d101 bne.n 8016608 /* No change in size, simply return */ return rmem; 8016604: 687b ldr r3, [r7, #4] 8016606: e093 b.n 8016730 } /* protect the heap from concurrent access */ LWIP_MEM_FREE_PROTECT(); 8016608: 4852 ldr r0, [pc, #328] ; (8016754 ) 801660a: f00a ffe1 bl 80215d0 mem2 = ptr_to_mem(mem->next); 801660e: 69bb ldr r3, [r7, #24] 8016610: 881b ldrh r3, [r3, #0] 8016612: 4618 mov r0, r3 8016614: f7ff fd96 bl 8016144 8016618: 6138 str r0, [r7, #16] if (mem2->used == 0) { 801661a: 693b ldr r3, [r7, #16] 801661c: 791b ldrb r3, [r3, #4] 801661e: 2b00 cmp r3, #0 8016620: d141 bne.n 80166a6 /* The next struct is unused, we can simply move it at little */ mem_size_t next; LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED); 8016622: 69bb ldr r3, [r7, #24] 8016624: 881b ldrh r3, [r3, #0] 8016626: f647 52e8 movw r2, #32232 ; 0x7de8 801662a: 4293 cmp r3, r2 801662c: d106 bne.n 801663c 801662e: 4b44 ldr r3, [pc, #272] ; (8016740 ) 8016630: f240 22f5 movw r2, #757 ; 0x2f5 8016634: 4948 ldr r1, [pc, #288] ; (8016758 ) 8016636: 4844 ldr r0, [pc, #272] ; (8016748 ) 8016638: f00b f9a6 bl 8021988 /* remember the old next pointer */ next = mem2->next; 801663c: 693b ldr r3, [r7, #16] 801663e: 881b ldrh r3, [r3, #0] 8016640: 81bb strh r3, [r7, #12] /* create new struct mem which is moved directly after the shrinked mem */ ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize); 8016642: 8afa ldrh r2, [r7, #22] 8016644: 8bfb ldrh r3, [r7, #30] 8016646: 4413 add r3, r2 8016648: b29b uxth r3, r3 801664a: 3308 adds r3, #8 801664c: 81fb strh r3, [r7, #14] if (lfree == mem2) { 801664e: 4b43 ldr r3, [pc, #268] ; (801675c ) 8016650: 681b ldr r3, [r3, #0] 8016652: 693a ldr r2, [r7, #16] 8016654: 429a cmp r2, r3 8016656: d106 bne.n 8016666 lfree = ptr_to_mem(ptr2); 8016658: 89fb ldrh r3, [r7, #14] 801665a: 4618 mov r0, r3 801665c: f7ff fd72 bl 8016144 8016660: 4603 mov r3, r0 8016662: 4a3e ldr r2, [pc, #248] ; (801675c ) 8016664: 6013 str r3, [r2, #0] } mem2 = ptr_to_mem(ptr2); 8016666: 89fb ldrh r3, [r7, #14] 8016668: 4618 mov r0, r3 801666a: f7ff fd6b bl 8016144 801666e: 6138 str r0, [r7, #16] mem2->used = 0; 8016670: 693b ldr r3, [r7, #16] 8016672: 2200 movs r2, #0 8016674: 711a strb r2, [r3, #4] /* restore the next pointer */ mem2->next = next; 8016676: 693b ldr r3, [r7, #16] 8016678: 89ba ldrh r2, [r7, #12] 801667a: 801a strh r2, [r3, #0] /* link it back to mem */ mem2->prev = ptr; 801667c: 693b ldr r3, [r7, #16] 801667e: 8afa ldrh r2, [r7, #22] 8016680: 805a strh r2, [r3, #2] /* link mem to it */ mem->next = ptr2; 8016682: 69bb ldr r3, [r7, #24] 8016684: 89fa ldrh r2, [r7, #14] 8016686: 801a strh r2, [r3, #0] /* last thing to restore linked list: as we have moved mem2, * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not * the end of the heap */ if (mem2->next != MEM_SIZE_ALIGNED) { 8016688: 693b ldr r3, [r7, #16] 801668a: 881b ldrh r3, [r3, #0] 801668c: f647 52e8 movw r2, #32232 ; 0x7de8 8016690: 4293 cmp r3, r2 8016692: d049 beq.n 8016728 ptr_to_mem(mem2->next)->prev = ptr2; 8016694: 693b ldr r3, [r7, #16] 8016696: 881b ldrh r3, [r3, #0] 8016698: 4618 mov r0, r3 801669a: f7ff fd53 bl 8016144 801669e: 4602 mov r2, r0 80166a0: 89fb ldrh r3, [r7, #14] 80166a2: 8053 strh r3, [r2, #2] 80166a4: e040 b.n 8016728 } MEM_STATS_DEC_USED(used, (size - newsize)); /* no need to plug holes, we've already done that */ } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) { 80166a6: 8bfb ldrh r3, [r7, #30] 80166a8: f103 0214 add.w r2, r3, #20 80166ac: 8abb ldrh r3, [r7, #20] 80166ae: 429a cmp r2, r3 80166b0: d83a bhi.n 8016728 * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED'). * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty * region that couldn't hold data, but when mem->next gets freed, * the 2 regions would be combined, resulting in more free memory */ ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize); 80166b2: 8afa ldrh r2, [r7, #22] 80166b4: 8bfb ldrh r3, [r7, #30] 80166b6: 4413 add r3, r2 80166b8: b29b uxth r3, r3 80166ba: 3308 adds r3, #8 80166bc: 81fb strh r3, [r7, #14] LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED); 80166be: 69bb ldr r3, [r7, #24] 80166c0: 881b ldrh r3, [r3, #0] 80166c2: f647 52e8 movw r2, #32232 ; 0x7de8 80166c6: 4293 cmp r3, r2 80166c8: d106 bne.n 80166d8 80166ca: 4b1d ldr r3, [pc, #116] ; (8016740 ) 80166cc: f240 3216 movw r2, #790 ; 0x316 80166d0: 4921 ldr r1, [pc, #132] ; (8016758 ) 80166d2: 481d ldr r0, [pc, #116] ; (8016748 ) 80166d4: f00b f958 bl 8021988 mem2 = ptr_to_mem(ptr2); 80166d8: 89fb ldrh r3, [r7, #14] 80166da: 4618 mov r0, r3 80166dc: f7ff fd32 bl 8016144 80166e0: 6138 str r0, [r7, #16] if (mem2 < lfree) { 80166e2: 4b1e ldr r3, [pc, #120] ; (801675c ) 80166e4: 681b ldr r3, [r3, #0] 80166e6: 693a ldr r2, [r7, #16] 80166e8: 429a cmp r2, r3 80166ea: d202 bcs.n 80166f2 lfree = mem2; 80166ec: 4a1b ldr r2, [pc, #108] ; (801675c ) 80166ee: 693b ldr r3, [r7, #16] 80166f0: 6013 str r3, [r2, #0] } mem2->used = 0; 80166f2: 693b ldr r3, [r7, #16] 80166f4: 2200 movs r2, #0 80166f6: 711a strb r2, [r3, #4] mem2->next = mem->next; 80166f8: 69bb ldr r3, [r7, #24] 80166fa: 881a ldrh r2, [r3, #0] 80166fc: 693b ldr r3, [r7, #16] 80166fe: 801a strh r2, [r3, #0] mem2->prev = ptr; 8016700: 693b ldr r3, [r7, #16] 8016702: 8afa ldrh r2, [r7, #22] 8016704: 805a strh r2, [r3, #2] mem->next = ptr2; 8016706: 69bb ldr r3, [r7, #24] 8016708: 89fa ldrh r2, [r7, #14] 801670a: 801a strh r2, [r3, #0] if (mem2->next != MEM_SIZE_ALIGNED) { 801670c: 693b ldr r3, [r7, #16] 801670e: 881b ldrh r3, [r3, #0] 8016710: f647 52e8 movw r2, #32232 ; 0x7de8 8016714: 4293 cmp r3, r2 8016716: d007 beq.n 8016728 ptr_to_mem(mem2->next)->prev = ptr2; 8016718: 693b ldr r3, [r7, #16] 801671a: 881b ldrh r3, [r3, #0] 801671c: 4618 mov r0, r3 801671e: f7ff fd11 bl 8016144 8016722: 4602 mov r2, r0 8016724: 89fb ldrh r3, [r7, #14] 8016726: 8053 strh r3, [r2, #2] #endif MEM_SANITY(); #if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT mem_free_count = 1; #endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ LWIP_MEM_FREE_UNPROTECT(); 8016728: 480a ldr r0, [pc, #40] ; (8016754 ) 801672a: f00a ff60 bl 80215ee return rmem; 801672e: 687b ldr r3, [r7, #4] } 8016730: 4618 mov r0, r3 8016732: 3720 adds r7, #32 8016734: 46bd mov sp, r7 8016736: bd80 pop {r7, pc} 8016738: 24013998 .word 0x24013998 801673c: 2401399c .word 0x2401399c 8016740: 08023df4 .word 0x08023df4 8016744: 08023ffc .word 0x08023ffc 8016748: 08023e3c .word 0x08023e3c 801674c: 08024014 .word 0x08024014 8016750: 08024030 .word 0x08024030 8016754: 240139a0 .word 0x240139a0 8016758: 08024050 .word 0x08024050 801675c: 240139a4 .word 0x240139a4 08016760 : * * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT). */ void * mem_malloc(mem_size_t size_in) { 8016760: b580 push {r7, lr} 8016762: b088 sub sp, #32 8016764: af00 add r7, sp, #0 8016766: 4603 mov r3, r0 8016768: 80fb strh r3, [r7, #6] #if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT u8_t local_mem_free_count = 0; #endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ LWIP_MEM_ALLOC_DECL_PROTECT(); if (size_in == 0) { 801676a: 88fb ldrh r3, [r7, #6] 801676c: 2b00 cmp r3, #0 801676e: d101 bne.n 8016774 return NULL; 8016770: 2300 movs r3, #0 8016772: e0ec b.n 801694e } /* Expand the size of the allocated memory region so that we can adjust for alignment. */ size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in); 8016774: 88fb ldrh r3, [r7, #6] 8016776: 3303 adds r3, #3 8016778: b29b uxth r3, r3 801677a: f023 0303 bic.w r3, r3, #3 801677e: 83bb strh r3, [r7, #28] if (size < MIN_SIZE_ALIGNED) { 8016780: 8bbb ldrh r3, [r7, #28] 8016782: 2b0b cmp r3, #11 8016784: d801 bhi.n 801678a /* every data block must be at least MIN_SIZE_ALIGNED long */ size = MIN_SIZE_ALIGNED; 8016786: 230c movs r3, #12 8016788: 83bb strh r3, [r7, #28] } #if MEM_OVERFLOW_CHECK size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED; #endif if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) { 801678a: 8bbb ldrh r3, [r7, #28] 801678c: f647 52e8 movw r2, #32232 ; 0x7de8 8016790: 4293 cmp r3, r2 8016792: d803 bhi.n 801679c 8016794: 8bba ldrh r2, [r7, #28] 8016796: 88fb ldrh r3, [r7, #6] 8016798: 429a cmp r2, r3 801679a: d201 bcs.n 80167a0 return NULL; 801679c: 2300 movs r3, #0 801679e: e0d6 b.n 801694e } /* protect the heap from concurrent access */ sys_mutex_lock(&mem_mutex); 80167a0: 486d ldr r0, [pc, #436] ; (8016958 ) 80167a2: f00a ff15 bl 80215d0 #endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ /* Scan through the heap searching for a free block that is big enough, * beginning with the lowest free block. */ for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size; 80167a6: 4b6d ldr r3, [pc, #436] ; (801695c ) 80167a8: 681b ldr r3, [r3, #0] 80167aa: 4618 mov r0, r3 80167ac: f7ff fcdc bl 8016168 80167b0: 4603 mov r3, r0 80167b2: 83fb strh r3, [r7, #30] 80167b4: e0b9 b.n 801692a ptr = ptr_to_mem(ptr)->next) { mem = ptr_to_mem(ptr); 80167b6: 8bfb ldrh r3, [r7, #30] 80167b8: 4618 mov r0, r3 80167ba: f7ff fcc3 bl 8016144 80167be: 6178 str r0, [r7, #20] local_mem_free_count = 1; break; } #endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ if ((!mem->used) && 80167c0: 697b ldr r3, [r7, #20] 80167c2: 791b ldrb r3, [r3, #4] 80167c4: 2b00 cmp r3, #0 80167c6: f040 80a9 bne.w 801691c (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) { 80167ca: 697b ldr r3, [r7, #20] 80167cc: 881b ldrh r3, [r3, #0] 80167ce: 461a mov r2, r3 80167d0: 8bfb ldrh r3, [r7, #30] 80167d2: 1ad3 subs r3, r2, r3 80167d4: f1a3 0208 sub.w r2, r3, #8 80167d8: 8bbb ldrh r3, [r7, #28] if ((!mem->used) && 80167da: 429a cmp r2, r3 80167dc: f0c0 809e bcc.w 801691c /* mem is not used and at least perfect fit is possible: * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */ if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) { 80167e0: 697b ldr r3, [r7, #20] 80167e2: 881b ldrh r3, [r3, #0] 80167e4: 461a mov r2, r3 80167e6: 8bfb ldrh r3, [r7, #30] 80167e8: 1ad3 subs r3, r2, r3 80167ea: f1a3 0208 sub.w r2, r3, #8 80167ee: 8bbb ldrh r3, [r7, #28] 80167f0: 3314 adds r3, #20 80167f2: 429a cmp r2, r3 80167f4: d335 bcc.n 8016862 * struct mem would fit in but no data between mem2 and mem2->next * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty * region that couldn't hold data, but when mem->next gets freed, * the 2 regions would be combined, resulting in more free memory */ ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size); 80167f6: 8bfa ldrh r2, [r7, #30] 80167f8: 8bbb ldrh r3, [r7, #28] 80167fa: 4413 add r3, r2 80167fc: b29b uxth r3, r3 80167fe: 3308 adds r3, #8 8016800: 827b strh r3, [r7, #18] LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED); 8016802: 8a7b ldrh r3, [r7, #18] 8016804: f647 52e8 movw r2, #32232 ; 0x7de8 8016808: 4293 cmp r3, r2 801680a: d106 bne.n 801681a 801680c: 4b54 ldr r3, [pc, #336] ; (8016960 ) 801680e: f240 3287 movw r2, #903 ; 0x387 8016812: 4954 ldr r1, [pc, #336] ; (8016964 ) 8016814: 4854 ldr r0, [pc, #336] ; (8016968 ) 8016816: f00b f8b7 bl 8021988 /* create mem2 struct */ mem2 = ptr_to_mem(ptr2); 801681a: 8a7b ldrh r3, [r7, #18] 801681c: 4618 mov r0, r3 801681e: f7ff fc91 bl 8016144 8016822: 60f8 str r0, [r7, #12] mem2->used = 0; 8016824: 68fb ldr r3, [r7, #12] 8016826: 2200 movs r2, #0 8016828: 711a strb r2, [r3, #4] mem2->next = mem->next; 801682a: 697b ldr r3, [r7, #20] 801682c: 881a ldrh r2, [r3, #0] 801682e: 68fb ldr r3, [r7, #12] 8016830: 801a strh r2, [r3, #0] mem2->prev = ptr; 8016832: 68fb ldr r3, [r7, #12] 8016834: 8bfa ldrh r2, [r7, #30] 8016836: 805a strh r2, [r3, #2] /* and insert it between mem and mem->next */ mem->next = ptr2; 8016838: 697b ldr r3, [r7, #20] 801683a: 8a7a ldrh r2, [r7, #18] 801683c: 801a strh r2, [r3, #0] mem->used = 1; 801683e: 697b ldr r3, [r7, #20] 8016840: 2201 movs r2, #1 8016842: 711a strb r2, [r3, #4] if (mem2->next != MEM_SIZE_ALIGNED) { 8016844: 68fb ldr r3, [r7, #12] 8016846: 881b ldrh r3, [r3, #0] 8016848: f647 52e8 movw r2, #32232 ; 0x7de8 801684c: 4293 cmp r3, r2 801684e: d00b beq.n 8016868 ptr_to_mem(mem2->next)->prev = ptr2; 8016850: 68fb ldr r3, [r7, #12] 8016852: 881b ldrh r3, [r3, #0] 8016854: 4618 mov r0, r3 8016856: f7ff fc75 bl 8016144 801685a: 4602 mov r2, r0 801685c: 8a7b ldrh r3, [r7, #18] 801685e: 8053 strh r3, [r2, #2] 8016860: e002 b.n 8016868 * take care of this). * -> near fit or exact fit: do not split, no mem2 creation * also can't move mem->next directly behind mem, since mem->next * will always be used at this point! */ mem->used = 1; 8016862: 697b ldr r3, [r7, #20] 8016864: 2201 movs r2, #1 8016866: 711a strb r2, [r3, #4] MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem)); } #if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT mem_malloc_adjust_lfree: #endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ if (mem == lfree) { 8016868: 4b3c ldr r3, [pc, #240] ; (801695c ) 801686a: 681b ldr r3, [r3, #0] 801686c: 697a ldr r2, [r7, #20] 801686e: 429a cmp r2, r3 8016870: d127 bne.n 80168c2 struct mem *cur = lfree; 8016872: 4b3a ldr r3, [pc, #232] ; (801695c ) 8016874: 681b ldr r3, [r3, #0] 8016876: 61bb str r3, [r7, #24] /* Find next free block after mem and update lowest free pointer */ while (cur->used && cur != ram_end) { 8016878: e005 b.n 8016886 /* If mem_free or mem_trim have run, we have to restart since they could have altered our current struct mem or lfree. */ goto mem_malloc_adjust_lfree; } #endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ cur = ptr_to_mem(cur->next); 801687a: 69bb ldr r3, [r7, #24] 801687c: 881b ldrh r3, [r3, #0] 801687e: 4618 mov r0, r3 8016880: f7ff fc60 bl 8016144 8016884: 61b8 str r0, [r7, #24] while (cur->used && cur != ram_end) { 8016886: 69bb ldr r3, [r7, #24] 8016888: 791b ldrb r3, [r3, #4] 801688a: 2b00 cmp r3, #0 801688c: d004 beq.n 8016898 801688e: 4b37 ldr r3, [pc, #220] ; (801696c ) 8016890: 681b ldr r3, [r3, #0] 8016892: 69ba ldr r2, [r7, #24] 8016894: 429a cmp r2, r3 8016896: d1f0 bne.n 801687a } lfree = cur; 8016898: 4a30 ldr r2, [pc, #192] ; (801695c ) 801689a: 69bb ldr r3, [r7, #24] 801689c: 6013 str r3, [r2, #0] LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used))); 801689e: 4b2f ldr r3, [pc, #188] ; (801695c ) 80168a0: 681a ldr r2, [r3, #0] 80168a2: 4b32 ldr r3, [pc, #200] ; (801696c ) 80168a4: 681b ldr r3, [r3, #0] 80168a6: 429a cmp r2, r3 80168a8: d00b beq.n 80168c2 80168aa: 4b2c ldr r3, [pc, #176] ; (801695c ) 80168ac: 681b ldr r3, [r3, #0] 80168ae: 791b ldrb r3, [r3, #4] 80168b0: 2b00 cmp r3, #0 80168b2: d006 beq.n 80168c2 80168b4: 4b2a ldr r3, [pc, #168] ; (8016960 ) 80168b6: f240 32b5 movw r2, #949 ; 0x3b5 80168ba: 492d ldr r1, [pc, #180] ; (8016970 ) 80168bc: 482a ldr r0, [pc, #168] ; (8016968 ) 80168be: f00b f863 bl 8021988 } LWIP_MEM_ALLOC_UNPROTECT(); sys_mutex_unlock(&mem_mutex); 80168c2: 4825 ldr r0, [pc, #148] ; (8016958 ) 80168c4: f00a fe93 bl 80215ee LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", 80168c8: 8bba ldrh r2, [r7, #28] 80168ca: 697b ldr r3, [r7, #20] 80168cc: 4413 add r3, r2 80168ce: 3308 adds r3, #8 80168d0: 4a26 ldr r2, [pc, #152] ; (801696c ) 80168d2: 6812 ldr r2, [r2, #0] 80168d4: 4293 cmp r3, r2 80168d6: d906 bls.n 80168e6 80168d8: 4b21 ldr r3, [pc, #132] ; (8016960 ) 80168da: f240 32b9 movw r2, #953 ; 0x3b9 80168de: 4925 ldr r1, [pc, #148] ; (8016974 ) 80168e0: 4821 ldr r0, [pc, #132] ; (8016968 ) 80168e2: f00b f851 bl 8021988 (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", 80168e6: 697b ldr r3, [r7, #20] 80168e8: f003 0303 and.w r3, r3, #3 80168ec: 2b00 cmp r3, #0 80168ee: d006 beq.n 80168fe 80168f0: 4b1b ldr r3, [pc, #108] ; (8016960 ) 80168f2: f240 32bb movw r2, #955 ; 0x3bb 80168f6: 4920 ldr r1, [pc, #128] ; (8016978 ) 80168f8: 481b ldr r0, [pc, #108] ; (8016968 ) 80168fa: f00b f845 bl 8021988 ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); LWIP_ASSERT("mem_malloc: sanity check alignment", 80168fe: 697b ldr r3, [r7, #20] 8016900: f003 0303 and.w r3, r3, #3 8016904: 2b00 cmp r3, #0 8016906: d006 beq.n 8016916 8016908: 4b15 ldr r3, [pc, #84] ; (8016960 ) 801690a: f240 32bd movw r2, #957 ; 0x3bd 801690e: 491b ldr r1, [pc, #108] ; (801697c ) 8016910: 4815 ldr r0, [pc, #84] ; (8016968 ) 8016912: f00b f839 bl 8021988 #if MEM_OVERFLOW_CHECK mem_overflow_init_element(mem, size_in); #endif MEM_SANITY(); return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET; 8016916: 697b ldr r3, [r7, #20] 8016918: 3308 adds r3, #8 801691a: e018 b.n 801694e ptr = ptr_to_mem(ptr)->next) { 801691c: 8bfb ldrh r3, [r7, #30] 801691e: 4618 mov r0, r3 8016920: f7ff fc10 bl 8016144 8016924: 4603 mov r3, r0 8016926: 881b ldrh r3, [r3, #0] 8016928: 83fb strh r3, [r7, #30] for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size; 801692a: 8bfa ldrh r2, [r7, #30] 801692c: 8bb9 ldrh r1, [r7, #28] 801692e: f647 53e8 movw r3, #32232 ; 0x7de8 8016932: 1a5b subs r3, r3, r1 8016934: 429a cmp r2, r3 8016936: f4ff af3e bcc.w 80167b6 /* if we got interrupted by a mem_free, try again */ } while (local_mem_free_count != 0); #endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ MEM_STATS_INC(err); LWIP_MEM_ALLOC_UNPROTECT(); sys_mutex_unlock(&mem_mutex); 801693a: 4807 ldr r0, [pc, #28] ; (8016958 ) 801693c: f00a fe57 bl 80215ee LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); 8016940: f9b7 301c ldrsh.w r3, [r7, #28] 8016944: 4619 mov r1, r3 8016946: 480e ldr r0, [pc, #56] ; (8016980 ) 8016948: f00b f81e bl 8021988 return NULL; 801694c: 2300 movs r3, #0 } 801694e: 4618 mov r0, r3 8016950: 3720 adds r7, #32 8016952: 46bd mov sp, r7 8016954: bd80 pop {r7, pc} 8016956: bf00 nop 8016958: 240139a0 .word 0x240139a0 801695c: 240139a4 .word 0x240139a4 8016960: 08023df4 .word 0x08023df4 8016964: 08024050 .word 0x08024050 8016968: 08023e3c .word 0x08023e3c 801696c: 2401399c .word 0x2401399c 8016970: 08024064 .word 0x08024064 8016974: 08024080 .word 0x08024080 8016978: 080240b0 .word 0x080240b0 801697c: 080240e0 .word 0x080240e0 8016980: 08024104 .word 0x08024104 08016984 : * * @param desc pool to initialize */ void memp_init_pool(const struct memp_desc *desc) { 8016984: b480 push {r7} 8016986: b085 sub sp, #20 8016988: af00 add r7, sp, #0 801698a: 6078 str r0, [r7, #4] LWIP_UNUSED_ARG(desc); #else int i; struct memp *memp; *desc->tab = NULL; 801698c: 687b ldr r3, [r7, #4] 801698e: 68db ldr r3, [r3, #12] 8016990: 2200 movs r2, #0 8016992: 601a str r2, [r3, #0] memp = (struct memp *)LWIP_MEM_ALIGN(desc->base); 8016994: 687b ldr r3, [r7, #4] 8016996: 689b ldr r3, [r3, #8] 8016998: 3303 adds r3, #3 801699a: f023 0303 bic.w r3, r3, #3 801699e: 60bb str r3, [r7, #8] + MEM_SANITY_REGION_AFTER_ALIGNED #endif )); #endif /* create a linked list of memp elements */ for (i = 0; i < desc->num; ++i) { 80169a0: 2300 movs r3, #0 80169a2: 60fb str r3, [r7, #12] 80169a4: e011 b.n 80169ca memp->next = *desc->tab; 80169a6: 687b ldr r3, [r7, #4] 80169a8: 68db ldr r3, [r3, #12] 80169aa: 681a ldr r2, [r3, #0] 80169ac: 68bb ldr r3, [r7, #8] 80169ae: 601a str r2, [r3, #0] *desc->tab = memp; 80169b0: 687b ldr r3, [r7, #4] 80169b2: 68db ldr r3, [r3, #12] 80169b4: 68ba ldr r2, [r7, #8] 80169b6: 601a str r2, [r3, #0] #if MEMP_OVERFLOW_CHECK memp_overflow_init_element(memp, desc); #endif /* MEMP_OVERFLOW_CHECK */ /* cast through void* to get rid of alignment warnings */ memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size 80169b8: 687b ldr r3, [r7, #4] 80169ba: 889b ldrh r3, [r3, #4] 80169bc: 461a mov r2, r3 80169be: 68bb ldr r3, [r7, #8] 80169c0: 4413 add r3, r2 80169c2: 60bb str r3, [r7, #8] for (i = 0; i < desc->num; ++i) { 80169c4: 68fb ldr r3, [r7, #12] 80169c6: 3301 adds r3, #1 80169c8: 60fb str r3, [r7, #12] 80169ca: 687b ldr r3, [r7, #4] 80169cc: 88db ldrh r3, [r3, #6] 80169ce: 461a mov r2, r3 80169d0: 68fb ldr r3, [r7, #12] 80169d2: 4293 cmp r3, r2 80169d4: dbe7 blt.n 80169a6 #endif /* !MEMP_MEM_MALLOC */ #if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) desc->stats->name = desc->desc; #endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */ } 80169d6: bf00 nop 80169d8: bf00 nop 80169da: 3714 adds r7, #20 80169dc: 46bd mov sp, r7 80169de: f85d 7b04 ldr.w r7, [sp], #4 80169e2: 4770 bx lr 080169e4 : * * Carves out memp_memory into linked lists for each pool-type. */ void memp_init(void) { 80169e4: b580 push {r7, lr} 80169e6: b082 sub sp, #8 80169e8: af00 add r7, sp, #0 u16_t i; /* for every pool: */ for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) { 80169ea: 2300 movs r3, #0 80169ec: 80fb strh r3, [r7, #6] 80169ee: e009 b.n 8016a04 memp_init_pool(memp_pools[i]); 80169f0: 88fb ldrh r3, [r7, #6] 80169f2: 4a08 ldr r2, [pc, #32] ; (8016a14 ) 80169f4: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80169f8: 4618 mov r0, r3 80169fa: f7ff ffc3 bl 8016984 for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) { 80169fe: 88fb ldrh r3, [r7, #6] 8016a00: 3301 adds r3, #1 8016a02: 80fb strh r3, [r7, #6] 8016a04: 88fb ldrh r3, [r7, #6] 8016a06: 2b0c cmp r3, #12 8016a08: d9f2 bls.n 80169f0 #if MEMP_OVERFLOW_CHECK >= 2 /* check everything a first time to see if it worked */ memp_overflow_check_all(); #endif /* MEMP_OVERFLOW_CHECK >= 2 */ } 8016a0a: bf00 nop 8016a0c: bf00 nop 8016a0e: 3708 adds r7, #8 8016a10: 46bd mov sp, r7 8016a12: bd80 pop {r7, pc} 8016a14: 08026c78 .word 0x08026c78 08016a18 : #if !MEMP_OVERFLOW_CHECK do_memp_malloc_pool(const struct memp_desc *desc) #else do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line) #endif { 8016a18: b580 push {r7, lr} 8016a1a: b084 sub sp, #16 8016a1c: af00 add r7, sp, #0 8016a1e: 6078 str r0, [r7, #4] #if MEMP_MEM_MALLOC memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size)); SYS_ARCH_PROTECT(old_level); #else /* MEMP_MEM_MALLOC */ SYS_ARCH_PROTECT(old_level); 8016a20: f00a fe18 bl 8021654 8016a24: 60f8 str r0, [r7, #12] memp = *desc->tab; 8016a26: 687b ldr r3, [r7, #4] 8016a28: 68db ldr r3, [r3, #12] 8016a2a: 681b ldr r3, [r3, #0] 8016a2c: 60bb str r3, [r7, #8] #endif /* MEMP_MEM_MALLOC */ if (memp != NULL) { 8016a2e: 68bb ldr r3, [r7, #8] 8016a30: 2b00 cmp r3, #0 8016a32: d015 beq.n 8016a60 #if !MEMP_MEM_MALLOC #if MEMP_OVERFLOW_CHECK == 1 memp_overflow_check_element(memp, desc); #endif /* MEMP_OVERFLOW_CHECK */ *desc->tab = memp->next; 8016a34: 687b ldr r3, [r7, #4] 8016a36: 68db ldr r3, [r3, #12] 8016a38: 68ba ldr r2, [r7, #8] 8016a3a: 6812 ldr r2, [r2, #0] 8016a3c: 601a str r2, [r3, #0] memp->line = line; #if MEMP_MEM_MALLOC memp_overflow_init_element(memp, desc); #endif /* MEMP_MEM_MALLOC */ #endif /* MEMP_OVERFLOW_CHECK */ LWIP_ASSERT("memp_malloc: memp properly aligned", 8016a3e: 68bb ldr r3, [r7, #8] 8016a40: f003 0303 and.w r3, r3, #3 8016a44: 2b00 cmp r3, #0 8016a46: d006 beq.n 8016a56 8016a48: 4b0c ldr r3, [pc, #48] ; (8016a7c ) 8016a4a: f44f 728c mov.w r2, #280 ; 0x118 8016a4e: 490c ldr r1, [pc, #48] ; (8016a80 ) 8016a50: 480c ldr r0, [pc, #48] ; (8016a84 ) 8016a52: f00a ff99 bl 8021988 desc->stats->used++; if (desc->stats->used > desc->stats->max) { desc->stats->max = desc->stats->used; } #endif SYS_ARCH_UNPROTECT(old_level); 8016a56: 68f8 ldr r0, [r7, #12] 8016a58: f00a fe0a bl 8021670 /* cast through u8_t* to get rid of alignment warnings */ return ((u8_t *)memp + MEMP_SIZE); 8016a5c: 68bb ldr r3, [r7, #8] 8016a5e: e009 b.n 8016a74 } else { #if MEMP_STATS desc->stats->err++; #endif SYS_ARCH_UNPROTECT(old_level); 8016a60: 68f8 ldr r0, [r7, #12] 8016a62: f00a fe05 bl 8021670 LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc)); 8016a66: 687b ldr r3, [r7, #4] 8016a68: 681b ldr r3, [r3, #0] 8016a6a: 4619 mov r1, r3 8016a6c: 4806 ldr r0, [pc, #24] ; (8016a88 ) 8016a6e: f00a ff8b bl 8021988 } return NULL; 8016a72: 2300 movs r3, #0 } 8016a74: 4618 mov r0, r3 8016a76: 3710 adds r7, #16 8016a78: 46bd mov sp, r7 8016a7a: bd80 pop {r7, pc} 8016a7c: 080241f4 .word 0x080241f4 8016a80: 08024224 .word 0x08024224 8016a84: 08024248 .word 0x08024248 8016a88: 08024270 .word 0x08024270 08016a8c : #if !MEMP_OVERFLOW_CHECK memp_malloc_pool(const struct memp_desc *desc) #else memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line) #endif { 8016a8c: b580 push {r7, lr} 8016a8e: b082 sub sp, #8 8016a90: af00 add r7, sp, #0 8016a92: 6078 str r0, [r7, #4] LWIP_ASSERT("invalid pool desc", desc != NULL); 8016a94: 687b ldr r3, [r7, #4] 8016a96: 2b00 cmp r3, #0 8016a98: d106 bne.n 8016aa8 8016a9a: 4b0a ldr r3, [pc, #40] ; (8016ac4 ) 8016a9c: f44f 729e mov.w r2, #316 ; 0x13c 8016aa0: 4909 ldr r1, [pc, #36] ; (8016ac8 ) 8016aa2: 480a ldr r0, [pc, #40] ; (8016acc ) 8016aa4: f00a ff70 bl 8021988 if (desc == NULL) { 8016aa8: 687b ldr r3, [r7, #4] 8016aaa: 2b00 cmp r3, #0 8016aac: d101 bne.n 8016ab2 return NULL; 8016aae: 2300 movs r3, #0 8016ab0: e003 b.n 8016aba } #if !MEMP_OVERFLOW_CHECK return do_memp_malloc_pool(desc); 8016ab2: 6878 ldr r0, [r7, #4] 8016ab4: f7ff ffb0 bl 8016a18 8016ab8: 4603 mov r3, r0 #else return do_memp_malloc_pool_fn(desc, file, line); #endif } 8016aba: 4618 mov r0, r3 8016abc: 3708 adds r7, #8 8016abe: 46bd mov sp, r7 8016ac0: bd80 pop {r7, pc} 8016ac2: bf00 nop 8016ac4: 080241f4 .word 0x080241f4 8016ac8: 08024298 .word 0x08024298 8016acc: 08024248 .word 0x08024248 08016ad0 : #if !MEMP_OVERFLOW_CHECK memp_malloc(memp_t type) #else memp_malloc_fn(memp_t type, const char *file, const int line) #endif { 8016ad0: b580 push {r7, lr} 8016ad2: b084 sub sp, #16 8016ad4: af00 add r7, sp, #0 8016ad6: 4603 mov r3, r0 8016ad8: 71fb strb r3, [r7, #7] void *memp; LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;); 8016ada: 79fb ldrb r3, [r7, #7] 8016adc: 2b0c cmp r3, #12 8016ade: d908 bls.n 8016af2 8016ae0: 4b0a ldr r3, [pc, #40] ; (8016b0c ) 8016ae2: f240 1257 movw r2, #343 ; 0x157 8016ae6: 490a ldr r1, [pc, #40] ; (8016b10 ) 8016ae8: 480a ldr r0, [pc, #40] ; (8016b14 ) 8016aea: f00a ff4d bl 8021988 8016aee: 2300 movs r3, #0 8016af0: e008 b.n 8016b04 #if MEMP_OVERFLOW_CHECK >= 2 memp_overflow_check_all(); #endif /* MEMP_OVERFLOW_CHECK >= 2 */ #if !MEMP_OVERFLOW_CHECK memp = do_memp_malloc_pool(memp_pools[type]); 8016af2: 79fb ldrb r3, [r7, #7] 8016af4: 4a08 ldr r2, [pc, #32] ; (8016b18 ) 8016af6: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8016afa: 4618 mov r0, r3 8016afc: f7ff ff8c bl 8016a18 8016b00: 60f8 str r0, [r7, #12] #else memp = do_memp_malloc_pool_fn(memp_pools[type], file, line); #endif return memp; 8016b02: 68fb ldr r3, [r7, #12] } 8016b04: 4618 mov r0, r3 8016b06: 3710 adds r7, #16 8016b08: 46bd mov sp, r7 8016b0a: bd80 pop {r7, pc} 8016b0c: 080241f4 .word 0x080241f4 8016b10: 080242ac .word 0x080242ac 8016b14: 08024248 .word 0x08024248 8016b18: 08026c78 .word 0x08026c78 08016b1c : static void do_memp_free_pool(const struct memp_desc *desc, void *mem) { 8016b1c: b580 push {r7, lr} 8016b1e: b084 sub sp, #16 8016b20: af00 add r7, sp, #0 8016b22: 6078 str r0, [r7, #4] 8016b24: 6039 str r1, [r7, #0] struct memp *memp; SYS_ARCH_DECL_PROTECT(old_level); LWIP_ASSERT("memp_free: mem properly aligned", 8016b26: 683b ldr r3, [r7, #0] 8016b28: f003 0303 and.w r3, r3, #3 8016b2c: 2b00 cmp r3, #0 8016b2e: d006 beq.n 8016b3e 8016b30: 4b0d ldr r3, [pc, #52] ; (8016b68 ) 8016b32: f44f 72b6 mov.w r2, #364 ; 0x16c 8016b36: 490d ldr r1, [pc, #52] ; (8016b6c ) 8016b38: 480d ldr r0, [pc, #52] ; (8016b70 ) 8016b3a: f00a ff25 bl 8021988 ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0); /* cast through void* to get rid of alignment warnings */ memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE); 8016b3e: 683b ldr r3, [r7, #0] 8016b40: 60fb str r3, [r7, #12] SYS_ARCH_PROTECT(old_level); 8016b42: f00a fd87 bl 8021654 8016b46: 60b8 str r0, [r7, #8] #if MEMP_MEM_MALLOC LWIP_UNUSED_ARG(desc); SYS_ARCH_UNPROTECT(old_level); mem_free(memp); #else /* MEMP_MEM_MALLOC */ memp->next = *desc->tab; 8016b48: 687b ldr r3, [r7, #4] 8016b4a: 68db ldr r3, [r3, #12] 8016b4c: 681a ldr r2, [r3, #0] 8016b4e: 68fb ldr r3, [r7, #12] 8016b50: 601a str r2, [r3, #0] *desc->tab = memp; 8016b52: 687b ldr r3, [r7, #4] 8016b54: 68db ldr r3, [r3, #12] 8016b56: 68fa ldr r2, [r7, #12] 8016b58: 601a str r2, [r3, #0] #if MEMP_SANITY_CHECK LWIP_ASSERT("memp sanity", memp_sanity(desc)); #endif /* MEMP_SANITY_CHECK */ SYS_ARCH_UNPROTECT(old_level); 8016b5a: 68b8 ldr r0, [r7, #8] 8016b5c: f00a fd88 bl 8021670 #endif /* !MEMP_MEM_MALLOC */ } 8016b60: bf00 nop 8016b62: 3710 adds r7, #16 8016b64: 46bd mov sp, r7 8016b66: bd80 pop {r7, pc} 8016b68: 080241f4 .word 0x080241f4 8016b6c: 080242cc .word 0x080242cc 8016b70: 08024248 .word 0x08024248 08016b74 : * @param desc the pool where to put mem * @param mem the memp element to free */ void memp_free_pool(const struct memp_desc *desc, void *mem) { 8016b74: b580 push {r7, lr} 8016b76: b082 sub sp, #8 8016b78: af00 add r7, sp, #0 8016b7a: 6078 str r0, [r7, #4] 8016b7c: 6039 str r1, [r7, #0] LWIP_ASSERT("invalid pool desc", desc != NULL); 8016b7e: 687b ldr r3, [r7, #4] 8016b80: 2b00 cmp r3, #0 8016b82: d106 bne.n 8016b92 8016b84: 4b0a ldr r3, [pc, #40] ; (8016bb0 ) 8016b86: f240 1295 movw r2, #405 ; 0x195 8016b8a: 490a ldr r1, [pc, #40] ; (8016bb4 ) 8016b8c: 480a ldr r0, [pc, #40] ; (8016bb8 ) 8016b8e: f00a fefb bl 8021988 if ((desc == NULL) || (mem == NULL)) { 8016b92: 687b ldr r3, [r7, #4] 8016b94: 2b00 cmp r3, #0 8016b96: d007 beq.n 8016ba8 8016b98: 683b ldr r3, [r7, #0] 8016b9a: 2b00 cmp r3, #0 8016b9c: d004 beq.n 8016ba8 return; } do_memp_free_pool(desc, mem); 8016b9e: 6839 ldr r1, [r7, #0] 8016ba0: 6878 ldr r0, [r7, #4] 8016ba2: f7ff ffbb bl 8016b1c 8016ba6: e000 b.n 8016baa return; 8016ba8: bf00 nop } 8016baa: 3708 adds r7, #8 8016bac: 46bd mov sp, r7 8016bae: bd80 pop {r7, pc} 8016bb0: 080241f4 .word 0x080241f4 8016bb4: 08024298 .word 0x08024298 8016bb8: 08024248 .word 0x08024248 08016bbc : * @param type the pool where to put mem * @param mem the memp element to free */ void memp_free(memp_t type, void *mem) { 8016bbc: b580 push {r7, lr} 8016bbe: b082 sub sp, #8 8016bc0: af00 add r7, sp, #0 8016bc2: 4603 mov r3, r0 8016bc4: 6039 str r1, [r7, #0] 8016bc6: 71fb strb r3, [r7, #7] #ifdef LWIP_HOOK_MEMP_AVAILABLE struct memp *old_first; #endif LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;); 8016bc8: 79fb ldrb r3, [r7, #7] 8016bca: 2b0c cmp r3, #12 8016bcc: d907 bls.n 8016bde 8016bce: 4b0c ldr r3, [pc, #48] ; (8016c00 ) 8016bd0: f44f 72d5 mov.w r2, #426 ; 0x1aa 8016bd4: 490b ldr r1, [pc, #44] ; (8016c04 ) 8016bd6: 480c ldr r0, [pc, #48] ; (8016c08 ) 8016bd8: f00a fed6 bl 8021988 8016bdc: e00c b.n 8016bf8 if (mem == NULL) { 8016bde: 683b ldr r3, [r7, #0] 8016be0: 2b00 cmp r3, #0 8016be2: d008 beq.n 8016bf6 #ifdef LWIP_HOOK_MEMP_AVAILABLE old_first = *memp_pools[type]->tab; #endif do_memp_free_pool(memp_pools[type], mem); 8016be4: 79fb ldrb r3, [r7, #7] 8016be6: 4a09 ldr r2, [pc, #36] ; (8016c0c ) 8016be8: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8016bec: 6839 ldr r1, [r7, #0] 8016bee: 4618 mov r0, r3 8016bf0: f7ff ff94 bl 8016b1c 8016bf4: e000 b.n 8016bf8 return; 8016bf6: bf00 nop #ifdef LWIP_HOOK_MEMP_AVAILABLE if (old_first == NULL) { LWIP_HOOK_MEMP_AVAILABLE(type); } #endif } 8016bf8: 3708 adds r7, #8 8016bfa: 46bd mov sp, r7 8016bfc: bd80 pop {r7, pc} 8016bfe: bf00 nop 8016c00: 080241f4 .word 0x080241f4 8016c04: 080242ec .word 0x080242ec 8016c08: 08024248 .word 0x08024248 8016c0c: 08026c78 .word 0x08026c78 08016c10 : } #endif /* LWIP_HAVE_LOOPIF */ void netif_init(void) { 8016c10: b480 push {r7} 8016c12: af00 add r7, sp, #0 netif_set_link_up(&loop_netif); netif_set_up(&loop_netif); #endif /* LWIP_HAVE_LOOPIF */ } 8016c14: bf00 nop 8016c16: 46bd mov sp, r7 8016c18: f85d 7b04 ldr.w r7, [sp], #4 8016c1c: 4770 bx lr ... 08016c20 : netif_add(struct netif *netif, #if LWIP_IPV4 const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, #endif /* LWIP_IPV4 */ void *state, netif_init_fn init, netif_input_fn input) { 8016c20: b580 push {r7, lr} 8016c22: b088 sub sp, #32 8016c24: af02 add r7, sp, #8 8016c26: 60f8 str r0, [r7, #12] 8016c28: 60b9 str r1, [r7, #8] 8016c2a: 607a str r2, [r7, #4] 8016c2c: 603b str r3, [r7, #0] LWIP_ASSERT("single netif already set", 0); return NULL; } #endif LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL); 8016c2e: 68fb ldr r3, [r7, #12] 8016c30: 2b00 cmp r3, #0 8016c32: d108 bne.n 8016c46 8016c34: 4b96 ldr r3, [pc, #600] ; (8016e90 ) 8016c36: f240 1227 movw r2, #295 ; 0x127 8016c3a: 4996 ldr r1, [pc, #600] ; (8016e94 ) 8016c3c: 4896 ldr r0, [pc, #600] ; (8016e98 ) 8016c3e: f00a fea3 bl 8021988 8016c42: 2300 movs r3, #0 8016c44: e14c b.n 8016ee0 LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL); 8016c46: 6a7b ldr r3, [r7, #36] ; 0x24 8016c48: 2b00 cmp r3, #0 8016c4a: d108 bne.n 8016c5e 8016c4c: 4b90 ldr r3, [pc, #576] ; (8016e90 ) 8016c4e: f44f 7294 mov.w r2, #296 ; 0x128 8016c52: 4992 ldr r1, [pc, #584] ; (8016e9c ) 8016c54: 4890 ldr r0, [pc, #576] ; (8016e98 ) 8016c56: f00a fe97 bl 8021988 8016c5a: 2300 movs r3, #0 8016c5c: e140 b.n 8016ee0 #if LWIP_IPV4 if (ipaddr == NULL) { 8016c5e: 68bb ldr r3, [r7, #8] 8016c60: 2b00 cmp r3, #0 8016c62: d101 bne.n 8016c68 ipaddr = ip_2_ip4(IP4_ADDR_ANY); 8016c64: 4b8e ldr r3, [pc, #568] ; (8016ea0 ) 8016c66: 60bb str r3, [r7, #8] } if (netmask == NULL) { 8016c68: 687b ldr r3, [r7, #4] 8016c6a: 2b00 cmp r3, #0 8016c6c: d101 bne.n 8016c72 netmask = ip_2_ip4(IP4_ADDR_ANY); 8016c6e: 4b8c ldr r3, [pc, #560] ; (8016ea0 ) 8016c70: 607b str r3, [r7, #4] } if (gw == NULL) { 8016c72: 683b ldr r3, [r7, #0] 8016c74: 2b00 cmp r3, #0 8016c76: d101 bne.n 8016c7c gw = ip_2_ip4(IP4_ADDR_ANY); 8016c78: 4b89 ldr r3, [pc, #548] ; (8016ea0 ) 8016c7a: 603b str r3, [r7, #0] } /* reset new interface configuration state */ ip_addr_set_zero_ip4(&netif->ip_addr); 8016c7c: 68fb ldr r3, [r7, #12] 8016c7e: 2200 movs r2, #0 8016c80: 605a str r2, [r3, #4] ip_addr_set_zero_ip4(&netif->netmask); 8016c82: 68fb ldr r3, [r7, #12] 8016c84: 2200 movs r2, #0 8016c86: 609a str r2, [r3, #8] ip_addr_set_zero_ip4(&netif->gw); 8016c88: 68fb ldr r3, [r7, #12] 8016c8a: 2200 movs r2, #0 8016c8c: 60da str r2, [r3, #12] netif->output = netif_null_output_ip4; 8016c8e: 68fb ldr r3, [r7, #12] 8016c90: 4a84 ldr r2, [pc, #528] ; (8016ea4 ) 8016c92: 615a str r2, [r3, #20] #endif /* LWIP_IPV6_ADDRESS_LIFETIMES */ } netif->output_ip6 = netif_null_output_ip6; #endif /* LWIP_IPV6 */ NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL); netif->mtu = 0; 8016c94: 68fb ldr r3, [r7, #12] 8016c96: 2200 movs r2, #0 8016c98: 849a strh r2, [r3, #36] ; 0x24 netif->flags = 0; 8016c9a: 68fb ldr r3, [r7, #12] 8016c9c: 2200 movs r2, #0 8016c9e: f883 202d strb.w r2, [r3, #45] ; 0x2d #endif /* LWIP_IPV6 */ #if LWIP_NETIF_STATUS_CALLBACK netif->status_callback = NULL; #endif /* LWIP_NETIF_STATUS_CALLBACK */ #if LWIP_NETIF_LINK_CALLBACK netif->link_callback = NULL; 8016ca2: 68fb ldr r3, [r7, #12] 8016ca4: 2200 movs r2, #0 8016ca6: 61da str r2, [r3, #28] netif->loop_first = NULL; netif->loop_last = NULL; #endif /* ENABLE_LOOPBACK */ /* remember netif specific state information data */ netif->state = state; 8016ca8: 68fb ldr r3, [r7, #12] 8016caa: 6a3a ldr r2, [r7, #32] 8016cac: 621a str r2, [r3, #32] netif->num = netif_num; 8016cae: 4b7e ldr r3, [pc, #504] ; (8016ea8 ) 8016cb0: 781a ldrb r2, [r3, #0] 8016cb2: 68fb ldr r3, [r7, #12] 8016cb4: f883 2030 strb.w r2, [r3, #48] ; 0x30 netif->input = input; 8016cb8: 68fb ldr r3, [r7, #12] 8016cba: 6aba ldr r2, [r7, #40] ; 0x28 8016cbc: 611a str r2, [r3, #16] #if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS netif->loop_cnt_current = 0; #endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */ #if LWIP_IPV4 netif_set_addr(netif, ipaddr, netmask, gw); 8016cbe: 683b ldr r3, [r7, #0] 8016cc0: 687a ldr r2, [r7, #4] 8016cc2: 68b9 ldr r1, [r7, #8] 8016cc4: 68f8 ldr r0, [r7, #12] 8016cc6: f000 f9f5 bl 80170b4 #endif /* LWIP_IPV4 */ /* call user specified initialization function for netif */ if (init(netif) != ERR_OK) { 8016cca: 6a7b ldr r3, [r7, #36] ; 0x24 8016ccc: 68f8 ldr r0, [r7, #12] 8016cce: 4798 blx r3 8016cd0: 4603 mov r3, r0 8016cd2: 2b00 cmp r3, #0 8016cd4: d001 beq.n 8016cda return NULL; 8016cd6: 2300 movs r3, #0 8016cd8: e102 b.n 8016ee0 */ { struct netif *netif2; int num_netifs; do { if (netif->num == 255) { 8016cda: 68fb ldr r3, [r7, #12] 8016cdc: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 8016ce0: 2bff cmp r3, #255 ; 0xff 8016ce2: d103 bne.n 8016cec netif->num = 0; 8016ce4: 68fb ldr r3, [r7, #12] 8016ce6: 2200 movs r2, #0 8016ce8: f883 2030 strb.w r2, [r3, #48] ; 0x30 } num_netifs = 0; 8016cec: 2300 movs r3, #0 8016cee: 613b str r3, [r7, #16] for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) { 8016cf0: 4b6e ldr r3, [pc, #440] ; (8016eac ) 8016cf2: 681b ldr r3, [r3, #0] 8016cf4: 617b str r3, [r7, #20] 8016cf6: e02b b.n 8016d50 LWIP_ASSERT("netif already added", netif2 != netif); 8016cf8: 697a ldr r2, [r7, #20] 8016cfa: 68fb ldr r3, [r7, #12] 8016cfc: 429a cmp r2, r3 8016cfe: d106 bne.n 8016d0e 8016d00: 4b63 ldr r3, [pc, #396] ; (8016e90 ) 8016d02: f240 128b movw r2, #395 ; 0x18b 8016d06: 496a ldr r1, [pc, #424] ; (8016eb0 ) 8016d08: 4863 ldr r0, [pc, #396] ; (8016e98 ) 8016d0a: f00a fe3d bl 8021988 num_netifs++; 8016d0e: 693b ldr r3, [r7, #16] 8016d10: 3301 adds r3, #1 8016d12: 613b str r3, [r7, #16] LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255); 8016d14: 693b ldr r3, [r7, #16] 8016d16: 2bff cmp r3, #255 ; 0xff 8016d18: dd06 ble.n 8016d28 8016d1a: 4b5d ldr r3, [pc, #372] ; (8016e90 ) 8016d1c: f240 128d movw r2, #397 ; 0x18d 8016d20: 4964 ldr r1, [pc, #400] ; (8016eb4 ) 8016d22: 485d ldr r0, [pc, #372] ; (8016e98 ) 8016d24: f00a fe30 bl 8021988 if (netif2->num == netif->num) { 8016d28: 697b ldr r3, [r7, #20] 8016d2a: f893 2030 ldrb.w r2, [r3, #48] ; 0x30 8016d2e: 68fb ldr r3, [r7, #12] 8016d30: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 8016d34: 429a cmp r2, r3 8016d36: d108 bne.n 8016d4a netif->num++; 8016d38: 68fb ldr r3, [r7, #12] 8016d3a: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 8016d3e: 3301 adds r3, #1 8016d40: b2da uxtb r2, r3 8016d42: 68fb ldr r3, [r7, #12] 8016d44: f883 2030 strb.w r2, [r3, #48] ; 0x30 break; 8016d48: e005 b.n 8016d56 for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) { 8016d4a: 697b ldr r3, [r7, #20] 8016d4c: 681b ldr r3, [r3, #0] 8016d4e: 617b str r3, [r7, #20] 8016d50: 697b ldr r3, [r7, #20] 8016d52: 2b00 cmp r3, #0 8016d54: d1d0 bne.n 8016cf8 } } } while (netif2 != NULL); 8016d56: 697b ldr r3, [r7, #20] 8016d58: 2b00 cmp r3, #0 8016d5a: d1be bne.n 8016cda } if (netif->num == 254) { 8016d5c: 68fb ldr r3, [r7, #12] 8016d5e: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 8016d62: 2bfe cmp r3, #254 ; 0xfe 8016d64: d103 bne.n 8016d6e netif_num = 0; 8016d66: 4b50 ldr r3, [pc, #320] ; (8016ea8 ) 8016d68: 2200 movs r2, #0 8016d6a: 701a strb r2, [r3, #0] 8016d6c: e006 b.n 8016d7c } else { netif_num = (u8_t)(netif->num + 1); 8016d6e: 68fb ldr r3, [r7, #12] 8016d70: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 8016d74: 3301 adds r3, #1 8016d76: b2da uxtb r2, r3 8016d78: 4b4b ldr r3, [pc, #300] ; (8016ea8 ) 8016d7a: 701a strb r2, [r3, #0] } /* add this netif to the list */ netif->next = netif_list; 8016d7c: 4b4b ldr r3, [pc, #300] ; (8016eac ) 8016d7e: 681a ldr r2, [r3, #0] 8016d80: 68fb ldr r3, [r7, #12] 8016d82: 601a str r2, [r3, #0] netif_list = netif; 8016d84: 4a49 ldr r2, [pc, #292] ; (8016eac ) 8016d86: 68fb ldr r3, [r7, #12] 8016d88: 6013 str r3, [r2, #0] if (netif->flags & NETIF_FLAG_IGMP) { igmp_start(netif); } #endif /* LWIP_IGMP */ LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP", 8016d8a: 68fb ldr r3, [r7, #12] 8016d8c: f893 302e ldrb.w r3, [r3, #46] ; 0x2e 8016d90: 4619 mov r1, r3 8016d92: 68fb ldr r3, [r7, #12] 8016d94: f893 302f ldrb.w r3, [r3, #47] ; 0x2f 8016d98: 461a mov r2, r3 8016d9a: 4847 ldr r0, [pc, #284] ; (8016eb8 ) 8016d9c: f00a fdf4 bl 8021988 netif->name[0], netif->name[1])); #if LWIP_IPV4 LWIP_DEBUGF(NETIF_DEBUG, (" addr ")); 8016da0: 4846 ldr r0, [pc, #280] ; (8016ebc ) 8016da2: f00a fdf1 bl 8021988 ip4_addr_debug_print(NETIF_DEBUG, ipaddr); 8016da6: 68bb ldr r3, [r7, #8] 8016da8: 2b00 cmp r3, #0 8016daa: d003 beq.n 8016db4 8016dac: 68bb ldr r3, [r7, #8] 8016dae: 781b ldrb r3, [r3, #0] 8016db0: 4619 mov r1, r3 8016db2: e000 b.n 8016db6 8016db4: 2100 movs r1, #0 8016db6: 68bb ldr r3, [r7, #8] 8016db8: 2b00 cmp r3, #0 8016dba: d004 beq.n 8016dc6 8016dbc: 68bb ldr r3, [r7, #8] 8016dbe: 3301 adds r3, #1 8016dc0: 781b ldrb r3, [r3, #0] 8016dc2: 461a mov r2, r3 8016dc4: e000 b.n 8016dc8 8016dc6: 2200 movs r2, #0 8016dc8: 68bb ldr r3, [r7, #8] 8016dca: 2b00 cmp r3, #0 8016dcc: d004 beq.n 8016dd8 8016dce: 68bb ldr r3, [r7, #8] 8016dd0: 3302 adds r3, #2 8016dd2: 781b ldrb r3, [r3, #0] 8016dd4: 4618 mov r0, r3 8016dd6: e000 b.n 8016dda 8016dd8: 2000 movs r0, #0 8016dda: 68bb ldr r3, [r7, #8] 8016ddc: 2b00 cmp r3, #0 8016dde: d003 beq.n 8016de8 8016de0: 68bb ldr r3, [r7, #8] 8016de2: 3303 adds r3, #3 8016de4: 781b ldrb r3, [r3, #0] 8016de6: e000 b.n 8016dea 8016de8: 2300 movs r3, #0 8016dea: 9300 str r3, [sp, #0] 8016dec: 4603 mov r3, r0 8016dee: 4834 ldr r0, [pc, #208] ; (8016ec0 ) 8016df0: f00a fdca bl 8021988 LWIP_DEBUGF(NETIF_DEBUG, (" netmask ")); 8016df4: 4833 ldr r0, [pc, #204] ; (8016ec4 ) 8016df6: f00a fdc7 bl 8021988 ip4_addr_debug_print(NETIF_DEBUG, netmask); 8016dfa: 687b ldr r3, [r7, #4] 8016dfc: 2b00 cmp r3, #0 8016dfe: d003 beq.n 8016e08 8016e00: 687b ldr r3, [r7, #4] 8016e02: 781b ldrb r3, [r3, #0] 8016e04: 4619 mov r1, r3 8016e06: e000 b.n 8016e0a 8016e08: 2100 movs r1, #0 8016e0a: 687b ldr r3, [r7, #4] 8016e0c: 2b00 cmp r3, #0 8016e0e: d004 beq.n 8016e1a 8016e10: 687b ldr r3, [r7, #4] 8016e12: 3301 adds r3, #1 8016e14: 781b ldrb r3, [r3, #0] 8016e16: 461a mov r2, r3 8016e18: e000 b.n 8016e1c 8016e1a: 2200 movs r2, #0 8016e1c: 687b ldr r3, [r7, #4] 8016e1e: 2b00 cmp r3, #0 8016e20: d004 beq.n 8016e2c 8016e22: 687b ldr r3, [r7, #4] 8016e24: 3302 adds r3, #2 8016e26: 781b ldrb r3, [r3, #0] 8016e28: 4618 mov r0, r3 8016e2a: e000 b.n 8016e2e 8016e2c: 2000 movs r0, #0 8016e2e: 687b ldr r3, [r7, #4] 8016e30: 2b00 cmp r3, #0 8016e32: d003 beq.n 8016e3c 8016e34: 687b ldr r3, [r7, #4] 8016e36: 3303 adds r3, #3 8016e38: 781b ldrb r3, [r3, #0] 8016e3a: e000 b.n 8016e3e 8016e3c: 2300 movs r3, #0 8016e3e: 9300 str r3, [sp, #0] 8016e40: 4603 mov r3, r0 8016e42: 481f ldr r0, [pc, #124] ; (8016ec0 ) 8016e44: f00a fda0 bl 8021988 LWIP_DEBUGF(NETIF_DEBUG, (" gw ")); 8016e48: 481f ldr r0, [pc, #124] ; (8016ec8 ) 8016e4a: f00a fd9d bl 8021988 ip4_addr_debug_print(NETIF_DEBUG, gw); 8016e4e: 683b ldr r3, [r7, #0] 8016e50: 2b00 cmp r3, #0 8016e52: d003 beq.n 8016e5c 8016e54: 683b ldr r3, [r7, #0] 8016e56: 781b ldrb r3, [r3, #0] 8016e58: 4619 mov r1, r3 8016e5a: e000 b.n 8016e5e 8016e5c: 2100 movs r1, #0 8016e5e: 683b ldr r3, [r7, #0] 8016e60: 2b00 cmp r3, #0 8016e62: d004 beq.n 8016e6e 8016e64: 683b ldr r3, [r7, #0] 8016e66: 3301 adds r3, #1 8016e68: 781b ldrb r3, [r3, #0] 8016e6a: 461a mov r2, r3 8016e6c: e000 b.n 8016e70 8016e6e: 2200 movs r2, #0 8016e70: 683b ldr r3, [r7, #0] 8016e72: 2b00 cmp r3, #0 8016e74: d004 beq.n 8016e80 8016e76: 683b ldr r3, [r7, #0] 8016e78: 3302 adds r3, #2 8016e7a: 781b ldrb r3, [r3, #0] 8016e7c: 4618 mov r0, r3 8016e7e: e000 b.n 8016e82 8016e80: 2000 movs r0, #0 8016e82: 683b ldr r3, [r7, #0] 8016e84: 2b00 cmp r3, #0 8016e86: d021 beq.n 8016ecc 8016e88: 683b ldr r3, [r7, #0] 8016e8a: 3303 adds r3, #3 8016e8c: 781b ldrb r3, [r3, #0] 8016e8e: e01e b.n 8016ece 8016e90: 08024308 .word 0x08024308 8016e94: 0802439c .word 0x0802439c 8016e98: 08024358 .word 0x08024358 8016e9c: 080243b8 .word 0x080243b8 8016ea0: 08026cec .word 0x08026cec 8016ea4: 080173b7 .word 0x080173b7 8016ea8: 2401a47c .word 0x2401a47c 8016eac: 2401a474 .word 0x2401a474 8016eb0: 080243dc .word 0x080243dc 8016eb4: 080243f0 .word 0x080243f0 8016eb8: 08024420 .word 0x08024420 8016ebc: 08024440 .word 0x08024440 8016ec0: 08024448 .word 0x08024448 8016ec4: 08024458 .word 0x08024458 8016ec8: 08024464 .word 0x08024464 8016ecc: 2300 movs r3, #0 8016ece: 9300 str r3, [sp, #0] 8016ed0: 4603 mov r3, r0 8016ed2: 4805 ldr r0, [pc, #20] ; (8016ee8 ) 8016ed4: f00a fd58 bl 8021988 #endif /* LWIP_IPV4 */ LWIP_DEBUGF(NETIF_DEBUG, ("\n")); 8016ed8: 200a movs r0, #10 8016eda: f00a fd67 bl 80219ac netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL); return netif; 8016ede: 68fb ldr r3, [r7, #12] } 8016ee0: 4618 mov r0, r3 8016ee2: 3718 adds r7, #24 8016ee4: 46bd mov sp, r7 8016ee6: bd80 pop {r7, pc} 8016ee8: 08024448 .word 0x08024448 08016eec : static void netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) { 8016eec: b580 push {r7, lr} 8016eee: b082 sub sp, #8 8016ef0: af00 add r7, sp, #0 8016ef2: 6078 str r0, [r7, #4] 8016ef4: 6039 str r1, [r7, #0] #if LWIP_TCP tcp_netif_ip_addr_changed(old_addr, new_addr); 8016ef6: 6839 ldr r1, [r7, #0] 8016ef8: 6878 ldr r0, [r7, #4] 8016efa: f002 ff09 bl 8019d10 #endif /* LWIP_TCP */ #if LWIP_UDP udp_netif_ip_addr_changed(old_addr, new_addr); 8016efe: 6839 ldr r1, [r7, #0] 8016f00: 6878 ldr r0, [r7, #4] 8016f02: f007 fe95 bl 801ec30 #endif /* LWIP_UDP */ #if LWIP_RAW raw_netif_ip_addr_changed(old_addr, new_addr); #endif /* LWIP_RAW */ } 8016f06: bf00 nop 8016f08: 3708 adds r7, #8 8016f0a: 46bd mov sp, r7 8016f0c: bd80 pop {r7, pc} ... 08016f10 : #if LWIP_IPV4 static int netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr) { 8016f10: b580 push {r7, lr} 8016f12: b086 sub sp, #24 8016f14: af00 add r7, sp, #0 8016f16: 60f8 str r0, [r7, #12] 8016f18: 60b9 str r1, [r7, #8] 8016f1a: 607a str r2, [r7, #4] LWIP_ASSERT("invalid pointer", ipaddr != NULL); 8016f1c: 68bb ldr r3, [r7, #8] 8016f1e: 2b00 cmp r3, #0 8016f20: d106 bne.n 8016f30 8016f22: 4b1e ldr r3, [pc, #120] ; (8016f9c ) 8016f24: f240 12cb movw r2, #459 ; 0x1cb 8016f28: 491d ldr r1, [pc, #116] ; (8016fa0 ) 8016f2a: 481e ldr r0, [pc, #120] ; (8016fa4 ) 8016f2c: f00a fd2c bl 8021988 LWIP_ASSERT("invalid pointer", old_addr != NULL); 8016f30: 687b ldr r3, [r7, #4] 8016f32: 2b00 cmp r3, #0 8016f34: d106 bne.n 8016f44 8016f36: 4b19 ldr r3, [pc, #100] ; (8016f9c ) 8016f38: f44f 72e6 mov.w r2, #460 ; 0x1cc 8016f3c: 4918 ldr r1, [pc, #96] ; (8016fa0 ) 8016f3e: 4819 ldr r0, [pc, #100] ; (8016fa4 ) 8016f40: f00a fd22 bl 8021988 /* address is actually being changed? */ if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) { 8016f44: 68bb ldr r3, [r7, #8] 8016f46: 681a ldr r2, [r3, #0] 8016f48: 68fb ldr r3, [r7, #12] 8016f4a: 3304 adds r3, #4 8016f4c: 681b ldr r3, [r3, #0] 8016f4e: 429a cmp r2, r3 8016f50: d01f beq.n 8016f92 ip_addr_t new_addr; *ip_2_ip4(&new_addr) = *ipaddr; 8016f52: 68bb ldr r3, [r7, #8] 8016f54: 681b ldr r3, [r3, #0] 8016f56: 617b str r3, [r7, #20] IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4); ip_addr_copy(*old_addr, *netif_ip_addr4(netif)); 8016f58: 68fb ldr r3, [r7, #12] 8016f5a: 3304 adds r3, #4 8016f5c: 681a ldr r2, [r3, #0] 8016f5e: 687b ldr r3, [r7, #4] 8016f60: 601a str r2, [r3, #0] LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n")); 8016f62: 4811 ldr r0, [pc, #68] ; (8016fa8 ) 8016f64: f00a fd7e bl 8021a64 netif_do_ip_addr_changed(old_addr, &new_addr); 8016f68: f107 0314 add.w r3, r7, #20 8016f6c: 4619 mov r1, r3 8016f6e: 6878 ldr r0, [r7, #4] 8016f70: f7ff ffbc bl 8016eec mib2_remove_ip4(netif); mib2_remove_route_ip4(0, netif); /* set new IP address to netif */ ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr); 8016f74: 68bb ldr r3, [r7, #8] 8016f76: 2b00 cmp r3, #0 8016f78: d002 beq.n 8016f80 8016f7a: 68bb ldr r3, [r7, #8] 8016f7c: 681b ldr r3, [r3, #0] 8016f7e: e000 b.n 8016f82 8016f80: 2300 movs r3, #0 8016f82: 68fa ldr r2, [r7, #12] 8016f84: 6053 str r3, [r2, #4] IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4); mib2_add_ip4(netif); mib2_add_route_ip4(0, netif); netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4); 8016f86: 2101 movs r1, #1 8016f88: 68f8 ldr r0, [r7, #12] 8016f8a: f000 f92d bl 80171e8 NETIF_STATUS_CALLBACK(netif); return 1; /* address changed */ 8016f8e: 2301 movs r3, #1 8016f90: e000 b.n 8016f94 } return 0; /* address unchanged */ 8016f92: 2300 movs r3, #0 } 8016f94: 4618 mov r0, r3 8016f96: 3718 adds r7, #24 8016f98: 46bd mov sp, r7 8016f9a: bd80 pop {r7, pc} 8016f9c: 08024308 .word 0x08024308 8016fa0: 0802446c .word 0x0802446c 8016fa4: 08024358 .word 0x08024358 8016fa8: 0802447c .word 0x0802447c 08016fac : } } static int netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm) { 8016fac: b5b0 push {r4, r5, r7, lr} 8016fae: b088 sub sp, #32 8016fb0: af04 add r7, sp, #16 8016fb2: 60f8 str r0, [r7, #12] 8016fb4: 60b9 str r1, [r7, #8] 8016fb6: 607a str r2, [r7, #4] /* address is actually being changed? */ if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) { 8016fb8: 68bb ldr r3, [r7, #8] 8016fba: 681a ldr r2, [r3, #0] 8016fbc: 68fb ldr r3, [r7, #12] 8016fbe: 3308 adds r3, #8 8016fc0: 681b ldr r3, [r3, #0] 8016fc2: 429a cmp r2, r3 8016fc4: d02d beq.n 8017022 #else LWIP_UNUSED_ARG(old_nm); #endif mib2_remove_route_ip4(0, netif); /* set new netmask to netif */ ip4_addr_set(ip_2_ip4(&netif->netmask), netmask); 8016fc6: 68bb ldr r3, [r7, #8] 8016fc8: 2b00 cmp r3, #0 8016fca: d002 beq.n 8016fd2 8016fcc: 68bb ldr r3, [r7, #8] 8016fce: 681b ldr r3, [r3, #0] 8016fd0: e000 b.n 8016fd4 8016fd2: 2300 movs r3, #0 8016fd4: 68fa ldr r2, [r7, #12] 8016fd6: 6093 str r3, [r2, #8] IP_SET_TYPE_VAL(netif->netmask, IPADDR_TYPE_V4); mib2_add_route_ip4(0, netif); LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", 8016fd8: 68fb ldr r3, [r7, #12] 8016fda: f893 302e ldrb.w r3, [r3, #46] ; 0x2e 8016fde: 4618 mov r0, r3 8016fe0: 68fb ldr r3, [r7, #12] 8016fe2: f893 302f ldrb.w r3, [r3, #47] ; 0x2f 8016fe6: 461c mov r4, r3 8016fe8: 68fb ldr r3, [r7, #12] 8016fea: 3308 adds r3, #8 8016fec: 781b ldrb r3, [r3, #0] 8016fee: 461d mov r5, r3 8016ff0: 68fb ldr r3, [r7, #12] 8016ff2: 3308 adds r3, #8 8016ff4: 3301 adds r3, #1 8016ff6: 781b ldrb r3, [r3, #0] 8016ff8: 461a mov r2, r3 8016ffa: 68fb ldr r3, [r7, #12] 8016ffc: 3308 adds r3, #8 8016ffe: 3302 adds r3, #2 8017000: 781b ldrb r3, [r3, #0] 8017002: 4619 mov r1, r3 8017004: 68fb ldr r3, [r7, #12] 8017006: 3308 adds r3, #8 8017008: 3303 adds r3, #3 801700a: 781b ldrb r3, [r3, #0] 801700c: 9302 str r3, [sp, #8] 801700e: 9101 str r1, [sp, #4] 8017010: 9200 str r2, [sp, #0] 8017012: 462b mov r3, r5 8017014: 4622 mov r2, r4 8017016: 4601 mov r1, r0 8017018: 4804 ldr r0, [pc, #16] ; (801702c ) 801701a: f00a fcb5 bl 8021988 netif->name[0], netif->name[1], ip4_addr1_16(netif_ip4_netmask(netif)), ip4_addr2_16(netif_ip4_netmask(netif)), ip4_addr3_16(netif_ip4_netmask(netif)), ip4_addr4_16(netif_ip4_netmask(netif)))); return 1; /* netmask changed */ 801701e: 2301 movs r3, #1 8017020: e000 b.n 8017024 } return 0; /* netmask unchanged */ 8017022: 2300 movs r3, #0 } 8017024: 4618 mov r0, r3 8017026: 3710 adds r7, #16 8017028: 46bd mov sp, r7 801702a: bdb0 pop {r4, r5, r7, pc} 801702c: 080244cc .word 0x080244cc 08017030 : } } static int netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw) { 8017030: b5b0 push {r4, r5, r7, lr} 8017032: b088 sub sp, #32 8017034: af04 add r7, sp, #16 8017036: 60f8 str r0, [r7, #12] 8017038: 60b9 str r1, [r7, #8] 801703a: 607a str r2, [r7, #4] /* address is actually being changed? */ if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) { 801703c: 68bb ldr r3, [r7, #8] 801703e: 681a ldr r2, [r3, #0] 8017040: 68fb ldr r3, [r7, #12] 8017042: 330c adds r3, #12 8017044: 681b ldr r3, [r3, #0] 8017046: 429a cmp r2, r3 8017048: d02d beq.n 80170a6 ip_addr_copy(*old_gw, *netif_ip_gw4(netif)); #else LWIP_UNUSED_ARG(old_gw); #endif ip4_addr_set(ip_2_ip4(&netif->gw), gw); 801704a: 68bb ldr r3, [r7, #8] 801704c: 2b00 cmp r3, #0 801704e: d002 beq.n 8017056 8017050: 68bb ldr r3, [r7, #8] 8017052: 681b ldr r3, [r3, #0] 8017054: e000 b.n 8017058 8017056: 2300 movs r3, #0 8017058: 68fa ldr r2, [r7, #12] 801705a: 60d3 str r3, [r2, #12] IP_SET_TYPE_VAL(netif->gw, IPADDR_TYPE_V4); LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", 801705c: 68fb ldr r3, [r7, #12] 801705e: f893 302e ldrb.w r3, [r3, #46] ; 0x2e 8017062: 4618 mov r0, r3 8017064: 68fb ldr r3, [r7, #12] 8017066: f893 302f ldrb.w r3, [r3, #47] ; 0x2f 801706a: 461c mov r4, r3 801706c: 68fb ldr r3, [r7, #12] 801706e: 330c adds r3, #12 8017070: 781b ldrb r3, [r3, #0] 8017072: 461d mov r5, r3 8017074: 68fb ldr r3, [r7, #12] 8017076: 330c adds r3, #12 8017078: 3301 adds r3, #1 801707a: 781b ldrb r3, [r3, #0] 801707c: 461a mov r2, r3 801707e: 68fb ldr r3, [r7, #12] 8017080: 330c adds r3, #12 8017082: 3302 adds r3, #2 8017084: 781b ldrb r3, [r3, #0] 8017086: 4619 mov r1, r3 8017088: 68fb ldr r3, [r7, #12] 801708a: 330c adds r3, #12 801708c: 3303 adds r3, #3 801708e: 781b ldrb r3, [r3, #0] 8017090: 9302 str r3, [sp, #8] 8017092: 9101 str r1, [sp, #4] 8017094: 9200 str r2, [sp, #0] 8017096: 462b mov r3, r5 8017098: 4622 mov r2, r4 801709a: 4601 mov r1, r0 801709c: 4804 ldr r0, [pc, #16] ; (80170b0 ) 801709e: f00a fc73 bl 8021988 netif->name[0], netif->name[1], ip4_addr1_16(netif_ip4_gw(netif)), ip4_addr2_16(netif_ip4_gw(netif)), ip4_addr3_16(netif_ip4_gw(netif)), ip4_addr4_16(netif_ip4_gw(netif)))); return 1; /* gateway changed */ 80170a2: 2301 movs r3, #1 80170a4: e000 b.n 80170a8 } return 0; /* gateway unchanged */ 80170a6: 2300 movs r3, #0 } 80170a8: 4618 mov r0, r3 80170aa: 3710 adds r7, #16 80170ac: 46bd mov sp, r7 80170ae: bdb0 pop {r4, r5, r7, pc} 80170b0: 0802452c .word 0x0802452c 080170b4 : * @param gw the new default gateway */ void netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw) { 80170b4: b580 push {r7, lr} 80170b6: b088 sub sp, #32 80170b8: af00 add r7, sp, #0 80170ba: 60f8 str r0, [r7, #12] 80170bc: 60b9 str r1, [r7, #8] 80170be: 607a str r2, [r7, #4] 80170c0: 603b str r3, [r7, #0] ip_addr_t old_nm_val; ip_addr_t old_gw_val; ip_addr_t *old_nm = &old_nm_val; ip_addr_t *old_gw = &old_gw_val; #else ip_addr_t *old_nm = NULL; 80170c2: 2300 movs r3, #0 80170c4: 61fb str r3, [r7, #28] ip_addr_t *old_gw = NULL; 80170c6: 2300 movs r3, #0 80170c8: 61bb str r3, [r7, #24] int remove; LWIP_ASSERT_CORE_LOCKED(); /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ if (ipaddr == NULL) { 80170ca: 68bb ldr r3, [r7, #8] 80170cc: 2b00 cmp r3, #0 80170ce: d101 bne.n 80170d4 ipaddr = IP4_ADDR_ANY4; 80170d0: 4b1c ldr r3, [pc, #112] ; (8017144 ) 80170d2: 60bb str r3, [r7, #8] } if (netmask == NULL) { 80170d4: 687b ldr r3, [r7, #4] 80170d6: 2b00 cmp r3, #0 80170d8: d101 bne.n 80170de netmask = IP4_ADDR_ANY4; 80170da: 4b1a ldr r3, [pc, #104] ; (8017144 ) 80170dc: 607b str r3, [r7, #4] } if (gw == NULL) { 80170de: 683b ldr r3, [r7, #0] 80170e0: 2b00 cmp r3, #0 80170e2: d101 bne.n 80170e8 gw = IP4_ADDR_ANY4; 80170e4: 4b17 ldr r3, [pc, #92] ; (8017144 ) 80170e6: 603b str r3, [r7, #0] } remove = ip4_addr_isany(ipaddr); 80170e8: 68bb ldr r3, [r7, #8] 80170ea: 2b00 cmp r3, #0 80170ec: d003 beq.n 80170f6 80170ee: 68bb ldr r3, [r7, #8] 80170f0: 681b ldr r3, [r3, #0] 80170f2: 2b00 cmp r3, #0 80170f4: d101 bne.n 80170fa 80170f6: 2301 movs r3, #1 80170f8: e000 b.n 80170fc 80170fa: 2300 movs r3, #0 80170fc: 617b str r3, [r7, #20] if (remove) { 80170fe: 697b ldr r3, [r7, #20] 8017100: 2b00 cmp r3, #0 8017102: d006 beq.n 8017112 /* when removing an address, we have to remove it *before* changing netmask/gw to ensure that tcp RST segment can be sent correctly */ if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) { 8017104: f107 0310 add.w r3, r7, #16 8017108: 461a mov r2, r3 801710a: 68b9 ldr r1, [r7, #8] 801710c: 68f8 ldr r0, [r7, #12] 801710e: f7ff feff bl 8016f10 change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED; cb_args.ipv4_changed.old_address = &old_addr; #endif } } if (netif_do_set_netmask(netif, netmask, old_nm)) { 8017112: 69fa ldr r2, [r7, #28] 8017114: 6879 ldr r1, [r7, #4] 8017116: 68f8 ldr r0, [r7, #12] 8017118: f7ff ff48 bl 8016fac #if LWIP_NETIF_EXT_STATUS_CALLBACK change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED; cb_args.ipv4_changed.old_netmask = old_nm; #endif } if (netif_do_set_gw(netif, gw, old_gw)) { 801711c: 69ba ldr r2, [r7, #24] 801711e: 6839 ldr r1, [r7, #0] 8017120: 68f8 ldr r0, [r7, #12] 8017122: f7ff ff85 bl 8017030 #if LWIP_NETIF_EXT_STATUS_CALLBACK change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED; cb_args.ipv4_changed.old_gw = old_gw; #endif } if (!remove) { 8017126: 697b ldr r3, [r7, #20] 8017128: 2b00 cmp r3, #0 801712a: d106 bne.n 801713a /* set ipaddr last to ensure netmask/gw have been set when status callback is called */ if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) { 801712c: f107 0310 add.w r3, r7, #16 8017130: 461a mov r2, r3 8017132: 68b9 ldr r1, [r7, #8] 8017134: 68f8 ldr r0, [r7, #12] 8017136: f7ff feeb bl 8016f10 if (change_reason != LWIP_NSC_NONE) { change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED; netif_invoke_ext_callback(netif, change_reason, &cb_args); } #endif } 801713a: bf00 nop 801713c: 3720 adds r7, #32 801713e: 46bd mov sp, r7 8017140: bd80 pop {r7, pc} 8017142: bf00 nop 8017144: 08026cec .word 0x08026cec 08017148 : * * @param netif the default network interface */ void netif_set_default(struct netif *netif) { 8017148: b580 push {r7, lr} 801714a: b082 sub sp, #8 801714c: af00 add r7, sp, #0 801714e: 6078 str r0, [r7, #4] mib2_remove_route_ip4(1, netif); } else { /* install default route */ mib2_add_route_ip4(1, netif); } netif_default = netif; 8017150: 4a0d ldr r2, [pc, #52] ; (8017188 ) 8017152: 687b ldr r3, [r7, #4] 8017154: 6013 str r3, [r2, #0] LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", 8017156: 687b ldr r3, [r7, #4] 8017158: 2b00 cmp r3, #0 801715a: d004 beq.n 8017166 801715c: 687b ldr r3, [r7, #4] 801715e: f893 302e ldrb.w r3, [r3, #46] ; 0x2e 8017162: 4619 mov r1, r3 8017164: e000 b.n 8017168 8017166: 2127 movs r1, #39 ; 0x27 8017168: 687b ldr r3, [r7, #4] 801716a: 2b00 cmp r3, #0 801716c: d003 beq.n 8017176 801716e: 687b ldr r3, [r7, #4] 8017170: f893 302f ldrb.w r3, [r3, #47] ; 0x2f 8017174: e000 b.n 8017178 8017176: 2327 movs r3, #39 ; 0x27 8017178: 461a mov r2, r3 801717a: 4804 ldr r0, [pc, #16] ; (801718c ) 801717c: f00a fc04 bl 8021988 netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); } 8017180: bf00 nop 8017182: 3708 adds r7, #8 8017184: 46bd mov sp, r7 8017186: bd80 pop {r7, pc} 8017188: 2401a478 .word 0x2401a478 801718c: 080245a0 .word 0x080245a0 08017190 : * Bring an interface up, available for processing * traffic. */ void netif_set_up(struct netif *netif) { 8017190: b580 push {r7, lr} 8017192: b082 sub sp, #8 8017194: af00 add r7, sp, #0 8017196: 6078 str r0, [r7, #4] LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return); 8017198: 687b ldr r3, [r7, #4] 801719a: 2b00 cmp r3, #0 801719c: d107 bne.n 80171ae 801719e: 4b0f ldr r3, [pc, #60] ; (80171dc ) 80171a0: f44f 7254 mov.w r2, #848 ; 0x350 80171a4: 490e ldr r1, [pc, #56] ; (80171e0 ) 80171a6: 480f ldr r0, [pc, #60] ; (80171e4 ) 80171a8: f00a fbee bl 8021988 80171ac: e013 b.n 80171d6 if (!(netif->flags & NETIF_FLAG_UP)) { 80171ae: 687b ldr r3, [r7, #4] 80171b0: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 80171b4: f003 0301 and.w r3, r3, #1 80171b8: 2b00 cmp r3, #0 80171ba: d10c bne.n 80171d6 netif_set_flags(netif, NETIF_FLAG_UP); 80171bc: 687b ldr r3, [r7, #4] 80171be: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 80171c2: f043 0301 orr.w r3, r3, #1 80171c6: b2da uxtb r2, r3 80171c8: 687b ldr r3, [r7, #4] 80171ca: f883 202d strb.w r2, [r3, #45] ; 0x2d args.status_changed.state = 1; netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args); } #endif netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6); 80171ce: 2103 movs r1, #3 80171d0: 6878 ldr r0, [r7, #4] 80171d2: f000 f809 bl 80171e8 #if LWIP_IPV6 nd6_restart_netif(netif); #endif /* LWIP_IPV6 */ } } 80171d6: 3708 adds r7, #8 80171d8: 46bd mov sp, r7 80171da: bd80 pop {r7, pc} 80171dc: 08024308 .word 0x08024308 80171e0: 080245c8 .word 0x080245c8 80171e4: 08024358 .word 0x08024358 080171e8 : /** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change */ static void netif_issue_reports(struct netif *netif, u8_t report_type) { 80171e8: b580 push {r7, lr} 80171ea: b082 sub sp, #8 80171ec: af00 add r7, sp, #0 80171ee: 6078 str r0, [r7, #4] 80171f0: 460b mov r3, r1 80171f2: 70fb strb r3, [r7, #3] LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL); 80171f4: 687b ldr r3, [r7, #4] 80171f6: 2b00 cmp r3, #0 80171f8: d106 bne.n 8017208 80171fa: 4b18 ldr r3, [pc, #96] ; (801725c ) 80171fc: f240 326d movw r2, #877 ; 0x36d 8017200: 4917 ldr r1, [pc, #92] ; (8017260 ) 8017202: 4818 ldr r0, [pc, #96] ; (8017264 ) 8017204: f00a fbc0 bl 8021988 /* Only send reports when both link and admin states are up */ if (!(netif->flags & NETIF_FLAG_LINK_UP) || 8017208: 687b ldr r3, [r7, #4] 801720a: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801720e: f003 0304 and.w r3, r3, #4 8017212: 2b00 cmp r3, #0 8017214: d01e beq.n 8017254 !(netif->flags & NETIF_FLAG_UP)) { 8017216: 687b ldr r3, [r7, #4] 8017218: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801721c: f003 0301 and.w r3, r3, #1 if (!(netif->flags & NETIF_FLAG_LINK_UP) || 8017220: 2b00 cmp r3, #0 8017222: d017 beq.n 8017254 return; } #if LWIP_IPV4 if ((report_type & NETIF_REPORT_TYPE_IPV4) && 8017224: 78fb ldrb r3, [r7, #3] 8017226: f003 0301 and.w r3, r3, #1 801722a: 2b00 cmp r3, #0 801722c: d013 beq.n 8017256 !ip4_addr_isany_val(*netif_ip4_addr(netif))) { 801722e: 687b ldr r3, [r7, #4] 8017230: 3304 adds r3, #4 8017232: 681b ldr r3, [r3, #0] if ((report_type & NETIF_REPORT_TYPE_IPV4) && 8017234: 2b00 cmp r3, #0 8017236: d00e beq.n 8017256 #if LWIP_ARP /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ if (netif->flags & (NETIF_FLAG_ETHARP)) { 8017238: 687b ldr r3, [r7, #4] 801723a: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801723e: f003 0308 and.w r3, r3, #8 8017242: 2b00 cmp r3, #0 8017244: d007 beq.n 8017256 etharp_gratuitous(netif); 8017246: 687b ldr r3, [r7, #4] 8017248: 3304 adds r3, #4 801724a: 4619 mov r1, r3 801724c: 6878 ldr r0, [r7, #4] 801724e: f008 fc87 bl 801fb60 8017252: e000 b.n 8017256 return; 8017254: bf00 nop /* send mld memberships */ mld6_report_groups(netif); #endif /* LWIP_IPV6_MLD */ } #endif /* LWIP_IPV6 */ } 8017256: 3708 adds r7, #8 8017258: 46bd mov sp, r7 801725a: bd80 pop {r7, pc} 801725c: 08024308 .word 0x08024308 8017260: 080245e4 .word 0x080245e4 8017264: 08024358 .word 0x08024358 08017268 : * @ingroup netif * Bring an interface down, disabling any traffic processing. */ void netif_set_down(struct netif *netif) { 8017268: b580 push {r7, lr} 801726a: b082 sub sp, #8 801726c: af00 add r7, sp, #0 801726e: 6078 str r0, [r7, #4] LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return); 8017270: 687b ldr r3, [r7, #4] 8017272: 2b00 cmp r3, #0 8017274: d107 bne.n 8017286 8017276: 4b12 ldr r3, [pc, #72] ; (80172c0 ) 8017278: f240 329b movw r2, #923 ; 0x39b 801727c: 4911 ldr r1, [pc, #68] ; (80172c4 ) 801727e: 4812 ldr r0, [pc, #72] ; (80172c8 ) 8017280: f00a fb82 bl 8021988 8017284: e019 b.n 80172ba if (netif->flags & NETIF_FLAG_UP) { 8017286: 687b ldr r3, [r7, #4] 8017288: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801728c: f003 0301 and.w r3, r3, #1 8017290: 2b00 cmp r3, #0 8017292: d012 beq.n 80172ba args.status_changed.state = 0; netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args); } #endif netif_clear_flags(netif, NETIF_FLAG_UP); 8017294: 687b ldr r3, [r7, #4] 8017296: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801729a: f023 0301 bic.w r3, r3, #1 801729e: b2da uxtb r2, r3 80172a0: 687b ldr r3, [r7, #4] 80172a2: f883 202d strb.w r2, [r3, #45] ; 0x2d MIB2_COPY_SYSUPTIME_TO(&netif->ts); #if LWIP_IPV4 && LWIP_ARP if (netif->flags & NETIF_FLAG_ETHARP) { 80172a6: 687b ldr r3, [r7, #4] 80172a8: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 80172ac: f003 0308 and.w r3, r3, #8 80172b0: 2b00 cmp r3, #0 80172b2: d002 beq.n 80172ba etharp_cleanup_netif(netif); 80172b4: 6878 ldr r0, [r7, #4] 80172b6: f008 f811 bl 801f2dc nd6_cleanup_netif(netif); #endif /* LWIP_IPV6 */ NETIF_STATUS_CALLBACK(netif); } } 80172ba: 3708 adds r7, #8 80172bc: 46bd mov sp, r7 80172be: bd80 pop {r7, pc} 80172c0: 08024308 .word 0x08024308 80172c4: 08024608 .word 0x08024608 80172c8: 08024358 .word 0x08024358 080172cc : * @ingroup netif * Called by a driver when its link goes up */ void netif_set_link_up(struct netif *netif) { 80172cc: b580 push {r7, lr} 80172ce: b082 sub sp, #8 80172d0: af00 add r7, sp, #0 80172d2: 6078 str r0, [r7, #4] LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return); 80172d4: 687b ldr r3, [r7, #4] 80172d6: 2b00 cmp r3, #0 80172d8: d107 bne.n 80172ea 80172da: 4b13 ldr r3, [pc, #76] ; (8017328 ) 80172dc: f44f 7278 mov.w r2, #992 ; 0x3e0 80172e0: 4912 ldr r1, [pc, #72] ; (801732c ) 80172e2: 4813 ldr r0, [pc, #76] ; (8017330 ) 80172e4: f00a fb50 bl 8021988 80172e8: e01b b.n 8017322 if (!(netif->flags & NETIF_FLAG_LINK_UP)) { 80172ea: 687b ldr r3, [r7, #4] 80172ec: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 80172f0: f003 0304 and.w r3, r3, #4 80172f4: 2b00 cmp r3, #0 80172f6: d114 bne.n 8017322 netif_set_flags(netif, NETIF_FLAG_LINK_UP); 80172f8: 687b ldr r3, [r7, #4] 80172fa: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 80172fe: f043 0304 orr.w r3, r3, #4 8017302: b2da uxtb r2, r3 8017304: 687b ldr r3, [r7, #4] 8017306: f883 202d strb.w r2, [r3, #45] ; 0x2d #if LWIP_AUTOIP autoip_network_changed(netif); #endif /* LWIP_AUTOIP */ netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6); 801730a: 2103 movs r1, #3 801730c: 6878 ldr r0, [r7, #4] 801730e: f7ff ff6b bl 80171e8 #if LWIP_IPV6 nd6_restart_netif(netif); #endif /* LWIP_IPV6 */ NETIF_LINK_CALLBACK(netif); 8017312: 687b ldr r3, [r7, #4] 8017314: 69db ldr r3, [r3, #28] 8017316: 2b00 cmp r3, #0 8017318: d003 beq.n 8017322 801731a: 687b ldr r3, [r7, #4] 801731c: 69db ldr r3, [r3, #28] 801731e: 6878 ldr r0, [r7, #4] 8017320: 4798 blx r3 args.link_changed.state = 1; netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args); } #endif } } 8017322: 3708 adds r7, #8 8017324: 46bd mov sp, r7 8017326: bd80 pop {r7, pc} 8017328: 08024308 .word 0x08024308 801732c: 08024628 .word 0x08024628 8017330: 08024358 .word 0x08024358 08017334 : * @ingroup netif * Called by a driver when its link goes down */ void netif_set_link_down(struct netif *netif) { 8017334: b580 push {r7, lr} 8017336: b082 sub sp, #8 8017338: af00 add r7, sp, #0 801733a: 6078 str r0, [r7, #4] LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return); 801733c: 687b ldr r3, [r7, #4] 801733e: 2b00 cmp r3, #0 8017340: d107 bne.n 8017352 8017342: 4b11 ldr r3, [pc, #68] ; (8017388 ) 8017344: f240 4206 movw r2, #1030 ; 0x406 8017348: 4910 ldr r1, [pc, #64] ; (801738c ) 801734a: 4811 ldr r0, [pc, #68] ; (8017390 ) 801734c: f00a fb1c bl 8021988 8017350: e017 b.n 8017382 if (netif->flags & NETIF_FLAG_LINK_UP) { 8017352: 687b ldr r3, [r7, #4] 8017354: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 8017358: f003 0304 and.w r3, r3, #4 801735c: 2b00 cmp r3, #0 801735e: d010 beq.n 8017382 netif_clear_flags(netif, NETIF_FLAG_LINK_UP); 8017360: 687b ldr r3, [r7, #4] 8017362: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 8017366: f023 0304 bic.w r3, r3, #4 801736a: b2da uxtb r2, r3 801736c: 687b ldr r3, [r7, #4] 801736e: f883 202d strb.w r2, [r3, #45] ; 0x2d NETIF_LINK_CALLBACK(netif); 8017372: 687b ldr r3, [r7, #4] 8017374: 69db ldr r3, [r3, #28] 8017376: 2b00 cmp r3, #0 8017378: d003 beq.n 8017382 801737a: 687b ldr r3, [r7, #4] 801737c: 69db ldr r3, [r3, #28] 801737e: 6878 ldr r0, [r7, #4] 8017380: 4798 blx r3 args.link_changed.state = 0; netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args); } #endif } } 8017382: 3708 adds r7, #8 8017384: 46bd mov sp, r7 8017386: bd80 pop {r7, pc} 8017388: 08024308 .word 0x08024308 801738c: 0802464c .word 0x0802464c 8017390: 08024358 .word 0x08024358 08017394 : * @ingroup netif * Set callback to be called when link is brought up/down */ void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback) { 8017394: b480 push {r7} 8017396: b083 sub sp, #12 8017398: af00 add r7, sp, #0 801739a: 6078 str r0, [r7, #4] 801739c: 6039 str r1, [r7, #0] LWIP_ASSERT_CORE_LOCKED(); if (netif) { 801739e: 687b ldr r3, [r7, #4] 80173a0: 2b00 cmp r3, #0 80173a2: d002 beq.n 80173aa netif->link_callback = link_callback; 80173a4: 687b ldr r3, [r7, #4] 80173a6: 683a ldr r2, [r7, #0] 80173a8: 61da str r2, [r3, #28] } } 80173aa: bf00 nop 80173ac: 370c adds r7, #12 80173ae: 46bd mov sp, r7 80173b0: f85d 7b04 ldr.w r7, [sp], #4 80173b4: 4770 bx lr 080173b6 : #if LWIP_IPV4 /** Dummy IPv4 output function for netifs not supporting IPv4 */ static err_t netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr) { 80173b6: b480 push {r7} 80173b8: b085 sub sp, #20 80173ba: af00 add r7, sp, #0 80173bc: 60f8 str r0, [r7, #12] 80173be: 60b9 str r1, [r7, #8] 80173c0: 607a str r2, [r7, #4] LWIP_UNUSED_ARG(netif); LWIP_UNUSED_ARG(p); LWIP_UNUSED_ARG(ipaddr); return ERR_IF; 80173c2: f06f 030b mvn.w r3, #11 } 80173c6: 4618 mov r0, r3 80173c8: 3714 adds r7, #20 80173ca: 46bd mov sp, r7 80173cc: f85d 7b04 ldr.w r7, [sp], #4 80173d0: 4770 bx lr ... 080173d4 : * * @param idx index of netif to find */ struct netif * netif_get_by_index(u8_t idx) { 80173d4: b480 push {r7} 80173d6: b085 sub sp, #20 80173d8: af00 add r7, sp, #0 80173da: 4603 mov r3, r0 80173dc: 71fb strb r3, [r7, #7] struct netif *netif; LWIP_ASSERT_CORE_LOCKED(); if (idx != NETIF_NO_INDEX) { 80173de: 79fb ldrb r3, [r7, #7] 80173e0: 2b00 cmp r3, #0 80173e2: d013 beq.n 801740c NETIF_FOREACH(netif) { 80173e4: 4b0d ldr r3, [pc, #52] ; (801741c ) 80173e6: 681b ldr r3, [r3, #0] 80173e8: 60fb str r3, [r7, #12] 80173ea: e00c b.n 8017406 if (idx == netif_get_index(netif)) { 80173ec: 68fb ldr r3, [r7, #12] 80173ee: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 80173f2: 3301 adds r3, #1 80173f4: b2db uxtb r3, r3 80173f6: 79fa ldrb r2, [r7, #7] 80173f8: 429a cmp r2, r3 80173fa: d101 bne.n 8017400 return netif; /* found! */ 80173fc: 68fb ldr r3, [r7, #12] 80173fe: e006 b.n 801740e NETIF_FOREACH(netif) { 8017400: 68fb ldr r3, [r7, #12] 8017402: 681b ldr r3, [r3, #0] 8017404: 60fb str r3, [r7, #12] 8017406: 68fb ldr r3, [r7, #12] 8017408: 2b00 cmp r3, #0 801740a: d1ef bne.n 80173ec } } } return NULL; 801740c: 2300 movs r3, #0 } 801740e: 4618 mov r0, r3 8017410: 3714 adds r7, #20 8017412: 46bd mov sp, r7 8017414: f85d 7b04 ldr.w r7, [sp], #4 8017418: 4770 bx lr 801741a: bf00 nop 801741c: 2401a474 .word 0x2401a474 08017420 : #if !NO_SYS static #endif /* !NO_SYS */ void pbuf_free_ooseq(void) { 8017420: b580 push {r7, lr} 8017422: b082 sub sp, #8 8017424: af00 add r7, sp, #0 struct tcp_pcb *pcb; SYS_ARCH_SET(pbuf_free_ooseq_pending, 0); 8017426: f00a f915 bl 8021654 801742a: 6038 str r0, [r7, #0] 801742c: 4b0d ldr r3, [pc, #52] ; (8017464 ) 801742e: 2200 movs r2, #0 8017430: 701a strb r2, [r3, #0] 8017432: 6838 ldr r0, [r7, #0] 8017434: f00a f91c bl 8021670 for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { 8017438: 4b0b ldr r3, [pc, #44] ; (8017468 ) 801743a: 681b ldr r3, [r3, #0] 801743c: 607b str r3, [r7, #4] 801743e: e00a b.n 8017456 if (pcb->ooseq != NULL) { 8017440: 687b ldr r3, [r7, #4] 8017442: 6f5b ldr r3, [r3, #116] ; 0x74 8017444: 2b00 cmp r3, #0 8017446: d003 beq.n 8017450 /** Free the ooseq pbufs of one PCB only */ LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n")); tcp_free_ooseq(pcb); 8017448: 6878 ldr r0, [r7, #4] 801744a: f002 fc9f bl 8019d8c return; 801744e: e005 b.n 801745c for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { 8017450: 687b ldr r3, [r7, #4] 8017452: 68db ldr r3, [r3, #12] 8017454: 607b str r3, [r7, #4] 8017456: 687b ldr r3, [r7, #4] 8017458: 2b00 cmp r3, #0 801745a: d1f1 bne.n 8017440 } } } 801745c: 3708 adds r7, #8 801745e: 46bd mov sp, r7 8017460: bd80 pop {r7, pc} 8017462: bf00 nop 8017464: 2401a47d .word 0x2401a47d 8017468: 2401a48c .word 0x2401a48c 0801746c : /** * Just a callback function for tcpip_callback() that calls pbuf_free_ooseq(). */ static void pbuf_free_ooseq_callback(void *arg) { 801746c: b580 push {r7, lr} 801746e: b082 sub sp, #8 8017470: af00 add r7, sp, #0 8017472: 6078 str r0, [r7, #4] LWIP_UNUSED_ARG(arg); pbuf_free_ooseq(); 8017474: f7ff ffd4 bl 8017420 } 8017478: bf00 nop 801747a: 3708 adds r7, #8 801747c: 46bd mov sp, r7 801747e: bd80 pop {r7, pc} 08017480 : #endif /* !NO_SYS */ /** Queue a call to pbuf_free_ooseq if not already queued. */ static void pbuf_pool_is_empty(void) { 8017480: b580 push {r7, lr} 8017482: b082 sub sp, #8 8017484: af00 add r7, sp, #0 #ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL SYS_ARCH_SET(pbuf_free_ooseq_pending, 1); #else /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ u8_t queued; SYS_ARCH_DECL_PROTECT(old_level); SYS_ARCH_PROTECT(old_level); 8017486: f00a f8e5 bl 8021654 801748a: 6078 str r0, [r7, #4] queued = pbuf_free_ooseq_pending; 801748c: 4b0f ldr r3, [pc, #60] ; (80174cc ) 801748e: 781b ldrb r3, [r3, #0] 8017490: 70fb strb r3, [r7, #3] pbuf_free_ooseq_pending = 1; 8017492: 4b0e ldr r3, [pc, #56] ; (80174cc ) 8017494: 2201 movs r2, #1 8017496: 701a strb r2, [r3, #0] SYS_ARCH_UNPROTECT(old_level); 8017498: 6878 ldr r0, [r7, #4] 801749a: f00a f8e9 bl 8021670 if (!queued) { 801749e: 78fb ldrb r3, [r7, #3] 80174a0: 2b00 cmp r3, #0 80174a2: d10f bne.n 80174c4 /* queue a call to pbuf_free_ooseq if not already queued */ PBUF_POOL_FREE_OOSEQ_QUEUE_CALL(); 80174a4: 2100 movs r1, #0 80174a6: 480a ldr r0, [pc, #40] ; (80174d0 ) 80174a8: f7fe fcaa bl 8015e00 80174ac: 4603 mov r3, r0 80174ae: 2b00 cmp r3, #0 80174b0: d008 beq.n 80174c4 80174b2: f00a f8cf bl 8021654 80174b6: 6078 str r0, [r7, #4] 80174b8: 4b04 ldr r3, [pc, #16] ; (80174cc ) 80174ba: 2200 movs r2, #0 80174bc: 701a strb r2, [r3, #0] 80174be: 6878 ldr r0, [r7, #4] 80174c0: f00a f8d6 bl 8021670 } #endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ } 80174c4: bf00 nop 80174c6: 3708 adds r7, #8 80174c8: 46bd mov sp, r7 80174ca: bd80 pop {r7, pc} 80174cc: 2401a47d .word 0x2401a47d 80174d0: 0801746d .word 0x0801746d 080174d4 : #endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */ /* Initialize members of struct pbuf after allocation */ static void pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags) { 80174d4: b480 push {r7} 80174d6: b085 sub sp, #20 80174d8: af00 add r7, sp, #0 80174da: 60f8 str r0, [r7, #12] 80174dc: 60b9 str r1, [r7, #8] 80174de: 4611 mov r1, r2 80174e0: 461a mov r2, r3 80174e2: 460b mov r3, r1 80174e4: 80fb strh r3, [r7, #6] 80174e6: 4613 mov r3, r2 80174e8: 80bb strh r3, [r7, #4] p->next = NULL; 80174ea: 68fb ldr r3, [r7, #12] 80174ec: 2200 movs r2, #0 80174ee: 601a str r2, [r3, #0] p->payload = payload; 80174f0: 68fb ldr r3, [r7, #12] 80174f2: 68ba ldr r2, [r7, #8] 80174f4: 605a str r2, [r3, #4] p->tot_len = tot_len; 80174f6: 68fb ldr r3, [r7, #12] 80174f8: 88fa ldrh r2, [r7, #6] 80174fa: 811a strh r2, [r3, #8] p->len = len; 80174fc: 68fb ldr r3, [r7, #12] 80174fe: 88ba ldrh r2, [r7, #4] 8017500: 815a strh r2, [r3, #10] p->type_internal = (u8_t)type; 8017502: 8b3b ldrh r3, [r7, #24] 8017504: b2da uxtb r2, r3 8017506: 68fb ldr r3, [r7, #12] 8017508: 731a strb r2, [r3, #12] p->flags = flags; 801750a: 68fb ldr r3, [r7, #12] 801750c: 7f3a ldrb r2, [r7, #28] 801750e: 735a strb r2, [r3, #13] p->ref = 1; 8017510: 68fb ldr r3, [r7, #12] 8017512: 2201 movs r2, #1 8017514: 739a strb r2, [r3, #14] p->if_idx = NETIF_NO_INDEX; 8017516: 68fb ldr r3, [r7, #12] 8017518: 2200 movs r2, #0 801751a: 73da strb r2, [r3, #15] } 801751c: bf00 nop 801751e: 3714 adds r7, #20 8017520: 46bd mov sp, r7 8017522: f85d 7b04 ldr.w r7, [sp], #4 8017526: 4770 bx lr 08017528 : * @return the allocated pbuf. If multiple pbufs where allocated, this * is the first pbuf of a pbuf chain. */ struct pbuf * pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type) { 8017528: b580 push {r7, lr} 801752a: b08c sub sp, #48 ; 0x30 801752c: af02 add r7, sp, #8 801752e: 4603 mov r3, r0 8017530: 71fb strb r3, [r7, #7] 8017532: 460b mov r3, r1 8017534: 80bb strh r3, [r7, #4] 8017536: 4613 mov r3, r2 8017538: 807b strh r3, [r7, #2] struct pbuf *p; u16_t offset = (u16_t)layer; 801753a: 79fb ldrb r3, [r7, #7] 801753c: 847b strh r3, [r7, #34] ; 0x22 LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length)); switch (type) { 801753e: 887b ldrh r3, [r7, #2] 8017540: f5b3 7f20 cmp.w r3, #640 ; 0x280 8017544: f000 8082 beq.w 801764c 8017548: f5b3 7f20 cmp.w r3, #640 ; 0x280 801754c: f300 80ca bgt.w 80176e4 8017550: f5b3 7fc1 cmp.w r3, #386 ; 0x182 8017554: d010 beq.n 8017578 8017556: f5b3 7fc1 cmp.w r3, #386 ; 0x182 801755a: f300 80c3 bgt.w 80176e4 801755e: 2b01 cmp r3, #1 8017560: d002 beq.n 8017568 8017562: 2b41 cmp r3, #65 ; 0x41 8017564: f040 80be bne.w 80176e4 case PBUF_REF: /* fall through */ case PBUF_ROM: p = pbuf_alloc_reference(NULL, length, type); 8017568: 887a ldrh r2, [r7, #2] 801756a: 88bb ldrh r3, [r7, #4] 801756c: 4619 mov r1, r3 801756e: 2000 movs r0, #0 8017570: f000 f8d4 bl 801771c 8017574: 6278 str r0, [r7, #36] ; 0x24 break; 8017576: e0bf b.n 80176f8 case PBUF_POOL: { struct pbuf *q, *last; u16_t rem_len; /* remaining length */ p = NULL; 8017578: 2300 movs r3, #0 801757a: 627b str r3, [r7, #36] ; 0x24 last = NULL; 801757c: 2300 movs r3, #0 801757e: 61fb str r3, [r7, #28] rem_len = length; 8017580: 88bb ldrh r3, [r7, #4] 8017582: 837b strh r3, [r7, #26] do { u16_t qlen; q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL); 8017584: 200c movs r0, #12 8017586: f7ff faa3 bl 8016ad0 801758a: 6138 str r0, [r7, #16] if (q == NULL) { 801758c: 693b ldr r3, [r7, #16] 801758e: 2b00 cmp r3, #0 8017590: d109 bne.n 80175a6 PBUF_POOL_IS_EMPTY(); 8017592: f7ff ff75 bl 8017480 /* free chain so far allocated */ if (p) { 8017596: 6a7b ldr r3, [r7, #36] ; 0x24 8017598: 2b00 cmp r3, #0 801759a: d002 beq.n 80175a2 pbuf_free(p); 801759c: 6a78 ldr r0, [r7, #36] ; 0x24 801759e: f000 faab bl 8017af8 } /* bail out unsuccessfully */ return NULL; 80175a2: 2300 movs r3, #0 80175a4: e0a9 b.n 80176fa } qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset))); 80175a6: 8c7b ldrh r3, [r7, #34] ; 0x22 80175a8: 3303 adds r3, #3 80175aa: b29b uxth r3, r3 80175ac: f023 0303 bic.w r3, r3, #3 80175b0: b29a uxth r2, r3 80175b2: f240 53ec movw r3, #1516 ; 0x5ec 80175b6: 1a9b subs r3, r3, r2 80175b8: b29b uxth r3, r3 80175ba: 8b7a ldrh r2, [r7, #26] 80175bc: 4293 cmp r3, r2 80175be: bf28 it cs 80175c0: 4613 movcs r3, r2 80175c2: 81fb strh r3, [r7, #14] pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)), 80175c4: 8c7b ldrh r3, [r7, #34] ; 0x22 80175c6: 3310 adds r3, #16 80175c8: 693a ldr r2, [r7, #16] 80175ca: 4413 add r3, r2 80175cc: 3303 adds r3, #3 80175ce: f023 0303 bic.w r3, r3, #3 80175d2: 4618 mov r0, r3 80175d4: 89f9 ldrh r1, [r7, #14] 80175d6: 8b7a ldrh r2, [r7, #26] 80175d8: 2300 movs r3, #0 80175da: 9301 str r3, [sp, #4] 80175dc: 887b ldrh r3, [r7, #2] 80175de: 9300 str r3, [sp, #0] 80175e0: 460b mov r3, r1 80175e2: 4601 mov r1, r0 80175e4: 6938 ldr r0, [r7, #16] 80175e6: f7ff ff75 bl 80174d4 rem_len, qlen, type, 0); LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", 80175ea: 693b ldr r3, [r7, #16] 80175ec: 685b ldr r3, [r3, #4] 80175ee: f003 0303 and.w r3, r3, #3 80175f2: 2b00 cmp r3, #0 80175f4: d006 beq.n 8017604 80175f6: 4b43 ldr r3, [pc, #268] ; (8017704 ) 80175f8: f44f 7280 mov.w r2, #256 ; 0x100 80175fc: 4942 ldr r1, [pc, #264] ; (8017708 ) 80175fe: 4843 ldr r0, [pc, #268] ; (801770c ) 8017600: f00a f9c2 bl 8021988 ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT", 8017604: 8c7b ldrh r3, [r7, #34] ; 0x22 8017606: 3303 adds r3, #3 8017608: f023 0303 bic.w r3, r3, #3 801760c: f240 52ec movw r2, #1516 ; 0x5ec 8017610: 4293 cmp r3, r2 8017612: d106 bne.n 8017622 8017614: 4b3b ldr r3, [pc, #236] ; (8017704 ) 8017616: f44f 7281 mov.w r2, #258 ; 0x102 801761a: 493d ldr r1, [pc, #244] ; (8017710 ) 801761c: 483b ldr r0, [pc, #236] ; (801770c ) 801761e: f00a f9b3 bl 8021988 (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 ); if (p == NULL) { 8017622: 6a7b ldr r3, [r7, #36] ; 0x24 8017624: 2b00 cmp r3, #0 8017626: d102 bne.n 801762e /* allocated head of pbuf chain (into p) */ p = q; 8017628: 693b ldr r3, [r7, #16] 801762a: 627b str r3, [r7, #36] ; 0x24 801762c: e002 b.n 8017634 } else { /* make previous pbuf point to this pbuf */ last->next = q; 801762e: 69fb ldr r3, [r7, #28] 8017630: 693a ldr r2, [r7, #16] 8017632: 601a str r2, [r3, #0] } last = q; 8017634: 693b ldr r3, [r7, #16] 8017636: 61fb str r3, [r7, #28] rem_len = (u16_t)(rem_len - qlen); 8017638: 8b7a ldrh r2, [r7, #26] 801763a: 89fb ldrh r3, [r7, #14] 801763c: 1ad3 subs r3, r2, r3 801763e: 837b strh r3, [r7, #26] offset = 0; 8017640: 2300 movs r3, #0 8017642: 847b strh r3, [r7, #34] ; 0x22 } while (rem_len > 0); 8017644: 8b7b ldrh r3, [r7, #26] 8017646: 2b00 cmp r3, #0 8017648: d19c bne.n 8017584 break; 801764a: e055 b.n 80176f8 } case PBUF_RAM: { u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length)); 801764c: 8c7b ldrh r3, [r7, #34] ; 0x22 801764e: 3303 adds r3, #3 8017650: b29b uxth r3, r3 8017652: f023 0303 bic.w r3, r3, #3 8017656: b29a uxth r2, r3 8017658: 88bb ldrh r3, [r7, #4] 801765a: 3303 adds r3, #3 801765c: b29b uxth r3, r3 801765e: f023 0303 bic.w r3, r3, #3 8017662: b29b uxth r3, r3 8017664: 4413 add r3, r2 8017666: 833b strh r3, [r7, #24] mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len); 8017668: 8b3b ldrh r3, [r7, #24] 801766a: 3310 adds r3, #16 801766c: 82fb strh r3, [r7, #22] /* bug #50040: Check for integer overflow when calculating alloc_len */ if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) || 801766e: 8b3a ldrh r2, [r7, #24] 8017670: 88bb ldrh r3, [r7, #4] 8017672: 3303 adds r3, #3 8017674: f023 0303 bic.w r3, r3, #3 8017678: 429a cmp r2, r3 801767a: d306 bcc.n 801768a (alloc_len < LWIP_MEM_ALIGN_SIZE(length))) { 801767c: 8afa ldrh r2, [r7, #22] 801767e: 88bb ldrh r3, [r7, #4] 8017680: 3303 adds r3, #3 8017682: f023 0303 bic.w r3, r3, #3 if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) || 8017686: 429a cmp r2, r3 8017688: d201 bcs.n 801768e return NULL; 801768a: 2300 movs r3, #0 801768c: e035 b.n 80176fa } /* If pbuf is to be allocated in RAM, allocate memory for it. */ p = (struct pbuf *)mem_malloc(alloc_len); 801768e: 8afb ldrh r3, [r7, #22] 8017690: 4618 mov r0, r3 8017692: f7ff f865 bl 8016760 8017696: 6278 str r0, [r7, #36] ; 0x24 if (p == NULL) { 8017698: 6a7b ldr r3, [r7, #36] ; 0x24 801769a: 2b00 cmp r3, #0 801769c: d101 bne.n 80176a2 return NULL; 801769e: 2300 movs r3, #0 80176a0: e02b b.n 80176fa } pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)), 80176a2: 8c7b ldrh r3, [r7, #34] ; 0x22 80176a4: 3310 adds r3, #16 80176a6: 6a7a ldr r2, [r7, #36] ; 0x24 80176a8: 4413 add r3, r2 80176aa: 3303 adds r3, #3 80176ac: f023 0303 bic.w r3, r3, #3 80176b0: 4618 mov r0, r3 80176b2: 88b9 ldrh r1, [r7, #4] 80176b4: 88ba ldrh r2, [r7, #4] 80176b6: 2300 movs r3, #0 80176b8: 9301 str r3, [sp, #4] 80176ba: 887b ldrh r3, [r7, #2] 80176bc: 9300 str r3, [sp, #0] 80176be: 460b mov r3, r1 80176c0: 4601 mov r1, r0 80176c2: 6a78 ldr r0, [r7, #36] ; 0x24 80176c4: f7ff ff06 bl 80174d4 length, length, type, 0); LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", 80176c8: 6a7b ldr r3, [r7, #36] ; 0x24 80176ca: 685b ldr r3, [r3, #4] 80176cc: f003 0303 and.w r3, r3, #3 80176d0: 2b00 cmp r3, #0 80176d2: d010 beq.n 80176f6 80176d4: 4b0b ldr r3, [pc, #44] ; (8017704 ) 80176d6: f44f 7291 mov.w r2, #290 ; 0x122 80176da: 490e ldr r1, [pc, #56] ; (8017714 ) 80176dc: 480b ldr r0, [pc, #44] ; (801770c ) 80176de: f00a f953 bl 8021988 ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); break; 80176e2: e008 b.n 80176f6 } default: LWIP_ASSERT("pbuf_alloc: erroneous type", 0); 80176e4: 4b07 ldr r3, [pc, #28] ; (8017704 ) 80176e6: f240 1227 movw r2, #295 ; 0x127 80176ea: 490b ldr r1, [pc, #44] ; (8017718 ) 80176ec: 4807 ldr r0, [pc, #28] ; (801770c ) 80176ee: f00a f94b bl 8021988 return NULL; 80176f2: 2300 movs r3, #0 80176f4: e001 b.n 80176fa break; 80176f6: bf00 nop } LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); return p; 80176f8: 6a7b ldr r3, [r7, #36] ; 0x24 } 80176fa: 4618 mov r0, r3 80176fc: 3728 adds r7, #40 ; 0x28 80176fe: 46bd mov sp, r7 8017700: bd80 pop {r7, pc} 8017702: bf00 nop 8017704: 080246a8 .word 0x080246a8 8017708: 080246d8 .word 0x080246d8 801770c: 08024708 .word 0x08024708 8017710: 08024730 .word 0x08024730 8017714: 08024764 .word 0x08024764 8017718: 08024790 .word 0x08024790 0801771c : * * @return the allocated pbuf. */ struct pbuf * pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type) { 801771c: b580 push {r7, lr} 801771e: b086 sub sp, #24 8017720: af02 add r7, sp, #8 8017722: 6078 str r0, [r7, #4] 8017724: 460b mov r3, r1 8017726: 807b strh r3, [r7, #2] 8017728: 4613 mov r3, r2 801772a: 803b strh r3, [r7, #0] struct pbuf *p; LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM)); 801772c: 883b ldrh r3, [r7, #0] 801772e: 2b41 cmp r3, #65 ; 0x41 8017730: d009 beq.n 8017746 8017732: 883b ldrh r3, [r7, #0] 8017734: 2b01 cmp r3, #1 8017736: d006 beq.n 8017746 8017738: 4b0f ldr r3, [pc, #60] ; (8017778 ) 801773a: f44f 72a5 mov.w r2, #330 ; 0x14a 801773e: 490f ldr r1, [pc, #60] ; (801777c ) 8017740: 480f ldr r0, [pc, #60] ; (8017780 ) 8017742: f00a f921 bl 8021988 /* only allocate memory for the pbuf structure */ p = (struct pbuf *)memp_malloc(MEMP_PBUF); 8017746: 200b movs r0, #11 8017748: f7ff f9c2 bl 8016ad0 801774c: 60f8 str r0, [r7, #12] if (p == NULL) { 801774e: 68fb ldr r3, [r7, #12] 8017750: 2b00 cmp r3, #0 8017752: d101 bne.n 8017758 LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n", (type == PBUF_ROM) ? "ROM" : "REF")); return NULL; 8017754: 2300 movs r3, #0 8017756: e00b b.n 8017770 } pbuf_init_alloced_pbuf(p, payload, length, length, type, 0); 8017758: 8879 ldrh r1, [r7, #2] 801775a: 887a ldrh r2, [r7, #2] 801775c: 2300 movs r3, #0 801775e: 9301 str r3, [sp, #4] 8017760: 883b ldrh r3, [r7, #0] 8017762: 9300 str r3, [sp, #0] 8017764: 460b mov r3, r1 8017766: 6879 ldr r1, [r7, #4] 8017768: 68f8 ldr r0, [r7, #12] 801776a: f7ff feb3 bl 80174d4 return p; 801776e: 68fb ldr r3, [r7, #12] } 8017770: 4618 mov r0, r3 8017772: 3710 adds r7, #16 8017774: 46bd mov sp, r7 8017776: bd80 pop {r7, pc} 8017778: 080246a8 .word 0x080246a8 801777c: 080247ac .word 0x080247ac 8017780: 08024708 .word 0x08024708 08017784 : * big enough to hold 'length' plus the header size */ struct pbuf * pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p, void *payload_mem, u16_t payload_mem_len) { 8017784: b580 push {r7, lr} 8017786: b088 sub sp, #32 8017788: af02 add r7, sp, #8 801778a: 607b str r3, [r7, #4] 801778c: 4603 mov r3, r0 801778e: 73fb strb r3, [r7, #15] 8017790: 460b mov r3, r1 8017792: 81bb strh r3, [r7, #12] 8017794: 4613 mov r3, r2 8017796: 817b strh r3, [r7, #10] u16_t offset = (u16_t)l; 8017798: 7bfb ldrb r3, [r7, #15] 801779a: 827b strh r3, [r7, #18] void *payload; LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length)); if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) { 801779c: 8a7b ldrh r3, [r7, #18] 801779e: 3303 adds r3, #3 80177a0: f023 0203 bic.w r2, r3, #3 80177a4: 89bb ldrh r3, [r7, #12] 80177a6: 441a add r2, r3 80177a8: 8cbb ldrh r3, [r7, #36] ; 0x24 80177aa: 429a cmp r2, r3 80177ac: d901 bls.n 80177b2 LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length)); return NULL; 80177ae: 2300 movs r3, #0 80177b0: e018 b.n 80177e4 } if (payload_mem != NULL) { 80177b2: 6a3b ldr r3, [r7, #32] 80177b4: 2b00 cmp r3, #0 80177b6: d007 beq.n 80177c8 payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset); 80177b8: 8a7b ldrh r3, [r7, #18] 80177ba: 3303 adds r3, #3 80177bc: f023 0303 bic.w r3, r3, #3 80177c0: 6a3a ldr r2, [r7, #32] 80177c2: 4413 add r3, r2 80177c4: 617b str r3, [r7, #20] 80177c6: e001 b.n 80177cc } else { payload = NULL; 80177c8: 2300 movs r3, #0 80177ca: 617b str r3, [r7, #20] } pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM); 80177cc: 6878 ldr r0, [r7, #4] 80177ce: 89b9 ldrh r1, [r7, #12] 80177d0: 89ba ldrh r2, [r7, #12] 80177d2: 2302 movs r3, #2 80177d4: 9301 str r3, [sp, #4] 80177d6: 897b ldrh r3, [r7, #10] 80177d8: 9300 str r3, [sp, #0] 80177da: 460b mov r3, r1 80177dc: 6979 ldr r1, [r7, #20] 80177de: f7ff fe79 bl 80174d4 return &p->pbuf; 80177e2: 687b ldr r3, [r7, #4] } 80177e4: 4618 mov r0, r3 80177e6: 3718 adds r7, #24 80177e8: 46bd mov sp, r7 80177ea: bd80 pop {r7, pc} 080177ec : * * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain). */ void pbuf_realloc(struct pbuf *p, u16_t new_len) { 80177ec: b580 push {r7, lr} 80177ee: b084 sub sp, #16 80177f0: af00 add r7, sp, #0 80177f2: 6078 str r0, [r7, #4] 80177f4: 460b mov r3, r1 80177f6: 807b strh r3, [r7, #2] struct pbuf *q; u16_t rem_len; /* remaining length */ u16_t shrink; LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL); 80177f8: 687b ldr r3, [r7, #4] 80177fa: 2b00 cmp r3, #0 80177fc: d106 bne.n 801780c 80177fe: 4b3a ldr r3, [pc, #232] ; (80178e8 ) 8017800: f44f 72cc mov.w r2, #408 ; 0x198 8017804: 4939 ldr r1, [pc, #228] ; (80178ec ) 8017806: 483a ldr r0, [pc, #232] ; (80178f0 ) 8017808: f00a f8be bl 8021988 /* desired length larger than current length? */ if (new_len >= p->tot_len) { 801780c: 687b ldr r3, [r7, #4] 801780e: 891b ldrh r3, [r3, #8] 8017810: 887a ldrh r2, [r7, #2] 8017812: 429a cmp r2, r3 8017814: d263 bcs.n 80178de return; } /* the pbuf chain grows by (new_len - p->tot_len) bytes * (which may be negative in case of shrinking) */ shrink = (u16_t)(p->tot_len - new_len); 8017816: 687b ldr r3, [r7, #4] 8017818: 891a ldrh r2, [r3, #8] 801781a: 887b ldrh r3, [r7, #2] 801781c: 1ad3 subs r3, r2, r3 801781e: 813b strh r3, [r7, #8] /* first, step over any pbufs that should remain in the chain */ rem_len = new_len; 8017820: 887b ldrh r3, [r7, #2] 8017822: 817b strh r3, [r7, #10] q = p; 8017824: 687b ldr r3, [r7, #4] 8017826: 60fb str r3, [r7, #12] /* should this pbuf be kept? */ while (rem_len > q->len) { 8017828: e018 b.n 801785c /* decrease remaining length by pbuf length */ rem_len = (u16_t)(rem_len - q->len); 801782a: 68fb ldr r3, [r7, #12] 801782c: 895b ldrh r3, [r3, #10] 801782e: 897a ldrh r2, [r7, #10] 8017830: 1ad3 subs r3, r2, r3 8017832: 817b strh r3, [r7, #10] /* decrease total length indicator */ q->tot_len = (u16_t)(q->tot_len - shrink); 8017834: 68fb ldr r3, [r7, #12] 8017836: 891a ldrh r2, [r3, #8] 8017838: 893b ldrh r3, [r7, #8] 801783a: 1ad3 subs r3, r2, r3 801783c: b29a uxth r2, r3 801783e: 68fb ldr r3, [r7, #12] 8017840: 811a strh r2, [r3, #8] /* proceed to next pbuf in chain */ q = q->next; 8017842: 68fb ldr r3, [r7, #12] 8017844: 681b ldr r3, [r3, #0] 8017846: 60fb str r3, [r7, #12] LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL); 8017848: 68fb ldr r3, [r7, #12] 801784a: 2b00 cmp r3, #0 801784c: d106 bne.n 801785c 801784e: 4b26 ldr r3, [pc, #152] ; (80178e8 ) 8017850: f240 12af movw r2, #431 ; 0x1af 8017854: 4927 ldr r1, [pc, #156] ; (80178f4 ) 8017856: 4826 ldr r0, [pc, #152] ; (80178f0 ) 8017858: f00a f896 bl 8021988 while (rem_len > q->len) { 801785c: 68fb ldr r3, [r7, #12] 801785e: 895b ldrh r3, [r3, #10] 8017860: 897a ldrh r2, [r7, #10] 8017862: 429a cmp r2, r3 8017864: d8e1 bhi.n 801782a /* we have now reached the new last pbuf (in q) */ /* rem_len == desired length for pbuf q */ /* shrink allocated memory for PBUF_RAM */ /* (other types merely adjust their length fields */ if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len) 8017866: 68fb ldr r3, [r7, #12] 8017868: 7b1b ldrb r3, [r3, #12] 801786a: f003 030f and.w r3, r3, #15 801786e: 2b00 cmp r3, #0 8017870: d121 bne.n 80178b6 8017872: 68fb ldr r3, [r7, #12] 8017874: 895b ldrh r3, [r3, #10] 8017876: 897a ldrh r2, [r7, #10] 8017878: 429a cmp r2, r3 801787a: d01c beq.n 80178b6 #if LWIP_SUPPORT_CUSTOM_PBUF && ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0) 801787c: 68fb ldr r3, [r7, #12] 801787e: 7b5b ldrb r3, [r3, #13] 8017880: f003 0302 and.w r3, r3, #2 8017884: 2b00 cmp r3, #0 8017886: d116 bne.n 80178b6 #endif /* LWIP_SUPPORT_CUSTOM_PBUF */ ) { /* reallocate and adjust the length of the pbuf that will be split */ q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len)); 8017888: 68fb ldr r3, [r7, #12] 801788a: 685a ldr r2, [r3, #4] 801788c: 68fb ldr r3, [r7, #12] 801788e: 1ad3 subs r3, r2, r3 8017890: b29a uxth r2, r3 8017892: 897b ldrh r3, [r7, #10] 8017894: 4413 add r3, r2 8017896: b29b uxth r3, r3 8017898: 4619 mov r1, r3 801789a: 68f8 ldr r0, [r7, #12] 801789c: f7fe fe4c bl 8016538 80178a0: 60f8 str r0, [r7, #12] LWIP_ASSERT("mem_trim returned q == NULL", q != NULL); 80178a2: 68fb ldr r3, [r7, #12] 80178a4: 2b00 cmp r3, #0 80178a6: d106 bne.n 80178b6 80178a8: 4b0f ldr r3, [pc, #60] ; (80178e8 ) 80178aa: f240 12bd movw r2, #445 ; 0x1bd 80178ae: 4912 ldr r1, [pc, #72] ; (80178f8 ) 80178b0: 480f ldr r0, [pc, #60] ; (80178f0 ) 80178b2: f00a f869 bl 8021988 } /* adjust length fields for new last pbuf */ q->len = rem_len; 80178b6: 68fb ldr r3, [r7, #12] 80178b8: 897a ldrh r2, [r7, #10] 80178ba: 815a strh r2, [r3, #10] q->tot_len = q->len; 80178bc: 68fb ldr r3, [r7, #12] 80178be: 895a ldrh r2, [r3, #10] 80178c0: 68fb ldr r3, [r7, #12] 80178c2: 811a strh r2, [r3, #8] /* any remaining pbufs in chain? */ if (q->next != NULL) { 80178c4: 68fb ldr r3, [r7, #12] 80178c6: 681b ldr r3, [r3, #0] 80178c8: 2b00 cmp r3, #0 80178ca: d004 beq.n 80178d6 /* free remaining pbufs in chain */ pbuf_free(q->next); 80178cc: 68fb ldr r3, [r7, #12] 80178ce: 681b ldr r3, [r3, #0] 80178d0: 4618 mov r0, r3 80178d2: f000 f911 bl 8017af8 } /* q is last packet in chain */ q->next = NULL; 80178d6: 68fb ldr r3, [r7, #12] 80178d8: 2200 movs r2, #0 80178da: 601a str r2, [r3, #0] 80178dc: e000 b.n 80178e0 return; 80178de: bf00 nop } 80178e0: 3710 adds r7, #16 80178e2: 46bd mov sp, r7 80178e4: bd80 pop {r7, pc} 80178e6: bf00 nop 80178e8: 080246a8 .word 0x080246a8 80178ec: 080247c0 .word 0x080247c0 80178f0: 08024708 .word 0x08024708 80178f4: 080247d8 .word 0x080247d8 80178f8: 080247f0 .word 0x080247f0 080178fc : * @return non-zero on failure, zero on success. * */ static u8_t pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force) { 80178fc: b580 push {r7, lr} 80178fe: b086 sub sp, #24 8017900: af00 add r7, sp, #0 8017902: 60f8 str r0, [r7, #12] 8017904: 60b9 str r1, [r7, #8] 8017906: 4613 mov r3, r2 8017908: 71fb strb r3, [r7, #7] u16_t type_internal; void *payload; u16_t increment_magnitude; LWIP_ASSERT("p != NULL", p != NULL); 801790a: 68fb ldr r3, [r7, #12] 801790c: 2b00 cmp r3, #0 801790e: d106 bne.n 801791e 8017910: 4b2b ldr r3, [pc, #172] ; (80179c0 ) 8017912: f240 12df movw r2, #479 ; 0x1df 8017916: 492b ldr r1, [pc, #172] ; (80179c4 ) 8017918: 482b ldr r0, [pc, #172] ; (80179c8 ) 801791a: f00a f835 bl 8021988 if ((p == NULL) || (header_size_increment > 0xFFFF)) { 801791e: 68fb ldr r3, [r7, #12] 8017920: 2b00 cmp r3, #0 8017922: d003 beq.n 801792c 8017924: 68bb ldr r3, [r7, #8] 8017926: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 801792a: d301 bcc.n 8017930 return 1; 801792c: 2301 movs r3, #1 801792e: e043 b.n 80179b8 } if (header_size_increment == 0) { 8017930: 68bb ldr r3, [r7, #8] 8017932: 2b00 cmp r3, #0 8017934: d101 bne.n 801793a return 0; 8017936: 2300 movs r3, #0 8017938: e03e b.n 80179b8 } increment_magnitude = (u16_t)header_size_increment; 801793a: 68bb ldr r3, [r7, #8] 801793c: 827b strh r3, [r7, #18] /* Do not allow tot_len to wrap as a result. */ if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) { 801793e: 68fb ldr r3, [r7, #12] 8017940: 891a ldrh r2, [r3, #8] 8017942: 8a7b ldrh r3, [r7, #18] 8017944: 4413 add r3, r2 8017946: b29b uxth r3, r3 8017948: 8a7a ldrh r2, [r7, #18] 801794a: 429a cmp r2, r3 801794c: d901 bls.n 8017952 return 1; 801794e: 2301 movs r3, #1 8017950: e032 b.n 80179b8 } type_internal = p->type_internal; 8017952: 68fb ldr r3, [r7, #12] 8017954: 7b1b ldrb r3, [r3, #12] 8017956: 823b strh r3, [r7, #16] /* pbuf types containing payloads? */ if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) { 8017958: 8a3b ldrh r3, [r7, #16] 801795a: f003 0380 and.w r3, r3, #128 ; 0x80 801795e: 2b00 cmp r3, #0 8017960: d00c beq.n 801797c /* set new payload pointer */ payload = (u8_t *)p->payload - header_size_increment; 8017962: 68fb ldr r3, [r7, #12] 8017964: 685a ldr r2, [r3, #4] 8017966: 68bb ldr r3, [r7, #8] 8017968: 425b negs r3, r3 801796a: 4413 add r3, r2 801796c: 617b str r3, [r7, #20] /* boundary check fails? */ if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) { 801796e: 68fb ldr r3, [r7, #12] 8017970: 3310 adds r3, #16 8017972: 697a ldr r2, [r7, #20] 8017974: 429a cmp r2, r3 8017976: d20d bcs.n 8017994 LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n", (void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF))); /* bail out unsuccessfully */ return 1; 8017978: 2301 movs r3, #1 801797a: e01d b.n 80179b8 } /* pbuf types referring to external payloads? */ } else { /* hide a header in the payload? */ if (force) { 801797c: 79fb ldrb r3, [r7, #7] 801797e: 2b00 cmp r3, #0 8017980: d006 beq.n 8017990 payload = (u8_t *)p->payload - header_size_increment; 8017982: 68fb ldr r3, [r7, #12] 8017984: 685a ldr r2, [r3, #4] 8017986: 68bb ldr r3, [r7, #8] 8017988: 425b negs r3, r3 801798a: 4413 add r3, r2 801798c: 617b str r3, [r7, #20] 801798e: e001 b.n 8017994 } else { /* cannot expand payload to front (yet!) * bail out unsuccessfully */ return 1; 8017990: 2301 movs r3, #1 8017992: e011 b.n 80179b8 } LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n", (void *)p->payload, (void *)payload, increment_magnitude)); /* modify pbuf fields */ p->payload = payload; 8017994: 68fb ldr r3, [r7, #12] 8017996: 697a ldr r2, [r7, #20] 8017998: 605a str r2, [r3, #4] p->len = (u16_t)(p->len + increment_magnitude); 801799a: 68fb ldr r3, [r7, #12] 801799c: 895a ldrh r2, [r3, #10] 801799e: 8a7b ldrh r3, [r7, #18] 80179a0: 4413 add r3, r2 80179a2: b29a uxth r2, r3 80179a4: 68fb ldr r3, [r7, #12] 80179a6: 815a strh r2, [r3, #10] p->tot_len = (u16_t)(p->tot_len + increment_magnitude); 80179a8: 68fb ldr r3, [r7, #12] 80179aa: 891a ldrh r2, [r3, #8] 80179ac: 8a7b ldrh r3, [r7, #18] 80179ae: 4413 add r3, r2 80179b0: b29a uxth r2, r3 80179b2: 68fb ldr r3, [r7, #12] 80179b4: 811a strh r2, [r3, #8] return 0; 80179b6: 2300 movs r3, #0 } 80179b8: 4618 mov r0, r3 80179ba: 3718 adds r7, #24 80179bc: 46bd mov sp, r7 80179be: bd80 pop {r7, pc} 80179c0: 080246a8 .word 0x080246a8 80179c4: 0802480c .word 0x0802480c 80179c8: 08024708 .word 0x08024708 080179cc : * @return non-zero on failure, zero on success. * */ u8_t pbuf_add_header(struct pbuf *p, size_t header_size_increment) { 80179cc: b580 push {r7, lr} 80179ce: b082 sub sp, #8 80179d0: af00 add r7, sp, #0 80179d2: 6078 str r0, [r7, #4] 80179d4: 6039 str r1, [r7, #0] return pbuf_add_header_impl(p, header_size_increment, 0); 80179d6: 2200 movs r2, #0 80179d8: 6839 ldr r1, [r7, #0] 80179da: 6878 ldr r0, [r7, #4] 80179dc: f7ff ff8e bl 80178fc 80179e0: 4603 mov r3, r0 } 80179e2: 4618 mov r0, r3 80179e4: 3708 adds r7, #8 80179e6: 46bd mov sp, r7 80179e8: bd80 pop {r7, pc} ... 080179ec : * @return non-zero on failure, zero on success. * */ u8_t pbuf_remove_header(struct pbuf *p, size_t header_size_decrement) { 80179ec: b580 push {r7, lr} 80179ee: b084 sub sp, #16 80179f0: af00 add r7, sp, #0 80179f2: 6078 str r0, [r7, #4] 80179f4: 6039 str r1, [r7, #0] void *payload; u16_t increment_magnitude; LWIP_ASSERT("p != NULL", p != NULL); 80179f6: 687b ldr r3, [r7, #4] 80179f8: 2b00 cmp r3, #0 80179fa: d106 bne.n 8017a0a 80179fc: 4b20 ldr r3, [pc, #128] ; (8017a80 ) 80179fe: f240 224b movw r2, #587 ; 0x24b 8017a02: 4920 ldr r1, [pc, #128] ; (8017a84 ) 8017a04: 4820 ldr r0, [pc, #128] ; (8017a88 ) 8017a06: f009 ffbf bl 8021988 if ((p == NULL) || (header_size_decrement > 0xFFFF)) { 8017a0a: 687b ldr r3, [r7, #4] 8017a0c: 2b00 cmp r3, #0 8017a0e: d003 beq.n 8017a18 8017a10: 683b ldr r3, [r7, #0] 8017a12: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8017a16: d301 bcc.n 8017a1c return 1; 8017a18: 2301 movs r3, #1 8017a1a: e02c b.n 8017a76 } if (header_size_decrement == 0) { 8017a1c: 683b ldr r3, [r7, #0] 8017a1e: 2b00 cmp r3, #0 8017a20: d101 bne.n 8017a26 return 0; 8017a22: 2300 movs r3, #0 8017a24: e027 b.n 8017a76 } increment_magnitude = (u16_t)header_size_decrement; 8017a26: 683b ldr r3, [r7, #0] 8017a28: 81fb strh r3, [r7, #14] /* Check that we aren't going to move off the end of the pbuf */ LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;); 8017a2a: 687b ldr r3, [r7, #4] 8017a2c: 895b ldrh r3, [r3, #10] 8017a2e: 89fa ldrh r2, [r7, #14] 8017a30: 429a cmp r2, r3 8017a32: d908 bls.n 8017a46 8017a34: 4b12 ldr r3, [pc, #72] ; (8017a80 ) 8017a36: f240 2255 movw r2, #597 ; 0x255 8017a3a: 4914 ldr r1, [pc, #80] ; (8017a8c ) 8017a3c: 4812 ldr r0, [pc, #72] ; (8017a88 ) 8017a3e: f009 ffa3 bl 8021988 8017a42: 2301 movs r3, #1 8017a44: e017 b.n 8017a76 /* remember current payload pointer */ payload = p->payload; 8017a46: 687b ldr r3, [r7, #4] 8017a48: 685b ldr r3, [r3, #4] 8017a4a: 60bb str r3, [r7, #8] LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */ /* increase payload pointer (guarded by length check above) */ p->payload = (u8_t *)p->payload + header_size_decrement; 8017a4c: 687b ldr r3, [r7, #4] 8017a4e: 685a ldr r2, [r3, #4] 8017a50: 683b ldr r3, [r7, #0] 8017a52: 441a add r2, r3 8017a54: 687b ldr r3, [r7, #4] 8017a56: 605a str r2, [r3, #4] /* modify pbuf length fields */ p->len = (u16_t)(p->len - increment_magnitude); 8017a58: 687b ldr r3, [r7, #4] 8017a5a: 895a ldrh r2, [r3, #10] 8017a5c: 89fb ldrh r3, [r7, #14] 8017a5e: 1ad3 subs r3, r2, r3 8017a60: b29a uxth r2, r3 8017a62: 687b ldr r3, [r7, #4] 8017a64: 815a strh r2, [r3, #10] p->tot_len = (u16_t)(p->tot_len - increment_magnitude); 8017a66: 687b ldr r3, [r7, #4] 8017a68: 891a ldrh r2, [r3, #8] 8017a6a: 89fb ldrh r3, [r7, #14] 8017a6c: 1ad3 subs r3, r2, r3 8017a6e: b29a uxth r2, r3 8017a70: 687b ldr r3, [r7, #4] 8017a72: 811a strh r2, [r3, #8] LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n", (void *)payload, (void *)p->payload, increment_magnitude)); return 0; 8017a74: 2300 movs r3, #0 } 8017a76: 4618 mov r0, r3 8017a78: 3710 adds r7, #16 8017a7a: 46bd mov sp, r7 8017a7c: bd80 pop {r7, pc} 8017a7e: bf00 nop 8017a80: 080246a8 .word 0x080246a8 8017a84: 0802480c .word 0x0802480c 8017a88: 08024708 .word 0x08024708 8017a8c: 08024818 .word 0x08024818 08017a90 : static u8_t pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force) { 8017a90: b580 push {r7, lr} 8017a92: b082 sub sp, #8 8017a94: af00 add r7, sp, #0 8017a96: 6078 str r0, [r7, #4] 8017a98: 460b mov r3, r1 8017a9a: 807b strh r3, [r7, #2] 8017a9c: 4613 mov r3, r2 8017a9e: 707b strb r3, [r7, #1] if (header_size_increment < 0) { 8017aa0: f9b7 3002 ldrsh.w r3, [r7, #2] 8017aa4: 2b00 cmp r3, #0 8017aa6: da08 bge.n 8017aba return pbuf_remove_header(p, (size_t) - header_size_increment); 8017aa8: f9b7 3002 ldrsh.w r3, [r7, #2] 8017aac: 425b negs r3, r3 8017aae: 4619 mov r1, r3 8017ab0: 6878 ldr r0, [r7, #4] 8017ab2: f7ff ff9b bl 80179ec 8017ab6: 4603 mov r3, r0 8017ab8: e007 b.n 8017aca } else { return pbuf_add_header_impl(p, (size_t)header_size_increment, force); 8017aba: f9b7 3002 ldrsh.w r3, [r7, #2] 8017abe: 787a ldrb r2, [r7, #1] 8017ac0: 4619 mov r1, r3 8017ac2: 6878 ldr r0, [r7, #4] 8017ac4: f7ff ff1a bl 80178fc 8017ac8: 4603 mov r3, r0 } } 8017aca: 4618 mov r0, r3 8017acc: 3708 adds r7, #8 8017ace: 46bd mov sp, r7 8017ad0: bd80 pop {r7, pc} 08017ad2 : * Same as pbuf_header but does not check if 'header_size > 0' is allowed. * This is used internally only, to allow PBUF_REF for RX. */ u8_t pbuf_header_force(struct pbuf *p, s16_t header_size_increment) { 8017ad2: b580 push {r7, lr} 8017ad4: b082 sub sp, #8 8017ad6: af00 add r7, sp, #0 8017ad8: 6078 str r0, [r7, #4] 8017ada: 460b mov r3, r1 8017adc: 807b strh r3, [r7, #2] return pbuf_header_impl(p, header_size_increment, 1); 8017ade: f9b7 3002 ldrsh.w r3, [r7, #2] 8017ae2: 2201 movs r2, #1 8017ae4: 4619 mov r1, r3 8017ae6: 6878 ldr r0, [r7, #4] 8017ae8: f7ff ffd2 bl 8017a90 8017aec: 4603 mov r3, r0 } 8017aee: 4618 mov r0, r3 8017af0: 3708 adds r7, #8 8017af2: 46bd mov sp, r7 8017af4: bd80 pop {r7, pc} ... 08017af8 : * 1->1->1 becomes ....... * */ u8_t pbuf_free(struct pbuf *p) { 8017af8: b580 push {r7, lr} 8017afa: b088 sub sp, #32 8017afc: af00 add r7, sp, #0 8017afe: 6078 str r0, [r7, #4] u8_t alloc_src; struct pbuf *q; u8_t count; if (p == NULL) { 8017b00: 687b ldr r3, [r7, #4] 8017b02: 2b00 cmp r3, #0 8017b04: d10b bne.n 8017b1e LWIP_ASSERT("p != NULL", p != NULL); 8017b06: 687b ldr r3, [r7, #4] 8017b08: 2b00 cmp r3, #0 8017b0a: d106 bne.n 8017b1a 8017b0c: 4b3b ldr r3, [pc, #236] ; (8017bfc ) 8017b0e: f44f 7237 mov.w r2, #732 ; 0x2dc 8017b12: 493b ldr r1, [pc, #236] ; (8017c00 ) 8017b14: 483b ldr r0, [pc, #236] ; (8017c04 ) 8017b16: f009 ff37 bl 8021988 /* if assertions are disabled, proceed with debug output */ LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("pbuf_free(p == NULL) was called.\n")); return 0; 8017b1a: 2300 movs r3, #0 8017b1c: e069 b.n 8017bf2 } LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p)); PERF_START; count = 0; 8017b1e: 2300 movs r3, #0 8017b20: 77fb strb r3, [r7, #31] /* de-allocate all consecutive pbufs from the head of the chain that * obtain a zero reference count after decrementing*/ while (p != NULL) { 8017b22: e062 b.n 8017bea LWIP_PBUF_REF_T ref; SYS_ARCH_DECL_PROTECT(old_level); /* Since decrementing ref cannot be guaranteed to be a single machine operation * we must protect it. We put the new ref into a local variable to prevent * further protection. */ SYS_ARCH_PROTECT(old_level); 8017b24: f009 fd96 bl 8021654 8017b28: 61b8 str r0, [r7, #24] /* all pbufs in a chain are referenced at least once */ LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); 8017b2a: 687b ldr r3, [r7, #4] 8017b2c: 7b9b ldrb r3, [r3, #14] 8017b2e: 2b00 cmp r3, #0 8017b30: d106 bne.n 8017b40 8017b32: 4b32 ldr r3, [pc, #200] ; (8017bfc ) 8017b34: f240 22f1 movw r2, #753 ; 0x2f1 8017b38: 4933 ldr r1, [pc, #204] ; (8017c08 ) 8017b3a: 4832 ldr r0, [pc, #200] ; (8017c04 ) 8017b3c: f009 ff24 bl 8021988 /* decrease reference count (number of pointers to pbuf) */ ref = --(p->ref); 8017b40: 687b ldr r3, [r7, #4] 8017b42: 7b9b ldrb r3, [r3, #14] 8017b44: 3b01 subs r3, #1 8017b46: b2da uxtb r2, r3 8017b48: 687b ldr r3, [r7, #4] 8017b4a: 739a strb r2, [r3, #14] 8017b4c: 687b ldr r3, [r7, #4] 8017b4e: 7b9b ldrb r3, [r3, #14] 8017b50: 75fb strb r3, [r7, #23] SYS_ARCH_UNPROTECT(old_level); 8017b52: 69b8 ldr r0, [r7, #24] 8017b54: f009 fd8c bl 8021670 /* this pbuf is no longer referenced to? */ if (ref == 0) { 8017b58: 7dfb ldrb r3, [r7, #23] 8017b5a: 2b00 cmp r3, #0 8017b5c: d143 bne.n 8017be6 /* remember next pbuf in chain for next iteration */ q = p->next; 8017b5e: 687b ldr r3, [r7, #4] 8017b60: 681b ldr r3, [r3, #0] 8017b62: 613b str r3, [r7, #16] LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p)); alloc_src = pbuf_get_allocsrc(p); 8017b64: 687b ldr r3, [r7, #4] 8017b66: 7b1b ldrb r3, [r3, #12] 8017b68: f003 030f and.w r3, r3, #15 8017b6c: 73fb strb r3, [r7, #15] #if LWIP_SUPPORT_CUSTOM_PBUF /* is this a custom pbuf? */ if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) { 8017b6e: 687b ldr r3, [r7, #4] 8017b70: 7b5b ldrb r3, [r3, #13] 8017b72: f003 0302 and.w r3, r3, #2 8017b76: 2b00 cmp r3, #0 8017b78: d011 beq.n 8017b9e struct pbuf_custom *pc = (struct pbuf_custom *)p; 8017b7a: 687b ldr r3, [r7, #4] 8017b7c: 60bb str r3, [r7, #8] LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL); 8017b7e: 68bb ldr r3, [r7, #8] 8017b80: 691b ldr r3, [r3, #16] 8017b82: 2b00 cmp r3, #0 8017b84: d106 bne.n 8017b94 8017b86: 4b1d ldr r3, [pc, #116] ; (8017bfc ) 8017b88: f240 22ff movw r2, #767 ; 0x2ff 8017b8c: 491f ldr r1, [pc, #124] ; (8017c0c ) 8017b8e: 481d ldr r0, [pc, #116] ; (8017c04 ) 8017b90: f009 fefa bl 8021988 pc->custom_free_function(p); 8017b94: 68bb ldr r3, [r7, #8] 8017b96: 691b ldr r3, [r3, #16] 8017b98: 6878 ldr r0, [r7, #4] 8017b9a: 4798 blx r3 8017b9c: e01d b.n 8017bda } else #endif /* LWIP_SUPPORT_CUSTOM_PBUF */ { /* is this a pbuf from the pool? */ if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) { 8017b9e: 7bfb ldrb r3, [r7, #15] 8017ba0: 2b02 cmp r3, #2 8017ba2: d104 bne.n 8017bae memp_free(MEMP_PBUF_POOL, p); 8017ba4: 6879 ldr r1, [r7, #4] 8017ba6: 200c movs r0, #12 8017ba8: f7ff f808 bl 8016bbc 8017bac: e015 b.n 8017bda /* is this a ROM or RAM referencing pbuf? */ } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) { 8017bae: 7bfb ldrb r3, [r7, #15] 8017bb0: 2b01 cmp r3, #1 8017bb2: d104 bne.n 8017bbe memp_free(MEMP_PBUF, p); 8017bb4: 6879 ldr r1, [r7, #4] 8017bb6: 200b movs r0, #11 8017bb8: f7ff f800 bl 8016bbc 8017bbc: e00d b.n 8017bda /* type == PBUF_RAM */ } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) { 8017bbe: 7bfb ldrb r3, [r7, #15] 8017bc0: 2b00 cmp r3, #0 8017bc2: d103 bne.n 8017bcc mem_free(p); 8017bc4: 6878 ldr r0, [r7, #4] 8017bc6: f7fe fc13 bl 80163f0 8017bca: e006 b.n 8017bda } else { /* @todo: support freeing other types */ LWIP_ASSERT("invalid pbuf type", 0); 8017bcc: 4b0b ldr r3, [pc, #44] ; (8017bfc ) 8017bce: f240 320f movw r2, #783 ; 0x30f 8017bd2: 490f ldr r1, [pc, #60] ; (8017c10 ) 8017bd4: 480b ldr r0, [pc, #44] ; (8017c04 ) 8017bd6: f009 fed7 bl 8021988 } } count++; 8017bda: 7ffb ldrb r3, [r7, #31] 8017bdc: 3301 adds r3, #1 8017bde: 77fb strb r3, [r7, #31] /* proceed to next pbuf */ p = q; 8017be0: 693b ldr r3, [r7, #16] 8017be2: 607b str r3, [r7, #4] 8017be4: e001 b.n 8017bea /* p->ref > 0, this pbuf is still referenced to */ /* (and so the remaining pbufs in chain as well) */ } else { LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref)); /* stop walking through the chain */ p = NULL; 8017be6: 2300 movs r3, #0 8017be8: 607b str r3, [r7, #4] while (p != NULL) { 8017bea: 687b ldr r3, [r7, #4] 8017bec: 2b00 cmp r3, #0 8017bee: d199 bne.n 8017b24 } } PERF_STOP("pbuf_free"); /* return number of de-allocated pbufs */ return count; 8017bf0: 7ffb ldrb r3, [r7, #31] } 8017bf2: 4618 mov r0, r3 8017bf4: 3720 adds r7, #32 8017bf6: 46bd mov sp, r7 8017bf8: bd80 pop {r7, pc} 8017bfa: bf00 nop 8017bfc: 080246a8 .word 0x080246a8 8017c00: 0802480c .word 0x0802480c 8017c04: 08024708 .word 0x08024708 8017c08: 08024838 .word 0x08024838 8017c0c: 08024850 .word 0x08024850 8017c10: 08024874 .word 0x08024874 08017c14 : * @param p first pbuf of chain * @return the number of pbufs in a chain */ u16_t pbuf_clen(const struct pbuf *p) { 8017c14: b480 push {r7} 8017c16: b085 sub sp, #20 8017c18: af00 add r7, sp, #0 8017c1a: 6078 str r0, [r7, #4] u16_t len; len = 0; 8017c1c: 2300 movs r3, #0 8017c1e: 81fb strh r3, [r7, #14] while (p != NULL) { 8017c20: e005 b.n 8017c2e ++len; 8017c22: 89fb ldrh r3, [r7, #14] 8017c24: 3301 adds r3, #1 8017c26: 81fb strh r3, [r7, #14] p = p->next; 8017c28: 687b ldr r3, [r7, #4] 8017c2a: 681b ldr r3, [r3, #0] 8017c2c: 607b str r3, [r7, #4] while (p != NULL) { 8017c2e: 687b ldr r3, [r7, #4] 8017c30: 2b00 cmp r3, #0 8017c32: d1f6 bne.n 8017c22 } return len; 8017c34: 89fb ldrh r3, [r7, #14] } 8017c36: 4618 mov r0, r3 8017c38: 3714 adds r7, #20 8017c3a: 46bd mov sp, r7 8017c3c: f85d 7b04 ldr.w r7, [sp], #4 8017c40: 4770 bx lr ... 08017c44 : * @param p pbuf to increase reference counter of * */ void pbuf_ref(struct pbuf *p) { 8017c44: b580 push {r7, lr} 8017c46: b084 sub sp, #16 8017c48: af00 add r7, sp, #0 8017c4a: 6078 str r0, [r7, #4] /* pbuf given? */ if (p != NULL) { 8017c4c: 687b ldr r3, [r7, #4] 8017c4e: 2b00 cmp r3, #0 8017c50: d016 beq.n 8017c80 SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1)); 8017c52: f009 fcff bl 8021654 8017c56: 60f8 str r0, [r7, #12] 8017c58: 687b ldr r3, [r7, #4] 8017c5a: 7b9b ldrb r3, [r3, #14] 8017c5c: 3301 adds r3, #1 8017c5e: b2da uxtb r2, r3 8017c60: 687b ldr r3, [r7, #4] 8017c62: 739a strb r2, [r3, #14] 8017c64: 68f8 ldr r0, [r7, #12] 8017c66: f009 fd03 bl 8021670 LWIP_ASSERT("pbuf ref overflow", p->ref > 0); 8017c6a: 687b ldr r3, [r7, #4] 8017c6c: 7b9b ldrb r3, [r3, #14] 8017c6e: 2b00 cmp r3, #0 8017c70: d106 bne.n 8017c80 8017c72: 4b05 ldr r3, [pc, #20] ; (8017c88 ) 8017c74: f240 3242 movw r2, #834 ; 0x342 8017c78: 4904 ldr r1, [pc, #16] ; (8017c8c ) 8017c7a: 4805 ldr r0, [pc, #20] ; (8017c90 ) 8017c7c: f009 fe84 bl 8021988 } } 8017c80: bf00 nop 8017c82: 3710 adds r7, #16 8017c84: 46bd mov sp, r7 8017c86: bd80 pop {r7, pc} 8017c88: 080246a8 .word 0x080246a8 8017c8c: 08024888 .word 0x08024888 8017c90: 08024708 .word 0x08024708 08017c94 : * * @see pbuf_chain() */ void pbuf_cat(struct pbuf *h, struct pbuf *t) { 8017c94: b580 push {r7, lr} 8017c96: b084 sub sp, #16 8017c98: af00 add r7, sp, #0 8017c9a: 6078 str r0, [r7, #4] 8017c9c: 6039 str r1, [r7, #0] struct pbuf *p; LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)", 8017c9e: 687b ldr r3, [r7, #4] 8017ca0: 2b00 cmp r3, #0 8017ca2: d002 beq.n 8017caa 8017ca4: 683b ldr r3, [r7, #0] 8017ca6: 2b00 cmp r3, #0 8017ca8: d107 bne.n 8017cba 8017caa: 4b20 ldr r3, [pc, #128] ; (8017d2c ) 8017cac: f240 3259 movw r2, #857 ; 0x359 8017cb0: 491f ldr r1, [pc, #124] ; (8017d30 ) 8017cb2: 4820 ldr r0, [pc, #128] ; (8017d34 ) 8017cb4: f009 fe68 bl 8021988 8017cb8: e034 b.n 8017d24 ((h != NULL) && (t != NULL)), return;); /* proceed to last pbuf of chain */ for (p = h; p->next != NULL; p = p->next) { 8017cba: 687b ldr r3, [r7, #4] 8017cbc: 60fb str r3, [r7, #12] 8017cbe: e00a b.n 8017cd6 /* add total length of second chain to all totals of first chain */ p->tot_len = (u16_t)(p->tot_len + t->tot_len); 8017cc0: 68fb ldr r3, [r7, #12] 8017cc2: 891a ldrh r2, [r3, #8] 8017cc4: 683b ldr r3, [r7, #0] 8017cc6: 891b ldrh r3, [r3, #8] 8017cc8: 4413 add r3, r2 8017cca: b29a uxth r2, r3 8017ccc: 68fb ldr r3, [r7, #12] 8017cce: 811a strh r2, [r3, #8] for (p = h; p->next != NULL; p = p->next) { 8017cd0: 68fb ldr r3, [r7, #12] 8017cd2: 681b ldr r3, [r3, #0] 8017cd4: 60fb str r3, [r7, #12] 8017cd6: 68fb ldr r3, [r7, #12] 8017cd8: 681b ldr r3, [r3, #0] 8017cda: 2b00 cmp r3, #0 8017cdc: d1f0 bne.n 8017cc0 } /* { p is last pbuf of first h chain, p->next == NULL } */ LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); 8017cde: 68fb ldr r3, [r7, #12] 8017ce0: 891a ldrh r2, [r3, #8] 8017ce2: 68fb ldr r3, [r7, #12] 8017ce4: 895b ldrh r3, [r3, #10] 8017ce6: 429a cmp r2, r3 8017ce8: d006 beq.n 8017cf8 8017cea: 4b10 ldr r3, [pc, #64] ; (8017d2c ) 8017cec: f240 3262 movw r2, #866 ; 0x362 8017cf0: 4911 ldr r1, [pc, #68] ; (8017d38 ) 8017cf2: 4810 ldr r0, [pc, #64] ; (8017d34 ) 8017cf4: f009 fe48 bl 8021988 LWIP_ASSERT("p->next == NULL", p->next == NULL); 8017cf8: 68fb ldr r3, [r7, #12] 8017cfa: 681b ldr r3, [r3, #0] 8017cfc: 2b00 cmp r3, #0 8017cfe: d006 beq.n 8017d0e 8017d00: 4b0a ldr r3, [pc, #40] ; (8017d2c ) 8017d02: f240 3263 movw r2, #867 ; 0x363 8017d06: 490d ldr r1, [pc, #52] ; (8017d3c ) 8017d08: 480a ldr r0, [pc, #40] ; (8017d34 ) 8017d0a: f009 fe3d bl 8021988 /* add total length of second chain to last pbuf total of first chain */ p->tot_len = (u16_t)(p->tot_len + t->tot_len); 8017d0e: 68fb ldr r3, [r7, #12] 8017d10: 891a ldrh r2, [r3, #8] 8017d12: 683b ldr r3, [r7, #0] 8017d14: 891b ldrh r3, [r3, #8] 8017d16: 4413 add r3, r2 8017d18: b29a uxth r2, r3 8017d1a: 68fb ldr r3, [r7, #12] 8017d1c: 811a strh r2, [r3, #8] /* chain last pbuf of head (p) with first of tail (t) */ p->next = t; 8017d1e: 68fb ldr r3, [r7, #12] 8017d20: 683a ldr r2, [r7, #0] 8017d22: 601a str r2, [r3, #0] /* p->next now references t, but the caller will drop its reference to t, * so netto there is no change to the reference count of t. */ } 8017d24: 3710 adds r7, #16 8017d26: 46bd mov sp, r7 8017d28: bd80 pop {r7, pc} 8017d2a: bf00 nop 8017d2c: 080246a8 .word 0x080246a8 8017d30: 0802489c .word 0x0802489c 8017d34: 08024708 .word 0x08024708 8017d38: 080248d4 .word 0x080248d4 8017d3c: 08024904 .word 0x08024904 08017d40 : * ERR_ARG if one of the pbufs is NULL or p_to is not big * enough to hold p_from */ err_t pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from) { 8017d40: b580 push {r7, lr} 8017d42: b086 sub sp, #24 8017d44: af00 add r7, sp, #0 8017d46: 6078 str r0, [r7, #4] 8017d48: 6039 str r1, [r7, #0] size_t offset_to = 0, offset_from = 0, len; 8017d4a: 2300 movs r3, #0 8017d4c: 617b str r3, [r7, #20] 8017d4e: 2300 movs r3, #0 8017d50: 613b str r3, [r7, #16] LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n", (const void *)p_to, (const void *)p_from)); /* is the target big enough to hold the source? */ LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) && 8017d52: 687b ldr r3, [r7, #4] 8017d54: 2b00 cmp r3, #0 8017d56: d008 beq.n 8017d6a 8017d58: 683b ldr r3, [r7, #0] 8017d5a: 2b00 cmp r3, #0 8017d5c: d005 beq.n 8017d6a 8017d5e: 687b ldr r3, [r7, #4] 8017d60: 891a ldrh r2, [r3, #8] 8017d62: 683b ldr r3, [r7, #0] 8017d64: 891b ldrh r3, [r3, #8] 8017d66: 429a cmp r2, r3 8017d68: d209 bcs.n 8017d7e 8017d6a: 4b57 ldr r3, [pc, #348] ; (8017ec8 ) 8017d6c: f240 32c9 movw r2, #969 ; 0x3c9 8017d70: 4956 ldr r1, [pc, #344] ; (8017ecc ) 8017d72: 4857 ldr r0, [pc, #348] ; (8017ed0 ) 8017d74: f009 fe08 bl 8021988 8017d78: f06f 030f mvn.w r3, #15 8017d7c: e09f b.n 8017ebe (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;); /* iterate through pbuf chain */ do { /* copy one part of the original chain */ if ((p_to->len - offset_to) >= (p_from->len - offset_from)) { 8017d7e: 687b ldr r3, [r7, #4] 8017d80: 895b ldrh r3, [r3, #10] 8017d82: 461a mov r2, r3 8017d84: 697b ldr r3, [r7, #20] 8017d86: 1ad2 subs r2, r2, r3 8017d88: 683b ldr r3, [r7, #0] 8017d8a: 895b ldrh r3, [r3, #10] 8017d8c: 4619 mov r1, r3 8017d8e: 693b ldr r3, [r7, #16] 8017d90: 1acb subs r3, r1, r3 8017d92: 429a cmp r2, r3 8017d94: d306 bcc.n 8017da4 /* complete current p_from fits into current p_to */ len = p_from->len - offset_from; 8017d96: 683b ldr r3, [r7, #0] 8017d98: 895b ldrh r3, [r3, #10] 8017d9a: 461a mov r2, r3 8017d9c: 693b ldr r3, [r7, #16] 8017d9e: 1ad3 subs r3, r2, r3 8017da0: 60fb str r3, [r7, #12] 8017da2: e005 b.n 8017db0 } else { /* current p_from does not fit into current p_to */ len = p_to->len - offset_to; 8017da4: 687b ldr r3, [r7, #4] 8017da6: 895b ldrh r3, [r3, #10] 8017da8: 461a mov r2, r3 8017daa: 697b ldr r3, [r7, #20] 8017dac: 1ad3 subs r3, r2, r3 8017dae: 60fb str r3, [r7, #12] } MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len); 8017db0: 687b ldr r3, [r7, #4] 8017db2: 685a ldr r2, [r3, #4] 8017db4: 697b ldr r3, [r7, #20] 8017db6: 18d0 adds r0, r2, r3 8017db8: 683b ldr r3, [r7, #0] 8017dba: 685a ldr r2, [r3, #4] 8017dbc: 693b ldr r3, [r7, #16] 8017dbe: 4413 add r3, r2 8017dc0: 68fa ldr r2, [r7, #12] 8017dc2: 4619 mov r1, r3 8017dc4: f00a f80f bl 8021de6 offset_to += len; 8017dc8: 697a ldr r2, [r7, #20] 8017dca: 68fb ldr r3, [r7, #12] 8017dcc: 4413 add r3, r2 8017dce: 617b str r3, [r7, #20] offset_from += len; 8017dd0: 693a ldr r2, [r7, #16] 8017dd2: 68fb ldr r3, [r7, #12] 8017dd4: 4413 add r3, r2 8017dd6: 613b str r3, [r7, #16] LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len); 8017dd8: 687b ldr r3, [r7, #4] 8017dda: 895b ldrh r3, [r3, #10] 8017ddc: 461a mov r2, r3 8017dde: 697b ldr r3, [r7, #20] 8017de0: 4293 cmp r3, r2 8017de2: d906 bls.n 8017df2 8017de4: 4b38 ldr r3, [pc, #224] ; (8017ec8 ) 8017de6: f240 32d9 movw r2, #985 ; 0x3d9 8017dea: 493a ldr r1, [pc, #232] ; (8017ed4 ) 8017dec: 4838 ldr r0, [pc, #224] ; (8017ed0 ) 8017dee: f009 fdcb bl 8021988 LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len); 8017df2: 683b ldr r3, [r7, #0] 8017df4: 895b ldrh r3, [r3, #10] 8017df6: 461a mov r2, r3 8017df8: 693b ldr r3, [r7, #16] 8017dfa: 4293 cmp r3, r2 8017dfc: d906 bls.n 8017e0c 8017dfe: 4b32 ldr r3, [pc, #200] ; (8017ec8 ) 8017e00: f240 32da movw r2, #986 ; 0x3da 8017e04: 4934 ldr r1, [pc, #208] ; (8017ed8 ) 8017e06: 4832 ldr r0, [pc, #200] ; (8017ed0 ) 8017e08: f009 fdbe bl 8021988 if (offset_from >= p_from->len) { 8017e0c: 683b ldr r3, [r7, #0] 8017e0e: 895b ldrh r3, [r3, #10] 8017e10: 461a mov r2, r3 8017e12: 693b ldr r3, [r7, #16] 8017e14: 4293 cmp r3, r2 8017e16: d304 bcc.n 8017e22 /* on to next p_from (if any) */ offset_from = 0; 8017e18: 2300 movs r3, #0 8017e1a: 613b str r3, [r7, #16] p_from = p_from->next; 8017e1c: 683b ldr r3, [r7, #0] 8017e1e: 681b ldr r3, [r3, #0] 8017e20: 603b str r3, [r7, #0] } if (offset_to == p_to->len) { 8017e22: 687b ldr r3, [r7, #4] 8017e24: 895b ldrh r3, [r3, #10] 8017e26: 461a mov r2, r3 8017e28: 697b ldr r3, [r7, #20] 8017e2a: 4293 cmp r3, r2 8017e2c: d114 bne.n 8017e58 /* on to next p_to (if any) */ offset_to = 0; 8017e2e: 2300 movs r3, #0 8017e30: 617b str r3, [r7, #20] p_to = p_to->next; 8017e32: 687b ldr r3, [r7, #4] 8017e34: 681b ldr r3, [r3, #0] 8017e36: 607b str r3, [r7, #4] LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;); 8017e38: 687b ldr r3, [r7, #4] 8017e3a: 2b00 cmp r3, #0 8017e3c: d10c bne.n 8017e58 8017e3e: 683b ldr r3, [r7, #0] 8017e40: 2b00 cmp r3, #0 8017e42: d009 beq.n 8017e58 8017e44: 4b20 ldr r3, [pc, #128] ; (8017ec8 ) 8017e46: f44f 7279 mov.w r2, #996 ; 0x3e4 8017e4a: 4924 ldr r1, [pc, #144] ; (8017edc ) 8017e4c: 4820 ldr r0, [pc, #128] ; (8017ed0 ) 8017e4e: f009 fd9b bl 8021988 8017e52: f06f 030f mvn.w r3, #15 8017e56: e032 b.n 8017ebe } if ((p_from != NULL) && (p_from->len == p_from->tot_len)) { 8017e58: 683b ldr r3, [r7, #0] 8017e5a: 2b00 cmp r3, #0 8017e5c: d013 beq.n 8017e86 8017e5e: 683b ldr r3, [r7, #0] 8017e60: 895a ldrh r2, [r3, #10] 8017e62: 683b ldr r3, [r7, #0] 8017e64: 891b ldrh r3, [r3, #8] 8017e66: 429a cmp r2, r3 8017e68: d10d bne.n 8017e86 /* don't copy more than one packet! */ LWIP_ERROR("pbuf_copy() does not allow packet queues!", 8017e6a: 683b ldr r3, [r7, #0] 8017e6c: 681b ldr r3, [r3, #0] 8017e6e: 2b00 cmp r3, #0 8017e70: d009 beq.n 8017e86 8017e72: 4b15 ldr r3, [pc, #84] ; (8017ec8 ) 8017e74: f240 32e9 movw r2, #1001 ; 0x3e9 8017e78: 4919 ldr r1, [pc, #100] ; (8017ee0 ) 8017e7a: 4815 ldr r0, [pc, #84] ; (8017ed0 ) 8017e7c: f009 fd84 bl 8021988 8017e80: f06f 0305 mvn.w r3, #5 8017e84: e01b b.n 8017ebe (p_from->next == NULL), return ERR_VAL;); } if ((p_to != NULL) && (p_to->len == p_to->tot_len)) { 8017e86: 687b ldr r3, [r7, #4] 8017e88: 2b00 cmp r3, #0 8017e8a: d013 beq.n 8017eb4 8017e8c: 687b ldr r3, [r7, #4] 8017e8e: 895a ldrh r2, [r3, #10] 8017e90: 687b ldr r3, [r7, #4] 8017e92: 891b ldrh r3, [r3, #8] 8017e94: 429a cmp r2, r3 8017e96: d10d bne.n 8017eb4 /* don't copy more than one packet! */ LWIP_ERROR("pbuf_copy() does not allow packet queues!", 8017e98: 687b ldr r3, [r7, #4] 8017e9a: 681b ldr r3, [r3, #0] 8017e9c: 2b00 cmp r3, #0 8017e9e: d009 beq.n 8017eb4 8017ea0: 4b09 ldr r3, [pc, #36] ; (8017ec8 ) 8017ea2: f240 32ee movw r2, #1006 ; 0x3ee 8017ea6: 490e ldr r1, [pc, #56] ; (8017ee0 ) 8017ea8: 4809 ldr r0, [pc, #36] ; (8017ed0 ) 8017eaa: f009 fd6d bl 8021988 8017eae: f06f 0305 mvn.w r3, #5 8017eb2: e004 b.n 8017ebe (p_to->next == NULL), return ERR_VAL;); } } while (p_from); 8017eb4: 683b ldr r3, [r7, #0] 8017eb6: 2b00 cmp r3, #0 8017eb8: f47f af61 bne.w 8017d7e LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n")); return ERR_OK; 8017ebc: 2300 movs r3, #0 } 8017ebe: 4618 mov r0, r3 8017ec0: 3718 adds r7, #24 8017ec2: 46bd mov sp, r7 8017ec4: bd80 pop {r7, pc} 8017ec6: bf00 nop 8017ec8: 080246a8 .word 0x080246a8 8017ecc: 08024950 .word 0x08024950 8017ed0: 08024708 .word 0x08024708 8017ed4: 08024980 .word 0x08024980 8017ed8: 08024998 .word 0x08024998 8017edc: 080249b4 .word 0x080249b4 8017ee0: 080249c4 .word 0x080249c4 08017ee4 : * @param offset offset into the packet buffer from where to begin copying len bytes * @return the number of bytes copied, or 0 on failure */ u16_t pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset) { 8017ee4: b580 push {r7, lr} 8017ee6: b088 sub sp, #32 8017ee8: af00 add r7, sp, #0 8017eea: 60f8 str r0, [r7, #12] 8017eec: 60b9 str r1, [r7, #8] 8017eee: 4611 mov r1, r2 8017ef0: 461a mov r2, r3 8017ef2: 460b mov r3, r1 8017ef4: 80fb strh r3, [r7, #6] 8017ef6: 4613 mov r3, r2 8017ef8: 80bb strh r3, [r7, #4] const struct pbuf *p; u16_t left = 0; 8017efa: 2300 movs r3, #0 8017efc: 837b strh r3, [r7, #26] u16_t buf_copy_len; u16_t copied_total = 0; 8017efe: 2300 movs r3, #0 8017f00: 82fb strh r3, [r7, #22] LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;); 8017f02: 68fb ldr r3, [r7, #12] 8017f04: 2b00 cmp r3, #0 8017f06: d108 bne.n 8017f1a 8017f08: 4b2b ldr r3, [pc, #172] ; (8017fb8 ) 8017f0a: f240 420a movw r2, #1034 ; 0x40a 8017f0e: 492b ldr r1, [pc, #172] ; (8017fbc ) 8017f10: 482b ldr r0, [pc, #172] ; (8017fc0 ) 8017f12: f009 fd39 bl 8021988 8017f16: 2300 movs r3, #0 8017f18: e04a b.n 8017fb0 LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;); 8017f1a: 68bb ldr r3, [r7, #8] 8017f1c: 2b00 cmp r3, #0 8017f1e: d108 bne.n 8017f32 8017f20: 4b25 ldr r3, [pc, #148] ; (8017fb8 ) 8017f22: f240 420b movw r2, #1035 ; 0x40b 8017f26: 4927 ldr r1, [pc, #156] ; (8017fc4 ) 8017f28: 4825 ldr r0, [pc, #148] ; (8017fc0 ) 8017f2a: f009 fd2d bl 8021988 8017f2e: 2300 movs r3, #0 8017f30: e03e b.n 8017fb0 /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ for (p = buf; len != 0 && p != NULL; p = p->next) { 8017f32: 68fb ldr r3, [r7, #12] 8017f34: 61fb str r3, [r7, #28] 8017f36: e034 b.n 8017fa2 if ((offset != 0) && (offset >= p->len)) { 8017f38: 88bb ldrh r3, [r7, #4] 8017f3a: 2b00 cmp r3, #0 8017f3c: d00a beq.n 8017f54 8017f3e: 69fb ldr r3, [r7, #28] 8017f40: 895b ldrh r3, [r3, #10] 8017f42: 88ba ldrh r2, [r7, #4] 8017f44: 429a cmp r2, r3 8017f46: d305 bcc.n 8017f54 /* don't copy from this buffer -> on to the next */ offset = (u16_t)(offset - p->len); 8017f48: 69fb ldr r3, [r7, #28] 8017f4a: 895b ldrh r3, [r3, #10] 8017f4c: 88ba ldrh r2, [r7, #4] 8017f4e: 1ad3 subs r3, r2, r3 8017f50: 80bb strh r3, [r7, #4] 8017f52: e023 b.n 8017f9c } else { /* copy from this buffer. maybe only partially. */ buf_copy_len = (u16_t)(p->len - offset); 8017f54: 69fb ldr r3, [r7, #28] 8017f56: 895a ldrh r2, [r3, #10] 8017f58: 88bb ldrh r3, [r7, #4] 8017f5a: 1ad3 subs r3, r2, r3 8017f5c: 833b strh r3, [r7, #24] if (buf_copy_len > len) { 8017f5e: 8b3a ldrh r2, [r7, #24] 8017f60: 88fb ldrh r3, [r7, #6] 8017f62: 429a cmp r2, r3 8017f64: d901 bls.n 8017f6a buf_copy_len = len; 8017f66: 88fb ldrh r3, [r7, #6] 8017f68: 833b strh r3, [r7, #24] } /* copy the necessary parts of the buffer */ MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len); 8017f6a: 8b7b ldrh r3, [r7, #26] 8017f6c: 68ba ldr r2, [r7, #8] 8017f6e: 18d0 adds r0, r2, r3 8017f70: 69fb ldr r3, [r7, #28] 8017f72: 685a ldr r2, [r3, #4] 8017f74: 88bb ldrh r3, [r7, #4] 8017f76: 4413 add r3, r2 8017f78: 8b3a ldrh r2, [r7, #24] 8017f7a: 4619 mov r1, r3 8017f7c: f009 ff33 bl 8021de6 copied_total = (u16_t)(copied_total + buf_copy_len); 8017f80: 8afa ldrh r2, [r7, #22] 8017f82: 8b3b ldrh r3, [r7, #24] 8017f84: 4413 add r3, r2 8017f86: 82fb strh r3, [r7, #22] left = (u16_t)(left + buf_copy_len); 8017f88: 8b7a ldrh r2, [r7, #26] 8017f8a: 8b3b ldrh r3, [r7, #24] 8017f8c: 4413 add r3, r2 8017f8e: 837b strh r3, [r7, #26] len = (u16_t)(len - buf_copy_len); 8017f90: 88fa ldrh r2, [r7, #6] 8017f92: 8b3b ldrh r3, [r7, #24] 8017f94: 1ad3 subs r3, r2, r3 8017f96: 80fb strh r3, [r7, #6] offset = 0; 8017f98: 2300 movs r3, #0 8017f9a: 80bb strh r3, [r7, #4] for (p = buf; len != 0 && p != NULL; p = p->next) { 8017f9c: 69fb ldr r3, [r7, #28] 8017f9e: 681b ldr r3, [r3, #0] 8017fa0: 61fb str r3, [r7, #28] 8017fa2: 88fb ldrh r3, [r7, #6] 8017fa4: 2b00 cmp r3, #0 8017fa6: d002 beq.n 8017fae 8017fa8: 69fb ldr r3, [r7, #28] 8017faa: 2b00 cmp r3, #0 8017fac: d1c4 bne.n 8017f38 } } return copied_total; 8017fae: 8afb ldrh r3, [r7, #22] } 8017fb0: 4618 mov r0, r3 8017fb2: 3720 adds r7, #32 8017fb4: 46bd mov sp, r7 8017fb6: bd80 pop {r7, pc} 8017fb8: 080246a8 .word 0x080246a8 8017fbc: 080249f0 .word 0x080249f0 8017fc0: 08024708 .word 0x08024708 8017fc4: 08024a10 .word 0x08024a10 08017fc8 : * * @return a new pbuf or NULL if allocation fails */ struct pbuf * pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p) { 8017fc8: b580 push {r7, lr} 8017fca: b084 sub sp, #16 8017fcc: af00 add r7, sp, #0 8017fce: 4603 mov r3, r0 8017fd0: 603a str r2, [r7, #0] 8017fd2: 71fb strb r3, [r7, #7] 8017fd4: 460b mov r3, r1 8017fd6: 80bb strh r3, [r7, #4] struct pbuf *q; err_t err; q = pbuf_alloc(layer, p->tot_len, type); 8017fd8: 683b ldr r3, [r7, #0] 8017fda: 8919 ldrh r1, [r3, #8] 8017fdc: 88ba ldrh r2, [r7, #4] 8017fde: 79fb ldrb r3, [r7, #7] 8017fe0: 4618 mov r0, r3 8017fe2: f7ff faa1 bl 8017528 8017fe6: 60f8 str r0, [r7, #12] if (q == NULL) { 8017fe8: 68fb ldr r3, [r7, #12] 8017fea: 2b00 cmp r3, #0 8017fec: d101 bne.n 8017ff2 return NULL; 8017fee: 2300 movs r3, #0 8017ff0: e011 b.n 8018016 } err = pbuf_copy(q, p); 8017ff2: 6839 ldr r1, [r7, #0] 8017ff4: 68f8 ldr r0, [r7, #12] 8017ff6: f7ff fea3 bl 8017d40 8017ffa: 4603 mov r3, r0 8017ffc: 72fb strb r3, [r7, #11] LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */ LWIP_ASSERT("pbuf_copy failed", err == ERR_OK); 8017ffe: f997 300b ldrsb.w r3, [r7, #11] 8018002: 2b00 cmp r3, #0 8018004: d006 beq.n 8018014 8018006: 4b06 ldr r3, [pc, #24] ; (8018020 ) 8018008: f240 5224 movw r2, #1316 ; 0x524 801800c: 4905 ldr r1, [pc, #20] ; (8018024 ) 801800e: 4806 ldr r0, [pc, #24] ; (8018028 ) 8018010: f009 fcba bl 8021988 return q; 8018014: 68fb ldr r3, [r7, #12] } 8018016: 4618 mov r0, r3 8018018: 3710 adds r7, #16 801801a: 46bd mov sp, r7 801801c: bd80 pop {r7, pc} 801801e: bf00 nop 8018020: 080246a8 .word 0x080246a8 8018024: 08024b1c .word 0x08024b1c 8018028: 08024708 .word 0x08024708 0801802c : /** * Initialize this module. */ void tcp_init(void) { 801802c: b580 push {r7, lr} 801802e: af00 add r7, sp, #0 #ifdef LWIP_RAND tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND()); 8018030: f009 fb2e bl 8021690 8018034: 4603 mov r3, r0 8018036: b29b uxth r3, r3 8018038: f3c3 030d ubfx r3, r3, #0, #14 801803c: b29b uxth r3, r3 801803e: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000 8018042: b29a uxth r2, r3 8018044: 4b01 ldr r3, [pc, #4] ; (801804c ) 8018046: 801a strh r2, [r3, #0] #endif /* LWIP_RAND */ } 8018048: bf00 nop 801804a: bd80 pop {r7, pc} 801804c: 2400003c .word 0x2400003c 08018050 : /** Free a tcp pcb */ void tcp_free(struct tcp_pcb *pcb) { 8018050: b580 push {r7, lr} 8018052: b082 sub sp, #8 8018054: af00 add r7, sp, #0 8018056: 6078 str r0, [r7, #4] LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN); 8018058: 687b ldr r3, [r7, #4] 801805a: 7d1b ldrb r3, [r3, #20] 801805c: 2b01 cmp r3, #1 801805e: d105 bne.n 801806c 8018060: 4b06 ldr r3, [pc, #24] ; (801807c ) 8018062: 22d4 movs r2, #212 ; 0xd4 8018064: 4906 ldr r1, [pc, #24] ; (8018080 ) 8018066: 4807 ldr r0, [pc, #28] ; (8018084 ) 8018068: f009 fc8e bl 8021988 #if LWIP_TCP_PCB_NUM_EXT_ARGS tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args); #endif memp_free(MEMP_TCP_PCB, pcb); 801806c: 6879 ldr r1, [r7, #4] 801806e: 2001 movs r0, #1 8018070: f7fe fda4 bl 8016bbc } 8018074: bf00 nop 8018076: 3708 adds r7, #8 8018078: 46bd mov sp, r7 801807a: bd80 pop {r7, pc} 801807c: 08024ba8 .word 0x08024ba8 8018080: 08024bd8 .word 0x08024bd8 8018084: 08024bec .word 0x08024bec 08018088 : /** Free a tcp listen pcb */ static void tcp_free_listen(struct tcp_pcb *pcb) { 8018088: b580 push {r7, lr} 801808a: b082 sub sp, #8 801808c: af00 add r7, sp, #0 801808e: 6078 str r0, [r7, #4] LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN); 8018090: 687b ldr r3, [r7, #4] 8018092: 7d1b ldrb r3, [r3, #20] 8018094: 2b01 cmp r3, #1 8018096: d105 bne.n 80180a4 8018098: 4b06 ldr r3, [pc, #24] ; (80180b4 ) 801809a: 22df movs r2, #223 ; 0xdf 801809c: 4906 ldr r1, [pc, #24] ; (80180b8 ) 801809e: 4807 ldr r0, [pc, #28] ; (80180bc ) 80180a0: f009 fc72 bl 8021988 #if LWIP_TCP_PCB_NUM_EXT_ARGS tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args); #endif memp_free(MEMP_TCP_PCB_LISTEN, pcb); 80180a4: 6879 ldr r1, [r7, #4] 80180a6: 2002 movs r0, #2 80180a8: f7fe fd88 bl 8016bbc } 80180ac: bf00 nop 80180ae: 3708 adds r7, #8 80180b0: 46bd mov sp, r7 80180b2: bd80 pop {r7, pc} 80180b4: 08024ba8 .word 0x08024ba8 80180b8: 08024c14 .word 0x08024c14 80180bc: 08024bec .word 0x08024bec 080180c0 : /** * Called periodically to dispatch TCP timers. */ void tcp_tmr(void) { 80180c0: b580 push {r7, lr} 80180c2: af00 add r7, sp, #0 /* Call tcp_fasttmr() every 250 ms */ tcp_fasttmr(); 80180c4: f001 f8f6 bl 80192b4 if (++tcp_timer & 1) { 80180c8: 4b07 ldr r3, [pc, #28] ; (80180e8 ) 80180ca: 781b ldrb r3, [r3, #0] 80180cc: 3301 adds r3, #1 80180ce: b2da uxtb r2, r3 80180d0: 4b05 ldr r3, [pc, #20] ; (80180e8 ) 80180d2: 701a strb r2, [r3, #0] 80180d4: 4b04 ldr r3, [pc, #16] ; (80180e8 ) 80180d6: 781b ldrb r3, [r3, #0] 80180d8: f003 0301 and.w r3, r3, #1 80180dc: 2b00 cmp r3, #0 80180de: d001 beq.n 80180e4 /* Call tcp_slowtmr() every 500 ms, i.e., every other timer tcp_tmr() is called. */ tcp_slowtmr(); 80180e0: f000 fda8 bl 8018c34 } } 80180e4: bf00 nop 80180e6: bd80 pop {r7, pc} 80180e8: 2401a495 .word 0x2401a495 080180ec : /** Called when a listen pcb is closed. Iterates one pcb list and removes the * closed listener pcb from pcb->listener if matching. */ static void tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb) { 80180ec: b580 push {r7, lr} 80180ee: b084 sub sp, #16 80180f0: af00 add r7, sp, #0 80180f2: 6078 str r0, [r7, #4] 80180f4: 6039 str r1, [r7, #0] struct tcp_pcb *pcb; LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL); 80180f6: 683b ldr r3, [r7, #0] 80180f8: 2b00 cmp r3, #0 80180fa: d105 bne.n 8018108 80180fc: 4b0d ldr r3, [pc, #52] ; (8018134 ) 80180fe: 22ff movs r2, #255 ; 0xff 8018100: 490d ldr r1, [pc, #52] ; (8018138 ) 8018102: 480e ldr r0, [pc, #56] ; (801813c ) 8018104: f009 fc40 bl 8021988 for (pcb = list; pcb != NULL; pcb = pcb->next) { 8018108: 687b ldr r3, [r7, #4] 801810a: 60fb str r3, [r7, #12] 801810c: e00a b.n 8018124 if (pcb->listener == lpcb) { 801810e: 68fb ldr r3, [r7, #12] 8018110: 6fdb ldr r3, [r3, #124] ; 0x7c 8018112: 683a ldr r2, [r7, #0] 8018114: 429a cmp r2, r3 8018116: d102 bne.n 801811e pcb->listener = NULL; 8018118: 68fb ldr r3, [r7, #12] 801811a: 2200 movs r2, #0 801811c: 67da str r2, [r3, #124] ; 0x7c for (pcb = list; pcb != NULL; pcb = pcb->next) { 801811e: 68fb ldr r3, [r7, #12] 8018120: 68db ldr r3, [r3, #12] 8018122: 60fb str r3, [r7, #12] 8018124: 68fb ldr r3, [r7, #12] 8018126: 2b00 cmp r3, #0 8018128: d1f1 bne.n 801810e } } } 801812a: bf00 nop 801812c: bf00 nop 801812e: 3710 adds r7, #16 8018130: 46bd mov sp, r7 8018132: bd80 pop {r7, pc} 8018134: 08024ba8 .word 0x08024ba8 8018138: 08024c30 .word 0x08024c30 801813c: 08024bec .word 0x08024bec 08018140 : /** Called when a listen pcb is closed. Iterates all pcb lists and removes the * closed listener pcb from pcb->listener if matching. */ static void tcp_listen_closed(struct tcp_pcb *pcb) { 8018140: b580 push {r7, lr} 8018142: b084 sub sp, #16 8018144: af00 add r7, sp, #0 8018146: 6078 str r0, [r7, #4] #if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG size_t i; LWIP_ASSERT("pcb != NULL", pcb != NULL); 8018148: 687b ldr r3, [r7, #4] 801814a: 2b00 cmp r3, #0 801814c: d106 bne.n 801815c 801814e: 4b14 ldr r3, [pc, #80] ; (80181a0 ) 8018150: f240 1211 movw r2, #273 ; 0x111 8018154: 4913 ldr r1, [pc, #76] ; (80181a4 ) 8018156: 4814 ldr r0, [pc, #80] ; (80181a8 ) 8018158: f009 fc16 bl 8021988 LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN); 801815c: 687b ldr r3, [r7, #4] 801815e: 7d1b ldrb r3, [r3, #20] 8018160: 2b01 cmp r3, #1 8018162: d006 beq.n 8018172 8018164: 4b0e ldr r3, [pc, #56] ; (80181a0 ) 8018166: f44f 7289 mov.w r2, #274 ; 0x112 801816a: 4910 ldr r1, [pc, #64] ; (80181ac ) 801816c: 480e ldr r0, [pc, #56] ; (80181a8 ) 801816e: f009 fc0b bl 8021988 for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) { 8018172: 2301 movs r3, #1 8018174: 60fb str r3, [r7, #12] 8018176: e00b b.n 8018190 tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb); 8018178: 4a0d ldr r2, [pc, #52] ; (80181b0 ) 801817a: 68fb ldr r3, [r7, #12] 801817c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8018180: 681b ldr r3, [r3, #0] 8018182: 6879 ldr r1, [r7, #4] 8018184: 4618 mov r0, r3 8018186: f7ff ffb1 bl 80180ec for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) { 801818a: 68fb ldr r3, [r7, #12] 801818c: 3301 adds r3, #1 801818e: 60fb str r3, [r7, #12] 8018190: 68fb ldr r3, [r7, #12] 8018192: 2b03 cmp r3, #3 8018194: d9f0 bls.n 8018178 } #endif LWIP_UNUSED_ARG(pcb); } 8018196: bf00 nop 8018198: bf00 nop 801819a: 3710 adds r7, #16 801819c: 46bd mov sp, r7 801819e: bd80 pop {r7, pc} 80181a0: 08024ba8 .word 0x08024ba8 80181a4: 08024c58 .word 0x08024c58 80181a8: 08024bec .word 0x08024bec 80181ac: 08024c64 .word 0x08024c64 80181b0: 08026cc4 .word 0x08026cc4 080181b4 : * @return ERR_OK if connection has been closed * another err_t if closing failed and pcb is not freed */ static err_t tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data) { 80181b4: b5b0 push {r4, r5, r7, lr} 80181b6: b088 sub sp, #32 80181b8: af04 add r7, sp, #16 80181ba: 6078 str r0, [r7, #4] 80181bc: 460b mov r3, r1 80181be: 70fb strb r3, [r7, #3] LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL); 80181c0: 687b ldr r3, [r7, #4] 80181c2: 2b00 cmp r3, #0 80181c4: d106 bne.n 80181d4 80181c6: 4b63 ldr r3, [pc, #396] ; (8018354 ) 80181c8: f44f 72af mov.w r2, #350 ; 0x15e 80181cc: 4962 ldr r1, [pc, #392] ; (8018358 ) 80181ce: 4863 ldr r0, [pc, #396] ; (801835c ) 80181d0: f009 fbda bl 8021988 if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) { 80181d4: 78fb ldrb r3, [r7, #3] 80181d6: 2b00 cmp r3, #0 80181d8: d067 beq.n 80182aa 80181da: 687b ldr r3, [r7, #4] 80181dc: 7d1b ldrb r3, [r3, #20] 80181de: 2b04 cmp r3, #4 80181e0: d003 beq.n 80181ea 80181e2: 687b ldr r3, [r7, #4] 80181e4: 7d1b ldrb r3, [r3, #20] 80181e6: 2b07 cmp r3, #7 80181e8: d15f bne.n 80182aa if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) { 80181ea: 687b ldr r3, [r7, #4] 80181ec: 6f9b ldr r3, [r3, #120] ; 0x78 80181ee: 2b00 cmp r3, #0 80181f0: d105 bne.n 80181fe 80181f2: 687b ldr r3, [r7, #4] 80181f4: 8d1b ldrh r3, [r3, #40] ; 0x28 80181f6: f241 62d0 movw r2, #5840 ; 0x16d0 80181fa: 4293 cmp r3, r2 80181fc: d055 beq.n 80182aa /* Not all data received by application, send RST to tell the remote side about this. */ LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED); 80181fe: 687b ldr r3, [r7, #4] 8018200: 8b5b ldrh r3, [r3, #26] 8018202: f003 0310 and.w r3, r3, #16 8018206: 2b00 cmp r3, #0 8018208: d106 bne.n 8018218 801820a: 4b52 ldr r3, [pc, #328] ; (8018354 ) 801820c: f44f 72b2 mov.w r2, #356 ; 0x164 8018210: 4953 ldr r1, [pc, #332] ; (8018360 ) 8018212: 4852 ldr r0, [pc, #328] ; (801835c ) 8018214: f009 fbb8 bl 8021988 /* don't call tcp_abort here: we must not deallocate the pcb since that might not be expected when calling tcp_close */ tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, 8018218: 687b ldr r3, [r7, #4] 801821a: 6d18 ldr r0, [r3, #80] ; 0x50 801821c: 687b ldr r3, [r7, #4] 801821e: 6a5c ldr r4, [r3, #36] ; 0x24 8018220: 687d ldr r5, [r7, #4] 8018222: 687b ldr r3, [r7, #4] 8018224: 3304 adds r3, #4 8018226: 687a ldr r2, [r7, #4] 8018228: 8ad2 ldrh r2, [r2, #22] 801822a: 6879 ldr r1, [r7, #4] 801822c: 8b09 ldrh r1, [r1, #24] 801822e: 9102 str r1, [sp, #8] 8018230: 9201 str r2, [sp, #4] 8018232: 9300 str r3, [sp, #0] 8018234: 462b mov r3, r5 8018236: 4622 mov r2, r4 8018238: 4601 mov r1, r0 801823a: 6878 ldr r0, [r7, #4] 801823c: f005 fe7e bl 801df3c pcb->local_port, pcb->remote_port); tcp_pcb_purge(pcb); 8018240: 6878 ldr r0, [r7, #4] 8018242: f001 fbe9 bl 8019a18 TCP_RMV_ACTIVE(pcb); 8018246: 4b47 ldr r3, [pc, #284] ; (8018364 ) 8018248: 681b ldr r3, [r3, #0] 801824a: 687a ldr r2, [r7, #4] 801824c: 429a cmp r2, r3 801824e: d105 bne.n 801825c 8018250: 4b44 ldr r3, [pc, #272] ; (8018364 ) 8018252: 681b ldr r3, [r3, #0] 8018254: 68db ldr r3, [r3, #12] 8018256: 4a43 ldr r2, [pc, #268] ; (8018364 ) 8018258: 6013 str r3, [r2, #0] 801825a: e013 b.n 8018284 801825c: 4b41 ldr r3, [pc, #260] ; (8018364 ) 801825e: 681b ldr r3, [r3, #0] 8018260: 60fb str r3, [r7, #12] 8018262: e00c b.n 801827e 8018264: 68fb ldr r3, [r7, #12] 8018266: 68db ldr r3, [r3, #12] 8018268: 687a ldr r2, [r7, #4] 801826a: 429a cmp r2, r3 801826c: d104 bne.n 8018278 801826e: 687b ldr r3, [r7, #4] 8018270: 68da ldr r2, [r3, #12] 8018272: 68fb ldr r3, [r7, #12] 8018274: 60da str r2, [r3, #12] 8018276: e005 b.n 8018284 8018278: 68fb ldr r3, [r7, #12] 801827a: 68db ldr r3, [r3, #12] 801827c: 60fb str r3, [r7, #12] 801827e: 68fb ldr r3, [r7, #12] 8018280: 2b00 cmp r3, #0 8018282: d1ef bne.n 8018264 8018284: 687b ldr r3, [r7, #4] 8018286: 2200 movs r2, #0 8018288: 60da str r2, [r3, #12] 801828a: 4b37 ldr r3, [pc, #220] ; (8018368 ) 801828c: 2201 movs r2, #1 801828e: 701a strb r2, [r3, #0] /* Deallocate the pcb since we already sent a RST for it */ if (tcp_input_pcb == pcb) { 8018290: 4b36 ldr r3, [pc, #216] ; (801836c ) 8018292: 681b ldr r3, [r3, #0] 8018294: 687a ldr r2, [r7, #4] 8018296: 429a cmp r2, r3 8018298: d102 bne.n 80182a0 /* prevent using a deallocated pcb: free it from tcp_input later */ tcp_trigger_input_pcb_close(); 801829a: f004 f887 bl 801c3ac 801829e: e002 b.n 80182a6 } else { tcp_free(pcb); 80182a0: 6878 ldr r0, [r7, #4] 80182a2: f7ff fed5 bl 8018050 } return ERR_OK; 80182a6: 2300 movs r3, #0 80182a8: e050 b.n 801834c } } /* - states which free the pcb are handled here, - states which send FIN and change state are handled in tcp_close_shutdown_fin() */ switch (pcb->state) { 80182aa: 687b ldr r3, [r7, #4] 80182ac: 7d1b ldrb r3, [r3, #20] 80182ae: 2b02 cmp r3, #2 80182b0: d03b beq.n 801832a 80182b2: 2b02 cmp r3, #2 80182b4: dc44 bgt.n 8018340 80182b6: 2b00 cmp r3, #0 80182b8: d002 beq.n 80182c0 80182ba: 2b01 cmp r3, #1 80182bc: d02a beq.n 8018314 80182be: e03f b.n 8018340 * and the user needs some way to free it should the need arise. * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) * or for a pcb that has been used and then entered the CLOSED state * is erroneous, but this should never happen as the pcb has in those cases * been freed, and so any remaining handles are bogus. */ if (pcb->local_port != 0) { 80182c0: 687b ldr r3, [r7, #4] 80182c2: 8adb ldrh r3, [r3, #22] 80182c4: 2b00 cmp r3, #0 80182c6: d021 beq.n 801830c TCP_RMV(&tcp_bound_pcbs, pcb); 80182c8: 4b29 ldr r3, [pc, #164] ; (8018370 ) 80182ca: 681b ldr r3, [r3, #0] 80182cc: 687a ldr r2, [r7, #4] 80182ce: 429a cmp r2, r3 80182d0: d105 bne.n 80182de 80182d2: 4b27 ldr r3, [pc, #156] ; (8018370 ) 80182d4: 681b ldr r3, [r3, #0] 80182d6: 68db ldr r3, [r3, #12] 80182d8: 4a25 ldr r2, [pc, #148] ; (8018370 ) 80182da: 6013 str r3, [r2, #0] 80182dc: e013 b.n 8018306 80182de: 4b24 ldr r3, [pc, #144] ; (8018370 ) 80182e0: 681b ldr r3, [r3, #0] 80182e2: 60bb str r3, [r7, #8] 80182e4: e00c b.n 8018300 80182e6: 68bb ldr r3, [r7, #8] 80182e8: 68db ldr r3, [r3, #12] 80182ea: 687a ldr r2, [r7, #4] 80182ec: 429a cmp r2, r3 80182ee: d104 bne.n 80182fa 80182f0: 687b ldr r3, [r7, #4] 80182f2: 68da ldr r2, [r3, #12] 80182f4: 68bb ldr r3, [r7, #8] 80182f6: 60da str r2, [r3, #12] 80182f8: e005 b.n 8018306 80182fa: 68bb ldr r3, [r7, #8] 80182fc: 68db ldr r3, [r3, #12] 80182fe: 60bb str r3, [r7, #8] 8018300: 68bb ldr r3, [r7, #8] 8018302: 2b00 cmp r3, #0 8018304: d1ef bne.n 80182e6 8018306: 687b ldr r3, [r7, #4] 8018308: 2200 movs r2, #0 801830a: 60da str r2, [r3, #12] } tcp_free(pcb); 801830c: 6878 ldr r0, [r7, #4] 801830e: f7ff fe9f bl 8018050 break; 8018312: e01a b.n 801834a case LISTEN: tcp_listen_closed(pcb); 8018314: 6878 ldr r0, [r7, #4] 8018316: f7ff ff13 bl 8018140 tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb); 801831a: 6879 ldr r1, [r7, #4] 801831c: 4815 ldr r0, [pc, #84] ; (8018374 ) 801831e: f001 fbcb bl 8019ab8 tcp_free_listen(pcb); 8018322: 6878 ldr r0, [r7, #4] 8018324: f7ff feb0 bl 8018088 break; 8018328: e00f b.n 801834a case SYN_SENT: TCP_PCB_REMOVE_ACTIVE(pcb); 801832a: 6879 ldr r1, [r7, #4] 801832c: 480d ldr r0, [pc, #52] ; (8018364 ) 801832e: f001 fbc3 bl 8019ab8 8018332: 4b0d ldr r3, [pc, #52] ; (8018368 ) 8018334: 2201 movs r2, #1 8018336: 701a strb r2, [r3, #0] tcp_free(pcb); 8018338: 6878 ldr r0, [r7, #4] 801833a: f7ff fe89 bl 8018050 MIB2_STATS_INC(mib2.tcpattemptfails); break; 801833e: e004 b.n 801834a default: return tcp_close_shutdown_fin(pcb); 8018340: 6878 ldr r0, [r7, #4] 8018342: f000 f819 bl 8018378 8018346: 4603 mov r3, r0 8018348: e000 b.n 801834c } return ERR_OK; 801834a: 2300 movs r3, #0 } 801834c: 4618 mov r0, r3 801834e: 3710 adds r7, #16 8018350: 46bd mov sp, r7 8018352: bdb0 pop {r4, r5, r7, pc} 8018354: 08024ba8 .word 0x08024ba8 8018358: 08024c7c .word 0x08024c7c 801835c: 08024bec .word 0x08024bec 8018360: 08024c9c .word 0x08024c9c 8018364: 2401a48c .word 0x2401a48c 8018368: 2401a494 .word 0x2401a494 801836c: 2401a4d0 .word 0x2401a4d0 8018370: 2401a484 .word 0x2401a484 8018374: 2401a488 .word 0x2401a488 08018378 : static err_t tcp_close_shutdown_fin(struct tcp_pcb *pcb) { 8018378: b580 push {r7, lr} 801837a: b084 sub sp, #16 801837c: af00 add r7, sp, #0 801837e: 6078 str r0, [r7, #4] err_t err; LWIP_ASSERT("pcb != NULL", pcb != NULL); 8018380: 687b ldr r3, [r7, #4] 8018382: 2b00 cmp r3, #0 8018384: d106 bne.n 8018394 8018386: 4b2e ldr r3, [pc, #184] ; (8018440 ) 8018388: f44f 72ce mov.w r2, #412 ; 0x19c 801838c: 492d ldr r1, [pc, #180] ; (8018444 ) 801838e: 482e ldr r0, [pc, #184] ; (8018448 ) 8018390: f009 fafa bl 8021988 switch (pcb->state) { 8018394: 687b ldr r3, [r7, #4] 8018396: 7d1b ldrb r3, [r3, #20] 8018398: 2b07 cmp r3, #7 801839a: d020 beq.n 80183de 801839c: 2b07 cmp r3, #7 801839e: dc2b bgt.n 80183f8 80183a0: 2b03 cmp r3, #3 80183a2: d002 beq.n 80183aa 80183a4: 2b04 cmp r3, #4 80183a6: d00d beq.n 80183c4 80183a8: e026 b.n 80183f8 case SYN_RCVD: err = tcp_send_fin(pcb); 80183aa: 6878 ldr r0, [r7, #4] 80183ac: f004 fec8 bl 801d140 80183b0: 4603 mov r3, r0 80183b2: 73fb strb r3, [r7, #15] if (err == ERR_OK) { 80183b4: f997 300f ldrsb.w r3, [r7, #15] 80183b8: 2b00 cmp r3, #0 80183ba: d11f bne.n 80183fc tcp_backlog_accepted(pcb); MIB2_STATS_INC(mib2.tcpattemptfails); pcb->state = FIN_WAIT_1; 80183bc: 687b ldr r3, [r7, #4] 80183be: 2205 movs r2, #5 80183c0: 751a strb r2, [r3, #20] } break; 80183c2: e01b b.n 80183fc case ESTABLISHED: err = tcp_send_fin(pcb); 80183c4: 6878 ldr r0, [r7, #4] 80183c6: f004 febb bl 801d140 80183ca: 4603 mov r3, r0 80183cc: 73fb strb r3, [r7, #15] if (err == ERR_OK) { 80183ce: f997 300f ldrsb.w r3, [r7, #15] 80183d2: 2b00 cmp r3, #0 80183d4: d114 bne.n 8018400 MIB2_STATS_INC(mib2.tcpestabresets); pcb->state = FIN_WAIT_1; 80183d6: 687b ldr r3, [r7, #4] 80183d8: 2205 movs r2, #5 80183da: 751a strb r2, [r3, #20] } break; 80183dc: e010 b.n 8018400 case CLOSE_WAIT: err = tcp_send_fin(pcb); 80183de: 6878 ldr r0, [r7, #4] 80183e0: f004 feae bl 801d140 80183e4: 4603 mov r3, r0 80183e6: 73fb strb r3, [r7, #15] if (err == ERR_OK) { 80183e8: f997 300f ldrsb.w r3, [r7, #15] 80183ec: 2b00 cmp r3, #0 80183ee: d109 bne.n 8018404 MIB2_STATS_INC(mib2.tcpestabresets); pcb->state = LAST_ACK; 80183f0: 687b ldr r3, [r7, #4] 80183f2: 2209 movs r2, #9 80183f4: 751a strb r2, [r3, #20] } break; 80183f6: e005 b.n 8018404 default: /* Has already been closed, do nothing. */ return ERR_OK; 80183f8: 2300 movs r3, #0 80183fa: e01c b.n 8018436 break; 80183fc: bf00 nop 80183fe: e002 b.n 8018406 break; 8018400: bf00 nop 8018402: e000 b.n 8018406 break; 8018404: bf00 nop } if (err == ERR_OK) { 8018406: f997 300f ldrsb.w r3, [r7, #15] 801840a: 2b00 cmp r3, #0 801840c: d103 bne.n 8018416 /* To ensure all data has been sent when tcp_close returns, we have to make sure tcp_output doesn't fail. Since we don't really have to ensure all data has been sent when tcp_close returns (unsent data is sent from tcp timer functions, also), we don't care for the return value of tcp_output for now. */ tcp_output(pcb); 801840e: 6878 ldr r0, [r7, #4] 8018410: f004 ffd4 bl 801d3bc 8018414: e00d b.n 8018432 } else if (err == ERR_MEM) { 8018416: f997 300f ldrsb.w r3, [r7, #15] 801841a: f1b3 3fff cmp.w r3, #4294967295 801841e: d108 bne.n 8018432 /* Mark this pcb for closing. Closing is retried from tcp_tmr. */ tcp_set_flags(pcb, TF_CLOSEPEND); 8018420: 687b ldr r3, [r7, #4] 8018422: 8b5b ldrh r3, [r3, #26] 8018424: f043 0308 orr.w r3, r3, #8 8018428: b29a uxth r2, r3 801842a: 687b ldr r3, [r7, #4] 801842c: 835a strh r2, [r3, #26] /* We have to return ERR_OK from here to indicate to the callers that this pcb should not be used any more as it will be freed soon via tcp_tmr. This is OK here since sending FIN does not guarantee a time frime for actually freeing the pcb, either (it is left in closure states for remote ACK or timeout) */ return ERR_OK; 801842e: 2300 movs r3, #0 8018430: e001 b.n 8018436 } return err; 8018432: f997 300f ldrsb.w r3, [r7, #15] } 8018436: 4618 mov r0, r3 8018438: 3710 adds r7, #16 801843a: 46bd mov sp, r7 801843c: bd80 pop {r7, pc} 801843e: bf00 nop 8018440: 08024ba8 .word 0x08024ba8 8018444: 08024c58 .word 0x08024c58 8018448: 08024bec .word 0x08024bec 0801844c : * @return ERR_OK if connection has been closed * another err_t if closing failed and pcb is not freed */ err_t tcp_close(struct tcp_pcb *pcb) { 801844c: b580 push {r7, lr} 801844e: b082 sub sp, #8 8018450: af00 add r7, sp, #0 8018452: 6078 str r0, [r7, #4] LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG); 8018454: 687b ldr r3, [r7, #4] 8018456: 2b00 cmp r3, #0 8018458: d109 bne.n 801846e 801845a: 4b0f ldr r3, [pc, #60] ; (8018498 ) 801845c: f44f 72f4 mov.w r2, #488 ; 0x1e8 8018460: 490e ldr r1, [pc, #56] ; (801849c ) 8018462: 480f ldr r0, [pc, #60] ; (80184a0 ) 8018464: f009 fa90 bl 8021988 8018468: f06f 030f mvn.w r3, #15 801846c: e00f b.n 801848e LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in ")); tcp_debug_print_state(pcb->state); if (pcb->state != LISTEN) { 801846e: 687b ldr r3, [r7, #4] 8018470: 7d1b ldrb r3, [r3, #20] 8018472: 2b01 cmp r3, #1 8018474: d006 beq.n 8018484 /* Set a flag not to receive any more data... */ tcp_set_flags(pcb, TF_RXCLOSED); 8018476: 687b ldr r3, [r7, #4] 8018478: 8b5b ldrh r3, [r3, #26] 801847a: f043 0310 orr.w r3, r3, #16 801847e: b29a uxth r2, r3 8018480: 687b ldr r3, [r7, #4] 8018482: 835a strh r2, [r3, #26] } /* ... and close */ return tcp_close_shutdown(pcb, 1); 8018484: 2101 movs r1, #1 8018486: 6878 ldr r0, [r7, #4] 8018488: f7ff fe94 bl 80181b4 801848c: 4603 mov r3, r0 } 801848e: 4618 mov r0, r3 8018490: 3708 adds r7, #8 8018492: 46bd mov sp, r7 8018494: bd80 pop {r7, pc} 8018496: bf00 nop 8018498: 08024ba8 .word 0x08024ba8 801849c: 08024cb8 .word 0x08024cb8 80184a0: 08024bec .word 0x08024bec 080184a4 : * @return ERR_OK if shutdown succeeded (or the PCB has already been shut down) * another err_t on error. */ err_t tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx) { 80184a4: b580 push {r7, lr} 80184a6: b084 sub sp, #16 80184a8: af00 add r7, sp, #0 80184aa: 60f8 str r0, [r7, #12] 80184ac: 60b9 str r1, [r7, #8] 80184ae: 607a str r2, [r7, #4] LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("tcp_shutdown: invalid pcb", pcb != NULL, return ERR_ARG); 80184b0: 68fb ldr r3, [r7, #12] 80184b2: 2b00 cmp r3, #0 80184b4: d109 bne.n 80184ca 80184b6: 4b26 ldr r3, [pc, #152] ; (8018550 ) 80184b8: f240 2207 movw r2, #519 ; 0x207 80184bc: 4925 ldr r1, [pc, #148] ; (8018554 ) 80184be: 4826 ldr r0, [pc, #152] ; (8018558 ) 80184c0: f009 fa62 bl 8021988 80184c4: f06f 030f mvn.w r3, #15 80184c8: e03d b.n 8018546 if (pcb->state == LISTEN) { 80184ca: 68fb ldr r3, [r7, #12] 80184cc: 7d1b ldrb r3, [r3, #20] 80184ce: 2b01 cmp r3, #1 80184d0: d102 bne.n 80184d8 return ERR_CONN; 80184d2: f06f 030a mvn.w r3, #10 80184d6: e036 b.n 8018546 } if (shut_rx) { 80184d8: 68bb ldr r3, [r7, #8] 80184da: 2b00 cmp r3, #0 80184dc: d01b beq.n 8018516 /* shut down the receive side: set a flag not to receive any more data... */ tcp_set_flags(pcb, TF_RXCLOSED); 80184de: 68fb ldr r3, [r7, #12] 80184e0: 8b5b ldrh r3, [r3, #26] 80184e2: f043 0310 orr.w r3, r3, #16 80184e6: b29a uxth r2, r3 80184e8: 68fb ldr r3, [r7, #12] 80184ea: 835a strh r2, [r3, #26] if (shut_tx) { 80184ec: 687b ldr r3, [r7, #4] 80184ee: 2b00 cmp r3, #0 80184f0: d005 beq.n 80184fe /* shutting down the tx AND rx side is the same as closing for the raw API */ return tcp_close_shutdown(pcb, 1); 80184f2: 2101 movs r1, #1 80184f4: 68f8 ldr r0, [r7, #12] 80184f6: f7ff fe5d bl 80181b4 80184fa: 4603 mov r3, r0 80184fc: e023 b.n 8018546 } /* ... and free buffered data */ if (pcb->refused_data != NULL) { 80184fe: 68fb ldr r3, [r7, #12] 8018500: 6f9b ldr r3, [r3, #120] ; 0x78 8018502: 2b00 cmp r3, #0 8018504: d007 beq.n 8018516 pbuf_free(pcb->refused_data); 8018506: 68fb ldr r3, [r7, #12] 8018508: 6f9b ldr r3, [r3, #120] ; 0x78 801850a: 4618 mov r0, r3 801850c: f7ff faf4 bl 8017af8 pcb->refused_data = NULL; 8018510: 68fb ldr r3, [r7, #12] 8018512: 2200 movs r2, #0 8018514: 679a str r2, [r3, #120] ; 0x78 } } if (shut_tx) { 8018516: 687b ldr r3, [r7, #4] 8018518: 2b00 cmp r3, #0 801851a: d013 beq.n 8018544 /* This can't happen twice since if it succeeds, the pcb's state is changed. Only close in these states as the others directly deallocate the PCB */ switch (pcb->state) { 801851c: 68fb ldr r3, [r7, #12] 801851e: 7d1b ldrb r3, [r3, #20] 8018520: 2b04 cmp r3, #4 8018522: dc02 bgt.n 801852a 8018524: 2b03 cmp r3, #3 8018526: da02 bge.n 801852e 8018528: e009 b.n 801853e 801852a: 2b07 cmp r3, #7 801852c: d107 bne.n 801853e case SYN_RCVD: case ESTABLISHED: case CLOSE_WAIT: return tcp_close_shutdown(pcb, (u8_t)shut_rx); 801852e: 68bb ldr r3, [r7, #8] 8018530: b2db uxtb r3, r3 8018532: 4619 mov r1, r3 8018534: 68f8 ldr r0, [r7, #12] 8018536: f7ff fe3d bl 80181b4 801853a: 4603 mov r3, r0 801853c: e003 b.n 8018546 default: /* Not (yet?) connected, cannot shutdown the TX side as that would bring us into CLOSED state, where the PCB is deallocated. */ return ERR_CONN; 801853e: f06f 030a mvn.w r3, #10 8018542: e000 b.n 8018546 } } return ERR_OK; 8018544: 2300 movs r3, #0 } 8018546: 4618 mov r0, r3 8018548: 3710 adds r7, #16 801854a: 46bd mov sp, r7 801854c: bd80 pop {r7, pc} 801854e: bf00 nop 8018550: 08024ba8 .word 0x08024ba8 8018554: 08024cd0 .word 0x08024cd0 8018558: 08024bec .word 0x08024bec 0801855c : * @param pcb the tcp_pcb to abort * @param reset boolean to indicate whether a reset should be sent */ void tcp_abandon(struct tcp_pcb *pcb, int reset) { 801855c: b580 push {r7, lr} 801855e: b08e sub sp, #56 ; 0x38 8018560: af04 add r7, sp, #16 8018562: 6078 str r0, [r7, #4] 8018564: 6039 str r1, [r7, #0] #endif /* LWIP_CALLBACK_API */ void *errf_arg; LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return); 8018566: 687b ldr r3, [r7, #4] 8018568: 2b00 cmp r3, #0 801856a: d107 bne.n 801857c 801856c: 4b52 ldr r3, [pc, #328] ; (80186b8 ) 801856e: f240 223d movw r2, #573 ; 0x23d 8018572: 4952 ldr r1, [pc, #328] ; (80186bc ) 8018574: 4852 ldr r0, [pc, #328] ; (80186c0 ) 8018576: f009 fa07 bl 8021988 801857a: e099 b.n 80186b0 /* pcb->state LISTEN not allowed here */ LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs", 801857c: 687b ldr r3, [r7, #4] 801857e: 7d1b ldrb r3, [r3, #20] 8018580: 2b01 cmp r3, #1 8018582: d106 bne.n 8018592 8018584: 4b4c ldr r3, [pc, #304] ; (80186b8 ) 8018586: f44f 7210 mov.w r2, #576 ; 0x240 801858a: 494e ldr r1, [pc, #312] ; (80186c4 ) 801858c: 484c ldr r0, [pc, #304] ; (80186c0 ) 801858e: f009 f9fb bl 8021988 pcb->state != LISTEN); /* Figure out on which TCP PCB list we are, and remove us. If we are in an active state, call the receive function associated with the PCB with a NULL argument, and send an RST to the remote end. */ if (pcb->state == TIME_WAIT) { 8018592: 687b ldr r3, [r7, #4] 8018594: 7d1b ldrb r3, [r3, #20] 8018596: 2b0a cmp r3, #10 8018598: d107 bne.n 80185aa tcp_pcb_remove(&tcp_tw_pcbs, pcb); 801859a: 6879 ldr r1, [r7, #4] 801859c: 484a ldr r0, [pc, #296] ; (80186c8 ) 801859e: f001 fa8b bl 8019ab8 tcp_free(pcb); 80185a2: 6878 ldr r0, [r7, #4] 80185a4: f7ff fd54 bl 8018050 80185a8: e082 b.n 80186b0 } else { int send_rst = 0; 80185aa: 2300 movs r3, #0 80185ac: 627b str r3, [r7, #36] ; 0x24 u16_t local_port = 0; 80185ae: 2300 movs r3, #0 80185b0: 847b strh r3, [r7, #34] ; 0x22 enum tcp_state last_state; seqno = pcb->snd_nxt; 80185b2: 687b ldr r3, [r7, #4] 80185b4: 6d1b ldr r3, [r3, #80] ; 0x50 80185b6: 61bb str r3, [r7, #24] ackno = pcb->rcv_nxt; 80185b8: 687b ldr r3, [r7, #4] 80185ba: 6a5b ldr r3, [r3, #36] ; 0x24 80185bc: 617b str r3, [r7, #20] #if LWIP_CALLBACK_API errf = pcb->errf; 80185be: 687b ldr r3, [r7, #4] 80185c0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 80185c4: 613b str r3, [r7, #16] #endif /* LWIP_CALLBACK_API */ errf_arg = pcb->callback_arg; 80185c6: 687b ldr r3, [r7, #4] 80185c8: 691b ldr r3, [r3, #16] 80185ca: 60fb str r3, [r7, #12] if (pcb->state == CLOSED) { 80185cc: 687b ldr r3, [r7, #4] 80185ce: 7d1b ldrb r3, [r3, #20] 80185d0: 2b00 cmp r3, #0 80185d2: d126 bne.n 8018622 if (pcb->local_port != 0) { 80185d4: 687b ldr r3, [r7, #4] 80185d6: 8adb ldrh r3, [r3, #22] 80185d8: 2b00 cmp r3, #0 80185da: d02e beq.n 801863a /* bound, not yet opened */ TCP_RMV(&tcp_bound_pcbs, pcb); 80185dc: 4b3b ldr r3, [pc, #236] ; (80186cc ) 80185de: 681b ldr r3, [r3, #0] 80185e0: 687a ldr r2, [r7, #4] 80185e2: 429a cmp r2, r3 80185e4: d105 bne.n 80185f2 80185e6: 4b39 ldr r3, [pc, #228] ; (80186cc ) 80185e8: 681b ldr r3, [r3, #0] 80185ea: 68db ldr r3, [r3, #12] 80185ec: 4a37 ldr r2, [pc, #220] ; (80186cc ) 80185ee: 6013 str r3, [r2, #0] 80185f0: e013 b.n 801861a 80185f2: 4b36 ldr r3, [pc, #216] ; (80186cc ) 80185f4: 681b ldr r3, [r3, #0] 80185f6: 61fb str r3, [r7, #28] 80185f8: e00c b.n 8018614 80185fa: 69fb ldr r3, [r7, #28] 80185fc: 68db ldr r3, [r3, #12] 80185fe: 687a ldr r2, [r7, #4] 8018600: 429a cmp r2, r3 8018602: d104 bne.n 801860e 8018604: 687b ldr r3, [r7, #4] 8018606: 68da ldr r2, [r3, #12] 8018608: 69fb ldr r3, [r7, #28] 801860a: 60da str r2, [r3, #12] 801860c: e005 b.n 801861a 801860e: 69fb ldr r3, [r7, #28] 8018610: 68db ldr r3, [r3, #12] 8018612: 61fb str r3, [r7, #28] 8018614: 69fb ldr r3, [r7, #28] 8018616: 2b00 cmp r3, #0 8018618: d1ef bne.n 80185fa 801861a: 687b ldr r3, [r7, #4] 801861c: 2200 movs r2, #0 801861e: 60da str r2, [r3, #12] 8018620: e00b b.n 801863a } } else { send_rst = reset; 8018622: 683b ldr r3, [r7, #0] 8018624: 627b str r3, [r7, #36] ; 0x24 local_port = pcb->local_port; 8018626: 687b ldr r3, [r7, #4] 8018628: 8adb ldrh r3, [r3, #22] 801862a: 847b strh r3, [r7, #34] ; 0x22 TCP_PCB_REMOVE_ACTIVE(pcb); 801862c: 6879 ldr r1, [r7, #4] 801862e: 4828 ldr r0, [pc, #160] ; (80186d0 ) 8018630: f001 fa42 bl 8019ab8 8018634: 4b27 ldr r3, [pc, #156] ; (80186d4 ) 8018636: 2201 movs r2, #1 8018638: 701a strb r2, [r3, #0] } if (pcb->unacked != NULL) { 801863a: 687b ldr r3, [r7, #4] 801863c: 6f1b ldr r3, [r3, #112] ; 0x70 801863e: 2b00 cmp r3, #0 8018640: d004 beq.n 801864c tcp_segs_free(pcb->unacked); 8018642: 687b ldr r3, [r7, #4] 8018644: 6f1b ldr r3, [r3, #112] ; 0x70 8018646: 4618 mov r0, r3 8018648: f000 ff16 bl 8019478 } if (pcb->unsent != NULL) { 801864c: 687b ldr r3, [r7, #4] 801864e: 6edb ldr r3, [r3, #108] ; 0x6c 8018650: 2b00 cmp r3, #0 8018652: d004 beq.n 801865e tcp_segs_free(pcb->unsent); 8018654: 687b ldr r3, [r7, #4] 8018656: 6edb ldr r3, [r3, #108] ; 0x6c 8018658: 4618 mov r0, r3 801865a: f000 ff0d bl 8019478 } #if TCP_QUEUE_OOSEQ if (pcb->ooseq != NULL) { 801865e: 687b ldr r3, [r7, #4] 8018660: 6f5b ldr r3, [r3, #116] ; 0x74 8018662: 2b00 cmp r3, #0 8018664: d004 beq.n 8018670 tcp_segs_free(pcb->ooseq); 8018666: 687b ldr r3, [r7, #4] 8018668: 6f5b ldr r3, [r3, #116] ; 0x74 801866a: 4618 mov r0, r3 801866c: f000 ff04 bl 8019478 } #endif /* TCP_QUEUE_OOSEQ */ tcp_backlog_accepted(pcb); if (send_rst) { 8018670: 6a7b ldr r3, [r7, #36] ; 0x24 8018672: 2b00 cmp r3, #0 8018674: d00e beq.n 8018694 LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n")); tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port); 8018676: 6879 ldr r1, [r7, #4] 8018678: 687b ldr r3, [r7, #4] 801867a: 3304 adds r3, #4 801867c: 687a ldr r2, [r7, #4] 801867e: 8b12 ldrh r2, [r2, #24] 8018680: 9202 str r2, [sp, #8] 8018682: 8c7a ldrh r2, [r7, #34] ; 0x22 8018684: 9201 str r2, [sp, #4] 8018686: 9300 str r3, [sp, #0] 8018688: 460b mov r3, r1 801868a: 697a ldr r2, [r7, #20] 801868c: 69b9 ldr r1, [r7, #24] 801868e: 6878 ldr r0, [r7, #4] 8018690: f005 fc54 bl 801df3c } last_state = pcb->state; 8018694: 687b ldr r3, [r7, #4] 8018696: 7d1b ldrb r3, [r3, #20] 8018698: 72fb strb r3, [r7, #11] tcp_free(pcb); 801869a: 6878 ldr r0, [r7, #4] 801869c: f7ff fcd8 bl 8018050 TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT); 80186a0: 693b ldr r3, [r7, #16] 80186a2: 2b00 cmp r3, #0 80186a4: d004 beq.n 80186b0 80186a6: 693b ldr r3, [r7, #16] 80186a8: f06f 010c mvn.w r1, #12 80186ac: 68f8 ldr r0, [r7, #12] 80186ae: 4798 blx r3 } } 80186b0: 3728 adds r7, #40 ; 0x28 80186b2: 46bd mov sp, r7 80186b4: bd80 pop {r7, pc} 80186b6: bf00 nop 80186b8: 08024ba8 .word 0x08024ba8 80186bc: 08024cec .word 0x08024cec 80186c0: 08024bec .word 0x08024bec 80186c4: 08024d08 .word 0x08024d08 80186c8: 2401a490 .word 0x2401a490 80186cc: 2401a484 .word 0x2401a484 80186d0: 2401a48c .word 0x2401a48c 80186d4: 2401a494 .word 0x2401a494 080186d8 : * * @param pcb the tcp pcb to abort */ void tcp_abort(struct tcp_pcb *pcb) { 80186d8: b580 push {r7, lr} 80186da: b082 sub sp, #8 80186dc: af00 add r7, sp, #0 80186de: 6078 str r0, [r7, #4] tcp_abandon(pcb, 1); 80186e0: 2101 movs r1, #1 80186e2: 6878 ldr r0, [r7, #4] 80186e4: f7ff ff3a bl 801855c } 80186e8: bf00 nop 80186ea: 3708 adds r7, #8 80186ec: 46bd mov sp, r7 80186ee: bd80 pop {r7, pc} 080186f0 : * ERR_VAL if bind failed because the PCB is not in a valid state * ERR_OK if bound */ err_t tcp_bind(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) { 80186f0: b580 push {r7, lr} 80186f2: b088 sub sp, #32 80186f4: af00 add r7, sp, #0 80186f6: 60f8 str r0, [r7, #12] 80186f8: 60b9 str r1, [r7, #8] 80186fa: 4613 mov r3, r2 80186fc: 80fb strh r3, [r7, #6] int i; int max_pcb_list = NUM_TCP_PCB_LISTS; 80186fe: 2304 movs r3, #4 8018700: 617b str r3, [r7, #20] LWIP_ASSERT_CORE_LOCKED(); #if LWIP_IPV4 /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ if (ipaddr == NULL) { 8018702: 68bb ldr r3, [r7, #8] 8018704: 2b00 cmp r3, #0 8018706: d101 bne.n 801870c ipaddr = IP4_ADDR_ANY; 8018708: 4b3e ldr r3, [pc, #248] ; (8018804 ) 801870a: 60bb str r3, [r7, #8] } #else /* LWIP_IPV4 */ LWIP_ERROR("tcp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG); #endif /* LWIP_IPV4 */ LWIP_ERROR("tcp_bind: invalid pcb", pcb != NULL, return ERR_ARG); 801870c: 68fb ldr r3, [r7, #12] 801870e: 2b00 cmp r3, #0 8018710: d109 bne.n 8018726 8018712: 4b3d ldr r3, [pc, #244] ; (8018808 ) 8018714: f240 22a9 movw r2, #681 ; 0x2a9 8018718: 493c ldr r1, [pc, #240] ; (801880c ) 801871a: 483d ldr r0, [pc, #244] ; (8018810 ) 801871c: f009 f934 bl 8021988 8018720: f06f 030f mvn.w r3, #15 8018724: e06a b.n 80187fc LWIP_ERROR("tcp_bind: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_VAL); 8018726: 68fb ldr r3, [r7, #12] 8018728: 7d1b ldrb r3, [r3, #20] 801872a: 2b00 cmp r3, #0 801872c: d009 beq.n 8018742 801872e: 4b36 ldr r3, [pc, #216] ; (8018808 ) 8018730: f240 22ab movw r2, #683 ; 0x2ab 8018734: 4937 ldr r1, [pc, #220] ; (8018814 ) 8018736: 4836 ldr r0, [pc, #216] ; (8018810 ) 8018738: f009 f926 bl 8021988 801873c: f06f 0305 mvn.w r3, #5 8018740: e05c b.n 80187fc ip6_addr_select_zone(ip_2_ip6(&zoned_ipaddr), ip_2_ip6(&zoned_ipaddr)); ipaddr = &zoned_ipaddr; } #endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ if (port == 0) { 8018742: 88fb ldrh r3, [r7, #6] 8018744: 2b00 cmp r3, #0 8018746: d109 bne.n 801875c port = tcp_new_port(); 8018748: f000 f916 bl 8018978 801874c: 4603 mov r3, r0 801874e: 80fb strh r3, [r7, #6] if (port == 0) { 8018750: 88fb ldrh r3, [r7, #6] 8018752: 2b00 cmp r3, #0 8018754: d135 bne.n 80187c2 return ERR_BUF; 8018756: f06f 0301 mvn.w r3, #1 801875a: e04f b.n 80187fc } } else { /* Check if the address already is in use (on all lists) */ for (i = 0; i < max_pcb_list; i++) { 801875c: 2300 movs r3, #0 801875e: 61fb str r3, [r7, #28] 8018760: e02b b.n 80187ba for (cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) { 8018762: 4a2d ldr r2, [pc, #180] ; (8018818 ) 8018764: 69fb ldr r3, [r7, #28] 8018766: f852 3023 ldr.w r3, [r2, r3, lsl #2] 801876a: 681b ldr r3, [r3, #0] 801876c: 61bb str r3, [r7, #24] 801876e: e01e b.n 80187ae if (cpcb->local_port == port) { 8018770: 69bb ldr r3, [r7, #24] 8018772: 8adb ldrh r3, [r3, #22] 8018774: 88fa ldrh r2, [r7, #6] 8018776: 429a cmp r2, r3 8018778: d116 bne.n 80187a8 !ip_get_option(cpcb, SOF_REUSEADDR)) #endif /* SO_REUSE */ { /* @todo: check accept_any_ip_version */ if ((IP_IS_V6(ipaddr) == IP_IS_V6_VAL(cpcb->local_ip)) && (ip_addr_isany(&cpcb->local_ip) || 801877a: 69bb ldr r3, [r7, #24] if ((IP_IS_V6(ipaddr) == IP_IS_V6_VAL(cpcb->local_ip)) && 801877c: 2b00 cmp r3, #0 801877e: d010 beq.n 80187a2 (ip_addr_isany(&cpcb->local_ip) || 8018780: 69bb ldr r3, [r7, #24] 8018782: 681b ldr r3, [r3, #0] 8018784: 2b00 cmp r3, #0 8018786: d00c beq.n 80187a2 8018788: 68bb ldr r3, [r7, #8] 801878a: 2b00 cmp r3, #0 801878c: d009 beq.n 80187a2 ip_addr_isany(ipaddr) || 801878e: 68bb ldr r3, [r7, #8] 8018790: 681b ldr r3, [r3, #0] 8018792: 2b00 cmp r3, #0 8018794: d005 beq.n 80187a2 ip_addr_cmp(&cpcb->local_ip, ipaddr))) { 8018796: 69bb ldr r3, [r7, #24] 8018798: 681a ldr r2, [r3, #0] 801879a: 68bb ldr r3, [r7, #8] 801879c: 681b ldr r3, [r3, #0] if ((IP_IS_V6(ipaddr) == IP_IS_V6_VAL(cpcb->local_ip)) && 801879e: 429a cmp r2, r3 80187a0: d102 bne.n 80187a8 return ERR_USE; 80187a2: f06f 0307 mvn.w r3, #7 80187a6: e029 b.n 80187fc for (cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) { 80187a8: 69bb ldr r3, [r7, #24] 80187aa: 68db ldr r3, [r3, #12] 80187ac: 61bb str r3, [r7, #24] 80187ae: 69bb ldr r3, [r7, #24] 80187b0: 2b00 cmp r3, #0 80187b2: d1dd bne.n 8018770 for (i = 0; i < max_pcb_list; i++) { 80187b4: 69fb ldr r3, [r7, #28] 80187b6: 3301 adds r3, #1 80187b8: 61fb str r3, [r7, #28] 80187ba: 69fa ldr r2, [r7, #28] 80187bc: 697b ldr r3, [r7, #20] 80187be: 429a cmp r2, r3 80187c0: dbcf blt.n 8018762 } } } } if (!ip_addr_isany(ipaddr) 80187c2: 68bb ldr r3, [r7, #8] 80187c4: 2b00 cmp r3, #0 80187c6: d00c beq.n 80187e2 80187c8: 68bb ldr r3, [r7, #8] 80187ca: 681b ldr r3, [r3, #0] 80187cc: 2b00 cmp r3, #0 80187ce: d008 beq.n 80187e2 #if LWIP_IPV4 && LWIP_IPV6 || (IP_GET_TYPE(ipaddr) != IP_GET_TYPE(&pcb->local_ip)) #endif /* LWIP_IPV4 && LWIP_IPV6 */ ) { ip_addr_set(&pcb->local_ip, ipaddr); 80187d0: 68bb ldr r3, [r7, #8] 80187d2: 2b00 cmp r3, #0 80187d4: d002 beq.n 80187dc 80187d6: 68bb ldr r3, [r7, #8] 80187d8: 681b ldr r3, [r3, #0] 80187da: e000 b.n 80187de 80187dc: 2300 movs r3, #0 80187de: 68fa ldr r2, [r7, #12] 80187e0: 6013 str r3, [r2, #0] } pcb->local_port = port; 80187e2: 68fb ldr r3, [r7, #12] 80187e4: 88fa ldrh r2, [r7, #6] 80187e6: 82da strh r2, [r3, #22] TCP_REG(&tcp_bound_pcbs, pcb); 80187e8: 4b0c ldr r3, [pc, #48] ; (801881c ) 80187ea: 681a ldr r2, [r3, #0] 80187ec: 68fb ldr r3, [r7, #12] 80187ee: 60da str r2, [r3, #12] 80187f0: 4a0a ldr r2, [pc, #40] ; (801881c ) 80187f2: 68fb ldr r3, [r7, #12] 80187f4: 6013 str r3, [r2, #0] 80187f6: f005 fd63 bl 801e2c0 LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); return ERR_OK; 80187fa: 2300 movs r3, #0 } 80187fc: 4618 mov r0, r3 80187fe: 3720 adds r7, #32 8018800: 46bd mov sp, r7 8018802: bd80 pop {r7, pc} 8018804: 08026cec .word 0x08026cec 8018808: 08024ba8 .word 0x08024ba8 801880c: 08024d3c .word 0x08024d3c 8018810: 08024bec .word 0x08024bec 8018814: 08024d54 .word 0x08024d54 8018818: 08026cc4 .word 0x08026cc4 801881c: 2401a484 .word 0x2401a484 08018820 : * Returns how much extra window would be advertised if we sent an * update now. */ u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb) { 8018820: b580 push {r7, lr} 8018822: b084 sub sp, #16 8018824: af00 add r7, sp, #0 8018826: 6078 str r0, [r7, #4] u32_t new_right_edge; LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL); 8018828: 687b ldr r3, [r7, #4] 801882a: 2b00 cmp r3, #0 801882c: d106 bne.n 801883c 801882e: 4b25 ldr r3, [pc, #148] ; (80188c4 ) 8018830: f240 32a6 movw r2, #934 ; 0x3a6 8018834: 4924 ldr r1, [pc, #144] ; (80188c8 ) 8018836: 4825 ldr r0, [pc, #148] ; (80188cc ) 8018838: f009 f8a6 bl 8021988 new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd; 801883c: 687b ldr r3, [r7, #4] 801883e: 6a5b ldr r3, [r3, #36] ; 0x24 8018840: 687a ldr r2, [r7, #4] 8018842: 8d12 ldrh r2, [r2, #40] ; 0x28 8018844: 4413 add r3, r2 8018846: 60fb str r3, [r7, #12] if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) { 8018848: 687b ldr r3, [r7, #4] 801884a: 6adb ldr r3, [r3, #44] ; 0x2c 801884c: 687a ldr r2, [r7, #4] 801884e: 8e52 ldrh r2, [r2, #50] ; 0x32 8018850: f640 3168 movw r1, #2920 ; 0xb68 8018854: 428a cmp r2, r1 8018856: bf28 it cs 8018858: 460a movcs r2, r1 801885a: b292 uxth r2, r2 801885c: 4413 add r3, r2 801885e: 68fa ldr r2, [r7, #12] 8018860: 1ad3 subs r3, r2, r3 8018862: 2b00 cmp r3, #0 8018864: db08 blt.n 8018878 /* we can advertise more window */ pcb->rcv_ann_wnd = pcb->rcv_wnd; 8018866: 687b ldr r3, [r7, #4] 8018868: 8d1a ldrh r2, [r3, #40] ; 0x28 801886a: 687b ldr r3, [r7, #4] 801886c: 855a strh r2, [r3, #42] ; 0x2a return new_right_edge - pcb->rcv_ann_right_edge; 801886e: 687b ldr r3, [r7, #4] 8018870: 6adb ldr r3, [r3, #44] ; 0x2c 8018872: 68fa ldr r2, [r7, #12] 8018874: 1ad3 subs r3, r2, r3 8018876: e020 b.n 80188ba } else { if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) { 8018878: 687b ldr r3, [r7, #4] 801887a: 6a5a ldr r2, [r3, #36] ; 0x24 801887c: 687b ldr r3, [r7, #4] 801887e: 6adb ldr r3, [r3, #44] ; 0x2c 8018880: 1ad3 subs r3, r2, r3 8018882: 2b00 cmp r3, #0 8018884: dd03 ble.n 801888e /* Can happen due to other end sending out of advertised window, * but within actual available (but not yet advertised) window */ pcb->rcv_ann_wnd = 0; 8018886: 687b ldr r3, [r7, #4] 8018888: 2200 movs r2, #0 801888a: 855a strh r2, [r3, #42] ; 0x2a 801888c: e014 b.n 80188b8 } else { /* keep the right edge of window constant */ u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt; 801888e: 687b ldr r3, [r7, #4] 8018890: 6ada ldr r2, [r3, #44] ; 0x2c 8018892: 687b ldr r3, [r7, #4] 8018894: 6a5b ldr r3, [r3, #36] ; 0x24 8018896: 1ad3 subs r3, r2, r3 8018898: 60bb str r3, [r7, #8] #if !LWIP_WND_SCALE LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff); 801889a: 68bb ldr r3, [r7, #8] 801889c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80188a0: d306 bcc.n 80188b0 80188a2: 4b08 ldr r3, [pc, #32] ; (80188c4 ) 80188a4: f240 32b6 movw r2, #950 ; 0x3b6 80188a8: 4909 ldr r1, [pc, #36] ; (80188d0 ) 80188aa: 4808 ldr r0, [pc, #32] ; (80188cc ) 80188ac: f009 f86c bl 8021988 #endif pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd; 80188b0: 68bb ldr r3, [r7, #8] 80188b2: b29a uxth r2, r3 80188b4: 687b ldr r3, [r7, #4] 80188b6: 855a strh r2, [r3, #42] ; 0x2a } return 0; 80188b8: 2300 movs r3, #0 } } 80188ba: 4618 mov r0, r3 80188bc: 3710 adds r7, #16 80188be: 46bd mov sp, r7 80188c0: bd80 pop {r7, pc} 80188c2: bf00 nop 80188c4: 08024ba8 .word 0x08024ba8 80188c8: 08024e04 .word 0x08024e04 80188cc: 08024bec .word 0x08024bec 80188d0: 08024e28 .word 0x08024e28 080188d4 : * @param pcb the tcp_pcb for which data is read * @param len the amount of bytes that have been read by the application */ void tcp_recved(struct tcp_pcb *pcb, u16_t len) { 80188d4: b580 push {r7, lr} 80188d6: b084 sub sp, #16 80188d8: af00 add r7, sp, #0 80188da: 6078 str r0, [r7, #4] 80188dc: 460b mov r3, r1 80188de: 807b strh r3, [r7, #2] u32_t wnd_inflation; tcpwnd_size_t rcv_wnd; LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return); 80188e0: 687b ldr r3, [r7, #4] 80188e2: 2b00 cmp r3, #0 80188e4: d107 bne.n 80188f6 80188e6: 4b20 ldr r3, [pc, #128] ; (8018968 ) 80188e8: f240 32cf movw r2, #975 ; 0x3cf 80188ec: 491f ldr r1, [pc, #124] ; (801896c ) 80188ee: 4820 ldr r0, [pc, #128] ; (8018970 ) 80188f0: f009 f84a bl 8021988 80188f4: e034 b.n 8018960 /* pcb->state LISTEN not allowed here */ LWIP_ASSERT("don't call tcp_recved for listen-pcbs", 80188f6: 687b ldr r3, [r7, #4] 80188f8: 7d1b ldrb r3, [r3, #20] 80188fa: 2b01 cmp r3, #1 80188fc: d106 bne.n 801890c 80188fe: 4b1a ldr r3, [pc, #104] ; (8018968 ) 8018900: f240 32d2 movw r2, #978 ; 0x3d2 8018904: 491b ldr r1, [pc, #108] ; (8018974 ) 8018906: 481a ldr r0, [pc, #104] ; (8018970 ) 8018908: f009 f83e bl 8021988 pcb->state != LISTEN); rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len); 801890c: 687b ldr r3, [r7, #4] 801890e: 8d1a ldrh r2, [r3, #40] ; 0x28 8018910: 887b ldrh r3, [r7, #2] 8018912: 4413 add r3, r2 8018914: 81fb strh r3, [r7, #14] if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) { 8018916: 89fb ldrh r3, [r7, #14] 8018918: f241 62d0 movw r2, #5840 ; 0x16d0 801891c: 4293 cmp r3, r2 801891e: d804 bhi.n 801892a 8018920: 687b ldr r3, [r7, #4] 8018922: 8d1b ldrh r3, [r3, #40] ; 0x28 8018924: 89fa ldrh r2, [r7, #14] 8018926: 429a cmp r2, r3 8018928: d204 bcs.n 8018934 /* window got too big or tcpwnd_size_t overflow */ LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n")); pcb->rcv_wnd = TCP_WND_MAX(pcb); 801892a: 687b ldr r3, [r7, #4] 801892c: f241 62d0 movw r2, #5840 ; 0x16d0 8018930: 851a strh r2, [r3, #40] ; 0x28 8018932: e002 b.n 801893a } else { pcb->rcv_wnd = rcv_wnd; 8018934: 687b ldr r3, [r7, #4] 8018936: 89fa ldrh r2, [r7, #14] 8018938: 851a strh r2, [r3, #40] ; 0x28 } wnd_inflation = tcp_update_rcv_ann_wnd(pcb); 801893a: 6878 ldr r0, [r7, #4] 801893c: f7ff ff70 bl 8018820 8018940: 60b8 str r0, [r7, #8] /* If the change in the right edge of window is significant (default * watermark is TCP_WND/4), then send an explicit update now. * Otherwise wait for a packet to be sent in the normal course of * events (or more window to be available later) */ if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) { 8018942: 68bb ldr r3, [r7, #8] 8018944: f240 52b3 movw r2, #1459 ; 0x5b3 8018948: 4293 cmp r3, r2 801894a: d909 bls.n 8018960 tcp_ack_now(pcb); 801894c: 687b ldr r3, [r7, #4] 801894e: 8b5b ldrh r3, [r3, #26] 8018950: f043 0302 orr.w r3, r3, #2 8018954: b29a uxth r2, r3 8018956: 687b ldr r3, [r7, #4] 8018958: 835a strh r2, [r3, #26] tcp_output(pcb); 801895a: 6878 ldr r0, [r7, #4] 801895c: f004 fd2e bl 801d3bc } LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n", len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd))); } 8018960: 3710 adds r7, #16 8018962: 46bd mov sp, r7 8018964: bd80 pop {r7, pc} 8018966: bf00 nop 8018968: 08024ba8 .word 0x08024ba8 801896c: 08024e44 .word 0x08024e44 8018970: 08024bec .word 0x08024bec 8018974: 08024e5c .word 0x08024e5c 08018978 : * * @return a new (free) local TCP port number */ static u16_t tcp_new_port(void) { 8018978: b480 push {r7} 801897a: b083 sub sp, #12 801897c: af00 add r7, sp, #0 u8_t i; u16_t n = 0; 801897e: 2300 movs r3, #0 8018980: 80bb strh r3, [r7, #4] struct tcp_pcb *pcb; again: tcp_port++; 8018982: 4b1e ldr r3, [pc, #120] ; (80189fc ) 8018984: 881b ldrh r3, [r3, #0] 8018986: 3301 adds r3, #1 8018988: b29a uxth r2, r3 801898a: 4b1c ldr r3, [pc, #112] ; (80189fc ) 801898c: 801a strh r2, [r3, #0] if (tcp_port == TCP_LOCAL_PORT_RANGE_END) { 801898e: 4b1b ldr r3, [pc, #108] ; (80189fc ) 8018990: 881b ldrh r3, [r3, #0] 8018992: f64f 72ff movw r2, #65535 ; 0xffff 8018996: 4293 cmp r3, r2 8018998: d103 bne.n 80189a2 tcp_port = TCP_LOCAL_PORT_RANGE_START; 801899a: 4b18 ldr r3, [pc, #96] ; (80189fc ) 801899c: f44f 4240 mov.w r2, #49152 ; 0xc000 80189a0: 801a strh r2, [r3, #0] } /* Check all PCB lists. */ for (i = 0; i < NUM_TCP_PCB_LISTS; i++) { 80189a2: 2300 movs r3, #0 80189a4: 71fb strb r3, [r7, #7] 80189a6: e01e b.n 80189e6 for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) { 80189a8: 79fb ldrb r3, [r7, #7] 80189aa: 4a15 ldr r2, [pc, #84] ; (8018a00 ) 80189ac: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80189b0: 681b ldr r3, [r3, #0] 80189b2: 603b str r3, [r7, #0] 80189b4: e011 b.n 80189da if (pcb->local_port == tcp_port) { 80189b6: 683b ldr r3, [r7, #0] 80189b8: 8ada ldrh r2, [r3, #22] 80189ba: 4b10 ldr r3, [pc, #64] ; (80189fc ) 80189bc: 881b ldrh r3, [r3, #0] 80189be: 429a cmp r2, r3 80189c0: d108 bne.n 80189d4 n++; 80189c2: 88bb ldrh r3, [r7, #4] 80189c4: 3301 adds r3, #1 80189c6: 80bb strh r3, [r7, #4] if (n > (TCP_LOCAL_PORT_RANGE_END - TCP_LOCAL_PORT_RANGE_START)) { 80189c8: 88bb ldrh r3, [r7, #4] 80189ca: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 80189ce: d3d8 bcc.n 8018982 return 0; 80189d0: 2300 movs r3, #0 80189d2: e00d b.n 80189f0 for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) { 80189d4: 683b ldr r3, [r7, #0] 80189d6: 68db ldr r3, [r3, #12] 80189d8: 603b str r3, [r7, #0] 80189da: 683b ldr r3, [r7, #0] 80189dc: 2b00 cmp r3, #0 80189de: d1ea bne.n 80189b6 for (i = 0; i < NUM_TCP_PCB_LISTS; i++) { 80189e0: 79fb ldrb r3, [r7, #7] 80189e2: 3301 adds r3, #1 80189e4: 71fb strb r3, [r7, #7] 80189e6: 79fb ldrb r3, [r7, #7] 80189e8: 2b03 cmp r3, #3 80189ea: d9dd bls.n 80189a8 } goto again; } } } return tcp_port; 80189ec: 4b03 ldr r3, [pc, #12] ; (80189fc ) 80189ee: 881b ldrh r3, [r3, #0] } 80189f0: 4618 mov r0, r3 80189f2: 370c adds r7, #12 80189f4: 46bd mov sp, r7 80189f6: f85d 7b04 ldr.w r7, [sp], #4 80189fa: 4770 bx lr 80189fc: 2400003c .word 0x2400003c 8018a00: 08026cc4 .word 0x08026cc4 08018a04 : * other err_t values if connect request couldn't be sent */ err_t tcp_connect(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port, tcp_connected_fn connected) { 8018a04: b580 push {r7, lr} 8018a06: b08a sub sp, #40 ; 0x28 8018a08: af00 add r7, sp, #0 8018a0a: 60f8 str r0, [r7, #12] 8018a0c: 60b9 str r1, [r7, #8] 8018a0e: 603b str r3, [r7, #0] 8018a10: 4613 mov r3, r2 8018a12: 80fb strh r3, [r7, #6] struct netif *netif = NULL; 8018a14: 2300 movs r3, #0 8018a16: 627b str r3, [r7, #36] ; 0x24 u32_t iss; u16_t old_local_port; LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("tcp_connect: invalid pcb", pcb != NULL, return ERR_ARG); 8018a18: 68fb ldr r3, [r7, #12] 8018a1a: 2b00 cmp r3, #0 8018a1c: d109 bne.n 8018a32 8018a1e: 4b7d ldr r3, [pc, #500] ; (8018c14 ) 8018a20: f240 4235 movw r2, #1077 ; 0x435 8018a24: 497c ldr r1, [pc, #496] ; (8018c18 ) 8018a26: 487d ldr r0, [pc, #500] ; (8018c1c ) 8018a28: f008 ffae bl 8021988 8018a2c: f06f 030f mvn.w r3, #15 8018a30: e0ec b.n 8018c0c LWIP_ERROR("tcp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG); 8018a32: 68bb ldr r3, [r7, #8] 8018a34: 2b00 cmp r3, #0 8018a36: d109 bne.n 8018a4c 8018a38: 4b76 ldr r3, [pc, #472] ; (8018c14 ) 8018a3a: f240 4236 movw r2, #1078 ; 0x436 8018a3e: 4978 ldr r1, [pc, #480] ; (8018c20 ) 8018a40: 4876 ldr r0, [pc, #472] ; (8018c1c ) 8018a42: f008 ffa1 bl 8021988 8018a46: f06f 030f mvn.w r3, #15 8018a4a: e0df b.n 8018c0c LWIP_ERROR("tcp_connect: can only connect from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN); 8018a4c: 68fb ldr r3, [r7, #12] 8018a4e: 7d1b ldrb r3, [r3, #20] 8018a50: 2b00 cmp r3, #0 8018a52: d009 beq.n 8018a68 8018a54: 4b6f ldr r3, [pc, #444] ; (8018c14 ) 8018a56: f44f 6287 mov.w r2, #1080 ; 0x438 8018a5a: 4972 ldr r1, [pc, #456] ; (8018c24 ) 8018a5c: 486f ldr r0, [pc, #444] ; (8018c1c ) 8018a5e: f008 ff93 bl 8021988 8018a62: f06f 0309 mvn.w r3, #9 8018a66: e0d1 b.n 8018c0c LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); ip_addr_set(&pcb->remote_ip, ipaddr); 8018a68: 68bb ldr r3, [r7, #8] 8018a6a: 2b00 cmp r3, #0 8018a6c: d002 beq.n 8018a74 8018a6e: 68bb ldr r3, [r7, #8] 8018a70: 681b ldr r3, [r3, #0] 8018a72: e000 b.n 8018a76 8018a74: 2300 movs r3, #0 8018a76: 68fa ldr r2, [r7, #12] 8018a78: 6053 str r3, [r2, #4] pcb->remote_port = port; 8018a7a: 68fb ldr r3, [r7, #12] 8018a7c: 88fa ldrh r2, [r7, #6] 8018a7e: 831a strh r2, [r3, #24] if (pcb->netif_idx != NETIF_NO_INDEX) { 8018a80: 68fb ldr r3, [r7, #12] 8018a82: 7a1b ldrb r3, [r3, #8] 8018a84: 2b00 cmp r3, #0 8018a86: d006 beq.n 8018a96 netif = netif_get_by_index(pcb->netif_idx); 8018a88: 68fb ldr r3, [r7, #12] 8018a8a: 7a1b ldrb r3, [r3, #8] 8018a8c: 4618 mov r0, r3 8018a8e: f7fe fca1 bl 80173d4 8018a92: 6278 str r0, [r7, #36] ; 0x24 8018a94: e005 b.n 8018aa2 } else { /* check if we have a route to the remote host */ netif = ip_route(&pcb->local_ip, &pcb->remote_ip); 8018a96: 68fb ldr r3, [r7, #12] 8018a98: 3304 adds r3, #4 8018a9a: 4618 mov r0, r3 8018a9c: f007 fa2a bl 801fef4 8018aa0: 6278 str r0, [r7, #36] ; 0x24 } if (netif == NULL) { 8018aa2: 6a7b ldr r3, [r7, #36] ; 0x24 8018aa4: 2b00 cmp r3, #0 8018aa6: d102 bne.n 8018aae /* Don't even try to send a SYN packet if we have no route since that will fail. */ return ERR_RTE; 8018aa8: f06f 0303 mvn.w r3, #3 8018aac: e0ae b.n 8018c0c } /* check if local IP has been assigned to pcb, if not, get one */ if (ip_addr_isany(&pcb->local_ip)) { 8018aae: 68fb ldr r3, [r7, #12] 8018ab0: 2b00 cmp r3, #0 8018ab2: d003 beq.n 8018abc 8018ab4: 68fb ldr r3, [r7, #12] 8018ab6: 681b ldr r3, [r3, #0] 8018ab8: 2b00 cmp r3, #0 8018aba: d111 bne.n 8018ae0 const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, ipaddr); 8018abc: 6a7b ldr r3, [r7, #36] ; 0x24 8018abe: 2b00 cmp r3, #0 8018ac0: d002 beq.n 8018ac8 8018ac2: 6a7b ldr r3, [r7, #36] ; 0x24 8018ac4: 3304 adds r3, #4 8018ac6: e000 b.n 8018aca 8018ac8: 2300 movs r3, #0 8018aca: 61fb str r3, [r7, #28] if (local_ip == NULL) { 8018acc: 69fb ldr r3, [r7, #28] 8018ace: 2b00 cmp r3, #0 8018ad0: d102 bne.n 8018ad8 return ERR_RTE; 8018ad2: f06f 0303 mvn.w r3, #3 8018ad6: e099 b.n 8018c0c } ip_addr_copy(pcb->local_ip, *local_ip); 8018ad8: 69fb ldr r3, [r7, #28] 8018ada: 681a ldr r2, [r3, #0] 8018adc: 68fb ldr r3, [r7, #12] 8018ade: 601a str r2, [r3, #0] ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST)) { ip6_addr_assign_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST, netif); } #endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ old_local_port = pcb->local_port; 8018ae0: 68fb ldr r3, [r7, #12] 8018ae2: 8adb ldrh r3, [r3, #22] 8018ae4: 837b strh r3, [r7, #26] if (pcb->local_port == 0) { 8018ae6: 68fb ldr r3, [r7, #12] 8018ae8: 8adb ldrh r3, [r3, #22] 8018aea: 2b00 cmp r3, #0 8018aec: d10c bne.n 8018b08 pcb->local_port = tcp_new_port(); 8018aee: f7ff ff43 bl 8018978 8018af2: 4603 mov r3, r0 8018af4: 461a mov r2, r3 8018af6: 68fb ldr r3, [r7, #12] 8018af8: 82da strh r2, [r3, #22] if (pcb->local_port == 0) { 8018afa: 68fb ldr r3, [r7, #12] 8018afc: 8adb ldrh r3, [r3, #22] 8018afe: 2b00 cmp r3, #0 8018b00: d102 bne.n 8018b08 return ERR_BUF; 8018b02: f06f 0301 mvn.w r3, #1 8018b06: e081 b.n 8018c0c } } #endif /* SO_REUSE */ } iss = tcp_next_iss(pcb); 8018b08: 68f8 ldr r0, [r7, #12] 8018b0a: f001 f869 bl 8019be0 8018b0e: 6178 str r0, [r7, #20] pcb->rcv_nxt = 0; 8018b10: 68fb ldr r3, [r7, #12] 8018b12: 2200 movs r2, #0 8018b14: 625a str r2, [r3, #36] ; 0x24 pcb->snd_nxt = iss; 8018b16: 68fb ldr r3, [r7, #12] 8018b18: 697a ldr r2, [r7, #20] 8018b1a: 651a str r2, [r3, #80] ; 0x50 pcb->lastack = iss - 1; 8018b1c: 697b ldr r3, [r7, #20] 8018b1e: 1e5a subs r2, r3, #1 8018b20: 68fb ldr r3, [r7, #12] 8018b22: 645a str r2, [r3, #68] ; 0x44 pcb->snd_wl2 = iss - 1; 8018b24: 697b ldr r3, [r7, #20] 8018b26: 1e5a subs r2, r3, #1 8018b28: 68fb ldr r3, [r7, #12] 8018b2a: 659a str r2, [r3, #88] ; 0x58 pcb->snd_lbb = iss - 1; 8018b2c: 697b ldr r3, [r7, #20] 8018b2e: 1e5a subs r2, r3, #1 8018b30: 68fb ldr r3, [r7, #12] 8018b32: 65da str r2, [r3, #92] ; 0x5c /* Start with a window that does not need scaling. When window scaling is enabled and used, the window is enlarged when both sides agree on scaling. */ pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND); 8018b34: 68fb ldr r3, [r7, #12] 8018b36: f241 62d0 movw r2, #5840 ; 0x16d0 8018b3a: 855a strh r2, [r3, #42] ; 0x2a 8018b3c: 68fb ldr r3, [r7, #12] 8018b3e: 8d5a ldrh r2, [r3, #42] ; 0x2a 8018b40: 68fb ldr r3, [r7, #12] 8018b42: 851a strh r2, [r3, #40] ; 0x28 pcb->rcv_ann_right_edge = pcb->rcv_nxt; 8018b44: 68fb ldr r3, [r7, #12] 8018b46: 6a5a ldr r2, [r3, #36] ; 0x24 8018b48: 68fb ldr r3, [r7, #12] 8018b4a: 62da str r2, [r3, #44] ; 0x2c pcb->snd_wnd = TCP_WND; 8018b4c: 68fb ldr r3, [r7, #12] 8018b4e: f241 62d0 movw r2, #5840 ; 0x16d0 8018b52: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 /* As initial send MSS, we use TCP_MSS but limit it to 536. The send MSS is updated when an MSS option is received. */ pcb->mss = INITIAL_MSS; 8018b56: 68fb ldr r3, [r7, #12] 8018b58: f44f 7206 mov.w r2, #536 ; 0x218 8018b5c: 865a strh r2, [r3, #50] ; 0x32 #if TCP_CALCULATE_EFF_SEND_MSS pcb->mss = tcp_eff_send_mss_netif(pcb->mss, netif, &pcb->remote_ip); 8018b5e: 68fb ldr r3, [r7, #12] 8018b60: 8e58 ldrh r0, [r3, #50] ; 0x32 8018b62: 68fb ldr r3, [r7, #12] 8018b64: 3304 adds r3, #4 8018b66: 461a mov r2, r3 8018b68: 6a79 ldr r1, [r7, #36] ; 0x24 8018b6a: f001 f85f bl 8019c2c 8018b6e: 4603 mov r3, r0 8018b70: 461a mov r2, r3 8018b72: 68fb ldr r3, [r7, #12] 8018b74: 865a strh r2, [r3, #50] ; 0x32 #endif /* TCP_CALCULATE_EFF_SEND_MSS */ pcb->cwnd = 1; 8018b76: 68fb ldr r3, [r7, #12] 8018b78: 2201 movs r2, #1 8018b7a: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 #if LWIP_CALLBACK_API pcb->connected = connected; 8018b7e: 68fb ldr r3, [r7, #12] 8018b80: 683a ldr r2, [r7, #0] 8018b82: f8c3 2088 str.w r2, [r3, #136] ; 0x88 #else /* LWIP_CALLBACK_API */ LWIP_UNUSED_ARG(connected); #endif /* LWIP_CALLBACK_API */ /* Send a SYN together with the MSS option. */ ret = tcp_enqueue_flags(pcb, TCP_SYN); 8018b86: 2102 movs r1, #2 8018b88: 68f8 ldr r0, [r7, #12] 8018b8a: f004 fb29 bl 801d1e0 8018b8e: 4603 mov r3, r0 8018b90: 74fb strb r3, [r7, #19] if (ret == ERR_OK) { 8018b92: f997 3013 ldrsb.w r3, [r7, #19] 8018b96: 2b00 cmp r3, #0 8018b98: d136 bne.n 8018c08 /* SYN segment was enqueued, changed the pcbs state now */ pcb->state = SYN_SENT; 8018b9a: 68fb ldr r3, [r7, #12] 8018b9c: 2202 movs r2, #2 8018b9e: 751a strb r2, [r3, #20] if (old_local_port != 0) { 8018ba0: 8b7b ldrh r3, [r7, #26] 8018ba2: 2b00 cmp r3, #0 8018ba4: d021 beq.n 8018bea TCP_RMV(&tcp_bound_pcbs, pcb); 8018ba6: 4b20 ldr r3, [pc, #128] ; (8018c28 ) 8018ba8: 681b ldr r3, [r3, #0] 8018baa: 68fa ldr r2, [r7, #12] 8018bac: 429a cmp r2, r3 8018bae: d105 bne.n 8018bbc 8018bb0: 4b1d ldr r3, [pc, #116] ; (8018c28 ) 8018bb2: 681b ldr r3, [r3, #0] 8018bb4: 68db ldr r3, [r3, #12] 8018bb6: 4a1c ldr r2, [pc, #112] ; (8018c28 ) 8018bb8: 6013 str r3, [r2, #0] 8018bba: e013 b.n 8018be4 8018bbc: 4b1a ldr r3, [pc, #104] ; (8018c28 ) 8018bbe: 681b ldr r3, [r3, #0] 8018bc0: 623b str r3, [r7, #32] 8018bc2: e00c b.n 8018bde 8018bc4: 6a3b ldr r3, [r7, #32] 8018bc6: 68db ldr r3, [r3, #12] 8018bc8: 68fa ldr r2, [r7, #12] 8018bca: 429a cmp r2, r3 8018bcc: d104 bne.n 8018bd8 8018bce: 68fb ldr r3, [r7, #12] 8018bd0: 68da ldr r2, [r3, #12] 8018bd2: 6a3b ldr r3, [r7, #32] 8018bd4: 60da str r2, [r3, #12] 8018bd6: e005 b.n 8018be4 8018bd8: 6a3b ldr r3, [r7, #32] 8018bda: 68db ldr r3, [r3, #12] 8018bdc: 623b str r3, [r7, #32] 8018bde: 6a3b ldr r3, [r7, #32] 8018be0: 2b00 cmp r3, #0 8018be2: d1ef bne.n 8018bc4 8018be4: 68fb ldr r3, [r7, #12] 8018be6: 2200 movs r2, #0 8018be8: 60da str r2, [r3, #12] } TCP_REG_ACTIVE(pcb); 8018bea: 4b10 ldr r3, [pc, #64] ; (8018c2c ) 8018bec: 681a ldr r2, [r3, #0] 8018bee: 68fb ldr r3, [r7, #12] 8018bf0: 60da str r2, [r3, #12] 8018bf2: 4a0e ldr r2, [pc, #56] ; (8018c2c ) 8018bf4: 68fb ldr r3, [r7, #12] 8018bf6: 6013 str r3, [r2, #0] 8018bf8: f005 fb62 bl 801e2c0 8018bfc: 4b0c ldr r3, [pc, #48] ; (8018c30 ) 8018bfe: 2201 movs r2, #1 8018c00: 701a strb r2, [r3, #0] MIB2_STATS_INC(mib2.tcpactiveopens); tcp_output(pcb); 8018c02: 68f8 ldr r0, [r7, #12] 8018c04: f004 fbda bl 801d3bc } return ret; 8018c08: f997 3013 ldrsb.w r3, [r7, #19] } 8018c0c: 4618 mov r0, r3 8018c0e: 3728 adds r7, #40 ; 0x28 8018c10: 46bd mov sp, r7 8018c12: bd80 pop {r7, pc} 8018c14: 08024ba8 .word 0x08024ba8 8018c18: 08024e84 .word 0x08024e84 8018c1c: 08024bec .word 0x08024bec 8018c20: 08024ea0 .word 0x08024ea0 8018c24: 08024ebc .word 0x08024ebc 8018c28: 2401a484 .word 0x2401a484 8018c2c: 2401a48c .word 0x2401a48c 8018c30: 2401a494 .word 0x2401a494 08018c34 : * * Automatically called from tcp_tmr(). */ void tcp_slowtmr(void) { 8018c34: b5b0 push {r4, r5, r7, lr} 8018c36: b090 sub sp, #64 ; 0x40 8018c38: af04 add r7, sp, #16 tcpwnd_size_t eff_wnd; u8_t pcb_remove; /* flag if a PCB should be removed */ u8_t pcb_reset; /* flag if a RST should be sent when removing */ err_t err; err = ERR_OK; 8018c3a: 2300 movs r3, #0 8018c3c: f887 3025 strb.w r3, [r7, #37] ; 0x25 ++tcp_ticks; 8018c40: 4b94 ldr r3, [pc, #592] ; (8018e94 ) 8018c42: 681b ldr r3, [r3, #0] 8018c44: 3301 adds r3, #1 8018c46: 4a93 ldr r2, [pc, #588] ; (8018e94 ) 8018c48: 6013 str r3, [r2, #0] ++tcp_timer_ctr; 8018c4a: 4b93 ldr r3, [pc, #588] ; (8018e98 ) 8018c4c: 781b ldrb r3, [r3, #0] 8018c4e: 3301 adds r3, #1 8018c50: b2da uxtb r2, r3 8018c52: 4b91 ldr r3, [pc, #580] ; (8018e98 ) 8018c54: 701a strb r2, [r3, #0] tcp_slowtmr_start: /* Steps through all of the active PCBs. */ prev = NULL; 8018c56: 2300 movs r3, #0 8018c58: 62bb str r3, [r7, #40] ; 0x28 pcb = tcp_active_pcbs; 8018c5a: 4b90 ldr r3, [pc, #576] ; (8018e9c ) 8018c5c: 681b ldr r3, [r3, #0] 8018c5e: 62fb str r3, [r7, #44] ; 0x2c if (pcb == NULL) { LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); } while (pcb != NULL) { 8018c60: e29d b.n 801919e LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); 8018c62: 6afb ldr r3, [r7, #44] ; 0x2c 8018c64: 7d1b ldrb r3, [r3, #20] 8018c66: 2b00 cmp r3, #0 8018c68: d106 bne.n 8018c78 8018c6a: 4b8d ldr r3, [pc, #564] ; (8018ea0 ) 8018c6c: f240 42be movw r2, #1214 ; 0x4be 8018c70: 498c ldr r1, [pc, #560] ; (8018ea4 ) 8018c72: 488d ldr r0, [pc, #564] ; (8018ea8 ) 8018c74: f008 fe88 bl 8021988 LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); 8018c78: 6afb ldr r3, [r7, #44] ; 0x2c 8018c7a: 7d1b ldrb r3, [r3, #20] 8018c7c: 2b01 cmp r3, #1 8018c7e: d106 bne.n 8018c8e 8018c80: 4b87 ldr r3, [pc, #540] ; (8018ea0 ) 8018c82: f240 42bf movw r2, #1215 ; 0x4bf 8018c86: 4989 ldr r1, [pc, #548] ; (8018eac ) 8018c88: 4887 ldr r0, [pc, #540] ; (8018ea8 ) 8018c8a: f008 fe7d bl 8021988 LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); 8018c8e: 6afb ldr r3, [r7, #44] ; 0x2c 8018c90: 7d1b ldrb r3, [r3, #20] 8018c92: 2b0a cmp r3, #10 8018c94: d106 bne.n 8018ca4 8018c96: 4b82 ldr r3, [pc, #520] ; (8018ea0 ) 8018c98: f44f 6298 mov.w r2, #1216 ; 0x4c0 8018c9c: 4984 ldr r1, [pc, #528] ; (8018eb0 ) 8018c9e: 4882 ldr r0, [pc, #520] ; (8018ea8 ) 8018ca0: f008 fe72 bl 8021988 if (pcb->last_timer == tcp_timer_ctr) { 8018ca4: 6afb ldr r3, [r7, #44] ; 0x2c 8018ca6: 7f9a ldrb r2, [r3, #30] 8018ca8: 4b7b ldr r3, [pc, #492] ; (8018e98 ) 8018caa: 781b ldrb r3, [r3, #0] 8018cac: 429a cmp r2, r3 8018cae: d105 bne.n 8018cbc /* skip this pcb, we have already processed it */ prev = pcb; 8018cb0: 6afb ldr r3, [r7, #44] ; 0x2c 8018cb2: 62bb str r3, [r7, #40] ; 0x28 pcb = pcb->next; 8018cb4: 6afb ldr r3, [r7, #44] ; 0x2c 8018cb6: 68db ldr r3, [r3, #12] 8018cb8: 62fb str r3, [r7, #44] ; 0x2c continue; 8018cba: e270 b.n 801919e } pcb->last_timer = tcp_timer_ctr; 8018cbc: 4b76 ldr r3, [pc, #472] ; (8018e98 ) 8018cbe: 781a ldrb r2, [r3, #0] 8018cc0: 6afb ldr r3, [r7, #44] ; 0x2c 8018cc2: 779a strb r2, [r3, #30] pcb_remove = 0; 8018cc4: 2300 movs r3, #0 8018cc6: f887 3027 strb.w r3, [r7, #39] ; 0x27 pcb_reset = 0; 8018cca: 2300 movs r3, #0 8018ccc: f887 3026 strb.w r3, [r7, #38] ; 0x26 if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) { 8018cd0: 6afb ldr r3, [r7, #44] ; 0x2c 8018cd2: 7d1b ldrb r3, [r3, #20] 8018cd4: 2b02 cmp r3, #2 8018cd6: d10a bne.n 8018cee 8018cd8: 6afb ldr r3, [r7, #44] ; 0x2c 8018cda: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 8018cde: 2b05 cmp r3, #5 8018ce0: d905 bls.n 8018cee ++pcb_remove; 8018ce2: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8018ce6: 3301 adds r3, #1 8018ce8: f887 3027 strb.w r3, [r7, #39] ; 0x27 LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); 8018cec: e11e b.n 8018f2c } else if (pcb->nrtx >= TCP_MAXRTX) { 8018cee: 6afb ldr r3, [r7, #44] ; 0x2c 8018cf0: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 8018cf4: 2b0b cmp r3, #11 8018cf6: d905 bls.n 8018d04 ++pcb_remove; 8018cf8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8018cfc: 3301 adds r3, #1 8018cfe: f887 3027 strb.w r3, [r7, #39] ; 0x27 8018d02: e113 b.n 8018f2c LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); } else { if (pcb->persist_backoff > 0) { 8018d04: 6afb ldr r3, [r7, #44] ; 0x2c 8018d06: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 8018d0a: 2b00 cmp r3, #0 8018d0c: d075 beq.n 8018dfa LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL); 8018d0e: 6afb ldr r3, [r7, #44] ; 0x2c 8018d10: 6f1b ldr r3, [r3, #112] ; 0x70 8018d12: 2b00 cmp r3, #0 8018d14: d006 beq.n 8018d24 8018d16: 4b62 ldr r3, [pc, #392] ; (8018ea0 ) 8018d18: f240 42d4 movw r2, #1236 ; 0x4d4 8018d1c: 4965 ldr r1, [pc, #404] ; (8018eb4 ) 8018d1e: 4862 ldr r0, [pc, #392] ; (8018ea8 ) 8018d20: f008 fe32 bl 8021988 LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL); 8018d24: 6afb ldr r3, [r7, #44] ; 0x2c 8018d26: 6edb ldr r3, [r3, #108] ; 0x6c 8018d28: 2b00 cmp r3, #0 8018d2a: d106 bne.n 8018d3a 8018d2c: 4b5c ldr r3, [pc, #368] ; (8018ea0 ) 8018d2e: f240 42d5 movw r2, #1237 ; 0x4d5 8018d32: 4961 ldr r1, [pc, #388] ; (8018eb8 ) 8018d34: 485c ldr r0, [pc, #368] ; (8018ea8 ) 8018d36: f008 fe27 bl 8021988 if (pcb->persist_probe >= TCP_MAXRTX) { 8018d3a: 6afb ldr r3, [r7, #44] ; 0x2c 8018d3c: f893 309a ldrb.w r3, [r3, #154] ; 0x9a 8018d40: 2b0b cmp r3, #11 8018d42: d905 bls.n 8018d50 ++pcb_remove; /* max probes reached */ 8018d44: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8018d48: 3301 adds r3, #1 8018d4a: f887 3027 strb.w r3, [r7, #39] ; 0x27 8018d4e: e0ed b.n 8018f2c } else { u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1]; 8018d50: 6afb ldr r3, [r7, #44] ; 0x2c 8018d52: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 8018d56: 3b01 subs r3, #1 8018d58: 4a58 ldr r2, [pc, #352] ; (8018ebc ) 8018d5a: 5cd3 ldrb r3, [r2, r3] 8018d5c: 747b strb r3, [r7, #17] if (pcb->persist_cnt < backoff_cnt) { 8018d5e: 6afb ldr r3, [r7, #44] ; 0x2c 8018d60: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 8018d64: 7c7a ldrb r2, [r7, #17] 8018d66: 429a cmp r2, r3 8018d68: d907 bls.n 8018d7a pcb->persist_cnt++; 8018d6a: 6afb ldr r3, [r7, #44] ; 0x2c 8018d6c: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 8018d70: 3301 adds r3, #1 8018d72: b2da uxtb r2, r3 8018d74: 6afb ldr r3, [r7, #44] ; 0x2c 8018d76: f883 2098 strb.w r2, [r3, #152] ; 0x98 } if (pcb->persist_cnt >= backoff_cnt) { 8018d7a: 6afb ldr r3, [r7, #44] ; 0x2c 8018d7c: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 8018d80: 7c7a ldrb r2, [r7, #17] 8018d82: 429a cmp r2, r3 8018d84: f200 80d2 bhi.w 8018f2c int next_slot = 1; /* increment timer to next slot */ 8018d88: 2301 movs r3, #1 8018d8a: 623b str r3, [r7, #32] /* If snd_wnd is zero, send 1 byte probes */ if (pcb->snd_wnd == 0) { 8018d8c: 6afb ldr r3, [r7, #44] ; 0x2c 8018d8e: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 8018d92: 2b00 cmp r3, #0 8018d94: d108 bne.n 8018da8 if (tcp_zero_window_probe(pcb) != ERR_OK) { 8018d96: 6af8 ldr r0, [r7, #44] ; 0x2c 8018d98: f005 f9c4 bl 801e124 8018d9c: 4603 mov r3, r0 8018d9e: 2b00 cmp r3, #0 8018da0: d014 beq.n 8018dcc next_slot = 0; /* try probe again with current slot */ 8018da2: 2300 movs r3, #0 8018da4: 623b str r3, [r7, #32] 8018da6: e011 b.n 8018dcc } /* snd_wnd not fully closed, split unsent head and fill window */ } else { if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) { 8018da8: 6afb ldr r3, [r7, #44] ; 0x2c 8018daa: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 8018dae: 4619 mov r1, r3 8018db0: 6af8 ldr r0, [r7, #44] ; 0x2c 8018db2: f004 f879 bl 801cea8 8018db6: 4603 mov r3, r0 8018db8: 2b00 cmp r3, #0 8018dba: d107 bne.n 8018dcc if (tcp_output(pcb) == ERR_OK) { 8018dbc: 6af8 ldr r0, [r7, #44] ; 0x2c 8018dbe: f004 fafd bl 801d3bc 8018dc2: 4603 mov r3, r0 8018dc4: 2b00 cmp r3, #0 8018dc6: d101 bne.n 8018dcc /* sending will cancel persist timer, else retry with current slot */ next_slot = 0; 8018dc8: 2300 movs r3, #0 8018dca: 623b str r3, [r7, #32] } } } if (next_slot) { 8018dcc: 6a3b ldr r3, [r7, #32] 8018dce: 2b00 cmp r3, #0 8018dd0: f000 80ac beq.w 8018f2c pcb->persist_cnt = 0; 8018dd4: 6afb ldr r3, [r7, #44] ; 0x2c 8018dd6: 2200 movs r2, #0 8018dd8: f883 2098 strb.w r2, [r3, #152] ; 0x98 if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) { 8018ddc: 6afb ldr r3, [r7, #44] ; 0x2c 8018dde: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 8018de2: 2b06 cmp r3, #6 8018de4: f200 80a2 bhi.w 8018f2c pcb->persist_backoff++; 8018de8: 6afb ldr r3, [r7, #44] ; 0x2c 8018dea: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 8018dee: 3301 adds r3, #1 8018df0: b2da uxtb r2, r3 8018df2: 6afb ldr r3, [r7, #44] ; 0x2c 8018df4: f883 2099 strb.w r2, [r3, #153] ; 0x99 8018df8: e098 b.n 8018f2c } } } } else { /* Increase the retransmission timer if it is running */ if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) { 8018dfa: 6afb ldr r3, [r7, #44] ; 0x2c 8018dfc: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 8018e00: 2b00 cmp r3, #0 8018e02: db0f blt.n 8018e24 8018e04: 6afb ldr r3, [r7, #44] ; 0x2c 8018e06: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 8018e0a: f647 72ff movw r2, #32767 ; 0x7fff 8018e0e: 4293 cmp r3, r2 8018e10: d008 beq.n 8018e24 ++pcb->rtime; 8018e12: 6afb ldr r3, [r7, #44] ; 0x2c 8018e14: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 8018e18: b29b uxth r3, r3 8018e1a: 3301 adds r3, #1 8018e1c: b29b uxth r3, r3 8018e1e: b21a sxth r2, r3 8018e20: 6afb ldr r3, [r7, #44] ; 0x2c 8018e22: 861a strh r2, [r3, #48] ; 0x30 } if (pcb->rtime >= pcb->rto) { 8018e24: 6afb ldr r3, [r7, #44] ; 0x2c 8018e26: f9b3 2030 ldrsh.w r2, [r3, #48] ; 0x30 8018e2a: 6afb ldr r3, [r7, #44] ; 0x2c 8018e2c: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40 8018e30: 429a cmp r2, r3 8018e32: db7b blt.n 8018f2c " pcb->rto %"S16_F"\n", pcb->rtime, pcb->rto)); /* If prepare phase fails but we have unsent data but no unacked data, still execute the backoff calculations below, as this means we somehow failed to send segment. */ if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) { 8018e34: 6af8 ldr r0, [r7, #44] ; 0x2c 8018e36: f004 fdb7 bl 801d9a8 8018e3a: 4603 mov r3, r0 8018e3c: 2b00 cmp r3, #0 8018e3e: d007 beq.n 8018e50 8018e40: 6afb ldr r3, [r7, #44] ; 0x2c 8018e42: 6f1b ldr r3, [r3, #112] ; 0x70 8018e44: 2b00 cmp r3, #0 8018e46: d171 bne.n 8018f2c 8018e48: 6afb ldr r3, [r7, #44] ; 0x2c 8018e4a: 6edb ldr r3, [r3, #108] ; 0x6c 8018e4c: 2b00 cmp r3, #0 8018e4e: d06d beq.n 8018f2c /* Double retransmission time-out unless we are trying to * connect to somebody (i.e., we are in SYN_SENT). */ if (pcb->state != SYN_SENT) { 8018e50: 6afb ldr r3, [r7, #44] ; 0x2c 8018e52: 7d1b ldrb r3, [r3, #20] 8018e54: 2b02 cmp r3, #2 8018e56: d03a beq.n 8018ece u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1); 8018e58: 6afb ldr r3, [r7, #44] ; 0x2c 8018e5a: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 8018e5e: 2b0c cmp r3, #12 8018e60: bf28 it cs 8018e62: 230c movcs r3, #12 8018e64: 76fb strb r3, [r7, #27] int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx]; 8018e66: 6afb ldr r3, [r7, #44] ; 0x2c 8018e68: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c 8018e6c: 10db asrs r3, r3, #3 8018e6e: b21b sxth r3, r3 8018e70: 461a mov r2, r3 8018e72: 6afb ldr r3, [r7, #44] ; 0x2c 8018e74: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e 8018e78: 4413 add r3, r2 8018e7a: 7efa ldrb r2, [r7, #27] 8018e7c: 4910 ldr r1, [pc, #64] ; (8018ec0 ) 8018e7e: 5c8a ldrb r2, [r1, r2] 8018e80: 4093 lsls r3, r2 8018e82: 617b str r3, [r7, #20] pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF); 8018e84: 697b ldr r3, [r7, #20] 8018e86: f647 72fe movw r2, #32766 ; 0x7ffe 8018e8a: 4293 cmp r3, r2 8018e8c: dc1a bgt.n 8018ec4 8018e8e: 697b ldr r3, [r7, #20] 8018e90: b21a sxth r2, r3 8018e92: e019 b.n 8018ec8 8018e94: 2401a480 .word 0x2401a480 8018e98: 2401a496 .word 0x2401a496 8018e9c: 2401a48c .word 0x2401a48c 8018ea0: 08024ba8 .word 0x08024ba8 8018ea4: 08024eec .word 0x08024eec 8018ea8: 08024bec .word 0x08024bec 8018eac: 08024f18 .word 0x08024f18 8018eb0: 08024f44 .word 0x08024f44 8018eb4: 08024f74 .word 0x08024f74 8018eb8: 08024fa8 .word 0x08024fa8 8018ebc: 08026cbc .word 0x08026cbc 8018ec0: 08026cac .word 0x08026cac 8018ec4: f647 72ff movw r2, #32767 ; 0x7fff 8018ec8: 6afb ldr r3, [r7, #44] ; 0x2c 8018eca: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 } /* Reset the retransmission timer. */ pcb->rtime = 0; 8018ece: 6afb ldr r3, [r7, #44] ; 0x2c 8018ed0: 2200 movs r2, #0 8018ed2: 861a strh r2, [r3, #48] ; 0x30 /* Reduce congestion window and ssthresh. */ eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); 8018ed4: 6afb ldr r3, [r7, #44] ; 0x2c 8018ed6: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 8018eda: 6afb ldr r3, [r7, #44] ; 0x2c 8018edc: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 8018ee0: 4293 cmp r3, r2 8018ee2: bf28 it cs 8018ee4: 4613 movcs r3, r2 8018ee6: 827b strh r3, [r7, #18] pcb->ssthresh = eff_wnd >> 1; 8018ee8: 8a7b ldrh r3, [r7, #18] 8018eea: 085b lsrs r3, r3, #1 8018eec: b29a uxth r2, r3 8018eee: 6afb ldr r3, [r7, #44] ; 0x2c 8018ef0: f8a3 204a strh.w r2, [r3, #74] ; 0x4a if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) { 8018ef4: 6afb ldr r3, [r7, #44] ; 0x2c 8018ef6: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a 8018efa: 6afb ldr r3, [r7, #44] ; 0x2c 8018efc: 8e5b ldrh r3, [r3, #50] ; 0x32 8018efe: 005b lsls r3, r3, #1 8018f00: b29b uxth r3, r3 8018f02: 429a cmp r2, r3 8018f04: d206 bcs.n 8018f14 pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1); 8018f06: 6afb ldr r3, [r7, #44] ; 0x2c 8018f08: 8e5b ldrh r3, [r3, #50] ; 0x32 8018f0a: 005b lsls r3, r3, #1 8018f0c: b29a uxth r2, r3 8018f0e: 6afb ldr r3, [r7, #44] ; 0x2c 8018f10: f8a3 204a strh.w r2, [r3, #74] ; 0x4a } pcb->cwnd = pcb->mss; 8018f14: 6afb ldr r3, [r7, #44] ; 0x2c 8018f16: 8e5a ldrh r2, [r3, #50] ; 0x32 8018f18: 6afb ldr r3, [r7, #44] ; 0x2c 8018f1a: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F " ssthresh %"TCPWNDSIZE_F"\n", pcb->cwnd, pcb->ssthresh)); pcb->bytes_acked = 0; 8018f1e: 6afb ldr r3, [r7, #44] ; 0x2c 8018f20: 2200 movs r2, #0 8018f22: f8a3 206a strh.w r2, [r3, #106] ; 0x6a /* The following needs to be called AFTER cwnd is set to one mss - STJ */ tcp_rexmit_rto_commit(pcb); 8018f26: 6af8 ldr r0, [r7, #44] ; 0x2c 8018f28: f004 fdb8 bl 801da9c } } } } /* Check if this PCB has stayed too long in FIN-WAIT-2 */ if (pcb->state == FIN_WAIT_2) { 8018f2c: 6afb ldr r3, [r7, #44] ; 0x2c 8018f2e: 7d1b ldrb r3, [r3, #20] 8018f30: 2b06 cmp r3, #6 8018f32: d111 bne.n 8018f58 /* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */ if (pcb->flags & TF_RXCLOSED) { 8018f34: 6afb ldr r3, [r7, #44] ; 0x2c 8018f36: 8b5b ldrh r3, [r3, #26] 8018f38: f003 0310 and.w r3, r3, #16 8018f3c: 2b00 cmp r3, #0 8018f3e: d00b beq.n 8018f58 /* PCB was fully closed (either through close() or SHUT_RDWR): normal FIN-WAIT timeout handling. */ if ((u32_t)(tcp_ticks - pcb->tmr) > 8018f40: 4b9c ldr r3, [pc, #624] ; (80191b4 ) 8018f42: 681a ldr r2, [r3, #0] 8018f44: 6afb ldr r3, [r7, #44] ; 0x2c 8018f46: 6a1b ldr r3, [r3, #32] 8018f48: 1ad3 subs r3, r2, r3 8018f4a: 2b28 cmp r3, #40 ; 0x28 8018f4c: d904 bls.n 8018f58 TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { ++pcb_remove; 8018f4e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8018f52: 3301 adds r3, #1 8018f54: f887 3027 strb.w r3, [r7, #39] ; 0x27 } } } /* Check if KEEPALIVE should be sent */ if (ip_get_option(pcb, SOF_KEEPALIVE) && 8018f58: 6afb ldr r3, [r7, #44] ; 0x2c 8018f5a: 7a5b ldrb r3, [r3, #9] 8018f5c: f003 0308 and.w r3, r3, #8 8018f60: 2b00 cmp r3, #0 8018f62: d04a beq.n 8018ffa ((pcb->state == ESTABLISHED) || 8018f64: 6afb ldr r3, [r7, #44] ; 0x2c 8018f66: 7d1b ldrb r3, [r3, #20] if (ip_get_option(pcb, SOF_KEEPALIVE) && 8018f68: 2b04 cmp r3, #4 8018f6a: d003 beq.n 8018f74 (pcb->state == CLOSE_WAIT))) { 8018f6c: 6afb ldr r3, [r7, #44] ; 0x2c 8018f6e: 7d1b ldrb r3, [r3, #20] ((pcb->state == ESTABLISHED) || 8018f70: 2b07 cmp r3, #7 8018f72: d142 bne.n 8018ffa if ((u32_t)(tcp_ticks - pcb->tmr) > 8018f74: 4b8f ldr r3, [pc, #572] ; (80191b4 ) 8018f76: 681a ldr r2, [r3, #0] 8018f78: 6afb ldr r3, [r7, #44] ; 0x2c 8018f7a: 6a1b ldr r3, [r3, #32] 8018f7c: 1ad2 subs r2, r2, r3 (pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) { 8018f7e: 6afb ldr r3, [r7, #44] ; 0x2c 8018f80: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94 8018f84: 4b8c ldr r3, [pc, #560] ; (80191b8 ) 8018f86: 440b add r3, r1 8018f88: 498c ldr r1, [pc, #560] ; (80191bc ) 8018f8a: fba1 1303 umull r1, r3, r1, r3 8018f8e: 095b lsrs r3, r3, #5 if ((u32_t)(tcp_ticks - pcb->tmr) > 8018f90: 429a cmp r2, r3 8018f92: d90a bls.n 8018faa LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to ")); ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip); LWIP_DEBUGF(TCP_DEBUG, ("\n")); ++pcb_remove; 8018f94: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8018f98: 3301 adds r3, #1 8018f9a: f887 3027 strb.w r3, [r7, #39] ; 0x27 ++pcb_reset; 8018f9e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 8018fa2: 3301 adds r3, #1 8018fa4: f887 3026 strb.w r3, [r7, #38] ; 0x26 8018fa8: e027 b.n 8018ffa } else if ((u32_t)(tcp_ticks - pcb->tmr) > 8018faa: 4b82 ldr r3, [pc, #520] ; (80191b4 ) 8018fac: 681a ldr r2, [r3, #0] 8018fae: 6afb ldr r3, [r7, #44] ; 0x2c 8018fb0: 6a1b ldr r3, [r3, #32] 8018fb2: 1ad2 subs r2, r2, r3 (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb)) 8018fb4: 6afb ldr r3, [r7, #44] ; 0x2c 8018fb6: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94 8018fba: 6afb ldr r3, [r7, #44] ; 0x2c 8018fbc: f893 309b ldrb.w r3, [r3, #155] ; 0x9b 8018fc0: 4618 mov r0, r3 8018fc2: 4b7f ldr r3, [pc, #508] ; (80191c0 ) 8018fc4: fb00 f303 mul.w r3, r0, r3 8018fc8: 440b add r3, r1 / TCP_SLOW_INTERVAL) { 8018fca: 497c ldr r1, [pc, #496] ; (80191bc ) 8018fcc: fba1 1303 umull r1, r3, r1, r3 8018fd0: 095b lsrs r3, r3, #5 } else if ((u32_t)(tcp_ticks - pcb->tmr) > 8018fd2: 429a cmp r2, r3 8018fd4: d911 bls.n 8018ffa err = tcp_keepalive(pcb); 8018fd6: 6af8 ldr r0, [r7, #44] ; 0x2c 8018fd8: f005 f864 bl 801e0a4 8018fdc: 4603 mov r3, r0 8018fde: f887 3025 strb.w r3, [r7, #37] ; 0x25 if (err == ERR_OK) { 8018fe2: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25 8018fe6: 2b00 cmp r3, #0 8018fe8: d107 bne.n 8018ffa pcb->keep_cnt_sent++; 8018fea: 6afb ldr r3, [r7, #44] ; 0x2c 8018fec: f893 309b ldrb.w r3, [r3, #155] ; 0x9b 8018ff0: 3301 adds r3, #1 8018ff2: b2da uxtb r2, r3 8018ff4: 6afb ldr r3, [r7, #44] ; 0x2c 8018ff6: f883 209b strb.w r2, [r3, #155] ; 0x9b /* If this PCB has queued out of sequence data, but has been inactive for too long, will drop the data (it will eventually be retransmitted). */ #if TCP_QUEUE_OOSEQ if (pcb->ooseq != NULL && 8018ffa: 6afb ldr r3, [r7, #44] ; 0x2c 8018ffc: 6f5b ldr r3, [r3, #116] ; 0x74 8018ffe: 2b00 cmp r3, #0 8019000: d011 beq.n 8019026 (tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) { 8019002: 4b6c ldr r3, [pc, #432] ; (80191b4 ) 8019004: 681a ldr r2, [r3, #0] 8019006: 6afb ldr r3, [r7, #44] ; 0x2c 8019008: 6a1b ldr r3, [r3, #32] 801900a: 1ad2 subs r2, r2, r3 801900c: 6afb ldr r3, [r7, #44] ; 0x2c 801900e: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40 8019012: 4619 mov r1, r3 8019014: 460b mov r3, r1 8019016: 005b lsls r3, r3, #1 8019018: 440b add r3, r1 801901a: 005b lsls r3, r3, #1 if (pcb->ooseq != NULL && 801901c: 429a cmp r2, r3 801901e: d302 bcc.n 8019026 LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); tcp_free_ooseq(pcb); 8019020: 6af8 ldr r0, [r7, #44] ; 0x2c 8019022: f000 feb3 bl 8019d8c } #endif /* TCP_QUEUE_OOSEQ */ /* Check if this PCB has stayed too long in SYN-RCVD */ if (pcb->state == SYN_RCVD) { 8019026: 6afb ldr r3, [r7, #44] ; 0x2c 8019028: 7d1b ldrb r3, [r3, #20] 801902a: 2b03 cmp r3, #3 801902c: d10b bne.n 8019046 if ((u32_t)(tcp_ticks - pcb->tmr) > 801902e: 4b61 ldr r3, [pc, #388] ; (80191b4 ) 8019030: 681a ldr r2, [r3, #0] 8019032: 6afb ldr r3, [r7, #44] ; 0x2c 8019034: 6a1b ldr r3, [r3, #32] 8019036: 1ad3 subs r3, r2, r3 8019038: 2b28 cmp r3, #40 ; 0x28 801903a: d904 bls.n 8019046 TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { ++pcb_remove; 801903c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8019040: 3301 adds r3, #1 8019042: f887 3027 strb.w r3, [r7, #39] ; 0x27 LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); } } /* Check if this PCB has stayed too long in LAST-ACK */ if (pcb->state == LAST_ACK) { 8019046: 6afb ldr r3, [r7, #44] ; 0x2c 8019048: 7d1b ldrb r3, [r3, #20] 801904a: 2b09 cmp r3, #9 801904c: d10b bne.n 8019066 if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { 801904e: 4b59 ldr r3, [pc, #356] ; (80191b4 ) 8019050: 681a ldr r2, [r3, #0] 8019052: 6afb ldr r3, [r7, #44] ; 0x2c 8019054: 6a1b ldr r3, [r3, #32] 8019056: 1ad3 subs r3, r2, r3 8019058: 2bf0 cmp r3, #240 ; 0xf0 801905a: d904 bls.n 8019066 ++pcb_remove; 801905c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8019060: 3301 adds r3, #1 8019062: f887 3027 strb.w r3, [r7, #39] ; 0x27 LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); } } /* If the PCB should be removed, do it. */ if (pcb_remove) { 8019066: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 801906a: 2b00 cmp r3, #0 801906c: d060 beq.n 8019130 struct tcp_pcb *pcb2; #if LWIP_CALLBACK_API tcp_err_fn err_fn = pcb->errf; 801906e: 6afb ldr r3, [r7, #44] ; 0x2c 8019070: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8019074: 60fb str r3, [r7, #12] #endif /* LWIP_CALLBACK_API */ void *err_arg; enum tcp_state last_state; tcp_pcb_purge(pcb); 8019076: 6af8 ldr r0, [r7, #44] ; 0x2c 8019078: f000 fcce bl 8019a18 /* Remove PCB from tcp_active_pcbs list. */ if (prev != NULL) { 801907c: 6abb ldr r3, [r7, #40] ; 0x28 801907e: 2b00 cmp r3, #0 8019080: d010 beq.n 80190a4 LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); 8019082: 4b50 ldr r3, [pc, #320] ; (80191c4 ) 8019084: 681b ldr r3, [r3, #0] 8019086: 6afa ldr r2, [r7, #44] ; 0x2c 8019088: 429a cmp r2, r3 801908a: d106 bne.n 801909a 801908c: 4b4e ldr r3, [pc, #312] ; (80191c8 ) 801908e: f240 526d movw r2, #1389 ; 0x56d 8019092: 494e ldr r1, [pc, #312] ; (80191cc ) 8019094: 484e ldr r0, [pc, #312] ; (80191d0 ) 8019096: f008 fc77 bl 8021988 prev->next = pcb->next; 801909a: 6afb ldr r3, [r7, #44] ; 0x2c 801909c: 68da ldr r2, [r3, #12] 801909e: 6abb ldr r3, [r7, #40] ; 0x28 80190a0: 60da str r2, [r3, #12] 80190a2: e00f b.n 80190c4 } else { /* This PCB was the first. */ LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); 80190a4: 4b47 ldr r3, [pc, #284] ; (80191c4 ) 80190a6: 681b ldr r3, [r3, #0] 80190a8: 6afa ldr r2, [r7, #44] ; 0x2c 80190aa: 429a cmp r2, r3 80190ac: d006 beq.n 80190bc 80190ae: 4b46 ldr r3, [pc, #280] ; (80191c8 ) 80190b0: f240 5271 movw r2, #1393 ; 0x571 80190b4: 4947 ldr r1, [pc, #284] ; (80191d4 ) 80190b6: 4846 ldr r0, [pc, #280] ; (80191d0 ) 80190b8: f008 fc66 bl 8021988 tcp_active_pcbs = pcb->next; 80190bc: 6afb ldr r3, [r7, #44] ; 0x2c 80190be: 68db ldr r3, [r3, #12] 80190c0: 4a40 ldr r2, [pc, #256] ; (80191c4 ) 80190c2: 6013 str r3, [r2, #0] } if (pcb_reset) { 80190c4: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 80190c8: 2b00 cmp r3, #0 80190ca: d013 beq.n 80190f4 tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, 80190cc: 6afb ldr r3, [r7, #44] ; 0x2c 80190ce: 6d18 ldr r0, [r3, #80] ; 0x50 80190d0: 6afb ldr r3, [r7, #44] ; 0x2c 80190d2: 6a5c ldr r4, [r3, #36] ; 0x24 80190d4: 6afd ldr r5, [r7, #44] ; 0x2c 80190d6: 6afb ldr r3, [r7, #44] ; 0x2c 80190d8: 3304 adds r3, #4 80190da: 6afa ldr r2, [r7, #44] ; 0x2c 80190dc: 8ad2 ldrh r2, [r2, #22] 80190de: 6af9 ldr r1, [r7, #44] ; 0x2c 80190e0: 8b09 ldrh r1, [r1, #24] 80190e2: 9102 str r1, [sp, #8] 80190e4: 9201 str r2, [sp, #4] 80190e6: 9300 str r3, [sp, #0] 80190e8: 462b mov r3, r5 80190ea: 4622 mov r2, r4 80190ec: 4601 mov r1, r0 80190ee: 6af8 ldr r0, [r7, #44] ; 0x2c 80190f0: f004 ff24 bl 801df3c pcb->local_port, pcb->remote_port); } err_arg = pcb->callback_arg; 80190f4: 6afb ldr r3, [r7, #44] ; 0x2c 80190f6: 691b ldr r3, [r3, #16] 80190f8: 60bb str r3, [r7, #8] last_state = pcb->state; 80190fa: 6afb ldr r3, [r7, #44] ; 0x2c 80190fc: 7d1b ldrb r3, [r3, #20] 80190fe: 71fb strb r3, [r7, #7] pcb2 = pcb; 8019100: 6afb ldr r3, [r7, #44] ; 0x2c 8019102: 603b str r3, [r7, #0] pcb = pcb->next; 8019104: 6afb ldr r3, [r7, #44] ; 0x2c 8019106: 68db ldr r3, [r3, #12] 8019108: 62fb str r3, [r7, #44] ; 0x2c tcp_free(pcb2); 801910a: 6838 ldr r0, [r7, #0] 801910c: f7fe ffa0 bl 8018050 tcp_active_pcbs_changed = 0; 8019110: 4b31 ldr r3, [pc, #196] ; (80191d8 ) 8019112: 2200 movs r2, #0 8019114: 701a strb r2, [r3, #0] TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT); 8019116: 68fb ldr r3, [r7, #12] 8019118: 2b00 cmp r3, #0 801911a: d004 beq.n 8019126 801911c: 68fb ldr r3, [r7, #12] 801911e: f06f 010c mvn.w r1, #12 8019122: 68b8 ldr r0, [r7, #8] 8019124: 4798 blx r3 if (tcp_active_pcbs_changed) { 8019126: 4b2c ldr r3, [pc, #176] ; (80191d8 ) 8019128: 781b ldrb r3, [r3, #0] 801912a: 2b00 cmp r3, #0 801912c: d037 beq.n 801919e goto tcp_slowtmr_start; 801912e: e592 b.n 8018c56 } } else { /* get the 'next' element now and work with 'prev' below (in case of abort) */ prev = pcb; 8019130: 6afb ldr r3, [r7, #44] ; 0x2c 8019132: 62bb str r3, [r7, #40] ; 0x28 pcb = pcb->next; 8019134: 6afb ldr r3, [r7, #44] ; 0x2c 8019136: 68db ldr r3, [r3, #12] 8019138: 62fb str r3, [r7, #44] ; 0x2c /* We check if we should poll the connection. */ ++prev->polltmr; 801913a: 6abb ldr r3, [r7, #40] ; 0x28 801913c: 7f1b ldrb r3, [r3, #28] 801913e: 3301 adds r3, #1 8019140: b2da uxtb r2, r3 8019142: 6abb ldr r3, [r7, #40] ; 0x28 8019144: 771a strb r2, [r3, #28] if (prev->polltmr >= prev->pollinterval) { 8019146: 6abb ldr r3, [r7, #40] ; 0x28 8019148: 7f1a ldrb r2, [r3, #28] 801914a: 6abb ldr r3, [r7, #40] ; 0x28 801914c: 7f5b ldrb r3, [r3, #29] 801914e: 429a cmp r2, r3 8019150: d325 bcc.n 801919e prev->polltmr = 0; 8019152: 6abb ldr r3, [r7, #40] ; 0x28 8019154: 2200 movs r2, #0 8019156: 771a strb r2, [r3, #28] LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); tcp_active_pcbs_changed = 0; 8019158: 4b1f ldr r3, [pc, #124] ; (80191d8 ) 801915a: 2200 movs r2, #0 801915c: 701a strb r2, [r3, #0] TCP_EVENT_POLL(prev, err); 801915e: 6abb ldr r3, [r7, #40] ; 0x28 8019160: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8019164: 2b00 cmp r3, #0 8019166: d00b beq.n 8019180 8019168: 6abb ldr r3, [r7, #40] ; 0x28 801916a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 801916e: 6aba ldr r2, [r7, #40] ; 0x28 8019170: 6912 ldr r2, [r2, #16] 8019172: 6ab9 ldr r1, [r7, #40] ; 0x28 8019174: 4610 mov r0, r2 8019176: 4798 blx r3 8019178: 4603 mov r3, r0 801917a: f887 3025 strb.w r3, [r7, #37] ; 0x25 801917e: e002 b.n 8019186 8019180: 2300 movs r3, #0 8019182: f887 3025 strb.w r3, [r7, #37] ; 0x25 if (tcp_active_pcbs_changed) { 8019186: 4b14 ldr r3, [pc, #80] ; (80191d8 ) 8019188: 781b ldrb r3, [r3, #0] 801918a: 2b00 cmp r3, #0 801918c: d000 beq.n 8019190 goto tcp_slowtmr_start; 801918e: e562 b.n 8018c56 } /* if err == ERR_ABRT, 'prev' is already deallocated */ if (err == ERR_OK) { 8019190: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25 8019194: 2b00 cmp r3, #0 8019196: d102 bne.n 801919e tcp_output(prev); 8019198: 6ab8 ldr r0, [r7, #40] ; 0x28 801919a: f004 f90f bl 801d3bc while (pcb != NULL) { 801919e: 6afb ldr r3, [r7, #44] ; 0x2c 80191a0: 2b00 cmp r3, #0 80191a2: f47f ad5e bne.w 8018c62 } } /* Steps through all of the TIME-WAIT PCBs. */ prev = NULL; 80191a6: 2300 movs r3, #0 80191a8: 62bb str r3, [r7, #40] ; 0x28 pcb = tcp_tw_pcbs; 80191aa: 4b0c ldr r3, [pc, #48] ; (80191dc ) 80191ac: 681b ldr r3, [r3, #0] 80191ae: 62fb str r3, [r7, #44] ; 0x2c while (pcb != NULL) { 80191b0: e069 b.n 8019286 80191b2: bf00 nop 80191b4: 2401a480 .word 0x2401a480 80191b8: 000a4cb8 .word 0x000a4cb8 80191bc: 10624dd3 .word 0x10624dd3 80191c0: 000124f8 .word 0x000124f8 80191c4: 2401a48c .word 0x2401a48c 80191c8: 08024ba8 .word 0x08024ba8 80191cc: 08024fe0 .word 0x08024fe0 80191d0: 08024bec .word 0x08024bec 80191d4: 0802500c .word 0x0802500c 80191d8: 2401a494 .word 0x2401a494 80191dc: 2401a490 .word 0x2401a490 LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); 80191e0: 6afb ldr r3, [r7, #44] ; 0x2c 80191e2: 7d1b ldrb r3, [r3, #20] 80191e4: 2b0a cmp r3, #10 80191e6: d006 beq.n 80191f6 80191e8: 4b2b ldr r3, [pc, #172] ; (8019298 ) 80191ea: f240 52a1 movw r2, #1441 ; 0x5a1 80191ee: 492b ldr r1, [pc, #172] ; (801929c ) 80191f0: 482b ldr r0, [pc, #172] ; (80192a0 ) 80191f2: f008 fbc9 bl 8021988 pcb_remove = 0; 80191f6: 2300 movs r3, #0 80191f8: f887 3027 strb.w r3, [r7, #39] ; 0x27 /* Check if this PCB has stayed long enough in TIME-WAIT */ if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { 80191fc: 4b29 ldr r3, [pc, #164] ; (80192a4 ) 80191fe: 681a ldr r2, [r3, #0] 8019200: 6afb ldr r3, [r7, #44] ; 0x2c 8019202: 6a1b ldr r3, [r3, #32] 8019204: 1ad3 subs r3, r2, r3 8019206: 2bf0 cmp r3, #240 ; 0xf0 8019208: d904 bls.n 8019214 ++pcb_remove; 801920a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 801920e: 3301 adds r3, #1 8019210: f887 3027 strb.w r3, [r7, #39] ; 0x27 } /* If the PCB should be removed, do it. */ if (pcb_remove) { 8019214: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8019218: 2b00 cmp r3, #0 801921a: d02f beq.n 801927c struct tcp_pcb *pcb2; tcp_pcb_purge(pcb); 801921c: 6af8 ldr r0, [r7, #44] ; 0x2c 801921e: f000 fbfb bl 8019a18 /* Remove PCB from tcp_tw_pcbs list. */ if (prev != NULL) { 8019222: 6abb ldr r3, [r7, #40] ; 0x28 8019224: 2b00 cmp r3, #0 8019226: d010 beq.n 801924a LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); 8019228: 4b1f ldr r3, [pc, #124] ; (80192a8 ) 801922a: 681b ldr r3, [r3, #0] 801922c: 6afa ldr r2, [r7, #44] ; 0x2c 801922e: 429a cmp r2, r3 8019230: d106 bne.n 8019240 8019232: 4b19 ldr r3, [pc, #100] ; (8019298 ) 8019234: f240 52af movw r2, #1455 ; 0x5af 8019238: 491c ldr r1, [pc, #112] ; (80192ac ) 801923a: 4819 ldr r0, [pc, #100] ; (80192a0 ) 801923c: f008 fba4 bl 8021988 prev->next = pcb->next; 8019240: 6afb ldr r3, [r7, #44] ; 0x2c 8019242: 68da ldr r2, [r3, #12] 8019244: 6abb ldr r3, [r7, #40] ; 0x28 8019246: 60da str r2, [r3, #12] 8019248: e00f b.n 801926a } else { /* This PCB was the first. */ LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); 801924a: 4b17 ldr r3, [pc, #92] ; (80192a8 ) 801924c: 681b ldr r3, [r3, #0] 801924e: 6afa ldr r2, [r7, #44] ; 0x2c 8019250: 429a cmp r2, r3 8019252: d006 beq.n 8019262 8019254: 4b10 ldr r3, [pc, #64] ; (8019298 ) 8019256: f240 52b3 movw r2, #1459 ; 0x5b3 801925a: 4915 ldr r1, [pc, #84] ; (80192b0 ) 801925c: 4810 ldr r0, [pc, #64] ; (80192a0 ) 801925e: f008 fb93 bl 8021988 tcp_tw_pcbs = pcb->next; 8019262: 6afb ldr r3, [r7, #44] ; 0x2c 8019264: 68db ldr r3, [r3, #12] 8019266: 4a10 ldr r2, [pc, #64] ; (80192a8 ) 8019268: 6013 str r3, [r2, #0] } pcb2 = pcb; 801926a: 6afb ldr r3, [r7, #44] ; 0x2c 801926c: 61fb str r3, [r7, #28] pcb = pcb->next; 801926e: 6afb ldr r3, [r7, #44] ; 0x2c 8019270: 68db ldr r3, [r3, #12] 8019272: 62fb str r3, [r7, #44] ; 0x2c tcp_free(pcb2); 8019274: 69f8 ldr r0, [r7, #28] 8019276: f7fe feeb bl 8018050 801927a: e004 b.n 8019286 } else { prev = pcb; 801927c: 6afb ldr r3, [r7, #44] ; 0x2c 801927e: 62bb str r3, [r7, #40] ; 0x28 pcb = pcb->next; 8019280: 6afb ldr r3, [r7, #44] ; 0x2c 8019282: 68db ldr r3, [r3, #12] 8019284: 62fb str r3, [r7, #44] ; 0x2c while (pcb != NULL) { 8019286: 6afb ldr r3, [r7, #44] ; 0x2c 8019288: 2b00 cmp r3, #0 801928a: d1a9 bne.n 80191e0 } } } 801928c: bf00 nop 801928e: bf00 nop 8019290: 3730 adds r7, #48 ; 0x30 8019292: 46bd mov sp, r7 8019294: bdb0 pop {r4, r5, r7, pc} 8019296: bf00 nop 8019298: 08024ba8 .word 0x08024ba8 801929c: 08025038 .word 0x08025038 80192a0: 08024bec .word 0x08024bec 80192a4: 2401a480 .word 0x2401a480 80192a8: 2401a490 .word 0x2401a490 80192ac: 08025068 .word 0x08025068 80192b0: 08025090 .word 0x08025090 080192b4 : * * Automatically called from tcp_tmr(). */ void tcp_fasttmr(void) { 80192b4: b580 push {r7, lr} 80192b6: b082 sub sp, #8 80192b8: af00 add r7, sp, #0 struct tcp_pcb *pcb; ++tcp_timer_ctr; 80192ba: 4b2d ldr r3, [pc, #180] ; (8019370 ) 80192bc: 781b ldrb r3, [r3, #0] 80192be: 3301 adds r3, #1 80192c0: b2da uxtb r2, r3 80192c2: 4b2b ldr r3, [pc, #172] ; (8019370 ) 80192c4: 701a strb r2, [r3, #0] tcp_fasttmr_start: pcb = tcp_active_pcbs; 80192c6: 4b2b ldr r3, [pc, #172] ; (8019374 ) 80192c8: 681b ldr r3, [r3, #0] 80192ca: 607b str r3, [r7, #4] while (pcb != NULL) { 80192cc: e048 b.n 8019360 if (pcb->last_timer != tcp_timer_ctr) { 80192ce: 687b ldr r3, [r7, #4] 80192d0: 7f9a ldrb r2, [r3, #30] 80192d2: 4b27 ldr r3, [pc, #156] ; (8019370 ) 80192d4: 781b ldrb r3, [r3, #0] 80192d6: 429a cmp r2, r3 80192d8: d03f beq.n 801935a struct tcp_pcb *next; pcb->last_timer = tcp_timer_ctr; 80192da: 4b25 ldr r3, [pc, #148] ; (8019370 ) 80192dc: 781a ldrb r2, [r3, #0] 80192de: 687b ldr r3, [r7, #4] 80192e0: 779a strb r2, [r3, #30] /* send delayed ACKs */ if (pcb->flags & TF_ACK_DELAY) { 80192e2: 687b ldr r3, [r7, #4] 80192e4: 8b5b ldrh r3, [r3, #26] 80192e6: f003 0301 and.w r3, r3, #1 80192ea: 2b00 cmp r3, #0 80192ec: d010 beq.n 8019310 LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); tcp_ack_now(pcb); 80192ee: 687b ldr r3, [r7, #4] 80192f0: 8b5b ldrh r3, [r3, #26] 80192f2: f043 0302 orr.w r3, r3, #2 80192f6: b29a uxth r2, r3 80192f8: 687b ldr r3, [r7, #4] 80192fa: 835a strh r2, [r3, #26] tcp_output(pcb); 80192fc: 6878 ldr r0, [r7, #4] 80192fe: f004 f85d bl 801d3bc tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); 8019302: 687b ldr r3, [r7, #4] 8019304: 8b5b ldrh r3, [r3, #26] 8019306: f023 0303 bic.w r3, r3, #3 801930a: b29a uxth r2, r3 801930c: 687b ldr r3, [r7, #4] 801930e: 835a strh r2, [r3, #26] } /* send pending FIN */ if (pcb->flags & TF_CLOSEPEND) { 8019310: 687b ldr r3, [r7, #4] 8019312: 8b5b ldrh r3, [r3, #26] 8019314: f003 0308 and.w r3, r3, #8 8019318: 2b00 cmp r3, #0 801931a: d009 beq.n 8019330 LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n")); tcp_clear_flags(pcb, TF_CLOSEPEND); 801931c: 687b ldr r3, [r7, #4] 801931e: 8b5b ldrh r3, [r3, #26] 8019320: f023 0308 bic.w r3, r3, #8 8019324: b29a uxth r2, r3 8019326: 687b ldr r3, [r7, #4] 8019328: 835a strh r2, [r3, #26] tcp_close_shutdown_fin(pcb); 801932a: 6878 ldr r0, [r7, #4] 801932c: f7ff f824 bl 8018378 } next = pcb->next; 8019330: 687b ldr r3, [r7, #4] 8019332: 68db ldr r3, [r3, #12] 8019334: 603b str r3, [r7, #0] /* If there is data which was previously "refused" by upper layer */ if (pcb->refused_data != NULL) { 8019336: 687b ldr r3, [r7, #4] 8019338: 6f9b ldr r3, [r3, #120] ; 0x78 801933a: 2b00 cmp r3, #0 801933c: d00a beq.n 8019354 tcp_active_pcbs_changed = 0; 801933e: 4b0e ldr r3, [pc, #56] ; (8019378 ) 8019340: 2200 movs r2, #0 8019342: 701a strb r2, [r3, #0] tcp_process_refused_data(pcb); 8019344: 6878 ldr r0, [r7, #4] 8019346: f000 f819 bl 801937c if (tcp_active_pcbs_changed) { 801934a: 4b0b ldr r3, [pc, #44] ; (8019378 ) 801934c: 781b ldrb r3, [r3, #0] 801934e: 2b00 cmp r3, #0 8019350: d000 beq.n 8019354 /* application callback has changed the pcb list: restart the loop */ goto tcp_fasttmr_start; 8019352: e7b8 b.n 80192c6 } } pcb = next; 8019354: 683b ldr r3, [r7, #0] 8019356: 607b str r3, [r7, #4] 8019358: e002 b.n 8019360 } else { pcb = pcb->next; 801935a: 687b ldr r3, [r7, #4] 801935c: 68db ldr r3, [r3, #12] 801935e: 607b str r3, [r7, #4] while (pcb != NULL) { 8019360: 687b ldr r3, [r7, #4] 8019362: 2b00 cmp r3, #0 8019364: d1b3 bne.n 80192ce } } } 8019366: bf00 nop 8019368: bf00 nop 801936a: 3708 adds r7, #8 801936c: 46bd mov sp, r7 801936e: bd80 pop {r7, pc} 8019370: 2401a496 .word 0x2401a496 8019374: 2401a48c .word 0x2401a48c 8019378: 2401a494 .word 0x2401a494 0801937c : } /** Pass pcb->refused_data to the recv callback */ err_t tcp_process_refused_data(struct tcp_pcb *pcb) { 801937c: b590 push {r4, r7, lr} 801937e: b085 sub sp, #20 8019380: af00 add r7, sp, #0 8019382: 6078 str r0, [r7, #4] #if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE struct pbuf *rest; #endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG); 8019384: 687b ldr r3, [r7, #4] 8019386: 2b00 cmp r3, #0 8019388: d109 bne.n 801939e 801938a: 4b38 ldr r3, [pc, #224] ; (801946c ) 801938c: f240 6209 movw r2, #1545 ; 0x609 8019390: 4937 ldr r1, [pc, #220] ; (8019470 ) 8019392: 4838 ldr r0, [pc, #224] ; (8019474 ) 8019394: f008 faf8 bl 8021988 8019398: f06f 030f mvn.w r3, #15 801939c: e061 b.n 8019462 #if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE while (pcb->refused_data != NULL) #endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ { err_t err; u8_t refused_flags = pcb->refused_data->flags; 801939e: 687b ldr r3, [r7, #4] 80193a0: 6f9b ldr r3, [r3, #120] ; 0x78 80193a2: 7b5b ldrb r3, [r3, #13] 80193a4: 73bb strb r3, [r7, #14] /* set pcb->refused_data to NULL in case the callback frees it and then closes the pcb */ struct pbuf *refused_data = pcb->refused_data; 80193a6: 687b ldr r3, [r7, #4] 80193a8: 6f9b ldr r3, [r3, #120] ; 0x78 80193aa: 60bb str r3, [r7, #8] #if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE pbuf_split_64k(refused_data, &rest); pcb->refused_data = rest; #else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ pcb->refused_data = NULL; 80193ac: 687b ldr r3, [r7, #4] 80193ae: 2200 movs r2, #0 80193b0: 679a str r2, [r3, #120] ; 0x78 #endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ /* Notify again application with data previously received. */ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n")); TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err); 80193b2: 687b ldr r3, [r7, #4] 80193b4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80193b8: 2b00 cmp r3, #0 80193ba: d00b beq.n 80193d4 80193bc: 687b ldr r3, [r7, #4] 80193be: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 80193c2: 687b ldr r3, [r7, #4] 80193c4: 6918 ldr r0, [r3, #16] 80193c6: 2300 movs r3, #0 80193c8: 68ba ldr r2, [r7, #8] 80193ca: 6879 ldr r1, [r7, #4] 80193cc: 47a0 blx r4 80193ce: 4603 mov r3, r0 80193d0: 73fb strb r3, [r7, #15] 80193d2: e007 b.n 80193e4 80193d4: 2300 movs r3, #0 80193d6: 68ba ldr r2, [r7, #8] 80193d8: 6879 ldr r1, [r7, #4] 80193da: 2000 movs r0, #0 80193dc: f000 f8a6 bl 801952c 80193e0: 4603 mov r3, r0 80193e2: 73fb strb r3, [r7, #15] if (err == ERR_OK) { 80193e4: f997 300f ldrsb.w r3, [r7, #15] 80193e8: 2b00 cmp r3, #0 80193ea: d12b bne.n 8019444 /* did refused_data include a FIN? */ if ((refused_flags & PBUF_FLAG_TCP_FIN) 80193ec: 7bbb ldrb r3, [r7, #14] 80193ee: f003 0320 and.w r3, r3, #32 80193f2: 2b00 cmp r3, #0 80193f4: d034 beq.n 8019460 && (rest == NULL) #endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ ) { /* correct rcv_wnd as the application won't call tcp_recved() for the FIN's seqno */ if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) { 80193f6: 687b ldr r3, [r7, #4] 80193f8: 8d1b ldrh r3, [r3, #40] ; 0x28 80193fa: f241 62d0 movw r2, #5840 ; 0x16d0 80193fe: 4293 cmp r3, r2 8019400: d005 beq.n 801940e pcb->rcv_wnd++; 8019402: 687b ldr r3, [r7, #4] 8019404: 8d1b ldrh r3, [r3, #40] ; 0x28 8019406: 3301 adds r3, #1 8019408: b29a uxth r2, r3 801940a: 687b ldr r3, [r7, #4] 801940c: 851a strh r2, [r3, #40] ; 0x28 } TCP_EVENT_CLOSED(pcb, err); 801940e: 687b ldr r3, [r7, #4] 8019410: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8019414: 2b00 cmp r3, #0 8019416: d00b beq.n 8019430 8019418: 687b ldr r3, [r7, #4] 801941a: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 801941e: 687b ldr r3, [r7, #4] 8019420: 6918 ldr r0, [r3, #16] 8019422: 2300 movs r3, #0 8019424: 2200 movs r2, #0 8019426: 6879 ldr r1, [r7, #4] 8019428: 47a0 blx r4 801942a: 4603 mov r3, r0 801942c: 73fb strb r3, [r7, #15] 801942e: e001 b.n 8019434 8019430: 2300 movs r3, #0 8019432: 73fb strb r3, [r7, #15] if (err == ERR_ABRT) { 8019434: f997 300f ldrsb.w r3, [r7, #15] 8019438: f113 0f0d cmn.w r3, #13 801943c: d110 bne.n 8019460 return ERR_ABRT; 801943e: f06f 030c mvn.w r3, #12 8019442: e00e b.n 8019462 } } } else if (err == ERR_ABRT) { 8019444: f997 300f ldrsb.w r3, [r7, #15] 8019448: f113 0f0d cmn.w r3, #13 801944c: d102 bne.n 8019454 /* if err == ERR_ABRT, 'pcb' is already deallocated */ /* Drop incoming packets because pcb is "full" (only if the incoming segment contains data). */ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n")); return ERR_ABRT; 801944e: f06f 030c mvn.w r3, #12 8019452: e006 b.n 8019462 #if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE if (rest != NULL) { pbuf_cat(refused_data, rest); } #endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ pcb->refused_data = refused_data; 8019454: 687b ldr r3, [r7, #4] 8019456: 68ba ldr r2, [r7, #8] 8019458: 679a str r2, [r3, #120] ; 0x78 return ERR_INPROGRESS; 801945a: f06f 0304 mvn.w r3, #4 801945e: e000 b.n 8019462 } } return ERR_OK; 8019460: 2300 movs r3, #0 } 8019462: 4618 mov r0, r3 8019464: 3714 adds r7, #20 8019466: 46bd mov sp, r7 8019468: bd90 pop {r4, r7, pc} 801946a: bf00 nop 801946c: 08024ba8 .word 0x08024ba8 8019470: 080250b8 .word 0x080250b8 8019474: 08024bec .word 0x08024bec 08019478 : * * @param seg tcp_seg list of TCP segments to free */ void tcp_segs_free(struct tcp_seg *seg) { 8019478: b580 push {r7, lr} 801947a: b084 sub sp, #16 801947c: af00 add r7, sp, #0 801947e: 6078 str r0, [r7, #4] while (seg != NULL) { 8019480: e007 b.n 8019492 struct tcp_seg *next = seg->next; 8019482: 687b ldr r3, [r7, #4] 8019484: 681b ldr r3, [r3, #0] 8019486: 60fb str r3, [r7, #12] tcp_seg_free(seg); 8019488: 6878 ldr r0, [r7, #4] 801948a: f000 f80a bl 80194a2 seg = next; 801948e: 68fb ldr r3, [r7, #12] 8019490: 607b str r3, [r7, #4] while (seg != NULL) { 8019492: 687b ldr r3, [r7, #4] 8019494: 2b00 cmp r3, #0 8019496: d1f4 bne.n 8019482 } } 8019498: bf00 nop 801949a: bf00 nop 801949c: 3710 adds r7, #16 801949e: 46bd mov sp, r7 80194a0: bd80 pop {r7, pc} 080194a2 : * * @param seg single tcp_seg to free */ void tcp_seg_free(struct tcp_seg *seg) { 80194a2: b580 push {r7, lr} 80194a4: b082 sub sp, #8 80194a6: af00 add r7, sp, #0 80194a8: 6078 str r0, [r7, #4] if (seg != NULL) { 80194aa: 687b ldr r3, [r7, #4] 80194ac: 2b00 cmp r3, #0 80194ae: d00c beq.n 80194ca if (seg->p != NULL) { 80194b0: 687b ldr r3, [r7, #4] 80194b2: 685b ldr r3, [r3, #4] 80194b4: 2b00 cmp r3, #0 80194b6: d004 beq.n 80194c2 pbuf_free(seg->p); 80194b8: 687b ldr r3, [r7, #4] 80194ba: 685b ldr r3, [r3, #4] 80194bc: 4618 mov r0, r3 80194be: f7fe fb1b bl 8017af8 #if TCP_DEBUG seg->p = NULL; #endif /* TCP_DEBUG */ } memp_free(MEMP_TCP_SEG, seg); 80194c2: 6879 ldr r1, [r7, #4] 80194c4: 2003 movs r0, #3 80194c6: f7fd fb79 bl 8016bbc } } 80194ca: bf00 nop 80194cc: 3708 adds r7, #8 80194ce: 46bd mov sp, r7 80194d0: bd80 pop {r7, pc} ... 080194d4 : * @param seg the old tcp_seg * @return a copy of seg */ struct tcp_seg * tcp_seg_copy(struct tcp_seg *seg) { 80194d4: b580 push {r7, lr} 80194d6: b084 sub sp, #16 80194d8: af00 add r7, sp, #0 80194da: 6078 str r0, [r7, #4] struct tcp_seg *cseg; LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL); 80194dc: 687b ldr r3, [r7, #4] 80194de: 2b00 cmp r3, #0 80194e0: d106 bne.n 80194f0 80194e2: 4b0f ldr r3, [pc, #60] ; (8019520 ) 80194e4: f240 6282 movw r2, #1666 ; 0x682 80194e8: 490e ldr r1, [pc, #56] ; (8019524 ) 80194ea: 480f ldr r0, [pc, #60] ; (8019528 ) 80194ec: f008 fa4c bl 8021988 cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG); 80194f0: 2003 movs r0, #3 80194f2: f7fd faed bl 8016ad0 80194f6: 60f8 str r0, [r7, #12] if (cseg == NULL) { 80194f8: 68fb ldr r3, [r7, #12] 80194fa: 2b00 cmp r3, #0 80194fc: d101 bne.n 8019502 return NULL; 80194fe: 2300 movs r3, #0 8019500: e00a b.n 8019518 } SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); 8019502: 2214 movs r2, #20 8019504: 6879 ldr r1, [r7, #4] 8019506: 68f8 ldr r0, [r7, #12] 8019508: f008 fc6d bl 8021de6 pbuf_ref(cseg->p); 801950c: 68fb ldr r3, [r7, #12] 801950e: 685b ldr r3, [r3, #4] 8019510: 4618 mov r0, r3 8019512: f7fe fb97 bl 8017c44 return cseg; 8019516: 68fb ldr r3, [r7, #12] } 8019518: 4618 mov r0, r3 801951a: 3710 adds r7, #16 801951c: 46bd mov sp, r7 801951e: bd80 pop {r7, pc} 8019520: 08024ba8 .word 0x08024ba8 8019524: 080250fc .word 0x080250fc 8019528: 08024bec .word 0x08024bec 0801952c : * Default receive callback that is called if the user didn't register * a recv callback for the pcb. */ err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) { 801952c: b580 push {r7, lr} 801952e: b084 sub sp, #16 8019530: af00 add r7, sp, #0 8019532: 60f8 str r0, [r7, #12] 8019534: 60b9 str r1, [r7, #8] 8019536: 607a str r2, [r7, #4] 8019538: 70fb strb r3, [r7, #3] LWIP_UNUSED_ARG(arg); LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG); 801953a: 68bb ldr r3, [r7, #8] 801953c: 2b00 cmp r3, #0 801953e: d109 bne.n 8019554 8019540: 4b12 ldr r3, [pc, #72] ; (801958c ) 8019542: f44f 62d3 mov.w r2, #1688 ; 0x698 8019546: 4912 ldr r1, [pc, #72] ; (8019590 ) 8019548: 4812 ldr r0, [pc, #72] ; (8019594 ) 801954a: f008 fa1d bl 8021988 801954e: f06f 030f mvn.w r3, #15 8019552: e016 b.n 8019582 if (p != NULL) { 8019554: 687b ldr r3, [r7, #4] 8019556: 2b00 cmp r3, #0 8019558: d009 beq.n 801956e tcp_recved(pcb, p->tot_len); 801955a: 687b ldr r3, [r7, #4] 801955c: 891b ldrh r3, [r3, #8] 801955e: 4619 mov r1, r3 8019560: 68b8 ldr r0, [r7, #8] 8019562: f7ff f9b7 bl 80188d4 pbuf_free(p); 8019566: 6878 ldr r0, [r7, #4] 8019568: f7fe fac6 bl 8017af8 801956c: e008 b.n 8019580 } else if (err == ERR_OK) { 801956e: f997 3003 ldrsb.w r3, [r7, #3] 8019572: 2b00 cmp r3, #0 8019574: d104 bne.n 8019580 return tcp_close(pcb); 8019576: 68b8 ldr r0, [r7, #8] 8019578: f7fe ff68 bl 801844c 801957c: 4603 mov r3, r0 801957e: e000 b.n 8019582 } return ERR_OK; 8019580: 2300 movs r3, #0 } 8019582: 4618 mov r0, r3 8019584: 3710 adds r7, #16 8019586: 46bd mov sp, r7 8019588: bd80 pop {r7, pc} 801958a: bf00 nop 801958c: 08024ba8 .word 0x08024ba8 8019590: 08025118 .word 0x08025118 8019594: 08024bec .word 0x08024bec 08019598 : * * @param prio minimum priority */ static void tcp_kill_prio(u8_t prio) { 8019598: b580 push {r7, lr} 801959a: b086 sub sp, #24 801959c: af00 add r7, sp, #0 801959e: 4603 mov r3, r0 80195a0: 71fb strb r3, [r7, #7] struct tcp_pcb *pcb, *inactive; u32_t inactivity; u8_t mprio; mprio = LWIP_MIN(TCP_PRIO_MAX, prio); 80195a2: f997 3007 ldrsb.w r3, [r7, #7] 80195a6: 2b00 cmp r3, #0 80195a8: db01 blt.n 80195ae 80195aa: 79fb ldrb r3, [r7, #7] 80195ac: e000 b.n 80195b0 80195ae: 237f movs r3, #127 ; 0x7f 80195b0: 72fb strb r3, [r7, #11] /* We want to kill connections with a lower prio, so bail out if * supplied prio is 0 - there can never be a lower prio */ if (mprio == 0) { 80195b2: 7afb ldrb r3, [r7, #11] 80195b4: 2b00 cmp r3, #0 80195b6: d034 beq.n 8019622 /* We only want kill connections with a lower prio, so decrement prio by one * and start searching for oldest connection with same or lower priority than mprio. * We want to find the connections with the lowest possible prio, and among * these the one with the longest inactivity time. */ mprio--; 80195b8: 7afb ldrb r3, [r7, #11] 80195ba: 3b01 subs r3, #1 80195bc: 72fb strb r3, [r7, #11] inactivity = 0; 80195be: 2300 movs r3, #0 80195c0: 60fb str r3, [r7, #12] inactive = NULL; 80195c2: 2300 movs r3, #0 80195c4: 613b str r3, [r7, #16] for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { 80195c6: 4b19 ldr r3, [pc, #100] ; (801962c ) 80195c8: 681b ldr r3, [r3, #0] 80195ca: 617b str r3, [r7, #20] 80195cc: e01f b.n 801960e /* lower prio is always a kill candidate */ if ((pcb->prio < mprio) || 80195ce: 697b ldr r3, [r7, #20] 80195d0: 7d5b ldrb r3, [r3, #21] 80195d2: 7afa ldrb r2, [r7, #11] 80195d4: 429a cmp r2, r3 80195d6: d80c bhi.n 80195f2 /* longer inactivity is also a kill candidate */ ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) { 80195d8: 697b ldr r3, [r7, #20] 80195da: 7d5b ldrb r3, [r3, #21] if ((pcb->prio < mprio) || 80195dc: 7afa ldrb r2, [r7, #11] 80195de: 429a cmp r2, r3 80195e0: d112 bne.n 8019608 ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) { 80195e2: 4b13 ldr r3, [pc, #76] ; (8019630 ) 80195e4: 681a ldr r2, [r3, #0] 80195e6: 697b ldr r3, [r7, #20] 80195e8: 6a1b ldr r3, [r3, #32] 80195ea: 1ad3 subs r3, r2, r3 80195ec: 68fa ldr r2, [r7, #12] 80195ee: 429a cmp r2, r3 80195f0: d80a bhi.n 8019608 inactivity = tcp_ticks - pcb->tmr; 80195f2: 4b0f ldr r3, [pc, #60] ; (8019630 ) 80195f4: 681a ldr r2, [r3, #0] 80195f6: 697b ldr r3, [r7, #20] 80195f8: 6a1b ldr r3, [r3, #32] 80195fa: 1ad3 subs r3, r2, r3 80195fc: 60fb str r3, [r7, #12] inactive = pcb; 80195fe: 697b ldr r3, [r7, #20] 8019600: 613b str r3, [r7, #16] mprio = pcb->prio; 8019602: 697b ldr r3, [r7, #20] 8019604: 7d5b ldrb r3, [r3, #21] 8019606: 72fb strb r3, [r7, #11] for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { 8019608: 697b ldr r3, [r7, #20] 801960a: 68db ldr r3, [r3, #12] 801960c: 617b str r3, [r7, #20] 801960e: 697b ldr r3, [r7, #20] 8019610: 2b00 cmp r3, #0 8019612: d1dc bne.n 80195ce } } if (inactive != NULL) { 8019614: 693b ldr r3, [r7, #16] 8019616: 2b00 cmp r3, #0 8019618: d004 beq.n 8019624 LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", (void *)inactive, inactivity)); tcp_abort(inactive); 801961a: 6938 ldr r0, [r7, #16] 801961c: f7ff f85c bl 80186d8 8019620: e000 b.n 8019624 return; 8019622: bf00 nop } } 8019624: 3718 adds r7, #24 8019626: 46bd mov sp, r7 8019628: bd80 pop {r7, pc} 801962a: bf00 nop 801962c: 2401a48c .word 0x2401a48c 8019630: 2401a480 .word 0x2401a480 08019634 : * Kills the oldest connection that is in specific state. * Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available. */ static void tcp_kill_state(enum tcp_state state) { 8019634: b580 push {r7, lr} 8019636: b086 sub sp, #24 8019638: af00 add r7, sp, #0 801963a: 4603 mov r3, r0 801963c: 71fb strb r3, [r7, #7] struct tcp_pcb *pcb, *inactive; u32_t inactivity; LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK)); 801963e: 79fb ldrb r3, [r7, #7] 8019640: 2b08 cmp r3, #8 8019642: d009 beq.n 8019658 8019644: 79fb ldrb r3, [r7, #7] 8019646: 2b09 cmp r3, #9 8019648: d006 beq.n 8019658 801964a: 4b1a ldr r3, [pc, #104] ; (80196b4 ) 801964c: f240 62dd movw r2, #1757 ; 0x6dd 8019650: 4919 ldr r1, [pc, #100] ; (80196b8 ) 8019652: 481a ldr r0, [pc, #104] ; (80196bc ) 8019654: f008 f998 bl 8021988 inactivity = 0; 8019658: 2300 movs r3, #0 801965a: 60fb str r3, [r7, #12] inactive = NULL; 801965c: 2300 movs r3, #0 801965e: 613b str r3, [r7, #16] /* Go through the list of active pcbs and get the oldest pcb that is in state CLOSING/LAST_ACK. */ for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { 8019660: 4b17 ldr r3, [pc, #92] ; (80196c0 ) 8019662: 681b ldr r3, [r3, #0] 8019664: 617b str r3, [r7, #20] 8019666: e017 b.n 8019698 if (pcb->state == state) { 8019668: 697b ldr r3, [r7, #20] 801966a: 7d1b ldrb r3, [r3, #20] 801966c: 79fa ldrb r2, [r7, #7] 801966e: 429a cmp r2, r3 8019670: d10f bne.n 8019692 if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { 8019672: 4b14 ldr r3, [pc, #80] ; (80196c4 ) 8019674: 681a ldr r2, [r3, #0] 8019676: 697b ldr r3, [r7, #20] 8019678: 6a1b ldr r3, [r3, #32] 801967a: 1ad3 subs r3, r2, r3 801967c: 68fa ldr r2, [r7, #12] 801967e: 429a cmp r2, r3 8019680: d807 bhi.n 8019692 inactivity = tcp_ticks - pcb->tmr; 8019682: 4b10 ldr r3, [pc, #64] ; (80196c4 ) 8019684: 681a ldr r2, [r3, #0] 8019686: 697b ldr r3, [r7, #20] 8019688: 6a1b ldr r3, [r3, #32] 801968a: 1ad3 subs r3, r2, r3 801968c: 60fb str r3, [r7, #12] inactive = pcb; 801968e: 697b ldr r3, [r7, #20] 8019690: 613b str r3, [r7, #16] for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { 8019692: 697b ldr r3, [r7, #20] 8019694: 68db ldr r3, [r3, #12] 8019696: 617b str r3, [r7, #20] 8019698: 697b ldr r3, [r7, #20] 801969a: 2b00 cmp r3, #0 801969c: d1e4 bne.n 8019668 } } } if (inactive != NULL) { 801969e: 693b ldr r3, [r7, #16] 80196a0: 2b00 cmp r3, #0 80196a2: d003 beq.n 80196ac LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n", tcp_state_str[state], (void *)inactive, inactivity)); /* Don't send a RST, since no data is lost. */ tcp_abandon(inactive, 0); 80196a4: 2100 movs r1, #0 80196a6: 6938 ldr r0, [r7, #16] 80196a8: f7fe ff58 bl 801855c } } 80196ac: bf00 nop 80196ae: 3718 adds r7, #24 80196b0: 46bd mov sp, r7 80196b2: bd80 pop {r7, pc} 80196b4: 08024ba8 .word 0x08024ba8 80196b8: 08025134 .word 0x08025134 80196bc: 08024bec .word 0x08024bec 80196c0: 2401a48c .word 0x2401a48c 80196c4: 2401a480 .word 0x2401a480 080196c8 : * Kills the oldest connection that is in TIME_WAIT state. * Called from tcp_alloc() if no more connections are available. */ static void tcp_kill_timewait(void) { 80196c8: b580 push {r7, lr} 80196ca: b084 sub sp, #16 80196cc: af00 add r7, sp, #0 struct tcp_pcb *pcb, *inactive; u32_t inactivity; inactivity = 0; 80196ce: 2300 movs r3, #0 80196d0: 607b str r3, [r7, #4] inactive = NULL; 80196d2: 2300 movs r3, #0 80196d4: 60bb str r3, [r7, #8] /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */ for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { 80196d6: 4b12 ldr r3, [pc, #72] ; (8019720 ) 80196d8: 681b ldr r3, [r3, #0] 80196da: 60fb str r3, [r7, #12] 80196dc: e012 b.n 8019704 if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { 80196de: 4b11 ldr r3, [pc, #68] ; (8019724 ) 80196e0: 681a ldr r2, [r3, #0] 80196e2: 68fb ldr r3, [r7, #12] 80196e4: 6a1b ldr r3, [r3, #32] 80196e6: 1ad3 subs r3, r2, r3 80196e8: 687a ldr r2, [r7, #4] 80196ea: 429a cmp r2, r3 80196ec: d807 bhi.n 80196fe inactivity = tcp_ticks - pcb->tmr; 80196ee: 4b0d ldr r3, [pc, #52] ; (8019724 ) 80196f0: 681a ldr r2, [r3, #0] 80196f2: 68fb ldr r3, [r7, #12] 80196f4: 6a1b ldr r3, [r3, #32] 80196f6: 1ad3 subs r3, r2, r3 80196f8: 607b str r3, [r7, #4] inactive = pcb; 80196fa: 68fb ldr r3, [r7, #12] 80196fc: 60bb str r3, [r7, #8] for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { 80196fe: 68fb ldr r3, [r7, #12] 8019700: 68db ldr r3, [r3, #12] 8019702: 60fb str r3, [r7, #12] 8019704: 68fb ldr r3, [r7, #12] 8019706: 2b00 cmp r3, #0 8019708: d1e9 bne.n 80196de } } if (inactive != NULL) { 801970a: 68bb ldr r3, [r7, #8] 801970c: 2b00 cmp r3, #0 801970e: d002 beq.n 8019716 LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", (void *)inactive, inactivity)); tcp_abort(inactive); 8019710: 68b8 ldr r0, [r7, #8] 8019712: f7fe ffe1 bl 80186d8 } } 8019716: bf00 nop 8019718: 3710 adds r7, #16 801971a: 46bd mov sp, r7 801971c: bd80 pop {r7, pc} 801971e: bf00 nop 8019720: 2401a490 .word 0x2401a490 8019724: 2401a480 .word 0x2401a480 08019728 : * now send the FIN (which failed before), the pcb might be in a state that is * OK for us to now free it. */ static void tcp_handle_closepend(void) { 8019728: b580 push {r7, lr} 801972a: b082 sub sp, #8 801972c: af00 add r7, sp, #0 struct tcp_pcb *pcb = tcp_active_pcbs; 801972e: 4b10 ldr r3, [pc, #64] ; (8019770 ) 8019730: 681b ldr r3, [r3, #0] 8019732: 607b str r3, [r7, #4] while (pcb != NULL) { 8019734: e014 b.n 8019760 struct tcp_pcb *next = pcb->next; 8019736: 687b ldr r3, [r7, #4] 8019738: 68db ldr r3, [r3, #12] 801973a: 603b str r3, [r7, #0] /* send pending FIN */ if (pcb->flags & TF_CLOSEPEND) { 801973c: 687b ldr r3, [r7, #4] 801973e: 8b5b ldrh r3, [r3, #26] 8019740: f003 0308 and.w r3, r3, #8 8019744: 2b00 cmp r3, #0 8019746: d009 beq.n 801975c LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n")); tcp_clear_flags(pcb, TF_CLOSEPEND); 8019748: 687b ldr r3, [r7, #4] 801974a: 8b5b ldrh r3, [r3, #26] 801974c: f023 0308 bic.w r3, r3, #8 8019750: b29a uxth r2, r3 8019752: 687b ldr r3, [r7, #4] 8019754: 835a strh r2, [r3, #26] tcp_close_shutdown_fin(pcb); 8019756: 6878 ldr r0, [r7, #4] 8019758: f7fe fe0e bl 8018378 } pcb = next; 801975c: 683b ldr r3, [r7, #0] 801975e: 607b str r3, [r7, #4] while (pcb != NULL) { 8019760: 687b ldr r3, [r7, #4] 8019762: 2b00 cmp r3, #0 8019764: d1e7 bne.n 8019736 } } 8019766: bf00 nop 8019768: bf00 nop 801976a: 3708 adds r7, #8 801976c: 46bd mov sp, r7 801976e: bd80 pop {r7, pc} 8019770: 2401a48c .word 0x2401a48c 08019774 : * @param prio priority for the new pcb * @return a new tcp_pcb that initially is in state CLOSED */ struct tcp_pcb * tcp_alloc(u8_t prio) { 8019774: b580 push {r7, lr} 8019776: b084 sub sp, #16 8019778: af00 add r7, sp, #0 801977a: 4603 mov r3, r0 801977c: 71fb strb r3, [r7, #7] struct tcp_pcb *pcb; LWIP_ASSERT_CORE_LOCKED(); pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); 801977e: 2001 movs r0, #1 8019780: f7fd f9a6 bl 8016ad0 8019784: 60f8 str r0, [r7, #12] if (pcb == NULL) { 8019786: 68fb ldr r3, [r7, #12] 8019788: 2b00 cmp r3, #0 801978a: d126 bne.n 80197da /* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */ tcp_handle_closepend(); 801978c: f7ff ffcc bl 8019728 /* Try killing oldest connection in TIME-WAIT. */ LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); tcp_kill_timewait(); 8019790: f7ff ff9a bl 80196c8 /* Try to allocate a tcp_pcb again. */ pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); 8019794: 2001 movs r0, #1 8019796: f7fd f99b bl 8016ad0 801979a: 60f8 str r0, [r7, #12] if (pcb == NULL) { 801979c: 68fb ldr r3, [r7, #12] 801979e: 2b00 cmp r3, #0 80197a0: d11b bne.n 80197da /* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */ LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n")); tcp_kill_state(LAST_ACK); 80197a2: 2009 movs r0, #9 80197a4: f7ff ff46 bl 8019634 /* Try to allocate a tcp_pcb again. */ pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); 80197a8: 2001 movs r0, #1 80197aa: f7fd f991 bl 8016ad0 80197ae: 60f8 str r0, [r7, #12] if (pcb == NULL) { 80197b0: 68fb ldr r3, [r7, #12] 80197b2: 2b00 cmp r3, #0 80197b4: d111 bne.n 80197da /* Try killing oldest connection in CLOSING. */ LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n")); tcp_kill_state(CLOSING); 80197b6: 2008 movs r0, #8 80197b8: f7ff ff3c bl 8019634 /* Try to allocate a tcp_pcb again. */ pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); 80197bc: 2001 movs r0, #1 80197be: f7fd f987 bl 8016ad0 80197c2: 60f8 str r0, [r7, #12] if (pcb == NULL) { 80197c4: 68fb ldr r3, [r7, #12] 80197c6: 2b00 cmp r3, #0 80197c8: d107 bne.n 80197da /* Try killing oldest active connection with lower priority than the new one. */ LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio)); tcp_kill_prio(prio); 80197ca: 79fb ldrb r3, [r7, #7] 80197cc: 4618 mov r0, r3 80197ce: f7ff fee3 bl 8019598 /* Try to allocate a tcp_pcb again. */ pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); 80197d2: 2001 movs r0, #1 80197d4: f7fd f97c bl 8016ad0 80197d8: 60f8 str r0, [r7, #12] if (pcb != NULL) { /* adjust err stats: memp_malloc failed above */ MEMP_STATS_DEC(err, MEMP_TCP_PCB); } } if (pcb != NULL) { 80197da: 68fb ldr r3, [r7, #12] 80197dc: 2b00 cmp r3, #0 80197de: d03f beq.n 8019860 /* zero out the whole pcb, so there is no need to initialize members to zero */ memset(pcb, 0, sizeof(struct tcp_pcb)); 80197e0: 229c movs r2, #156 ; 0x9c 80197e2: 2100 movs r1, #0 80197e4: 68f8 ldr r0, [r7, #12] 80197e6: f008 fa7b bl 8021ce0 pcb->prio = prio; 80197ea: 68fb ldr r3, [r7, #12] 80197ec: 79fa ldrb r2, [r7, #7] 80197ee: 755a strb r2, [r3, #21] pcb->snd_buf = TCP_SND_BUF; 80197f0: 68fb ldr r3, [r7, #12] 80197f2: f241 62d0 movw r2, #5840 ; 0x16d0 80197f6: f8a3 2064 strh.w r2, [r3, #100] ; 0x64 /* Start with a window that does not need scaling. When window scaling is enabled and used, the window is enlarged when both sides agree on scaling. */ pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND); 80197fa: 68fb ldr r3, [r7, #12] 80197fc: f241 62d0 movw r2, #5840 ; 0x16d0 8019800: 855a strh r2, [r3, #42] ; 0x2a 8019802: 68fb ldr r3, [r7, #12] 8019804: 8d5a ldrh r2, [r3, #42] ; 0x2a 8019806: 68fb ldr r3, [r7, #12] 8019808: 851a strh r2, [r3, #40] ; 0x28 pcb->ttl = TCP_TTL; 801980a: 68fb ldr r3, [r7, #12] 801980c: 22ff movs r2, #255 ; 0xff 801980e: 72da strb r2, [r3, #11] /* As initial send MSS, we use TCP_MSS but limit it to 536. The send MSS is updated when an MSS option is received. */ pcb->mss = INITIAL_MSS; 8019810: 68fb ldr r3, [r7, #12] 8019812: f44f 7206 mov.w r2, #536 ; 0x218 8019816: 865a strh r2, [r3, #50] ; 0x32 pcb->rto = 3000 / TCP_SLOW_INTERVAL; 8019818: 68fb ldr r3, [r7, #12] 801981a: 2206 movs r2, #6 801981c: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 pcb->sv = 3000 / TCP_SLOW_INTERVAL; 8019820: 68fb ldr r3, [r7, #12] 8019822: 2206 movs r2, #6 8019824: 87da strh r2, [r3, #62] ; 0x3e pcb->rtime = -1; 8019826: 68fb ldr r3, [r7, #12] 8019828: f64f 72ff movw r2, #65535 ; 0xffff 801982c: 861a strh r2, [r3, #48] ; 0x30 pcb->cwnd = 1; 801982e: 68fb ldr r3, [r7, #12] 8019830: 2201 movs r2, #1 8019832: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 pcb->tmr = tcp_ticks; 8019836: 4b0d ldr r3, [pc, #52] ; (801986c ) 8019838: 681a ldr r2, [r3, #0] 801983a: 68fb ldr r3, [r7, #12] 801983c: 621a str r2, [r3, #32] pcb->last_timer = tcp_timer_ctr; 801983e: 4b0c ldr r3, [pc, #48] ; (8019870 ) 8019840: 781a ldrb r2, [r3, #0] 8019842: 68fb ldr r3, [r7, #12] 8019844: 779a strb r2, [r3, #30] of using the largest advertised receive window. We've seen complications with receiving TCPs that use window scaling and/or window auto-tuning where the initial advertised window is very small and then grows rapidly once the connection is established. To avoid these complications, we set ssthresh to the largest effective cwnd (amount of in-flight data) that the sender can have. */ pcb->ssthresh = TCP_SND_BUF; 8019846: 68fb ldr r3, [r7, #12] 8019848: f241 62d0 movw r2, #5840 ; 0x16d0 801984c: f8a3 204a strh.w r2, [r3, #74] ; 0x4a #if LWIP_CALLBACK_API pcb->recv = tcp_recv_null; 8019850: 68fb ldr r3, [r7, #12] 8019852: 4a08 ldr r2, [pc, #32] ; (8019874 ) 8019854: f8c3 2084 str.w r2, [r3, #132] ; 0x84 #endif /* LWIP_CALLBACK_API */ /* Init KEEPALIVE timer */ pcb->keep_idle = TCP_KEEPIDLE_DEFAULT; 8019858: 68fb ldr r3, [r7, #12] 801985a: 4a07 ldr r2, [pc, #28] ; (8019878 ) 801985c: f8c3 2094 str.w r2, [r3, #148] ; 0x94 #if LWIP_TCP_KEEPALIVE pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT; pcb->keep_cnt = TCP_KEEPCNT_DEFAULT; #endif /* LWIP_TCP_KEEPALIVE */ } return pcb; 8019860: 68fb ldr r3, [r7, #12] } 8019862: 4618 mov r0, r3 8019864: 3710 adds r7, #16 8019866: 46bd mov sp, r7 8019868: bd80 pop {r7, pc} 801986a: bf00 nop 801986c: 2401a480 .word 0x2401a480 8019870: 2401a496 .word 0x2401a496 8019874: 0801952d .word 0x0801952d 8019878: 006ddd00 .word 0x006ddd00 0801987c : * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE. * @return a new tcp_pcb that initially is in state CLOSED */ struct tcp_pcb * tcp_new_ip_type(u8_t type) { 801987c: b580 push {r7, lr} 801987e: b084 sub sp, #16 8019880: af00 add r7, sp, #0 8019882: 4603 mov r3, r0 8019884: 71fb strb r3, [r7, #7] struct tcp_pcb *pcb; pcb = tcp_alloc(TCP_PRIO_NORMAL); 8019886: 2040 movs r0, #64 ; 0x40 8019888: f7ff ff74 bl 8019774 801988c: 60f8 str r0, [r7, #12] IP_SET_TYPE_VAL(pcb->remote_ip, type); } #else LWIP_UNUSED_ARG(type); #endif /* LWIP_IPV4 && LWIP_IPV6 */ return pcb; 801988e: 68fb ldr r3, [r7, #12] } 8019890: 4618 mov r0, r3 8019892: 3710 adds r7, #16 8019894: 46bd mov sp, r7 8019896: bd80 pop {r7, pc} 08019898 : * @param pcb tcp_pcb to set the callback argument * @param arg void pointer argument to pass to callback functions */ void tcp_arg(struct tcp_pcb *pcb, void *arg) { 8019898: b480 push {r7} 801989a: b083 sub sp, #12 801989c: af00 add r7, sp, #0 801989e: 6078 str r0, [r7, #4] 80198a0: 6039 str r1, [r7, #0] LWIP_ASSERT_CORE_LOCKED(); /* This function is allowed to be called for both listen pcbs and connection pcbs. */ if (pcb != NULL) { 80198a2: 687b ldr r3, [r7, #4] 80198a4: 2b00 cmp r3, #0 80198a6: d002 beq.n 80198ae pcb->callback_arg = arg; 80198a8: 687b ldr r3, [r7, #4] 80198aa: 683a ldr r2, [r7, #0] 80198ac: 611a str r2, [r3, #16] } } 80198ae: bf00 nop 80198b0: 370c adds r7, #12 80198b2: 46bd mov sp, r7 80198b4: f85d 7b04 ldr.w r7, [sp], #4 80198b8: 4770 bx lr ... 080198bc : * @param pcb tcp_pcb to set the recv callback * @param recv callback function to call for this pcb when data is received */ void tcp_recv(struct tcp_pcb *pcb, tcp_recv_fn recv) { 80198bc: b580 push {r7, lr} 80198be: b082 sub sp, #8 80198c0: af00 add r7, sp, #0 80198c2: 6078 str r0, [r7, #4] 80198c4: 6039 str r1, [r7, #0] LWIP_ASSERT_CORE_LOCKED(); if (pcb != NULL) { 80198c6: 687b ldr r3, [r7, #4] 80198c8: 2b00 cmp r3, #0 80198ca: d00e beq.n 80198ea LWIP_ASSERT("invalid socket state for recv callback", pcb->state != LISTEN); 80198cc: 687b ldr r3, [r7, #4] 80198ce: 7d1b ldrb r3, [r3, #20] 80198d0: 2b01 cmp r3, #1 80198d2: d106 bne.n 80198e2 80198d4: 4b07 ldr r3, [pc, #28] ; (80198f4 ) 80198d6: f240 72df movw r2, #2015 ; 0x7df 80198da: 4907 ldr r1, [pc, #28] ; (80198f8 ) 80198dc: 4807 ldr r0, [pc, #28] ; (80198fc ) 80198de: f008 f853 bl 8021988 pcb->recv = recv; 80198e2: 687b ldr r3, [r7, #4] 80198e4: 683a ldr r2, [r7, #0] 80198e6: f8c3 2084 str.w r2, [r3, #132] ; 0x84 } } 80198ea: bf00 nop 80198ec: 3708 adds r7, #8 80198ee: 46bd mov sp, r7 80198f0: bd80 pop {r7, pc} 80198f2: bf00 nop 80198f4: 08024ba8 .word 0x08024ba8 80198f8: 08025144 .word 0x08025144 80198fc: 08024bec .word 0x08024bec 08019900 : * @param pcb tcp_pcb to set the sent callback * @param sent callback function to call for this pcb when data is successfully sent */ void tcp_sent(struct tcp_pcb *pcb, tcp_sent_fn sent) { 8019900: b580 push {r7, lr} 8019902: b082 sub sp, #8 8019904: af00 add r7, sp, #0 8019906: 6078 str r0, [r7, #4] 8019908: 6039 str r1, [r7, #0] LWIP_ASSERT_CORE_LOCKED(); if (pcb != NULL) { 801990a: 687b ldr r3, [r7, #4] 801990c: 2b00 cmp r3, #0 801990e: d00e beq.n 801992e LWIP_ASSERT("invalid socket state for sent callback", pcb->state != LISTEN); 8019910: 687b ldr r3, [r7, #4] 8019912: 7d1b ldrb r3, [r3, #20] 8019914: 2b01 cmp r3, #1 8019916: d106 bne.n 8019926 8019918: 4b07 ldr r3, [pc, #28] ; (8019938 ) 801991a: f240 72f3 movw r2, #2035 ; 0x7f3 801991e: 4907 ldr r1, [pc, #28] ; (801993c ) 8019920: 4807 ldr r0, [pc, #28] ; (8019940 ) 8019922: f008 f831 bl 8021988 pcb->sent = sent; 8019926: 687b ldr r3, [r7, #4] 8019928: 683a ldr r2, [r7, #0] 801992a: f8c3 2080 str.w r2, [r3, #128] ; 0x80 } } 801992e: bf00 nop 8019930: 3708 adds r7, #8 8019932: 46bd mov sp, r7 8019934: bd80 pop {r7, pc} 8019936: bf00 nop 8019938: 08024ba8 .word 0x08024ba8 801993c: 0802516c .word 0x0802516c 8019940: 08024bec .word 0x08024bec 08019944 : * @param err callback function to call for this pcb when a fatal error * has occurred on the connection */ void tcp_err(struct tcp_pcb *pcb, tcp_err_fn err) { 8019944: b580 push {r7, lr} 8019946: b082 sub sp, #8 8019948: af00 add r7, sp, #0 801994a: 6078 str r0, [r7, #4] 801994c: 6039 str r1, [r7, #0] LWIP_ASSERT_CORE_LOCKED(); if (pcb != NULL) { 801994e: 687b ldr r3, [r7, #4] 8019950: 2b00 cmp r3, #0 8019952: d00e beq.n 8019972 LWIP_ASSERT("invalid socket state for err callback", pcb->state != LISTEN); 8019954: 687b ldr r3, [r7, #4] 8019956: 7d1b ldrb r3, [r3, #20] 8019958: 2b01 cmp r3, #1 801995a: d106 bne.n 801996a 801995c: 4b07 ldr r3, [pc, #28] ; (801997c ) 801995e: f640 020d movw r2, #2061 ; 0x80d 8019962: 4907 ldr r1, [pc, #28] ; (8019980 ) 8019964: 4807 ldr r0, [pc, #28] ; (8019984 ) 8019966: f008 f80f bl 8021988 pcb->errf = err; 801996a: 687b ldr r3, [r7, #4] 801996c: 683a ldr r2, [r7, #0] 801996e: f8c3 2090 str.w r2, [r3, #144] ; 0x90 } } 8019972: bf00 nop 8019974: 3708 adds r7, #8 8019976: 46bd mov sp, r7 8019978: bd80 pop {r7, pc} 801997a: bf00 nop 801997c: 08024ba8 .word 0x08024ba8 8019980: 08025194 .word 0x08025194 8019984: 08024bec .word 0x08024bec 08019988 : * @param accept callback function to call for this pcb when LISTENing * connection has been connected to another host */ void tcp_accept(struct tcp_pcb *pcb, tcp_accept_fn accept) { 8019988: b480 push {r7} 801998a: b085 sub sp, #20 801998c: af00 add r7, sp, #0 801998e: 6078 str r0, [r7, #4] 8019990: 6039 str r1, [r7, #0] LWIP_ASSERT_CORE_LOCKED(); if ((pcb != NULL) && (pcb->state == LISTEN)) { 8019992: 687b ldr r3, [r7, #4] 8019994: 2b00 cmp r3, #0 8019996: d008 beq.n 80199aa 8019998: 687b ldr r3, [r7, #4] 801999a: 7d1b ldrb r3, [r3, #20] 801999c: 2b01 cmp r3, #1 801999e: d104 bne.n 80199aa struct tcp_pcb_listen *lpcb = (struct tcp_pcb_listen *)pcb; 80199a0: 687b ldr r3, [r7, #4] 80199a2: 60fb str r3, [r7, #12] lpcb->accept = accept; 80199a4: 68fb ldr r3, [r7, #12] 80199a6: 683a ldr r2, [r7, #0] 80199a8: 619a str r2, [r3, #24] } } 80199aa: bf00 nop 80199ac: 3714 adds r7, #20 80199ae: 46bd mov sp, r7 80199b0: f85d 7b04 ldr.w r7, [sp], #4 80199b4: 4770 bx lr ... 080199b8 : * the application may use the polling functionality to call tcp_write() * again when the connection has been idle for a while. */ void tcp_poll(struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval) { 80199b8: b580 push {r7, lr} 80199ba: b084 sub sp, #16 80199bc: af00 add r7, sp, #0 80199be: 60f8 str r0, [r7, #12] 80199c0: 60b9 str r1, [r7, #8] 80199c2: 4613 mov r3, r2 80199c4: 71fb strb r3, [r7, #7] LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("tcp_poll: invalid pcb", pcb != NULL, return); 80199c6: 68fb ldr r3, [r7, #12] 80199c8: 2b00 cmp r3, #0 80199ca: d107 bne.n 80199dc 80199cc: 4b0e ldr r3, [pc, #56] ; (8019a08 ) 80199ce: f640 023d movw r2, #2109 ; 0x83d 80199d2: 490e ldr r1, [pc, #56] ; (8019a0c ) 80199d4: 480e ldr r0, [pc, #56] ; (8019a10 ) 80199d6: f007 ffd7 bl 8021988 80199da: e011 b.n 8019a00 LWIP_ASSERT("invalid socket state for poll", pcb->state != LISTEN); 80199dc: 68fb ldr r3, [r7, #12] 80199de: 7d1b ldrb r3, [r3, #20] 80199e0: 2b01 cmp r3, #1 80199e2: d106 bne.n 80199f2 80199e4: 4b08 ldr r3, [pc, #32] ; (8019a08 ) 80199e6: f640 023e movw r2, #2110 ; 0x83e 80199ea: 490a ldr r1, [pc, #40] ; (8019a14 ) 80199ec: 4808 ldr r0, [pc, #32] ; (8019a10 ) 80199ee: f007 ffcb bl 8021988 #if LWIP_CALLBACK_API pcb->poll = poll; 80199f2: 68fb ldr r3, [r7, #12] 80199f4: 68ba ldr r2, [r7, #8] 80199f6: f8c3 208c str.w r2, [r3, #140] ; 0x8c #else /* LWIP_CALLBACK_API */ LWIP_UNUSED_ARG(poll); #endif /* LWIP_CALLBACK_API */ pcb->pollinterval = interval; 80199fa: 68fb ldr r3, [r7, #12] 80199fc: 79fa ldrb r2, [r7, #7] 80199fe: 775a strb r2, [r3, #29] } 8019a00: 3710 adds r7, #16 8019a02: 46bd mov sp, r7 8019a04: bd80 pop {r7, pc} 8019a06: bf00 nop 8019a08: 08024ba8 .word 0x08024ba8 8019a0c: 080251bc .word 0x080251bc 8019a10: 08024bec .word 0x08024bec 8019a14: 080251d4 .word 0x080251d4 08019a18 : * * @param pcb tcp_pcb to purge. The pcb itself is not deallocated! */ void tcp_pcb_purge(struct tcp_pcb *pcb) { 8019a18: b580 push {r7, lr} 8019a1a: b082 sub sp, #8 8019a1c: af00 add r7, sp, #0 8019a1e: 6078 str r0, [r7, #4] LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return); 8019a20: 687b ldr r3, [r7, #4] 8019a22: 2b00 cmp r3, #0 8019a24: d107 bne.n 8019a36 8019a26: 4b21 ldr r3, [pc, #132] ; (8019aac ) 8019a28: f640 0251 movw r2, #2129 ; 0x851 8019a2c: 4920 ldr r1, [pc, #128] ; (8019ab0 ) 8019a2e: 4821 ldr r0, [pc, #132] ; (8019ab4 ) 8019a30: f007 ffaa bl 8021988 8019a34: e037 b.n 8019aa6 if (pcb->state != CLOSED && 8019a36: 687b ldr r3, [r7, #4] 8019a38: 7d1b ldrb r3, [r3, #20] 8019a3a: 2b00 cmp r3, #0 8019a3c: d033 beq.n 8019aa6 pcb->state != TIME_WAIT && 8019a3e: 687b ldr r3, [r7, #4] 8019a40: 7d1b ldrb r3, [r3, #20] if (pcb->state != CLOSED && 8019a42: 2b0a cmp r3, #10 8019a44: d02f beq.n 8019aa6 pcb->state != LISTEN) { 8019a46: 687b ldr r3, [r7, #4] 8019a48: 7d1b ldrb r3, [r3, #20] pcb->state != TIME_WAIT && 8019a4a: 2b01 cmp r3, #1 8019a4c: d02b beq.n 8019aa6 LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); tcp_backlog_accepted(pcb); if (pcb->refused_data != NULL) { 8019a4e: 687b ldr r3, [r7, #4] 8019a50: 6f9b ldr r3, [r3, #120] ; 0x78 8019a52: 2b00 cmp r3, #0 8019a54: d007 beq.n 8019a66 LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n")); pbuf_free(pcb->refused_data); 8019a56: 687b ldr r3, [r7, #4] 8019a58: 6f9b ldr r3, [r3, #120] ; 0x78 8019a5a: 4618 mov r0, r3 8019a5c: f7fe f84c bl 8017af8 pcb->refused_data = NULL; 8019a60: 687b ldr r3, [r7, #4] 8019a62: 2200 movs r2, #0 8019a64: 679a str r2, [r3, #120] ; 0x78 } if (pcb->unacked != NULL) { LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); } #if TCP_QUEUE_OOSEQ if (pcb->ooseq != NULL) { 8019a66: 687b ldr r3, [r7, #4] 8019a68: 6f5b ldr r3, [r3, #116] ; 0x74 8019a6a: 2b00 cmp r3, #0 8019a6c: d002 beq.n 8019a74 LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); tcp_free_ooseq(pcb); 8019a6e: 6878 ldr r0, [r7, #4] 8019a70: f000 f98c bl 8019d8c } #endif /* TCP_QUEUE_OOSEQ */ /* Stop the retransmission timer as it will expect data on unacked queue if it fires */ pcb->rtime = -1; 8019a74: 687b ldr r3, [r7, #4] 8019a76: f64f 72ff movw r2, #65535 ; 0xffff 8019a7a: 861a strh r2, [r3, #48] ; 0x30 tcp_segs_free(pcb->unsent); 8019a7c: 687b ldr r3, [r7, #4] 8019a7e: 6edb ldr r3, [r3, #108] ; 0x6c 8019a80: 4618 mov r0, r3 8019a82: f7ff fcf9 bl 8019478 tcp_segs_free(pcb->unacked); 8019a86: 687b ldr r3, [r7, #4] 8019a88: 6f1b ldr r3, [r3, #112] ; 0x70 8019a8a: 4618 mov r0, r3 8019a8c: f7ff fcf4 bl 8019478 pcb->unacked = pcb->unsent = NULL; 8019a90: 687b ldr r3, [r7, #4] 8019a92: 2200 movs r2, #0 8019a94: 66da str r2, [r3, #108] ; 0x6c 8019a96: 687b ldr r3, [r7, #4] 8019a98: 6eda ldr r2, [r3, #108] ; 0x6c 8019a9a: 687b ldr r3, [r7, #4] 8019a9c: 671a str r2, [r3, #112] ; 0x70 #if TCP_OVERSIZE pcb->unsent_oversize = 0; 8019a9e: 687b ldr r3, [r7, #4] 8019aa0: 2200 movs r2, #0 8019aa2: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 #endif /* TCP_OVERSIZE */ } } 8019aa6: 3708 adds r7, #8 8019aa8: 46bd mov sp, r7 8019aaa: bd80 pop {r7, pc} 8019aac: 08024ba8 .word 0x08024ba8 8019ab0: 080251f4 .word 0x080251f4 8019ab4: 08024bec .word 0x08024bec 08019ab8 : * @param pcblist PCB list to purge. * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated! */ void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) { 8019ab8: b580 push {r7, lr} 8019aba: b084 sub sp, #16 8019abc: af00 add r7, sp, #0 8019abe: 6078 str r0, [r7, #4] 8019ac0: 6039 str r1, [r7, #0] LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL); 8019ac2: 683b ldr r3, [r7, #0] 8019ac4: 2b00 cmp r3, #0 8019ac6: d106 bne.n 8019ad6 8019ac8: 4b3e ldr r3, [pc, #248] ; (8019bc4 ) 8019aca: f640 0283 movw r2, #2179 ; 0x883 8019ace: 493e ldr r1, [pc, #248] ; (8019bc8 ) 8019ad0: 483e ldr r0, [pc, #248] ; (8019bcc ) 8019ad2: f007 ff59 bl 8021988 LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL); 8019ad6: 687b ldr r3, [r7, #4] 8019ad8: 2b00 cmp r3, #0 8019ada: d106 bne.n 8019aea 8019adc: 4b39 ldr r3, [pc, #228] ; (8019bc4 ) 8019ade: f640 0284 movw r2, #2180 ; 0x884 8019ae2: 493b ldr r1, [pc, #236] ; (8019bd0 ) 8019ae4: 4839 ldr r0, [pc, #228] ; (8019bcc ) 8019ae6: f007 ff4f bl 8021988 TCP_RMV(pcblist, pcb); 8019aea: 687b ldr r3, [r7, #4] 8019aec: 681b ldr r3, [r3, #0] 8019aee: 683a ldr r2, [r7, #0] 8019af0: 429a cmp r2, r3 8019af2: d105 bne.n 8019b00 8019af4: 687b ldr r3, [r7, #4] 8019af6: 681b ldr r3, [r3, #0] 8019af8: 68da ldr r2, [r3, #12] 8019afa: 687b ldr r3, [r7, #4] 8019afc: 601a str r2, [r3, #0] 8019afe: e013 b.n 8019b28 8019b00: 687b ldr r3, [r7, #4] 8019b02: 681b ldr r3, [r3, #0] 8019b04: 60fb str r3, [r7, #12] 8019b06: e00c b.n 8019b22 8019b08: 68fb ldr r3, [r7, #12] 8019b0a: 68db ldr r3, [r3, #12] 8019b0c: 683a ldr r2, [r7, #0] 8019b0e: 429a cmp r2, r3 8019b10: d104 bne.n 8019b1c 8019b12: 683b ldr r3, [r7, #0] 8019b14: 68da ldr r2, [r3, #12] 8019b16: 68fb ldr r3, [r7, #12] 8019b18: 60da str r2, [r3, #12] 8019b1a: e005 b.n 8019b28 8019b1c: 68fb ldr r3, [r7, #12] 8019b1e: 68db ldr r3, [r3, #12] 8019b20: 60fb str r3, [r7, #12] 8019b22: 68fb ldr r3, [r7, #12] 8019b24: 2b00 cmp r3, #0 8019b26: d1ef bne.n 8019b08 8019b28: 683b ldr r3, [r7, #0] 8019b2a: 2200 movs r2, #0 8019b2c: 60da str r2, [r3, #12] tcp_pcb_purge(pcb); 8019b2e: 6838 ldr r0, [r7, #0] 8019b30: f7ff ff72 bl 8019a18 /* if there is an outstanding delayed ACKs, send it */ if ((pcb->state != TIME_WAIT) && 8019b34: 683b ldr r3, [r7, #0] 8019b36: 7d1b ldrb r3, [r3, #20] 8019b38: 2b0a cmp r3, #10 8019b3a: d013 beq.n 8019b64 (pcb->state != LISTEN) && 8019b3c: 683b ldr r3, [r7, #0] 8019b3e: 7d1b ldrb r3, [r3, #20] if ((pcb->state != TIME_WAIT) && 8019b40: 2b01 cmp r3, #1 8019b42: d00f beq.n 8019b64 (pcb->flags & TF_ACK_DELAY)) { 8019b44: 683b ldr r3, [r7, #0] 8019b46: 8b5b ldrh r3, [r3, #26] 8019b48: f003 0301 and.w r3, r3, #1 (pcb->state != LISTEN) && 8019b4c: 2b00 cmp r3, #0 8019b4e: d009 beq.n 8019b64 tcp_ack_now(pcb); 8019b50: 683b ldr r3, [r7, #0] 8019b52: 8b5b ldrh r3, [r3, #26] 8019b54: f043 0302 orr.w r3, r3, #2 8019b58: b29a uxth r2, r3 8019b5a: 683b ldr r3, [r7, #0] 8019b5c: 835a strh r2, [r3, #26] tcp_output(pcb); 8019b5e: 6838 ldr r0, [r7, #0] 8019b60: f003 fc2c bl 801d3bc } if (pcb->state != LISTEN) { 8019b64: 683b ldr r3, [r7, #0] 8019b66: 7d1b ldrb r3, [r3, #20] 8019b68: 2b01 cmp r3, #1 8019b6a: d020 beq.n 8019bae LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL); 8019b6c: 683b ldr r3, [r7, #0] 8019b6e: 6edb ldr r3, [r3, #108] ; 0x6c 8019b70: 2b00 cmp r3, #0 8019b72: d006 beq.n 8019b82 8019b74: 4b13 ldr r3, [pc, #76] ; (8019bc4 ) 8019b76: f640 0293 movw r2, #2195 ; 0x893 8019b7a: 4916 ldr r1, [pc, #88] ; (8019bd4 ) 8019b7c: 4813 ldr r0, [pc, #76] ; (8019bcc ) 8019b7e: f007 ff03 bl 8021988 LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL); 8019b82: 683b ldr r3, [r7, #0] 8019b84: 6f1b ldr r3, [r3, #112] ; 0x70 8019b86: 2b00 cmp r3, #0 8019b88: d006 beq.n 8019b98 8019b8a: 4b0e ldr r3, [pc, #56] ; (8019bc4 ) 8019b8c: f640 0294 movw r2, #2196 ; 0x894 8019b90: 4911 ldr r1, [pc, #68] ; (8019bd8 ) 8019b92: 480e ldr r0, [pc, #56] ; (8019bcc ) 8019b94: f007 fef8 bl 8021988 #if TCP_QUEUE_OOSEQ LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL); 8019b98: 683b ldr r3, [r7, #0] 8019b9a: 6f5b ldr r3, [r3, #116] ; 0x74 8019b9c: 2b00 cmp r3, #0 8019b9e: d006 beq.n 8019bae 8019ba0: 4b08 ldr r3, [pc, #32] ; (8019bc4 ) 8019ba2: f640 0296 movw r2, #2198 ; 0x896 8019ba6: 490d ldr r1, [pc, #52] ; (8019bdc ) 8019ba8: 4808 ldr r0, [pc, #32] ; (8019bcc ) 8019baa: f007 feed bl 8021988 #endif /* TCP_QUEUE_OOSEQ */ } pcb->state = CLOSED; 8019bae: 683b ldr r3, [r7, #0] 8019bb0: 2200 movs r2, #0 8019bb2: 751a strb r2, [r3, #20] /* reset the local port to prevent the pcb from being 'bound' */ pcb->local_port = 0; 8019bb4: 683b ldr r3, [r7, #0] 8019bb6: 2200 movs r2, #0 8019bb8: 82da strh r2, [r3, #22] LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); } 8019bba: bf00 nop 8019bbc: 3710 adds r7, #16 8019bbe: 46bd mov sp, r7 8019bc0: bd80 pop {r7, pc} 8019bc2: bf00 nop 8019bc4: 08024ba8 .word 0x08024ba8 8019bc8: 08025210 .word 0x08025210 8019bcc: 08024bec .word 0x08024bec 8019bd0: 0802522c .word 0x0802522c 8019bd4: 0802524c .word 0x0802524c 8019bd8: 08025264 .word 0x08025264 8019bdc: 08025280 .word 0x08025280 08019be0 : * * @return u32_t pseudo random sequence number */ u32_t tcp_next_iss(struct tcp_pcb *pcb) { 8019be0: b580 push {r7, lr} 8019be2: b082 sub sp, #8 8019be4: af00 add r7, sp, #0 8019be6: 6078 str r0, [r7, #4] LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL); return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port); #else /* LWIP_HOOK_TCP_ISN */ static u32_t iss = 6510; LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL); 8019be8: 687b ldr r3, [r7, #4] 8019bea: 2b00 cmp r3, #0 8019bec: d106 bne.n 8019bfc 8019bee: 4b0a ldr r3, [pc, #40] ; (8019c18 ) 8019bf0: f640 02af movw r2, #2223 ; 0x8af 8019bf4: 4909 ldr r1, [pc, #36] ; (8019c1c ) 8019bf6: 480a ldr r0, [pc, #40] ; (8019c20 ) 8019bf8: f007 fec6 bl 8021988 LWIP_UNUSED_ARG(pcb); iss += tcp_ticks; /* XXX */ 8019bfc: 4b09 ldr r3, [pc, #36] ; (8019c24 ) 8019bfe: 681a ldr r2, [r3, #0] 8019c00: 4b09 ldr r3, [pc, #36] ; (8019c28 ) 8019c02: 681b ldr r3, [r3, #0] 8019c04: 4413 add r3, r2 8019c06: 4a07 ldr r2, [pc, #28] ; (8019c24 ) 8019c08: 6013 str r3, [r2, #0] return iss; 8019c0a: 4b06 ldr r3, [pc, #24] ; (8019c24 ) 8019c0c: 681b ldr r3, [r3, #0] #endif /* LWIP_HOOK_TCP_ISN */ } 8019c0e: 4618 mov r0, r3 8019c10: 3708 adds r7, #8 8019c12: 46bd mov sp, r7 8019c14: bd80 pop {r7, pc} 8019c16: bf00 nop 8019c18: 08024ba8 .word 0x08024ba8 8019c1c: 08025298 .word 0x08025298 8019c20: 08024bec .word 0x08024bec 8019c24: 24000040 .word 0x24000040 8019c28: 2401a480 .word 0x2401a480 08019c2c : * by calculating the minimum of TCP_MSS and the mtu (if set) of the target * netif (if not NULL). */ u16_t tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest) { 8019c2c: b580 push {r7, lr} 8019c2e: b086 sub sp, #24 8019c30: af00 add r7, sp, #0 8019c32: 4603 mov r3, r0 8019c34: 60b9 str r1, [r7, #8] 8019c36: 607a str r2, [r7, #4] 8019c38: 81fb strh r3, [r7, #14] u16_t mss_s; u16_t mtu; LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */ LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL); 8019c3a: 687b ldr r3, [r7, #4] 8019c3c: 2b00 cmp r3, #0 8019c3e: d106 bne.n 8019c4e 8019c40: 4b14 ldr r3, [pc, #80] ; (8019c94 ) 8019c42: f640 02c5 movw r2, #2245 ; 0x8c5 8019c46: 4914 ldr r1, [pc, #80] ; (8019c98 ) 8019c48: 4814 ldr r0, [pc, #80] ; (8019c9c ) 8019c4a: f007 fe9d bl 8021988 else #endif /* LWIP_IPV4 */ #endif /* LWIP_IPV6 */ #if LWIP_IPV4 { if (outif == NULL) { 8019c4e: 68bb ldr r3, [r7, #8] 8019c50: 2b00 cmp r3, #0 8019c52: d101 bne.n 8019c58 return sendmss; 8019c54: 89fb ldrh r3, [r7, #14] 8019c56: e019 b.n 8019c8c } mtu = outif->mtu; 8019c58: 68bb ldr r3, [r7, #8] 8019c5a: 8c9b ldrh r3, [r3, #36] ; 0x24 8019c5c: 82fb strh r3, [r7, #22] } #endif /* LWIP_IPV4 */ if (mtu != 0) { 8019c5e: 8afb ldrh r3, [r7, #22] 8019c60: 2b00 cmp r3, #0 8019c62: d012 beq.n 8019c8a else #endif /* LWIP_IPV4 */ #endif /* LWIP_IPV6 */ #if LWIP_IPV4 { offset = IP_HLEN + TCP_HLEN; 8019c64: 2328 movs r3, #40 ; 0x28 8019c66: 82bb strh r3, [r7, #20] } #endif /* LWIP_IPV4 */ mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0; 8019c68: 8afa ldrh r2, [r7, #22] 8019c6a: 8abb ldrh r3, [r7, #20] 8019c6c: 429a cmp r2, r3 8019c6e: d904 bls.n 8019c7a 8019c70: 8afa ldrh r2, [r7, #22] 8019c72: 8abb ldrh r3, [r7, #20] 8019c74: 1ad3 subs r3, r2, r3 8019c76: b29b uxth r3, r3 8019c78: e000 b.n 8019c7c 8019c7a: 2300 movs r3, #0 8019c7c: 827b strh r3, [r7, #18] /* RFC 1122, chap 4.2.2.6: * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize * We correct for TCP options in tcp_write(), and don't support IP options. */ sendmss = LWIP_MIN(sendmss, mss_s); 8019c7e: 8a7a ldrh r2, [r7, #18] 8019c80: 89fb ldrh r3, [r7, #14] 8019c82: 4293 cmp r3, r2 8019c84: bf28 it cs 8019c86: 4613 movcs r3, r2 8019c88: 81fb strh r3, [r7, #14] } return sendmss; 8019c8a: 89fb ldrh r3, [r7, #14] } 8019c8c: 4618 mov r0, r3 8019c8e: 3718 adds r7, #24 8019c90: 46bd mov sp, r7 8019c92: bd80 pop {r7, pc} 8019c94: 08024ba8 .word 0x08024ba8 8019c98: 080252b4 .word 0x080252b4 8019c9c: 08024bec .word 0x08024bec 08019ca0 : #endif /* TCP_CALCULATE_EFF_SEND_MSS */ /** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */ static void tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list) { 8019ca0: b580 push {r7, lr} 8019ca2: b084 sub sp, #16 8019ca4: af00 add r7, sp, #0 8019ca6: 6078 str r0, [r7, #4] 8019ca8: 6039 str r1, [r7, #0] struct tcp_pcb *pcb; pcb = pcb_list; 8019caa: 683b ldr r3, [r7, #0] 8019cac: 60fb str r3, [r7, #12] LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL); 8019cae: 687b ldr r3, [r7, #4] 8019cb0: 2b00 cmp r3, #0 8019cb2: d11d bne.n 8019cf0 8019cb4: 4b12 ldr r3, [pc, #72] ; (8019d00 ) 8019cb6: f44f 6210 mov.w r2, #2304 ; 0x900 8019cba: 4912 ldr r1, [pc, #72] ; (8019d04 ) 8019cbc: 4812 ldr r0, [pc, #72] ; (8019d08 ) 8019cbe: f007 fe63 bl 8021988 while (pcb != NULL) { 8019cc2: e015 b.n 8019cf0 /* PCB bound to current local interface address? */ if (ip_addr_cmp(&pcb->local_ip, old_addr) 8019cc4: 68fb ldr r3, [r7, #12] 8019cc6: 681a ldr r2, [r3, #0] 8019cc8: 687b ldr r3, [r7, #4] 8019cca: 681b ldr r3, [r3, #0] 8019ccc: 429a cmp r2, r3 8019cce: d10c bne.n 8019cea /* connections to link-local addresses must persist (RFC3927 ch. 1.9) */ && (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip))) #endif /* LWIP_AUTOIP */ ) { /* this connection must be aborted */ struct tcp_pcb *next = pcb->next; 8019cd0: 68fb ldr r3, [r7, #12] 8019cd2: 68db ldr r3, [r3, #12] 8019cd4: 60bb str r3, [r7, #8] LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); 8019cd6: 68f9 ldr r1, [r7, #12] 8019cd8: 480c ldr r0, [pc, #48] ; (8019d0c ) 8019cda: f007 fe55 bl 8021988 tcp_abort(pcb); 8019cde: 68f8 ldr r0, [r7, #12] 8019ce0: f7fe fcfa bl 80186d8 pcb = next; 8019ce4: 68bb ldr r3, [r7, #8] 8019ce6: 60fb str r3, [r7, #12] 8019ce8: e002 b.n 8019cf0 } else { pcb = pcb->next; 8019cea: 68fb ldr r3, [r7, #12] 8019cec: 68db ldr r3, [r3, #12] 8019cee: 60fb str r3, [r7, #12] while (pcb != NULL) { 8019cf0: 68fb ldr r3, [r7, #12] 8019cf2: 2b00 cmp r3, #0 8019cf4: d1e6 bne.n 8019cc4 } } } 8019cf6: bf00 nop 8019cf8: bf00 nop 8019cfa: 3710 adds r7, #16 8019cfc: 46bd mov sp, r7 8019cfe: bd80 pop {r7, pc} 8019d00: 08024ba8 .word 0x08024ba8 8019d04: 080252dc .word 0x080252dc 8019d08: 08024bec .word 0x08024bec 8019d0c: 08025310 .word 0x08025310 08019d10 : * @param old_addr IP address of the netif before change * @param new_addr IP address of the netif after change or NULL if netif has been removed */ void tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) { 8019d10: b580 push {r7, lr} 8019d12: b084 sub sp, #16 8019d14: af00 add r7, sp, #0 8019d16: 6078 str r0, [r7, #4] 8019d18: 6039 str r1, [r7, #0] struct tcp_pcb_listen *lpcb; if (!ip_addr_isany(old_addr)) { 8019d1a: 687b ldr r3, [r7, #4] 8019d1c: 2b00 cmp r3, #0 8019d1e: d02a beq.n 8019d76 8019d20: 687b ldr r3, [r7, #4] 8019d22: 681b ldr r3, [r3, #0] 8019d24: 2b00 cmp r3, #0 8019d26: d026 beq.n 8019d76 tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs); 8019d28: 4b15 ldr r3, [pc, #84] ; (8019d80 ) 8019d2a: 681b ldr r3, [r3, #0] 8019d2c: 4619 mov r1, r3 8019d2e: 6878 ldr r0, [r7, #4] 8019d30: f7ff ffb6 bl 8019ca0 tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs); 8019d34: 4b13 ldr r3, [pc, #76] ; (8019d84 ) 8019d36: 681b ldr r3, [r3, #0] 8019d38: 4619 mov r1, r3 8019d3a: 6878 ldr r0, [r7, #4] 8019d3c: f7ff ffb0 bl 8019ca0 if (!ip_addr_isany(new_addr)) { 8019d40: 683b ldr r3, [r7, #0] 8019d42: 2b00 cmp r3, #0 8019d44: d017 beq.n 8019d76 8019d46: 683b ldr r3, [r7, #0] 8019d48: 681b ldr r3, [r3, #0] 8019d4a: 2b00 cmp r3, #0 8019d4c: d013 beq.n 8019d76 /* PCB bound to current local interface address? */ for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { 8019d4e: 4b0e ldr r3, [pc, #56] ; (8019d88 ) 8019d50: 681b ldr r3, [r3, #0] 8019d52: 60fb str r3, [r7, #12] 8019d54: e00c b.n 8019d70 /* PCB bound to current local interface address? */ if (ip_addr_cmp(&lpcb->local_ip, old_addr)) { 8019d56: 68fb ldr r3, [r7, #12] 8019d58: 681a ldr r2, [r3, #0] 8019d5a: 687b ldr r3, [r7, #4] 8019d5c: 681b ldr r3, [r3, #0] 8019d5e: 429a cmp r2, r3 8019d60: d103 bne.n 8019d6a /* The PCB is listening to the old ipaddr and * is set to listen to the new one instead */ ip_addr_copy(lpcb->local_ip, *new_addr); 8019d62: 683b ldr r3, [r7, #0] 8019d64: 681a ldr r2, [r3, #0] 8019d66: 68fb ldr r3, [r7, #12] 8019d68: 601a str r2, [r3, #0] for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { 8019d6a: 68fb ldr r3, [r7, #12] 8019d6c: 68db ldr r3, [r3, #12] 8019d6e: 60fb str r3, [r7, #12] 8019d70: 68fb ldr r3, [r7, #12] 8019d72: 2b00 cmp r3, #0 8019d74: d1ef bne.n 8019d56 } } } } } 8019d76: bf00 nop 8019d78: 3710 adds r7, #16 8019d7a: 46bd mov sp, r7 8019d7c: bd80 pop {r7, pc} 8019d7e: bf00 nop 8019d80: 2401a48c .word 0x2401a48c 8019d84: 2401a484 .word 0x2401a484 8019d88: 2401a488 .word 0x2401a488 08019d8c : #if TCP_QUEUE_OOSEQ /* Free all ooseq pbufs (and possibly reset SACK state) */ void tcp_free_ooseq(struct tcp_pcb *pcb) { 8019d8c: b580 push {r7, lr} 8019d8e: b082 sub sp, #8 8019d90: af00 add r7, sp, #0 8019d92: 6078 str r0, [r7, #4] if (pcb->ooseq) { 8019d94: 687b ldr r3, [r7, #4] 8019d96: 6f5b ldr r3, [r3, #116] ; 0x74 8019d98: 2b00 cmp r3, #0 8019d9a: d007 beq.n 8019dac tcp_segs_free(pcb->ooseq); 8019d9c: 687b ldr r3, [r7, #4] 8019d9e: 6f5b ldr r3, [r3, #116] ; 0x74 8019da0: 4618 mov r0, r3 8019da2: f7ff fb69 bl 8019478 pcb->ooseq = NULL; 8019da6: 687b ldr r3, [r7, #4] 8019da8: 2200 movs r2, #0 8019daa: 675a str r2, [r3, #116] ; 0x74 #if LWIP_TCP_SACK_OUT memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks)); #endif /* LWIP_TCP_SACK_OUT */ } } 8019dac: bf00 nop 8019dae: 3708 adds r7, #8 8019db0: 46bd mov sp, r7 8019db2: bd80 pop {r7, pc} 08019db4 : * @param p received TCP segment to process (p->payload pointing to the TCP header) * @param inp network interface on which this segment was received */ void tcp_input(struct pbuf *p, struct netif *inp) { 8019db4: b590 push {r4, r7, lr} 8019db6: b08d sub sp, #52 ; 0x34 8019db8: af04 add r7, sp, #16 8019dba: 6078 str r0, [r7, #4] 8019dbc: 6039 str r1, [r7, #0] u8_t hdrlen_bytes; err_t err; LWIP_UNUSED_ARG(inp); LWIP_ASSERT_CORE_LOCKED(); LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL); 8019dbe: 687b ldr r3, [r7, #4] 8019dc0: 2b00 cmp r3, #0 8019dc2: d105 bne.n 8019dd0 8019dc4: 4b9b ldr r3, [pc, #620] ; (801a034 ) 8019dc6: 2283 movs r2, #131 ; 0x83 8019dc8: 499b ldr r1, [pc, #620] ; (801a038 ) 8019dca: 489c ldr r0, [pc, #624] ; (801a03c ) 8019dcc: f007 fddc bl 8021988 PERF_START; TCP_STATS_INC(tcp.recv); MIB2_STATS_INC(mib2.tcpinsegs); tcphdr = (struct tcp_hdr *)p->payload; 8019dd0: 687b ldr r3, [r7, #4] 8019dd2: 685b ldr r3, [r3, #4] 8019dd4: 4a9a ldr r2, [pc, #616] ; (801a040 ) 8019dd6: 6013 str r3, [r2, #0] #if TCP_INPUT_DEBUG tcp_debug_print(tcphdr); #endif /* Check that TCP header fits in payload */ if (p->len < TCP_HLEN) { 8019dd8: 687b ldr r3, [r7, #4] 8019dda: 895b ldrh r3, [r3, #10] 8019ddc: 2b13 cmp r3, #19 8019dde: f240 83d1 bls.w 801a584 TCP_STATS_INC(tcp.lenerr); goto dropped; } /* Don't even process incoming broadcasts/multicasts. */ if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) || 8019de2: 4b98 ldr r3, [pc, #608] ; (801a044 ) 8019de4: 695b ldr r3, [r3, #20] 8019de6: 4a97 ldr r2, [pc, #604] ; (801a044 ) 8019de8: 6812 ldr r2, [r2, #0] 8019dea: 4611 mov r1, r2 8019dec: 4618 mov r0, r3 8019dee: f006 fb17 bl 8020420 8019df2: 4603 mov r3, r0 8019df4: 2b00 cmp r3, #0 8019df6: f040 83c7 bne.w 801a588 ip_addr_ismulticast(ip_current_dest_addr())) { 8019dfa: 4b92 ldr r3, [pc, #584] ; (801a044 ) 8019dfc: 695b ldr r3, [r3, #20] 8019dfe: f003 03f0 and.w r3, r3, #240 ; 0xf0 if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) || 8019e02: 2be0 cmp r3, #224 ; 0xe0 8019e04: f000 83c0 beq.w 801a588 } } #endif /* CHECKSUM_CHECK_TCP */ /* sanity-check header length */ hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr); 8019e08: 4b8d ldr r3, [pc, #564] ; (801a040 ) 8019e0a: 681b ldr r3, [r3, #0] 8019e0c: 899b ldrh r3, [r3, #12] 8019e0e: b29b uxth r3, r3 8019e10: 4618 mov r0, r3 8019e12: f7fc f895 bl 8015f40 8019e16: 4603 mov r3, r0 8019e18: 0b1b lsrs r3, r3, #12 8019e1a: b29b uxth r3, r3 8019e1c: b2db uxtb r3, r3 8019e1e: 009b lsls r3, r3, #2 8019e20: 74bb strb r3, [r7, #18] if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) { 8019e22: 7cbb ldrb r3, [r7, #18] 8019e24: 2b13 cmp r3, #19 8019e26: f240 83b1 bls.w 801a58c 8019e2a: 7cbb ldrb r3, [r7, #18] 8019e2c: b29a uxth r2, r3 8019e2e: 687b ldr r3, [r7, #4] 8019e30: 891b ldrh r3, [r3, #8] 8019e32: 429a cmp r2, r3 8019e34: f200 83aa bhi.w 801a58c goto dropped; } /* Move the payload pointer in the pbuf so that it points to the TCP data instead of the TCP header. */ tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN); 8019e38: 7cbb ldrb r3, [r7, #18] 8019e3a: b29b uxth r3, r3 8019e3c: 3b14 subs r3, #20 8019e3e: b29a uxth r2, r3 8019e40: 4b81 ldr r3, [pc, #516] ; (801a048 ) 8019e42: 801a strh r2, [r3, #0] tcphdr_opt2 = NULL; 8019e44: 4b81 ldr r3, [pc, #516] ; (801a04c ) 8019e46: 2200 movs r2, #0 8019e48: 601a str r2, [r3, #0] if (p->len >= hdrlen_bytes) { 8019e4a: 687b ldr r3, [r7, #4] 8019e4c: 895a ldrh r2, [r3, #10] 8019e4e: 7cbb ldrb r3, [r7, #18] 8019e50: b29b uxth r3, r3 8019e52: 429a cmp r2, r3 8019e54: d309 bcc.n 8019e6a /* all options are in the first pbuf */ tcphdr_opt1len = tcphdr_optlen; 8019e56: 4b7c ldr r3, [pc, #496] ; (801a048 ) 8019e58: 881a ldrh r2, [r3, #0] 8019e5a: 4b7d ldr r3, [pc, #500] ; (801a050 ) 8019e5c: 801a strh r2, [r3, #0] pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */ 8019e5e: 7cbb ldrb r3, [r7, #18] 8019e60: 4619 mov r1, r3 8019e62: 6878 ldr r0, [r7, #4] 8019e64: f7fd fdc2 bl 80179ec 8019e68: e04e b.n 8019f08 } else { u16_t opt2len; /* TCP header fits into first pbuf, options don't - data is in the next pbuf */ /* there must be a next pbuf, due to hdrlen_bytes sanity check above */ LWIP_ASSERT("p->next != NULL", p->next != NULL); 8019e6a: 687b ldr r3, [r7, #4] 8019e6c: 681b ldr r3, [r3, #0] 8019e6e: 2b00 cmp r3, #0 8019e70: d105 bne.n 8019e7e 8019e72: 4b70 ldr r3, [pc, #448] ; (801a034 ) 8019e74: 22c2 movs r2, #194 ; 0xc2 8019e76: 4977 ldr r1, [pc, #476] ; (801a054 ) 8019e78: 4870 ldr r0, [pc, #448] ; (801a03c ) 8019e7a: f007 fd85 bl 8021988 /* advance over the TCP header (cannot fail) */ pbuf_remove_header(p, TCP_HLEN); 8019e7e: 2114 movs r1, #20 8019e80: 6878 ldr r0, [r7, #4] 8019e82: f7fd fdb3 bl 80179ec /* determine how long the first and second parts of the options are */ tcphdr_opt1len = p->len; 8019e86: 687b ldr r3, [r7, #4] 8019e88: 895a ldrh r2, [r3, #10] 8019e8a: 4b71 ldr r3, [pc, #452] ; (801a050 ) 8019e8c: 801a strh r2, [r3, #0] opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len); 8019e8e: 4b6e ldr r3, [pc, #440] ; (801a048 ) 8019e90: 881a ldrh r2, [r3, #0] 8019e92: 4b6f ldr r3, [pc, #444] ; (801a050 ) 8019e94: 881b ldrh r3, [r3, #0] 8019e96: 1ad3 subs r3, r2, r3 8019e98: 823b strh r3, [r7, #16] /* options continue in the next pbuf: set p to zero length and hide the options in the next pbuf (adjusting p->tot_len) */ pbuf_remove_header(p, tcphdr_opt1len); 8019e9a: 4b6d ldr r3, [pc, #436] ; (801a050 ) 8019e9c: 881b ldrh r3, [r3, #0] 8019e9e: 4619 mov r1, r3 8019ea0: 6878 ldr r0, [r7, #4] 8019ea2: f7fd fda3 bl 80179ec /* check that the options fit in the second pbuf */ if (opt2len > p->next->len) { 8019ea6: 687b ldr r3, [r7, #4] 8019ea8: 681b ldr r3, [r3, #0] 8019eaa: 895b ldrh r3, [r3, #10] 8019eac: 8a3a ldrh r2, [r7, #16] 8019eae: 429a cmp r2, r3 8019eb0: f200 836e bhi.w 801a590 TCP_STATS_INC(tcp.lenerr); goto dropped; } /* remember the pointer to the second part of the options */ tcphdr_opt2 = (u8_t *)p->next->payload; 8019eb4: 687b ldr r3, [r7, #4] 8019eb6: 681b ldr r3, [r3, #0] 8019eb8: 685b ldr r3, [r3, #4] 8019eba: 4a64 ldr r2, [pc, #400] ; (801a04c ) 8019ebc: 6013 str r3, [r2, #0] /* advance p->next to point after the options, and manually adjust p->tot_len to keep it consistent with the changed p->next */ pbuf_remove_header(p->next, opt2len); 8019ebe: 687b ldr r3, [r7, #4] 8019ec0: 681b ldr r3, [r3, #0] 8019ec2: 8a3a ldrh r2, [r7, #16] 8019ec4: 4611 mov r1, r2 8019ec6: 4618 mov r0, r3 8019ec8: f7fd fd90 bl 80179ec p->tot_len = (u16_t)(p->tot_len - opt2len); 8019ecc: 687b ldr r3, [r7, #4] 8019ece: 891a ldrh r2, [r3, #8] 8019ed0: 8a3b ldrh r3, [r7, #16] 8019ed2: 1ad3 subs r3, r2, r3 8019ed4: b29a uxth r2, r3 8019ed6: 687b ldr r3, [r7, #4] 8019ed8: 811a strh r2, [r3, #8] LWIP_ASSERT("p->len == 0", p->len == 0); 8019eda: 687b ldr r3, [r7, #4] 8019edc: 895b ldrh r3, [r3, #10] 8019ede: 2b00 cmp r3, #0 8019ee0: d005 beq.n 8019eee 8019ee2: 4b54 ldr r3, [pc, #336] ; (801a034 ) 8019ee4: 22df movs r2, #223 ; 0xdf 8019ee6: 495c ldr r1, [pc, #368] ; (801a058 ) 8019ee8: 4854 ldr r0, [pc, #336] ; (801a03c ) 8019eea: f007 fd4d bl 8021988 LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len); 8019eee: 687b ldr r3, [r7, #4] 8019ef0: 891a ldrh r2, [r3, #8] 8019ef2: 687b ldr r3, [r7, #4] 8019ef4: 681b ldr r3, [r3, #0] 8019ef6: 891b ldrh r3, [r3, #8] 8019ef8: 429a cmp r2, r3 8019efa: d005 beq.n 8019f08 8019efc: 4b4d ldr r3, [pc, #308] ; (801a034 ) 8019efe: 22e0 movs r2, #224 ; 0xe0 8019f00: 4956 ldr r1, [pc, #344] ; (801a05c ) 8019f02: 484e ldr r0, [pc, #312] ; (801a03c ) 8019f04: f007 fd40 bl 8021988 } /* Convert fields in TCP header to host byte order. */ tcphdr->src = lwip_ntohs(tcphdr->src); 8019f08: 4b4d ldr r3, [pc, #308] ; (801a040 ) 8019f0a: 681b ldr r3, [r3, #0] 8019f0c: 881b ldrh r3, [r3, #0] 8019f0e: b29b uxth r3, r3 8019f10: 4a4b ldr r2, [pc, #300] ; (801a040 ) 8019f12: 6814 ldr r4, [r2, #0] 8019f14: 4618 mov r0, r3 8019f16: f7fc f813 bl 8015f40 8019f1a: 4603 mov r3, r0 8019f1c: 8023 strh r3, [r4, #0] tcphdr->dest = lwip_ntohs(tcphdr->dest); 8019f1e: 4b48 ldr r3, [pc, #288] ; (801a040 ) 8019f20: 681b ldr r3, [r3, #0] 8019f22: 885b ldrh r3, [r3, #2] 8019f24: b29b uxth r3, r3 8019f26: 4a46 ldr r2, [pc, #280] ; (801a040 ) 8019f28: 6814 ldr r4, [r2, #0] 8019f2a: 4618 mov r0, r3 8019f2c: f7fc f808 bl 8015f40 8019f30: 4603 mov r3, r0 8019f32: 8063 strh r3, [r4, #2] seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno); 8019f34: 4b42 ldr r3, [pc, #264] ; (801a040 ) 8019f36: 681b ldr r3, [r3, #0] 8019f38: 685b ldr r3, [r3, #4] 8019f3a: 4a41 ldr r2, [pc, #260] ; (801a040 ) 8019f3c: 6814 ldr r4, [r2, #0] 8019f3e: 4618 mov r0, r3 8019f40: f7fc f813 bl 8015f6a 8019f44: 4603 mov r3, r0 8019f46: 6063 str r3, [r4, #4] 8019f48: 6863 ldr r3, [r4, #4] 8019f4a: 4a45 ldr r2, [pc, #276] ; (801a060 ) 8019f4c: 6013 str r3, [r2, #0] ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno); 8019f4e: 4b3c ldr r3, [pc, #240] ; (801a040 ) 8019f50: 681b ldr r3, [r3, #0] 8019f52: 689b ldr r3, [r3, #8] 8019f54: 4a3a ldr r2, [pc, #232] ; (801a040 ) 8019f56: 6814 ldr r4, [r2, #0] 8019f58: 4618 mov r0, r3 8019f5a: f7fc f806 bl 8015f6a 8019f5e: 4603 mov r3, r0 8019f60: 60a3 str r3, [r4, #8] 8019f62: 68a3 ldr r3, [r4, #8] 8019f64: 4a3f ldr r2, [pc, #252] ; (801a064 ) 8019f66: 6013 str r3, [r2, #0] tcphdr->wnd = lwip_ntohs(tcphdr->wnd); 8019f68: 4b35 ldr r3, [pc, #212] ; (801a040 ) 8019f6a: 681b ldr r3, [r3, #0] 8019f6c: 89db ldrh r3, [r3, #14] 8019f6e: b29b uxth r3, r3 8019f70: 4a33 ldr r2, [pc, #204] ; (801a040 ) 8019f72: 6814 ldr r4, [r2, #0] 8019f74: 4618 mov r0, r3 8019f76: f7fb ffe3 bl 8015f40 8019f7a: 4603 mov r3, r0 8019f7c: 81e3 strh r3, [r4, #14] flags = TCPH_FLAGS(tcphdr); 8019f7e: 4b30 ldr r3, [pc, #192] ; (801a040 ) 8019f80: 681b ldr r3, [r3, #0] 8019f82: 899b ldrh r3, [r3, #12] 8019f84: b29b uxth r3, r3 8019f86: 4618 mov r0, r3 8019f88: f7fb ffda bl 8015f40 8019f8c: 4603 mov r3, r0 8019f8e: b2db uxtb r3, r3 8019f90: f003 033f and.w r3, r3, #63 ; 0x3f 8019f94: b2da uxtb r2, r3 8019f96: 4b34 ldr r3, [pc, #208] ; (801a068 ) 8019f98: 701a strb r2, [r3, #0] tcplen = p->tot_len; 8019f9a: 687b ldr r3, [r7, #4] 8019f9c: 891a ldrh r2, [r3, #8] 8019f9e: 4b33 ldr r3, [pc, #204] ; (801a06c ) 8019fa0: 801a strh r2, [r3, #0] if (flags & (TCP_FIN | TCP_SYN)) { 8019fa2: 4b31 ldr r3, [pc, #196] ; (801a068 ) 8019fa4: 781b ldrb r3, [r3, #0] 8019fa6: f003 0303 and.w r3, r3, #3 8019faa: 2b00 cmp r3, #0 8019fac: d00c beq.n 8019fc8 tcplen++; 8019fae: 4b2f ldr r3, [pc, #188] ; (801a06c ) 8019fb0: 881b ldrh r3, [r3, #0] 8019fb2: 3301 adds r3, #1 8019fb4: b29a uxth r2, r3 8019fb6: 4b2d ldr r3, [pc, #180] ; (801a06c ) 8019fb8: 801a strh r2, [r3, #0] if (tcplen < p->tot_len) { 8019fba: 687b ldr r3, [r7, #4] 8019fbc: 891a ldrh r2, [r3, #8] 8019fbe: 4b2b ldr r3, [pc, #172] ; (801a06c ) 8019fc0: 881b ldrh r3, [r3, #0] 8019fc2: 429a cmp r2, r3 8019fc4: f200 82e6 bhi.w 801a594 } } /* Demultiplex an incoming segment. First, we check if it is destined for an active connection. */ prev = NULL; 8019fc8: 2300 movs r3, #0 8019fca: 61fb str r3, [r7, #28] for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { 8019fcc: 4b28 ldr r3, [pc, #160] ; (801a070 ) 8019fce: 681b ldr r3, [r3, #0] 8019fd0: 61bb str r3, [r7, #24] 8019fd2: e09d b.n 801a110 LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); 8019fd4: 69bb ldr r3, [r7, #24] 8019fd6: 7d1b ldrb r3, [r3, #20] 8019fd8: 2b00 cmp r3, #0 8019fda: d105 bne.n 8019fe8 8019fdc: 4b15 ldr r3, [pc, #84] ; (801a034 ) 8019fde: 22fb movs r2, #251 ; 0xfb 8019fe0: 4924 ldr r1, [pc, #144] ; (801a074 ) 8019fe2: 4816 ldr r0, [pc, #88] ; (801a03c ) 8019fe4: f007 fcd0 bl 8021988 LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); 8019fe8: 69bb ldr r3, [r7, #24] 8019fea: 7d1b ldrb r3, [r3, #20] 8019fec: 2b0a cmp r3, #10 8019fee: d105 bne.n 8019ffc 8019ff0: 4b10 ldr r3, [pc, #64] ; (801a034 ) 8019ff2: 22fc movs r2, #252 ; 0xfc 8019ff4: 4920 ldr r1, [pc, #128] ; (801a078 ) 8019ff6: 4811 ldr r0, [pc, #68] ; (801a03c ) 8019ff8: f007 fcc6 bl 8021988 LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); 8019ffc: 69bb ldr r3, [r7, #24] 8019ffe: 7d1b ldrb r3, [r3, #20] 801a000: 2b01 cmp r3, #1 801a002: d105 bne.n 801a010 801a004: 4b0b ldr r3, [pc, #44] ; (801a034 ) 801a006: 22fd movs r2, #253 ; 0xfd 801a008: 491c ldr r1, [pc, #112] ; (801a07c ) 801a00a: 480c ldr r0, [pc, #48] ; (801a03c ) 801a00c: f007 fcbc bl 8021988 /* check if PCB is bound to specific netif */ if ((pcb->netif_idx != NETIF_NO_INDEX) && 801a010: 69bb ldr r3, [r7, #24] 801a012: 7a1b ldrb r3, [r3, #8] 801a014: 2b00 cmp r3, #0 801a016: d033 beq.n 801a080 (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { 801a018: 69bb ldr r3, [r7, #24] 801a01a: 7a1a ldrb r2, [r3, #8] 801a01c: 4b09 ldr r3, [pc, #36] ; (801a044 ) 801a01e: 685b ldr r3, [r3, #4] 801a020: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 801a024: 3301 adds r3, #1 801a026: b2db uxtb r3, r3 if ((pcb->netif_idx != NETIF_NO_INDEX) && 801a028: 429a cmp r2, r3 801a02a: d029 beq.n 801a080 prev = pcb; 801a02c: 69bb ldr r3, [r7, #24] 801a02e: 61fb str r3, [r7, #28] continue; 801a030: e06b b.n 801a10a 801a032: bf00 nop 801a034: 08025338 .word 0x08025338 801a038: 0802536c .word 0x0802536c 801a03c: 08025384 .word 0x08025384 801a040: 2401a4ac .word 0x2401a4ac 801a044: 24013980 .word 0x24013980 801a048: 2401a4b0 .word 0x2401a4b0 801a04c: 2401a4b4 .word 0x2401a4b4 801a050: 2401a4b2 .word 0x2401a4b2 801a054: 080253ac .word 0x080253ac 801a058: 080253bc .word 0x080253bc 801a05c: 080253c8 .word 0x080253c8 801a060: 2401a4bc .word 0x2401a4bc 801a064: 2401a4c0 .word 0x2401a4c0 801a068: 2401a4c8 .word 0x2401a4c8 801a06c: 2401a4c6 .word 0x2401a4c6 801a070: 2401a48c .word 0x2401a48c 801a074: 080253e8 .word 0x080253e8 801a078: 08025410 .word 0x08025410 801a07c: 0802543c .word 0x0802543c } if (pcb->remote_port == tcphdr->src && 801a080: 69bb ldr r3, [r7, #24] 801a082: 8b1a ldrh r2, [r3, #24] 801a084: 4b72 ldr r3, [pc, #456] ; (801a250 ) 801a086: 681b ldr r3, [r3, #0] 801a088: 881b ldrh r3, [r3, #0] 801a08a: b29b uxth r3, r3 801a08c: 429a cmp r2, r3 801a08e: d13a bne.n 801a106 pcb->local_port == tcphdr->dest && 801a090: 69bb ldr r3, [r7, #24] 801a092: 8ada ldrh r2, [r3, #22] 801a094: 4b6e ldr r3, [pc, #440] ; (801a250 ) 801a096: 681b ldr r3, [r3, #0] 801a098: 885b ldrh r3, [r3, #2] 801a09a: b29b uxth r3, r3 if (pcb->remote_port == tcphdr->src && 801a09c: 429a cmp r2, r3 801a09e: d132 bne.n 801a106 ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && 801a0a0: 69bb ldr r3, [r7, #24] 801a0a2: 685a ldr r2, [r3, #4] 801a0a4: 4b6b ldr r3, [pc, #428] ; (801a254 ) 801a0a6: 691b ldr r3, [r3, #16] pcb->local_port == tcphdr->dest && 801a0a8: 429a cmp r2, r3 801a0aa: d12c bne.n 801a106 ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { 801a0ac: 69bb ldr r3, [r7, #24] 801a0ae: 681a ldr r2, [r3, #0] 801a0b0: 4b68 ldr r3, [pc, #416] ; (801a254 ) 801a0b2: 695b ldr r3, [r3, #20] ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && 801a0b4: 429a cmp r2, r3 801a0b6: d126 bne.n 801a106 /* Move this PCB to the front of the list so that subsequent lookups will be faster (we exploit locality in TCP segment arrivals). */ LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); 801a0b8: 69bb ldr r3, [r7, #24] 801a0ba: 68db ldr r3, [r3, #12] 801a0bc: 69ba ldr r2, [r7, #24] 801a0be: 429a cmp r2, r3 801a0c0: d106 bne.n 801a0d0 801a0c2: 4b65 ldr r3, [pc, #404] ; (801a258 ) 801a0c4: f240 120d movw r2, #269 ; 0x10d 801a0c8: 4964 ldr r1, [pc, #400] ; (801a25c ) 801a0ca: 4865 ldr r0, [pc, #404] ; (801a260 ) 801a0cc: f007 fc5c bl 8021988 if (prev != NULL) { 801a0d0: 69fb ldr r3, [r7, #28] 801a0d2: 2b00 cmp r3, #0 801a0d4: d00a beq.n 801a0ec prev->next = pcb->next; 801a0d6: 69bb ldr r3, [r7, #24] 801a0d8: 68da ldr r2, [r3, #12] 801a0da: 69fb ldr r3, [r7, #28] 801a0dc: 60da str r2, [r3, #12] pcb->next = tcp_active_pcbs; 801a0de: 4b61 ldr r3, [pc, #388] ; (801a264 ) 801a0e0: 681a ldr r2, [r3, #0] 801a0e2: 69bb ldr r3, [r7, #24] 801a0e4: 60da str r2, [r3, #12] tcp_active_pcbs = pcb; 801a0e6: 4a5f ldr r2, [pc, #380] ; (801a264 ) 801a0e8: 69bb ldr r3, [r7, #24] 801a0ea: 6013 str r3, [r2, #0] } else { TCP_STATS_INC(tcp.cachehit); } LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); 801a0ec: 69bb ldr r3, [r7, #24] 801a0ee: 68db ldr r3, [r3, #12] 801a0f0: 69ba ldr r2, [r7, #24] 801a0f2: 429a cmp r2, r3 801a0f4: d111 bne.n 801a11a 801a0f6: 4b58 ldr r3, [pc, #352] ; (801a258 ) 801a0f8: f240 1215 movw r2, #277 ; 0x115 801a0fc: 495a ldr r1, [pc, #360] ; (801a268 ) 801a0fe: 4858 ldr r0, [pc, #352] ; (801a260 ) 801a100: f007 fc42 bl 8021988 break; 801a104: e009 b.n 801a11a } prev = pcb; 801a106: 69bb ldr r3, [r7, #24] 801a108: 61fb str r3, [r7, #28] for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { 801a10a: 69bb ldr r3, [r7, #24] 801a10c: 68db ldr r3, [r3, #12] 801a10e: 61bb str r3, [r7, #24] 801a110: 69bb ldr r3, [r7, #24] 801a112: 2b00 cmp r3, #0 801a114: f47f af5e bne.w 8019fd4 801a118: e000 b.n 801a11c break; 801a11a: bf00 nop } if (pcb == NULL) { 801a11c: 69bb ldr r3, [r7, #24] 801a11e: 2b00 cmp r3, #0 801a120: f040 80aa bne.w 801a278 /* If it did not go to an active connection, we check the connections in the TIME-WAIT state. */ for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { 801a124: 4b51 ldr r3, [pc, #324] ; (801a26c ) 801a126: 681b ldr r3, [r3, #0] 801a128: 61bb str r3, [r7, #24] 801a12a: e03f b.n 801a1ac LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); 801a12c: 69bb ldr r3, [r7, #24] 801a12e: 7d1b ldrb r3, [r3, #20] 801a130: 2b0a cmp r3, #10 801a132: d006 beq.n 801a142 801a134: 4b48 ldr r3, [pc, #288] ; (801a258 ) 801a136: f240 121f movw r2, #287 ; 0x11f 801a13a: 494d ldr r1, [pc, #308] ; (801a270 ) 801a13c: 4848 ldr r0, [pc, #288] ; (801a260 ) 801a13e: f007 fc23 bl 8021988 /* check if PCB is bound to specific netif */ if ((pcb->netif_idx != NETIF_NO_INDEX) && 801a142: 69bb ldr r3, [r7, #24] 801a144: 7a1b ldrb r3, [r3, #8] 801a146: 2b00 cmp r3, #0 801a148: d009 beq.n 801a15e (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { 801a14a: 69bb ldr r3, [r7, #24] 801a14c: 7a1a ldrb r2, [r3, #8] 801a14e: 4b41 ldr r3, [pc, #260] ; (801a254 ) 801a150: 685b ldr r3, [r3, #4] 801a152: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 801a156: 3301 adds r3, #1 801a158: b2db uxtb r3, r3 if ((pcb->netif_idx != NETIF_NO_INDEX) && 801a15a: 429a cmp r2, r3 801a15c: d122 bne.n 801a1a4 continue; } if (pcb->remote_port == tcphdr->src && 801a15e: 69bb ldr r3, [r7, #24] 801a160: 8b1a ldrh r2, [r3, #24] 801a162: 4b3b ldr r3, [pc, #236] ; (801a250 ) 801a164: 681b ldr r3, [r3, #0] 801a166: 881b ldrh r3, [r3, #0] 801a168: b29b uxth r3, r3 801a16a: 429a cmp r2, r3 801a16c: d11b bne.n 801a1a6 pcb->local_port == tcphdr->dest && 801a16e: 69bb ldr r3, [r7, #24] 801a170: 8ada ldrh r2, [r3, #22] 801a172: 4b37 ldr r3, [pc, #220] ; (801a250 ) 801a174: 681b ldr r3, [r3, #0] 801a176: 885b ldrh r3, [r3, #2] 801a178: b29b uxth r3, r3 if (pcb->remote_port == tcphdr->src && 801a17a: 429a cmp r2, r3 801a17c: d113 bne.n 801a1a6 ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && 801a17e: 69bb ldr r3, [r7, #24] 801a180: 685a ldr r2, [r3, #4] 801a182: 4b34 ldr r3, [pc, #208] ; (801a254 ) 801a184: 691b ldr r3, [r3, #16] pcb->local_port == tcphdr->dest && 801a186: 429a cmp r2, r3 801a188: d10d bne.n 801a1a6 ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { 801a18a: 69bb ldr r3, [r7, #24] 801a18c: 681a ldr r2, [r3, #0] 801a18e: 4b31 ldr r3, [pc, #196] ; (801a254 ) 801a190: 695b ldr r3, [r3, #20] ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && 801a192: 429a cmp r2, r3 801a194: d107 bne.n 801a1a6 #ifdef LWIP_HOOK_TCP_INPACKET_PCB if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK) #endif { tcp_timewait_input(pcb); 801a196: 69b8 ldr r0, [r7, #24] 801a198: f000 fb56 bl 801a848 } pbuf_free(p); 801a19c: 6878 ldr r0, [r7, #4] 801a19e: f7fd fcab bl 8017af8 return; 801a1a2: e1fd b.n 801a5a0 continue; 801a1a4: bf00 nop for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { 801a1a6: 69bb ldr r3, [r7, #24] 801a1a8: 68db ldr r3, [r3, #12] 801a1aa: 61bb str r3, [r7, #24] 801a1ac: 69bb ldr r3, [r7, #24] 801a1ae: 2b00 cmp r3, #0 801a1b0: d1bc bne.n 801a12c } } /* Finally, if we still did not get a match, we check all PCBs that are LISTENing for incoming connections. */ prev = NULL; 801a1b2: 2300 movs r3, #0 801a1b4: 61fb str r3, [r7, #28] for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { 801a1b6: 4b2f ldr r3, [pc, #188] ; (801a274 ) 801a1b8: 681b ldr r3, [r3, #0] 801a1ba: 617b str r3, [r7, #20] 801a1bc: e02a b.n 801a214 /* check if PCB is bound to specific netif */ if ((lpcb->netif_idx != NETIF_NO_INDEX) && 801a1be: 697b ldr r3, [r7, #20] 801a1c0: 7a1b ldrb r3, [r3, #8] 801a1c2: 2b00 cmp r3, #0 801a1c4: d00c beq.n 801a1e0 (lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { 801a1c6: 697b ldr r3, [r7, #20] 801a1c8: 7a1a ldrb r2, [r3, #8] 801a1ca: 4b22 ldr r3, [pc, #136] ; (801a254 ) 801a1cc: 685b ldr r3, [r3, #4] 801a1ce: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 801a1d2: 3301 adds r3, #1 801a1d4: b2db uxtb r3, r3 if ((lpcb->netif_idx != NETIF_NO_INDEX) && 801a1d6: 429a cmp r2, r3 801a1d8: d002 beq.n 801a1e0 prev = (struct tcp_pcb *)lpcb; 801a1da: 697b ldr r3, [r7, #20] 801a1dc: 61fb str r3, [r7, #28] continue; 801a1de: e016 b.n 801a20e } if (lpcb->local_port == tcphdr->dest) { 801a1e0: 697b ldr r3, [r7, #20] 801a1e2: 8ada ldrh r2, [r3, #22] 801a1e4: 4b1a ldr r3, [pc, #104] ; (801a250 ) 801a1e6: 681b ldr r3, [r3, #0] 801a1e8: 885b ldrh r3, [r3, #2] 801a1ea: b29b uxth r3, r3 801a1ec: 429a cmp r2, r3 801a1ee: d10c bne.n 801a20a lpcb_prev = prev; #else /* SO_REUSE */ break; #endif /* SO_REUSE */ } else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) { if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) { 801a1f0: 697b ldr r3, [r7, #20] 801a1f2: 681a ldr r2, [r3, #0] 801a1f4: 4b17 ldr r3, [pc, #92] ; (801a254 ) 801a1f6: 695b ldr r3, [r3, #20] 801a1f8: 429a cmp r2, r3 801a1fa: d00f beq.n 801a21c /* found an exact match */ break; } else if (ip_addr_isany(&lpcb->local_ip)) { 801a1fc: 697b ldr r3, [r7, #20] 801a1fe: 2b00 cmp r3, #0 801a200: d00d beq.n 801a21e 801a202: 697b ldr r3, [r7, #20] 801a204: 681b ldr r3, [r3, #0] 801a206: 2b00 cmp r3, #0 801a208: d009 beq.n 801a21e break; #endif /* SO_REUSE */ } } } prev = (struct tcp_pcb *)lpcb; 801a20a: 697b ldr r3, [r7, #20] 801a20c: 61fb str r3, [r7, #28] for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { 801a20e: 697b ldr r3, [r7, #20] 801a210: 68db ldr r3, [r3, #12] 801a212: 617b str r3, [r7, #20] 801a214: 697b ldr r3, [r7, #20] 801a216: 2b00 cmp r3, #0 801a218: d1d1 bne.n 801a1be 801a21a: e000 b.n 801a21e break; 801a21c: bf00 nop /* only pass to ANY if no specific local IP has been found */ lpcb = lpcb_any; prev = lpcb_prev; } #endif /* SO_REUSE */ if (lpcb != NULL) { 801a21e: 697b ldr r3, [r7, #20] 801a220: 2b00 cmp r3, #0 801a222: d029 beq.n 801a278 /* Move this PCB to the front of the list so that subsequent lookups will be faster (we exploit locality in TCP segment arrivals). */ if (prev != NULL) { 801a224: 69fb ldr r3, [r7, #28] 801a226: 2b00 cmp r3, #0 801a228: d00a beq.n 801a240 ((struct tcp_pcb_listen *)prev)->next = lpcb->next; 801a22a: 697b ldr r3, [r7, #20] 801a22c: 68da ldr r2, [r3, #12] 801a22e: 69fb ldr r3, [r7, #28] 801a230: 60da str r2, [r3, #12] /* our successor is the remainder of the listening list */ lpcb->next = tcp_listen_pcbs.listen_pcbs; 801a232: 4b10 ldr r3, [pc, #64] ; (801a274 ) 801a234: 681a ldr r2, [r3, #0] 801a236: 697b ldr r3, [r7, #20] 801a238: 60da str r2, [r3, #12] /* put this listening pcb at the head of the listening list */ tcp_listen_pcbs.listen_pcbs = lpcb; 801a23a: 4a0e ldr r2, [pc, #56] ; (801a274 ) 801a23c: 697b ldr r3, [r7, #20] 801a23e: 6013 str r3, [r2, #0] #ifdef LWIP_HOOK_TCP_INPACKET_PCB if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen, tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK) #endif { tcp_listen_input(lpcb); 801a240: 6978 ldr r0, [r7, #20] 801a242: f000 fa03 bl 801a64c } pbuf_free(p); 801a246: 6878 ldr r0, [r7, #4] 801a248: f7fd fc56 bl 8017af8 return; 801a24c: e1a8 b.n 801a5a0 801a24e: bf00 nop 801a250: 2401a4ac .word 0x2401a4ac 801a254: 24013980 .word 0x24013980 801a258: 08025338 .word 0x08025338 801a25c: 08025464 .word 0x08025464 801a260: 08025384 .word 0x08025384 801a264: 2401a48c .word 0x2401a48c 801a268: 08025490 .word 0x08025490 801a26c: 2401a490 .word 0x2401a490 801a270: 080254bc .word 0x080254bc 801a274: 2401a488 .word 0x2401a488 tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) { pbuf_free(p); return; } #endif if (pcb != NULL) { 801a278: 69bb ldr r3, [r7, #24] 801a27a: 2b00 cmp r3, #0 801a27c: f000 8158 beq.w 801a530 #if TCP_INPUT_DEBUG tcp_debug_print_state(pcb->state); #endif /* TCP_INPUT_DEBUG */ /* Set up a tcp_seg structure. */ inseg.next = NULL; 801a280: 4b95 ldr r3, [pc, #596] ; (801a4d8 ) 801a282: 2200 movs r2, #0 801a284: 601a str r2, [r3, #0] inseg.len = p->tot_len; 801a286: 687b ldr r3, [r7, #4] 801a288: 891a ldrh r2, [r3, #8] 801a28a: 4b93 ldr r3, [pc, #588] ; (801a4d8 ) 801a28c: 811a strh r2, [r3, #8] inseg.p = p; 801a28e: 4a92 ldr r2, [pc, #584] ; (801a4d8 ) 801a290: 687b ldr r3, [r7, #4] 801a292: 6053 str r3, [r2, #4] inseg.tcphdr = tcphdr; 801a294: 4b91 ldr r3, [pc, #580] ; (801a4dc ) 801a296: 681b ldr r3, [r3, #0] 801a298: 4a8f ldr r2, [pc, #572] ; (801a4d8 ) 801a29a: 6113 str r3, [r2, #16] recv_data = NULL; 801a29c: 4b90 ldr r3, [pc, #576] ; (801a4e0 ) 801a29e: 2200 movs r2, #0 801a2a0: 601a str r2, [r3, #0] recv_flags = 0; 801a2a2: 4b90 ldr r3, [pc, #576] ; (801a4e4 ) 801a2a4: 2200 movs r2, #0 801a2a6: 701a strb r2, [r3, #0] recv_acked = 0; 801a2a8: 4b8f ldr r3, [pc, #572] ; (801a4e8 ) 801a2aa: 2200 movs r2, #0 801a2ac: 801a strh r2, [r3, #0] if (flags & TCP_PSH) { 801a2ae: 4b8f ldr r3, [pc, #572] ; (801a4ec ) 801a2b0: 781b ldrb r3, [r3, #0] 801a2b2: f003 0308 and.w r3, r3, #8 801a2b6: 2b00 cmp r3, #0 801a2b8: d006 beq.n 801a2c8 p->flags |= PBUF_FLAG_PUSH; 801a2ba: 687b ldr r3, [r7, #4] 801a2bc: 7b5b ldrb r3, [r3, #13] 801a2be: f043 0301 orr.w r3, r3, #1 801a2c2: b2da uxtb r2, r3 801a2c4: 687b ldr r3, [r7, #4] 801a2c6: 735a strb r2, [r3, #13] } /* If there is data which was previously "refused" by upper layer */ if (pcb->refused_data != NULL) { 801a2c8: 69bb ldr r3, [r7, #24] 801a2ca: 6f9b ldr r3, [r3, #120] ; 0x78 801a2cc: 2b00 cmp r3, #0 801a2ce: d017 beq.n 801a300 if ((tcp_process_refused_data(pcb) == ERR_ABRT) || 801a2d0: 69b8 ldr r0, [r7, #24] 801a2d2: f7ff f853 bl 801937c 801a2d6: 4603 mov r3, r0 801a2d8: f113 0f0d cmn.w r3, #13 801a2dc: d007 beq.n 801a2ee ((pcb->refused_data != NULL) && (tcplen > 0))) { 801a2de: 69bb ldr r3, [r7, #24] 801a2e0: 6f9b ldr r3, [r3, #120] ; 0x78 if ((tcp_process_refused_data(pcb) == ERR_ABRT) || 801a2e2: 2b00 cmp r3, #0 801a2e4: d00c beq.n 801a300 ((pcb->refused_data != NULL) && (tcplen > 0))) { 801a2e6: 4b82 ldr r3, [pc, #520] ; (801a4f0 ) 801a2e8: 881b ldrh r3, [r3, #0] 801a2ea: 2b00 cmp r3, #0 801a2ec: d008 beq.n 801a300 /* pcb has been aborted or refused data is still refused and the new segment contains data */ if (pcb->rcv_ann_wnd == 0) { 801a2ee: 69bb ldr r3, [r7, #24] 801a2f0: 8d5b ldrh r3, [r3, #42] ; 0x2a 801a2f2: 2b00 cmp r3, #0 801a2f4: f040 80e4 bne.w 801a4c0 /* this is a zero-window probe, we respond to it with current RCV.NXT and drop the data segment */ tcp_send_empty_ack(pcb); 801a2f8: 69b8 ldr r0, [r7, #24] 801a2fa: f003 fe71 bl 801dfe0 } TCP_STATS_INC(tcp.drop); MIB2_STATS_INC(mib2.tcpinerrs); goto aborted; 801a2fe: e0df b.n 801a4c0 } } tcp_input_pcb = pcb; 801a300: 4a7c ldr r2, [pc, #496] ; (801a4f4 ) 801a302: 69bb ldr r3, [r7, #24] 801a304: 6013 str r3, [r2, #0] err = tcp_process(pcb); 801a306: 69b8 ldr r0, [r7, #24] 801a308: f000 fb18 bl 801a93c 801a30c: 4603 mov r3, r0 801a30e: 74fb strb r3, [r7, #19] /* A return value of ERR_ABRT means that tcp_abort() was called and that the pcb has been freed. If so, we don't do anything. */ if (err != ERR_ABRT) { 801a310: f997 3013 ldrsb.w r3, [r7, #19] 801a314: f113 0f0d cmn.w r3, #13 801a318: f000 80d4 beq.w 801a4c4 if (recv_flags & TF_RESET) { 801a31c: 4b71 ldr r3, [pc, #452] ; (801a4e4 ) 801a31e: 781b ldrb r3, [r3, #0] 801a320: f003 0308 and.w r3, r3, #8 801a324: 2b00 cmp r3, #0 801a326: d015 beq.n 801a354 /* TF_RESET means that the connection was reset by the other end. We then call the error callback to inform the application that the connection is dead before we deallocate the PCB. */ TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST); 801a328: 69bb ldr r3, [r7, #24] 801a32a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 801a32e: 2b00 cmp r3, #0 801a330: d008 beq.n 801a344 801a332: 69bb ldr r3, [r7, #24] 801a334: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 801a338: 69ba ldr r2, [r7, #24] 801a33a: 6912 ldr r2, [r2, #16] 801a33c: f06f 010d mvn.w r1, #13 801a340: 4610 mov r0, r2 801a342: 4798 blx r3 tcp_pcb_remove(&tcp_active_pcbs, pcb); 801a344: 69b9 ldr r1, [r7, #24] 801a346: 486c ldr r0, [pc, #432] ; (801a4f8 ) 801a348: f7ff fbb6 bl 8019ab8 tcp_free(pcb); 801a34c: 69b8 ldr r0, [r7, #24] 801a34e: f7fd fe7f bl 8018050 801a352: e0da b.n 801a50a } else { err = ERR_OK; 801a354: 2300 movs r3, #0 801a356: 74fb strb r3, [r7, #19] /* If the application has registered a "sent" function to be called when new send buffer space is available, we call it now. */ if (recv_acked > 0) { 801a358: 4b63 ldr r3, [pc, #396] ; (801a4e8 ) 801a35a: 881b ldrh r3, [r3, #0] 801a35c: 2b00 cmp r3, #0 801a35e: d01d beq.n 801a39c while (acked > 0) { acked16 = (u16_t)LWIP_MIN(acked, 0xffffu); acked -= acked16; #else { acked16 = recv_acked; 801a360: 4b61 ldr r3, [pc, #388] ; (801a4e8 ) 801a362: 881b ldrh r3, [r3, #0] 801a364: 81fb strh r3, [r7, #14] #endif TCP_EVENT_SENT(pcb, (u16_t)acked16, err); 801a366: 69bb ldr r3, [r7, #24] 801a368: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 801a36c: 2b00 cmp r3, #0 801a36e: d00a beq.n 801a386 801a370: 69bb ldr r3, [r7, #24] 801a372: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 801a376: 69ba ldr r2, [r7, #24] 801a378: 6910 ldr r0, [r2, #16] 801a37a: 89fa ldrh r2, [r7, #14] 801a37c: 69b9 ldr r1, [r7, #24] 801a37e: 4798 blx r3 801a380: 4603 mov r3, r0 801a382: 74fb strb r3, [r7, #19] 801a384: e001 b.n 801a38a 801a386: 2300 movs r3, #0 801a388: 74fb strb r3, [r7, #19] if (err == ERR_ABRT) { 801a38a: f997 3013 ldrsb.w r3, [r7, #19] 801a38e: f113 0f0d cmn.w r3, #13 801a392: f000 8099 beq.w 801a4c8 goto aborted; } } recv_acked = 0; 801a396: 4b54 ldr r3, [pc, #336] ; (801a4e8 ) 801a398: 2200 movs r2, #0 801a39a: 801a strh r2, [r3, #0] } if (tcp_input_delayed_close(pcb)) { 801a39c: 69b8 ldr r0, [r7, #24] 801a39e: f000 f915 bl 801a5cc 801a3a2: 4603 mov r3, r0 801a3a4: 2b00 cmp r3, #0 801a3a6: f040 8091 bne.w 801a4cc #if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE while (recv_data != NULL) { struct pbuf *rest = NULL; pbuf_split_64k(recv_data, &rest); #else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ if (recv_data != NULL) { 801a3aa: 4b4d ldr r3, [pc, #308] ; (801a4e0 ) 801a3ac: 681b ldr r3, [r3, #0] 801a3ae: 2b00 cmp r3, #0 801a3b0: d041 beq.n 801a436 #endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL); 801a3b2: 69bb ldr r3, [r7, #24] 801a3b4: 6f9b ldr r3, [r3, #120] ; 0x78 801a3b6: 2b00 cmp r3, #0 801a3b8: d006 beq.n 801a3c8 801a3ba: 4b50 ldr r3, [pc, #320] ; (801a4fc ) 801a3bc: f44f 72f3 mov.w r2, #486 ; 0x1e6 801a3c0: 494f ldr r1, [pc, #316] ; (801a500 ) 801a3c2: 4850 ldr r0, [pc, #320] ; (801a504 ) 801a3c4: f007 fae0 bl 8021988 if (pcb->flags & TF_RXCLOSED) { 801a3c8: 69bb ldr r3, [r7, #24] 801a3ca: 8b5b ldrh r3, [r3, #26] 801a3cc: f003 0310 and.w r3, r3, #16 801a3d0: 2b00 cmp r3, #0 801a3d2: d008 beq.n 801a3e6 /* received data although already closed -> abort (send RST) to notify the remote host that not all data has been processed */ pbuf_free(recv_data); 801a3d4: 4b42 ldr r3, [pc, #264] ; (801a4e0 ) 801a3d6: 681b ldr r3, [r3, #0] 801a3d8: 4618 mov r0, r3 801a3da: f7fd fb8d bl 8017af8 #if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE if (rest != NULL) { pbuf_free(rest); } #endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ tcp_abort(pcb); 801a3de: 69b8 ldr r0, [r7, #24] 801a3e0: f7fe f97a bl 80186d8 goto aborted; 801a3e4: e091 b.n 801a50a } /* Notify application that data has been received. */ TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); 801a3e6: 69bb ldr r3, [r7, #24] 801a3e8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 801a3ec: 2b00 cmp r3, #0 801a3ee: d00c beq.n 801a40a 801a3f0: 69bb ldr r3, [r7, #24] 801a3f2: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 801a3f6: 69bb ldr r3, [r7, #24] 801a3f8: 6918 ldr r0, [r3, #16] 801a3fa: 4b39 ldr r3, [pc, #228] ; (801a4e0 ) 801a3fc: 681a ldr r2, [r3, #0] 801a3fe: 2300 movs r3, #0 801a400: 69b9 ldr r1, [r7, #24] 801a402: 47a0 blx r4 801a404: 4603 mov r3, r0 801a406: 74fb strb r3, [r7, #19] 801a408: e008 b.n 801a41c 801a40a: 4b35 ldr r3, [pc, #212] ; (801a4e0 ) 801a40c: 681a ldr r2, [r3, #0] 801a40e: 2300 movs r3, #0 801a410: 69b9 ldr r1, [r7, #24] 801a412: 2000 movs r0, #0 801a414: f7ff f88a bl 801952c 801a418: 4603 mov r3, r0 801a41a: 74fb strb r3, [r7, #19] if (err == ERR_ABRT) { 801a41c: f997 3013 ldrsb.w r3, [r7, #19] 801a420: f113 0f0d cmn.w r3, #13 801a424: d054 beq.n 801a4d0 #endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ goto aborted; } /* If the upper layer can't receive this data, store it */ if (err != ERR_OK) { 801a426: f997 3013 ldrsb.w r3, [r7, #19] 801a42a: 2b00 cmp r3, #0 801a42c: d003 beq.n 801a436 #if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE if (rest != NULL) { pbuf_cat(recv_data, rest); } #endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ pcb->refused_data = recv_data; 801a42e: 4b2c ldr r3, [pc, #176] ; (801a4e0 ) 801a430: 681a ldr r2, [r3, #0] 801a432: 69bb ldr r3, [r7, #24] 801a434: 679a str r2, [r3, #120] ; 0x78 } } /* If a FIN segment was received, we call the callback function with a NULL buffer to indicate EOF. */ if (recv_flags & TF_GOT_FIN) { 801a436: 4b2b ldr r3, [pc, #172] ; (801a4e4 ) 801a438: 781b ldrb r3, [r3, #0] 801a43a: f003 0320 and.w r3, r3, #32 801a43e: 2b00 cmp r3, #0 801a440: d031 beq.n 801a4a6 if (pcb->refused_data != NULL) { 801a442: 69bb ldr r3, [r7, #24] 801a444: 6f9b ldr r3, [r3, #120] ; 0x78 801a446: 2b00 cmp r3, #0 801a448: d009 beq.n 801a45e /* Delay this if we have refused data. */ pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN; 801a44a: 69bb ldr r3, [r7, #24] 801a44c: 6f9b ldr r3, [r3, #120] ; 0x78 801a44e: 7b5a ldrb r2, [r3, #13] 801a450: 69bb ldr r3, [r7, #24] 801a452: 6f9b ldr r3, [r3, #120] ; 0x78 801a454: f042 0220 orr.w r2, r2, #32 801a458: b2d2 uxtb r2, r2 801a45a: 735a strb r2, [r3, #13] 801a45c: e023 b.n 801a4a6 } else { /* correct rcv_wnd as the application won't call tcp_recved() for the FIN's seqno */ if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) { 801a45e: 69bb ldr r3, [r7, #24] 801a460: 8d1b ldrh r3, [r3, #40] ; 0x28 801a462: f241 62d0 movw r2, #5840 ; 0x16d0 801a466: 4293 cmp r3, r2 801a468: d005 beq.n 801a476 pcb->rcv_wnd++; 801a46a: 69bb ldr r3, [r7, #24] 801a46c: 8d1b ldrh r3, [r3, #40] ; 0x28 801a46e: 3301 adds r3, #1 801a470: b29a uxth r2, r3 801a472: 69bb ldr r3, [r7, #24] 801a474: 851a strh r2, [r3, #40] ; 0x28 } TCP_EVENT_CLOSED(pcb, err); 801a476: 69bb ldr r3, [r7, #24] 801a478: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 801a47c: 2b00 cmp r3, #0 801a47e: d00b beq.n 801a498 801a480: 69bb ldr r3, [r7, #24] 801a482: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 801a486: 69bb ldr r3, [r7, #24] 801a488: 6918 ldr r0, [r3, #16] 801a48a: 2300 movs r3, #0 801a48c: 2200 movs r2, #0 801a48e: 69b9 ldr r1, [r7, #24] 801a490: 47a0 blx r4 801a492: 4603 mov r3, r0 801a494: 74fb strb r3, [r7, #19] 801a496: e001 b.n 801a49c 801a498: 2300 movs r3, #0 801a49a: 74fb strb r3, [r7, #19] if (err == ERR_ABRT) { 801a49c: f997 3013 ldrsb.w r3, [r7, #19] 801a4a0: f113 0f0d cmn.w r3, #13 801a4a4: d016 beq.n 801a4d4 goto aborted; } } } tcp_input_pcb = NULL; 801a4a6: 4b13 ldr r3, [pc, #76] ; (801a4f4 ) 801a4a8: 2200 movs r2, #0 801a4aa: 601a str r2, [r3, #0] if (tcp_input_delayed_close(pcb)) { 801a4ac: 69b8 ldr r0, [r7, #24] 801a4ae: f000 f88d bl 801a5cc 801a4b2: 4603 mov r3, r0 801a4b4: 2b00 cmp r3, #0 801a4b6: d127 bne.n 801a508 goto aborted; } /* Try to send something out. */ tcp_output(pcb); 801a4b8: 69b8 ldr r0, [r7, #24] 801a4ba: f002 ff7f bl 801d3bc 801a4be: e024 b.n 801a50a goto aborted; 801a4c0: bf00 nop 801a4c2: e022 b.n 801a50a #endif /* TCP_INPUT_DEBUG */ } } /* Jump target if pcb has been aborted in a callback (by calling tcp_abort()). Below this line, 'pcb' may not be dereferenced! */ aborted: 801a4c4: bf00 nop 801a4c6: e020 b.n 801a50a goto aborted; 801a4c8: bf00 nop 801a4ca: e01e b.n 801a50a goto aborted; 801a4cc: bf00 nop 801a4ce: e01c b.n 801a50a goto aborted; 801a4d0: bf00 nop 801a4d2: e01a b.n 801a50a goto aborted; 801a4d4: bf00 nop 801a4d6: e018 b.n 801a50a 801a4d8: 2401a498 .word 0x2401a498 801a4dc: 2401a4ac .word 0x2401a4ac 801a4e0: 2401a4cc .word 0x2401a4cc 801a4e4: 2401a4c9 .word 0x2401a4c9 801a4e8: 2401a4c4 .word 0x2401a4c4 801a4ec: 2401a4c8 .word 0x2401a4c8 801a4f0: 2401a4c6 .word 0x2401a4c6 801a4f4: 2401a4d0 .word 0x2401a4d0 801a4f8: 2401a48c .word 0x2401a48c 801a4fc: 08025338 .word 0x08025338 801a500: 080254ec .word 0x080254ec 801a504: 08025384 .word 0x08025384 goto aborted; 801a508: bf00 nop tcp_input_pcb = NULL; 801a50a: 4b27 ldr r3, [pc, #156] ; (801a5a8 ) 801a50c: 2200 movs r2, #0 801a50e: 601a str r2, [r3, #0] recv_data = NULL; 801a510: 4b26 ldr r3, [pc, #152] ; (801a5ac ) 801a512: 2200 movs r2, #0 801a514: 601a str r2, [r3, #0] /* give up our reference to inseg.p */ if (inseg.p != NULL) { 801a516: 4b26 ldr r3, [pc, #152] ; (801a5b0 ) 801a518: 685b ldr r3, [r3, #4] 801a51a: 2b00 cmp r3, #0 801a51c: d03f beq.n 801a59e pbuf_free(inseg.p); 801a51e: 4b24 ldr r3, [pc, #144] ; (801a5b0 ) 801a520: 685b ldr r3, [r3, #4] 801a522: 4618 mov r0, r3 801a524: f7fd fae8 bl 8017af8 inseg.p = NULL; 801a528: 4b21 ldr r3, [pc, #132] ; (801a5b0 ) 801a52a: 2200 movs r2, #0 801a52c: 605a str r2, [r3, #4] pbuf_free(p); } LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); PERF_STOP("tcp_input"); return; 801a52e: e036 b.n 801a59e if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { 801a530: 4b20 ldr r3, [pc, #128] ; (801a5b4 ) 801a532: 681b ldr r3, [r3, #0] 801a534: 899b ldrh r3, [r3, #12] 801a536: b29b uxth r3, r3 801a538: 4618 mov r0, r3 801a53a: f7fb fd01 bl 8015f40 801a53e: 4603 mov r3, r0 801a540: b2db uxtb r3, r3 801a542: f003 0304 and.w r3, r3, #4 801a546: 2b00 cmp r3, #0 801a548: d118 bne.n 801a57c tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(), 801a54a: 4b1b ldr r3, [pc, #108] ; (801a5b8 ) 801a54c: 6819 ldr r1, [r3, #0] 801a54e: 4b1b ldr r3, [pc, #108] ; (801a5bc ) 801a550: 881b ldrh r3, [r3, #0] 801a552: 461a mov r2, r3 801a554: 4b1a ldr r3, [pc, #104] ; (801a5c0 ) 801a556: 681b ldr r3, [r3, #0] 801a558: 18d0 adds r0, r2, r3 ip_current_src_addr(), tcphdr->dest, tcphdr->src); 801a55a: 4b16 ldr r3, [pc, #88] ; (801a5b4 ) 801a55c: 681b ldr r3, [r3, #0] tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(), 801a55e: 885b ldrh r3, [r3, #2] 801a560: b29b uxth r3, r3 ip_current_src_addr(), tcphdr->dest, tcphdr->src); 801a562: 4a14 ldr r2, [pc, #80] ; (801a5b4 ) 801a564: 6812 ldr r2, [r2, #0] tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(), 801a566: 8812 ldrh r2, [r2, #0] 801a568: b292 uxth r2, r2 801a56a: 9202 str r2, [sp, #8] 801a56c: 9301 str r3, [sp, #4] 801a56e: 4b15 ldr r3, [pc, #84] ; (801a5c4 ) 801a570: 9300 str r3, [sp, #0] 801a572: 4b15 ldr r3, [pc, #84] ; (801a5c8 ) 801a574: 4602 mov r2, r0 801a576: 2000 movs r0, #0 801a578: f003 fce0 bl 801df3c pbuf_free(p); 801a57c: 6878 ldr r0, [r7, #4] 801a57e: f7fd fabb bl 8017af8 return; 801a582: e00c b.n 801a59e goto dropped; 801a584: bf00 nop 801a586: e006 b.n 801a596 goto dropped; 801a588: bf00 nop 801a58a: e004 b.n 801a596 goto dropped; 801a58c: bf00 nop 801a58e: e002 b.n 801a596 goto dropped; 801a590: bf00 nop 801a592: e000 b.n 801a596 goto dropped; 801a594: bf00 nop dropped: TCP_STATS_INC(tcp.drop); MIB2_STATS_INC(mib2.tcpinerrs); pbuf_free(p); 801a596: 6878 ldr r0, [r7, #4] 801a598: f7fd faae bl 8017af8 801a59c: e000 b.n 801a5a0 return; 801a59e: bf00 nop } 801a5a0: 3724 adds r7, #36 ; 0x24 801a5a2: 46bd mov sp, r7 801a5a4: bd90 pop {r4, r7, pc} 801a5a6: bf00 nop 801a5a8: 2401a4d0 .word 0x2401a4d0 801a5ac: 2401a4cc .word 0x2401a4cc 801a5b0: 2401a498 .word 0x2401a498 801a5b4: 2401a4ac .word 0x2401a4ac 801a5b8: 2401a4c0 .word 0x2401a4c0 801a5bc: 2401a4c6 .word 0x2401a4c6 801a5c0: 2401a4bc .word 0x2401a4bc 801a5c4: 24013990 .word 0x24013990 801a5c8: 24013994 .word 0x24013994 0801a5cc : * any more. * @returns 1 if the pcb has been closed and deallocated, 0 otherwise */ static int tcp_input_delayed_close(struct tcp_pcb *pcb) { 801a5cc: b580 push {r7, lr} 801a5ce: b082 sub sp, #8 801a5d0: af00 add r7, sp, #0 801a5d2: 6078 str r0, [r7, #4] LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL); 801a5d4: 687b ldr r3, [r7, #4] 801a5d6: 2b00 cmp r3, #0 801a5d8: d106 bne.n 801a5e8 801a5da: 4b17 ldr r3, [pc, #92] ; (801a638 ) 801a5dc: f240 225a movw r2, #602 ; 0x25a 801a5e0: 4916 ldr r1, [pc, #88] ; (801a63c ) 801a5e2: 4817 ldr r0, [pc, #92] ; (801a640 ) 801a5e4: f007 f9d0 bl 8021988 if (recv_flags & TF_CLOSED) { 801a5e8: 4b16 ldr r3, [pc, #88] ; (801a644 ) 801a5ea: 781b ldrb r3, [r3, #0] 801a5ec: f003 0310 and.w r3, r3, #16 801a5f0: 2b00 cmp r3, #0 801a5f2: d01c beq.n 801a62e /* The connection has been closed and we will deallocate the PCB. */ if (!(pcb->flags & TF_RXCLOSED)) { 801a5f4: 687b ldr r3, [r7, #4] 801a5f6: 8b5b ldrh r3, [r3, #26] 801a5f8: f003 0310 and.w r3, r3, #16 801a5fc: 2b00 cmp r3, #0 801a5fe: d10d bne.n 801a61c /* Connection closed although the application has only shut down the tx side: call the PCB's err callback and indicate the closure to ensure the application doesn't continue using the PCB. */ TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD); 801a600: 687b ldr r3, [r7, #4] 801a602: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 801a606: 2b00 cmp r3, #0 801a608: d008 beq.n 801a61c 801a60a: 687b ldr r3, [r7, #4] 801a60c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 801a610: 687a ldr r2, [r7, #4] 801a612: 6912 ldr r2, [r2, #16] 801a614: f06f 010e mvn.w r1, #14 801a618: 4610 mov r0, r2 801a61a: 4798 blx r3 } tcp_pcb_remove(&tcp_active_pcbs, pcb); 801a61c: 6879 ldr r1, [r7, #4] 801a61e: 480a ldr r0, [pc, #40] ; (801a648 ) 801a620: f7ff fa4a bl 8019ab8 tcp_free(pcb); 801a624: 6878 ldr r0, [r7, #4] 801a626: f7fd fd13 bl 8018050 return 1; 801a62a: 2301 movs r3, #1 801a62c: e000 b.n 801a630 } return 0; 801a62e: 2300 movs r3, #0 } 801a630: 4618 mov r0, r3 801a632: 3708 adds r7, #8 801a634: 46bd mov sp, r7 801a636: bd80 pop {r7, pc} 801a638: 08025338 .word 0x08025338 801a63c: 08025508 .word 0x08025508 801a640: 08025384 .word 0x08025384 801a644: 2401a4c9 .word 0x2401a4c9 801a648: 2401a48c .word 0x2401a48c 0801a64c : * @note the segment which arrived is saved in global variables, therefore only the pcb * involved is passed as a parameter to this function */ static void tcp_listen_input(struct tcp_pcb_listen *pcb) { 801a64c: b590 push {r4, r7, lr} 801a64e: b08b sub sp, #44 ; 0x2c 801a650: af04 add r7, sp, #16 801a652: 6078 str r0, [r7, #4] struct tcp_pcb *npcb; u32_t iss; err_t rc; if (flags & TCP_RST) { 801a654: 4b6f ldr r3, [pc, #444] ; (801a814 ) 801a656: 781b ldrb r3, [r3, #0] 801a658: f003 0304 and.w r3, r3, #4 801a65c: 2b00 cmp r3, #0 801a65e: f040 80d2 bne.w 801a806 /* An incoming RST should be ignored. Return. */ return; } LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL); 801a662: 687b ldr r3, [r7, #4] 801a664: 2b00 cmp r3, #0 801a666: d106 bne.n 801a676 801a668: 4b6b ldr r3, [pc, #428] ; (801a818 ) 801a66a: f240 2281 movw r2, #641 ; 0x281 801a66e: 496b ldr r1, [pc, #428] ; (801a81c ) 801a670: 486b ldr r0, [pc, #428] ; (801a820 ) 801a672: f007 f989 bl 8021988 /* In the LISTEN state, we check for incoming SYN segments, creates a new PCB, and responds with a SYN|ACK. */ if (flags & TCP_ACK) { 801a676: 4b67 ldr r3, [pc, #412] ; (801a814 ) 801a678: 781b ldrb r3, [r3, #0] 801a67a: f003 0310 and.w r3, r3, #16 801a67e: 2b00 cmp r3, #0 801a680: d019 beq.n 801a6b6 /* For incoming segments with the ACK flag set, respond with a RST. */ LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801a682: 4b68 ldr r3, [pc, #416] ; (801a824 ) 801a684: 6819 ldr r1, [r3, #0] 801a686: 4b68 ldr r3, [pc, #416] ; (801a828 ) 801a688: 881b ldrh r3, [r3, #0] 801a68a: 461a mov r2, r3 801a68c: 4b67 ldr r3, [pc, #412] ; (801a82c ) 801a68e: 681b ldr r3, [r3, #0] 801a690: 18d0 adds r0, r2, r3 ip_current_src_addr(), tcphdr->dest, tcphdr->src); 801a692: 4b67 ldr r3, [pc, #412] ; (801a830 ) 801a694: 681b ldr r3, [r3, #0] tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801a696: 885b ldrh r3, [r3, #2] 801a698: b29b uxth r3, r3 ip_current_src_addr(), tcphdr->dest, tcphdr->src); 801a69a: 4a65 ldr r2, [pc, #404] ; (801a830 ) 801a69c: 6812 ldr r2, [r2, #0] tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801a69e: 8812 ldrh r2, [r2, #0] 801a6a0: b292 uxth r2, r2 801a6a2: 9202 str r2, [sp, #8] 801a6a4: 9301 str r3, [sp, #4] 801a6a6: 4b63 ldr r3, [pc, #396] ; (801a834 ) 801a6a8: 9300 str r3, [sp, #0] 801a6aa: 4b63 ldr r3, [pc, #396] ; (801a838 ) 801a6ac: 4602 mov r2, r0 801a6ae: 6878 ldr r0, [r7, #4] 801a6b0: f003 fc44 bl 801df3c tcp_abandon(npcb, 0); return; } tcp_output(npcb); } return; 801a6b4: e0a9 b.n 801a80a } else if (flags & TCP_SYN) { 801a6b6: 4b57 ldr r3, [pc, #348] ; (801a814 ) 801a6b8: 781b ldrb r3, [r3, #0] 801a6ba: f003 0302 and.w r3, r3, #2 801a6be: 2b00 cmp r3, #0 801a6c0: f000 80a3 beq.w 801a80a npcb = tcp_alloc(pcb->prio); 801a6c4: 687b ldr r3, [r7, #4] 801a6c6: 7d5b ldrb r3, [r3, #21] 801a6c8: 4618 mov r0, r3 801a6ca: f7ff f853 bl 8019774 801a6ce: 6178 str r0, [r7, #20] if (npcb == NULL) { 801a6d0: 697b ldr r3, [r7, #20] 801a6d2: 2b00 cmp r3, #0 801a6d4: d111 bne.n 801a6fa TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err); 801a6d6: 687b ldr r3, [r7, #4] 801a6d8: 699b ldr r3, [r3, #24] 801a6da: 2b00 cmp r3, #0 801a6dc: d00a beq.n 801a6f4 801a6de: 687b ldr r3, [r7, #4] 801a6e0: 699b ldr r3, [r3, #24] 801a6e2: 687a ldr r2, [r7, #4] 801a6e4: 6910 ldr r0, [r2, #16] 801a6e6: f04f 32ff mov.w r2, #4294967295 801a6ea: 2100 movs r1, #0 801a6ec: 4798 blx r3 801a6ee: 4603 mov r3, r0 801a6f0: 73bb strb r3, [r7, #14] return; 801a6f2: e08b b.n 801a80c TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err); 801a6f4: 23f0 movs r3, #240 ; 0xf0 801a6f6: 73bb strb r3, [r7, #14] return; 801a6f8: e088 b.n 801a80c ip_addr_copy(npcb->local_ip, *ip_current_dest_addr()); 801a6fa: 4b50 ldr r3, [pc, #320] ; (801a83c ) 801a6fc: 695a ldr r2, [r3, #20] 801a6fe: 697b ldr r3, [r7, #20] 801a700: 601a str r2, [r3, #0] ip_addr_copy(npcb->remote_ip, *ip_current_src_addr()); 801a702: 4b4e ldr r3, [pc, #312] ; (801a83c ) 801a704: 691a ldr r2, [r3, #16] 801a706: 697b ldr r3, [r7, #20] 801a708: 605a str r2, [r3, #4] npcb->local_port = pcb->local_port; 801a70a: 687b ldr r3, [r7, #4] 801a70c: 8ada ldrh r2, [r3, #22] 801a70e: 697b ldr r3, [r7, #20] 801a710: 82da strh r2, [r3, #22] npcb->remote_port = tcphdr->src; 801a712: 4b47 ldr r3, [pc, #284] ; (801a830 ) 801a714: 681b ldr r3, [r3, #0] 801a716: 881b ldrh r3, [r3, #0] 801a718: b29a uxth r2, r3 801a71a: 697b ldr r3, [r7, #20] 801a71c: 831a strh r2, [r3, #24] npcb->state = SYN_RCVD; 801a71e: 697b ldr r3, [r7, #20] 801a720: 2203 movs r2, #3 801a722: 751a strb r2, [r3, #20] npcb->rcv_nxt = seqno + 1; 801a724: 4b41 ldr r3, [pc, #260] ; (801a82c ) 801a726: 681b ldr r3, [r3, #0] 801a728: 1c5a adds r2, r3, #1 801a72a: 697b ldr r3, [r7, #20] 801a72c: 625a str r2, [r3, #36] ; 0x24 npcb->rcv_ann_right_edge = npcb->rcv_nxt; 801a72e: 697b ldr r3, [r7, #20] 801a730: 6a5a ldr r2, [r3, #36] ; 0x24 801a732: 697b ldr r3, [r7, #20] 801a734: 62da str r2, [r3, #44] ; 0x2c iss = tcp_next_iss(npcb); 801a736: 6978 ldr r0, [r7, #20] 801a738: f7ff fa52 bl 8019be0 801a73c: 6138 str r0, [r7, #16] npcb->snd_wl2 = iss; 801a73e: 697b ldr r3, [r7, #20] 801a740: 693a ldr r2, [r7, #16] 801a742: 659a str r2, [r3, #88] ; 0x58 npcb->snd_nxt = iss; 801a744: 697b ldr r3, [r7, #20] 801a746: 693a ldr r2, [r7, #16] 801a748: 651a str r2, [r3, #80] ; 0x50 npcb->lastack = iss; 801a74a: 697b ldr r3, [r7, #20] 801a74c: 693a ldr r2, [r7, #16] 801a74e: 645a str r2, [r3, #68] ; 0x44 npcb->snd_lbb = iss; 801a750: 697b ldr r3, [r7, #20] 801a752: 693a ldr r2, [r7, #16] 801a754: 65da str r2, [r3, #92] ; 0x5c npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ 801a756: 4b35 ldr r3, [pc, #212] ; (801a82c ) 801a758: 681b ldr r3, [r3, #0] 801a75a: 1e5a subs r2, r3, #1 801a75c: 697b ldr r3, [r7, #20] 801a75e: 655a str r2, [r3, #84] ; 0x54 npcb->callback_arg = pcb->callback_arg; 801a760: 687b ldr r3, [r7, #4] 801a762: 691a ldr r2, [r3, #16] 801a764: 697b ldr r3, [r7, #20] 801a766: 611a str r2, [r3, #16] npcb->listener = pcb; 801a768: 697b ldr r3, [r7, #20] 801a76a: 687a ldr r2, [r7, #4] 801a76c: 67da str r2, [r3, #124] ; 0x7c npcb->so_options = pcb->so_options & SOF_INHERITED; 801a76e: 687b ldr r3, [r7, #4] 801a770: 7a5b ldrb r3, [r3, #9] 801a772: f003 030c and.w r3, r3, #12 801a776: b2da uxtb r2, r3 801a778: 697b ldr r3, [r7, #20] 801a77a: 725a strb r2, [r3, #9] npcb->netif_idx = pcb->netif_idx; 801a77c: 687b ldr r3, [r7, #4] 801a77e: 7a1a ldrb r2, [r3, #8] 801a780: 697b ldr r3, [r7, #20] 801a782: 721a strb r2, [r3, #8] TCP_REG_ACTIVE(npcb); 801a784: 4b2e ldr r3, [pc, #184] ; (801a840 ) 801a786: 681a ldr r2, [r3, #0] 801a788: 697b ldr r3, [r7, #20] 801a78a: 60da str r2, [r3, #12] 801a78c: 4a2c ldr r2, [pc, #176] ; (801a840 ) 801a78e: 697b ldr r3, [r7, #20] 801a790: 6013 str r3, [r2, #0] 801a792: f003 fd95 bl 801e2c0 801a796: 4b2b ldr r3, [pc, #172] ; (801a844 ) 801a798: 2201 movs r2, #1 801a79a: 701a strb r2, [r3, #0] tcp_parseopt(npcb); 801a79c: 6978 ldr r0, [r7, #20] 801a79e: f001 fd8f bl 801c2c0 npcb->snd_wnd = tcphdr->wnd; 801a7a2: 4b23 ldr r3, [pc, #140] ; (801a830 ) 801a7a4: 681b ldr r3, [r3, #0] 801a7a6: 89db ldrh r3, [r3, #14] 801a7a8: b29a uxth r2, r3 801a7aa: 697b ldr r3, [r7, #20] 801a7ac: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 npcb->snd_wnd_max = npcb->snd_wnd; 801a7b0: 697b ldr r3, [r7, #20] 801a7b2: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 801a7b6: 697b ldr r3, [r7, #20] 801a7b8: f8a3 2062 strh.w r2, [r3, #98] ; 0x62 npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip); 801a7bc: 697b ldr r3, [r7, #20] 801a7be: 8e5c ldrh r4, [r3, #50] ; 0x32 801a7c0: 697b ldr r3, [r7, #20] 801a7c2: 3304 adds r3, #4 801a7c4: 4618 mov r0, r3 801a7c6: f005 fb95 bl 801fef4 801a7ca: 4601 mov r1, r0 801a7cc: 697b ldr r3, [r7, #20] 801a7ce: 3304 adds r3, #4 801a7d0: 461a mov r2, r3 801a7d2: 4620 mov r0, r4 801a7d4: f7ff fa2a bl 8019c2c 801a7d8: 4603 mov r3, r0 801a7da: 461a mov r2, r3 801a7dc: 697b ldr r3, [r7, #20] 801a7de: 865a strh r2, [r3, #50] ; 0x32 rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK); 801a7e0: 2112 movs r1, #18 801a7e2: 6978 ldr r0, [r7, #20] 801a7e4: f002 fcfc bl 801d1e0 801a7e8: 4603 mov r3, r0 801a7ea: 73fb strb r3, [r7, #15] if (rc != ERR_OK) { 801a7ec: f997 300f ldrsb.w r3, [r7, #15] 801a7f0: 2b00 cmp r3, #0 801a7f2: d004 beq.n 801a7fe tcp_abandon(npcb, 0); 801a7f4: 2100 movs r1, #0 801a7f6: 6978 ldr r0, [r7, #20] 801a7f8: f7fd feb0 bl 801855c return; 801a7fc: e006 b.n 801a80c tcp_output(npcb); 801a7fe: 6978 ldr r0, [r7, #20] 801a800: f002 fddc bl 801d3bc return; 801a804: e001 b.n 801a80a return; 801a806: bf00 nop 801a808: e000 b.n 801a80c return; 801a80a: bf00 nop } 801a80c: 371c adds r7, #28 801a80e: 46bd mov sp, r7 801a810: bd90 pop {r4, r7, pc} 801a812: bf00 nop 801a814: 2401a4c8 .word 0x2401a4c8 801a818: 08025338 .word 0x08025338 801a81c: 08025530 .word 0x08025530 801a820: 08025384 .word 0x08025384 801a824: 2401a4c0 .word 0x2401a4c0 801a828: 2401a4c6 .word 0x2401a4c6 801a82c: 2401a4bc .word 0x2401a4bc 801a830: 2401a4ac .word 0x2401a4ac 801a834: 24013990 .word 0x24013990 801a838: 24013994 .word 0x24013994 801a83c: 24013980 .word 0x24013980 801a840: 2401a48c .word 0x2401a48c 801a844: 2401a494 .word 0x2401a494 0801a848 : * @note the segment which arrived is saved in global variables, therefore only the pcb * involved is passed as a parameter to this function */ static void tcp_timewait_input(struct tcp_pcb *pcb) { 801a848: b580 push {r7, lr} 801a84a: b086 sub sp, #24 801a84c: af04 add r7, sp, #16 801a84e: 6078 str r0, [r7, #4] /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */ /* RFC 793 3.9 Event Processing - Segment Arrives: * - first check sequence number - we skip that one in TIME_WAIT (always * acceptable since we only send ACKs) * - second check the RST bit (... return) */ if (flags & TCP_RST) { 801a850: 4b2f ldr r3, [pc, #188] ; (801a910 ) 801a852: 781b ldrb r3, [r3, #0] 801a854: f003 0304 and.w r3, r3, #4 801a858: 2b00 cmp r3, #0 801a85a: d153 bne.n 801a904 return; } LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL); 801a85c: 687b ldr r3, [r7, #4] 801a85e: 2b00 cmp r3, #0 801a860: d106 bne.n 801a870 801a862: 4b2c ldr r3, [pc, #176] ; (801a914 ) 801a864: f240 22ee movw r2, #750 ; 0x2ee 801a868: 492b ldr r1, [pc, #172] ; (801a918 ) 801a86a: 482c ldr r0, [pc, #176] ; (801a91c ) 801a86c: f007 f88c bl 8021988 /* - fourth, check the SYN bit, */ if (flags & TCP_SYN) { 801a870: 4b27 ldr r3, [pc, #156] ; (801a910 ) 801a872: 781b ldrb r3, [r3, #0] 801a874: f003 0302 and.w r3, r3, #2 801a878: 2b00 cmp r3, #0 801a87a: d02a beq.n 801a8d2 /* If an incoming segment is not acceptable, an acknowledgment should be sent in reply */ if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) { 801a87c: 4b28 ldr r3, [pc, #160] ; (801a920 ) 801a87e: 681a ldr r2, [r3, #0] 801a880: 687b ldr r3, [r7, #4] 801a882: 6a5b ldr r3, [r3, #36] ; 0x24 801a884: 1ad3 subs r3, r2, r3 801a886: 2b00 cmp r3, #0 801a888: db2d blt.n 801a8e6 801a88a: 4b25 ldr r3, [pc, #148] ; (801a920 ) 801a88c: 681a ldr r2, [r3, #0] 801a88e: 687b ldr r3, [r7, #4] 801a890: 6a5b ldr r3, [r3, #36] ; 0x24 801a892: 6879 ldr r1, [r7, #4] 801a894: 8d09 ldrh r1, [r1, #40] ; 0x28 801a896: 440b add r3, r1 801a898: 1ad3 subs r3, r2, r3 801a89a: 2b00 cmp r3, #0 801a89c: dc23 bgt.n 801a8e6 /* If the SYN is in the window it is an error, send a reset */ tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801a89e: 4b21 ldr r3, [pc, #132] ; (801a924 ) 801a8a0: 6819 ldr r1, [r3, #0] 801a8a2: 4b21 ldr r3, [pc, #132] ; (801a928 ) 801a8a4: 881b ldrh r3, [r3, #0] 801a8a6: 461a mov r2, r3 801a8a8: 4b1d ldr r3, [pc, #116] ; (801a920 ) 801a8aa: 681b ldr r3, [r3, #0] 801a8ac: 18d0 adds r0, r2, r3 ip_current_src_addr(), tcphdr->dest, tcphdr->src); 801a8ae: 4b1f ldr r3, [pc, #124] ; (801a92c ) 801a8b0: 681b ldr r3, [r3, #0] tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801a8b2: 885b ldrh r3, [r3, #2] 801a8b4: b29b uxth r3, r3 ip_current_src_addr(), tcphdr->dest, tcphdr->src); 801a8b6: 4a1d ldr r2, [pc, #116] ; (801a92c ) 801a8b8: 6812 ldr r2, [r2, #0] tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801a8ba: 8812 ldrh r2, [r2, #0] 801a8bc: b292 uxth r2, r2 801a8be: 9202 str r2, [sp, #8] 801a8c0: 9301 str r3, [sp, #4] 801a8c2: 4b1b ldr r3, [pc, #108] ; (801a930 ) 801a8c4: 9300 str r3, [sp, #0] 801a8c6: 4b1b ldr r3, [pc, #108] ; (801a934 ) 801a8c8: 4602 mov r2, r0 801a8ca: 6878 ldr r0, [r7, #4] 801a8cc: f003 fb36 bl 801df3c return; 801a8d0: e01b b.n 801a90a } } else if (flags & TCP_FIN) { 801a8d2: 4b0f ldr r3, [pc, #60] ; (801a910 ) 801a8d4: 781b ldrb r3, [r3, #0] 801a8d6: f003 0301 and.w r3, r3, #1 801a8da: 2b00 cmp r3, #0 801a8dc: d003 beq.n 801a8e6 /* - eighth, check the FIN bit: Remain in the TIME-WAIT state. Restart the 2 MSL time-wait timeout.*/ pcb->tmr = tcp_ticks; 801a8de: 4b16 ldr r3, [pc, #88] ; (801a938 ) 801a8e0: 681a ldr r2, [r3, #0] 801a8e2: 687b ldr r3, [r7, #4] 801a8e4: 621a str r2, [r3, #32] } if ((tcplen > 0)) { 801a8e6: 4b10 ldr r3, [pc, #64] ; (801a928 ) 801a8e8: 881b ldrh r3, [r3, #0] 801a8ea: 2b00 cmp r3, #0 801a8ec: d00c beq.n 801a908 /* Acknowledge data, FIN or out-of-window SYN */ tcp_ack_now(pcb); 801a8ee: 687b ldr r3, [r7, #4] 801a8f0: 8b5b ldrh r3, [r3, #26] 801a8f2: f043 0302 orr.w r3, r3, #2 801a8f6: b29a uxth r2, r3 801a8f8: 687b ldr r3, [r7, #4] 801a8fa: 835a strh r2, [r3, #26] tcp_output(pcb); 801a8fc: 6878 ldr r0, [r7, #4] 801a8fe: f002 fd5d bl 801d3bc } return; 801a902: e001 b.n 801a908 return; 801a904: bf00 nop 801a906: e000 b.n 801a90a return; 801a908: bf00 nop } 801a90a: 3708 adds r7, #8 801a90c: 46bd mov sp, r7 801a90e: bd80 pop {r7, pc} 801a910: 2401a4c8 .word 0x2401a4c8 801a914: 08025338 .word 0x08025338 801a918: 08025550 .word 0x08025550 801a91c: 08025384 .word 0x08025384 801a920: 2401a4bc .word 0x2401a4bc 801a924: 2401a4c0 .word 0x2401a4c0 801a928: 2401a4c6 .word 0x2401a4c6 801a92c: 2401a4ac .word 0x2401a4ac 801a930: 24013990 .word 0x24013990 801a934: 24013994 .word 0x24013994 801a938: 2401a480 .word 0x2401a480 0801a93c : * @note the segment which arrived is saved in global variables, therefore only the pcb * involved is passed as a parameter to this function */ static err_t tcp_process(struct tcp_pcb *pcb) { 801a93c: b590 push {r4, r7, lr} 801a93e: b08d sub sp, #52 ; 0x34 801a940: af04 add r7, sp, #16 801a942: 6078 str r0, [r7, #4] struct tcp_seg *rseg; u8_t acceptable = 0; 801a944: 2300 movs r3, #0 801a946: 77fb strb r3, [r7, #31] err_t err; err = ERR_OK; 801a948: 2300 movs r3, #0 801a94a: 77bb strb r3, [r7, #30] LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL); 801a94c: 687b ldr r3, [r7, #4] 801a94e: 2b00 cmp r3, #0 801a950: d106 bne.n 801a960 801a952: 4b9d ldr r3, [pc, #628] ; (801abc8 ) 801a954: f44f 7247 mov.w r2, #796 ; 0x31c 801a958: 499c ldr r1, [pc, #624] ; (801abcc ) 801a95a: 489d ldr r0, [pc, #628] ; (801abd0 ) 801a95c: f007 f814 bl 8021988 /* Process incoming RST segments. */ if (flags & TCP_RST) { 801a960: 4b9c ldr r3, [pc, #624] ; (801abd4 ) 801a962: 781b ldrb r3, [r3, #0] 801a964: f003 0304 and.w r3, r3, #4 801a968: 2b00 cmp r3, #0 801a96a: d04e beq.n 801aa0a /* First, determine if the reset is acceptable. */ if (pcb->state == SYN_SENT) { 801a96c: 687b ldr r3, [r7, #4] 801a96e: 7d1b ldrb r3, [r3, #20] 801a970: 2b02 cmp r3, #2 801a972: d108 bne.n 801a986 /* "In the SYN-SENT state (a RST received in response to an initial SYN), the RST is acceptable if the ACK field acknowledges the SYN." */ if (ackno == pcb->snd_nxt) { 801a974: 687b ldr r3, [r7, #4] 801a976: 6d1a ldr r2, [r3, #80] ; 0x50 801a978: 4b97 ldr r3, [pc, #604] ; (801abd8 ) 801a97a: 681b ldr r3, [r3, #0] 801a97c: 429a cmp r2, r3 801a97e: d123 bne.n 801a9c8 acceptable = 1; 801a980: 2301 movs r3, #1 801a982: 77fb strb r3, [r7, #31] 801a984: e020 b.n 801a9c8 } } else { /* "In all states except SYN-SENT, all reset (RST) segments are validated by checking their SEQ-fields." */ if (seqno == pcb->rcv_nxt) { 801a986: 687b ldr r3, [r7, #4] 801a988: 6a5a ldr r2, [r3, #36] ; 0x24 801a98a: 4b94 ldr r3, [pc, #592] ; (801abdc ) 801a98c: 681b ldr r3, [r3, #0] 801a98e: 429a cmp r2, r3 801a990: d102 bne.n 801a998 acceptable = 1; 801a992: 2301 movs r3, #1 801a994: 77fb strb r3, [r7, #31] 801a996: e017 b.n 801a9c8 } else if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, 801a998: 4b90 ldr r3, [pc, #576] ; (801abdc ) 801a99a: 681a ldr r2, [r3, #0] 801a99c: 687b ldr r3, [r7, #4] 801a99e: 6a5b ldr r3, [r3, #36] ; 0x24 801a9a0: 1ad3 subs r3, r2, r3 801a9a2: 2b00 cmp r3, #0 801a9a4: db10 blt.n 801a9c8 801a9a6: 4b8d ldr r3, [pc, #564] ; (801abdc ) 801a9a8: 681a ldr r2, [r3, #0] 801a9aa: 687b ldr r3, [r7, #4] 801a9ac: 6a5b ldr r3, [r3, #36] ; 0x24 801a9ae: 6879 ldr r1, [r7, #4] 801a9b0: 8d09 ldrh r1, [r1, #40] ; 0x28 801a9b2: 440b add r3, r1 801a9b4: 1ad3 subs r3, r2, r3 801a9b6: 2b00 cmp r3, #0 801a9b8: dc06 bgt.n 801a9c8 pcb->rcv_nxt + pcb->rcv_wnd)) { /* If the sequence number is inside the window, we send a challenge ACK and wait for a re-send with matching sequence number. This follows RFC 5961 section 3.2 and addresses CVE-2004-0230 (RST spoofing attack), which is present in RFC 793 RST handling. */ tcp_ack_now(pcb); 801a9ba: 687b ldr r3, [r7, #4] 801a9bc: 8b5b ldrh r3, [r3, #26] 801a9be: f043 0302 orr.w r3, r3, #2 801a9c2: b29a uxth r2, r3 801a9c4: 687b ldr r3, [r7, #4] 801a9c6: 835a strh r2, [r3, #26] } } if (acceptable) { 801a9c8: 7ffb ldrb r3, [r7, #31] 801a9ca: 2b00 cmp r3, #0 801a9cc: d01b beq.n 801aa06 LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); 801a9ce: 687b ldr r3, [r7, #4] 801a9d0: 7d1b ldrb r3, [r3, #20] 801a9d2: 2b00 cmp r3, #0 801a9d4: d106 bne.n 801a9e4 801a9d6: 4b7c ldr r3, [pc, #496] ; (801abc8 ) 801a9d8: f44f 724e mov.w r2, #824 ; 0x338 801a9dc: 4980 ldr r1, [pc, #512] ; (801abe0 ) 801a9de: 487c ldr r0, [pc, #496] ; (801abd0 ) 801a9e0: f006 ffd2 bl 8021988 recv_flags |= TF_RESET; 801a9e4: 4b7f ldr r3, [pc, #508] ; (801abe4 ) 801a9e6: 781b ldrb r3, [r3, #0] 801a9e8: f043 0308 orr.w r3, r3, #8 801a9ec: b2da uxtb r2, r3 801a9ee: 4b7d ldr r3, [pc, #500] ; (801abe4 ) 801a9f0: 701a strb r2, [r3, #0] tcp_clear_flags(pcb, TF_ACK_DELAY); 801a9f2: 687b ldr r3, [r7, #4] 801a9f4: 8b5b ldrh r3, [r3, #26] 801a9f6: f023 0301 bic.w r3, r3, #1 801a9fa: b29a uxth r2, r3 801a9fc: 687b ldr r3, [r7, #4] 801a9fe: 835a strh r2, [r3, #26] return ERR_RST; 801aa00: f06f 030d mvn.w r3, #13 801aa04: e37a b.n 801b0fc } else { LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", seqno, pcb->rcv_nxt)); LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", seqno, pcb->rcv_nxt)); return ERR_OK; 801aa06: 2300 movs r3, #0 801aa08: e378 b.n 801b0fc } } if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) { 801aa0a: 4b72 ldr r3, [pc, #456] ; (801abd4 ) 801aa0c: 781b ldrb r3, [r3, #0] 801aa0e: f003 0302 and.w r3, r3, #2 801aa12: 2b00 cmp r3, #0 801aa14: d010 beq.n 801aa38 801aa16: 687b ldr r3, [r7, #4] 801aa18: 7d1b ldrb r3, [r3, #20] 801aa1a: 2b02 cmp r3, #2 801aa1c: d00c beq.n 801aa38 801aa1e: 687b ldr r3, [r7, #4] 801aa20: 7d1b ldrb r3, [r3, #20] 801aa22: 2b03 cmp r3, #3 801aa24: d008 beq.n 801aa38 /* Cope with new connection attempt after remote end crashed */ tcp_ack_now(pcb); 801aa26: 687b ldr r3, [r7, #4] 801aa28: 8b5b ldrh r3, [r3, #26] 801aa2a: f043 0302 orr.w r3, r3, #2 801aa2e: b29a uxth r2, r3 801aa30: 687b ldr r3, [r7, #4] 801aa32: 835a strh r2, [r3, #26] return ERR_OK; 801aa34: 2300 movs r3, #0 801aa36: e361 b.n 801b0fc } if ((pcb->flags & TF_RXCLOSED) == 0) { 801aa38: 687b ldr r3, [r7, #4] 801aa3a: 8b5b ldrh r3, [r3, #26] 801aa3c: f003 0310 and.w r3, r3, #16 801aa40: 2b00 cmp r3, #0 801aa42: d103 bne.n 801aa4c /* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */ pcb->tmr = tcp_ticks; 801aa44: 4b68 ldr r3, [pc, #416] ; (801abe8 ) 801aa46: 681a ldr r2, [r3, #0] 801aa48: 687b ldr r3, [r7, #4] 801aa4a: 621a str r2, [r3, #32] } pcb->keep_cnt_sent = 0; 801aa4c: 687b ldr r3, [r7, #4] 801aa4e: 2200 movs r2, #0 801aa50: f883 209b strb.w r2, [r3, #155] ; 0x9b pcb->persist_probe = 0; 801aa54: 687b ldr r3, [r7, #4] 801aa56: 2200 movs r2, #0 801aa58: f883 209a strb.w r2, [r3, #154] ; 0x9a tcp_parseopt(pcb); 801aa5c: 6878 ldr r0, [r7, #4] 801aa5e: f001 fc2f bl 801c2c0 /* Do different things depending on the TCP state. */ switch (pcb->state) { 801aa62: 687b ldr r3, [r7, #4] 801aa64: 7d1b ldrb r3, [r3, #20] 801aa66: 3b02 subs r3, #2 801aa68: 2b07 cmp r3, #7 801aa6a: f200 8337 bhi.w 801b0dc 801aa6e: a201 add r2, pc, #4 ; (adr r2, 801aa74 ) 801aa70: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801aa74: 0801aa95 .word 0x0801aa95 801aa78: 0801acc5 .word 0x0801acc5 801aa7c: 0801ae3d .word 0x0801ae3d 801aa80: 0801ae67 .word 0x0801ae67 801aa84: 0801af8b .word 0x0801af8b 801aa88: 0801ae3d .word 0x0801ae3d 801aa8c: 0801b017 .word 0x0801b017 801aa90: 0801b0a7 .word 0x0801b0a7 case SYN_SENT: LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno))); /* received SYN ACK with expected sequence number? */ if ((flags & TCP_ACK) && (flags & TCP_SYN) 801aa94: 4b4f ldr r3, [pc, #316] ; (801abd4 ) 801aa96: 781b ldrb r3, [r3, #0] 801aa98: f003 0310 and.w r3, r3, #16 801aa9c: 2b00 cmp r3, #0 801aa9e: f000 80e4 beq.w 801ac6a 801aaa2: 4b4c ldr r3, [pc, #304] ; (801abd4 ) 801aaa4: 781b ldrb r3, [r3, #0] 801aaa6: f003 0302 and.w r3, r3, #2 801aaaa: 2b00 cmp r3, #0 801aaac: f000 80dd beq.w 801ac6a && (ackno == pcb->lastack + 1)) { 801aab0: 687b ldr r3, [r7, #4] 801aab2: 6c5b ldr r3, [r3, #68] ; 0x44 801aab4: 1c5a adds r2, r3, #1 801aab6: 4b48 ldr r3, [pc, #288] ; (801abd8 ) 801aab8: 681b ldr r3, [r3, #0] 801aaba: 429a cmp r2, r3 801aabc: f040 80d5 bne.w 801ac6a pcb->rcv_nxt = seqno + 1; 801aac0: 4b46 ldr r3, [pc, #280] ; (801abdc ) 801aac2: 681b ldr r3, [r3, #0] 801aac4: 1c5a adds r2, r3, #1 801aac6: 687b ldr r3, [r7, #4] 801aac8: 625a str r2, [r3, #36] ; 0x24 pcb->rcv_ann_right_edge = pcb->rcv_nxt; 801aaca: 687b ldr r3, [r7, #4] 801aacc: 6a5a ldr r2, [r3, #36] ; 0x24 801aace: 687b ldr r3, [r7, #4] 801aad0: 62da str r2, [r3, #44] ; 0x2c pcb->lastack = ackno; 801aad2: 4b41 ldr r3, [pc, #260] ; (801abd8 ) 801aad4: 681a ldr r2, [r3, #0] 801aad6: 687b ldr r3, [r7, #4] 801aad8: 645a str r2, [r3, #68] ; 0x44 pcb->snd_wnd = tcphdr->wnd; 801aada: 4b44 ldr r3, [pc, #272] ; (801abec ) 801aadc: 681b ldr r3, [r3, #0] 801aade: 89db ldrh r3, [r3, #14] 801aae0: b29a uxth r2, r3 801aae2: 687b ldr r3, [r7, #4] 801aae4: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 pcb->snd_wnd_max = pcb->snd_wnd; 801aae8: 687b ldr r3, [r7, #4] 801aaea: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 801aaee: 687b ldr r3, [r7, #4] 801aaf0: f8a3 2062 strh.w r2, [r3, #98] ; 0x62 pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ 801aaf4: 4b39 ldr r3, [pc, #228] ; (801abdc ) 801aaf6: 681b ldr r3, [r3, #0] 801aaf8: 1e5a subs r2, r3, #1 801aafa: 687b ldr r3, [r7, #4] 801aafc: 655a str r2, [r3, #84] ; 0x54 pcb->state = ESTABLISHED; 801aafe: 687b ldr r3, [r7, #4] 801ab00: 2204 movs r2, #4 801ab02: 751a strb r2, [r3, #20] #if TCP_CALCULATE_EFF_SEND_MSS pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip); 801ab04: 687b ldr r3, [r7, #4] 801ab06: 8e5c ldrh r4, [r3, #50] ; 0x32 801ab08: 687b ldr r3, [r7, #4] 801ab0a: 3304 adds r3, #4 801ab0c: 4618 mov r0, r3 801ab0e: f005 f9f1 bl 801fef4 801ab12: 4601 mov r1, r0 801ab14: 687b ldr r3, [r7, #4] 801ab16: 3304 adds r3, #4 801ab18: 461a mov r2, r3 801ab1a: 4620 mov r0, r4 801ab1c: f7ff f886 bl 8019c2c 801ab20: 4603 mov r3, r0 801ab22: 461a mov r2, r3 801ab24: 687b ldr r3, [r7, #4] 801ab26: 865a strh r2, [r3, #50] ; 0x32 #endif /* TCP_CALCULATE_EFF_SEND_MSS */ pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss); 801ab28: 687b ldr r3, [r7, #4] 801ab2a: 8e5b ldrh r3, [r3, #50] ; 0x32 801ab2c: 009a lsls r2, r3, #2 801ab2e: 687b ldr r3, [r7, #4] 801ab30: 8e5b ldrh r3, [r3, #50] ; 0x32 801ab32: 005b lsls r3, r3, #1 801ab34: f241 111c movw r1, #4380 ; 0x111c 801ab38: 428b cmp r3, r1 801ab3a: bf38 it cc 801ab3c: 460b movcc r3, r1 801ab3e: 429a cmp r2, r3 801ab40: d204 bcs.n 801ab4c 801ab42: 687b ldr r3, [r7, #4] 801ab44: 8e5b ldrh r3, [r3, #50] ; 0x32 801ab46: 009b lsls r3, r3, #2 801ab48: b29b uxth r3, r3 801ab4a: e00d b.n 801ab68 801ab4c: 687b ldr r3, [r7, #4] 801ab4e: 8e5b ldrh r3, [r3, #50] ; 0x32 801ab50: 005b lsls r3, r3, #1 801ab52: f241 121c movw r2, #4380 ; 0x111c 801ab56: 4293 cmp r3, r2 801ab58: d904 bls.n 801ab64 801ab5a: 687b ldr r3, [r7, #4] 801ab5c: 8e5b ldrh r3, [r3, #50] ; 0x32 801ab5e: 005b lsls r3, r3, #1 801ab60: b29b uxth r3, r3 801ab62: e001 b.n 801ab68 801ab64: f241 131c movw r3, #4380 ; 0x111c 801ab68: 687a ldr r2, [r7, #4] 801ab6a: f8a2 3048 strh.w r3, [r2, #72] ; 0x48 LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F " ssthresh %"TCPWNDSIZE_F"\n", pcb->cwnd, pcb->ssthresh)); LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0)); 801ab6e: 687b ldr r3, [r7, #4] 801ab70: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801ab74: 2b00 cmp r3, #0 801ab76: d106 bne.n 801ab86 801ab78: 4b13 ldr r3, [pc, #76] ; (801abc8 ) 801ab7a: f44f 725b mov.w r2, #876 ; 0x36c 801ab7e: 491c ldr r1, [pc, #112] ; (801abf0 ) 801ab80: 4813 ldr r0, [pc, #76] ; (801abd0 ) 801ab82: f006 ff01 bl 8021988 --pcb->snd_queuelen; 801ab86: 687b ldr r3, [r7, #4] 801ab88: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801ab8c: 3b01 subs r3, #1 801ab8e: b29a uxth r2, r3 801ab90: 687b ldr r3, [r7, #4] 801ab92: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen)); rseg = pcb->unacked; 801ab96: 687b ldr r3, [r7, #4] 801ab98: 6f1b ldr r3, [r3, #112] ; 0x70 801ab9a: 617b str r3, [r7, #20] if (rseg == NULL) { 801ab9c: 697b ldr r3, [r7, #20] 801ab9e: 2b00 cmp r3, #0 801aba0: d12a bne.n 801abf8 /* might happen if tcp_output fails in tcp_rexmit_rto() in which case the segment is on the unsent list */ rseg = pcb->unsent; 801aba2: 687b ldr r3, [r7, #4] 801aba4: 6edb ldr r3, [r3, #108] ; 0x6c 801aba6: 617b str r3, [r7, #20] LWIP_ASSERT("no segment to free", rseg != NULL); 801aba8: 697b ldr r3, [r7, #20] 801abaa: 2b00 cmp r3, #0 801abac: d106 bne.n 801abbc 801abae: 4b06 ldr r3, [pc, #24] ; (801abc8 ) 801abb0: f44f 725d mov.w r2, #884 ; 0x374 801abb4: 490f ldr r1, [pc, #60] ; (801abf4 ) 801abb6: 4806 ldr r0, [pc, #24] ; (801abd0 ) 801abb8: f006 fee6 bl 8021988 pcb->unsent = rseg->next; 801abbc: 697b ldr r3, [r7, #20] 801abbe: 681a ldr r2, [r3, #0] 801abc0: 687b ldr r3, [r7, #4] 801abc2: 66da str r2, [r3, #108] ; 0x6c 801abc4: e01c b.n 801ac00 801abc6: bf00 nop 801abc8: 08025338 .word 0x08025338 801abcc: 08025570 .word 0x08025570 801abd0: 08025384 .word 0x08025384 801abd4: 2401a4c8 .word 0x2401a4c8 801abd8: 2401a4c0 .word 0x2401a4c0 801abdc: 2401a4bc .word 0x2401a4bc 801abe0: 0802558c .word 0x0802558c 801abe4: 2401a4c9 .word 0x2401a4c9 801abe8: 2401a480 .word 0x2401a480 801abec: 2401a4ac .word 0x2401a4ac 801abf0: 080255ac .word 0x080255ac 801abf4: 080255c4 .word 0x080255c4 } else { pcb->unacked = rseg->next; 801abf8: 697b ldr r3, [r7, #20] 801abfa: 681a ldr r2, [r3, #0] 801abfc: 687b ldr r3, [r7, #4] 801abfe: 671a str r2, [r3, #112] ; 0x70 } tcp_seg_free(rseg); 801ac00: 6978 ldr r0, [r7, #20] 801ac02: f7fe fc4e bl 80194a2 /* If there's nothing left to acknowledge, stop the retransmit timer, otherwise reset it to start again */ if (pcb->unacked == NULL) { 801ac06: 687b ldr r3, [r7, #4] 801ac08: 6f1b ldr r3, [r3, #112] ; 0x70 801ac0a: 2b00 cmp r3, #0 801ac0c: d104 bne.n 801ac18 pcb->rtime = -1; 801ac0e: 687b ldr r3, [r7, #4] 801ac10: f64f 72ff movw r2, #65535 ; 0xffff 801ac14: 861a strh r2, [r3, #48] ; 0x30 801ac16: e006 b.n 801ac26 } else { pcb->rtime = 0; 801ac18: 687b ldr r3, [r7, #4] 801ac1a: 2200 movs r2, #0 801ac1c: 861a strh r2, [r3, #48] ; 0x30 pcb->nrtx = 0; 801ac1e: 687b ldr r3, [r7, #4] 801ac20: 2200 movs r2, #0 801ac22: f883 2042 strb.w r2, [r3, #66] ; 0x42 } /* Call the user specified function to call when successfully * connected. */ TCP_EVENT_CONNECTED(pcb, ERR_OK, err); 801ac26: 687b ldr r3, [r7, #4] 801ac28: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 801ac2c: 2b00 cmp r3, #0 801ac2e: d00a beq.n 801ac46 801ac30: 687b ldr r3, [r7, #4] 801ac32: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 801ac36: 687a ldr r2, [r7, #4] 801ac38: 6910 ldr r0, [r2, #16] 801ac3a: 2200 movs r2, #0 801ac3c: 6879 ldr r1, [r7, #4] 801ac3e: 4798 blx r3 801ac40: 4603 mov r3, r0 801ac42: 77bb strb r3, [r7, #30] 801ac44: e001 b.n 801ac4a 801ac46: 2300 movs r3, #0 801ac48: 77bb strb r3, [r7, #30] if (err == ERR_ABRT) { 801ac4a: f997 301e ldrsb.w r3, [r7, #30] 801ac4e: f113 0f0d cmn.w r3, #13 801ac52: d102 bne.n 801ac5a return ERR_ABRT; 801ac54: f06f 030c mvn.w r3, #12 801ac58: e250 b.n 801b0fc } tcp_ack_now(pcb); 801ac5a: 687b ldr r3, [r7, #4] 801ac5c: 8b5b ldrh r3, [r3, #26] 801ac5e: f043 0302 orr.w r3, r3, #2 801ac62: b29a uxth r2, r3 801ac64: 687b ldr r3, [r7, #4] 801ac66: 835a strh r2, [r3, #26] if (pcb->nrtx < TCP_SYNMAXRTX) { pcb->rtime = 0; tcp_rexmit_rto(pcb); } } break; 801ac68: e23a b.n 801b0e0 else if (flags & TCP_ACK) { 801ac6a: 4b98 ldr r3, [pc, #608] ; (801aecc ) 801ac6c: 781b ldrb r3, [r3, #0] 801ac6e: f003 0310 and.w r3, r3, #16 801ac72: 2b00 cmp r3, #0 801ac74: f000 8234 beq.w 801b0e0 tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801ac78: 4b95 ldr r3, [pc, #596] ; (801aed0 ) 801ac7a: 6819 ldr r1, [r3, #0] 801ac7c: 4b95 ldr r3, [pc, #596] ; (801aed4 ) 801ac7e: 881b ldrh r3, [r3, #0] 801ac80: 461a mov r2, r3 801ac82: 4b95 ldr r3, [pc, #596] ; (801aed8 ) 801ac84: 681b ldr r3, [r3, #0] 801ac86: 18d0 adds r0, r2, r3 ip_current_src_addr(), tcphdr->dest, tcphdr->src); 801ac88: 4b94 ldr r3, [pc, #592] ; (801aedc ) 801ac8a: 681b ldr r3, [r3, #0] tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801ac8c: 885b ldrh r3, [r3, #2] 801ac8e: b29b uxth r3, r3 ip_current_src_addr(), tcphdr->dest, tcphdr->src); 801ac90: 4a92 ldr r2, [pc, #584] ; (801aedc ) 801ac92: 6812 ldr r2, [r2, #0] tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801ac94: 8812 ldrh r2, [r2, #0] 801ac96: b292 uxth r2, r2 801ac98: 9202 str r2, [sp, #8] 801ac9a: 9301 str r3, [sp, #4] 801ac9c: 4b90 ldr r3, [pc, #576] ; (801aee0 ) 801ac9e: 9300 str r3, [sp, #0] 801aca0: 4b90 ldr r3, [pc, #576] ; (801aee4 ) 801aca2: 4602 mov r2, r0 801aca4: 6878 ldr r0, [r7, #4] 801aca6: f003 f949 bl 801df3c if (pcb->nrtx < TCP_SYNMAXRTX) { 801acaa: 687b ldr r3, [r7, #4] 801acac: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 801acb0: 2b05 cmp r3, #5 801acb2: f200 8215 bhi.w 801b0e0 pcb->rtime = 0; 801acb6: 687b ldr r3, [r7, #4] 801acb8: 2200 movs r2, #0 801acba: 861a strh r2, [r3, #48] ; 0x30 tcp_rexmit_rto(pcb); 801acbc: 6878 ldr r0, [r7, #4] 801acbe: f002 ff15 bl 801daec break; 801acc2: e20d b.n 801b0e0 case SYN_RCVD: if (flags & TCP_ACK) { 801acc4: 4b81 ldr r3, [pc, #516] ; (801aecc ) 801acc6: 781b ldrb r3, [r3, #0] 801acc8: f003 0310 and.w r3, r3, #16 801accc: 2b00 cmp r3, #0 801acce: f000 80a1 beq.w 801ae14 /* expected ACK number? */ if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { 801acd2: 4b7f ldr r3, [pc, #508] ; (801aed0 ) 801acd4: 681a ldr r2, [r3, #0] 801acd6: 687b ldr r3, [r7, #4] 801acd8: 6c5b ldr r3, [r3, #68] ; 0x44 801acda: 1ad3 subs r3, r2, r3 801acdc: 3b01 subs r3, #1 801acde: 2b00 cmp r3, #0 801ace0: db7e blt.n 801ade0 801ace2: 4b7b ldr r3, [pc, #492] ; (801aed0 ) 801ace4: 681a ldr r2, [r3, #0] 801ace6: 687b ldr r3, [r7, #4] 801ace8: 6d1b ldr r3, [r3, #80] ; 0x50 801acea: 1ad3 subs r3, r2, r3 801acec: 2b00 cmp r3, #0 801acee: dc77 bgt.n 801ade0 pcb->state = ESTABLISHED; 801acf0: 687b ldr r3, [r7, #4] 801acf2: 2204 movs r2, #4 801acf4: 751a strb r2, [r3, #20] LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); #if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG if (pcb->listener == NULL) { 801acf6: 687b ldr r3, [r7, #4] 801acf8: 6fdb ldr r3, [r3, #124] ; 0x7c 801acfa: 2b00 cmp r3, #0 801acfc: d102 bne.n 801ad04 /* listen pcb might be closed by now */ err = ERR_VAL; 801acfe: 23fa movs r3, #250 ; 0xfa 801ad00: 77bb strb r3, [r7, #30] 801ad02: e01d b.n 801ad40 } else #endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */ { #if LWIP_CALLBACK_API LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL); 801ad04: 687b ldr r3, [r7, #4] 801ad06: 6fdb ldr r3, [r3, #124] ; 0x7c 801ad08: 699b ldr r3, [r3, #24] 801ad0a: 2b00 cmp r3, #0 801ad0c: d106 bne.n 801ad1c 801ad0e: 4b76 ldr r3, [pc, #472] ; (801aee8 ) 801ad10: f44f 726a mov.w r2, #936 ; 0x3a8 801ad14: 4975 ldr r1, [pc, #468] ; (801aeec ) 801ad16: 4876 ldr r0, [pc, #472] ; (801aef0 ) 801ad18: f006 fe36 bl 8021988 #endif tcp_backlog_accepted(pcb); /* Call the accept function. */ TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err); 801ad1c: 687b ldr r3, [r7, #4] 801ad1e: 6fdb ldr r3, [r3, #124] ; 0x7c 801ad20: 699b ldr r3, [r3, #24] 801ad22: 2b00 cmp r3, #0 801ad24: d00a beq.n 801ad3c 801ad26: 687b ldr r3, [r7, #4] 801ad28: 6fdb ldr r3, [r3, #124] ; 0x7c 801ad2a: 699b ldr r3, [r3, #24] 801ad2c: 687a ldr r2, [r7, #4] 801ad2e: 6910 ldr r0, [r2, #16] 801ad30: 2200 movs r2, #0 801ad32: 6879 ldr r1, [r7, #4] 801ad34: 4798 blx r3 801ad36: 4603 mov r3, r0 801ad38: 77bb strb r3, [r7, #30] 801ad3a: e001 b.n 801ad40 801ad3c: 23f0 movs r3, #240 ; 0xf0 801ad3e: 77bb strb r3, [r7, #30] } if (err != ERR_OK) { 801ad40: f997 301e ldrsb.w r3, [r7, #30] 801ad44: 2b00 cmp r3, #0 801ad46: d00a beq.n 801ad5e /* If the accept function returns with an error, we abort * the connection. */ /* Already aborted? */ if (err != ERR_ABRT) { 801ad48: f997 301e ldrsb.w r3, [r7, #30] 801ad4c: f113 0f0d cmn.w r3, #13 801ad50: d002 beq.n 801ad58 tcp_abort(pcb); 801ad52: 6878 ldr r0, [r7, #4] 801ad54: f7fd fcc0 bl 80186d8 } return ERR_ABRT; 801ad58: f06f 030c mvn.w r3, #12 801ad5c: e1ce b.n 801b0fc } /* If there was any data contained within this ACK, * we'd better pass it on to the application as well. */ tcp_receive(pcb); 801ad5e: 6878 ldr r0, [r7, #4] 801ad60: f000 fae0 bl 801b324 /* Prevent ACK for SYN to generate a sent event */ if (recv_acked != 0) { 801ad64: 4b63 ldr r3, [pc, #396] ; (801aef4 ) 801ad66: 881b ldrh r3, [r3, #0] 801ad68: 2b00 cmp r3, #0 801ad6a: d005 beq.n 801ad78 recv_acked--; 801ad6c: 4b61 ldr r3, [pc, #388] ; (801aef4 ) 801ad6e: 881b ldrh r3, [r3, #0] 801ad70: 3b01 subs r3, #1 801ad72: b29a uxth r2, r3 801ad74: 4b5f ldr r3, [pc, #380] ; (801aef4 ) 801ad76: 801a strh r2, [r3, #0] } pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss); 801ad78: 687b ldr r3, [r7, #4] 801ad7a: 8e5b ldrh r3, [r3, #50] ; 0x32 801ad7c: 009a lsls r2, r3, #2 801ad7e: 687b ldr r3, [r7, #4] 801ad80: 8e5b ldrh r3, [r3, #50] ; 0x32 801ad82: 005b lsls r3, r3, #1 801ad84: f241 111c movw r1, #4380 ; 0x111c 801ad88: 428b cmp r3, r1 801ad8a: bf38 it cc 801ad8c: 460b movcc r3, r1 801ad8e: 429a cmp r2, r3 801ad90: d204 bcs.n 801ad9c 801ad92: 687b ldr r3, [r7, #4] 801ad94: 8e5b ldrh r3, [r3, #50] ; 0x32 801ad96: 009b lsls r3, r3, #2 801ad98: b29b uxth r3, r3 801ad9a: e00d b.n 801adb8 801ad9c: 687b ldr r3, [r7, #4] 801ad9e: 8e5b ldrh r3, [r3, #50] ; 0x32 801ada0: 005b lsls r3, r3, #1 801ada2: f241 121c movw r2, #4380 ; 0x111c 801ada6: 4293 cmp r3, r2 801ada8: d904 bls.n 801adb4 801adaa: 687b ldr r3, [r7, #4] 801adac: 8e5b ldrh r3, [r3, #50] ; 0x32 801adae: 005b lsls r3, r3, #1 801adb0: b29b uxth r3, r3 801adb2: e001 b.n 801adb8 801adb4: f241 131c movw r3, #4380 ; 0x111c 801adb8: 687a ldr r2, [r7, #4] 801adba: f8a2 3048 strh.w r3, [r2, #72] ; 0x48 LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F " ssthresh %"TCPWNDSIZE_F"\n", pcb->cwnd, pcb->ssthresh)); if (recv_flags & TF_GOT_FIN) { 801adbe: 4b4e ldr r3, [pc, #312] ; (801aef8 ) 801adc0: 781b ldrb r3, [r3, #0] 801adc2: f003 0320 and.w r3, r3, #32 801adc6: 2b00 cmp r3, #0 801adc8: d037 beq.n 801ae3a tcp_ack_now(pcb); 801adca: 687b ldr r3, [r7, #4] 801adcc: 8b5b ldrh r3, [r3, #26] 801adce: f043 0302 orr.w r3, r3, #2 801add2: b29a uxth r2, r3 801add4: 687b ldr r3, [r7, #4] 801add6: 835a strh r2, [r3, #26] pcb->state = CLOSE_WAIT; 801add8: 687b ldr r3, [r7, #4] 801adda: 2207 movs r2, #7 801addc: 751a strb r2, [r3, #20] if (recv_flags & TF_GOT_FIN) { 801adde: e02c b.n 801ae3a } } else { /* incorrect ACK number, send RST */ tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801ade0: 4b3b ldr r3, [pc, #236] ; (801aed0 ) 801ade2: 6819 ldr r1, [r3, #0] 801ade4: 4b3b ldr r3, [pc, #236] ; (801aed4 ) 801ade6: 881b ldrh r3, [r3, #0] 801ade8: 461a mov r2, r3 801adea: 4b3b ldr r3, [pc, #236] ; (801aed8 ) 801adec: 681b ldr r3, [r3, #0] 801adee: 18d0 adds r0, r2, r3 ip_current_src_addr(), tcphdr->dest, tcphdr->src); 801adf0: 4b3a ldr r3, [pc, #232] ; (801aedc ) 801adf2: 681b ldr r3, [r3, #0] tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801adf4: 885b ldrh r3, [r3, #2] 801adf6: b29b uxth r3, r3 ip_current_src_addr(), tcphdr->dest, tcphdr->src); 801adf8: 4a38 ldr r2, [pc, #224] ; (801aedc ) 801adfa: 6812 ldr r2, [r2, #0] tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), 801adfc: 8812 ldrh r2, [r2, #0] 801adfe: b292 uxth r2, r2 801ae00: 9202 str r2, [sp, #8] 801ae02: 9301 str r3, [sp, #4] 801ae04: 4b36 ldr r3, [pc, #216] ; (801aee0 ) 801ae06: 9300 str r3, [sp, #0] 801ae08: 4b36 ldr r3, [pc, #216] ; (801aee4 ) 801ae0a: 4602 mov r2, r0 801ae0c: 6878 ldr r0, [r7, #4] 801ae0e: f003 f895 bl 801df3c } } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { /* Looks like another copy of the SYN - retransmit our SYN-ACK */ tcp_rexmit(pcb); } break; 801ae12: e167 b.n 801b0e4 } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { 801ae14: 4b2d ldr r3, [pc, #180] ; (801aecc ) 801ae16: 781b ldrb r3, [r3, #0] 801ae18: f003 0302 and.w r3, r3, #2 801ae1c: 2b00 cmp r3, #0 801ae1e: f000 8161 beq.w 801b0e4 801ae22: 687b ldr r3, [r7, #4] 801ae24: 6a5b ldr r3, [r3, #36] ; 0x24 801ae26: 1e5a subs r2, r3, #1 801ae28: 4b2b ldr r3, [pc, #172] ; (801aed8 ) 801ae2a: 681b ldr r3, [r3, #0] 801ae2c: 429a cmp r2, r3 801ae2e: f040 8159 bne.w 801b0e4 tcp_rexmit(pcb); 801ae32: 6878 ldr r0, [r7, #4] 801ae34: f002 fe7c bl 801db30 break; 801ae38: e154 b.n 801b0e4 801ae3a: e153 b.n 801b0e4 case CLOSE_WAIT: /* FALLTHROUGH */ case ESTABLISHED: tcp_receive(pcb); 801ae3c: 6878 ldr r0, [r7, #4] 801ae3e: f000 fa71 bl 801b324 if (recv_flags & TF_GOT_FIN) { /* passive close */ 801ae42: 4b2d ldr r3, [pc, #180] ; (801aef8 ) 801ae44: 781b ldrb r3, [r3, #0] 801ae46: f003 0320 and.w r3, r3, #32 801ae4a: 2b00 cmp r3, #0 801ae4c: f000 814c beq.w 801b0e8 tcp_ack_now(pcb); 801ae50: 687b ldr r3, [r7, #4] 801ae52: 8b5b ldrh r3, [r3, #26] 801ae54: f043 0302 orr.w r3, r3, #2 801ae58: b29a uxth r2, r3 801ae5a: 687b ldr r3, [r7, #4] 801ae5c: 835a strh r2, [r3, #26] pcb->state = CLOSE_WAIT; 801ae5e: 687b ldr r3, [r7, #4] 801ae60: 2207 movs r2, #7 801ae62: 751a strb r2, [r3, #20] } break; 801ae64: e140 b.n 801b0e8 case FIN_WAIT_1: tcp_receive(pcb); 801ae66: 6878 ldr r0, [r7, #4] 801ae68: f000 fa5c bl 801b324 if (recv_flags & TF_GOT_FIN) { 801ae6c: 4b22 ldr r3, [pc, #136] ; (801aef8 ) 801ae6e: 781b ldrb r3, [r3, #0] 801ae70: f003 0320 and.w r3, r3, #32 801ae74: 2b00 cmp r3, #0 801ae76: d071 beq.n 801af5c if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && 801ae78: 4b14 ldr r3, [pc, #80] ; (801aecc ) 801ae7a: 781b ldrb r3, [r3, #0] 801ae7c: f003 0310 and.w r3, r3, #16 801ae80: 2b00 cmp r3, #0 801ae82: d060 beq.n 801af46 801ae84: 687b ldr r3, [r7, #4] 801ae86: 6d1a ldr r2, [r3, #80] ; 0x50 801ae88: 4b11 ldr r3, [pc, #68] ; (801aed0 ) 801ae8a: 681b ldr r3, [r3, #0] 801ae8c: 429a cmp r2, r3 801ae8e: d15a bne.n 801af46 pcb->unsent == NULL) { 801ae90: 687b ldr r3, [r7, #4] 801ae92: 6edb ldr r3, [r3, #108] ; 0x6c if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && 801ae94: 2b00 cmp r3, #0 801ae96: d156 bne.n 801af46 LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); tcp_ack_now(pcb); 801ae98: 687b ldr r3, [r7, #4] 801ae9a: 8b5b ldrh r3, [r3, #26] 801ae9c: f043 0302 orr.w r3, r3, #2 801aea0: b29a uxth r2, r3 801aea2: 687b ldr r3, [r7, #4] 801aea4: 835a strh r2, [r3, #26] tcp_pcb_purge(pcb); 801aea6: 6878 ldr r0, [r7, #4] 801aea8: f7fe fdb6 bl 8019a18 TCP_RMV_ACTIVE(pcb); 801aeac: 4b13 ldr r3, [pc, #76] ; (801aefc ) 801aeae: 681b ldr r3, [r3, #0] 801aeb0: 687a ldr r2, [r7, #4] 801aeb2: 429a cmp r2, r3 801aeb4: d105 bne.n 801aec2 801aeb6: 4b11 ldr r3, [pc, #68] ; (801aefc ) 801aeb8: 681b ldr r3, [r3, #0] 801aeba: 68db ldr r3, [r3, #12] 801aebc: 4a0f ldr r2, [pc, #60] ; (801aefc ) 801aebe: 6013 str r3, [r2, #0] 801aec0: e02e b.n 801af20 801aec2: 4b0e ldr r3, [pc, #56] ; (801aefc ) 801aec4: 681b ldr r3, [r3, #0] 801aec6: 613b str r3, [r7, #16] 801aec8: e027 b.n 801af1a 801aeca: bf00 nop 801aecc: 2401a4c8 .word 0x2401a4c8 801aed0: 2401a4c0 .word 0x2401a4c0 801aed4: 2401a4c6 .word 0x2401a4c6 801aed8: 2401a4bc .word 0x2401a4bc 801aedc: 2401a4ac .word 0x2401a4ac 801aee0: 24013990 .word 0x24013990 801aee4: 24013994 .word 0x24013994 801aee8: 08025338 .word 0x08025338 801aeec: 080255d8 .word 0x080255d8 801aef0: 08025384 .word 0x08025384 801aef4: 2401a4c4 .word 0x2401a4c4 801aef8: 2401a4c9 .word 0x2401a4c9 801aefc: 2401a48c .word 0x2401a48c 801af00: 693b ldr r3, [r7, #16] 801af02: 68db ldr r3, [r3, #12] 801af04: 687a ldr r2, [r7, #4] 801af06: 429a cmp r2, r3 801af08: d104 bne.n 801af14 801af0a: 687b ldr r3, [r7, #4] 801af0c: 68da ldr r2, [r3, #12] 801af0e: 693b ldr r3, [r7, #16] 801af10: 60da str r2, [r3, #12] 801af12: e005 b.n 801af20 801af14: 693b ldr r3, [r7, #16] 801af16: 68db ldr r3, [r3, #12] 801af18: 613b str r3, [r7, #16] 801af1a: 693b ldr r3, [r7, #16] 801af1c: 2b00 cmp r3, #0 801af1e: d1ef bne.n 801af00 801af20: 687b ldr r3, [r7, #4] 801af22: 2200 movs r2, #0 801af24: 60da str r2, [r3, #12] 801af26: 4b77 ldr r3, [pc, #476] ; (801b104 ) 801af28: 2201 movs r2, #1 801af2a: 701a strb r2, [r3, #0] pcb->state = TIME_WAIT; 801af2c: 687b ldr r3, [r7, #4] 801af2e: 220a movs r2, #10 801af30: 751a strb r2, [r3, #20] TCP_REG(&tcp_tw_pcbs, pcb); 801af32: 4b75 ldr r3, [pc, #468] ; (801b108 ) 801af34: 681a ldr r2, [r3, #0] 801af36: 687b ldr r3, [r7, #4] 801af38: 60da str r2, [r3, #12] 801af3a: 4a73 ldr r2, [pc, #460] ; (801b108 ) 801af3c: 687b ldr r3, [r7, #4] 801af3e: 6013 str r3, [r2, #0] 801af40: f003 f9be bl 801e2c0 } } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && pcb->unsent == NULL) { pcb->state = FIN_WAIT_2; } break; 801af44: e0d2 b.n 801b0ec tcp_ack_now(pcb); 801af46: 687b ldr r3, [r7, #4] 801af48: 8b5b ldrh r3, [r3, #26] 801af4a: f043 0302 orr.w r3, r3, #2 801af4e: b29a uxth r2, r3 801af50: 687b ldr r3, [r7, #4] 801af52: 835a strh r2, [r3, #26] pcb->state = CLOSING; 801af54: 687b ldr r3, [r7, #4] 801af56: 2208 movs r2, #8 801af58: 751a strb r2, [r3, #20] break; 801af5a: e0c7 b.n 801b0ec } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && 801af5c: 4b6b ldr r3, [pc, #428] ; (801b10c ) 801af5e: 781b ldrb r3, [r3, #0] 801af60: f003 0310 and.w r3, r3, #16 801af64: 2b00 cmp r3, #0 801af66: f000 80c1 beq.w 801b0ec 801af6a: 687b ldr r3, [r7, #4] 801af6c: 6d1a ldr r2, [r3, #80] ; 0x50 801af6e: 4b68 ldr r3, [pc, #416] ; (801b110 ) 801af70: 681b ldr r3, [r3, #0] 801af72: 429a cmp r2, r3 801af74: f040 80ba bne.w 801b0ec pcb->unsent == NULL) { 801af78: 687b ldr r3, [r7, #4] 801af7a: 6edb ldr r3, [r3, #108] ; 0x6c } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && 801af7c: 2b00 cmp r3, #0 801af7e: f040 80b5 bne.w 801b0ec pcb->state = FIN_WAIT_2; 801af82: 687b ldr r3, [r7, #4] 801af84: 2206 movs r2, #6 801af86: 751a strb r2, [r3, #20] break; 801af88: e0b0 b.n 801b0ec case FIN_WAIT_2: tcp_receive(pcb); 801af8a: 6878 ldr r0, [r7, #4] 801af8c: f000 f9ca bl 801b324 if (recv_flags & TF_GOT_FIN) { 801af90: 4b60 ldr r3, [pc, #384] ; (801b114 ) 801af92: 781b ldrb r3, [r3, #0] 801af94: f003 0320 and.w r3, r3, #32 801af98: 2b00 cmp r3, #0 801af9a: f000 80a9 beq.w 801b0f0 LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); tcp_ack_now(pcb); 801af9e: 687b ldr r3, [r7, #4] 801afa0: 8b5b ldrh r3, [r3, #26] 801afa2: f043 0302 orr.w r3, r3, #2 801afa6: b29a uxth r2, r3 801afa8: 687b ldr r3, [r7, #4] 801afaa: 835a strh r2, [r3, #26] tcp_pcb_purge(pcb); 801afac: 6878 ldr r0, [r7, #4] 801afae: f7fe fd33 bl 8019a18 TCP_RMV_ACTIVE(pcb); 801afb2: 4b59 ldr r3, [pc, #356] ; (801b118 ) 801afb4: 681b ldr r3, [r3, #0] 801afb6: 687a ldr r2, [r7, #4] 801afb8: 429a cmp r2, r3 801afba: d105 bne.n 801afc8 801afbc: 4b56 ldr r3, [pc, #344] ; (801b118 ) 801afbe: 681b ldr r3, [r3, #0] 801afc0: 68db ldr r3, [r3, #12] 801afc2: 4a55 ldr r2, [pc, #340] ; (801b118 ) 801afc4: 6013 str r3, [r2, #0] 801afc6: e013 b.n 801aff0 801afc8: 4b53 ldr r3, [pc, #332] ; (801b118 ) 801afca: 681b ldr r3, [r3, #0] 801afcc: 60fb str r3, [r7, #12] 801afce: e00c b.n 801afea 801afd0: 68fb ldr r3, [r7, #12] 801afd2: 68db ldr r3, [r3, #12] 801afd4: 687a ldr r2, [r7, #4] 801afd6: 429a cmp r2, r3 801afd8: d104 bne.n 801afe4 801afda: 687b ldr r3, [r7, #4] 801afdc: 68da ldr r2, [r3, #12] 801afde: 68fb ldr r3, [r7, #12] 801afe0: 60da str r2, [r3, #12] 801afe2: e005 b.n 801aff0 801afe4: 68fb ldr r3, [r7, #12] 801afe6: 68db ldr r3, [r3, #12] 801afe8: 60fb str r3, [r7, #12] 801afea: 68fb ldr r3, [r7, #12] 801afec: 2b00 cmp r3, #0 801afee: d1ef bne.n 801afd0 801aff0: 687b ldr r3, [r7, #4] 801aff2: 2200 movs r2, #0 801aff4: 60da str r2, [r3, #12] 801aff6: 4b43 ldr r3, [pc, #268] ; (801b104 ) 801aff8: 2201 movs r2, #1 801affa: 701a strb r2, [r3, #0] pcb->state = TIME_WAIT; 801affc: 687b ldr r3, [r7, #4] 801affe: 220a movs r2, #10 801b000: 751a strb r2, [r3, #20] TCP_REG(&tcp_tw_pcbs, pcb); 801b002: 4b41 ldr r3, [pc, #260] ; (801b108 ) 801b004: 681a ldr r2, [r3, #0] 801b006: 687b ldr r3, [r7, #4] 801b008: 60da str r2, [r3, #12] 801b00a: 4a3f ldr r2, [pc, #252] ; (801b108 ) 801b00c: 687b ldr r3, [r7, #4] 801b00e: 6013 str r3, [r2, #0] 801b010: f003 f956 bl 801e2c0 } break; 801b014: e06c b.n 801b0f0 case CLOSING: tcp_receive(pcb); 801b016: 6878 ldr r0, [r7, #4] 801b018: f000 f984 bl 801b324 if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) { 801b01c: 4b3b ldr r3, [pc, #236] ; (801b10c ) 801b01e: 781b ldrb r3, [r3, #0] 801b020: f003 0310 and.w r3, r3, #16 801b024: 2b00 cmp r3, #0 801b026: d065 beq.n 801b0f4 801b028: 687b ldr r3, [r7, #4] 801b02a: 6d1a ldr r2, [r3, #80] ; 0x50 801b02c: 4b38 ldr r3, [pc, #224] ; (801b110 ) 801b02e: 681b ldr r3, [r3, #0] 801b030: 429a cmp r2, r3 801b032: d15f bne.n 801b0f4 801b034: 687b ldr r3, [r7, #4] 801b036: 6edb ldr r3, [r3, #108] ; 0x6c 801b038: 2b00 cmp r3, #0 801b03a: d15b bne.n 801b0f4 LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); tcp_pcb_purge(pcb); 801b03c: 6878 ldr r0, [r7, #4] 801b03e: f7fe fceb bl 8019a18 TCP_RMV_ACTIVE(pcb); 801b042: 4b35 ldr r3, [pc, #212] ; (801b118 ) 801b044: 681b ldr r3, [r3, #0] 801b046: 687a ldr r2, [r7, #4] 801b048: 429a cmp r2, r3 801b04a: d105 bne.n 801b058 801b04c: 4b32 ldr r3, [pc, #200] ; (801b118 ) 801b04e: 681b ldr r3, [r3, #0] 801b050: 68db ldr r3, [r3, #12] 801b052: 4a31 ldr r2, [pc, #196] ; (801b118 ) 801b054: 6013 str r3, [r2, #0] 801b056: e013 b.n 801b080 801b058: 4b2f ldr r3, [pc, #188] ; (801b118 ) 801b05a: 681b ldr r3, [r3, #0] 801b05c: 61bb str r3, [r7, #24] 801b05e: e00c b.n 801b07a 801b060: 69bb ldr r3, [r7, #24] 801b062: 68db ldr r3, [r3, #12] 801b064: 687a ldr r2, [r7, #4] 801b066: 429a cmp r2, r3 801b068: d104 bne.n 801b074 801b06a: 687b ldr r3, [r7, #4] 801b06c: 68da ldr r2, [r3, #12] 801b06e: 69bb ldr r3, [r7, #24] 801b070: 60da str r2, [r3, #12] 801b072: e005 b.n 801b080 801b074: 69bb ldr r3, [r7, #24] 801b076: 68db ldr r3, [r3, #12] 801b078: 61bb str r3, [r7, #24] 801b07a: 69bb ldr r3, [r7, #24] 801b07c: 2b00 cmp r3, #0 801b07e: d1ef bne.n 801b060 801b080: 687b ldr r3, [r7, #4] 801b082: 2200 movs r2, #0 801b084: 60da str r2, [r3, #12] 801b086: 4b1f ldr r3, [pc, #124] ; (801b104 ) 801b088: 2201 movs r2, #1 801b08a: 701a strb r2, [r3, #0] pcb->state = TIME_WAIT; 801b08c: 687b ldr r3, [r7, #4] 801b08e: 220a movs r2, #10 801b090: 751a strb r2, [r3, #20] TCP_REG(&tcp_tw_pcbs, pcb); 801b092: 4b1d ldr r3, [pc, #116] ; (801b108 ) 801b094: 681a ldr r2, [r3, #0] 801b096: 687b ldr r3, [r7, #4] 801b098: 60da str r2, [r3, #12] 801b09a: 4a1b ldr r2, [pc, #108] ; (801b108 ) 801b09c: 687b ldr r3, [r7, #4] 801b09e: 6013 str r3, [r2, #0] 801b0a0: f003 f90e bl 801e2c0 } break; 801b0a4: e026 b.n 801b0f4 case LAST_ACK: tcp_receive(pcb); 801b0a6: 6878 ldr r0, [r7, #4] 801b0a8: f000 f93c bl 801b324 if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) { 801b0ac: 4b17 ldr r3, [pc, #92] ; (801b10c ) 801b0ae: 781b ldrb r3, [r3, #0] 801b0b0: f003 0310 and.w r3, r3, #16 801b0b4: 2b00 cmp r3, #0 801b0b6: d01f beq.n 801b0f8 801b0b8: 687b ldr r3, [r7, #4] 801b0ba: 6d1a ldr r2, [r3, #80] ; 0x50 801b0bc: 4b14 ldr r3, [pc, #80] ; (801b110 ) 801b0be: 681b ldr r3, [r3, #0] 801b0c0: 429a cmp r2, r3 801b0c2: d119 bne.n 801b0f8 801b0c4: 687b ldr r3, [r7, #4] 801b0c6: 6edb ldr r3, [r3, #108] ; 0x6c 801b0c8: 2b00 cmp r3, #0 801b0ca: d115 bne.n 801b0f8 LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */ recv_flags |= TF_CLOSED; 801b0cc: 4b11 ldr r3, [pc, #68] ; (801b114 ) 801b0ce: 781b ldrb r3, [r3, #0] 801b0d0: f043 0310 orr.w r3, r3, #16 801b0d4: b2da uxtb r2, r3 801b0d6: 4b0f ldr r3, [pc, #60] ; (801b114 ) 801b0d8: 701a strb r2, [r3, #0] } break; 801b0da: e00d b.n 801b0f8 default: break; 801b0dc: bf00 nop 801b0de: e00c b.n 801b0fa break; 801b0e0: bf00 nop 801b0e2: e00a b.n 801b0fa break; 801b0e4: bf00 nop 801b0e6: e008 b.n 801b0fa break; 801b0e8: bf00 nop 801b0ea: e006 b.n 801b0fa break; 801b0ec: bf00 nop 801b0ee: e004 b.n 801b0fa break; 801b0f0: bf00 nop 801b0f2: e002 b.n 801b0fa break; 801b0f4: bf00 nop 801b0f6: e000 b.n 801b0fa break; 801b0f8: bf00 nop } return ERR_OK; 801b0fa: 2300 movs r3, #0 } 801b0fc: 4618 mov r0, r3 801b0fe: 3724 adds r7, #36 ; 0x24 801b100: 46bd mov sp, r7 801b102: bd90 pop {r4, r7, pc} 801b104: 2401a494 .word 0x2401a494 801b108: 2401a490 .word 0x2401a490 801b10c: 2401a4c8 .word 0x2401a4c8 801b110: 2401a4c0 .word 0x2401a4c0 801b114: 2401a4c9 .word 0x2401a4c9 801b118: 2401a48c .word 0x2401a48c 0801b11c : * * Called from tcp_receive() */ static void tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next) { 801b11c: b590 push {r4, r7, lr} 801b11e: b085 sub sp, #20 801b120: af00 add r7, sp, #0 801b122: 6078 str r0, [r7, #4] 801b124: 6039 str r1, [r7, #0] struct tcp_seg *old_seg; LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL); 801b126: 687b ldr r3, [r7, #4] 801b128: 2b00 cmp r3, #0 801b12a: d106 bne.n 801b13a 801b12c: 4b3b ldr r3, [pc, #236] ; (801b21c ) 801b12e: f240 421f movw r2, #1055 ; 0x41f 801b132: 493b ldr r1, [pc, #236] ; (801b220 ) 801b134: 483b ldr r0, [pc, #236] ; (801b224 ) 801b136: f006 fc27 bl 8021988 if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { 801b13a: 687b ldr r3, [r7, #4] 801b13c: 691b ldr r3, [r3, #16] 801b13e: 899b ldrh r3, [r3, #12] 801b140: b29b uxth r3, r3 801b142: 4618 mov r0, r3 801b144: f7fa fefc bl 8015f40 801b148: 4603 mov r3, r0 801b14a: b2db uxtb r3, r3 801b14c: f003 0301 and.w r3, r3, #1 801b150: 2b00 cmp r3, #0 801b152: d028 beq.n 801b1a6 /* received segment overlaps all following segments */ tcp_segs_free(next); 801b154: 6838 ldr r0, [r7, #0] 801b156: f7fe f98f bl 8019478 next = NULL; 801b15a: 2300 movs r3, #0 801b15c: 603b str r3, [r7, #0] 801b15e: e056 b.n 801b20e oos queue may have segments with FIN flag */ while (next && TCP_SEQ_GEQ((seqno + cseg->len), (next->tcphdr->seqno + next->len))) { /* cseg with FIN already processed */ if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { 801b160: 683b ldr r3, [r7, #0] 801b162: 691b ldr r3, [r3, #16] 801b164: 899b ldrh r3, [r3, #12] 801b166: b29b uxth r3, r3 801b168: 4618 mov r0, r3 801b16a: f7fa fee9 bl 8015f40 801b16e: 4603 mov r3, r0 801b170: b2db uxtb r3, r3 801b172: f003 0301 and.w r3, r3, #1 801b176: 2b00 cmp r3, #0 801b178: d00d beq.n 801b196 TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN); 801b17a: 687b ldr r3, [r7, #4] 801b17c: 691b ldr r3, [r3, #16] 801b17e: 899b ldrh r3, [r3, #12] 801b180: b29c uxth r4, r3 801b182: 2001 movs r0, #1 801b184: f7fa fedc bl 8015f40 801b188: 4603 mov r3, r0 801b18a: 461a mov r2, r3 801b18c: 687b ldr r3, [r7, #4] 801b18e: 691b ldr r3, [r3, #16] 801b190: 4322 orrs r2, r4 801b192: b292 uxth r2, r2 801b194: 819a strh r2, [r3, #12] } old_seg = next; 801b196: 683b ldr r3, [r7, #0] 801b198: 60fb str r3, [r7, #12] next = next->next; 801b19a: 683b ldr r3, [r7, #0] 801b19c: 681b ldr r3, [r3, #0] 801b19e: 603b str r3, [r7, #0] tcp_seg_free(old_seg); 801b1a0: 68f8 ldr r0, [r7, #12] 801b1a2: f7fe f97e bl 80194a2 while (next && 801b1a6: 683b ldr r3, [r7, #0] 801b1a8: 2b00 cmp r3, #0 801b1aa: d00e beq.n 801b1ca TCP_SEQ_GEQ((seqno + cseg->len), 801b1ac: 687b ldr r3, [r7, #4] 801b1ae: 891b ldrh r3, [r3, #8] 801b1b0: 461a mov r2, r3 801b1b2: 4b1d ldr r3, [pc, #116] ; (801b228 ) 801b1b4: 681b ldr r3, [r3, #0] 801b1b6: 441a add r2, r3 801b1b8: 683b ldr r3, [r7, #0] 801b1ba: 691b ldr r3, [r3, #16] 801b1bc: 685b ldr r3, [r3, #4] 801b1be: 6839 ldr r1, [r7, #0] 801b1c0: 8909 ldrh r1, [r1, #8] 801b1c2: 440b add r3, r1 801b1c4: 1ad3 subs r3, r2, r3 while (next && 801b1c6: 2b00 cmp r3, #0 801b1c8: daca bge.n 801b160 } if (next && 801b1ca: 683b ldr r3, [r7, #0] 801b1cc: 2b00 cmp r3, #0 801b1ce: d01e beq.n 801b20e TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) { 801b1d0: 687b ldr r3, [r7, #4] 801b1d2: 891b ldrh r3, [r3, #8] 801b1d4: 461a mov r2, r3 801b1d6: 4b14 ldr r3, [pc, #80] ; (801b228 ) 801b1d8: 681b ldr r3, [r3, #0] 801b1da: 441a add r2, r3 801b1dc: 683b ldr r3, [r7, #0] 801b1de: 691b ldr r3, [r3, #16] 801b1e0: 685b ldr r3, [r3, #4] 801b1e2: 1ad3 subs r3, r2, r3 if (next && 801b1e4: 2b00 cmp r3, #0 801b1e6: dd12 ble.n 801b20e /* We need to trim the incoming segment. */ cseg->len = (u16_t)(next->tcphdr->seqno - seqno); 801b1e8: 683b ldr r3, [r7, #0] 801b1ea: 691b ldr r3, [r3, #16] 801b1ec: 685b ldr r3, [r3, #4] 801b1ee: b29a uxth r2, r3 801b1f0: 4b0d ldr r3, [pc, #52] ; (801b228 ) 801b1f2: 681b ldr r3, [r3, #0] 801b1f4: b29b uxth r3, r3 801b1f6: 1ad3 subs r3, r2, r3 801b1f8: b29a uxth r2, r3 801b1fa: 687b ldr r3, [r7, #4] 801b1fc: 811a strh r2, [r3, #8] pbuf_realloc(cseg->p, cseg->len); 801b1fe: 687b ldr r3, [r7, #4] 801b200: 685a ldr r2, [r3, #4] 801b202: 687b ldr r3, [r7, #4] 801b204: 891b ldrh r3, [r3, #8] 801b206: 4619 mov r1, r3 801b208: 4610 mov r0, r2 801b20a: f7fc faef bl 80177ec } } cseg->next = next; 801b20e: 687b ldr r3, [r7, #4] 801b210: 683a ldr r2, [r7, #0] 801b212: 601a str r2, [r3, #0] } 801b214: bf00 nop 801b216: 3714 adds r7, #20 801b218: 46bd mov sp, r7 801b21a: bd90 pop {r4, r7, pc} 801b21c: 08025338 .word 0x08025338 801b220: 080255f8 .word 0x080255f8 801b224: 08025384 .word 0x08025384 801b228: 2401a4bc .word 0x2401a4bc 0801b22c : /** Remove segments from a list if the incoming ACK acknowledges them */ static struct tcp_seg * tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name, struct tcp_seg *dbg_other_seg_list) { 801b22c: b5b0 push {r4, r5, r7, lr} 801b22e: b086 sub sp, #24 801b230: af00 add r7, sp, #0 801b232: 60f8 str r0, [r7, #12] 801b234: 60b9 str r1, [r7, #8] 801b236: 607a str r2, [r7, #4] 801b238: 603b str r3, [r7, #0] u16_t clen; LWIP_UNUSED_ARG(dbg_list_name); LWIP_UNUSED_ARG(dbg_other_seg_list); while (seg_list != NULL && 801b23a: e03e b.n 801b2ba LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n", lwip_ntohl(seg_list->tcphdr->seqno), lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list), dbg_list_name)); next = seg_list; 801b23c: 68bb ldr r3, [r7, #8] 801b23e: 617b str r3, [r7, #20] seg_list = seg_list->next; 801b240: 68bb ldr r3, [r7, #8] 801b242: 681b ldr r3, [r3, #0] 801b244: 60bb str r3, [r7, #8] clen = pbuf_clen(next->p); 801b246: 697b ldr r3, [r7, #20] 801b248: 685b ldr r3, [r3, #4] 801b24a: 4618 mov r0, r3 801b24c: f7fc fce2 bl 8017c14 801b250: 4603 mov r3, r0 801b252: 827b strh r3, [r7, #18] LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ", (tcpwnd_size_t)pcb->snd_queuelen)); LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen)); 801b254: 68fb ldr r3, [r7, #12] 801b256: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801b25a: 8a7a ldrh r2, [r7, #18] 801b25c: 429a cmp r2, r3 801b25e: d906 bls.n 801b26e 801b260: 4b2a ldr r3, [pc, #168] ; (801b30c ) 801b262: f240 4257 movw r2, #1111 ; 0x457 801b266: 492a ldr r1, [pc, #168] ; (801b310 ) 801b268: 482a ldr r0, [pc, #168] ; (801b314 ) 801b26a: f006 fb8d bl 8021988 pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen); 801b26e: 68fb ldr r3, [r7, #12] 801b270: f8b3 2066 ldrh.w r2, [r3, #102] ; 0x66 801b274: 8a7b ldrh r3, [r7, #18] 801b276: 1ad3 subs r3, r2, r3 801b278: b29a uxth r2, r3 801b27a: 68fb ldr r3, [r7, #12] 801b27c: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 recv_acked = (tcpwnd_size_t)(recv_acked + next->len); 801b280: 697b ldr r3, [r7, #20] 801b282: 891a ldrh r2, [r3, #8] 801b284: 4b24 ldr r3, [pc, #144] ; (801b318 ) 801b286: 881b ldrh r3, [r3, #0] 801b288: 4413 add r3, r2 801b28a: b29a uxth r2, r3 801b28c: 4b22 ldr r3, [pc, #136] ; (801b318 ) 801b28e: 801a strh r2, [r3, #0] tcp_seg_free(next); 801b290: 6978 ldr r0, [r7, #20] 801b292: f7fe f906 bl 80194a2 LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n", (tcpwnd_size_t)pcb->snd_queuelen, dbg_list_name)); if (pcb->snd_queuelen != 0) { 801b296: 68fb ldr r3, [r7, #12] 801b298: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801b29c: 2b00 cmp r3, #0 801b29e: d00c beq.n 801b2ba LWIP_ASSERT("tcp_receive: valid queue length", 801b2a0: 68bb ldr r3, [r7, #8] 801b2a2: 2b00 cmp r3, #0 801b2a4: d109 bne.n 801b2ba 801b2a6: 683b ldr r3, [r7, #0] 801b2a8: 2b00 cmp r3, #0 801b2aa: d106 bne.n 801b2ba 801b2ac: 4b17 ldr r3, [pc, #92] ; (801b30c ) 801b2ae: f240 4261 movw r2, #1121 ; 0x461 801b2b2: 491a ldr r1, [pc, #104] ; (801b31c ) 801b2b4: 4817 ldr r0, [pc, #92] ; (801b314 ) 801b2b6: f006 fb67 bl 8021988 while (seg_list != NULL && 801b2ba: 68bb ldr r3, [r7, #8] 801b2bc: 2b00 cmp r3, #0 801b2be: d020 beq.n 801b302 TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) + 801b2c0: 68bb ldr r3, [r7, #8] 801b2c2: 691b ldr r3, [r3, #16] 801b2c4: 685b ldr r3, [r3, #4] 801b2c6: 4618 mov r0, r3 801b2c8: f7fa fe4f bl 8015f6a 801b2cc: 4604 mov r4, r0 801b2ce: 68bb ldr r3, [r7, #8] 801b2d0: 891b ldrh r3, [r3, #8] 801b2d2: 461d mov r5, r3 801b2d4: 68bb ldr r3, [r7, #8] 801b2d6: 691b ldr r3, [r3, #16] 801b2d8: 899b ldrh r3, [r3, #12] 801b2da: b29b uxth r3, r3 801b2dc: 4618 mov r0, r3 801b2de: f7fa fe2f bl 8015f40 801b2e2: 4603 mov r3, r0 801b2e4: b2db uxtb r3, r3 801b2e6: f003 0303 and.w r3, r3, #3 801b2ea: 2b00 cmp r3, #0 801b2ec: d001 beq.n 801b2f2 801b2ee: 2301 movs r3, #1 801b2f0: e000 b.n 801b2f4 801b2f2: 2300 movs r3, #0 801b2f4: 442b add r3, r5 801b2f6: 18e2 adds r2, r4, r3 801b2f8: 4b09 ldr r3, [pc, #36] ; (801b320 ) 801b2fa: 681b ldr r3, [r3, #0] 801b2fc: 1ad3 subs r3, r2, r3 while (seg_list != NULL && 801b2fe: 2b00 cmp r3, #0 801b300: dd9c ble.n 801b23c seg_list != NULL || dbg_other_seg_list != NULL); } } return seg_list; 801b302: 68bb ldr r3, [r7, #8] } 801b304: 4618 mov r0, r3 801b306: 3718 adds r7, #24 801b308: 46bd mov sp, r7 801b30a: bdb0 pop {r4, r5, r7, pc} 801b30c: 08025338 .word 0x08025338 801b310: 08025620 .word 0x08025620 801b314: 08025384 .word 0x08025384 801b318: 2401a4c4 .word 0x2401a4c4 801b31c: 08025648 .word 0x08025648 801b320: 2401a4c0 .word 0x2401a4c0 0801b324 : * * Called from tcp_process(). */ static void tcp_receive(struct tcp_pcb *pcb) { 801b324: b5b0 push {r4, r5, r7, lr} 801b326: b094 sub sp, #80 ; 0x50 801b328: af00 add r7, sp, #0 801b32a: 6078 str r0, [r7, #4] s16_t m; u32_t right_wnd_edge; int found_dupack = 0; 801b32c: 2300 movs r3, #0 801b32e: 64bb str r3, [r7, #72] ; 0x48 LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL); 801b330: 687b ldr r3, [r7, #4] 801b332: 2b00 cmp r3, #0 801b334: d106 bne.n 801b344 801b336: 4b91 ldr r3, [pc, #580] ; (801b57c ) 801b338: f240 427b movw r2, #1147 ; 0x47b 801b33c: 4990 ldr r1, [pc, #576] ; (801b580 ) 801b33e: 4891 ldr r0, [pc, #580] ; (801b584 ) 801b340: f006 fb22 bl 8021988 LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED); 801b344: 687b ldr r3, [r7, #4] 801b346: 7d1b ldrb r3, [r3, #20] 801b348: 2b03 cmp r3, #3 801b34a: d806 bhi.n 801b35a 801b34c: 4b8b ldr r3, [pc, #556] ; (801b57c ) 801b34e: f240 427c movw r2, #1148 ; 0x47c 801b352: 498d ldr r1, [pc, #564] ; (801b588 ) 801b354: 488b ldr r0, [pc, #556] ; (801b584 ) 801b356: f006 fb17 bl 8021988 if (flags & TCP_ACK) { 801b35a: 4b8c ldr r3, [pc, #560] ; (801b58c ) 801b35c: 781b ldrb r3, [r3, #0] 801b35e: f003 0310 and.w r3, r3, #16 801b362: 2b00 cmp r3, #0 801b364: f000 8264 beq.w 801b830 right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2; 801b368: 687b ldr r3, [r7, #4] 801b36a: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 801b36e: 461a mov r2, r3 801b370: 687b ldr r3, [r7, #4] 801b372: 6d9b ldr r3, [r3, #88] ; 0x58 801b374: 4413 add r3, r2 801b376: 633b str r3, [r7, #48] ; 0x30 /* Update window. */ if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || 801b378: 687b ldr r3, [r7, #4] 801b37a: 6d5a ldr r2, [r3, #84] ; 0x54 801b37c: 4b84 ldr r3, [pc, #528] ; (801b590 ) 801b37e: 681b ldr r3, [r3, #0] 801b380: 1ad3 subs r3, r2, r3 801b382: 2b00 cmp r3, #0 801b384: db1b blt.n 801b3be (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || 801b386: 687b ldr r3, [r7, #4] 801b388: 6d5a ldr r2, [r3, #84] ; 0x54 801b38a: 4b81 ldr r3, [pc, #516] ; (801b590 ) 801b38c: 681b ldr r3, [r3, #0] if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || 801b38e: 429a cmp r2, r3 801b390: d106 bne.n 801b3a0 (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || 801b392: 687b ldr r3, [r7, #4] 801b394: 6d9a ldr r2, [r3, #88] ; 0x58 801b396: 4b7f ldr r3, [pc, #508] ; (801b594 ) 801b398: 681b ldr r3, [r3, #0] 801b39a: 1ad3 subs r3, r2, r3 801b39c: 2b00 cmp r3, #0 801b39e: db0e blt.n 801b3be (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) { 801b3a0: 687b ldr r3, [r7, #4] 801b3a2: 6d9a ldr r2, [r3, #88] ; 0x58 801b3a4: 4b7b ldr r3, [pc, #492] ; (801b594 ) 801b3a6: 681b ldr r3, [r3, #0] (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || 801b3a8: 429a cmp r2, r3 801b3aa: d125 bne.n 801b3f8 (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) { 801b3ac: 4b7a ldr r3, [pc, #488] ; (801b598 ) 801b3ae: 681b ldr r3, [r3, #0] 801b3b0: 89db ldrh r3, [r3, #14] 801b3b2: b29a uxth r2, r3 801b3b4: 687b ldr r3, [r7, #4] 801b3b6: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 801b3ba: 429a cmp r2, r3 801b3bc: d91c bls.n 801b3f8 pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd); 801b3be: 4b76 ldr r3, [pc, #472] ; (801b598 ) 801b3c0: 681b ldr r3, [r3, #0] 801b3c2: 89db ldrh r3, [r3, #14] 801b3c4: b29a uxth r2, r3 801b3c6: 687b ldr r3, [r7, #4] 801b3c8: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 /* keep track of the biggest window announced by the remote host to calculate the maximum segment size */ if (pcb->snd_wnd_max < pcb->snd_wnd) { 801b3cc: 687b ldr r3, [r7, #4] 801b3ce: f8b3 2062 ldrh.w r2, [r3, #98] ; 0x62 801b3d2: 687b ldr r3, [r7, #4] 801b3d4: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 801b3d8: 429a cmp r2, r3 801b3da: d205 bcs.n 801b3e8 pcb->snd_wnd_max = pcb->snd_wnd; 801b3dc: 687b ldr r3, [r7, #4] 801b3de: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 801b3e2: 687b ldr r3, [r7, #4] 801b3e4: f8a3 2062 strh.w r2, [r3, #98] ; 0x62 } pcb->snd_wl1 = seqno; 801b3e8: 4b69 ldr r3, [pc, #420] ; (801b590 ) 801b3ea: 681a ldr r2, [r3, #0] 801b3ec: 687b ldr r3, [r7, #4] 801b3ee: 655a str r2, [r3, #84] ; 0x54 pcb->snd_wl2 = ackno; 801b3f0: 4b68 ldr r3, [pc, #416] ; (801b594 ) 801b3f2: 681a ldr r2, [r3, #0] 801b3f4: 687b ldr r3, [r7, #4] 801b3f6: 659a str r2, [r3, #88] ; 0x58 * If it only passes 1, should reset dupack counter * */ /* Clause 1 */ if (TCP_SEQ_LEQ(ackno, pcb->lastack)) { 801b3f8: 4b66 ldr r3, [pc, #408] ; (801b594 ) 801b3fa: 681a ldr r2, [r3, #0] 801b3fc: 687b ldr r3, [r7, #4] 801b3fe: 6c5b ldr r3, [r3, #68] ; 0x44 801b400: 1ad3 subs r3, r2, r3 801b402: 2b00 cmp r3, #0 801b404: dc58 bgt.n 801b4b8 /* Clause 2 */ if (tcplen == 0) { 801b406: 4b65 ldr r3, [pc, #404] ; (801b59c ) 801b408: 881b ldrh r3, [r3, #0] 801b40a: 2b00 cmp r3, #0 801b40c: d14b bne.n 801b4a6 /* Clause 3 */ if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) { 801b40e: 687b ldr r3, [r7, #4] 801b410: 6d9b ldr r3, [r3, #88] ; 0x58 801b412: 687a ldr r2, [r7, #4] 801b414: f8b2 2060 ldrh.w r2, [r2, #96] ; 0x60 801b418: 4413 add r3, r2 801b41a: 6b3a ldr r2, [r7, #48] ; 0x30 801b41c: 429a cmp r2, r3 801b41e: d142 bne.n 801b4a6 /* Clause 4 */ if (pcb->rtime >= 0) { 801b420: 687b ldr r3, [r7, #4] 801b422: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 801b426: 2b00 cmp r3, #0 801b428: db3d blt.n 801b4a6 /* Clause 5 */ if (pcb->lastack == ackno) { 801b42a: 687b ldr r3, [r7, #4] 801b42c: 6c5a ldr r2, [r3, #68] ; 0x44 801b42e: 4b59 ldr r3, [pc, #356] ; (801b594 ) 801b430: 681b ldr r3, [r3, #0] 801b432: 429a cmp r2, r3 801b434: d137 bne.n 801b4a6 found_dupack = 1; 801b436: 2301 movs r3, #1 801b438: 64bb str r3, [r7, #72] ; 0x48 if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) { 801b43a: 687b ldr r3, [r7, #4] 801b43c: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 801b440: 2bff cmp r3, #255 ; 0xff 801b442: d007 beq.n 801b454 ++pcb->dupacks; 801b444: 687b ldr r3, [r7, #4] 801b446: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 801b44a: 3301 adds r3, #1 801b44c: b2da uxtb r2, r3 801b44e: 687b ldr r3, [r7, #4] 801b450: f883 2043 strb.w r2, [r3, #67] ; 0x43 } if (pcb->dupacks > 3) { 801b454: 687b ldr r3, [r7, #4] 801b456: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 801b45a: 2b03 cmp r3, #3 801b45c: d91b bls.n 801b496 /* Inflate the congestion window */ TCP_WND_INC(pcb->cwnd, pcb->mss); 801b45e: 687b ldr r3, [r7, #4] 801b460: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 801b464: 687b ldr r3, [r7, #4] 801b466: 8e5b ldrh r3, [r3, #50] ; 0x32 801b468: 4413 add r3, r2 801b46a: b29a uxth r2, r3 801b46c: 687b ldr r3, [r7, #4] 801b46e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 801b472: 429a cmp r2, r3 801b474: d30a bcc.n 801b48c 801b476: 687b ldr r3, [r7, #4] 801b478: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 801b47c: 687b ldr r3, [r7, #4] 801b47e: 8e5b ldrh r3, [r3, #50] ; 0x32 801b480: 4413 add r3, r2 801b482: b29a uxth r2, r3 801b484: 687b ldr r3, [r7, #4] 801b486: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 801b48a: e004 b.n 801b496 801b48c: 687b ldr r3, [r7, #4] 801b48e: f64f 72ff movw r2, #65535 ; 0xffff 801b492: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 } if (pcb->dupacks >= 3) { 801b496: 687b ldr r3, [r7, #4] 801b498: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 801b49c: 2b02 cmp r3, #2 801b49e: d902 bls.n 801b4a6 /* Do fast retransmit (checked via TF_INFR, not via dupacks count) */ tcp_rexmit_fast(pcb); 801b4a0: 6878 ldr r0, [r7, #4] 801b4a2: f002 fbb1 bl 801dc08 } } } /* If Clause (1) or more is true, but not a duplicate ack, reset * count of consecutive duplicate acks */ if (!found_dupack) { 801b4a6: 6cbb ldr r3, [r7, #72] ; 0x48 801b4a8: 2b00 cmp r3, #0 801b4aa: f040 8161 bne.w 801b770 pcb->dupacks = 0; 801b4ae: 687b ldr r3, [r7, #4] 801b4b0: 2200 movs r2, #0 801b4b2: f883 2043 strb.w r2, [r3, #67] ; 0x43 801b4b6: e15b b.n 801b770 } } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { 801b4b8: 4b36 ldr r3, [pc, #216] ; (801b594 ) 801b4ba: 681a ldr r2, [r3, #0] 801b4bc: 687b ldr r3, [r7, #4] 801b4be: 6c5b ldr r3, [r3, #68] ; 0x44 801b4c0: 1ad3 subs r3, r2, r3 801b4c2: 3b01 subs r3, #1 801b4c4: 2b00 cmp r3, #0 801b4c6: f2c0 814e blt.w 801b766 801b4ca: 4b32 ldr r3, [pc, #200] ; (801b594 ) 801b4cc: 681a ldr r2, [r3, #0] 801b4ce: 687b ldr r3, [r7, #4] 801b4d0: 6d1b ldr r3, [r3, #80] ; 0x50 801b4d2: 1ad3 subs r3, r2, r3 801b4d4: 2b00 cmp r3, #0 801b4d6: f300 8146 bgt.w 801b766 tcpwnd_size_t acked; /* Reset the "IN Fast Retransmit" flag, since we are no longer in fast retransmit. Also reset the congestion window to the slow start threshold. */ if (pcb->flags & TF_INFR) { 801b4da: 687b ldr r3, [r7, #4] 801b4dc: 8b5b ldrh r3, [r3, #26] 801b4de: f003 0304 and.w r3, r3, #4 801b4e2: 2b00 cmp r3, #0 801b4e4: d010 beq.n 801b508 tcp_clear_flags(pcb, TF_INFR); 801b4e6: 687b ldr r3, [r7, #4] 801b4e8: 8b5b ldrh r3, [r3, #26] 801b4ea: f023 0304 bic.w r3, r3, #4 801b4ee: b29a uxth r2, r3 801b4f0: 687b ldr r3, [r7, #4] 801b4f2: 835a strh r2, [r3, #26] pcb->cwnd = pcb->ssthresh; 801b4f4: 687b ldr r3, [r7, #4] 801b4f6: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a 801b4fa: 687b ldr r3, [r7, #4] 801b4fc: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 pcb->bytes_acked = 0; 801b500: 687b ldr r3, [r7, #4] 801b502: 2200 movs r2, #0 801b504: f8a3 206a strh.w r2, [r3, #106] ; 0x6a } /* Reset the number of retransmissions. */ pcb->nrtx = 0; 801b508: 687b ldr r3, [r7, #4] 801b50a: 2200 movs r2, #0 801b50c: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Reset the retransmission time-out. */ pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv); 801b510: 687b ldr r3, [r7, #4] 801b512: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c 801b516: 10db asrs r3, r3, #3 801b518: b21b sxth r3, r3 801b51a: b29a uxth r2, r3 801b51c: 687b ldr r3, [r7, #4] 801b51e: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e 801b522: b29b uxth r3, r3 801b524: 4413 add r3, r2 801b526: b29b uxth r3, r3 801b528: b21a sxth r2, r3 801b52a: 687b ldr r3, [r7, #4] 801b52c: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 /* Record how much data this ACK acks */ acked = (tcpwnd_size_t)(ackno - pcb->lastack); 801b530: 4b18 ldr r3, [pc, #96] ; (801b594 ) 801b532: 681b ldr r3, [r3, #0] 801b534: b29a uxth r2, r3 801b536: 687b ldr r3, [r7, #4] 801b538: 6c5b ldr r3, [r3, #68] ; 0x44 801b53a: b29b uxth r3, r3 801b53c: 1ad3 subs r3, r2, r3 801b53e: 85fb strh r3, [r7, #46] ; 0x2e /* Reset the fast retransmit variables. */ pcb->dupacks = 0; 801b540: 687b ldr r3, [r7, #4] 801b542: 2200 movs r2, #0 801b544: f883 2043 strb.w r2, [r3, #67] ; 0x43 pcb->lastack = ackno; 801b548: 4b12 ldr r3, [pc, #72] ; (801b594 ) 801b54a: 681a ldr r2, [r3, #0] 801b54c: 687b ldr r3, [r7, #4] 801b54e: 645a str r2, [r3, #68] ; 0x44 /* Update the congestion control variables (cwnd and ssthresh). */ if (pcb->state >= ESTABLISHED) { 801b550: 687b ldr r3, [r7, #4] 801b552: 7d1b ldrb r3, [r3, #20] 801b554: 2b03 cmp r3, #3 801b556: f240 8097 bls.w 801b688 if (pcb->cwnd < pcb->ssthresh) { 801b55a: 687b ldr r3, [r7, #4] 801b55c: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 801b560: 687b ldr r3, [r7, #4] 801b562: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a 801b566: 429a cmp r2, r3 801b568: d245 bcs.n 801b5f6 tcpwnd_size_t increase; /* limit to 1 SMSS segment during period following RTO */ u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2; 801b56a: 687b ldr r3, [r7, #4] 801b56c: 8b5b ldrh r3, [r3, #26] 801b56e: f403 6300 and.w r3, r3, #2048 ; 0x800 801b572: 2b00 cmp r3, #0 801b574: d014 beq.n 801b5a0 801b576: 2301 movs r3, #1 801b578: e013 b.n 801b5a2 801b57a: bf00 nop 801b57c: 08025338 .word 0x08025338 801b580: 08025668 .word 0x08025668 801b584: 08025384 .word 0x08025384 801b588: 08025684 .word 0x08025684 801b58c: 2401a4c8 .word 0x2401a4c8 801b590: 2401a4bc .word 0x2401a4bc 801b594: 2401a4c0 .word 0x2401a4c0 801b598: 2401a4ac .word 0x2401a4ac 801b59c: 2401a4c6 .word 0x2401a4c6 801b5a0: 2302 movs r3, #2 801b5a2: f887 302d strb.w r3, [r7, #45] ; 0x2d /* RFC 3465, section 2.2 Slow Start */ increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss)); 801b5a6: f897 302d ldrb.w r3, [r7, #45] ; 0x2d 801b5aa: b29a uxth r2, r3 801b5ac: 687b ldr r3, [r7, #4] 801b5ae: 8e5b ldrh r3, [r3, #50] ; 0x32 801b5b0: fb12 f303 smulbb r3, r2, r3 801b5b4: b29b uxth r3, r3 801b5b6: 8dfa ldrh r2, [r7, #46] ; 0x2e 801b5b8: 4293 cmp r3, r2 801b5ba: bf28 it cs 801b5bc: 4613 movcs r3, r2 801b5be: 857b strh r3, [r7, #42] ; 0x2a TCP_WND_INC(pcb->cwnd, increase); 801b5c0: 687b ldr r3, [r7, #4] 801b5c2: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 801b5c6: 8d7b ldrh r3, [r7, #42] ; 0x2a 801b5c8: 4413 add r3, r2 801b5ca: b29a uxth r2, r3 801b5cc: 687b ldr r3, [r7, #4] 801b5ce: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 801b5d2: 429a cmp r2, r3 801b5d4: d309 bcc.n 801b5ea 801b5d6: 687b ldr r3, [r7, #4] 801b5d8: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 801b5dc: 8d7b ldrh r3, [r7, #42] ; 0x2a 801b5de: 4413 add r3, r2 801b5e0: b29a uxth r2, r3 801b5e2: 687b ldr r3, [r7, #4] 801b5e4: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 801b5e8: e04e b.n 801b688 801b5ea: 687b ldr r3, [r7, #4] 801b5ec: f64f 72ff movw r2, #65535 ; 0xffff 801b5f0: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 801b5f4: e048 b.n 801b688 LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd)); } else { /* RFC 3465, section 2.1 Congestion Avoidance */ TCP_WND_INC(pcb->bytes_acked, acked); 801b5f6: 687b ldr r3, [r7, #4] 801b5f8: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a 801b5fc: 8dfb ldrh r3, [r7, #46] ; 0x2e 801b5fe: 4413 add r3, r2 801b600: b29a uxth r2, r3 801b602: 687b ldr r3, [r7, #4] 801b604: f8b3 306a ldrh.w r3, [r3, #106] ; 0x6a 801b608: 429a cmp r2, r3 801b60a: d309 bcc.n 801b620 801b60c: 687b ldr r3, [r7, #4] 801b60e: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a 801b612: 8dfb ldrh r3, [r7, #46] ; 0x2e 801b614: 4413 add r3, r2 801b616: b29a uxth r2, r3 801b618: 687b ldr r3, [r7, #4] 801b61a: f8a3 206a strh.w r2, [r3, #106] ; 0x6a 801b61e: e004 b.n 801b62a 801b620: 687b ldr r3, [r7, #4] 801b622: f64f 72ff movw r2, #65535 ; 0xffff 801b626: f8a3 206a strh.w r2, [r3, #106] ; 0x6a if (pcb->bytes_acked >= pcb->cwnd) { 801b62a: 687b ldr r3, [r7, #4] 801b62c: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a 801b630: 687b ldr r3, [r7, #4] 801b632: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 801b636: 429a cmp r2, r3 801b638: d326 bcc.n 801b688 pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd); 801b63a: 687b ldr r3, [r7, #4] 801b63c: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a 801b640: 687b ldr r3, [r7, #4] 801b642: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 801b646: 1ad3 subs r3, r2, r3 801b648: b29a uxth r2, r3 801b64a: 687b ldr r3, [r7, #4] 801b64c: f8a3 206a strh.w r2, [r3, #106] ; 0x6a TCP_WND_INC(pcb->cwnd, pcb->mss); 801b650: 687b ldr r3, [r7, #4] 801b652: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 801b656: 687b ldr r3, [r7, #4] 801b658: 8e5b ldrh r3, [r3, #50] ; 0x32 801b65a: 4413 add r3, r2 801b65c: b29a uxth r2, r3 801b65e: 687b ldr r3, [r7, #4] 801b660: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 801b664: 429a cmp r2, r3 801b666: d30a bcc.n 801b67e 801b668: 687b ldr r3, [r7, #4] 801b66a: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 801b66e: 687b ldr r3, [r7, #4] 801b670: 8e5b ldrh r3, [r3, #50] ; 0x32 801b672: 4413 add r3, r2 801b674: b29a uxth r2, r3 801b676: 687b ldr r3, [r7, #4] 801b678: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 801b67c: e004 b.n 801b688 801b67e: 687b ldr r3, [r7, #4] 801b680: f64f 72ff movw r2, #65535 ; 0xffff 801b684: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 pcb->unacked != NULL ? lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0)); /* Remove segment from the unacknowledged list if the incoming ACK acknowledges them. */ pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent); 801b688: 687b ldr r3, [r7, #4] 801b68a: 6f19 ldr r1, [r3, #112] ; 0x70 801b68c: 687b ldr r3, [r7, #4] 801b68e: 6edb ldr r3, [r3, #108] ; 0x6c 801b690: 4a98 ldr r2, [pc, #608] ; (801b8f4 ) 801b692: 6878 ldr r0, [r7, #4] 801b694: f7ff fdca bl 801b22c 801b698: 4602 mov r2, r0 801b69a: 687b ldr r3, [r7, #4] 801b69c: 671a str r2, [r3, #112] ; 0x70 on the list are acknowledged by the ACK. This may seem strange since an "unsent" segment shouldn't be acked. The rationale is that lwIP puts all outstanding segments on the ->unsent list after a retransmission, so these segments may in fact have been sent once. */ pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked); 801b69e: 687b ldr r3, [r7, #4] 801b6a0: 6ed9 ldr r1, [r3, #108] ; 0x6c 801b6a2: 687b ldr r3, [r7, #4] 801b6a4: 6f1b ldr r3, [r3, #112] ; 0x70 801b6a6: 4a94 ldr r2, [pc, #592] ; (801b8f8 ) 801b6a8: 6878 ldr r0, [r7, #4] 801b6aa: f7ff fdbf bl 801b22c 801b6ae: 4602 mov r2, r0 801b6b0: 687b ldr r3, [r7, #4] 801b6b2: 66da str r2, [r3, #108] ; 0x6c /* If there's nothing left to acknowledge, stop the retransmit timer, otherwise reset it to start again */ if (pcb->unacked == NULL) { 801b6b4: 687b ldr r3, [r7, #4] 801b6b6: 6f1b ldr r3, [r3, #112] ; 0x70 801b6b8: 2b00 cmp r3, #0 801b6ba: d104 bne.n 801b6c6 pcb->rtime = -1; 801b6bc: 687b ldr r3, [r7, #4] 801b6be: f64f 72ff movw r2, #65535 ; 0xffff 801b6c2: 861a strh r2, [r3, #48] ; 0x30 801b6c4: e002 b.n 801b6cc } else { pcb->rtime = 0; 801b6c6: 687b ldr r3, [r7, #4] 801b6c8: 2200 movs r2, #0 801b6ca: 861a strh r2, [r3, #48] ; 0x30 } pcb->polltmr = 0; 801b6cc: 687b ldr r3, [r7, #4] 801b6ce: 2200 movs r2, #0 801b6d0: 771a strb r2, [r3, #28] #if TCP_OVERSIZE if (pcb->unsent == NULL) { 801b6d2: 687b ldr r3, [r7, #4] 801b6d4: 6edb ldr r3, [r3, #108] ; 0x6c 801b6d6: 2b00 cmp r3, #0 801b6d8: d103 bne.n 801b6e2 pcb->unsent_oversize = 0; 801b6da: 687b ldr r3, [r7, #4] 801b6dc: 2200 movs r2, #0 801b6de: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 /* Inform neighbor reachability of forward progress. */ nd6_reachability_hint(ip6_current_src_addr()); } #endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/ pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked); 801b6e2: 687b ldr r3, [r7, #4] 801b6e4: f8b3 2064 ldrh.w r2, [r3, #100] ; 0x64 801b6e8: 4b84 ldr r3, [pc, #528] ; (801b8fc ) 801b6ea: 881b ldrh r3, [r3, #0] 801b6ec: 4413 add r3, r2 801b6ee: b29a uxth r2, r3 801b6f0: 687b ldr r3, [r7, #4] 801b6f2: f8a3 2064 strh.w r2, [r3, #100] ; 0x64 /* check if this ACK ends our retransmission of in-flight data */ if (pcb->flags & TF_RTO) { 801b6f6: 687b ldr r3, [r7, #4] 801b6f8: 8b5b ldrh r3, [r3, #26] 801b6fa: f403 6300 and.w r3, r3, #2048 ; 0x800 801b6fe: 2b00 cmp r3, #0 801b700: d035 beq.n 801b76e /* RTO is done if 1) both queues are empty or 2) unacked is empty and unsent head contains data not part of RTO or 3) unacked head contains data not part of RTO */ if (pcb->unacked == NULL) { 801b702: 687b ldr r3, [r7, #4] 801b704: 6f1b ldr r3, [r3, #112] ; 0x70 801b706: 2b00 cmp r3, #0 801b708: d118 bne.n 801b73c if ((pcb->unsent == NULL) || 801b70a: 687b ldr r3, [r7, #4] 801b70c: 6edb ldr r3, [r3, #108] ; 0x6c 801b70e: 2b00 cmp r3, #0 801b710: d00c beq.n 801b72c (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) { 801b712: 687b ldr r3, [r7, #4] 801b714: 6cdc ldr r4, [r3, #76] ; 0x4c 801b716: 687b ldr r3, [r7, #4] 801b718: 6edb ldr r3, [r3, #108] ; 0x6c 801b71a: 691b ldr r3, [r3, #16] 801b71c: 685b ldr r3, [r3, #4] 801b71e: 4618 mov r0, r3 801b720: f7fa fc23 bl 8015f6a 801b724: 4603 mov r3, r0 801b726: 1ae3 subs r3, r4, r3 if ((pcb->unsent == NULL) || 801b728: 2b00 cmp r3, #0 801b72a: dc20 bgt.n 801b76e tcp_clear_flags(pcb, TF_RTO); 801b72c: 687b ldr r3, [r7, #4] 801b72e: 8b5b ldrh r3, [r3, #26] 801b730: f423 6300 bic.w r3, r3, #2048 ; 0x800 801b734: b29a uxth r2, r3 801b736: 687b ldr r3, [r7, #4] 801b738: 835a strh r2, [r3, #26] } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { 801b73a: e018 b.n 801b76e } } else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) { 801b73c: 687b ldr r3, [r7, #4] 801b73e: 6cdc ldr r4, [r3, #76] ; 0x4c 801b740: 687b ldr r3, [r7, #4] 801b742: 6f1b ldr r3, [r3, #112] ; 0x70 801b744: 691b ldr r3, [r3, #16] 801b746: 685b ldr r3, [r3, #4] 801b748: 4618 mov r0, r3 801b74a: f7fa fc0e bl 8015f6a 801b74e: 4603 mov r3, r0 801b750: 1ae3 subs r3, r4, r3 801b752: 2b00 cmp r3, #0 801b754: dc0b bgt.n 801b76e tcp_clear_flags(pcb, TF_RTO); 801b756: 687b ldr r3, [r7, #4] 801b758: 8b5b ldrh r3, [r3, #26] 801b75a: f423 6300 bic.w r3, r3, #2048 ; 0x800 801b75e: b29a uxth r2, r3 801b760: 687b ldr r3, [r7, #4] 801b762: 835a strh r2, [r3, #26] } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { 801b764: e003 b.n 801b76e } } /* End of ACK for new data processing. */ } else { /* Out of sequence ACK, didn't really ack anything */ tcp_send_empty_ack(pcb); 801b766: 6878 ldr r0, [r7, #4] 801b768: f002 fc3a bl 801dfe0 801b76c: e000 b.n 801b770 } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { 801b76e: bf00 nop pcb->rttest, pcb->rtseq, ackno)); /* RTT estimation calculations. This is done by checking if the incoming segment acknowledges the segment we use to take a round-trip time measurement. */ if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { 801b770: 687b ldr r3, [r7, #4] 801b772: 6b5b ldr r3, [r3, #52] ; 0x34 801b774: 2b00 cmp r3, #0 801b776: d05b beq.n 801b830 801b778: 687b ldr r3, [r7, #4] 801b77a: 6b9a ldr r2, [r3, #56] ; 0x38 801b77c: 4b60 ldr r3, [pc, #384] ; (801b900 ) 801b77e: 681b ldr r3, [r3, #0] 801b780: 1ad3 subs r3, r2, r3 801b782: 2b00 cmp r3, #0 801b784: da54 bge.n 801b830 /* diff between this shouldn't exceed 32K since this are tcp timer ticks and a round-trip shouldn't be that long... */ m = (s16_t)(tcp_ticks - pcb->rttest); 801b786: 4b5f ldr r3, [pc, #380] ; (801b904 ) 801b788: 681b ldr r3, [r3, #0] 801b78a: b29a uxth r2, r3 801b78c: 687b ldr r3, [r7, #4] 801b78e: 6b5b ldr r3, [r3, #52] ; 0x34 801b790: b29b uxth r3, r3 801b792: 1ad3 subs r3, r2, r3 801b794: b29b uxth r3, r3 801b796: f8a7 304e strh.w r3, [r7, #78] ; 0x4e LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", m, (u16_t)(m * TCP_SLOW_INTERVAL))); /* This is taken directly from VJs original code in his paper */ m = (s16_t)(m - (pcb->sa >> 3)); 801b79a: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e 801b79e: 687b ldr r3, [r7, #4] 801b7a0: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c 801b7a4: 10db asrs r3, r3, #3 801b7a6: b21b sxth r3, r3 801b7a8: b29b uxth r3, r3 801b7aa: 1ad3 subs r3, r2, r3 801b7ac: b29b uxth r3, r3 801b7ae: f8a7 304e strh.w r3, [r7, #78] ; 0x4e pcb->sa = (s16_t)(pcb->sa + m); 801b7b2: 687b ldr r3, [r7, #4] 801b7b4: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c 801b7b8: b29a uxth r2, r3 801b7ba: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e 801b7be: 4413 add r3, r2 801b7c0: b29b uxth r3, r3 801b7c2: b21a sxth r2, r3 801b7c4: 687b ldr r3, [r7, #4] 801b7c6: 879a strh r2, [r3, #60] ; 0x3c if (m < 0) { 801b7c8: f9b7 304e ldrsh.w r3, [r7, #78] ; 0x4e 801b7cc: 2b00 cmp r3, #0 801b7ce: da05 bge.n 801b7dc m = (s16_t) - m; 801b7d0: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e 801b7d4: 425b negs r3, r3 801b7d6: b29b uxth r3, r3 801b7d8: f8a7 304e strh.w r3, [r7, #78] ; 0x4e } m = (s16_t)(m - (pcb->sv >> 2)); 801b7dc: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e 801b7e0: 687b ldr r3, [r7, #4] 801b7e2: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e 801b7e6: 109b asrs r3, r3, #2 801b7e8: b21b sxth r3, r3 801b7ea: b29b uxth r3, r3 801b7ec: 1ad3 subs r3, r2, r3 801b7ee: b29b uxth r3, r3 801b7f0: f8a7 304e strh.w r3, [r7, #78] ; 0x4e pcb->sv = (s16_t)(pcb->sv + m); 801b7f4: 687b ldr r3, [r7, #4] 801b7f6: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e 801b7fa: b29a uxth r2, r3 801b7fc: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e 801b800: 4413 add r3, r2 801b802: b29b uxth r3, r3 801b804: b21a sxth r2, r3 801b806: 687b ldr r3, [r7, #4] 801b808: 87da strh r2, [r3, #62] ; 0x3e pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv); 801b80a: 687b ldr r3, [r7, #4] 801b80c: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c 801b810: 10db asrs r3, r3, #3 801b812: b21b sxth r3, r3 801b814: b29a uxth r2, r3 801b816: 687b ldr r3, [r7, #4] 801b818: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e 801b81c: b29b uxth r3, r3 801b81e: 4413 add r3, r2 801b820: b29b uxth r3, r3 801b822: b21a sxth r2, r3 801b824: 687b ldr r3, [r7, #4] 801b826: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n", pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL))); pcb->rttest = 0; 801b82a: 687b ldr r3, [r7, #4] 801b82c: 2200 movs r2, #0 801b82e: 635a str r2, [r3, #52] ; 0x34 /* If the incoming segment contains data, we must process it further unless the pcb already received a FIN. (RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING, LAST-ACK and TIME-WAIT: "Ignore the segment text.") */ if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) { 801b830: 4b35 ldr r3, [pc, #212] ; (801b908 ) 801b832: 881b ldrh r3, [r3, #0] 801b834: 2b00 cmp r3, #0 801b836: f000 84e2 beq.w 801c1fe 801b83a: 687b ldr r3, [r7, #4] 801b83c: 7d1b ldrb r3, [r3, #20] 801b83e: 2b06 cmp r3, #6 801b840: f200 84dd bhi.w 801c1fe this if the sequence number of the incoming segment is less than rcv_nxt, and the sequence number plus the length of the segment is larger than rcv_nxt. */ /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) { if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) { 801b844: 687b ldr r3, [r7, #4] 801b846: 6a5a ldr r2, [r3, #36] ; 0x24 801b848: 4b30 ldr r3, [pc, #192] ; (801b90c ) 801b84a: 681b ldr r3, [r3, #0] 801b84c: 1ad3 subs r3, r2, r3 801b84e: 3b01 subs r3, #1 801b850: 2b00 cmp r3, #0 801b852: f2c0 808f blt.w 801b974 801b856: 687b ldr r3, [r7, #4] 801b858: 6a5a ldr r2, [r3, #36] ; 0x24 801b85a: 4b2b ldr r3, [pc, #172] ; (801b908 ) 801b85c: 881b ldrh r3, [r3, #0] 801b85e: 4619 mov r1, r3 801b860: 4b2a ldr r3, [pc, #168] ; (801b90c ) 801b862: 681b ldr r3, [r3, #0] 801b864: 440b add r3, r1 801b866: 1ad3 subs r3, r2, r3 801b868: 3301 adds r3, #1 801b86a: 2b00 cmp r3, #0 801b86c: f300 8082 bgt.w 801b974 After we are done with adjusting the pbuf pointers we must adjust the ->data pointer in the seg and the segment length.*/ struct pbuf *p = inseg.p; 801b870: 4b27 ldr r3, [pc, #156] ; (801b910 ) 801b872: 685b ldr r3, [r3, #4] 801b874: 647b str r3, [r7, #68] ; 0x44 u32_t off32 = pcb->rcv_nxt - seqno; 801b876: 687b ldr r3, [r7, #4] 801b878: 6a5a ldr r2, [r3, #36] ; 0x24 801b87a: 4b24 ldr r3, [pc, #144] ; (801b90c ) 801b87c: 681b ldr r3, [r3, #0] 801b87e: 1ad3 subs r3, r2, r3 801b880: 627b str r3, [r7, #36] ; 0x24 u16_t new_tot_len, off; LWIP_ASSERT("inseg.p != NULL", inseg.p); 801b882: 4b23 ldr r3, [pc, #140] ; (801b910 ) 801b884: 685b ldr r3, [r3, #4] 801b886: 2b00 cmp r3, #0 801b888: d106 bne.n 801b898 801b88a: 4b22 ldr r3, [pc, #136] ; (801b914 ) 801b88c: f240 5294 movw r2, #1428 ; 0x594 801b890: 4921 ldr r1, [pc, #132] ; (801b918 ) 801b892: 4822 ldr r0, [pc, #136] ; (801b91c ) 801b894: f006 f878 bl 8021988 LWIP_ASSERT("insane offset!", (off32 < 0xffff)); 801b898: 6a7b ldr r3, [r7, #36] ; 0x24 801b89a: f64f 72fe movw r2, #65534 ; 0xfffe 801b89e: 4293 cmp r3, r2 801b8a0: d906 bls.n 801b8b0 801b8a2: 4b1c ldr r3, [pc, #112] ; (801b914 ) 801b8a4: f240 5295 movw r2, #1429 ; 0x595 801b8a8: 491d ldr r1, [pc, #116] ; (801b920 ) 801b8aa: 481c ldr r0, [pc, #112] ; (801b91c ) 801b8ac: f006 f86c bl 8021988 off = (u16_t)off32; 801b8b0: 6a7b ldr r3, [r7, #36] ; 0x24 801b8b2: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off)); 801b8b6: 4b16 ldr r3, [pc, #88] ; (801b910 ) 801b8b8: 685b ldr r3, [r3, #4] 801b8ba: 891b ldrh r3, [r3, #8] 801b8bc: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 801b8c0: 429a cmp r2, r3 801b8c2: d906 bls.n 801b8d2 801b8c4: 4b13 ldr r3, [pc, #76] ; (801b914 ) 801b8c6: f240 5297 movw r2, #1431 ; 0x597 801b8ca: 4916 ldr r1, [pc, #88] ; (801b924 ) 801b8cc: 4813 ldr r0, [pc, #76] ; (801b91c ) 801b8ce: f006 f85b bl 8021988 inseg.len -= off; 801b8d2: 4b0f ldr r3, [pc, #60] ; (801b910 ) 801b8d4: 891a ldrh r2, [r3, #8] 801b8d6: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 801b8da: 1ad3 subs r3, r2, r3 801b8dc: b29a uxth r2, r3 801b8de: 4b0c ldr r3, [pc, #48] ; (801b910 ) 801b8e0: 811a strh r2, [r3, #8] new_tot_len = (u16_t)(inseg.p->tot_len - off); 801b8e2: 4b0b ldr r3, [pc, #44] ; (801b910 ) 801b8e4: 685b ldr r3, [r3, #4] 801b8e6: 891a ldrh r2, [r3, #8] 801b8e8: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 801b8ec: 1ad3 subs r3, r2, r3 801b8ee: 847b strh r3, [r7, #34] ; 0x22 while (p->len < off) { 801b8f0: e02a b.n 801b948 801b8f2: bf00 nop 801b8f4: 080256a0 .word 0x080256a0 801b8f8: 080256a8 .word 0x080256a8 801b8fc: 2401a4c4 .word 0x2401a4c4 801b900: 2401a4c0 .word 0x2401a4c0 801b904: 2401a480 .word 0x2401a480 801b908: 2401a4c6 .word 0x2401a4c6 801b90c: 2401a4bc .word 0x2401a4bc 801b910: 2401a498 .word 0x2401a498 801b914: 08025338 .word 0x08025338 801b918: 080256b0 .word 0x080256b0 801b91c: 08025384 .word 0x08025384 801b920: 080256c0 .word 0x080256c0 801b924: 080256d0 .word 0x080256d0 off -= p->len; 801b928: 6c7b ldr r3, [r7, #68] ; 0x44 801b92a: 895b ldrh r3, [r3, #10] 801b92c: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 801b930: 1ad3 subs r3, r2, r3 801b932: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 /* all pbufs up to and including this one have len==0, so tot_len is equal */ p->tot_len = new_tot_len; 801b936: 6c7b ldr r3, [r7, #68] ; 0x44 801b938: 8c7a ldrh r2, [r7, #34] ; 0x22 801b93a: 811a strh r2, [r3, #8] p->len = 0; 801b93c: 6c7b ldr r3, [r7, #68] ; 0x44 801b93e: 2200 movs r2, #0 801b940: 815a strh r2, [r3, #10] p = p->next; 801b942: 6c7b ldr r3, [r7, #68] ; 0x44 801b944: 681b ldr r3, [r3, #0] 801b946: 647b str r3, [r7, #68] ; 0x44 while (p->len < off) { 801b948: 6c7b ldr r3, [r7, #68] ; 0x44 801b94a: 895b ldrh r3, [r3, #10] 801b94c: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 801b950: 429a cmp r2, r3 801b952: d8e9 bhi.n 801b928 } /* cannot fail... */ pbuf_remove_header(p, off); 801b954: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 801b958: 4619 mov r1, r3 801b95a: 6c78 ldr r0, [r7, #68] ; 0x44 801b95c: f7fc f846 bl 80179ec inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; 801b960: 687b ldr r3, [r7, #4] 801b962: 6a5b ldr r3, [r3, #36] ; 0x24 801b964: 4a91 ldr r2, [pc, #580] ; (801bbac ) 801b966: 6013 str r3, [r2, #0] 801b968: 4b91 ldr r3, [pc, #580] ; (801bbb0 ) 801b96a: 691b ldr r3, [r3, #16] 801b96c: 4a8f ldr r2, [pc, #572] ; (801bbac ) 801b96e: 6812 ldr r2, [r2, #0] 801b970: 605a str r2, [r3, #4] if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) { 801b972: e00d b.n 801b990 } else { if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) { 801b974: 4b8d ldr r3, [pc, #564] ; (801bbac ) 801b976: 681a ldr r2, [r3, #0] 801b978: 687b ldr r3, [r7, #4] 801b97a: 6a5b ldr r3, [r3, #36] ; 0x24 801b97c: 1ad3 subs r3, r2, r3 801b97e: 2b00 cmp r3, #0 801b980: da06 bge.n 801b990 /* the whole segment is < rcv_nxt */ /* must be a duplicate of a packet that has already been correctly handled */ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); tcp_ack_now(pcb); 801b982: 687b ldr r3, [r7, #4] 801b984: 8b5b ldrh r3, [r3, #26] 801b986: f043 0302 orr.w r3, r3, #2 801b98a: b29a uxth r2, r3 801b98c: 687b ldr r3, [r7, #4] 801b98e: 835a strh r2, [r3, #26] } /* The sequence number must be within the window (above rcv_nxt and below rcv_nxt + rcv_wnd) in order to be further processed. */ if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, 801b990: 4b86 ldr r3, [pc, #536] ; (801bbac ) 801b992: 681a ldr r2, [r3, #0] 801b994: 687b ldr r3, [r7, #4] 801b996: 6a5b ldr r3, [r3, #36] ; 0x24 801b998: 1ad3 subs r3, r2, r3 801b99a: 2b00 cmp r3, #0 801b99c: f2c0 842a blt.w 801c1f4 801b9a0: 4b82 ldr r3, [pc, #520] ; (801bbac ) 801b9a2: 681a ldr r2, [r3, #0] 801b9a4: 687b ldr r3, [r7, #4] 801b9a6: 6a5b ldr r3, [r3, #36] ; 0x24 801b9a8: 6879 ldr r1, [r7, #4] 801b9aa: 8d09 ldrh r1, [r1, #40] ; 0x28 801b9ac: 440b add r3, r1 801b9ae: 1ad3 subs r3, r2, r3 801b9b0: 3301 adds r3, #1 801b9b2: 2b00 cmp r3, #0 801b9b4: f300 841e bgt.w 801c1f4 pcb->rcv_nxt + pcb->rcv_wnd - 1)) { if (pcb->rcv_nxt == seqno) { 801b9b8: 687b ldr r3, [r7, #4] 801b9ba: 6a5a ldr r2, [r3, #36] ; 0x24 801b9bc: 4b7b ldr r3, [pc, #492] ; (801bbac ) 801b9be: 681b ldr r3, [r3, #0] 801b9c0: 429a cmp r2, r3 801b9c2: f040 829a bne.w 801befa /* The incoming segment is the next in sequence. We check if we have to trim the end of the segment and update rcv_nxt and pass the data to the application. */ tcplen = TCP_TCPLEN(&inseg); 801b9c6: 4b7a ldr r3, [pc, #488] ; (801bbb0 ) 801b9c8: 891c ldrh r4, [r3, #8] 801b9ca: 4b79 ldr r3, [pc, #484] ; (801bbb0 ) 801b9cc: 691b ldr r3, [r3, #16] 801b9ce: 899b ldrh r3, [r3, #12] 801b9d0: b29b uxth r3, r3 801b9d2: 4618 mov r0, r3 801b9d4: f7fa fab4 bl 8015f40 801b9d8: 4603 mov r3, r0 801b9da: b2db uxtb r3, r3 801b9dc: f003 0303 and.w r3, r3, #3 801b9e0: 2b00 cmp r3, #0 801b9e2: d001 beq.n 801b9e8 801b9e4: 2301 movs r3, #1 801b9e6: e000 b.n 801b9ea 801b9e8: 2300 movs r3, #0 801b9ea: 4423 add r3, r4 801b9ec: b29a uxth r2, r3 801b9ee: 4b71 ldr r3, [pc, #452] ; (801bbb4 ) 801b9f0: 801a strh r2, [r3, #0] if (tcplen > pcb->rcv_wnd) { 801b9f2: 687b ldr r3, [r7, #4] 801b9f4: 8d1a ldrh r2, [r3, #40] ; 0x28 801b9f6: 4b6f ldr r3, [pc, #444] ; (801bbb4 ) 801b9f8: 881b ldrh r3, [r3, #0] 801b9fa: 429a cmp r2, r3 801b9fc: d275 bcs.n 801baea LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: other end overran receive window" "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { 801b9fe: 4b6c ldr r3, [pc, #432] ; (801bbb0 ) 801ba00: 691b ldr r3, [r3, #16] 801ba02: 899b ldrh r3, [r3, #12] 801ba04: b29b uxth r3, r3 801ba06: 4618 mov r0, r3 801ba08: f7fa fa9a bl 8015f40 801ba0c: 4603 mov r3, r0 801ba0e: b2db uxtb r3, r3 801ba10: f003 0301 and.w r3, r3, #1 801ba14: 2b00 cmp r3, #0 801ba16: d01f beq.n 801ba58 /* Must remove the FIN from the header as we're trimming * that byte of sequence-space from the packet */ TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN); 801ba18: 4b65 ldr r3, [pc, #404] ; (801bbb0 ) 801ba1a: 691b ldr r3, [r3, #16] 801ba1c: 899b ldrh r3, [r3, #12] 801ba1e: b29b uxth r3, r3 801ba20: b21b sxth r3, r3 801ba22: f423 537c bic.w r3, r3, #16128 ; 0x3f00 801ba26: b21c sxth r4, r3 801ba28: 4b61 ldr r3, [pc, #388] ; (801bbb0 ) 801ba2a: 691b ldr r3, [r3, #16] 801ba2c: 899b ldrh r3, [r3, #12] 801ba2e: b29b uxth r3, r3 801ba30: 4618 mov r0, r3 801ba32: f7fa fa85 bl 8015f40 801ba36: 4603 mov r3, r0 801ba38: b2db uxtb r3, r3 801ba3a: b29b uxth r3, r3 801ba3c: f003 033e and.w r3, r3, #62 ; 0x3e 801ba40: b29b uxth r3, r3 801ba42: 4618 mov r0, r3 801ba44: f7fa fa7c bl 8015f40 801ba48: 4603 mov r3, r0 801ba4a: b21b sxth r3, r3 801ba4c: 4323 orrs r3, r4 801ba4e: b21a sxth r2, r3 801ba50: 4b57 ldr r3, [pc, #348] ; (801bbb0 ) 801ba52: 691b ldr r3, [r3, #16] 801ba54: b292 uxth r2, r2 801ba56: 819a strh r2, [r3, #12] } /* Adjust length of segment to fit in the window. */ TCPWND_CHECK16(pcb->rcv_wnd); inseg.len = (u16_t)pcb->rcv_wnd; 801ba58: 687b ldr r3, [r7, #4] 801ba5a: 8d1a ldrh r2, [r3, #40] ; 0x28 801ba5c: 4b54 ldr r3, [pc, #336] ; (801bbb0 ) 801ba5e: 811a strh r2, [r3, #8] if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { 801ba60: 4b53 ldr r3, [pc, #332] ; (801bbb0 ) 801ba62: 691b ldr r3, [r3, #16] 801ba64: 899b ldrh r3, [r3, #12] 801ba66: b29b uxth r3, r3 801ba68: 4618 mov r0, r3 801ba6a: f7fa fa69 bl 8015f40 801ba6e: 4603 mov r3, r0 801ba70: b2db uxtb r3, r3 801ba72: f003 0302 and.w r3, r3, #2 801ba76: 2b00 cmp r3, #0 801ba78: d005 beq.n 801ba86 inseg.len -= 1; 801ba7a: 4b4d ldr r3, [pc, #308] ; (801bbb0 ) 801ba7c: 891b ldrh r3, [r3, #8] 801ba7e: 3b01 subs r3, #1 801ba80: b29a uxth r2, r3 801ba82: 4b4b ldr r3, [pc, #300] ; (801bbb0 ) 801ba84: 811a strh r2, [r3, #8] } pbuf_realloc(inseg.p, inseg.len); 801ba86: 4b4a ldr r3, [pc, #296] ; (801bbb0 ) 801ba88: 685b ldr r3, [r3, #4] 801ba8a: 4a49 ldr r2, [pc, #292] ; (801bbb0 ) 801ba8c: 8912 ldrh r2, [r2, #8] 801ba8e: 4611 mov r1, r2 801ba90: 4618 mov r0, r3 801ba92: f7fb feab bl 80177ec tcplen = TCP_TCPLEN(&inseg); 801ba96: 4b46 ldr r3, [pc, #280] ; (801bbb0 ) 801ba98: 891c ldrh r4, [r3, #8] 801ba9a: 4b45 ldr r3, [pc, #276] ; (801bbb0 ) 801ba9c: 691b ldr r3, [r3, #16] 801ba9e: 899b ldrh r3, [r3, #12] 801baa0: b29b uxth r3, r3 801baa2: 4618 mov r0, r3 801baa4: f7fa fa4c bl 8015f40 801baa8: 4603 mov r3, r0 801baaa: b2db uxtb r3, r3 801baac: f003 0303 and.w r3, r3, #3 801bab0: 2b00 cmp r3, #0 801bab2: d001 beq.n 801bab8 801bab4: 2301 movs r3, #1 801bab6: e000 b.n 801baba 801bab8: 2300 movs r3, #0 801baba: 4423 add r3, r4 801babc: b29a uxth r2, r3 801babe: 4b3d ldr r3, [pc, #244] ; (801bbb4 ) 801bac0: 801a strh r2, [r3, #0] LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", 801bac2: 4b3c ldr r3, [pc, #240] ; (801bbb4 ) 801bac4: 881b ldrh r3, [r3, #0] 801bac6: 461a mov r2, r3 801bac8: 4b38 ldr r3, [pc, #224] ; (801bbac ) 801baca: 681b ldr r3, [r3, #0] 801bacc: 441a add r2, r3 801bace: 687b ldr r3, [r7, #4] 801bad0: 6a5b ldr r3, [r3, #36] ; 0x24 801bad2: 6879 ldr r1, [r7, #4] 801bad4: 8d09 ldrh r1, [r1, #40] ; 0x28 801bad6: 440b add r3, r1 801bad8: 429a cmp r2, r3 801bada: d006 beq.n 801baea 801badc: 4b36 ldr r3, [pc, #216] ; (801bbb8 ) 801bade: f240 52cb movw r2, #1483 ; 0x5cb 801bae2: 4936 ldr r1, [pc, #216] ; (801bbbc ) 801bae4: 4836 ldr r0, [pc, #216] ; (801bbc0 ) 801bae6: f005 ff4f bl 8021988 } #if TCP_QUEUE_OOSEQ /* Received in-sequence data, adjust ooseq data if: - FIN has been received or - inseq overlaps with ooseq */ if (pcb->ooseq != NULL) { 801baea: 687b ldr r3, [r7, #4] 801baec: 6f5b ldr r3, [r3, #116] ; 0x74 801baee: 2b00 cmp r3, #0 801baf0: f000 80e7 beq.w 801bcc2 if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { 801baf4: 4b2e ldr r3, [pc, #184] ; (801bbb0 ) 801baf6: 691b ldr r3, [r3, #16] 801baf8: 899b ldrh r3, [r3, #12] 801bafa: b29b uxth r3, r3 801bafc: 4618 mov r0, r3 801bafe: f7fa fa1f bl 8015f40 801bb02: 4603 mov r3, r0 801bb04: b2db uxtb r3, r3 801bb06: f003 0301 and.w r3, r3, #1 801bb0a: 2b00 cmp r3, #0 801bb0c: d010 beq.n 801bb30 LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received in-order FIN, binning ooseq queue\n")); /* Received in-order FIN means anything that was received * out of order must now have been received in-order, so * bin the ooseq queue */ while (pcb->ooseq != NULL) { 801bb0e: e00a b.n 801bb26 struct tcp_seg *old_ooseq = pcb->ooseq; 801bb10: 687b ldr r3, [r7, #4] 801bb12: 6f5b ldr r3, [r3, #116] ; 0x74 801bb14: 60fb str r3, [r7, #12] pcb->ooseq = pcb->ooseq->next; 801bb16: 687b ldr r3, [r7, #4] 801bb18: 6f5b ldr r3, [r3, #116] ; 0x74 801bb1a: 681a ldr r2, [r3, #0] 801bb1c: 687b ldr r3, [r7, #4] 801bb1e: 675a str r2, [r3, #116] ; 0x74 tcp_seg_free(old_ooseq); 801bb20: 68f8 ldr r0, [r7, #12] 801bb22: f7fd fcbe bl 80194a2 while (pcb->ooseq != NULL) { 801bb26: 687b ldr r3, [r7, #4] 801bb28: 6f5b ldr r3, [r3, #116] ; 0x74 801bb2a: 2b00 cmp r3, #0 801bb2c: d1f0 bne.n 801bb10 801bb2e: e0c8 b.n 801bcc2 } } else { struct tcp_seg *next = pcb->ooseq; 801bb30: 687b ldr r3, [r7, #4] 801bb32: 6f5b ldr r3, [r3, #116] ; 0x74 801bb34: 63fb str r3, [r7, #60] ; 0x3c /* Remove all segments on ooseq that are covered by inseg already. * FIN is copied from ooseq to inseg if present. */ while (next && 801bb36: e052 b.n 801bbde TCP_SEQ_GEQ(seqno + tcplen, next->tcphdr->seqno + next->len)) { struct tcp_seg *tmp; /* inseg cannot have FIN here (already processed above) */ if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 && 801bb38: 6bfb ldr r3, [r7, #60] ; 0x3c 801bb3a: 691b ldr r3, [r3, #16] 801bb3c: 899b ldrh r3, [r3, #12] 801bb3e: b29b uxth r3, r3 801bb40: 4618 mov r0, r3 801bb42: f7fa f9fd bl 8015f40 801bb46: 4603 mov r3, r0 801bb48: b2db uxtb r3, r3 801bb4a: f003 0301 and.w r3, r3, #1 801bb4e: 2b00 cmp r3, #0 801bb50: d03d beq.n 801bbce (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) { 801bb52: 4b17 ldr r3, [pc, #92] ; (801bbb0 ) 801bb54: 691b ldr r3, [r3, #16] 801bb56: 899b ldrh r3, [r3, #12] 801bb58: b29b uxth r3, r3 801bb5a: 4618 mov r0, r3 801bb5c: f7fa f9f0 bl 8015f40 801bb60: 4603 mov r3, r0 801bb62: b2db uxtb r3, r3 801bb64: f003 0302 and.w r3, r3, #2 if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 && 801bb68: 2b00 cmp r3, #0 801bb6a: d130 bne.n 801bbce TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN); 801bb6c: 4b10 ldr r3, [pc, #64] ; (801bbb0 ) 801bb6e: 691b ldr r3, [r3, #16] 801bb70: 899b ldrh r3, [r3, #12] 801bb72: b29c uxth r4, r3 801bb74: 2001 movs r0, #1 801bb76: f7fa f9e3 bl 8015f40 801bb7a: 4603 mov r3, r0 801bb7c: 461a mov r2, r3 801bb7e: 4b0c ldr r3, [pc, #48] ; (801bbb0 ) 801bb80: 691b ldr r3, [r3, #16] 801bb82: 4322 orrs r2, r4 801bb84: b292 uxth r2, r2 801bb86: 819a strh r2, [r3, #12] tcplen = TCP_TCPLEN(&inseg); 801bb88: 4b09 ldr r3, [pc, #36] ; (801bbb0 ) 801bb8a: 891c ldrh r4, [r3, #8] 801bb8c: 4b08 ldr r3, [pc, #32] ; (801bbb0 ) 801bb8e: 691b ldr r3, [r3, #16] 801bb90: 899b ldrh r3, [r3, #12] 801bb92: b29b uxth r3, r3 801bb94: 4618 mov r0, r3 801bb96: f7fa f9d3 bl 8015f40 801bb9a: 4603 mov r3, r0 801bb9c: b2db uxtb r3, r3 801bb9e: f003 0303 and.w r3, r3, #3 801bba2: 2b00 cmp r3, #0 801bba4: d00e beq.n 801bbc4 801bba6: 2301 movs r3, #1 801bba8: e00d b.n 801bbc6 801bbaa: bf00 nop 801bbac: 2401a4bc .word 0x2401a4bc 801bbb0: 2401a498 .word 0x2401a498 801bbb4: 2401a4c6 .word 0x2401a4c6 801bbb8: 08025338 .word 0x08025338 801bbbc: 080256e0 .word 0x080256e0 801bbc0: 08025384 .word 0x08025384 801bbc4: 2300 movs r3, #0 801bbc6: 4423 add r3, r4 801bbc8: b29a uxth r2, r3 801bbca: 4b98 ldr r3, [pc, #608] ; (801be2c ) 801bbcc: 801a strh r2, [r3, #0] } tmp = next; 801bbce: 6bfb ldr r3, [r7, #60] ; 0x3c 801bbd0: 613b str r3, [r7, #16] next = next->next; 801bbd2: 6bfb ldr r3, [r7, #60] ; 0x3c 801bbd4: 681b ldr r3, [r3, #0] 801bbd6: 63fb str r3, [r7, #60] ; 0x3c tcp_seg_free(tmp); 801bbd8: 6938 ldr r0, [r7, #16] 801bbda: f7fd fc62 bl 80194a2 while (next && 801bbde: 6bfb ldr r3, [r7, #60] ; 0x3c 801bbe0: 2b00 cmp r3, #0 801bbe2: d00e beq.n 801bc02 TCP_SEQ_GEQ(seqno + tcplen, 801bbe4: 4b91 ldr r3, [pc, #580] ; (801be2c ) 801bbe6: 881b ldrh r3, [r3, #0] 801bbe8: 461a mov r2, r3 801bbea: 4b91 ldr r3, [pc, #580] ; (801be30 ) 801bbec: 681b ldr r3, [r3, #0] 801bbee: 441a add r2, r3 801bbf0: 6bfb ldr r3, [r7, #60] ; 0x3c 801bbf2: 691b ldr r3, [r3, #16] 801bbf4: 685b ldr r3, [r3, #4] 801bbf6: 6bf9 ldr r1, [r7, #60] ; 0x3c 801bbf8: 8909 ldrh r1, [r1, #8] 801bbfa: 440b add r3, r1 801bbfc: 1ad3 subs r3, r2, r3 while (next && 801bbfe: 2b00 cmp r3, #0 801bc00: da9a bge.n 801bb38 } /* Now trim right side of inseg if it overlaps with the first * segment on ooseq */ if (next && 801bc02: 6bfb ldr r3, [r7, #60] ; 0x3c 801bc04: 2b00 cmp r3, #0 801bc06: d059 beq.n 801bcbc TCP_SEQ_GT(seqno + tcplen, 801bc08: 4b88 ldr r3, [pc, #544] ; (801be2c ) 801bc0a: 881b ldrh r3, [r3, #0] 801bc0c: 461a mov r2, r3 801bc0e: 4b88 ldr r3, [pc, #544] ; (801be30 ) 801bc10: 681b ldr r3, [r3, #0] 801bc12: 441a add r2, r3 801bc14: 6bfb ldr r3, [r7, #60] ; 0x3c 801bc16: 691b ldr r3, [r3, #16] 801bc18: 685b ldr r3, [r3, #4] 801bc1a: 1ad3 subs r3, r2, r3 if (next && 801bc1c: 2b00 cmp r3, #0 801bc1e: dd4d ble.n 801bcbc next->tcphdr->seqno)) { /* inseg cannot have FIN here (already processed above) */ inseg.len = (u16_t)(next->tcphdr->seqno - seqno); 801bc20: 6bfb ldr r3, [r7, #60] ; 0x3c 801bc22: 691b ldr r3, [r3, #16] 801bc24: 685b ldr r3, [r3, #4] 801bc26: b29a uxth r2, r3 801bc28: 4b81 ldr r3, [pc, #516] ; (801be30 ) 801bc2a: 681b ldr r3, [r3, #0] 801bc2c: b29b uxth r3, r3 801bc2e: 1ad3 subs r3, r2, r3 801bc30: b29a uxth r2, r3 801bc32: 4b80 ldr r3, [pc, #512] ; (801be34 ) 801bc34: 811a strh r2, [r3, #8] if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { 801bc36: 4b7f ldr r3, [pc, #508] ; (801be34 ) 801bc38: 691b ldr r3, [r3, #16] 801bc3a: 899b ldrh r3, [r3, #12] 801bc3c: b29b uxth r3, r3 801bc3e: 4618 mov r0, r3 801bc40: f7fa f97e bl 8015f40 801bc44: 4603 mov r3, r0 801bc46: b2db uxtb r3, r3 801bc48: f003 0302 and.w r3, r3, #2 801bc4c: 2b00 cmp r3, #0 801bc4e: d005 beq.n 801bc5c inseg.len -= 1; 801bc50: 4b78 ldr r3, [pc, #480] ; (801be34 ) 801bc52: 891b ldrh r3, [r3, #8] 801bc54: 3b01 subs r3, #1 801bc56: b29a uxth r2, r3 801bc58: 4b76 ldr r3, [pc, #472] ; (801be34 ) 801bc5a: 811a strh r2, [r3, #8] } pbuf_realloc(inseg.p, inseg.len); 801bc5c: 4b75 ldr r3, [pc, #468] ; (801be34 ) 801bc5e: 685b ldr r3, [r3, #4] 801bc60: 4a74 ldr r2, [pc, #464] ; (801be34 ) 801bc62: 8912 ldrh r2, [r2, #8] 801bc64: 4611 mov r1, r2 801bc66: 4618 mov r0, r3 801bc68: f7fb fdc0 bl 80177ec tcplen = TCP_TCPLEN(&inseg); 801bc6c: 4b71 ldr r3, [pc, #452] ; (801be34 ) 801bc6e: 891c ldrh r4, [r3, #8] 801bc70: 4b70 ldr r3, [pc, #448] ; (801be34 ) 801bc72: 691b ldr r3, [r3, #16] 801bc74: 899b ldrh r3, [r3, #12] 801bc76: b29b uxth r3, r3 801bc78: 4618 mov r0, r3 801bc7a: f7fa f961 bl 8015f40 801bc7e: 4603 mov r3, r0 801bc80: b2db uxtb r3, r3 801bc82: f003 0303 and.w r3, r3, #3 801bc86: 2b00 cmp r3, #0 801bc88: d001 beq.n 801bc8e 801bc8a: 2301 movs r3, #1 801bc8c: e000 b.n 801bc90 801bc8e: 2300 movs r3, #0 801bc90: 4423 add r3, r4 801bc92: b29a uxth r2, r3 801bc94: 4b65 ldr r3, [pc, #404] ; (801be2c ) 801bc96: 801a strh r2, [r3, #0] LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n", 801bc98: 4b64 ldr r3, [pc, #400] ; (801be2c ) 801bc9a: 881b ldrh r3, [r3, #0] 801bc9c: 461a mov r2, r3 801bc9e: 4b64 ldr r3, [pc, #400] ; (801be30 ) 801bca0: 681b ldr r3, [r3, #0] 801bca2: 441a add r2, r3 801bca4: 6bfb ldr r3, [r7, #60] ; 0x3c 801bca6: 691b ldr r3, [r3, #16] 801bca8: 685b ldr r3, [r3, #4] 801bcaa: 429a cmp r2, r3 801bcac: d006 beq.n 801bcbc 801bcae: 4b62 ldr r3, [pc, #392] ; (801be38 ) 801bcb0: f240 52fc movw r2, #1532 ; 0x5fc 801bcb4: 4961 ldr r1, [pc, #388] ; (801be3c ) 801bcb6: 4862 ldr r0, [pc, #392] ; (801be40 ) 801bcb8: f005 fe66 bl 8021988 (seqno + tcplen) == next->tcphdr->seqno); } pcb->ooseq = next; 801bcbc: 687b ldr r3, [r7, #4] 801bcbe: 6bfa ldr r2, [r7, #60] ; 0x3c 801bcc0: 675a str r2, [r3, #116] ; 0x74 } } #endif /* TCP_QUEUE_OOSEQ */ pcb->rcv_nxt = seqno + tcplen; 801bcc2: 4b5a ldr r3, [pc, #360] ; (801be2c ) 801bcc4: 881b ldrh r3, [r3, #0] 801bcc6: 461a mov r2, r3 801bcc8: 4b59 ldr r3, [pc, #356] ; (801be30 ) 801bcca: 681b ldr r3, [r3, #0] 801bccc: 441a add r2, r3 801bcce: 687b ldr r3, [r7, #4] 801bcd0: 625a str r2, [r3, #36] ; 0x24 /* Update the receiver's (our) window. */ LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen); 801bcd2: 687b ldr r3, [r7, #4] 801bcd4: 8d1a ldrh r2, [r3, #40] ; 0x28 801bcd6: 4b55 ldr r3, [pc, #340] ; (801be2c ) 801bcd8: 881b ldrh r3, [r3, #0] 801bcda: 429a cmp r2, r3 801bcdc: d206 bcs.n 801bcec 801bcde: 4b56 ldr r3, [pc, #344] ; (801be38 ) 801bce0: f240 6207 movw r2, #1543 ; 0x607 801bce4: 4957 ldr r1, [pc, #348] ; (801be44 ) 801bce6: 4856 ldr r0, [pc, #344] ; (801be40 ) 801bce8: f005 fe4e bl 8021988 pcb->rcv_wnd -= tcplen; 801bcec: 687b ldr r3, [r7, #4] 801bcee: 8d1a ldrh r2, [r3, #40] ; 0x28 801bcf0: 4b4e ldr r3, [pc, #312] ; (801be2c ) 801bcf2: 881b ldrh r3, [r3, #0] 801bcf4: 1ad3 subs r3, r2, r3 801bcf6: b29a uxth r2, r3 801bcf8: 687b ldr r3, [r7, #4] 801bcfa: 851a strh r2, [r3, #40] ; 0x28 tcp_update_rcv_ann_wnd(pcb); 801bcfc: 6878 ldr r0, [r7, #4] 801bcfe: f7fc fd8f bl 8018820 chains its data on this pbuf as well. If the segment was a FIN, we set the TF_GOT_FIN flag that will be used to indicate to the application that the remote side has closed its end of the connection. */ if (inseg.p->tot_len > 0) { 801bd02: 4b4c ldr r3, [pc, #304] ; (801be34 ) 801bd04: 685b ldr r3, [r3, #4] 801bd06: 891b ldrh r3, [r3, #8] 801bd08: 2b00 cmp r3, #0 801bd0a: d006 beq.n 801bd1a recv_data = inseg.p; 801bd0c: 4b49 ldr r3, [pc, #292] ; (801be34 ) 801bd0e: 685b ldr r3, [r3, #4] 801bd10: 4a4d ldr r2, [pc, #308] ; (801be48 ) 801bd12: 6013 str r3, [r2, #0] /* Since this pbuf now is the responsibility of the application, we delete our reference to it so that we won't (mistakingly) deallocate it. */ inseg.p = NULL; 801bd14: 4b47 ldr r3, [pc, #284] ; (801be34 ) 801bd16: 2200 movs r2, #0 801bd18: 605a str r2, [r3, #4] } if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { 801bd1a: 4b46 ldr r3, [pc, #280] ; (801be34 ) 801bd1c: 691b ldr r3, [r3, #16] 801bd1e: 899b ldrh r3, [r3, #12] 801bd20: b29b uxth r3, r3 801bd22: 4618 mov r0, r3 801bd24: f7fa f90c bl 8015f40 801bd28: 4603 mov r3, r0 801bd2a: b2db uxtb r3, r3 801bd2c: f003 0301 and.w r3, r3, #1 801bd30: 2b00 cmp r3, #0 801bd32: f000 80b8 beq.w 801bea6 LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); recv_flags |= TF_GOT_FIN; 801bd36: 4b45 ldr r3, [pc, #276] ; (801be4c ) 801bd38: 781b ldrb r3, [r3, #0] 801bd3a: f043 0320 orr.w r3, r3, #32 801bd3e: b2da uxtb r2, r3 801bd40: 4b42 ldr r3, [pc, #264] ; (801be4c ) 801bd42: 701a strb r2, [r3, #0] } #if TCP_QUEUE_OOSEQ /* We now check if we have segments on the ->ooseq queue that are now in sequence. */ while (pcb->ooseq != NULL && 801bd44: e0af b.n 801bea6 pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { struct tcp_seg *cseg = pcb->ooseq; 801bd46: 687b ldr r3, [r7, #4] 801bd48: 6f5b ldr r3, [r3, #116] ; 0x74 801bd4a: 60bb str r3, [r7, #8] seqno = pcb->ooseq->tcphdr->seqno; 801bd4c: 687b ldr r3, [r7, #4] 801bd4e: 6f5b ldr r3, [r3, #116] ; 0x74 801bd50: 691b ldr r3, [r3, #16] 801bd52: 685b ldr r3, [r3, #4] 801bd54: 4a36 ldr r2, [pc, #216] ; (801be30 ) 801bd56: 6013 str r3, [r2, #0] pcb->rcv_nxt += TCP_TCPLEN(cseg); 801bd58: 68bb ldr r3, [r7, #8] 801bd5a: 891b ldrh r3, [r3, #8] 801bd5c: 461c mov r4, r3 801bd5e: 68bb ldr r3, [r7, #8] 801bd60: 691b ldr r3, [r3, #16] 801bd62: 899b ldrh r3, [r3, #12] 801bd64: b29b uxth r3, r3 801bd66: 4618 mov r0, r3 801bd68: f7fa f8ea bl 8015f40 801bd6c: 4603 mov r3, r0 801bd6e: b2db uxtb r3, r3 801bd70: f003 0303 and.w r3, r3, #3 801bd74: 2b00 cmp r3, #0 801bd76: d001 beq.n 801bd7c 801bd78: 2301 movs r3, #1 801bd7a: e000 b.n 801bd7e 801bd7c: 2300 movs r3, #0 801bd7e: 191a adds r2, r3, r4 801bd80: 687b ldr r3, [r7, #4] 801bd82: 6a5b ldr r3, [r3, #36] ; 0x24 801bd84: 441a add r2, r3 801bd86: 687b ldr r3, [r7, #4] 801bd88: 625a str r2, [r3, #36] ; 0x24 LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n", 801bd8a: 687b ldr r3, [r7, #4] 801bd8c: 8d1b ldrh r3, [r3, #40] ; 0x28 801bd8e: 461c mov r4, r3 801bd90: 68bb ldr r3, [r7, #8] 801bd92: 891b ldrh r3, [r3, #8] 801bd94: 461d mov r5, r3 801bd96: 68bb ldr r3, [r7, #8] 801bd98: 691b ldr r3, [r3, #16] 801bd9a: 899b ldrh r3, [r3, #12] 801bd9c: b29b uxth r3, r3 801bd9e: 4618 mov r0, r3 801bda0: f7fa f8ce bl 8015f40 801bda4: 4603 mov r3, r0 801bda6: b2db uxtb r3, r3 801bda8: f003 0303 and.w r3, r3, #3 801bdac: 2b00 cmp r3, #0 801bdae: d001 beq.n 801bdb4 801bdb0: 2301 movs r3, #1 801bdb2: e000 b.n 801bdb6 801bdb4: 2300 movs r3, #0 801bdb6: 442b add r3, r5 801bdb8: 429c cmp r4, r3 801bdba: d206 bcs.n 801bdca 801bdbc: 4b1e ldr r3, [pc, #120] ; (801be38 ) 801bdbe: f240 622b movw r2, #1579 ; 0x62b 801bdc2: 4923 ldr r1, [pc, #140] ; (801be50 ) 801bdc4: 481e ldr r0, [pc, #120] ; (801be40 ) 801bdc6: f005 fddf bl 8021988 pcb->rcv_wnd >= TCP_TCPLEN(cseg)); pcb->rcv_wnd -= TCP_TCPLEN(cseg); 801bdca: 68bb ldr r3, [r7, #8] 801bdcc: 891b ldrh r3, [r3, #8] 801bdce: 461c mov r4, r3 801bdd0: 68bb ldr r3, [r7, #8] 801bdd2: 691b ldr r3, [r3, #16] 801bdd4: 899b ldrh r3, [r3, #12] 801bdd6: b29b uxth r3, r3 801bdd8: 4618 mov r0, r3 801bdda: f7fa f8b1 bl 8015f40 801bdde: 4603 mov r3, r0 801bde0: b2db uxtb r3, r3 801bde2: f003 0303 and.w r3, r3, #3 801bde6: 2b00 cmp r3, #0 801bde8: d001 beq.n 801bdee 801bdea: 2301 movs r3, #1 801bdec: e000 b.n 801bdf0 801bdee: 2300 movs r3, #0 801bdf0: 1919 adds r1, r3, r4 801bdf2: 687b ldr r3, [r7, #4] 801bdf4: 8d1a ldrh r2, [r3, #40] ; 0x28 801bdf6: b28b uxth r3, r1 801bdf8: 1ad3 subs r3, r2, r3 801bdfa: b29a uxth r2, r3 801bdfc: 687b ldr r3, [r7, #4] 801bdfe: 851a strh r2, [r3, #40] ; 0x28 tcp_update_rcv_ann_wnd(pcb); 801be00: 6878 ldr r0, [r7, #4] 801be02: f7fc fd0d bl 8018820 if (cseg->p->tot_len > 0) { 801be06: 68bb ldr r3, [r7, #8] 801be08: 685b ldr r3, [r3, #4] 801be0a: 891b ldrh r3, [r3, #8] 801be0c: 2b00 cmp r3, #0 801be0e: d028 beq.n 801be62 /* Chain this pbuf onto the pbuf that we will pass to the application. */ /* With window scaling, this can overflow recv_data->tot_len, but that's not a problem since we explicitly fix that before passing recv_data to the application. */ if (recv_data) { 801be10: 4b0d ldr r3, [pc, #52] ; (801be48 ) 801be12: 681b ldr r3, [r3, #0] 801be14: 2b00 cmp r3, #0 801be16: d01d beq.n 801be54 pbuf_cat(recv_data, cseg->p); 801be18: 4b0b ldr r3, [pc, #44] ; (801be48 ) 801be1a: 681a ldr r2, [r3, #0] 801be1c: 68bb ldr r3, [r7, #8] 801be1e: 685b ldr r3, [r3, #4] 801be20: 4619 mov r1, r3 801be22: 4610 mov r0, r2 801be24: f7fb ff36 bl 8017c94 801be28: e018 b.n 801be5c 801be2a: bf00 nop 801be2c: 2401a4c6 .word 0x2401a4c6 801be30: 2401a4bc .word 0x2401a4bc 801be34: 2401a498 .word 0x2401a498 801be38: 08025338 .word 0x08025338 801be3c: 08025718 .word 0x08025718 801be40: 08025384 .word 0x08025384 801be44: 08025754 .word 0x08025754 801be48: 2401a4cc .word 0x2401a4cc 801be4c: 2401a4c9 .word 0x2401a4c9 801be50: 08025774 .word 0x08025774 } else { recv_data = cseg->p; 801be54: 68bb ldr r3, [r7, #8] 801be56: 685b ldr r3, [r3, #4] 801be58: 4a70 ldr r2, [pc, #448] ; (801c01c ) 801be5a: 6013 str r3, [r2, #0] } cseg->p = NULL; 801be5c: 68bb ldr r3, [r7, #8] 801be5e: 2200 movs r2, #0 801be60: 605a str r2, [r3, #4] } if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { 801be62: 68bb ldr r3, [r7, #8] 801be64: 691b ldr r3, [r3, #16] 801be66: 899b ldrh r3, [r3, #12] 801be68: b29b uxth r3, r3 801be6a: 4618 mov r0, r3 801be6c: f7fa f868 bl 8015f40 801be70: 4603 mov r3, r0 801be72: b2db uxtb r3, r3 801be74: f003 0301 and.w r3, r3, #1 801be78: 2b00 cmp r3, #0 801be7a: d00d beq.n 801be98 LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); recv_flags |= TF_GOT_FIN; 801be7c: 4b68 ldr r3, [pc, #416] ; (801c020 ) 801be7e: 781b ldrb r3, [r3, #0] 801be80: f043 0320 orr.w r3, r3, #32 801be84: b2da uxtb r2, r3 801be86: 4b66 ldr r3, [pc, #408] ; (801c020 ) 801be88: 701a strb r2, [r3, #0] if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */ 801be8a: 687b ldr r3, [r7, #4] 801be8c: 7d1b ldrb r3, [r3, #20] 801be8e: 2b04 cmp r3, #4 801be90: d102 bne.n 801be98 pcb->state = CLOSE_WAIT; 801be92: 687b ldr r3, [r7, #4] 801be94: 2207 movs r2, #7 801be96: 751a strb r2, [r3, #20] } } pcb->ooseq = cseg->next; 801be98: 68bb ldr r3, [r7, #8] 801be9a: 681a ldr r2, [r3, #0] 801be9c: 687b ldr r3, [r7, #4] 801be9e: 675a str r2, [r3, #116] ; 0x74 tcp_seg_free(cseg); 801bea0: 68b8 ldr r0, [r7, #8] 801bea2: f7fd fafe bl 80194a2 while (pcb->ooseq != NULL && 801bea6: 687b ldr r3, [r7, #4] 801bea8: 6f5b ldr r3, [r3, #116] ; 0x74 801beaa: 2b00 cmp r3, #0 801beac: d008 beq.n 801bec0 pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { 801beae: 687b ldr r3, [r7, #4] 801beb0: 6f5b ldr r3, [r3, #116] ; 0x74 801beb2: 691b ldr r3, [r3, #16] 801beb4: 685a ldr r2, [r3, #4] 801beb6: 687b ldr r3, [r7, #4] 801beb8: 6a5b ldr r3, [r3, #36] ; 0x24 while (pcb->ooseq != NULL && 801beba: 429a cmp r2, r3 801bebc: f43f af43 beq.w 801bd46 #endif /* LWIP_TCP_SACK_OUT */ #endif /* TCP_QUEUE_OOSEQ */ /* Acknowledge the segment(s). */ tcp_ack(pcb); 801bec0: 687b ldr r3, [r7, #4] 801bec2: 8b5b ldrh r3, [r3, #26] 801bec4: f003 0301 and.w r3, r3, #1 801bec8: 2b00 cmp r3, #0 801beca: d00e beq.n 801beea 801becc: 687b ldr r3, [r7, #4] 801bece: 8b5b ldrh r3, [r3, #26] 801bed0: f023 0301 bic.w r3, r3, #1 801bed4: b29a uxth r2, r3 801bed6: 687b ldr r3, [r7, #4] 801bed8: 835a strh r2, [r3, #26] 801beda: 687b ldr r3, [r7, #4] 801bedc: 8b5b ldrh r3, [r3, #26] 801bede: f043 0302 orr.w r3, r3, #2 801bee2: b29a uxth r2, r3 801bee4: 687b ldr r3, [r7, #4] 801bee6: 835a strh r2, [r3, #26] if (pcb->rcv_nxt == seqno) { 801bee8: e188 b.n 801c1fc tcp_ack(pcb); 801beea: 687b ldr r3, [r7, #4] 801beec: 8b5b ldrh r3, [r3, #26] 801beee: f043 0301 orr.w r3, r3, #1 801bef2: b29a uxth r2, r3 801bef4: 687b ldr r3, [r7, #4] 801bef6: 835a strh r2, [r3, #26] if (pcb->rcv_nxt == seqno) { 801bef8: e180 b.n 801c1fc } else { /* We get here if the incoming segment is out-of-sequence. */ #if TCP_QUEUE_OOSEQ /* We queue the segment on the ->ooseq queue. */ if (pcb->ooseq == NULL) { 801befa: 687b ldr r3, [r7, #4] 801befc: 6f5b ldr r3, [r3, #116] ; 0x74 801befe: 2b00 cmp r3, #0 801bf00: d106 bne.n 801bf10 pcb->ooseq = tcp_seg_copy(&inseg); 801bf02: 4848 ldr r0, [pc, #288] ; (801c024 ) 801bf04: f7fd fae6 bl 80194d4 801bf08: 4602 mov r2, r0 801bf0a: 687b ldr r3, [r7, #4] 801bf0c: 675a str r2, [r3, #116] ; 0x74 801bf0e: e16d b.n 801c1ec #if LWIP_TCP_SACK_OUT /* This is the left edge of the lowest possible SACK range. It may start before the newly received segment (possibly adjusted below). */ u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno; #endif /* LWIP_TCP_SACK_OUT */ struct tcp_seg *next, *prev = NULL; 801bf10: 2300 movs r3, #0 801bf12: 637b str r3, [r7, #52] ; 0x34 for (next = pcb->ooseq; next != NULL; next = next->next) { 801bf14: 687b ldr r3, [r7, #4] 801bf16: 6f5b ldr r3, [r3, #116] ; 0x74 801bf18: 63bb str r3, [r7, #56] ; 0x38 801bf1a: e157 b.n 801c1cc if (seqno == next->tcphdr->seqno) { 801bf1c: 6bbb ldr r3, [r7, #56] ; 0x38 801bf1e: 691b ldr r3, [r3, #16] 801bf20: 685a ldr r2, [r3, #4] 801bf22: 4b41 ldr r3, [pc, #260] ; (801c028 ) 801bf24: 681b ldr r3, [r3, #0] 801bf26: 429a cmp r2, r3 801bf28: d11d bne.n 801bf66 /* The sequence number of the incoming segment is the same as the sequence number of the segment on ->ooseq. We check the lengths to see which one to discard. */ if (inseg.len > next->len) { 801bf2a: 4b3e ldr r3, [pc, #248] ; (801c024 ) 801bf2c: 891a ldrh r2, [r3, #8] 801bf2e: 6bbb ldr r3, [r7, #56] ; 0x38 801bf30: 891b ldrh r3, [r3, #8] 801bf32: 429a cmp r2, r3 801bf34: f240 814f bls.w 801c1d6 /* The incoming segment is larger than the old segment. We replace some segments with the new one. */ struct tcp_seg *cseg = tcp_seg_copy(&inseg); 801bf38: 483a ldr r0, [pc, #232] ; (801c024 ) 801bf3a: f7fd facb bl 80194d4 801bf3e: 6178 str r0, [r7, #20] if (cseg != NULL) { 801bf40: 697b ldr r3, [r7, #20] 801bf42: 2b00 cmp r3, #0 801bf44: f000 8149 beq.w 801c1da if (prev != NULL) { 801bf48: 6b7b ldr r3, [r7, #52] ; 0x34 801bf4a: 2b00 cmp r3, #0 801bf4c: d003 beq.n 801bf56 prev->next = cseg; 801bf4e: 6b7b ldr r3, [r7, #52] ; 0x34 801bf50: 697a ldr r2, [r7, #20] 801bf52: 601a str r2, [r3, #0] 801bf54: e002 b.n 801bf5c } else { pcb->ooseq = cseg; 801bf56: 687b ldr r3, [r7, #4] 801bf58: 697a ldr r2, [r7, #20] 801bf5a: 675a str r2, [r3, #116] ; 0x74 } tcp_oos_insert_segment(cseg, next); 801bf5c: 6bb9 ldr r1, [r7, #56] ; 0x38 801bf5e: 6978 ldr r0, [r7, #20] 801bf60: f7ff f8dc bl 801b11c } break; 801bf64: e139 b.n 801c1da segment was smaller than the old one; in either case, we ditch the incoming segment. */ break; } } else { if (prev == NULL) { 801bf66: 6b7b ldr r3, [r7, #52] ; 0x34 801bf68: 2b00 cmp r3, #0 801bf6a: d117 bne.n 801bf9c if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { 801bf6c: 4b2e ldr r3, [pc, #184] ; (801c028 ) 801bf6e: 681a ldr r2, [r3, #0] 801bf70: 6bbb ldr r3, [r7, #56] ; 0x38 801bf72: 691b ldr r3, [r3, #16] 801bf74: 685b ldr r3, [r3, #4] 801bf76: 1ad3 subs r3, r2, r3 801bf78: 2b00 cmp r3, #0 801bf7a: da57 bge.n 801c02c /* The sequence number of the incoming segment is lower than the sequence number of the first segment on the queue. We put the incoming segment first on the queue. */ struct tcp_seg *cseg = tcp_seg_copy(&inseg); 801bf7c: 4829 ldr r0, [pc, #164] ; (801c024 ) 801bf7e: f7fd faa9 bl 80194d4 801bf82: 61b8 str r0, [r7, #24] if (cseg != NULL) { 801bf84: 69bb ldr r3, [r7, #24] 801bf86: 2b00 cmp r3, #0 801bf88: f000 8129 beq.w 801c1de pcb->ooseq = cseg; 801bf8c: 687b ldr r3, [r7, #4] 801bf8e: 69ba ldr r2, [r7, #24] 801bf90: 675a str r2, [r3, #116] ; 0x74 tcp_oos_insert_segment(cseg, next); 801bf92: 6bb9 ldr r1, [r7, #56] ; 0x38 801bf94: 69b8 ldr r0, [r7, #24] 801bf96: f7ff f8c1 bl 801b11c } break; 801bf9a: e120 b.n 801c1de } } else { /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) { 801bf9c: 4b22 ldr r3, [pc, #136] ; (801c028 ) 801bf9e: 681a ldr r2, [r3, #0] 801bfa0: 6b7b ldr r3, [r7, #52] ; 0x34 801bfa2: 691b ldr r3, [r3, #16] 801bfa4: 685b ldr r3, [r3, #4] 801bfa6: 1ad3 subs r3, r2, r3 801bfa8: 3b01 subs r3, #1 801bfaa: 2b00 cmp r3, #0 801bfac: db3e blt.n 801c02c 801bfae: 4b1e ldr r3, [pc, #120] ; (801c028 ) 801bfb0: 681a ldr r2, [r3, #0] 801bfb2: 6bbb ldr r3, [r7, #56] ; 0x38 801bfb4: 691b ldr r3, [r3, #16] 801bfb6: 685b ldr r3, [r3, #4] 801bfb8: 1ad3 subs r3, r2, r3 801bfba: 3301 adds r3, #1 801bfbc: 2b00 cmp r3, #0 801bfbe: dc35 bgt.n 801c02c /* The sequence number of the incoming segment is in between the sequence numbers of the previous and the next segment on ->ooseq. We trim trim the previous segment, delete next segments that included in received segment and trim received, if needed. */ struct tcp_seg *cseg = tcp_seg_copy(&inseg); 801bfc0: 4818 ldr r0, [pc, #96] ; (801c024 ) 801bfc2: f7fd fa87 bl 80194d4 801bfc6: 61f8 str r0, [r7, #28] if (cseg != NULL) { 801bfc8: 69fb ldr r3, [r7, #28] 801bfca: 2b00 cmp r3, #0 801bfcc: f000 8109 beq.w 801c1e2 if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { 801bfd0: 6b7b ldr r3, [r7, #52] ; 0x34 801bfd2: 691b ldr r3, [r3, #16] 801bfd4: 685b ldr r3, [r3, #4] 801bfd6: 6b7a ldr r2, [r7, #52] ; 0x34 801bfd8: 8912 ldrh r2, [r2, #8] 801bfda: 441a add r2, r3 801bfdc: 4b12 ldr r3, [pc, #72] ; (801c028 ) 801bfde: 681b ldr r3, [r3, #0] 801bfe0: 1ad3 subs r3, r2, r3 801bfe2: 2b00 cmp r3, #0 801bfe4: dd12 ble.n 801c00c /* We need to trim the prev segment. */ prev->len = (u16_t)(seqno - prev->tcphdr->seqno); 801bfe6: 4b10 ldr r3, [pc, #64] ; (801c028 ) 801bfe8: 681b ldr r3, [r3, #0] 801bfea: b29a uxth r2, r3 801bfec: 6b7b ldr r3, [r7, #52] ; 0x34 801bfee: 691b ldr r3, [r3, #16] 801bff0: 685b ldr r3, [r3, #4] 801bff2: b29b uxth r3, r3 801bff4: 1ad3 subs r3, r2, r3 801bff6: b29a uxth r2, r3 801bff8: 6b7b ldr r3, [r7, #52] ; 0x34 801bffa: 811a strh r2, [r3, #8] pbuf_realloc(prev->p, prev->len); 801bffc: 6b7b ldr r3, [r7, #52] ; 0x34 801bffe: 685a ldr r2, [r3, #4] 801c000: 6b7b ldr r3, [r7, #52] ; 0x34 801c002: 891b ldrh r3, [r3, #8] 801c004: 4619 mov r1, r3 801c006: 4610 mov r0, r2 801c008: f7fb fbf0 bl 80177ec } prev->next = cseg; 801c00c: 6b7b ldr r3, [r7, #52] ; 0x34 801c00e: 69fa ldr r2, [r7, #28] 801c010: 601a str r2, [r3, #0] tcp_oos_insert_segment(cseg, next); 801c012: 6bb9 ldr r1, [r7, #56] ; 0x38 801c014: 69f8 ldr r0, [r7, #28] 801c016: f7ff f881 bl 801b11c } break; 801c01a: e0e2 b.n 801c1e2 801c01c: 2401a4cc .word 0x2401a4cc 801c020: 2401a4c9 .word 0x2401a4c9 801c024: 2401a498 .word 0x2401a498 801c028: 2401a4bc .word 0x2401a4bc #endif /* LWIP_TCP_SACK_OUT */ /* We don't use 'prev' below, so let's set it to current 'next'. This way even if we break the loop below, 'prev' will be pointing at the segment right in front of the newly added one. */ prev = next; 801c02c: 6bbb ldr r3, [r7, #56] ; 0x38 801c02e: 637b str r3, [r7, #52] ; 0x34 /* If the "next" segment is the last segment on the ooseq queue, we add the incoming segment to the end of the list. */ if (next->next == NULL && 801c030: 6bbb ldr r3, [r7, #56] ; 0x38 801c032: 681b ldr r3, [r3, #0] 801c034: 2b00 cmp r3, #0 801c036: f040 80c6 bne.w 801c1c6 TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { 801c03a: 4b80 ldr r3, [pc, #512] ; (801c23c ) 801c03c: 681a ldr r2, [r3, #0] 801c03e: 6bbb ldr r3, [r7, #56] ; 0x38 801c040: 691b ldr r3, [r3, #16] 801c042: 685b ldr r3, [r3, #4] 801c044: 1ad3 subs r3, r2, r3 if (next->next == NULL && 801c046: 2b00 cmp r3, #0 801c048: f340 80bd ble.w 801c1c6 if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { 801c04c: 6bbb ldr r3, [r7, #56] ; 0x38 801c04e: 691b ldr r3, [r3, #16] 801c050: 899b ldrh r3, [r3, #12] 801c052: b29b uxth r3, r3 801c054: 4618 mov r0, r3 801c056: f7f9 ff73 bl 8015f40 801c05a: 4603 mov r3, r0 801c05c: b2db uxtb r3, r3 801c05e: f003 0301 and.w r3, r3, #1 801c062: 2b00 cmp r3, #0 801c064: f040 80bf bne.w 801c1e6 /* segment "next" already contains all data */ break; } next->next = tcp_seg_copy(&inseg); 801c068: 4875 ldr r0, [pc, #468] ; (801c240 ) 801c06a: f7fd fa33 bl 80194d4 801c06e: 4602 mov r2, r0 801c070: 6bbb ldr r3, [r7, #56] ; 0x38 801c072: 601a str r2, [r3, #0] if (next->next != NULL) { 801c074: 6bbb ldr r3, [r7, #56] ; 0x38 801c076: 681b ldr r3, [r3, #0] 801c078: 2b00 cmp r3, #0 801c07a: f000 80b6 beq.w 801c1ea if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { 801c07e: 6bbb ldr r3, [r7, #56] ; 0x38 801c080: 691b ldr r3, [r3, #16] 801c082: 685b ldr r3, [r3, #4] 801c084: 6bba ldr r2, [r7, #56] ; 0x38 801c086: 8912 ldrh r2, [r2, #8] 801c088: 441a add r2, r3 801c08a: 4b6c ldr r3, [pc, #432] ; (801c23c ) 801c08c: 681b ldr r3, [r3, #0] 801c08e: 1ad3 subs r3, r2, r3 801c090: 2b00 cmp r3, #0 801c092: dd12 ble.n 801c0ba /* We need to trim the last segment. */ next->len = (u16_t)(seqno - next->tcphdr->seqno); 801c094: 4b69 ldr r3, [pc, #420] ; (801c23c ) 801c096: 681b ldr r3, [r3, #0] 801c098: b29a uxth r2, r3 801c09a: 6bbb ldr r3, [r7, #56] ; 0x38 801c09c: 691b ldr r3, [r3, #16] 801c09e: 685b ldr r3, [r3, #4] 801c0a0: b29b uxth r3, r3 801c0a2: 1ad3 subs r3, r2, r3 801c0a4: b29a uxth r2, r3 801c0a6: 6bbb ldr r3, [r7, #56] ; 0x38 801c0a8: 811a strh r2, [r3, #8] pbuf_realloc(next->p, next->len); 801c0aa: 6bbb ldr r3, [r7, #56] ; 0x38 801c0ac: 685a ldr r2, [r3, #4] 801c0ae: 6bbb ldr r3, [r7, #56] ; 0x38 801c0b0: 891b ldrh r3, [r3, #8] 801c0b2: 4619 mov r1, r3 801c0b4: 4610 mov r0, r2 801c0b6: f7fb fb99 bl 80177ec } /* check if the remote side overruns our receive window */ if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) { 801c0ba: 4b62 ldr r3, [pc, #392] ; (801c244 ) 801c0bc: 881b ldrh r3, [r3, #0] 801c0be: 461a mov r2, r3 801c0c0: 4b5e ldr r3, [pc, #376] ; (801c23c ) 801c0c2: 681b ldr r3, [r3, #0] 801c0c4: 441a add r2, r3 801c0c6: 687b ldr r3, [r7, #4] 801c0c8: 6a5b ldr r3, [r3, #36] ; 0x24 801c0ca: 6879 ldr r1, [r7, #4] 801c0cc: 8d09 ldrh r1, [r1, #40] ; 0x28 801c0ce: 440b add r3, r1 801c0d0: 1ad3 subs r3, r2, r3 801c0d2: 2b00 cmp r3, #0 801c0d4: f340 8089 ble.w 801c1ea LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: other end overran receive window" "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) { 801c0d8: 6bbb ldr r3, [r7, #56] ; 0x38 801c0da: 681b ldr r3, [r3, #0] 801c0dc: 691b ldr r3, [r3, #16] 801c0de: 899b ldrh r3, [r3, #12] 801c0e0: b29b uxth r3, r3 801c0e2: 4618 mov r0, r3 801c0e4: f7f9 ff2c bl 8015f40 801c0e8: 4603 mov r3, r0 801c0ea: b2db uxtb r3, r3 801c0ec: f003 0301 and.w r3, r3, #1 801c0f0: 2b00 cmp r3, #0 801c0f2: d022 beq.n 801c13a /* Must remove the FIN from the header as we're trimming * that byte of sequence-space from the packet */ TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN); 801c0f4: 6bbb ldr r3, [r7, #56] ; 0x38 801c0f6: 681b ldr r3, [r3, #0] 801c0f8: 691b ldr r3, [r3, #16] 801c0fa: 899b ldrh r3, [r3, #12] 801c0fc: b29b uxth r3, r3 801c0fe: b21b sxth r3, r3 801c100: f423 537c bic.w r3, r3, #16128 ; 0x3f00 801c104: b21c sxth r4, r3 801c106: 6bbb ldr r3, [r7, #56] ; 0x38 801c108: 681b ldr r3, [r3, #0] 801c10a: 691b ldr r3, [r3, #16] 801c10c: 899b ldrh r3, [r3, #12] 801c10e: b29b uxth r3, r3 801c110: 4618 mov r0, r3 801c112: f7f9 ff15 bl 8015f40 801c116: 4603 mov r3, r0 801c118: b2db uxtb r3, r3 801c11a: b29b uxth r3, r3 801c11c: f003 033e and.w r3, r3, #62 ; 0x3e 801c120: b29b uxth r3, r3 801c122: 4618 mov r0, r3 801c124: f7f9 ff0c bl 8015f40 801c128: 4603 mov r3, r0 801c12a: b21b sxth r3, r3 801c12c: 4323 orrs r3, r4 801c12e: b21a sxth r2, r3 801c130: 6bbb ldr r3, [r7, #56] ; 0x38 801c132: 681b ldr r3, [r3, #0] 801c134: 691b ldr r3, [r3, #16] 801c136: b292 uxth r2, r2 801c138: 819a strh r2, [r3, #12] } /* Adjust length of segment to fit in the window. */ next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno); 801c13a: 687b ldr r3, [r7, #4] 801c13c: 6a5b ldr r3, [r3, #36] ; 0x24 801c13e: b29a uxth r2, r3 801c140: 687b ldr r3, [r7, #4] 801c142: 8d1b ldrh r3, [r3, #40] ; 0x28 801c144: 4413 add r3, r2 801c146: b299 uxth r1, r3 801c148: 4b3c ldr r3, [pc, #240] ; (801c23c ) 801c14a: 681b ldr r3, [r3, #0] 801c14c: b29a uxth r2, r3 801c14e: 6bbb ldr r3, [r7, #56] ; 0x38 801c150: 681b ldr r3, [r3, #0] 801c152: 1a8a subs r2, r1, r2 801c154: b292 uxth r2, r2 801c156: 811a strh r2, [r3, #8] pbuf_realloc(next->next->p, next->next->len); 801c158: 6bbb ldr r3, [r7, #56] ; 0x38 801c15a: 681b ldr r3, [r3, #0] 801c15c: 685a ldr r2, [r3, #4] 801c15e: 6bbb ldr r3, [r7, #56] ; 0x38 801c160: 681b ldr r3, [r3, #0] 801c162: 891b ldrh r3, [r3, #8] 801c164: 4619 mov r1, r3 801c166: 4610 mov r0, r2 801c168: f7fb fb40 bl 80177ec tcplen = TCP_TCPLEN(next->next); 801c16c: 6bbb ldr r3, [r7, #56] ; 0x38 801c16e: 681b ldr r3, [r3, #0] 801c170: 891c ldrh r4, [r3, #8] 801c172: 6bbb ldr r3, [r7, #56] ; 0x38 801c174: 681b ldr r3, [r3, #0] 801c176: 691b ldr r3, [r3, #16] 801c178: 899b ldrh r3, [r3, #12] 801c17a: b29b uxth r3, r3 801c17c: 4618 mov r0, r3 801c17e: f7f9 fedf bl 8015f40 801c182: 4603 mov r3, r0 801c184: b2db uxtb r3, r3 801c186: f003 0303 and.w r3, r3, #3 801c18a: 2b00 cmp r3, #0 801c18c: d001 beq.n 801c192 801c18e: 2301 movs r3, #1 801c190: e000 b.n 801c194 801c192: 2300 movs r3, #0 801c194: 4423 add r3, r4 801c196: b29a uxth r2, r3 801c198: 4b2a ldr r3, [pc, #168] ; (801c244 ) 801c19a: 801a strh r2, [r3, #0] LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", 801c19c: 4b29 ldr r3, [pc, #164] ; (801c244 ) 801c19e: 881b ldrh r3, [r3, #0] 801c1a0: 461a mov r2, r3 801c1a2: 4b26 ldr r3, [pc, #152] ; (801c23c ) 801c1a4: 681b ldr r3, [r3, #0] 801c1a6: 441a add r2, r3 801c1a8: 687b ldr r3, [r7, #4] 801c1aa: 6a5b ldr r3, [r3, #36] ; 0x24 801c1ac: 6879 ldr r1, [r7, #4] 801c1ae: 8d09 ldrh r1, [r1, #40] ; 0x28 801c1b0: 440b add r3, r1 801c1b2: 429a cmp r2, r3 801c1b4: d019 beq.n 801c1ea 801c1b6: 4b24 ldr r3, [pc, #144] ; (801c248 ) 801c1b8: f44f 62df mov.w r2, #1784 ; 0x6f8 801c1bc: 4923 ldr r1, [pc, #140] ; (801c24c ) 801c1be: 4824 ldr r0, [pc, #144] ; (801c250 ) 801c1c0: f005 fbe2 bl 8021988 (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); } } break; 801c1c4: e011 b.n 801c1ea for (next = pcb->ooseq; next != NULL; next = next->next) { 801c1c6: 6bbb ldr r3, [r7, #56] ; 0x38 801c1c8: 681b ldr r3, [r3, #0] 801c1ca: 63bb str r3, [r7, #56] ; 0x38 801c1cc: 6bbb ldr r3, [r7, #56] ; 0x38 801c1ce: 2b00 cmp r3, #0 801c1d0: f47f aea4 bne.w 801bf1c 801c1d4: e00a b.n 801c1ec break; 801c1d6: bf00 nop 801c1d8: e008 b.n 801c1ec break; 801c1da: bf00 nop 801c1dc: e006 b.n 801c1ec break; 801c1de: bf00 nop 801c1e0: e004 b.n 801c1ec break; 801c1e2: bf00 nop 801c1e4: e002 b.n 801c1ec break; 801c1e6: bf00 nop 801c1e8: e000 b.n 801c1ec break; 801c1ea: bf00 nop #endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */ #endif /* TCP_QUEUE_OOSEQ */ /* We send the ACK packet after we've (potentially) dealt with SACKs, so they can be included in the acknowledgment. */ tcp_send_empty_ack(pcb); 801c1ec: 6878 ldr r0, [r7, #4] 801c1ee: f001 fef7 bl 801dfe0 if (pcb->rcv_nxt == seqno) { 801c1f2: e003 b.n 801c1fc } } else { /* The incoming segment is not within the window. */ tcp_send_empty_ack(pcb); 801c1f4: 6878 ldr r0, [r7, #4] 801c1f6: f001 fef3 bl 801dfe0 if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, 801c1fa: e01a b.n 801c232 801c1fc: e019 b.n 801c232 } } else { /* Segments with length 0 is taken care of here. Segments that fall out of the window are ACKed. */ if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) { 801c1fe: 4b0f ldr r3, [pc, #60] ; (801c23c ) 801c200: 681a ldr r2, [r3, #0] 801c202: 687b ldr r3, [r7, #4] 801c204: 6a5b ldr r3, [r3, #36] ; 0x24 801c206: 1ad3 subs r3, r2, r3 801c208: 2b00 cmp r3, #0 801c20a: db0a blt.n 801c222 801c20c: 4b0b ldr r3, [pc, #44] ; (801c23c ) 801c20e: 681a ldr r2, [r3, #0] 801c210: 687b ldr r3, [r7, #4] 801c212: 6a5b ldr r3, [r3, #36] ; 0x24 801c214: 6879 ldr r1, [r7, #4] 801c216: 8d09 ldrh r1, [r1, #40] ; 0x28 801c218: 440b add r3, r1 801c21a: 1ad3 subs r3, r2, r3 801c21c: 3301 adds r3, #1 801c21e: 2b00 cmp r3, #0 801c220: dd07 ble.n 801c232 tcp_ack_now(pcb); 801c222: 687b ldr r3, [r7, #4] 801c224: 8b5b ldrh r3, [r3, #26] 801c226: f043 0302 orr.w r3, r3, #2 801c22a: b29a uxth r2, r3 801c22c: 687b ldr r3, [r7, #4] 801c22e: 835a strh r2, [r3, #26] } } } 801c230: e7ff b.n 801c232 801c232: bf00 nop 801c234: 3750 adds r7, #80 ; 0x50 801c236: 46bd mov sp, r7 801c238: bdb0 pop {r4, r5, r7, pc} 801c23a: bf00 nop 801c23c: 2401a4bc .word 0x2401a4bc 801c240: 2401a498 .word 0x2401a498 801c244: 2401a4c6 .word 0x2401a4c6 801c248: 08025338 .word 0x08025338 801c24c: 080256e0 .word 0x080256e0 801c250: 08025384 .word 0x08025384 0801c254 : static u8_t tcp_get_next_optbyte(void) { 801c254: b480 push {r7} 801c256: b083 sub sp, #12 801c258: af00 add r7, sp, #0 u16_t optidx = tcp_optidx++; 801c25a: 4b15 ldr r3, [pc, #84] ; (801c2b0 ) 801c25c: 881b ldrh r3, [r3, #0] 801c25e: 1c5a adds r2, r3, #1 801c260: b291 uxth r1, r2 801c262: 4a13 ldr r2, [pc, #76] ; (801c2b0 ) 801c264: 8011 strh r1, [r2, #0] 801c266: 80fb strh r3, [r7, #6] if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) { 801c268: 4b12 ldr r3, [pc, #72] ; (801c2b4 ) 801c26a: 681b ldr r3, [r3, #0] 801c26c: 2b00 cmp r3, #0 801c26e: d004 beq.n 801c27a 801c270: 4b11 ldr r3, [pc, #68] ; (801c2b8 ) 801c272: 881b ldrh r3, [r3, #0] 801c274: 88fa ldrh r2, [r7, #6] 801c276: 429a cmp r2, r3 801c278: d208 bcs.n 801c28c u8_t *opts = (u8_t *)tcphdr + TCP_HLEN; 801c27a: 4b10 ldr r3, [pc, #64] ; (801c2bc ) 801c27c: 681b ldr r3, [r3, #0] 801c27e: 3314 adds r3, #20 801c280: 603b str r3, [r7, #0] return opts[optidx]; 801c282: 88fb ldrh r3, [r7, #6] 801c284: 683a ldr r2, [r7, #0] 801c286: 4413 add r3, r2 801c288: 781b ldrb r3, [r3, #0] 801c28a: e00b b.n 801c2a4 } else { u8_t idx = (u8_t)(optidx - tcphdr_opt1len); 801c28c: 88fb ldrh r3, [r7, #6] 801c28e: b2da uxtb r2, r3 801c290: 4b09 ldr r3, [pc, #36] ; (801c2b8 ) 801c292: 881b ldrh r3, [r3, #0] 801c294: b2db uxtb r3, r3 801c296: 1ad3 subs r3, r2, r3 801c298: 717b strb r3, [r7, #5] return tcphdr_opt2[idx]; 801c29a: 4b06 ldr r3, [pc, #24] ; (801c2b4 ) 801c29c: 681a ldr r2, [r3, #0] 801c29e: 797b ldrb r3, [r7, #5] 801c2a0: 4413 add r3, r2 801c2a2: 781b ldrb r3, [r3, #0] } } 801c2a4: 4618 mov r0, r3 801c2a6: 370c adds r7, #12 801c2a8: 46bd mov sp, r7 801c2aa: f85d 7b04 ldr.w r7, [sp], #4 801c2ae: 4770 bx lr 801c2b0: 2401a4b8 .word 0x2401a4b8 801c2b4: 2401a4b4 .word 0x2401a4b4 801c2b8: 2401a4b2 .word 0x2401a4b2 801c2bc: 2401a4ac .word 0x2401a4ac 0801c2c0 : * * @param pcb the tcp_pcb for which a segment arrived */ static void tcp_parseopt(struct tcp_pcb *pcb) { 801c2c0: b580 push {r7, lr} 801c2c2: b084 sub sp, #16 801c2c4: af00 add r7, sp, #0 801c2c6: 6078 str r0, [r7, #4] u16_t mss; #if LWIP_TCP_TIMESTAMPS u32_t tsval; #endif LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL); 801c2c8: 687b ldr r3, [r7, #4] 801c2ca: 2b00 cmp r3, #0 801c2cc: d106 bne.n 801c2dc 801c2ce: 4b32 ldr r3, [pc, #200] ; (801c398 ) 801c2d0: f240 727d movw r2, #1917 ; 0x77d 801c2d4: 4931 ldr r1, [pc, #196] ; (801c39c ) 801c2d6: 4832 ldr r0, [pc, #200] ; (801c3a0 ) 801c2d8: f005 fb56 bl 8021988 /* Parse the TCP MSS option, if present. */ if (tcphdr_optlen != 0) { 801c2dc: 4b31 ldr r3, [pc, #196] ; (801c3a4 ) 801c2de: 881b ldrh r3, [r3, #0] 801c2e0: 2b00 cmp r3, #0 801c2e2: d056 beq.n 801c392 for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) { 801c2e4: 4b30 ldr r3, [pc, #192] ; (801c3a8 ) 801c2e6: 2200 movs r2, #0 801c2e8: 801a strh r2, [r3, #0] 801c2ea: e046 b.n 801c37a u8_t opt = tcp_get_next_optbyte(); 801c2ec: f7ff ffb2 bl 801c254 801c2f0: 4603 mov r3, r0 801c2f2: 73fb strb r3, [r7, #15] switch (opt) { 801c2f4: 7bfb ldrb r3, [r7, #15] 801c2f6: 2b02 cmp r3, #2 801c2f8: d006 beq.n 801c308 801c2fa: 2b02 cmp r3, #2 801c2fc: dc2c bgt.n 801c358 801c2fe: 2b00 cmp r3, #0 801c300: d042 beq.n 801c388 801c302: 2b01 cmp r3, #1 801c304: d128 bne.n 801c358 LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n")); return; case LWIP_TCP_OPT_NOP: /* NOP option. */ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n")); break; 801c306: e038 b.n 801c37a case LWIP_TCP_OPT_MSS: LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n")); if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) { 801c308: f7ff ffa4 bl 801c254 801c30c: 4603 mov r3, r0 801c30e: 2b04 cmp r3, #4 801c310: d13c bne.n 801c38c 801c312: 4b25 ldr r3, [pc, #148] ; (801c3a8 ) 801c314: 881b ldrh r3, [r3, #0] 801c316: 3301 adds r3, #1 801c318: 4a22 ldr r2, [pc, #136] ; (801c3a4 ) 801c31a: 8812 ldrh r2, [r2, #0] 801c31c: 4293 cmp r3, r2 801c31e: da35 bge.n 801c38c /* Bad length */ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); return; } /* An MSS option with the right option length. */ mss = (u16_t)(tcp_get_next_optbyte() << 8); 801c320: f7ff ff98 bl 801c254 801c324: 4603 mov r3, r0 801c326: b29b uxth r3, r3 801c328: 021b lsls r3, r3, #8 801c32a: 81bb strh r3, [r7, #12] mss |= tcp_get_next_optbyte(); 801c32c: f7ff ff92 bl 801c254 801c330: 4603 mov r3, r0 801c332: b29a uxth r2, r3 801c334: 89bb ldrh r3, [r7, #12] 801c336: 4313 orrs r3, r2 801c338: 81bb strh r3, [r7, #12] /* Limit the mss to the configured TCP_MSS and prevent division by zero */ pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss; 801c33a: 89bb ldrh r3, [r7, #12] 801c33c: f240 52b4 movw r2, #1460 ; 0x5b4 801c340: 4293 cmp r3, r2 801c342: d804 bhi.n 801c34e 801c344: 89bb ldrh r3, [r7, #12] 801c346: 2b00 cmp r3, #0 801c348: d001 beq.n 801c34e 801c34a: 89ba ldrh r2, [r7, #12] 801c34c: e001 b.n 801c352 801c34e: f240 52b4 movw r2, #1460 ; 0x5b4 801c352: 687b ldr r3, [r7, #4] 801c354: 865a strh r2, [r3, #50] ; 0x32 break; 801c356: e010 b.n 801c37a } break; #endif /* LWIP_TCP_SACK_OUT */ default: LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n")); data = tcp_get_next_optbyte(); 801c358: f7ff ff7c bl 801c254 801c35c: 4603 mov r3, r0 801c35e: 72fb strb r3, [r7, #11] if (data < 2) { 801c360: 7afb ldrb r3, [r7, #11] 801c362: 2b01 cmp r3, #1 801c364: d914 bls.n 801c390 and we don't process them further. */ return; } /* All other options have a length field, so that we easily can skip past them. */ tcp_optidx += data - 2; 801c366: 7afb ldrb r3, [r7, #11] 801c368: b29a uxth r2, r3 801c36a: 4b0f ldr r3, [pc, #60] ; (801c3a8 ) 801c36c: 881b ldrh r3, [r3, #0] 801c36e: 4413 add r3, r2 801c370: b29b uxth r3, r3 801c372: 3b02 subs r3, #2 801c374: b29a uxth r2, r3 801c376: 4b0c ldr r3, [pc, #48] ; (801c3a8 ) 801c378: 801a strh r2, [r3, #0] for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) { 801c37a: 4b0b ldr r3, [pc, #44] ; (801c3a8 ) 801c37c: 881a ldrh r2, [r3, #0] 801c37e: 4b09 ldr r3, [pc, #36] ; (801c3a4 ) 801c380: 881b ldrh r3, [r3, #0] 801c382: 429a cmp r2, r3 801c384: d3b2 bcc.n 801c2ec 801c386: e004 b.n 801c392 return; 801c388: bf00 nop 801c38a: e002 b.n 801c392 return; 801c38c: bf00 nop 801c38e: e000 b.n 801c392 return; 801c390: bf00 nop } } } } 801c392: 3710 adds r7, #16 801c394: 46bd mov sp, r7 801c396: bd80 pop {r7, pc} 801c398: 08025338 .word 0x08025338 801c39c: 0802579c .word 0x0802579c 801c3a0: 08025384 .word 0x08025384 801c3a4: 2401a4b0 .word 0x2401a4b0 801c3a8: 2401a4b8 .word 0x2401a4b8 0801c3ac : void tcp_trigger_input_pcb_close(void) { 801c3ac: b480 push {r7} 801c3ae: af00 add r7, sp, #0 recv_flags |= TF_CLOSED; 801c3b0: 4b05 ldr r3, [pc, #20] ; (801c3c8 ) 801c3b2: 781b ldrb r3, [r3, #0] 801c3b4: f043 0310 orr.w r3, r3, #16 801c3b8: b2da uxtb r2, r3 801c3ba: 4b03 ldr r3, [pc, #12] ; (801c3c8 ) 801c3bc: 701a strb r2, [r3, #0] } 801c3be: bf00 nop 801c3c0: 46bd mov sp, r7 801c3c2: f85d 7b04 ldr.w r7, [sp], #4 801c3c6: 4770 bx lr 801c3c8: 2401a4c9 .word 0x2401a4c9 0801c3cc : static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif); /* tcp_route: common code that returns a fixed bound netif or calls ip_route */ static struct netif * tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst) { 801c3cc: b580 push {r7, lr} 801c3ce: b084 sub sp, #16 801c3d0: af00 add r7, sp, #0 801c3d2: 60f8 str r0, [r7, #12] 801c3d4: 60b9 str r1, [r7, #8] 801c3d6: 607a str r2, [r7, #4] LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */ if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) { 801c3d8: 68fb ldr r3, [r7, #12] 801c3da: 2b00 cmp r3, #0 801c3dc: d00a beq.n 801c3f4 801c3de: 68fb ldr r3, [r7, #12] 801c3e0: 7a1b ldrb r3, [r3, #8] 801c3e2: 2b00 cmp r3, #0 801c3e4: d006 beq.n 801c3f4 return netif_get_by_index(pcb->netif_idx); 801c3e6: 68fb ldr r3, [r7, #12] 801c3e8: 7a1b ldrb r3, [r3, #8] 801c3ea: 4618 mov r0, r3 801c3ec: f7fa fff2 bl 80173d4 801c3f0: 4603 mov r3, r0 801c3f2: e003 b.n 801c3fc } else { return ip_route(src, dst); 801c3f4: 6878 ldr r0, [r7, #4] 801c3f6: f003 fd7d bl 801fef4 801c3fa: 4603 mov r3, r0 } } 801c3fc: 4618 mov r0, r3 801c3fe: 3710 adds r7, #16 801c400: 46bd mov sp, r7 801c402: bd80 pop {r7, pc} 0801c404 : * The TCP header is filled in except ackno and wnd. * p is freed on failure. */ static struct tcp_seg * tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags) { 801c404: b590 push {r4, r7, lr} 801c406: b087 sub sp, #28 801c408: af00 add r7, sp, #0 801c40a: 60f8 str r0, [r7, #12] 801c40c: 60b9 str r1, [r7, #8] 801c40e: 603b str r3, [r7, #0] 801c410: 4613 mov r3, r2 801c412: 71fb strb r3, [r7, #7] struct tcp_seg *seg; u8_t optlen; LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL); 801c414: 68fb ldr r3, [r7, #12] 801c416: 2b00 cmp r3, #0 801c418: d105 bne.n 801c426 801c41a: 4b45 ldr r3, [pc, #276] ; (801c530 ) 801c41c: 22a3 movs r2, #163 ; 0xa3 801c41e: 4945 ldr r1, [pc, #276] ; (801c534 ) 801c420: 4845 ldr r0, [pc, #276] ; (801c538 ) 801c422: f005 fab1 bl 8021988 LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL); 801c426: 68bb ldr r3, [r7, #8] 801c428: 2b00 cmp r3, #0 801c42a: d105 bne.n 801c438 801c42c: 4b40 ldr r3, [pc, #256] ; (801c530 ) 801c42e: 22a4 movs r2, #164 ; 0xa4 801c430: 4942 ldr r1, [pc, #264] ; (801c53c ) 801c432: 4841 ldr r0, [pc, #260] ; (801c538 ) 801c434: f005 faa8 bl 8021988 optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); 801c438: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 801c43c: 009b lsls r3, r3, #2 801c43e: b2db uxtb r3, r3 801c440: f003 0304 and.w r3, r3, #4 801c444: 75fb strb r3, [r7, #23] if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) { 801c446: 2003 movs r0, #3 801c448: f7fa fb42 bl 8016ad0 801c44c: 6138 str r0, [r7, #16] 801c44e: 693b ldr r3, [r7, #16] 801c450: 2b00 cmp r3, #0 801c452: d104 bne.n 801c45e LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n")); pbuf_free(p); 801c454: 68b8 ldr r0, [r7, #8] 801c456: f7fb fb4f bl 8017af8 return NULL; 801c45a: 2300 movs r3, #0 801c45c: e064 b.n 801c528 } seg->flags = optflags; 801c45e: 693b ldr r3, [r7, #16] 801c460: f897 2028 ldrb.w r2, [r7, #40] ; 0x28 801c464: 731a strb r2, [r3, #12] seg->next = NULL; 801c466: 693b ldr r3, [r7, #16] 801c468: 2200 movs r2, #0 801c46a: 601a str r2, [r3, #0] seg->p = p; 801c46c: 693b ldr r3, [r7, #16] 801c46e: 68ba ldr r2, [r7, #8] 801c470: 605a str r2, [r3, #4] LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen); 801c472: 68bb ldr r3, [r7, #8] 801c474: 891a ldrh r2, [r3, #8] 801c476: 7dfb ldrb r3, [r7, #23] 801c478: b29b uxth r3, r3 801c47a: 429a cmp r2, r3 801c47c: d205 bcs.n 801c48a 801c47e: 4b2c ldr r3, [pc, #176] ; (801c530 ) 801c480: 22b0 movs r2, #176 ; 0xb0 801c482: 492f ldr r1, [pc, #188] ; (801c540 ) 801c484: 482c ldr r0, [pc, #176] ; (801c538 ) 801c486: f005 fa7f bl 8021988 seg->len = p->tot_len - optlen; 801c48a: 68bb ldr r3, [r7, #8] 801c48c: 891a ldrh r2, [r3, #8] 801c48e: 7dfb ldrb r3, [r7, #23] 801c490: b29b uxth r3, r3 801c492: 1ad3 subs r3, r2, r3 801c494: b29a uxth r2, r3 801c496: 693b ldr r3, [r7, #16] 801c498: 811a strh r2, [r3, #8] #if TCP_OVERSIZE_DBGCHECK seg->oversize_left = 0; 801c49a: 693b ldr r3, [r7, #16] 801c49c: 2200 movs r2, #0 801c49e: 815a strh r2, [r3, #10] LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED", (optflags & TF_SEG_DATA_CHECKSUMMED) == 0); #endif /* TCP_CHECKSUM_ON_COPY */ /* build TCP header */ if (pbuf_add_header(p, TCP_HLEN)) { 801c4a0: 2114 movs r1, #20 801c4a2: 68b8 ldr r0, [r7, #8] 801c4a4: f7fb fa92 bl 80179cc 801c4a8: 4603 mov r3, r0 801c4aa: 2b00 cmp r3, #0 801c4ac: d004 beq.n 801c4b8 LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n")); TCP_STATS_INC(tcp.err); tcp_seg_free(seg); 801c4ae: 6938 ldr r0, [r7, #16] 801c4b0: f7fc fff7 bl 80194a2 return NULL; 801c4b4: 2300 movs r3, #0 801c4b6: e037 b.n 801c528 } seg->tcphdr = (struct tcp_hdr *)seg->p->payload; 801c4b8: 693b ldr r3, [r7, #16] 801c4ba: 685b ldr r3, [r3, #4] 801c4bc: 685a ldr r2, [r3, #4] 801c4be: 693b ldr r3, [r7, #16] 801c4c0: 611a str r2, [r3, #16] seg->tcphdr->src = lwip_htons(pcb->local_port); 801c4c2: 68fb ldr r3, [r7, #12] 801c4c4: 8ada ldrh r2, [r3, #22] 801c4c6: 693b ldr r3, [r7, #16] 801c4c8: 691c ldr r4, [r3, #16] 801c4ca: 4610 mov r0, r2 801c4cc: f7f9 fd38 bl 8015f40 801c4d0: 4603 mov r3, r0 801c4d2: 8023 strh r3, [r4, #0] seg->tcphdr->dest = lwip_htons(pcb->remote_port); 801c4d4: 68fb ldr r3, [r7, #12] 801c4d6: 8b1a ldrh r2, [r3, #24] 801c4d8: 693b ldr r3, [r7, #16] 801c4da: 691c ldr r4, [r3, #16] 801c4dc: 4610 mov r0, r2 801c4de: f7f9 fd2f bl 8015f40 801c4e2: 4603 mov r3, r0 801c4e4: 8063 strh r3, [r4, #2] seg->tcphdr->seqno = lwip_htonl(seqno); 801c4e6: 693b ldr r3, [r7, #16] 801c4e8: 691c ldr r4, [r3, #16] 801c4ea: 6838 ldr r0, [r7, #0] 801c4ec: f7f9 fd3d bl 8015f6a 801c4f0: 4603 mov r3, r0 801c4f2: 6063 str r3, [r4, #4] /* ackno is set in tcp_output */ TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags); 801c4f4: 7dfb ldrb r3, [r7, #23] 801c4f6: 089b lsrs r3, r3, #2 801c4f8: b2db uxtb r3, r3 801c4fa: b29b uxth r3, r3 801c4fc: 3305 adds r3, #5 801c4fe: b29b uxth r3, r3 801c500: 031b lsls r3, r3, #12 801c502: b29a uxth r2, r3 801c504: 79fb ldrb r3, [r7, #7] 801c506: b29b uxth r3, r3 801c508: 4313 orrs r3, r2 801c50a: b29a uxth r2, r3 801c50c: 693b ldr r3, [r7, #16] 801c50e: 691c ldr r4, [r3, #16] 801c510: 4610 mov r0, r2 801c512: f7f9 fd15 bl 8015f40 801c516: 4603 mov r3, r0 801c518: 81a3 strh r3, [r4, #12] /* wnd and chksum are set in tcp_output */ seg->tcphdr->urgp = 0; 801c51a: 693b ldr r3, [r7, #16] 801c51c: 691b ldr r3, [r3, #16] 801c51e: 2200 movs r2, #0 801c520: 749a strb r2, [r3, #18] 801c522: 2200 movs r2, #0 801c524: 74da strb r2, [r3, #19] return seg; 801c526: 693b ldr r3, [r7, #16] } 801c528: 4618 mov r0, r3 801c52a: 371c adds r7, #28 801c52c: 46bd mov sp, r7 801c52e: bd90 pop {r4, r7, pc} 801c530: 080257b8 .word 0x080257b8 801c534: 080257ec .word 0x080257ec 801c538: 0802580c .word 0x0802580c 801c53c: 08025834 .word 0x08025834 801c540: 08025858 .word 0x08025858 0801c544 : #if TCP_OVERSIZE static struct pbuf * tcp_pbuf_prealloc(pbuf_layer layer, u16_t length, u16_t max_length, u16_t *oversize, const struct tcp_pcb *pcb, u8_t apiflags, u8_t first_seg) { 801c544: b580 push {r7, lr} 801c546: b086 sub sp, #24 801c548: af00 add r7, sp, #0 801c54a: 607b str r3, [r7, #4] 801c54c: 4603 mov r3, r0 801c54e: 73fb strb r3, [r7, #15] 801c550: 460b mov r3, r1 801c552: 81bb strh r3, [r7, #12] 801c554: 4613 mov r3, r2 801c556: 817b strh r3, [r7, #10] struct pbuf *p; u16_t alloc = length; 801c558: 89bb ldrh r3, [r7, #12] 801c55a: 82fb strh r3, [r7, #22] LWIP_ASSERT("tcp_pbuf_prealloc: invalid oversize", oversize != NULL); 801c55c: 687b ldr r3, [r7, #4] 801c55e: 2b00 cmp r3, #0 801c560: d105 bne.n 801c56e 801c562: 4b30 ldr r3, [pc, #192] ; (801c624 ) 801c564: 22e8 movs r2, #232 ; 0xe8 801c566: 4930 ldr r1, [pc, #192] ; (801c628 ) 801c568: 4830 ldr r0, [pc, #192] ; (801c62c ) 801c56a: f005 fa0d bl 8021988 LWIP_ASSERT("tcp_pbuf_prealloc: invalid pcb", pcb != NULL); 801c56e: 6a3b ldr r3, [r7, #32] 801c570: 2b00 cmp r3, #0 801c572: d105 bne.n 801c580 801c574: 4b2b ldr r3, [pc, #172] ; (801c624 ) 801c576: 22e9 movs r2, #233 ; 0xe9 801c578: 492d ldr r1, [pc, #180] ; (801c630 ) 801c57a: 482c ldr r0, [pc, #176] ; (801c62c ) 801c57c: f005 fa04 bl 8021988 LWIP_UNUSED_ARG(pcb); LWIP_UNUSED_ARG(apiflags); LWIP_UNUSED_ARG(first_seg); alloc = max_length; #else /* LWIP_NETIF_TX_SINGLE_PBUF */ if (length < max_length) { 801c580: 89ba ldrh r2, [r7, #12] 801c582: 897b ldrh r3, [r7, #10] 801c584: 429a cmp r2, r3 801c586: d221 bcs.n 801c5cc * * Did the user set TCP_WRITE_FLAG_MORE? * * Will the Nagle algorithm defer transmission of this segment? */ if ((apiflags & TCP_WRITE_FLAG_MORE) || 801c588: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 801c58c: f003 0302 and.w r3, r3, #2 801c590: 2b00 cmp r3, #0 801c592: d111 bne.n 801c5b8 (!(pcb->flags & TF_NODELAY) && 801c594: 6a3b ldr r3, [r7, #32] 801c596: 8b5b ldrh r3, [r3, #26] 801c598: f003 0340 and.w r3, r3, #64 ; 0x40 if ((apiflags & TCP_WRITE_FLAG_MORE) || 801c59c: 2b00 cmp r3, #0 801c59e: d115 bne.n 801c5cc (!(pcb->flags & TF_NODELAY) && 801c5a0: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 801c5a4: 2b00 cmp r3, #0 801c5a6: d007 beq.n 801c5b8 (!first_seg || pcb->unsent != NULL || 801c5a8: 6a3b ldr r3, [r7, #32] 801c5aa: 6edb ldr r3, [r3, #108] ; 0x6c (!first_seg || 801c5ac: 2b00 cmp r3, #0 801c5ae: d103 bne.n 801c5b8 pcb->unacked != NULL))) { 801c5b0: 6a3b ldr r3, [r7, #32] 801c5b2: 6f1b ldr r3, [r3, #112] ; 0x70 pcb->unsent != NULL || 801c5b4: 2b00 cmp r3, #0 801c5b6: d009 beq.n 801c5cc alloc = LWIP_MIN(max_length, LWIP_MEM_ALIGN_SIZE(TCP_OVERSIZE_CALC_LENGTH(length))); 801c5b8: 89bb ldrh r3, [r7, #12] 801c5ba: f203 53b7 addw r3, r3, #1463 ; 0x5b7 801c5be: f023 0203 bic.w r2, r3, #3 801c5c2: 897b ldrh r3, [r7, #10] 801c5c4: 4293 cmp r3, r2 801c5c6: bf28 it cs 801c5c8: 4613 movcs r3, r2 801c5ca: 82fb strh r3, [r7, #22] } } #endif /* LWIP_NETIF_TX_SINGLE_PBUF */ p = pbuf_alloc(layer, alloc, PBUF_RAM); 801c5cc: 8af9 ldrh r1, [r7, #22] 801c5ce: 7bfb ldrb r3, [r7, #15] 801c5d0: f44f 7220 mov.w r2, #640 ; 0x280 801c5d4: 4618 mov r0, r3 801c5d6: f7fa ffa7 bl 8017528 801c5da: 6138 str r0, [r7, #16] if (p == NULL) { 801c5dc: 693b ldr r3, [r7, #16] 801c5de: 2b00 cmp r3, #0 801c5e0: d101 bne.n 801c5e6 return NULL; 801c5e2: 2300 movs r3, #0 801c5e4: e019 b.n 801c61a } LWIP_ASSERT("need unchained pbuf", p->next == NULL); 801c5e6: 693b ldr r3, [r7, #16] 801c5e8: 681b ldr r3, [r3, #0] 801c5ea: 2b00 cmp r3, #0 801c5ec: d006 beq.n 801c5fc 801c5ee: 4b0d ldr r3, [pc, #52] ; (801c624 ) 801c5f0: f240 120b movw r2, #267 ; 0x10b 801c5f4: 490f ldr r1, [pc, #60] ; (801c634 ) 801c5f6: 480d ldr r0, [pc, #52] ; (801c62c ) 801c5f8: f005 f9c6 bl 8021988 *oversize = p->len - length; 801c5fc: 693b ldr r3, [r7, #16] 801c5fe: 895a ldrh r2, [r3, #10] 801c600: 89bb ldrh r3, [r7, #12] 801c602: 1ad3 subs r3, r2, r3 801c604: b29a uxth r2, r3 801c606: 687b ldr r3, [r7, #4] 801c608: 801a strh r2, [r3, #0] /* trim p->len to the currently used size */ p->len = p->tot_len = length; 801c60a: 693b ldr r3, [r7, #16] 801c60c: 89ba ldrh r2, [r7, #12] 801c60e: 811a strh r2, [r3, #8] 801c610: 693b ldr r3, [r7, #16] 801c612: 891a ldrh r2, [r3, #8] 801c614: 693b ldr r3, [r7, #16] 801c616: 815a strh r2, [r3, #10] return p; 801c618: 693b ldr r3, [r7, #16] } 801c61a: 4618 mov r0, r3 801c61c: 3718 adds r7, #24 801c61e: 46bd mov sp, r7 801c620: bd80 pop {r7, pc} 801c622: bf00 nop 801c624: 080257b8 .word 0x080257b8 801c628: 08025870 .word 0x08025870 801c62c: 0802580c .word 0x0802580c 801c630: 08025894 .word 0x08025894 801c634: 080258b4 .word 0x080258b4 0801c638 : * @param len length of data to send (checked agains snd_buf) * @return ERR_OK if tcp_write is allowed to proceed, another err_t otherwise */ static err_t tcp_write_checks(struct tcp_pcb *pcb, u16_t len) { 801c638: b580 push {r7, lr} 801c63a: b082 sub sp, #8 801c63c: af00 add r7, sp, #0 801c63e: 6078 str r0, [r7, #4] 801c640: 460b mov r3, r1 801c642: 807b strh r3, [r7, #2] LWIP_ASSERT("tcp_write_checks: invalid pcb", pcb != NULL); 801c644: 687b ldr r3, [r7, #4] 801c646: 2b00 cmp r3, #0 801c648: d106 bne.n 801c658 801c64a: 4b33 ldr r3, [pc, #204] ; (801c718 ) 801c64c: f240 1233 movw r2, #307 ; 0x133 801c650: 4932 ldr r1, [pc, #200] ; (801c71c ) 801c652: 4833 ldr r0, [pc, #204] ; (801c720 ) 801c654: f005 f998 bl 8021988 /* connection is in invalid state for data transmission? */ if ((pcb->state != ESTABLISHED) && 801c658: 687b ldr r3, [r7, #4] 801c65a: 7d1b ldrb r3, [r3, #20] 801c65c: 2b04 cmp r3, #4 801c65e: d00e beq.n 801c67e (pcb->state != CLOSE_WAIT) && 801c660: 687b ldr r3, [r7, #4] 801c662: 7d1b ldrb r3, [r3, #20] if ((pcb->state != ESTABLISHED) && 801c664: 2b07 cmp r3, #7 801c666: d00a beq.n 801c67e (pcb->state != SYN_SENT) && 801c668: 687b ldr r3, [r7, #4] 801c66a: 7d1b ldrb r3, [r3, #20] (pcb->state != CLOSE_WAIT) && 801c66c: 2b02 cmp r3, #2 801c66e: d006 beq.n 801c67e (pcb->state != SYN_RCVD)) { 801c670: 687b ldr r3, [r7, #4] 801c672: 7d1b ldrb r3, [r3, #20] (pcb->state != SYN_SENT) && 801c674: 2b03 cmp r3, #3 801c676: d002 beq.n 801c67e LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n")); return ERR_CONN; 801c678: f06f 030a mvn.w r3, #10 801c67c: e048 b.n 801c710 } else if (len == 0) { 801c67e: 887b ldrh r3, [r7, #2] 801c680: 2b00 cmp r3, #0 801c682: d101 bne.n 801c688 return ERR_OK; 801c684: 2300 movs r3, #0 801c686: e043 b.n 801c710 } /* fail on too much data */ if (len > pcb->snd_buf) { 801c688: 687b ldr r3, [r7, #4] 801c68a: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64 801c68e: 887a ldrh r2, [r7, #2] 801c690: 429a cmp r2, r3 801c692: d909 bls.n 801c6a8 LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too much data (len=%"U16_F" > snd_buf=%"TCPWNDSIZE_F")\n", len, pcb->snd_buf)); tcp_set_flags(pcb, TF_NAGLEMEMERR); 801c694: 687b ldr r3, [r7, #4] 801c696: 8b5b ldrh r3, [r3, #26] 801c698: f043 0380 orr.w r3, r3, #128 ; 0x80 801c69c: b29a uxth r2, r3 801c69e: 687b ldr r3, [r7, #4] 801c6a0: 835a strh r2, [r3, #26] return ERR_MEM; 801c6a2: f04f 33ff mov.w r3, #4294967295 801c6a6: e033 b.n 801c710 LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: queuelen: %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen)); /* If total number of pbufs on the unsent/unacked queues exceeds the * configured maximum, return an error */ /* check for configured max queuelen and possible overflow */ if (pcb->snd_queuelen >= LWIP_MIN(TCP_SND_QUEUELEN, (TCP_SNDQUEUELEN_OVERFLOW + 1))) { 801c6a8: 687b ldr r3, [r7, #4] 801c6aa: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801c6ae: 2b0f cmp r3, #15 801c6b0: d909 bls.n 801c6c6 LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too long queue %"U16_F" (max %"U16_F")\n", pcb->snd_queuelen, (u16_t)TCP_SND_QUEUELEN)); TCP_STATS_INC(tcp.memerr); tcp_set_flags(pcb, TF_NAGLEMEMERR); 801c6b2: 687b ldr r3, [r7, #4] 801c6b4: 8b5b ldrh r3, [r3, #26] 801c6b6: f043 0380 orr.w r3, r3, #128 ; 0x80 801c6ba: b29a uxth r2, r3 801c6bc: 687b ldr r3, [r7, #4] 801c6be: 835a strh r2, [r3, #26] return ERR_MEM; 801c6c0: f04f 33ff mov.w r3, #4294967295 801c6c4: e024 b.n 801c710 } if (pcb->snd_queuelen != 0) { 801c6c6: 687b ldr r3, [r7, #4] 801c6c8: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801c6cc: 2b00 cmp r3, #0 801c6ce: d00f beq.n 801c6f0 LWIP_ASSERT("tcp_write: pbufs on queue => at least one queue non-empty", 801c6d0: 687b ldr r3, [r7, #4] 801c6d2: 6f1b ldr r3, [r3, #112] ; 0x70 801c6d4: 2b00 cmp r3, #0 801c6d6: d11a bne.n 801c70e 801c6d8: 687b ldr r3, [r7, #4] 801c6da: 6edb ldr r3, [r3, #108] ; 0x6c 801c6dc: 2b00 cmp r3, #0 801c6de: d116 bne.n 801c70e 801c6e0: 4b0d ldr r3, [pc, #52] ; (801c718 ) 801c6e2: f240 1255 movw r2, #341 ; 0x155 801c6e6: 490f ldr r1, [pc, #60] ; (801c724 ) 801c6e8: 480d ldr r0, [pc, #52] ; (801c720 ) 801c6ea: f005 f94d bl 8021988 801c6ee: e00e b.n 801c70e pcb->unacked != NULL || pcb->unsent != NULL); } else { LWIP_ASSERT("tcp_write: no pbufs on queue => both queues empty", 801c6f0: 687b ldr r3, [r7, #4] 801c6f2: 6f1b ldr r3, [r3, #112] ; 0x70 801c6f4: 2b00 cmp r3, #0 801c6f6: d103 bne.n 801c700 801c6f8: 687b ldr r3, [r7, #4] 801c6fa: 6edb ldr r3, [r3, #108] ; 0x6c 801c6fc: 2b00 cmp r3, #0 801c6fe: d006 beq.n 801c70e 801c700: 4b05 ldr r3, [pc, #20] ; (801c718 ) 801c702: f44f 72ac mov.w r2, #344 ; 0x158 801c706: 4908 ldr r1, [pc, #32] ; (801c728 ) 801c708: 4805 ldr r0, [pc, #20] ; (801c720 ) 801c70a: f005 f93d bl 8021988 pcb->unacked == NULL && pcb->unsent == NULL); } return ERR_OK; 801c70e: 2300 movs r3, #0 } 801c710: 4618 mov r0, r3 801c712: 3708 adds r7, #8 801c714: 46bd mov sp, r7 801c716: bd80 pop {r7, pc} 801c718: 080257b8 .word 0x080257b8 801c71c: 080258c8 .word 0x080258c8 801c720: 0802580c .word 0x0802580c 801c724: 080258e8 .word 0x080258e8 801c728: 08025924 .word 0x08025924 0801c72c : * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will not be set on last segment sent, * @return ERR_OK if enqueued, another err_t on error */ err_t tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t apiflags) { 801c72c: b590 push {r4, r7, lr} 801c72e: b09d sub sp, #116 ; 0x74 801c730: af04 add r7, sp, #16 801c732: 60f8 str r0, [r7, #12] 801c734: 60b9 str r1, [r7, #8] 801c736: 4611 mov r1, r2 801c738: 461a mov r2, r3 801c73a: 460b mov r3, r1 801c73c: 80fb strh r3, [r7, #6] 801c73e: 4613 mov r3, r2 801c740: 717b strb r3, [r7, #5] struct pbuf *concat_p = NULL; 801c742: 2300 movs r3, #0 801c744: 63fb str r3, [r7, #60] ; 0x3c struct tcp_seg *last_unsent = NULL, *seg = NULL, *prev_seg = NULL, *queue = NULL; 801c746: 2300 movs r3, #0 801c748: 643b str r3, [r7, #64] ; 0x40 801c74a: 2300 movs r3, #0 801c74c: 657b str r3, [r7, #84] ; 0x54 801c74e: 2300 movs r3, #0 801c750: 653b str r3, [r7, #80] ; 0x50 801c752: 2300 movs r3, #0 801c754: 64fb str r3, [r7, #76] ; 0x4c u16_t pos = 0; /* position in 'arg' data */ 801c756: 2300 movs r3, #0 801c758: f8a7 304a strh.w r3, [r7, #74] ; 0x4a u16_t queuelen; u8_t optlen; u8_t optflags = 0; 801c75c: 2300 movs r3, #0 801c75e: f887 302b strb.w r3, [r7, #43] ; 0x2b #if TCP_OVERSIZE u16_t oversize = 0; 801c762: 2300 movs r3, #0 801c764: 82fb strh r3, [r7, #22] u16_t oversize_used = 0; 801c766: 2300 movs r3, #0 801c768: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 #if TCP_OVERSIZE_DBGCHECK u16_t oversize_add = 0; 801c76c: 2300 movs r3, #0 801c76e: f8a7 305a strh.w r3, [r7, #90] ; 0x5a #endif /* TCP_OVERSIZE_DBGCHECK*/ #endif /* TCP_OVERSIZE */ u16_t extendlen = 0; 801c772: 2300 movs r3, #0 801c774: f8a7 305e strh.w r3, [r7, #94] ; 0x5e u16_t concat_chksummed = 0; #endif /* TCP_CHECKSUM_ON_COPY */ err_t err; u16_t mss_local; LWIP_ERROR("tcp_write: invalid pcb", pcb != NULL, return ERR_ARG); 801c778: 68fb ldr r3, [r7, #12] 801c77a: 2b00 cmp r3, #0 801c77c: d109 bne.n 801c792 801c77e: 4b9c ldr r3, [pc, #624] ; (801c9f0 ) 801c780: f44f 72cf mov.w r2, #414 ; 0x19e 801c784: 499b ldr r1, [pc, #620] ; (801c9f4 ) 801c786: 489c ldr r0, [pc, #624] ; (801c9f8 ) 801c788: f005 f8fe bl 8021988 801c78c: f06f 030f mvn.w r3, #15 801c790: e379 b.n 801ce86 /* don't allocate segments bigger than half the maximum window we ever received */ mss_local = LWIP_MIN(pcb->mss, TCPWND_MIN16(pcb->snd_wnd_max / 2)); 801c792: 68fb ldr r3, [r7, #12] 801c794: f8b3 3062 ldrh.w r3, [r3, #98] ; 0x62 801c798: 085b lsrs r3, r3, #1 801c79a: b29a uxth r2, r3 801c79c: 68fb ldr r3, [r7, #12] 801c79e: 8e5b ldrh r3, [r3, #50] ; 0x32 801c7a0: 4293 cmp r3, r2 801c7a2: bf28 it cs 801c7a4: 4613 movcs r3, r2 801c7a6: 853b strh r3, [r7, #40] ; 0x28 mss_local = mss_local ? mss_local : pcb->mss; 801c7a8: 8d3b ldrh r3, [r7, #40] ; 0x28 801c7aa: 2b00 cmp r3, #0 801c7ac: d102 bne.n 801c7b4 801c7ae: 68fb ldr r3, [r7, #12] 801c7b0: 8e5b ldrh r3, [r3, #50] ; 0x32 801c7b2: e000 b.n 801c7b6 801c7b4: 8d3b ldrh r3, [r7, #40] ; 0x28 801c7b6: 853b strh r3, [r7, #40] ; 0x28 apiflags |= TCP_WRITE_FLAG_COPY; #endif /* LWIP_NETIF_TX_SINGLE_PBUF */ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n", (void *)pcb, arg, len, (u16_t)apiflags)); LWIP_ERROR("tcp_write: arg == NULL (programmer violates API)", 801c7b8: 68bb ldr r3, [r7, #8] 801c7ba: 2b00 cmp r3, #0 801c7bc: d109 bne.n 801c7d2 801c7be: 4b8c ldr r3, [pc, #560] ; (801c9f0 ) 801c7c0: f240 12ad movw r2, #429 ; 0x1ad 801c7c4: 498d ldr r1, [pc, #564] ; (801c9fc ) 801c7c6: 488c ldr r0, [pc, #560] ; (801c9f8 ) 801c7c8: f005 f8de bl 8021988 801c7cc: f06f 030f mvn.w r3, #15 801c7d0: e359 b.n 801ce86 arg != NULL, return ERR_ARG;); err = tcp_write_checks(pcb, len); 801c7d2: 88fb ldrh r3, [r7, #6] 801c7d4: 4619 mov r1, r3 801c7d6: 68f8 ldr r0, [r7, #12] 801c7d8: f7ff ff2e bl 801c638 801c7dc: 4603 mov r3, r0 801c7de: f887 3027 strb.w r3, [r7, #39] ; 0x27 if (err != ERR_OK) { 801c7e2: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 801c7e6: 2b00 cmp r3, #0 801c7e8: d002 beq.n 801c7f0 return err; 801c7ea: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 801c7ee: e34a b.n 801ce86 } queuelen = pcb->snd_queuelen; 801c7f0: 68fb ldr r3, [r7, #12] 801c7f2: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801c7f6: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 /* ensure that segments can hold at least one data byte... */ mss_local = LWIP_MAX(mss_local, LWIP_TCP_OPT_LEN_TS + 1); } else #endif /* LWIP_TCP_TIMESTAMPS */ { optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); 801c7fa: 2300 movs r3, #0 801c7fc: f887 3026 strb.w r3, [r7, #38] ; 0x26 * * pos records progress as data is segmented. */ /* Find the tail of the unsent queue. */ if (pcb->unsent != NULL) { 801c800: 68fb ldr r3, [r7, #12] 801c802: 6edb ldr r3, [r3, #108] ; 0x6c 801c804: 2b00 cmp r3, #0 801c806: f000 8127 beq.w 801ca58 u16_t space; u16_t unsent_optlen; /* @todo: this could be sped up by keeping last_unsent in the pcb */ for (last_unsent = pcb->unsent; last_unsent->next != NULL; 801c80a: 68fb ldr r3, [r7, #12] 801c80c: 6edb ldr r3, [r3, #108] ; 0x6c 801c80e: 643b str r3, [r7, #64] ; 0x40 801c810: e002 b.n 801c818 last_unsent = last_unsent->next); 801c812: 6c3b ldr r3, [r7, #64] ; 0x40 801c814: 681b ldr r3, [r3, #0] 801c816: 643b str r3, [r7, #64] ; 0x40 for (last_unsent = pcb->unsent; last_unsent->next != NULL; 801c818: 6c3b ldr r3, [r7, #64] ; 0x40 801c81a: 681b ldr r3, [r3, #0] 801c81c: 2b00 cmp r3, #0 801c81e: d1f8 bne.n 801c812 /* Usable space at the end of the last unsent segment */ unsent_optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(last_unsent->flags, pcb); 801c820: 6c3b ldr r3, [r7, #64] ; 0x40 801c822: 7b1b ldrb r3, [r3, #12] 801c824: 009b lsls r3, r3, #2 801c826: b29b uxth r3, r3 801c828: f003 0304 and.w r3, r3, #4 801c82c: 84bb strh r3, [r7, #36] ; 0x24 LWIP_ASSERT("mss_local is too small", mss_local >= last_unsent->len + unsent_optlen); 801c82e: 8d3a ldrh r2, [r7, #40] ; 0x28 801c830: 6c3b ldr r3, [r7, #64] ; 0x40 801c832: 891b ldrh r3, [r3, #8] 801c834: 4619 mov r1, r3 801c836: 8cbb ldrh r3, [r7, #36] ; 0x24 801c838: 440b add r3, r1 801c83a: 429a cmp r2, r3 801c83c: da06 bge.n 801c84c 801c83e: 4b6c ldr r3, [pc, #432] ; (801c9f0 ) 801c840: f44f 72f3 mov.w r2, #486 ; 0x1e6 801c844: 496e ldr r1, [pc, #440] ; (801ca00 ) 801c846: 486c ldr r0, [pc, #432] ; (801c9f8 ) 801c848: f005 f89e bl 8021988 space = mss_local - (last_unsent->len + unsent_optlen); 801c84c: 6c3b ldr r3, [r7, #64] ; 0x40 801c84e: 891a ldrh r2, [r3, #8] 801c850: 8cbb ldrh r3, [r7, #36] ; 0x24 801c852: 4413 add r3, r2 801c854: b29b uxth r3, r3 801c856: 8d3a ldrh r2, [r7, #40] ; 0x28 801c858: 1ad3 subs r3, r2, r3 801c85a: f8a7 305c strh.w r3, [r7, #92] ; 0x5c * function. */ #if TCP_OVERSIZE #if TCP_OVERSIZE_DBGCHECK /* check that pcb->unsent_oversize matches last_unsent->oversize_left */ LWIP_ASSERT("unsent_oversize mismatch (pcb vs. last_unsent)", 801c85e: 68fb ldr r3, [r7, #12] 801c860: f8b3 2068 ldrh.w r2, [r3, #104] ; 0x68 801c864: 6c3b ldr r3, [r7, #64] ; 0x40 801c866: 895b ldrh r3, [r3, #10] 801c868: 429a cmp r2, r3 801c86a: d006 beq.n 801c87a 801c86c: 4b60 ldr r3, [pc, #384] ; (801c9f0 ) 801c86e: f240 12f3 movw r2, #499 ; 0x1f3 801c872: 4964 ldr r1, [pc, #400] ; (801ca04 ) 801c874: 4860 ldr r0, [pc, #384] ; (801c9f8 ) 801c876: f005 f887 bl 8021988 pcb->unsent_oversize == last_unsent->oversize_left); #endif /* TCP_OVERSIZE_DBGCHECK */ oversize = pcb->unsent_oversize; 801c87a: 68fb ldr r3, [r7, #12] 801c87c: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 801c880: 82fb strh r3, [r7, #22] if (oversize > 0) { 801c882: 8afb ldrh r3, [r7, #22] 801c884: 2b00 cmp r3, #0 801c886: d02e beq.n 801c8e6 LWIP_ASSERT("inconsistent oversize vs. space", oversize <= space); 801c888: 8afb ldrh r3, [r7, #22] 801c88a: f8b7 205c ldrh.w r2, [r7, #92] ; 0x5c 801c88e: 429a cmp r2, r3 801c890: d206 bcs.n 801c8a0 801c892: 4b57 ldr r3, [pc, #348] ; (801c9f0 ) 801c894: f44f 72fc mov.w r2, #504 ; 0x1f8 801c898: 495b ldr r1, [pc, #364] ; (801ca08 ) 801c89a: 4857 ldr r0, [pc, #348] ; (801c9f8 ) 801c89c: f005 f874 bl 8021988 seg = last_unsent; 801c8a0: 6c3b ldr r3, [r7, #64] ; 0x40 801c8a2: 657b str r3, [r7, #84] ; 0x54 oversize_used = LWIP_MIN(space, LWIP_MIN(oversize, len)); 801c8a4: 8afb ldrh r3, [r7, #22] 801c8a6: 88fa ldrh r2, [r7, #6] 801c8a8: 4293 cmp r3, r2 801c8aa: bf28 it cs 801c8ac: 4613 movcs r3, r2 801c8ae: b29b uxth r3, r3 801c8b0: f8b7 205c ldrh.w r2, [r7, #92] ; 0x5c 801c8b4: 4293 cmp r3, r2 801c8b6: bf28 it cs 801c8b8: 4613 movcs r3, r2 801c8ba: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 pos += oversize_used; 801c8be: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a 801c8c2: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 801c8c6: 4413 add r3, r2 801c8c8: f8a7 304a strh.w r3, [r7, #74] ; 0x4a oversize -= oversize_used; 801c8cc: 8afa ldrh r2, [r7, #22] 801c8ce: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 801c8d2: 1ad3 subs r3, r2, r3 801c8d4: b29b uxth r3, r3 801c8d6: 82fb strh r3, [r7, #22] space -= oversize_used; 801c8d8: f8b7 205c ldrh.w r2, [r7, #92] ; 0x5c 801c8dc: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 801c8e0: 1ad3 subs r3, r2, r3 801c8e2: f8a7 305c strh.w r3, [r7, #92] ; 0x5c } /* now we are either finished or oversize is zero */ LWIP_ASSERT("inconsistent oversize vs. len", (oversize == 0) || (pos == len)); 801c8e6: 8afb ldrh r3, [r7, #22] 801c8e8: 2b00 cmp r3, #0 801c8ea: d00b beq.n 801c904 801c8ec: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a 801c8f0: 88fb ldrh r3, [r7, #6] 801c8f2: 429a cmp r2, r3 801c8f4: d006 beq.n 801c904 801c8f6: 4b3e ldr r3, [pc, #248] ; (801c9f0 ) 801c8f8: f44f 7200 mov.w r2, #512 ; 0x200 801c8fc: 4943 ldr r1, [pc, #268] ; (801ca0c ) 801c8fe: 483e ldr r0, [pc, #248] ; (801c9f8 ) 801c900: f005 f842 bl 8021988 * * This phase is skipped for LWIP_NETIF_TX_SINGLE_PBUF as we could only execute * it after rexmit puts a segment from unacked to unsent and at this point, * oversize info is lost. */ if ((pos < len) && (space > 0) && (last_unsent->len > 0)) { 801c904: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a 801c908: 88fb ldrh r3, [r7, #6] 801c90a: 429a cmp r2, r3 801c90c: f080 8172 bcs.w 801cbf4 801c910: f8b7 305c ldrh.w r3, [r7, #92] ; 0x5c 801c914: 2b00 cmp r3, #0 801c916: f000 816d beq.w 801cbf4 801c91a: 6c3b ldr r3, [r7, #64] ; 0x40 801c91c: 891b ldrh r3, [r3, #8] 801c91e: 2b00 cmp r3, #0 801c920: f000 8168 beq.w 801cbf4 u16_t seglen = LWIP_MIN(space, len - pos); 801c924: 88fa ldrh r2, [r7, #6] 801c926: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a 801c92a: 1ad2 subs r2, r2, r3 801c92c: f8b7 305c ldrh.w r3, [r7, #92] ; 0x5c 801c930: 4293 cmp r3, r2 801c932: bfa8 it ge 801c934: 4613 movge r3, r2 801c936: 847b strh r3, [r7, #34] ; 0x22 seg = last_unsent; 801c938: 6c3b ldr r3, [r7, #64] ; 0x40 801c93a: 657b str r3, [r7, #84] ; 0x54 /* Create a pbuf with a copy or reference to seglen bytes. We * can use PBUF_RAW here since the data appears in the middle of * a segment. A header will never be prepended. */ if (apiflags & TCP_WRITE_FLAG_COPY) { 801c93c: 797b ldrb r3, [r7, #5] 801c93e: f003 0301 and.w r3, r3, #1 801c942: 2b00 cmp r3, #0 801c944: d02b beq.n 801c99e /* Data is copied */ if ((concat_p = tcp_pbuf_prealloc(PBUF_RAW, seglen, space, &oversize, pcb, apiflags, 1)) == NULL) { 801c946: f107 0016 add.w r0, r7, #22 801c94a: f8b7 205c ldrh.w r2, [r7, #92] ; 0x5c 801c94e: 8c79 ldrh r1, [r7, #34] ; 0x22 801c950: 2301 movs r3, #1 801c952: 9302 str r3, [sp, #8] 801c954: 797b ldrb r3, [r7, #5] 801c956: 9301 str r3, [sp, #4] 801c958: 68fb ldr r3, [r7, #12] 801c95a: 9300 str r3, [sp, #0] 801c95c: 4603 mov r3, r0 801c95e: 2000 movs r0, #0 801c960: f7ff fdf0 bl 801c544 801c964: 63f8 str r0, [r7, #60] ; 0x3c 801c966: 6bfb ldr r3, [r7, #60] ; 0x3c 801c968: 2b00 cmp r3, #0 801c96a: f000 825a beq.w 801ce22 ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); goto memerr; } #if TCP_OVERSIZE_DBGCHECK oversize_add = oversize; 801c96e: 8afb ldrh r3, [r7, #22] 801c970: f8a7 305a strh.w r3, [r7, #90] ; 0x5a #endif /* TCP_OVERSIZE_DBGCHECK */ TCP_DATA_COPY2(concat_p->payload, (const u8_t *)arg + pos, seglen, &concat_chksum, &concat_chksum_swapped); 801c974: 6bfb ldr r3, [r7, #60] ; 0x3c 801c976: 6858 ldr r0, [r3, #4] 801c978: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a 801c97c: 68ba ldr r2, [r7, #8] 801c97e: 4413 add r3, r2 801c980: 8c7a ldrh r2, [r7, #34] ; 0x22 801c982: 4619 mov r1, r3 801c984: f005 fa2f bl 8021de6 #if TCP_CHECKSUM_ON_COPY concat_chksummed += seglen; #endif /* TCP_CHECKSUM_ON_COPY */ queuelen += pbuf_clen(concat_p); 801c988: 6bf8 ldr r0, [r7, #60] ; 0x3c 801c98a: f7fb f943 bl 8017c14 801c98e: 4603 mov r3, r0 801c990: 461a mov r2, r3 801c992: f8b7 3048 ldrh.w r3, [r7, #72] ; 0x48 801c996: 4413 add r3, r2 801c998: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 801c99c: e055 b.n 801ca4a } else { /* Data is not copied */ /* If the last unsent pbuf is of type PBUF_ROM, try to extend it. */ struct pbuf *p; for (p = last_unsent->p; p->next != NULL; p = p->next); 801c99e: 6c3b ldr r3, [r7, #64] ; 0x40 801c9a0: 685b ldr r3, [r3, #4] 801c9a2: 63bb str r3, [r7, #56] ; 0x38 801c9a4: e002 b.n 801c9ac 801c9a6: 6bbb ldr r3, [r7, #56] ; 0x38 801c9a8: 681b ldr r3, [r3, #0] 801c9aa: 63bb str r3, [r7, #56] ; 0x38 801c9ac: 6bbb ldr r3, [r7, #56] ; 0x38 801c9ae: 681b ldr r3, [r3, #0] 801c9b0: 2b00 cmp r3, #0 801c9b2: d1f8 bne.n 801c9a6 if (((p->type_internal & (PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_DATA_VOLATILE)) == 0) && 801c9b4: 6bbb ldr r3, [r7, #56] ; 0x38 801c9b6: 7b1b ldrb r3, [r3, #12] 801c9b8: f003 03c0 and.w r3, r3, #192 ; 0xc0 801c9bc: 2b00 cmp r3, #0 801c9be: d129 bne.n 801ca14 (const u8_t *)p->payload + p->len == (const u8_t *)arg) { 801c9c0: 6bbb ldr r3, [r7, #56] ; 0x38 801c9c2: 685b ldr r3, [r3, #4] 801c9c4: 6bba ldr r2, [r7, #56] ; 0x38 801c9c6: 8952 ldrh r2, [r2, #10] 801c9c8: 4413 add r3, r2 if (((p->type_internal & (PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_DATA_VOLATILE)) == 0) && 801c9ca: 68ba ldr r2, [r7, #8] 801c9cc: 429a cmp r2, r3 801c9ce: d121 bne.n 801ca14 LWIP_ASSERT("tcp_write: ROM pbufs cannot be oversized", pos == 0); 801c9d0: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a 801c9d4: 2b00 cmp r3, #0 801c9d6: d006 beq.n 801c9e6 801c9d8: 4b05 ldr r3, [pc, #20] ; (801c9f0 ) 801c9da: f240 2231 movw r2, #561 ; 0x231 801c9de: 490c ldr r1, [pc, #48] ; (801ca10 ) 801c9e0: 4805 ldr r0, [pc, #20] ; (801c9f8 ) 801c9e2: f004 ffd1 bl 8021988 extendlen = seglen; 801c9e6: 8c7b ldrh r3, [r7, #34] ; 0x22 801c9e8: f8a7 305e strh.w r3, [r7, #94] ; 0x5e 801c9ec: e02d b.n 801ca4a 801c9ee: bf00 nop 801c9f0: 080257b8 .word 0x080257b8 801c9f4: 08025958 .word 0x08025958 801c9f8: 0802580c .word 0x0802580c 801c9fc: 08025970 .word 0x08025970 801ca00: 080259a4 .word 0x080259a4 801ca04: 080259bc .word 0x080259bc 801ca08: 080259ec .word 0x080259ec 801ca0c: 08025a0c .word 0x08025a0c 801ca10: 08025a2c .word 0x08025a2c } else { if ((concat_p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) { 801ca14: 8c7b ldrh r3, [r7, #34] ; 0x22 801ca16: 2201 movs r2, #1 801ca18: 4619 mov r1, r3 801ca1a: 2000 movs r0, #0 801ca1c: f7fa fd84 bl 8017528 801ca20: 63f8 str r0, [r7, #60] ; 0x3c 801ca22: 6bfb ldr r3, [r7, #60] ; 0x3c 801ca24: 2b00 cmp r3, #0 801ca26: f000 81fe beq.w 801ce26 LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for zero-copy pbuf\n")); goto memerr; } /* reference the non-volatile payload data */ ((struct pbuf_rom *)concat_p)->payload = (const u8_t *)arg + pos; 801ca2a: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a 801ca2e: 68ba ldr r2, [r7, #8] 801ca30: 441a add r2, r3 801ca32: 6bfb ldr r3, [r7, #60] ; 0x3c 801ca34: 605a str r2, [r3, #4] queuelen += pbuf_clen(concat_p); 801ca36: 6bf8 ldr r0, [r7, #60] ; 0x3c 801ca38: f7fb f8ec bl 8017c14 801ca3c: 4603 mov r3, r0 801ca3e: 461a mov r2, r3 801ca40: f8b7 3048 ldrh.w r3, [r7, #72] ; 0x48 801ca44: 4413 add r3, r2 801ca46: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 &concat_chksum, &concat_chksum_swapped); concat_chksummed += seglen; #endif /* TCP_CHECKSUM_ON_COPY */ } pos += seglen; 801ca4a: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a 801ca4e: 8c7b ldrh r3, [r7, #34] ; 0x22 801ca50: 4413 add r3, r2 801ca52: f8a7 304a strh.w r3, [r7, #74] ; 0x4a 801ca56: e0cd b.n 801cbf4 } #endif /* !LWIP_NETIF_TX_SINGLE_PBUF */ } else { #if TCP_OVERSIZE LWIP_ASSERT("unsent_oversize mismatch (pcb->unsent is NULL)", 801ca58: 68fb ldr r3, [r7, #12] 801ca5a: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 801ca5e: 2b00 cmp r3, #0 801ca60: f000 80c8 beq.w 801cbf4 801ca64: 4b72 ldr r3, [pc, #456] ; (801cc30 ) 801ca66: f240 224a movw r2, #586 ; 0x24a 801ca6a: 4972 ldr r1, [pc, #456] ; (801cc34 ) 801ca6c: 4872 ldr r0, [pc, #456] ; (801cc38 ) 801ca6e: f004 ff8b bl 8021988 * Phase 3: Create new segments. * * The new segments are chained together in the local 'queue' * variable, ready to be appended to pcb->unsent. */ while (pos < len) { 801ca72: e0bf b.n 801cbf4 struct pbuf *p; u16_t left = len - pos; 801ca74: 88fa ldrh r2, [r7, #6] 801ca76: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a 801ca7a: 1ad3 subs r3, r2, r3 801ca7c: 843b strh r3, [r7, #32] u16_t max_len = mss_local - optlen; 801ca7e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 801ca82: b29b uxth r3, r3 801ca84: 8d3a ldrh r2, [r7, #40] ; 0x28 801ca86: 1ad3 subs r3, r2, r3 801ca88: 83fb strh r3, [r7, #30] u16_t seglen = LWIP_MIN(left, max_len); 801ca8a: 8bfa ldrh r2, [r7, #30] 801ca8c: 8c3b ldrh r3, [r7, #32] 801ca8e: 4293 cmp r3, r2 801ca90: bf28 it cs 801ca92: 4613 movcs r3, r2 801ca94: 83bb strh r3, [r7, #28] #if TCP_CHECKSUM_ON_COPY u16_t chksum = 0; u8_t chksum_swapped = 0; #endif /* TCP_CHECKSUM_ON_COPY */ if (apiflags & TCP_WRITE_FLAG_COPY) { 801ca96: 797b ldrb r3, [r7, #5] 801ca98: f003 0301 and.w r3, r3, #1 801ca9c: 2b00 cmp r3, #0 801ca9e: d036 beq.n 801cb0e /* If copy is set, memory should be allocated and data copied * into pbuf */ if ((p = tcp_pbuf_prealloc(PBUF_TRANSPORT, seglen + optlen, mss_local, &oversize, pcb, apiflags, queue == NULL)) == NULL) { 801caa0: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 801caa4: b29a uxth r2, r3 801caa6: 8bbb ldrh r3, [r7, #28] 801caa8: 4413 add r3, r2 801caaa: b299 uxth r1, r3 801caac: 6cfb ldr r3, [r7, #76] ; 0x4c 801caae: 2b00 cmp r3, #0 801cab0: bf0c ite eq 801cab2: 2301 moveq r3, #1 801cab4: 2300 movne r3, #0 801cab6: b2db uxtb r3, r3 801cab8: f107 0016 add.w r0, r7, #22 801cabc: 8d3a ldrh r2, [r7, #40] ; 0x28 801cabe: 9302 str r3, [sp, #8] 801cac0: 797b ldrb r3, [r7, #5] 801cac2: 9301 str r3, [sp, #4] 801cac4: 68fb ldr r3, [r7, #12] 801cac6: 9300 str r3, [sp, #0] 801cac8: 4603 mov r3, r0 801caca: 2036 movs r0, #54 ; 0x36 801cacc: f7ff fd3a bl 801c544 801cad0: 6378 str r0, [r7, #52] ; 0x34 801cad2: 6b7b ldr r3, [r7, #52] ; 0x34 801cad4: 2b00 cmp r3, #0 801cad6: f000 81a8 beq.w 801ce2a LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); goto memerr; } LWIP_ASSERT("tcp_write: check that first pbuf can hold the complete seglen", 801cada: 6b7b ldr r3, [r7, #52] ; 0x34 801cadc: 895b ldrh r3, [r3, #10] 801cade: 8bba ldrh r2, [r7, #28] 801cae0: 429a cmp r2, r3 801cae2: d906 bls.n 801caf2 801cae4: 4b52 ldr r3, [pc, #328] ; (801cc30 ) 801cae6: f240 2266 movw r2, #614 ; 0x266 801caea: 4954 ldr r1, [pc, #336] ; (801cc3c ) 801caec: 4852 ldr r0, [pc, #328] ; (801cc38 ) 801caee: f004 ff4b bl 8021988 (p->len >= seglen)); TCP_DATA_COPY2((char *)p->payload + optlen, (const u8_t *)arg + pos, seglen, &chksum, &chksum_swapped); 801caf2: 6b7b ldr r3, [r7, #52] ; 0x34 801caf4: 685a ldr r2, [r3, #4] 801caf6: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 801cafa: 18d0 adds r0, r2, r3 801cafc: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a 801cb00: 68ba ldr r2, [r7, #8] 801cb02: 4413 add r3, r2 801cb04: 8bba ldrh r2, [r7, #28] 801cb06: 4619 mov r1, r3 801cb08: f005 f96d bl 8021de6 801cb0c: e02f b.n 801cb6e * sent out on the link (as it has to be ACKed by the remote * party) we can safely use PBUF_ROM instead of PBUF_REF here. */ struct pbuf *p2; #if TCP_OVERSIZE LWIP_ASSERT("oversize == 0", oversize == 0); 801cb0e: 8afb ldrh r3, [r7, #22] 801cb10: 2b00 cmp r3, #0 801cb12: d006 beq.n 801cb22 801cb14: 4b46 ldr r3, [pc, #280] ; (801cc30 ) 801cb16: f240 2271 movw r2, #625 ; 0x271 801cb1a: 4949 ldr r1, [pc, #292] ; (801cc40 ) 801cb1c: 4846 ldr r0, [pc, #280] ; (801cc38 ) 801cb1e: f004 ff33 bl 8021988 #endif /* TCP_OVERSIZE */ if ((p2 = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) { 801cb22: 8bbb ldrh r3, [r7, #28] 801cb24: 2201 movs r2, #1 801cb26: 4619 mov r1, r3 801cb28: 2036 movs r0, #54 ; 0x36 801cb2a: f7fa fcfd bl 8017528 801cb2e: 61b8 str r0, [r7, #24] 801cb30: 69bb ldr r3, [r7, #24] 801cb32: 2b00 cmp r3, #0 801cb34: f000 817b beq.w 801ce2e chksum_swapped = 1; chksum = SWAP_BYTES_IN_WORD(chksum); } #endif /* TCP_CHECKSUM_ON_COPY */ /* reference the non-volatile payload data */ ((struct pbuf_rom *)p2)->payload = (const u8_t *)arg + pos; 801cb38: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a 801cb3c: 68ba ldr r2, [r7, #8] 801cb3e: 441a add r2, r3 801cb40: 69bb ldr r3, [r7, #24] 801cb42: 605a str r2, [r3, #4] /* Second, allocate a pbuf for the headers. */ if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { 801cb44: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 801cb48: b29b uxth r3, r3 801cb4a: f44f 7220 mov.w r2, #640 ; 0x280 801cb4e: 4619 mov r1, r3 801cb50: 2036 movs r0, #54 ; 0x36 801cb52: f7fa fce9 bl 8017528 801cb56: 6378 str r0, [r7, #52] ; 0x34 801cb58: 6b7b ldr r3, [r7, #52] ; 0x34 801cb5a: 2b00 cmp r3, #0 801cb5c: d103 bne.n 801cb66 /* If allocation fails, we have to deallocate the data pbuf as * well. */ pbuf_free(p2); 801cb5e: 69b8 ldr r0, [r7, #24] 801cb60: f7fa ffca bl 8017af8 LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for header pbuf\n")); goto memerr; 801cb64: e166 b.n 801ce34 } /* Concatenate the headers and data pbufs together. */ pbuf_cat(p/*header*/, p2/*data*/); 801cb66: 69b9 ldr r1, [r7, #24] 801cb68: 6b78 ldr r0, [r7, #52] ; 0x34 801cb6a: f7fb f893 bl 8017c94 } queuelen += pbuf_clen(p); 801cb6e: 6b78 ldr r0, [r7, #52] ; 0x34 801cb70: f7fb f850 bl 8017c14 801cb74: 4603 mov r3, r0 801cb76: 461a mov r2, r3 801cb78: f8b7 3048 ldrh.w r3, [r7, #72] ; 0x48 801cb7c: 4413 add r3, r2 801cb7e: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 /* Now that there are more segments queued, we check again if the * length of the queue exceeds the configured maximum or * overflows. */ if (queuelen > LWIP_MIN(TCP_SND_QUEUELEN, TCP_SNDQUEUELEN_OVERFLOW)) { 801cb82: f8b7 3048 ldrh.w r3, [r7, #72] ; 0x48 801cb86: 2b10 cmp r3, #16 801cb88: d903 bls.n 801cb92 LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: queue too long %"U16_F" (%d)\n", queuelen, (int)TCP_SND_QUEUELEN)); pbuf_free(p); 801cb8a: 6b78 ldr r0, [r7, #52] ; 0x34 801cb8c: f7fa ffb4 bl 8017af8 goto memerr; 801cb90: e150 b.n 801ce34 } if ((seg = tcp_create_segment(pcb, p, 0, pcb->snd_lbb + pos, optflags)) == NULL) { 801cb92: 68fb ldr r3, [r7, #12] 801cb94: 6dda ldr r2, [r3, #92] ; 0x5c 801cb96: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a 801cb9a: 441a add r2, r3 801cb9c: f897 302b ldrb.w r3, [r7, #43] ; 0x2b 801cba0: 9300 str r3, [sp, #0] 801cba2: 4613 mov r3, r2 801cba4: 2200 movs r2, #0 801cba6: 6b79 ldr r1, [r7, #52] ; 0x34 801cba8: 68f8 ldr r0, [r7, #12] 801cbaa: f7ff fc2b bl 801c404 801cbae: 6578 str r0, [r7, #84] ; 0x54 801cbb0: 6d7b ldr r3, [r7, #84] ; 0x54 801cbb2: 2b00 cmp r3, #0 801cbb4: f000 813d beq.w 801ce32 goto memerr; } #if TCP_OVERSIZE_DBGCHECK seg->oversize_left = oversize; 801cbb8: 8afa ldrh r2, [r7, #22] 801cbba: 6d7b ldr r3, [r7, #84] ; 0x54 801cbbc: 815a strh r2, [r3, #10] seg->chksum_swapped = chksum_swapped; seg->flags |= TF_SEG_DATA_CHECKSUMMED; #endif /* TCP_CHECKSUM_ON_COPY */ /* first segment of to-be-queued data? */ if (queue == NULL) { 801cbbe: 6cfb ldr r3, [r7, #76] ; 0x4c 801cbc0: 2b00 cmp r3, #0 801cbc2: d102 bne.n 801cbca queue = seg; 801cbc4: 6d7b ldr r3, [r7, #84] ; 0x54 801cbc6: 64fb str r3, [r7, #76] ; 0x4c 801cbc8: e00c b.n 801cbe4 } else { /* Attach the segment to the end of the queued segments */ LWIP_ASSERT("prev_seg != NULL", prev_seg != NULL); 801cbca: 6d3b ldr r3, [r7, #80] ; 0x50 801cbcc: 2b00 cmp r3, #0 801cbce: d106 bne.n 801cbde 801cbd0: 4b17 ldr r3, [pc, #92] ; (801cc30 ) 801cbd2: f240 22ab movw r2, #683 ; 0x2ab 801cbd6: 491b ldr r1, [pc, #108] ; (801cc44 ) 801cbd8: 4817 ldr r0, [pc, #92] ; (801cc38 ) 801cbda: f004 fed5 bl 8021988 prev_seg->next = seg; 801cbde: 6d3b ldr r3, [r7, #80] ; 0x50 801cbe0: 6d7a ldr r2, [r7, #84] ; 0x54 801cbe2: 601a str r2, [r3, #0] } /* remember last segment of to-be-queued data for next iteration */ prev_seg = seg; 801cbe4: 6d7b ldr r3, [r7, #84] ; 0x54 801cbe6: 653b str r3, [r7, #80] ; 0x50 LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_write: queueing %"U32_F":%"U32_F"\n", lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg))); pos += seglen; 801cbe8: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a 801cbec: 8bbb ldrh r3, [r7, #28] 801cbee: 4413 add r3, r2 801cbf0: f8a7 304a strh.w r3, [r7, #74] ; 0x4a while (pos < len) { 801cbf4: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a 801cbf8: 88fb ldrh r3, [r7, #6] 801cbfa: 429a cmp r2, r3 801cbfc: f4ff af3a bcc.w 801ca74 /* * All three segmentation phases were successful. We can commit the * transaction. */ #if TCP_OVERSIZE_DBGCHECK if ((last_unsent != NULL) && (oversize_add != 0)) { 801cc00: 6c3b ldr r3, [r7, #64] ; 0x40 801cc02: 2b00 cmp r3, #0 801cc04: d00b beq.n 801cc1e 801cc06: f8b7 305a ldrh.w r3, [r7, #90] ; 0x5a 801cc0a: 2b00 cmp r3, #0 801cc0c: d007 beq.n 801cc1e last_unsent->oversize_left += oversize_add; 801cc0e: 6c3b ldr r3, [r7, #64] ; 0x40 801cc10: 895a ldrh r2, [r3, #10] 801cc12: f8b7 305a ldrh.w r3, [r7, #90] ; 0x5a 801cc16: 4413 add r3, r2 801cc18: b29a uxth r2, r3 801cc1a: 6c3b ldr r3, [r7, #64] ; 0x40 801cc1c: 815a strh r2, [r3, #10] /* * Phase 1: If data has been added to the preallocated tail of * last_unsent, we update the length fields of the pbuf chain. */ #if TCP_OVERSIZE if (oversize_used > 0) { 801cc1e: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 801cc22: 2b00 cmp r3, #0 801cc24: d052 beq.n 801cccc struct pbuf *p; /* Bump tot_len of whole chain, len of tail */ for (p = last_unsent->p; p; p = p->next) { 801cc26: 6c3b ldr r3, [r7, #64] ; 0x40 801cc28: 685b ldr r3, [r3, #4] 801cc2a: 633b str r3, [r7, #48] ; 0x30 801cc2c: e02e b.n 801cc8c 801cc2e: bf00 nop 801cc30: 080257b8 .word 0x080257b8 801cc34: 08025a58 .word 0x08025a58 801cc38: 0802580c .word 0x0802580c 801cc3c: 08025a88 .word 0x08025a88 801cc40: 08025ac8 .word 0x08025ac8 801cc44: 08025ad8 .word 0x08025ad8 p->tot_len += oversize_used; 801cc48: 6b3b ldr r3, [r7, #48] ; 0x30 801cc4a: 891a ldrh r2, [r3, #8] 801cc4c: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 801cc50: 4413 add r3, r2 801cc52: b29a uxth r2, r3 801cc54: 6b3b ldr r3, [r7, #48] ; 0x30 801cc56: 811a strh r2, [r3, #8] if (p->next == NULL) { 801cc58: 6b3b ldr r3, [r7, #48] ; 0x30 801cc5a: 681b ldr r3, [r3, #0] 801cc5c: 2b00 cmp r3, #0 801cc5e: d112 bne.n 801cc86 TCP_DATA_COPY((char *)p->payload + p->len, arg, oversize_used, last_unsent); 801cc60: 6b3b ldr r3, [r7, #48] ; 0x30 801cc62: 685b ldr r3, [r3, #4] 801cc64: 6b3a ldr r2, [r7, #48] ; 0x30 801cc66: 8952 ldrh r2, [r2, #10] 801cc68: 4413 add r3, r2 801cc6a: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46 801cc6e: 68b9 ldr r1, [r7, #8] 801cc70: 4618 mov r0, r3 801cc72: f005 f8b8 bl 8021de6 p->len += oversize_used; 801cc76: 6b3b ldr r3, [r7, #48] ; 0x30 801cc78: 895a ldrh r2, [r3, #10] 801cc7a: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 801cc7e: 4413 add r3, r2 801cc80: b29a uxth r2, r3 801cc82: 6b3b ldr r3, [r7, #48] ; 0x30 801cc84: 815a strh r2, [r3, #10] for (p = last_unsent->p; p; p = p->next) { 801cc86: 6b3b ldr r3, [r7, #48] ; 0x30 801cc88: 681b ldr r3, [r3, #0] 801cc8a: 633b str r3, [r7, #48] ; 0x30 801cc8c: 6b3b ldr r3, [r7, #48] ; 0x30 801cc8e: 2b00 cmp r3, #0 801cc90: d1da bne.n 801cc48 } } last_unsent->len += oversize_used; 801cc92: 6c3b ldr r3, [r7, #64] ; 0x40 801cc94: 891a ldrh r2, [r3, #8] 801cc96: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 801cc9a: 4413 add r3, r2 801cc9c: b29a uxth r2, r3 801cc9e: 6c3b ldr r3, [r7, #64] ; 0x40 801cca0: 811a strh r2, [r3, #8] #if TCP_OVERSIZE_DBGCHECK LWIP_ASSERT("last_unsent->oversize_left >= oversize_used", 801cca2: 6c3b ldr r3, [r7, #64] ; 0x40 801cca4: 895b ldrh r3, [r3, #10] 801cca6: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46 801ccaa: 429a cmp r2, r3 801ccac: d906 bls.n 801ccbc 801ccae: 4b78 ldr r3, [pc, #480] ; (801ce90 ) 801ccb0: f240 22d3 movw r2, #723 ; 0x2d3 801ccb4: 4977 ldr r1, [pc, #476] ; (801ce94 ) 801ccb6: 4878 ldr r0, [pc, #480] ; (801ce98 ) 801ccb8: f004 fe66 bl 8021988 last_unsent->oversize_left >= oversize_used); last_unsent->oversize_left -= oversize_used; 801ccbc: 6c3b ldr r3, [r7, #64] ; 0x40 801ccbe: 895a ldrh r2, [r3, #10] 801ccc0: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 801ccc4: 1ad3 subs r3, r2, r3 801ccc6: b29a uxth r2, r3 801ccc8: 6c3b ldr r3, [r7, #64] ; 0x40 801ccca: 815a strh r2, [r3, #10] #endif /* TCP_OVERSIZE_DBGCHECK */ } pcb->unsent_oversize = oversize; 801cccc: 8afa ldrh r2, [r7, #22] 801ccce: 68fb ldr r3, [r7, #12] 801ccd0: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 /* * Phase 2: concat_p can be concatenated onto last_unsent->p, unless we * determined that the last ROM pbuf can be extended to include the new data. */ if (concat_p != NULL) { 801ccd4: 6bfb ldr r3, [r7, #60] ; 0x3c 801ccd6: 2b00 cmp r3, #0 801ccd8: d018 beq.n 801cd0c LWIP_ASSERT("tcp_write: cannot concatenate when pcb->unsent is empty", 801ccda: 6c3b ldr r3, [r7, #64] ; 0x40 801ccdc: 2b00 cmp r3, #0 801ccde: d106 bne.n 801ccee 801cce0: 4b6b ldr r3, [pc, #428] ; (801ce90 ) 801cce2: f44f 7238 mov.w r2, #736 ; 0x2e0 801cce6: 496d ldr r1, [pc, #436] ; (801ce9c ) 801cce8: 486b ldr r0, [pc, #428] ; (801ce98 ) 801ccea: f004 fe4d bl 8021988 (last_unsent != NULL)); pbuf_cat(last_unsent->p, concat_p); 801ccee: 6c3b ldr r3, [r7, #64] ; 0x40 801ccf0: 685b ldr r3, [r3, #4] 801ccf2: 6bf9 ldr r1, [r7, #60] ; 0x3c 801ccf4: 4618 mov r0, r3 801ccf6: f7fa ffcd bl 8017c94 last_unsent->len += concat_p->tot_len; 801ccfa: 6c3b ldr r3, [r7, #64] ; 0x40 801ccfc: 891a ldrh r2, [r3, #8] 801ccfe: 6bfb ldr r3, [r7, #60] ; 0x3c 801cd00: 891b ldrh r3, [r3, #8] 801cd02: 4413 add r3, r2 801cd04: b29a uxth r2, r3 801cd06: 6c3b ldr r3, [r7, #64] ; 0x40 801cd08: 811a strh r2, [r3, #8] 801cd0a: e03c b.n 801cd86 } else if (extendlen > 0) { 801cd0c: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e 801cd10: 2b00 cmp r3, #0 801cd12: d038 beq.n 801cd86 struct pbuf *p; LWIP_ASSERT("tcp_write: extension of reference requires reference", 801cd14: 6c3b ldr r3, [r7, #64] ; 0x40 801cd16: 2b00 cmp r3, #0 801cd18: d003 beq.n 801cd22 801cd1a: 6c3b ldr r3, [r7, #64] ; 0x40 801cd1c: 685b ldr r3, [r3, #4] 801cd1e: 2b00 cmp r3, #0 801cd20: d106 bne.n 801cd30 801cd22: 4b5b ldr r3, [pc, #364] ; (801ce90 ) 801cd24: f240 22e6 movw r2, #742 ; 0x2e6 801cd28: 495d ldr r1, [pc, #372] ; (801cea0 ) 801cd2a: 485b ldr r0, [pc, #364] ; (801ce98 ) 801cd2c: f004 fe2c bl 8021988 last_unsent != NULL && last_unsent->p != NULL); for (p = last_unsent->p; p->next != NULL; p = p->next) { 801cd30: 6c3b ldr r3, [r7, #64] ; 0x40 801cd32: 685b ldr r3, [r3, #4] 801cd34: 62fb str r3, [r7, #44] ; 0x2c 801cd36: e00a b.n 801cd4e p->tot_len += extendlen; 801cd38: 6afb ldr r3, [r7, #44] ; 0x2c 801cd3a: 891a ldrh r2, [r3, #8] 801cd3c: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e 801cd40: 4413 add r3, r2 801cd42: b29a uxth r2, r3 801cd44: 6afb ldr r3, [r7, #44] ; 0x2c 801cd46: 811a strh r2, [r3, #8] for (p = last_unsent->p; p->next != NULL; p = p->next) { 801cd48: 6afb ldr r3, [r7, #44] ; 0x2c 801cd4a: 681b ldr r3, [r3, #0] 801cd4c: 62fb str r3, [r7, #44] ; 0x2c 801cd4e: 6afb ldr r3, [r7, #44] ; 0x2c 801cd50: 681b ldr r3, [r3, #0] 801cd52: 2b00 cmp r3, #0 801cd54: d1f0 bne.n 801cd38 } p->tot_len += extendlen; 801cd56: 6afb ldr r3, [r7, #44] ; 0x2c 801cd58: 891a ldrh r2, [r3, #8] 801cd5a: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e 801cd5e: 4413 add r3, r2 801cd60: b29a uxth r2, r3 801cd62: 6afb ldr r3, [r7, #44] ; 0x2c 801cd64: 811a strh r2, [r3, #8] p->len += extendlen; 801cd66: 6afb ldr r3, [r7, #44] ; 0x2c 801cd68: 895a ldrh r2, [r3, #10] 801cd6a: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e 801cd6e: 4413 add r3, r2 801cd70: b29a uxth r2, r3 801cd72: 6afb ldr r3, [r7, #44] ; 0x2c 801cd74: 815a strh r2, [r3, #10] last_unsent->len += extendlen; 801cd76: 6c3b ldr r3, [r7, #64] ; 0x40 801cd78: 891a ldrh r2, [r3, #8] 801cd7a: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e 801cd7e: 4413 add r3, r2 801cd80: b29a uxth r2, r3 801cd82: 6c3b ldr r3, [r7, #64] ; 0x40 801cd84: 811a strh r2, [r3, #8] /* * Phase 3: Append queue to pcb->unsent. Queue may be NULL, but that * is harmless */ if (last_unsent == NULL) { 801cd86: 6c3b ldr r3, [r7, #64] ; 0x40 801cd88: 2b00 cmp r3, #0 801cd8a: d103 bne.n 801cd94 pcb->unsent = queue; 801cd8c: 68fb ldr r3, [r7, #12] 801cd8e: 6cfa ldr r2, [r7, #76] ; 0x4c 801cd90: 66da str r2, [r3, #108] ; 0x6c 801cd92: e002 b.n 801cd9a } else { last_unsent->next = queue; 801cd94: 6c3b ldr r3, [r7, #64] ; 0x40 801cd96: 6cfa ldr r2, [r7, #76] ; 0x4c 801cd98: 601a str r2, [r3, #0] } /* * Finally update the pcb state. */ pcb->snd_lbb += len; 801cd9a: 68fb ldr r3, [r7, #12] 801cd9c: 6dda ldr r2, [r3, #92] ; 0x5c 801cd9e: 88fb ldrh r3, [r7, #6] 801cda0: 441a add r2, r3 801cda2: 68fb ldr r3, [r7, #12] 801cda4: 65da str r2, [r3, #92] ; 0x5c pcb->snd_buf -= len; 801cda6: 68fb ldr r3, [r7, #12] 801cda8: f8b3 2064 ldrh.w r2, [r3, #100] ; 0x64 801cdac: 88fb ldrh r3, [r7, #6] 801cdae: 1ad3 subs r3, r2, r3 801cdb0: b29a uxth r2, r3 801cdb2: 68fb ldr r3, [r7, #12] 801cdb4: f8a3 2064 strh.w r2, [r3, #100] ; 0x64 pcb->snd_queuelen = queuelen; 801cdb8: 68fb ldr r3, [r7, #12] 801cdba: f8b7 2048 ldrh.w r2, [r7, #72] ; 0x48 801cdbe: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); if (pcb->snd_queuelen != 0) { 801cdc2: 68fb ldr r3, [r7, #12] 801cdc4: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801cdc8: 2b00 cmp r3, #0 801cdca: d00e beq.n 801cdea LWIP_ASSERT("tcp_write: valid queue length", 801cdcc: 68fb ldr r3, [r7, #12] 801cdce: 6f1b ldr r3, [r3, #112] ; 0x70 801cdd0: 2b00 cmp r3, #0 801cdd2: d10a bne.n 801cdea 801cdd4: 68fb ldr r3, [r7, #12] 801cdd6: 6edb ldr r3, [r3, #108] ; 0x6c 801cdd8: 2b00 cmp r3, #0 801cdda: d106 bne.n 801cdea 801cddc: 4b2c ldr r3, [pc, #176] ; (801ce90 ) 801cdde: f240 3212 movw r2, #786 ; 0x312 801cde2: 4930 ldr r1, [pc, #192] ; (801cea4 ) 801cde4: 482c ldr r0, [pc, #176] ; (801ce98 ) 801cde6: f004 fdcf bl 8021988 pcb->unacked != NULL || pcb->unsent != NULL); } /* Set the PSH flag in the last segment that we enqueued. */ if (seg != NULL && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE) == 0)) { 801cdea: 6d7b ldr r3, [r7, #84] ; 0x54 801cdec: 2b00 cmp r3, #0 801cdee: d016 beq.n 801ce1e 801cdf0: 6d7b ldr r3, [r7, #84] ; 0x54 801cdf2: 691b ldr r3, [r3, #16] 801cdf4: 2b00 cmp r3, #0 801cdf6: d012 beq.n 801ce1e 801cdf8: 797b ldrb r3, [r7, #5] 801cdfa: f003 0302 and.w r3, r3, #2 801cdfe: 2b00 cmp r3, #0 801ce00: d10d bne.n 801ce1e TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); 801ce02: 6d7b ldr r3, [r7, #84] ; 0x54 801ce04: 691b ldr r3, [r3, #16] 801ce06: 899b ldrh r3, [r3, #12] 801ce08: b29c uxth r4, r3 801ce0a: 2008 movs r0, #8 801ce0c: f7f9 f898 bl 8015f40 801ce10: 4603 mov r3, r0 801ce12: 461a mov r2, r3 801ce14: 6d7b ldr r3, [r7, #84] ; 0x54 801ce16: 691b ldr r3, [r3, #16] 801ce18: 4322 orrs r2, r4 801ce1a: b292 uxth r2, r2 801ce1c: 819a strh r2, [r3, #12] } return ERR_OK; 801ce1e: 2300 movs r3, #0 801ce20: e031 b.n 801ce86 goto memerr; 801ce22: bf00 nop 801ce24: e006 b.n 801ce34 goto memerr; 801ce26: bf00 nop 801ce28: e004 b.n 801ce34 goto memerr; 801ce2a: bf00 nop 801ce2c: e002 b.n 801ce34 goto memerr; 801ce2e: bf00 nop 801ce30: e000 b.n 801ce34 goto memerr; 801ce32: bf00 nop memerr: tcp_set_flags(pcb, TF_NAGLEMEMERR); 801ce34: 68fb ldr r3, [r7, #12] 801ce36: 8b5b ldrh r3, [r3, #26] 801ce38: f043 0380 orr.w r3, r3, #128 ; 0x80 801ce3c: b29a uxth r2, r3 801ce3e: 68fb ldr r3, [r7, #12] 801ce40: 835a strh r2, [r3, #26] TCP_STATS_INC(tcp.memerr); if (concat_p != NULL) { 801ce42: 6bfb ldr r3, [r7, #60] ; 0x3c 801ce44: 2b00 cmp r3, #0 801ce46: d002 beq.n 801ce4e pbuf_free(concat_p); 801ce48: 6bf8 ldr r0, [r7, #60] ; 0x3c 801ce4a: f7fa fe55 bl 8017af8 } if (queue != NULL) { 801ce4e: 6cfb ldr r3, [r7, #76] ; 0x4c 801ce50: 2b00 cmp r3, #0 801ce52: d002 beq.n 801ce5a tcp_segs_free(queue); 801ce54: 6cf8 ldr r0, [r7, #76] ; 0x4c 801ce56: f7fc fb0f bl 8019478 } if (pcb->snd_queuelen != 0) { 801ce5a: 68fb ldr r3, [r7, #12] 801ce5c: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801ce60: 2b00 cmp r3, #0 801ce62: d00e beq.n 801ce82 LWIP_ASSERT("tcp_write: valid queue length", pcb->unacked != NULL || 801ce64: 68fb ldr r3, [r7, #12] 801ce66: 6f1b ldr r3, [r3, #112] ; 0x70 801ce68: 2b00 cmp r3, #0 801ce6a: d10a bne.n 801ce82 801ce6c: 68fb ldr r3, [r7, #12] 801ce6e: 6edb ldr r3, [r3, #108] ; 0x6c 801ce70: 2b00 cmp r3, #0 801ce72: d106 bne.n 801ce82 801ce74: 4b06 ldr r3, [pc, #24] ; (801ce90 ) 801ce76: f240 3227 movw r2, #807 ; 0x327 801ce7a: 490a ldr r1, [pc, #40] ; (801cea4 ) 801ce7c: 4806 ldr r0, [pc, #24] ; (801ce98 ) 801ce7e: f004 fd83 bl 8021988 pcb->unsent != NULL); } LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_write: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); return ERR_MEM; 801ce82: f04f 33ff mov.w r3, #4294967295 } 801ce86: 4618 mov r0, r3 801ce88: 3764 adds r7, #100 ; 0x64 801ce8a: 46bd mov sp, r7 801ce8c: bd90 pop {r4, r7, pc} 801ce8e: bf00 nop 801ce90: 080257b8 .word 0x080257b8 801ce94: 08025aec .word 0x08025aec 801ce98: 0802580c .word 0x0802580c 801ce9c: 08025b18 .word 0x08025b18 801cea0: 08025b50 .word 0x08025b50 801cea4: 08025b88 .word 0x08025b88 0801cea8 : * @param pcb the tcp_pcb for which to split the unsent head * @param split the amount of payload to remain in the head */ err_t tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split) { 801cea8: b590 push {r4, r7, lr} 801ceaa: b08b sub sp, #44 ; 0x2c 801ceac: af02 add r7, sp, #8 801ceae: 6078 str r0, [r7, #4] 801ceb0: 460b mov r3, r1 801ceb2: 807b strh r3, [r7, #2] struct tcp_seg *seg = NULL, *useg = NULL; 801ceb4: 2300 movs r3, #0 801ceb6: 61bb str r3, [r7, #24] 801ceb8: 2300 movs r3, #0 801ceba: 617b str r3, [r7, #20] struct pbuf *p = NULL; 801cebc: 2300 movs r3, #0 801cebe: 613b str r3, [r7, #16] u16_t chksum = 0; u8_t chksum_swapped = 0; struct pbuf *q; #endif /* TCP_CHECKSUM_ON_COPY */ LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL); 801cec0: 687b ldr r3, [r7, #4] 801cec2: 2b00 cmp r3, #0 801cec4: d106 bne.n 801ced4 801cec6: 4b97 ldr r3, [pc, #604] ; (801d124 ) 801cec8: f240 324b movw r2, #843 ; 0x34b 801cecc: 4996 ldr r1, [pc, #600] ; (801d128 ) 801cece: 4897 ldr r0, [pc, #604] ; (801d12c ) 801ced0: f004 fd5a bl 8021988 useg = pcb->unsent; 801ced4: 687b ldr r3, [r7, #4] 801ced6: 6edb ldr r3, [r3, #108] ; 0x6c 801ced8: 617b str r3, [r7, #20] if (useg == NULL) { 801ceda: 697b ldr r3, [r7, #20] 801cedc: 2b00 cmp r3, #0 801cede: d102 bne.n 801cee6 return ERR_MEM; 801cee0: f04f 33ff mov.w r3, #4294967295 801cee4: e119 b.n 801d11a } if (split == 0) { 801cee6: 887b ldrh r3, [r7, #2] 801cee8: 2b00 cmp r3, #0 801ceea: d109 bne.n 801cf00 LWIP_ASSERT("Can't split segment into length 0", 0); 801ceec: 4b8d ldr r3, [pc, #564] ; (801d124 ) 801ceee: f240 3253 movw r2, #851 ; 0x353 801cef2: 498f ldr r1, [pc, #572] ; (801d130 ) 801cef4: 488d ldr r0, [pc, #564] ; (801d12c ) 801cef6: f004 fd47 bl 8021988 return ERR_VAL; 801cefa: f06f 0305 mvn.w r3, #5 801cefe: e10c b.n 801d11a } if (useg->len <= split) { 801cf00: 697b ldr r3, [r7, #20] 801cf02: 891b ldrh r3, [r3, #8] 801cf04: 887a ldrh r2, [r7, #2] 801cf06: 429a cmp r2, r3 801cf08: d301 bcc.n 801cf0e return ERR_OK; 801cf0a: 2300 movs r3, #0 801cf0c: e105 b.n 801d11a } LWIP_ASSERT("split <= mss", split <= pcb->mss); 801cf0e: 687b ldr r3, [r7, #4] 801cf10: 8e5b ldrh r3, [r3, #50] ; 0x32 801cf12: 887a ldrh r2, [r7, #2] 801cf14: 429a cmp r2, r3 801cf16: d906 bls.n 801cf26 801cf18: 4b82 ldr r3, [pc, #520] ; (801d124 ) 801cf1a: f240 325b movw r2, #859 ; 0x35b 801cf1e: 4985 ldr r1, [pc, #532] ; (801d134 ) 801cf20: 4882 ldr r0, [pc, #520] ; (801d12c ) 801cf22: f004 fd31 bl 8021988 LWIP_ASSERT("useg->len > 0", useg->len > 0); 801cf26: 697b ldr r3, [r7, #20] 801cf28: 891b ldrh r3, [r3, #8] 801cf2a: 2b00 cmp r3, #0 801cf2c: d106 bne.n 801cf3c 801cf2e: 4b7d ldr r3, [pc, #500] ; (801d124 ) 801cf30: f44f 7257 mov.w r2, #860 ; 0x35c 801cf34: 4980 ldr r1, [pc, #512] ; (801d138 ) 801cf36: 487d ldr r0, [pc, #500] ; (801d12c ) 801cf38: f004 fd26 bl 8021988 * to split this packet so we may actually exceed the max value by * one! */ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen)); optflags = useg->flags; 801cf3c: 697b ldr r3, [r7, #20] 801cf3e: 7b1b ldrb r3, [r3, #12] 801cf40: 73fb strb r3, [r7, #15] #if TCP_CHECKSUM_ON_COPY /* Remove since checksum is not stored until after tcp_create_segment() */ optflags &= ~TF_SEG_DATA_CHECKSUMMED; #endif /* TCP_CHECKSUM_ON_COPY */ optlen = LWIP_TCP_OPT_LENGTH(optflags); 801cf42: 7bfb ldrb r3, [r7, #15] 801cf44: 009b lsls r3, r3, #2 801cf46: b2db uxtb r3, r3 801cf48: f003 0304 and.w r3, r3, #4 801cf4c: 73bb strb r3, [r7, #14] remainder = useg->len - split; 801cf4e: 697b ldr r3, [r7, #20] 801cf50: 891a ldrh r2, [r3, #8] 801cf52: 887b ldrh r3, [r7, #2] 801cf54: 1ad3 subs r3, r2, r3 801cf56: 81bb strh r3, [r7, #12] /* Create new pbuf for the remainder of the split */ p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM); 801cf58: 7bbb ldrb r3, [r7, #14] 801cf5a: b29a uxth r2, r3 801cf5c: 89bb ldrh r3, [r7, #12] 801cf5e: 4413 add r3, r2 801cf60: b29b uxth r3, r3 801cf62: f44f 7220 mov.w r2, #640 ; 0x280 801cf66: 4619 mov r1, r3 801cf68: 2036 movs r0, #54 ; 0x36 801cf6a: f7fa fadd bl 8017528 801cf6e: 6138 str r0, [r7, #16] if (p == NULL) { 801cf70: 693b ldr r3, [r7, #16] 801cf72: 2b00 cmp r3, #0 801cf74: f000 80ba beq.w 801d0ec ("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder)); goto memerr; } /* Offset into the original pbuf is past TCP/IP headers, options, and split amount */ offset = useg->p->tot_len - useg->len + split; 801cf78: 697b ldr r3, [r7, #20] 801cf7a: 685b ldr r3, [r3, #4] 801cf7c: 891a ldrh r2, [r3, #8] 801cf7e: 697b ldr r3, [r7, #20] 801cf80: 891b ldrh r3, [r3, #8] 801cf82: 1ad3 subs r3, r2, r3 801cf84: b29a uxth r2, r3 801cf86: 887b ldrh r3, [r7, #2] 801cf88: 4413 add r3, r2 801cf8a: 817b strh r3, [r7, #10] /* Copy remainder into new pbuf, headers and options will not be filled out */ if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) { 801cf8c: 697b ldr r3, [r7, #20] 801cf8e: 6858 ldr r0, [r3, #4] 801cf90: 693b ldr r3, [r7, #16] 801cf92: 685a ldr r2, [r3, #4] 801cf94: 7bbb ldrb r3, [r7, #14] 801cf96: 18d1 adds r1, r2, r3 801cf98: 897b ldrh r3, [r7, #10] 801cf9a: 89ba ldrh r2, [r7, #12] 801cf9c: f7fa ffa2 bl 8017ee4 801cfa0: 4603 mov r3, r0 801cfa2: 461a mov r2, r3 801cfa4: 89bb ldrh r3, [r7, #12] 801cfa6: 4293 cmp r3, r2 801cfa8: f040 80a2 bne.w 801d0f0 #endif /* TCP_CHECKSUM_ON_COPY */ /* Options are created when calling tcp_output() */ /* Migrate flags from original segment */ split_flags = TCPH_FLAGS(useg->tcphdr); 801cfac: 697b ldr r3, [r7, #20] 801cfae: 691b ldr r3, [r3, #16] 801cfb0: 899b ldrh r3, [r3, #12] 801cfb2: b29b uxth r3, r3 801cfb4: 4618 mov r0, r3 801cfb6: f7f8 ffc3 bl 8015f40 801cfba: 4603 mov r3, r0 801cfbc: b2db uxtb r3, r3 801cfbe: f003 033f and.w r3, r3, #63 ; 0x3f 801cfc2: 77fb strb r3, [r7, #31] remainder_flags = 0; /* ACK added in tcp_output() */ 801cfc4: 2300 movs r3, #0 801cfc6: 77bb strb r3, [r7, #30] if (split_flags & TCP_PSH) { 801cfc8: 7ffb ldrb r3, [r7, #31] 801cfca: f003 0308 and.w r3, r3, #8 801cfce: 2b00 cmp r3, #0 801cfd0: d007 beq.n 801cfe2 split_flags &= ~TCP_PSH; 801cfd2: 7ffb ldrb r3, [r7, #31] 801cfd4: f023 0308 bic.w r3, r3, #8 801cfd8: 77fb strb r3, [r7, #31] remainder_flags |= TCP_PSH; 801cfda: 7fbb ldrb r3, [r7, #30] 801cfdc: f043 0308 orr.w r3, r3, #8 801cfe0: 77bb strb r3, [r7, #30] } if (split_flags & TCP_FIN) { 801cfe2: 7ffb ldrb r3, [r7, #31] 801cfe4: f003 0301 and.w r3, r3, #1 801cfe8: 2b00 cmp r3, #0 801cfea: d007 beq.n 801cffc split_flags &= ~TCP_FIN; 801cfec: 7ffb ldrb r3, [r7, #31] 801cfee: f023 0301 bic.w r3, r3, #1 801cff2: 77fb strb r3, [r7, #31] remainder_flags |= TCP_FIN; 801cff4: 7fbb ldrb r3, [r7, #30] 801cff6: f043 0301 orr.w r3, r3, #1 801cffa: 77bb strb r3, [r7, #30] } /* SYN should be left on split, RST should not be present with data */ seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags); 801cffc: 697b ldr r3, [r7, #20] 801cffe: 691b ldr r3, [r3, #16] 801d000: 685b ldr r3, [r3, #4] 801d002: 4618 mov r0, r3 801d004: f7f8 ffb1 bl 8015f6a 801d008: 4602 mov r2, r0 801d00a: 887b ldrh r3, [r7, #2] 801d00c: 18d1 adds r1, r2, r3 801d00e: 7fba ldrb r2, [r7, #30] 801d010: 7bfb ldrb r3, [r7, #15] 801d012: 9300 str r3, [sp, #0] 801d014: 460b mov r3, r1 801d016: 6939 ldr r1, [r7, #16] 801d018: 6878 ldr r0, [r7, #4] 801d01a: f7ff f9f3 bl 801c404 801d01e: 61b8 str r0, [r7, #24] if (seg == NULL) { 801d020: 69bb ldr r3, [r7, #24] 801d022: 2b00 cmp r3, #0 801d024: d066 beq.n 801d0f4 seg->chksum_swapped = chksum_swapped; seg->flags |= TF_SEG_DATA_CHECKSUMMED; #endif /* TCP_CHECKSUM_ON_COPY */ /* Remove this segment from the queue since trimming it may free pbufs */ pcb->snd_queuelen -= pbuf_clen(useg->p); 801d026: 697b ldr r3, [r7, #20] 801d028: 685b ldr r3, [r3, #4] 801d02a: 4618 mov r0, r3 801d02c: f7fa fdf2 bl 8017c14 801d030: 4603 mov r3, r0 801d032: 461a mov r2, r3 801d034: 687b ldr r3, [r7, #4] 801d036: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801d03a: 1a9b subs r3, r3, r2 801d03c: b29a uxth r2, r3 801d03e: 687b ldr r3, [r7, #4] 801d040: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 /* Trim the original pbuf into our split size. At this point our remainder segment must be setup successfully because we are modifying the original segment */ pbuf_realloc(useg->p, useg->p->tot_len - remainder); 801d044: 697b ldr r3, [r7, #20] 801d046: 6858 ldr r0, [r3, #4] 801d048: 697b ldr r3, [r7, #20] 801d04a: 685b ldr r3, [r3, #4] 801d04c: 891a ldrh r2, [r3, #8] 801d04e: 89bb ldrh r3, [r7, #12] 801d050: 1ad3 subs r3, r2, r3 801d052: b29b uxth r3, r3 801d054: 4619 mov r1, r3 801d056: f7fa fbc9 bl 80177ec useg->len -= remainder; 801d05a: 697b ldr r3, [r7, #20] 801d05c: 891a ldrh r2, [r3, #8] 801d05e: 89bb ldrh r3, [r7, #12] 801d060: 1ad3 subs r3, r2, r3 801d062: b29a uxth r2, r3 801d064: 697b ldr r3, [r7, #20] 801d066: 811a strh r2, [r3, #8] TCPH_SET_FLAG(useg->tcphdr, split_flags); 801d068: 697b ldr r3, [r7, #20] 801d06a: 691b ldr r3, [r3, #16] 801d06c: 899b ldrh r3, [r3, #12] 801d06e: b29c uxth r4, r3 801d070: 7ffb ldrb r3, [r7, #31] 801d072: b29b uxth r3, r3 801d074: 4618 mov r0, r3 801d076: f7f8 ff63 bl 8015f40 801d07a: 4603 mov r3, r0 801d07c: 461a mov r2, r3 801d07e: 697b ldr r3, [r7, #20] 801d080: 691b ldr r3, [r3, #16] 801d082: 4322 orrs r2, r4 801d084: b292 uxth r2, r2 801d086: 819a strh r2, [r3, #12] #if TCP_OVERSIZE_DBGCHECK /* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */ useg->oversize_left = 0; 801d088: 697b ldr r3, [r7, #20] 801d08a: 2200 movs r2, #0 801d08c: 815a strh r2, [r3, #10] #endif /* TCP_OVERSIZE_DBGCHECK */ /* Add back to the queue with new trimmed pbuf */ pcb->snd_queuelen += pbuf_clen(useg->p); 801d08e: 697b ldr r3, [r7, #20] 801d090: 685b ldr r3, [r3, #4] 801d092: 4618 mov r0, r3 801d094: f7fa fdbe bl 8017c14 801d098: 4603 mov r3, r0 801d09a: 461a mov r2, r3 801d09c: 687b ldr r3, [r7, #4] 801d09e: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801d0a2: 4413 add r3, r2 801d0a4: b29a uxth r2, r3 801d0a6: 687b ldr r3, [r7, #4] 801d0a8: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 #endif /* TCP_CHECKSUM_ON_COPY */ /* Update number of segments on the queues. Note that length now may * exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf * because the total amount of data is constant when packet is split */ pcb->snd_queuelen += pbuf_clen(seg->p); 801d0ac: 69bb ldr r3, [r7, #24] 801d0ae: 685b ldr r3, [r3, #4] 801d0b0: 4618 mov r0, r3 801d0b2: f7fa fdaf bl 8017c14 801d0b6: 4603 mov r3, r0 801d0b8: 461a mov r2, r3 801d0ba: 687b ldr r3, [r7, #4] 801d0bc: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801d0c0: 4413 add r3, r2 801d0c2: b29a uxth r2, r3 801d0c4: 687b ldr r3, [r7, #4] 801d0c6: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 /* Finally insert remainder into queue after split (which stays head) */ seg->next = useg->next; 801d0ca: 697b ldr r3, [r7, #20] 801d0cc: 681a ldr r2, [r3, #0] 801d0ce: 69bb ldr r3, [r7, #24] 801d0d0: 601a str r2, [r3, #0] useg->next = seg; 801d0d2: 697b ldr r3, [r7, #20] 801d0d4: 69ba ldr r2, [r7, #24] 801d0d6: 601a str r2, [r3, #0] #if TCP_OVERSIZE /* If remainder is last segment on the unsent, ensure we clear the oversize amount * because the remainder is always sized to the exact remaining amount */ if (seg->next == NULL) { 801d0d8: 69bb ldr r3, [r7, #24] 801d0da: 681b ldr r3, [r3, #0] 801d0dc: 2b00 cmp r3, #0 801d0de: d103 bne.n 801d0e8 pcb->unsent_oversize = 0; 801d0e0: 687b ldr r3, [r7, #4] 801d0e2: 2200 movs r2, #0 801d0e4: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 } #endif /* TCP_OVERSIZE */ return ERR_OK; 801d0e8: 2300 movs r3, #0 801d0ea: e016 b.n 801d11a goto memerr; 801d0ec: bf00 nop 801d0ee: e002 b.n 801d0f6 goto memerr; 801d0f0: bf00 nop 801d0f2: e000 b.n 801d0f6 goto memerr; 801d0f4: bf00 nop memerr: TCP_STATS_INC(tcp.memerr); LWIP_ASSERT("seg == NULL", seg == NULL); 801d0f6: 69bb ldr r3, [r7, #24] 801d0f8: 2b00 cmp r3, #0 801d0fa: d006 beq.n 801d10a 801d0fc: 4b09 ldr r3, [pc, #36] ; (801d124 ) 801d0fe: f44f 7276 mov.w r2, #984 ; 0x3d8 801d102: 490e ldr r1, [pc, #56] ; (801d13c ) 801d104: 4809 ldr r0, [pc, #36] ; (801d12c ) 801d106: f004 fc3f bl 8021988 if (p != NULL) { 801d10a: 693b ldr r3, [r7, #16] 801d10c: 2b00 cmp r3, #0 801d10e: d002 beq.n 801d116 pbuf_free(p); 801d110: 6938 ldr r0, [r7, #16] 801d112: f7fa fcf1 bl 8017af8 } return ERR_MEM; 801d116: f04f 33ff mov.w r3, #4294967295 } 801d11a: 4618 mov r0, r3 801d11c: 3724 adds r7, #36 ; 0x24 801d11e: 46bd mov sp, r7 801d120: bd90 pop {r4, r7, pc} 801d122: bf00 nop 801d124: 080257b8 .word 0x080257b8 801d128: 08025ba8 .word 0x08025ba8 801d12c: 0802580c .word 0x0802580c 801d130: 08025bcc .word 0x08025bcc 801d134: 08025bf0 .word 0x08025bf0 801d138: 08025c00 .word 0x08025c00 801d13c: 08025c10 .word 0x08025c10 0801d140 : * @param pcb the tcp_pcb over which to send a segment * @return ERR_OK if sent, another err_t otherwise */ err_t tcp_send_fin(struct tcp_pcb *pcb) { 801d140: b590 push {r4, r7, lr} 801d142: b085 sub sp, #20 801d144: af00 add r7, sp, #0 801d146: 6078 str r0, [r7, #4] LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL); 801d148: 687b ldr r3, [r7, #4] 801d14a: 2b00 cmp r3, #0 801d14c: d106 bne.n 801d15c 801d14e: 4b21 ldr r3, [pc, #132] ; (801d1d4 ) 801d150: f240 32eb movw r2, #1003 ; 0x3eb 801d154: 4920 ldr r1, [pc, #128] ; (801d1d8 ) 801d156: 4821 ldr r0, [pc, #132] ; (801d1dc ) 801d158: f004 fc16 bl 8021988 /* first, try to add the fin to the last unsent segment */ if (pcb->unsent != NULL) { 801d15c: 687b ldr r3, [r7, #4] 801d15e: 6edb ldr r3, [r3, #108] ; 0x6c 801d160: 2b00 cmp r3, #0 801d162: d02e beq.n 801d1c2 struct tcp_seg *last_unsent; for (last_unsent = pcb->unsent; last_unsent->next != NULL; 801d164: 687b ldr r3, [r7, #4] 801d166: 6edb ldr r3, [r3, #108] ; 0x6c 801d168: 60fb str r3, [r7, #12] 801d16a: e002 b.n 801d172 last_unsent = last_unsent->next); 801d16c: 68fb ldr r3, [r7, #12] 801d16e: 681b ldr r3, [r3, #0] 801d170: 60fb str r3, [r7, #12] for (last_unsent = pcb->unsent; last_unsent->next != NULL; 801d172: 68fb ldr r3, [r7, #12] 801d174: 681b ldr r3, [r3, #0] 801d176: 2b00 cmp r3, #0 801d178: d1f8 bne.n 801d16c if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) { 801d17a: 68fb ldr r3, [r7, #12] 801d17c: 691b ldr r3, [r3, #16] 801d17e: 899b ldrh r3, [r3, #12] 801d180: b29b uxth r3, r3 801d182: 4618 mov r0, r3 801d184: f7f8 fedc bl 8015f40 801d188: 4603 mov r3, r0 801d18a: b2db uxtb r3, r3 801d18c: f003 0307 and.w r3, r3, #7 801d190: 2b00 cmp r3, #0 801d192: d116 bne.n 801d1c2 /* no SYN/FIN/RST flag in the header, we can add the FIN flag */ TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN); 801d194: 68fb ldr r3, [r7, #12] 801d196: 691b ldr r3, [r3, #16] 801d198: 899b ldrh r3, [r3, #12] 801d19a: b29c uxth r4, r3 801d19c: 2001 movs r0, #1 801d19e: f7f8 fecf bl 8015f40 801d1a2: 4603 mov r3, r0 801d1a4: 461a mov r2, r3 801d1a6: 68fb ldr r3, [r7, #12] 801d1a8: 691b ldr r3, [r3, #16] 801d1aa: 4322 orrs r2, r4 801d1ac: b292 uxth r2, r2 801d1ae: 819a strh r2, [r3, #12] tcp_set_flags(pcb, TF_FIN); 801d1b0: 687b ldr r3, [r7, #4] 801d1b2: 8b5b ldrh r3, [r3, #26] 801d1b4: f043 0320 orr.w r3, r3, #32 801d1b8: b29a uxth r2, r3 801d1ba: 687b ldr r3, [r7, #4] 801d1bc: 835a strh r2, [r3, #26] return ERR_OK; 801d1be: 2300 movs r3, #0 801d1c0: e004 b.n 801d1cc } } /* no data, no length, flags, copy=1, no optdata */ return tcp_enqueue_flags(pcb, TCP_FIN); 801d1c2: 2101 movs r1, #1 801d1c4: 6878 ldr r0, [r7, #4] 801d1c6: f000 f80b bl 801d1e0 801d1ca: 4603 mov r3, r0 } 801d1cc: 4618 mov r0, r3 801d1ce: 3714 adds r7, #20 801d1d0: 46bd mov sp, r7 801d1d2: bd90 pop {r4, r7, pc} 801d1d4: 080257b8 .word 0x080257b8 801d1d8: 08025c1c .word 0x08025c1c 801d1dc: 0802580c .word 0x0802580c 0801d1e0 : * @param pcb Protocol control block for the TCP connection. * @param flags TCP header flags to set in the outgoing segment. */ err_t tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags) { 801d1e0: b580 push {r7, lr} 801d1e2: b088 sub sp, #32 801d1e4: af02 add r7, sp, #8 801d1e6: 6078 str r0, [r7, #4] 801d1e8: 460b mov r3, r1 801d1ea: 70fb strb r3, [r7, #3] struct pbuf *p; struct tcp_seg *seg; u8_t optflags = 0; 801d1ec: 2300 movs r3, #0 801d1ee: 75fb strb r3, [r7, #23] u8_t optlen = 0; 801d1f0: 2300 movs r3, #0 801d1f2: 75bb strb r3, [r7, #22] LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)", 801d1f4: 78fb ldrb r3, [r7, #3] 801d1f6: f003 0303 and.w r3, r3, #3 801d1fa: 2b00 cmp r3, #0 801d1fc: d106 bne.n 801d20c 801d1fe: 4b67 ldr r3, [pc, #412] ; (801d39c ) 801d200: f240 4211 movw r2, #1041 ; 0x411 801d204: 4966 ldr r1, [pc, #408] ; (801d3a0 ) 801d206: 4867 ldr r0, [pc, #412] ; (801d3a4 ) 801d208: f004 fbbe bl 8021988 (flags & (TCP_SYN | TCP_FIN)) != 0); LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL); 801d20c: 687b ldr r3, [r7, #4] 801d20e: 2b00 cmp r3, #0 801d210: d106 bne.n 801d220 801d212: 4b62 ldr r3, [pc, #392] ; (801d39c ) 801d214: f240 4213 movw r2, #1043 ; 0x413 801d218: 4963 ldr r1, [pc, #396] ; (801d3a8 ) 801d21a: 4862 ldr r0, [pc, #392] ; (801d3a4 ) 801d21c: f004 fbb4 bl 8021988 /* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */ /* Get options for this segment. This is a special case since this is the only place where a SYN can be sent. */ if (flags & TCP_SYN) { 801d220: 78fb ldrb r3, [r7, #3] 801d222: f003 0302 and.w r3, r3, #2 801d226: 2b00 cmp r3, #0 801d228: d001 beq.n 801d22e optflags = TF_SEG_OPTS_MSS; 801d22a: 2301 movs r3, #1 801d22c: 75fb strb r3, [r7, #23] /* Make sure the timestamp option is only included in data segments if we agreed about it with the remote host (and in active open SYN segments). */ optflags |= TF_SEG_OPTS_TS; } #endif /* LWIP_TCP_TIMESTAMPS */ optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); 801d22e: 7dfb ldrb r3, [r7, #23] 801d230: 009b lsls r3, r3, #2 801d232: b2db uxtb r3, r3 801d234: f003 0304 and.w r3, r3, #4 801d238: 75bb strb r3, [r7, #22] /* Allocate pbuf with room for TCP header + options */ if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { 801d23a: 7dbb ldrb r3, [r7, #22] 801d23c: b29b uxth r3, r3 801d23e: f44f 7220 mov.w r2, #640 ; 0x280 801d242: 4619 mov r1, r3 801d244: 2036 movs r0, #54 ; 0x36 801d246: f7fa f96f bl 8017528 801d24a: 60f8 str r0, [r7, #12] 801d24c: 68fb ldr r3, [r7, #12] 801d24e: 2b00 cmp r3, #0 801d250: d109 bne.n 801d266 tcp_set_flags(pcb, TF_NAGLEMEMERR); 801d252: 687b ldr r3, [r7, #4] 801d254: 8b5b ldrh r3, [r3, #26] 801d256: f043 0380 orr.w r3, r3, #128 ; 0x80 801d25a: b29a uxth r2, r3 801d25c: 687b ldr r3, [r7, #4] 801d25e: 835a strh r2, [r3, #26] TCP_STATS_INC(tcp.memerr); return ERR_MEM; 801d260: f04f 33ff mov.w r3, #4294967295 801d264: e095 b.n 801d392 } LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen", 801d266: 68fb ldr r3, [r7, #12] 801d268: 895a ldrh r2, [r3, #10] 801d26a: 7dbb ldrb r3, [r7, #22] 801d26c: b29b uxth r3, r3 801d26e: 429a cmp r2, r3 801d270: d206 bcs.n 801d280 801d272: 4b4a ldr r3, [pc, #296] ; (801d39c ) 801d274: f240 4239 movw r2, #1081 ; 0x439 801d278: 494c ldr r1, [pc, #304] ; (801d3ac ) 801d27a: 484a ldr r0, [pc, #296] ; (801d3a4 ) 801d27c: f004 fb84 bl 8021988 (p->len >= optlen)); /* Allocate memory for tcp_seg, and fill in fields. */ if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) { 801d280: 687b ldr r3, [r7, #4] 801d282: 6dd9 ldr r1, [r3, #92] ; 0x5c 801d284: 78fa ldrb r2, [r7, #3] 801d286: 7dfb ldrb r3, [r7, #23] 801d288: 9300 str r3, [sp, #0] 801d28a: 460b mov r3, r1 801d28c: 68f9 ldr r1, [r7, #12] 801d28e: 6878 ldr r0, [r7, #4] 801d290: f7ff f8b8 bl 801c404 801d294: 60b8 str r0, [r7, #8] 801d296: 68bb ldr r3, [r7, #8] 801d298: 2b00 cmp r3, #0 801d29a: d109 bne.n 801d2b0 tcp_set_flags(pcb, TF_NAGLEMEMERR); 801d29c: 687b ldr r3, [r7, #4] 801d29e: 8b5b ldrh r3, [r3, #26] 801d2a0: f043 0380 orr.w r3, r3, #128 ; 0x80 801d2a4: b29a uxth r2, r3 801d2a6: 687b ldr r3, [r7, #4] 801d2a8: 835a strh r2, [r3, #26] TCP_STATS_INC(tcp.memerr); return ERR_MEM; 801d2aa: f04f 33ff mov.w r3, #4294967295 801d2ae: e070 b.n 801d392 } LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0); 801d2b0: 68bb ldr r3, [r7, #8] 801d2b2: 691b ldr r3, [r3, #16] 801d2b4: f003 0303 and.w r3, r3, #3 801d2b8: 2b00 cmp r3, #0 801d2ba: d006 beq.n 801d2ca 801d2bc: 4b37 ldr r3, [pc, #220] ; (801d39c ) 801d2be: f240 4242 movw r2, #1090 ; 0x442 801d2c2: 493b ldr r1, [pc, #236] ; (801d3b0 ) 801d2c4: 4837 ldr r0, [pc, #220] ; (801d3a4 ) 801d2c6: f004 fb5f bl 8021988 LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0); 801d2ca: 68bb ldr r3, [r7, #8] 801d2cc: 891b ldrh r3, [r3, #8] 801d2ce: 2b00 cmp r3, #0 801d2d0: d006 beq.n 801d2e0 801d2d2: 4b32 ldr r3, [pc, #200] ; (801d39c ) 801d2d4: f240 4243 movw r2, #1091 ; 0x443 801d2d8: 4936 ldr r1, [pc, #216] ; (801d3b4 ) 801d2da: 4832 ldr r0, [pc, #200] ; (801d3a4 ) 801d2dc: f004 fb54 bl 8021988 lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), (u16_t)flags)); /* Now append seg to pcb->unsent queue */ if (pcb->unsent == NULL) { 801d2e0: 687b ldr r3, [r7, #4] 801d2e2: 6edb ldr r3, [r3, #108] ; 0x6c 801d2e4: 2b00 cmp r3, #0 801d2e6: d103 bne.n 801d2f0 pcb->unsent = seg; 801d2e8: 687b ldr r3, [r7, #4] 801d2ea: 68ba ldr r2, [r7, #8] 801d2ec: 66da str r2, [r3, #108] ; 0x6c 801d2ee: e00d b.n 801d30c } else { struct tcp_seg *useg; for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); 801d2f0: 687b ldr r3, [r7, #4] 801d2f2: 6edb ldr r3, [r3, #108] ; 0x6c 801d2f4: 613b str r3, [r7, #16] 801d2f6: e002 b.n 801d2fe 801d2f8: 693b ldr r3, [r7, #16] 801d2fa: 681b ldr r3, [r3, #0] 801d2fc: 613b str r3, [r7, #16] 801d2fe: 693b ldr r3, [r7, #16] 801d300: 681b ldr r3, [r3, #0] 801d302: 2b00 cmp r3, #0 801d304: d1f8 bne.n 801d2f8 useg->next = seg; 801d306: 693b ldr r3, [r7, #16] 801d308: 68ba ldr r2, [r7, #8] 801d30a: 601a str r2, [r3, #0] } #if TCP_OVERSIZE /* The new unsent tail has no space */ pcb->unsent_oversize = 0; 801d30c: 687b ldr r3, [r7, #4] 801d30e: 2200 movs r2, #0 801d310: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 #endif /* TCP_OVERSIZE */ /* SYN and FIN bump the sequence number */ if ((flags & TCP_SYN) || (flags & TCP_FIN)) { 801d314: 78fb ldrb r3, [r7, #3] 801d316: f003 0302 and.w r3, r3, #2 801d31a: 2b00 cmp r3, #0 801d31c: d104 bne.n 801d328 801d31e: 78fb ldrb r3, [r7, #3] 801d320: f003 0301 and.w r3, r3, #1 801d324: 2b00 cmp r3, #0 801d326: d004 beq.n 801d332 pcb->snd_lbb++; 801d328: 687b ldr r3, [r7, #4] 801d32a: 6ddb ldr r3, [r3, #92] ; 0x5c 801d32c: 1c5a adds r2, r3, #1 801d32e: 687b ldr r3, [r7, #4] 801d330: 65da str r2, [r3, #92] ; 0x5c /* optlen does not influence snd_buf */ } if (flags & TCP_FIN) { 801d332: 78fb ldrb r3, [r7, #3] 801d334: f003 0301 and.w r3, r3, #1 801d338: 2b00 cmp r3, #0 801d33a: d006 beq.n 801d34a tcp_set_flags(pcb, TF_FIN); 801d33c: 687b ldr r3, [r7, #4] 801d33e: 8b5b ldrh r3, [r3, #26] 801d340: f043 0320 orr.w r3, r3, #32 801d344: b29a uxth r2, r3 801d346: 687b ldr r3, [r7, #4] 801d348: 835a strh r2, [r3, #26] } /* update number of segments on the queues */ pcb->snd_queuelen += pbuf_clen(seg->p); 801d34a: 68bb ldr r3, [r7, #8] 801d34c: 685b ldr r3, [r3, #4] 801d34e: 4618 mov r0, r3 801d350: f7fa fc60 bl 8017c14 801d354: 4603 mov r3, r0 801d356: 461a mov r2, r3 801d358: 687b ldr r3, [r7, #4] 801d35a: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801d35e: 4413 add r3, r2 801d360: b29a uxth r2, r3 801d362: 687b ldr r3, [r7, #4] 801d364: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); if (pcb->snd_queuelen != 0) { 801d368: 687b ldr r3, [r7, #4] 801d36a: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801d36e: 2b00 cmp r3, #0 801d370: d00e beq.n 801d390 LWIP_ASSERT("tcp_enqueue_flags: invalid queue length", 801d372: 687b ldr r3, [r7, #4] 801d374: 6f1b ldr r3, [r3, #112] ; 0x70 801d376: 2b00 cmp r3, #0 801d378: d10a bne.n 801d390 801d37a: 687b ldr r3, [r7, #4] 801d37c: 6edb ldr r3, [r3, #108] ; 0x6c 801d37e: 2b00 cmp r3, #0 801d380: d106 bne.n 801d390 801d382: 4b06 ldr r3, [pc, #24] ; (801d39c ) 801d384: f240 4265 movw r2, #1125 ; 0x465 801d388: 490b ldr r1, [pc, #44] ; (801d3b8 ) 801d38a: 4806 ldr r0, [pc, #24] ; (801d3a4 ) 801d38c: f004 fafc bl 8021988 pcb->unacked != NULL || pcb->unsent != NULL); } return ERR_OK; 801d390: 2300 movs r3, #0 } 801d392: 4618 mov r0, r3 801d394: 3718 adds r7, #24 801d396: 46bd mov sp, r7 801d398: bd80 pop {r7, pc} 801d39a: bf00 nop 801d39c: 080257b8 .word 0x080257b8 801d3a0: 08025c38 .word 0x08025c38 801d3a4: 0802580c .word 0x0802580c 801d3a8: 08025c90 .word 0x08025c90 801d3ac: 08025cb0 .word 0x08025cb0 801d3b0: 08025cec .word 0x08025cec 801d3b4: 08025d04 .word 0x08025d04 801d3b8: 08025d30 .word 0x08025d30 0801d3bc : * @return ERR_OK if data has been sent or nothing to send * another err_t on error */ err_t tcp_output(struct tcp_pcb *pcb) { 801d3bc: b5b0 push {r4, r5, r7, lr} 801d3be: b08a sub sp, #40 ; 0x28 801d3c0: af00 add r7, sp, #0 801d3c2: 6078 str r0, [r7, #4] s16_t i = 0; #endif /* TCP_CWND_DEBUG */ LWIP_ASSERT_CORE_LOCKED(); LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL); 801d3c4: 687b ldr r3, [r7, #4] 801d3c6: 2b00 cmp r3, #0 801d3c8: d106 bne.n 801d3d8 801d3ca: 4b8a ldr r3, [pc, #552] ; (801d5f4 ) 801d3cc: f240 42e1 movw r2, #1249 ; 0x4e1 801d3d0: 4989 ldr r1, [pc, #548] ; (801d5f8 ) 801d3d2: 488a ldr r0, [pc, #552] ; (801d5fc ) 801d3d4: f004 fad8 bl 8021988 /* pcb->state LISTEN not allowed here */ LWIP_ASSERT("don't call tcp_output for listen-pcbs", 801d3d8: 687b ldr r3, [r7, #4] 801d3da: 7d1b ldrb r3, [r3, #20] 801d3dc: 2b01 cmp r3, #1 801d3de: d106 bne.n 801d3ee 801d3e0: 4b84 ldr r3, [pc, #528] ; (801d5f4 ) 801d3e2: f240 42e3 movw r2, #1251 ; 0x4e3 801d3e6: 4986 ldr r1, [pc, #536] ; (801d600 ) 801d3e8: 4884 ldr r0, [pc, #528] ; (801d5fc ) 801d3ea: f004 facd bl 8021988 /* First, check if we are invoked by the TCP input processing code. If so, we do not output anything. Instead, we rely on the input processing code to call us when input processing is done with. */ if (tcp_input_pcb == pcb) { 801d3ee: 4b85 ldr r3, [pc, #532] ; (801d604 ) 801d3f0: 681b ldr r3, [r3, #0] 801d3f2: 687a ldr r2, [r7, #4] 801d3f4: 429a cmp r2, r3 801d3f6: d101 bne.n 801d3fc return ERR_OK; 801d3f8: 2300 movs r3, #0 801d3fa: e1d1 b.n 801d7a0 } wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); 801d3fc: 687b ldr r3, [r7, #4] 801d3fe: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 801d402: 687b ldr r3, [r7, #4] 801d404: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 801d408: 4293 cmp r3, r2 801d40a: bf28 it cs 801d40c: 4613 movcs r3, r2 801d40e: b29b uxth r3, r3 801d410: 61bb str r3, [r7, #24] seg = pcb->unsent; 801d412: 687b ldr r3, [r7, #4] 801d414: 6edb ldr r3, [r3, #108] ; 0x6c 801d416: 627b str r3, [r7, #36] ; 0x24 if (seg == NULL) { 801d418: 6a7b ldr r3, [r7, #36] ; 0x24 801d41a: 2b00 cmp r3, #0 801d41c: d10b bne.n 801d436 ", seg == NULL, ack %"U32_F"\n", pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack)); /* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct * an empty ACK segment and send it. */ if (pcb->flags & TF_ACK_NOW) { 801d41e: 687b ldr r3, [r7, #4] 801d420: 8b5b ldrh r3, [r3, #26] 801d422: f003 0302 and.w r3, r3, #2 801d426: 2b00 cmp r3, #0 801d428: f000 81ad beq.w 801d786 return tcp_send_empty_ack(pcb); 801d42c: 6878 ldr r0, [r7, #4] 801d42e: f000 fdd7 bl 801dfe0 801d432: 4603 mov r3, r0 801d434: e1b4 b.n 801d7a0 pcb->snd_wnd, pcb->cwnd, wnd, lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, lwip_ntohl(seg->tcphdr->seqno), pcb->lastack)); } netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip); 801d436: 6879 ldr r1, [r7, #4] 801d438: 687b ldr r3, [r7, #4] 801d43a: 3304 adds r3, #4 801d43c: 461a mov r2, r3 801d43e: 6878 ldr r0, [r7, #4] 801d440: f7fe ffc4 bl 801c3cc 801d444: 6178 str r0, [r7, #20] if (netif == NULL) { 801d446: 697b ldr r3, [r7, #20] 801d448: 2b00 cmp r3, #0 801d44a: d102 bne.n 801d452 return ERR_RTE; 801d44c: f06f 0303 mvn.w r3, #3 801d450: e1a6 b.n 801d7a0 } /* If we don't have a local IP address, we get one from netif */ if (ip_addr_isany(&pcb->local_ip)) { 801d452: 687b ldr r3, [r7, #4] 801d454: 2b00 cmp r3, #0 801d456: d003 beq.n 801d460 801d458: 687b ldr r3, [r7, #4] 801d45a: 681b ldr r3, [r3, #0] 801d45c: 2b00 cmp r3, #0 801d45e: d111 bne.n 801d484 const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip); 801d460: 697b ldr r3, [r7, #20] 801d462: 2b00 cmp r3, #0 801d464: d002 beq.n 801d46c 801d466: 697b ldr r3, [r7, #20] 801d468: 3304 adds r3, #4 801d46a: e000 b.n 801d46e 801d46c: 2300 movs r3, #0 801d46e: 613b str r3, [r7, #16] if (local_ip == NULL) { 801d470: 693b ldr r3, [r7, #16] 801d472: 2b00 cmp r3, #0 801d474: d102 bne.n 801d47c return ERR_RTE; 801d476: f06f 0303 mvn.w r3, #3 801d47a: e191 b.n 801d7a0 } ip_addr_copy(pcb->local_ip, *local_ip); 801d47c: 693b ldr r3, [r7, #16] 801d47e: 681a ldr r2, [r3, #0] 801d480: 687b ldr r3, [r7, #4] 801d482: 601a str r2, [r3, #0] } /* Handle the current segment not fitting within the window */ if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) { 801d484: 6a7b ldr r3, [r7, #36] ; 0x24 801d486: 691b ldr r3, [r3, #16] 801d488: 685b ldr r3, [r3, #4] 801d48a: 4618 mov r0, r3 801d48c: f7f8 fd6d bl 8015f6a 801d490: 4602 mov r2, r0 801d492: 687b ldr r3, [r7, #4] 801d494: 6c5b ldr r3, [r3, #68] ; 0x44 801d496: 1ad3 subs r3, r2, r3 801d498: 6a7a ldr r2, [r7, #36] ; 0x24 801d49a: 8912 ldrh r2, [r2, #8] 801d49c: 4413 add r3, r2 801d49e: 69ba ldr r2, [r7, #24] 801d4a0: 429a cmp r2, r3 801d4a2: d227 bcs.n 801d4f4 * within the remaining (could be 0) send window and RTO timer is not running (we * have no in-flight data). If window is still too small after persist timer fires, * then we split the segment. We don't consider the congestion window since a cwnd * smaller than 1 SMSS implies in-flight data */ if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) { 801d4a4: 687b ldr r3, [r7, #4] 801d4a6: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 801d4aa: 461a mov r2, r3 801d4ac: 69bb ldr r3, [r7, #24] 801d4ae: 4293 cmp r3, r2 801d4b0: d114 bne.n 801d4dc 801d4b2: 687b ldr r3, [r7, #4] 801d4b4: 6f1b ldr r3, [r3, #112] ; 0x70 801d4b6: 2b00 cmp r3, #0 801d4b8: d110 bne.n 801d4dc 801d4ba: 687b ldr r3, [r7, #4] 801d4bc: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 801d4c0: 2b00 cmp r3, #0 801d4c2: d10b bne.n 801d4dc pcb->persist_cnt = 0; 801d4c4: 687b ldr r3, [r7, #4] 801d4c6: 2200 movs r2, #0 801d4c8: f883 2098 strb.w r2, [r3, #152] ; 0x98 pcb->persist_backoff = 1; 801d4cc: 687b ldr r3, [r7, #4] 801d4ce: 2201 movs r2, #1 801d4d0: f883 2099 strb.w r2, [r3, #153] ; 0x99 pcb->persist_probe = 0; 801d4d4: 687b ldr r3, [r7, #4] 801d4d6: 2200 movs r2, #0 801d4d8: f883 209a strb.w r2, [r3, #154] ; 0x9a } /* We need an ACK, but can't send data now, so send an empty ACK */ if (pcb->flags & TF_ACK_NOW) { 801d4dc: 687b ldr r3, [r7, #4] 801d4de: 8b5b ldrh r3, [r3, #26] 801d4e0: f003 0302 and.w r3, r3, #2 801d4e4: 2b00 cmp r3, #0 801d4e6: f000 8150 beq.w 801d78a return tcp_send_empty_ack(pcb); 801d4ea: 6878 ldr r0, [r7, #4] 801d4ec: f000 fd78 bl 801dfe0 801d4f0: 4603 mov r3, r0 801d4f2: e155 b.n 801d7a0 } goto output_done; } /* Stop persist timer, above conditions are not active */ pcb->persist_backoff = 0; 801d4f4: 687b ldr r3, [r7, #4] 801d4f6: 2200 movs r2, #0 801d4f8: f883 2099 strb.w r2, [r3, #153] ; 0x99 /* useg should point to last segment on unacked queue */ useg = pcb->unacked; 801d4fc: 687b ldr r3, [r7, #4] 801d4fe: 6f1b ldr r3, [r3, #112] ; 0x70 801d500: 623b str r3, [r7, #32] if (useg != NULL) { 801d502: 6a3b ldr r3, [r7, #32] 801d504: 2b00 cmp r3, #0 801d506: f000 811f beq.w 801d748 for (; useg->next != NULL; useg = useg->next); 801d50a: e002 b.n 801d512 801d50c: 6a3b ldr r3, [r7, #32] 801d50e: 681b ldr r3, [r3, #0] 801d510: 623b str r3, [r7, #32] 801d512: 6a3b ldr r3, [r7, #32] 801d514: 681b ldr r3, [r3, #0] 801d516: 2b00 cmp r3, #0 801d518: d1f8 bne.n 801d50c } /* data available and window allows it to be sent? */ while (seg != NULL && 801d51a: e115 b.n 801d748 lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { LWIP_ASSERT("RST not expected here!", 801d51c: 6a7b ldr r3, [r7, #36] ; 0x24 801d51e: 691b ldr r3, [r3, #16] 801d520: 899b ldrh r3, [r3, #12] 801d522: b29b uxth r3, r3 801d524: 4618 mov r0, r3 801d526: f7f8 fd0b bl 8015f40 801d52a: 4603 mov r3, r0 801d52c: b2db uxtb r3, r3 801d52e: f003 0304 and.w r3, r3, #4 801d532: 2b00 cmp r3, #0 801d534: d006 beq.n 801d544 801d536: 4b2f ldr r3, [pc, #188] ; (801d5f4 ) 801d538: f240 5236 movw r2, #1334 ; 0x536 801d53c: 4932 ldr r1, [pc, #200] ; (801d608 ) 801d53e: 482f ldr r0, [pc, #188] ; (801d5fc ) 801d540: f004 fa22 bl 8021988 * - if tcp_write had a memory error before (prevent delayed ACK timeout) or * - if FIN was already enqueued for this PCB (SYN is always alone in a segment - * either seg->next != NULL or pcb->unacked == NULL; * RST is no sent using tcp_write/tcp_output. */ if ((tcp_do_output_nagle(pcb) == 0) && 801d544: 687b ldr r3, [r7, #4] 801d546: 6f1b ldr r3, [r3, #112] ; 0x70 801d548: 2b00 cmp r3, #0 801d54a: d01f beq.n 801d58c 801d54c: 687b ldr r3, [r7, #4] 801d54e: 8b5b ldrh r3, [r3, #26] 801d550: f003 0344 and.w r3, r3, #68 ; 0x44 801d554: 2b00 cmp r3, #0 801d556: d119 bne.n 801d58c 801d558: 687b ldr r3, [r7, #4] 801d55a: 6edb ldr r3, [r3, #108] ; 0x6c 801d55c: 2b00 cmp r3, #0 801d55e: d00b beq.n 801d578 801d560: 687b ldr r3, [r7, #4] 801d562: 6edb ldr r3, [r3, #108] ; 0x6c 801d564: 681b ldr r3, [r3, #0] 801d566: 2b00 cmp r3, #0 801d568: d110 bne.n 801d58c 801d56a: 687b ldr r3, [r7, #4] 801d56c: 6edb ldr r3, [r3, #108] ; 0x6c 801d56e: 891a ldrh r2, [r3, #8] 801d570: 687b ldr r3, [r7, #4] 801d572: 8e5b ldrh r3, [r3, #50] ; 0x32 801d574: 429a cmp r2, r3 801d576: d209 bcs.n 801d58c 801d578: 687b ldr r3, [r7, #4] 801d57a: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64 801d57e: 2b00 cmp r3, #0 801d580: d004 beq.n 801d58c 801d582: 687b ldr r3, [r7, #4] 801d584: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 801d588: 2b0f cmp r3, #15 801d58a: d901 bls.n 801d590 801d58c: 2301 movs r3, #1 801d58e: e000 b.n 801d592 801d590: 2300 movs r3, #0 801d592: 2b00 cmp r3, #0 801d594: d106 bne.n 801d5a4 ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) { 801d596: 687b ldr r3, [r7, #4] 801d598: 8b5b ldrh r3, [r3, #26] 801d59a: f003 03a0 and.w r3, r3, #160 ; 0xa0 if ((tcp_do_output_nagle(pcb) == 0) && 801d59e: 2b00 cmp r3, #0 801d5a0: f000 80e7 beq.w 801d772 pcb->lastack, lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i)); ++i; #endif /* TCP_CWND_DEBUG */ if (pcb->state != SYN_SENT) { 801d5a4: 687b ldr r3, [r7, #4] 801d5a6: 7d1b ldrb r3, [r3, #20] 801d5a8: 2b02 cmp r3, #2 801d5aa: d00d beq.n 801d5c8 TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); 801d5ac: 6a7b ldr r3, [r7, #36] ; 0x24 801d5ae: 691b ldr r3, [r3, #16] 801d5b0: 899b ldrh r3, [r3, #12] 801d5b2: b29c uxth r4, r3 801d5b4: 2010 movs r0, #16 801d5b6: f7f8 fcc3 bl 8015f40 801d5ba: 4603 mov r3, r0 801d5bc: 461a mov r2, r3 801d5be: 6a7b ldr r3, [r7, #36] ; 0x24 801d5c0: 691b ldr r3, [r3, #16] 801d5c2: 4322 orrs r2, r4 801d5c4: b292 uxth r2, r2 801d5c6: 819a strh r2, [r3, #12] } err = tcp_output_segment(seg, pcb, netif); 801d5c8: 697a ldr r2, [r7, #20] 801d5ca: 6879 ldr r1, [r7, #4] 801d5cc: 6a78 ldr r0, [r7, #36] ; 0x24 801d5ce: f000 f90b bl 801d7e8 801d5d2: 4603 mov r3, r0 801d5d4: 73fb strb r3, [r7, #15] if (err != ERR_OK) { 801d5d6: f997 300f ldrsb.w r3, [r7, #15] 801d5da: 2b00 cmp r3, #0 801d5dc: d016 beq.n 801d60c /* segment could not be sent, for whatever reason */ tcp_set_flags(pcb, TF_NAGLEMEMERR); 801d5de: 687b ldr r3, [r7, #4] 801d5e0: 8b5b ldrh r3, [r3, #26] 801d5e2: f043 0380 orr.w r3, r3, #128 ; 0x80 801d5e6: b29a uxth r2, r3 801d5e8: 687b ldr r3, [r7, #4] 801d5ea: 835a strh r2, [r3, #26] return err; 801d5ec: f997 300f ldrsb.w r3, [r7, #15] 801d5f0: e0d6 b.n 801d7a0 801d5f2: bf00 nop 801d5f4: 080257b8 .word 0x080257b8 801d5f8: 08025d58 .word 0x08025d58 801d5fc: 0802580c .word 0x0802580c 801d600: 08025d70 .word 0x08025d70 801d604: 2401a4d0 .word 0x2401a4d0 801d608: 08025d98 .word 0x08025d98 } #if TCP_OVERSIZE_DBGCHECK seg->oversize_left = 0; 801d60c: 6a7b ldr r3, [r7, #36] ; 0x24 801d60e: 2200 movs r2, #0 801d610: 815a strh r2, [r3, #10] #endif /* TCP_OVERSIZE_DBGCHECK */ pcb->unsent = seg->next; 801d612: 6a7b ldr r3, [r7, #36] ; 0x24 801d614: 681a ldr r2, [r3, #0] 801d616: 687b ldr r3, [r7, #4] 801d618: 66da str r2, [r3, #108] ; 0x6c if (pcb->state != SYN_SENT) { 801d61a: 687b ldr r3, [r7, #4] 801d61c: 7d1b ldrb r3, [r3, #20] 801d61e: 2b02 cmp r3, #2 801d620: d006 beq.n 801d630 tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); 801d622: 687b ldr r3, [r7, #4] 801d624: 8b5b ldrh r3, [r3, #26] 801d626: f023 0303 bic.w r3, r3, #3 801d62a: b29a uxth r2, r3 801d62c: 687b ldr r3, [r7, #4] 801d62e: 835a strh r2, [r3, #26] } snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); 801d630: 6a7b ldr r3, [r7, #36] ; 0x24 801d632: 691b ldr r3, [r3, #16] 801d634: 685b ldr r3, [r3, #4] 801d636: 4618 mov r0, r3 801d638: f7f8 fc97 bl 8015f6a 801d63c: 4604 mov r4, r0 801d63e: 6a7b ldr r3, [r7, #36] ; 0x24 801d640: 891b ldrh r3, [r3, #8] 801d642: 461d mov r5, r3 801d644: 6a7b ldr r3, [r7, #36] ; 0x24 801d646: 691b ldr r3, [r3, #16] 801d648: 899b ldrh r3, [r3, #12] 801d64a: b29b uxth r3, r3 801d64c: 4618 mov r0, r3 801d64e: f7f8 fc77 bl 8015f40 801d652: 4603 mov r3, r0 801d654: b2db uxtb r3, r3 801d656: f003 0303 and.w r3, r3, #3 801d65a: 2b00 cmp r3, #0 801d65c: d001 beq.n 801d662 801d65e: 2301 movs r3, #1 801d660: e000 b.n 801d664 801d662: 2300 movs r3, #0 801d664: 442b add r3, r5 801d666: 4423 add r3, r4 801d668: 60bb str r3, [r7, #8] if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { 801d66a: 687b ldr r3, [r7, #4] 801d66c: 6d1a ldr r2, [r3, #80] ; 0x50 801d66e: 68bb ldr r3, [r7, #8] 801d670: 1ad3 subs r3, r2, r3 801d672: 2b00 cmp r3, #0 801d674: da02 bge.n 801d67c pcb->snd_nxt = snd_nxt; 801d676: 687b ldr r3, [r7, #4] 801d678: 68ba ldr r2, [r7, #8] 801d67a: 651a str r2, [r3, #80] ; 0x50 } /* put segment on unacknowledged list if length > 0 */ if (TCP_TCPLEN(seg) > 0) { 801d67c: 6a7b ldr r3, [r7, #36] ; 0x24 801d67e: 891b ldrh r3, [r3, #8] 801d680: 461c mov r4, r3 801d682: 6a7b ldr r3, [r7, #36] ; 0x24 801d684: 691b ldr r3, [r3, #16] 801d686: 899b ldrh r3, [r3, #12] 801d688: b29b uxth r3, r3 801d68a: 4618 mov r0, r3 801d68c: f7f8 fc58 bl 8015f40 801d690: 4603 mov r3, r0 801d692: b2db uxtb r3, r3 801d694: f003 0303 and.w r3, r3, #3 801d698: 2b00 cmp r3, #0 801d69a: d001 beq.n 801d6a0 801d69c: 2301 movs r3, #1 801d69e: e000 b.n 801d6a2 801d6a0: 2300 movs r3, #0 801d6a2: 4423 add r3, r4 801d6a4: 2b00 cmp r3, #0 801d6a6: d049 beq.n 801d73c seg->next = NULL; 801d6a8: 6a7b ldr r3, [r7, #36] ; 0x24 801d6aa: 2200 movs r2, #0 801d6ac: 601a str r2, [r3, #0] /* unacked list is empty? */ if (pcb->unacked == NULL) { 801d6ae: 687b ldr r3, [r7, #4] 801d6b0: 6f1b ldr r3, [r3, #112] ; 0x70 801d6b2: 2b00 cmp r3, #0 801d6b4: d105 bne.n 801d6c2 pcb->unacked = seg; 801d6b6: 687b ldr r3, [r7, #4] 801d6b8: 6a7a ldr r2, [r7, #36] ; 0x24 801d6ba: 671a str r2, [r3, #112] ; 0x70 useg = seg; 801d6bc: 6a7b ldr r3, [r7, #36] ; 0x24 801d6be: 623b str r3, [r7, #32] 801d6c0: e03f b.n 801d742 /* unacked list is not empty? */ } else { /* In the case of fast retransmit, the packet should not go to the tail * of the unacked queue, but rather somewhere before it. We need to check for * this case. -STJ Jul 27, 2004 */ if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) { 801d6c2: 6a7b ldr r3, [r7, #36] ; 0x24 801d6c4: 691b ldr r3, [r3, #16] 801d6c6: 685b ldr r3, [r3, #4] 801d6c8: 4618 mov r0, r3 801d6ca: f7f8 fc4e bl 8015f6a 801d6ce: 4604 mov r4, r0 801d6d0: 6a3b ldr r3, [r7, #32] 801d6d2: 691b ldr r3, [r3, #16] 801d6d4: 685b ldr r3, [r3, #4] 801d6d6: 4618 mov r0, r3 801d6d8: f7f8 fc47 bl 8015f6a 801d6dc: 4603 mov r3, r0 801d6de: 1ae3 subs r3, r4, r3 801d6e0: 2b00 cmp r3, #0 801d6e2: da24 bge.n 801d72e /* add segment to before tail of unacked list, keeping the list sorted */ struct tcp_seg **cur_seg = &(pcb->unacked); 801d6e4: 687b ldr r3, [r7, #4] 801d6e6: 3370 adds r3, #112 ; 0x70 801d6e8: 61fb str r3, [r7, #28] while (*cur_seg && 801d6ea: e002 b.n 801d6f2 TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { cur_seg = &((*cur_seg)->next ); 801d6ec: 69fb ldr r3, [r7, #28] 801d6ee: 681b ldr r3, [r3, #0] 801d6f0: 61fb str r3, [r7, #28] while (*cur_seg && 801d6f2: 69fb ldr r3, [r7, #28] 801d6f4: 681b ldr r3, [r3, #0] 801d6f6: 2b00 cmp r3, #0 801d6f8: d011 beq.n 801d71e TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { 801d6fa: 69fb ldr r3, [r7, #28] 801d6fc: 681b ldr r3, [r3, #0] 801d6fe: 691b ldr r3, [r3, #16] 801d700: 685b ldr r3, [r3, #4] 801d702: 4618 mov r0, r3 801d704: f7f8 fc31 bl 8015f6a 801d708: 4604 mov r4, r0 801d70a: 6a7b ldr r3, [r7, #36] ; 0x24 801d70c: 691b ldr r3, [r3, #16] 801d70e: 685b ldr r3, [r3, #4] 801d710: 4618 mov r0, r3 801d712: f7f8 fc2a bl 8015f6a 801d716: 4603 mov r3, r0 801d718: 1ae3 subs r3, r4, r3 while (*cur_seg && 801d71a: 2b00 cmp r3, #0 801d71c: dbe6 blt.n 801d6ec } seg->next = (*cur_seg); 801d71e: 69fb ldr r3, [r7, #28] 801d720: 681a ldr r2, [r3, #0] 801d722: 6a7b ldr r3, [r7, #36] ; 0x24 801d724: 601a str r2, [r3, #0] (*cur_seg) = seg; 801d726: 69fb ldr r3, [r7, #28] 801d728: 6a7a ldr r2, [r7, #36] ; 0x24 801d72a: 601a str r2, [r3, #0] 801d72c: e009 b.n 801d742 } else { /* add segment to tail of unacked list */ useg->next = seg; 801d72e: 6a3b ldr r3, [r7, #32] 801d730: 6a7a ldr r2, [r7, #36] ; 0x24 801d732: 601a str r2, [r3, #0] useg = useg->next; 801d734: 6a3b ldr r3, [r7, #32] 801d736: 681b ldr r3, [r3, #0] 801d738: 623b str r3, [r7, #32] 801d73a: e002 b.n 801d742 } } /* do not queue empty segments on the unacked list */ } else { tcp_seg_free(seg); 801d73c: 6a78 ldr r0, [r7, #36] ; 0x24 801d73e: f7fb feb0 bl 80194a2 } seg = pcb->unsent; 801d742: 687b ldr r3, [r7, #4] 801d744: 6edb ldr r3, [r3, #108] ; 0x6c 801d746: 627b str r3, [r7, #36] ; 0x24 while (seg != NULL && 801d748: 6a7b ldr r3, [r7, #36] ; 0x24 801d74a: 2b00 cmp r3, #0 801d74c: d012 beq.n 801d774 lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { 801d74e: 6a7b ldr r3, [r7, #36] ; 0x24 801d750: 691b ldr r3, [r3, #16] 801d752: 685b ldr r3, [r3, #4] 801d754: 4618 mov r0, r3 801d756: f7f8 fc08 bl 8015f6a 801d75a: 4602 mov r2, r0 801d75c: 687b ldr r3, [r7, #4] 801d75e: 6c5b ldr r3, [r3, #68] ; 0x44 801d760: 1ad3 subs r3, r2, r3 801d762: 6a7a ldr r2, [r7, #36] ; 0x24 801d764: 8912 ldrh r2, [r2, #8] 801d766: 4413 add r3, r2 while (seg != NULL && 801d768: 69ba ldr r2, [r7, #24] 801d76a: 429a cmp r2, r3 801d76c: f4bf aed6 bcs.w 801d51c 801d770: e000 b.n 801d774 break; 801d772: bf00 nop } #if TCP_OVERSIZE if (pcb->unsent == NULL) { 801d774: 687b ldr r3, [r7, #4] 801d776: 6edb ldr r3, [r3, #108] ; 0x6c 801d778: 2b00 cmp r3, #0 801d77a: d108 bne.n 801d78e /* last unsent has been removed, reset unsent_oversize */ pcb->unsent_oversize = 0; 801d77c: 687b ldr r3, [r7, #4] 801d77e: 2200 movs r2, #0 801d780: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 801d784: e004 b.n 801d790 goto output_done; 801d786: bf00 nop 801d788: e002 b.n 801d790 goto output_done; 801d78a: bf00 nop 801d78c: e000 b.n 801d790 } #endif /* TCP_OVERSIZE */ output_done: 801d78e: bf00 nop tcp_clear_flags(pcb, TF_NAGLEMEMERR); 801d790: 687b ldr r3, [r7, #4] 801d792: 8b5b ldrh r3, [r3, #26] 801d794: f023 0380 bic.w r3, r3, #128 ; 0x80 801d798: b29a uxth r2, r3 801d79a: 687b ldr r3, [r7, #4] 801d79c: 835a strh r2, [r3, #26] return ERR_OK; 801d79e: 2300 movs r3, #0 } 801d7a0: 4618 mov r0, r3 801d7a2: 3728 adds r7, #40 ; 0x28 801d7a4: 46bd mov sp, r7 801d7a6: bdb0 pop {r4, r5, r7, pc} 0801d7a8 : * @arg seg the tcp segment to check * @return 1 if ref != 1, 0 if ref == 1 */ static int tcp_output_segment_busy(const struct tcp_seg *seg) { 801d7a8: b580 push {r7, lr} 801d7aa: b082 sub sp, #8 801d7ac: af00 add r7, sp, #0 801d7ae: 6078 str r0, [r7, #4] LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL); 801d7b0: 687b ldr r3, [r7, #4] 801d7b2: 2b00 cmp r3, #0 801d7b4: d106 bne.n 801d7c4 801d7b6: 4b09 ldr r3, [pc, #36] ; (801d7dc ) 801d7b8: f240 529a movw r2, #1434 ; 0x59a 801d7bc: 4908 ldr r1, [pc, #32] ; (801d7e0 ) 801d7be: 4809 ldr r0, [pc, #36] ; (801d7e4 ) 801d7c0: f004 f8e2 bl 8021988 /* We only need to check the first pbuf here: If a pbuf is queued for transmission, a driver calls pbuf_ref(), which only changes the ref count of the first pbuf */ if (seg->p->ref != 1) { 801d7c4: 687b ldr r3, [r7, #4] 801d7c6: 685b ldr r3, [r3, #4] 801d7c8: 7b9b ldrb r3, [r3, #14] 801d7ca: 2b01 cmp r3, #1 801d7cc: d001 beq.n 801d7d2 /* other reference found */ return 1; 801d7ce: 2301 movs r3, #1 801d7d0: e000 b.n 801d7d4 } /* no other references found */ return 0; 801d7d2: 2300 movs r3, #0 } 801d7d4: 4618 mov r0, r3 801d7d6: 3708 adds r7, #8 801d7d8: 46bd mov sp, r7 801d7da: bd80 pop {r7, pc} 801d7dc: 080257b8 .word 0x080257b8 801d7e0: 08025db0 .word 0x08025db0 801d7e4: 0802580c .word 0x0802580c 0801d7e8 : * @param pcb the tcp_pcb for the TCP connection used to send the segment * @param netif the netif used to send the segment */ static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif) { 801d7e8: b5b0 push {r4, r5, r7, lr} 801d7ea: b08c sub sp, #48 ; 0x30 801d7ec: af04 add r7, sp, #16 801d7ee: 60f8 str r0, [r7, #12] 801d7f0: 60b9 str r1, [r7, #8] 801d7f2: 607a str r2, [r7, #4] u32_t *opts; #if TCP_CHECKSUM_ON_COPY int seg_chksum_was_swapped = 0; #endif LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL); 801d7f4: 68fb ldr r3, [r7, #12] 801d7f6: 2b00 cmp r3, #0 801d7f8: d106 bne.n 801d808 801d7fa: 4b64 ldr r3, [pc, #400] ; (801d98c ) 801d7fc: f44f 62b7 mov.w r2, #1464 ; 0x5b8 801d800: 4963 ldr r1, [pc, #396] ; (801d990 ) 801d802: 4864 ldr r0, [pc, #400] ; (801d994 ) 801d804: f004 f8c0 bl 8021988 LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL); 801d808: 68bb ldr r3, [r7, #8] 801d80a: 2b00 cmp r3, #0 801d80c: d106 bne.n 801d81c 801d80e: 4b5f ldr r3, [pc, #380] ; (801d98c ) 801d810: f240 52b9 movw r2, #1465 ; 0x5b9 801d814: 4960 ldr r1, [pc, #384] ; (801d998 ) 801d816: 485f ldr r0, [pc, #380] ; (801d994 ) 801d818: f004 f8b6 bl 8021988 LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL); 801d81c: 687b ldr r3, [r7, #4] 801d81e: 2b00 cmp r3, #0 801d820: d106 bne.n 801d830 801d822: 4b5a ldr r3, [pc, #360] ; (801d98c ) 801d824: f240 52ba movw r2, #1466 ; 0x5ba 801d828: 495c ldr r1, [pc, #368] ; (801d99c ) 801d82a: 485a ldr r0, [pc, #360] ; (801d994 ) 801d82c: f004 f8ac bl 8021988 if (tcp_output_segment_busy(seg)) { 801d830: 68f8 ldr r0, [r7, #12] 801d832: f7ff ffb9 bl 801d7a8 801d836: 4603 mov r3, r0 801d838: 2b00 cmp r3, #0 801d83a: d001 beq.n 801d840 /* This should not happen: rexmit functions should have checked this. However, since this function modifies p->len, we must not continue in this case. */ LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n")); return ERR_OK; 801d83c: 2300 movs r3, #0 801d83e: e0a1 b.n 801d984 } /* The TCP header has already been constructed, but the ackno and wnd fields remain. */ seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt); 801d840: 68bb ldr r3, [r7, #8] 801d842: 6a5a ldr r2, [r3, #36] ; 0x24 801d844: 68fb ldr r3, [r7, #12] 801d846: 691c ldr r4, [r3, #16] 801d848: 4610 mov r0, r2 801d84a: f7f8 fb8e bl 8015f6a 801d84e: 4603 mov r3, r0 801d850: 60a3 str r3, [r4, #8] the window scale option) is never scaled. */ seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd)); } else #endif /* LWIP_WND_SCALE */ { seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd))); 801d852: 68bb ldr r3, [r7, #8] 801d854: 8d5a ldrh r2, [r3, #42] ; 0x2a 801d856: 68fb ldr r3, [r7, #12] 801d858: 691c ldr r4, [r3, #16] 801d85a: 4610 mov r0, r2 801d85c: f7f8 fb70 bl 8015f40 801d860: 4603 mov r3, r0 801d862: 81e3 strh r3, [r4, #14] } pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; 801d864: 68bb ldr r3, [r7, #8] 801d866: 6a5b ldr r3, [r3, #36] ; 0x24 801d868: 68ba ldr r2, [r7, #8] 801d86a: 8d52 ldrh r2, [r2, #42] ; 0x2a 801d86c: 441a add r2, r3 801d86e: 68bb ldr r3, [r7, #8] 801d870: 62da str r2, [r3, #44] ; 0x2c /* Add any requested options. NB MSS option is only set on SYN packets, so ignore it here */ /* cast through void* to get rid of alignment warnings */ opts = (u32_t *)(void *)(seg->tcphdr + 1); 801d872: 68fb ldr r3, [r7, #12] 801d874: 691b ldr r3, [r3, #16] 801d876: 3314 adds r3, #20 801d878: 61fb str r3, [r7, #28] if (seg->flags & TF_SEG_OPTS_MSS) { 801d87a: 68fb ldr r3, [r7, #12] 801d87c: 7b1b ldrb r3, [r3, #12] 801d87e: f003 0301 and.w r3, r3, #1 801d882: 2b00 cmp r3, #0 801d884: d015 beq.n 801d8b2 u16_t mss; #if TCP_CALCULATE_EFF_SEND_MSS mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip); 801d886: 68bb ldr r3, [r7, #8] 801d888: 3304 adds r3, #4 801d88a: 461a mov r2, r3 801d88c: 6879 ldr r1, [r7, #4] 801d88e: f240 50b4 movw r0, #1460 ; 0x5b4 801d892: f7fc f9cb bl 8019c2c 801d896: 4603 mov r3, r0 801d898: 837b strh r3, [r7, #26] #else /* TCP_CALCULATE_EFF_SEND_MSS */ mss = TCP_MSS; #endif /* TCP_CALCULATE_EFF_SEND_MSS */ *opts = TCP_BUILD_MSS_OPTION(mss); 801d89a: 8b7b ldrh r3, [r7, #26] 801d89c: f043 7301 orr.w r3, r3, #33816576 ; 0x2040000 801d8a0: 4618 mov r0, r3 801d8a2: f7f8 fb62 bl 8015f6a 801d8a6: 4602 mov r2, r0 801d8a8: 69fb ldr r3, [r7, #28] 801d8aa: 601a str r2, [r3, #0] opts += 1; 801d8ac: 69fb ldr r3, [r7, #28] 801d8ae: 3304 adds r3, #4 801d8b0: 61fb str r3, [r7, #28] } #endif /* Set retransmission timer running if it is not currently enabled This must be set before checking the route. */ if (pcb->rtime < 0) { 801d8b2: 68bb ldr r3, [r7, #8] 801d8b4: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 801d8b8: 2b00 cmp r3, #0 801d8ba: da02 bge.n 801d8c2 pcb->rtime = 0; 801d8bc: 68bb ldr r3, [r7, #8] 801d8be: 2200 movs r2, #0 801d8c0: 861a strh r2, [r3, #48] ; 0x30 } if (pcb->rttest == 0) { 801d8c2: 68bb ldr r3, [r7, #8] 801d8c4: 6b5b ldr r3, [r3, #52] ; 0x34 801d8c6: 2b00 cmp r3, #0 801d8c8: d10c bne.n 801d8e4 pcb->rttest = tcp_ticks; 801d8ca: 4b35 ldr r3, [pc, #212] ; (801d9a0 ) 801d8cc: 681a ldr r2, [r3, #0] 801d8ce: 68bb ldr r3, [r7, #8] 801d8d0: 635a str r2, [r3, #52] ; 0x34 pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno); 801d8d2: 68fb ldr r3, [r7, #12] 801d8d4: 691b ldr r3, [r3, #16] 801d8d6: 685b ldr r3, [r3, #4] 801d8d8: 4618 mov r0, r3 801d8da: f7f8 fb46 bl 8015f6a 801d8de: 4602 mov r2, r0 801d8e0: 68bb ldr r3, [r7, #8] 801d8e2: 639a str r2, [r3, #56] ; 0x38 } LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) + seg->len)); len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); 801d8e4: 68fb ldr r3, [r7, #12] 801d8e6: 691a ldr r2, [r3, #16] 801d8e8: 68fb ldr r3, [r7, #12] 801d8ea: 685b ldr r3, [r3, #4] 801d8ec: 685b ldr r3, [r3, #4] 801d8ee: 1ad3 subs r3, r2, r3 801d8f0: 833b strh r3, [r7, #24] if (len == 0) { /** Exclude retransmitted segments from this count. */ MIB2_STATS_INC(mib2.tcpoutsegs); } seg->p->len -= len; 801d8f2: 68fb ldr r3, [r7, #12] 801d8f4: 685b ldr r3, [r3, #4] 801d8f6: 8959 ldrh r1, [r3, #10] 801d8f8: 68fb ldr r3, [r7, #12] 801d8fa: 685b ldr r3, [r3, #4] 801d8fc: 8b3a ldrh r2, [r7, #24] 801d8fe: 1a8a subs r2, r1, r2 801d900: b292 uxth r2, r2 801d902: 815a strh r2, [r3, #10] seg->p->tot_len -= len; 801d904: 68fb ldr r3, [r7, #12] 801d906: 685b ldr r3, [r3, #4] 801d908: 8919 ldrh r1, [r3, #8] 801d90a: 68fb ldr r3, [r7, #12] 801d90c: 685b ldr r3, [r3, #4] 801d90e: 8b3a ldrh r2, [r7, #24] 801d910: 1a8a subs r2, r1, r2 801d912: b292 uxth r2, r2 801d914: 811a strh r2, [r3, #8] seg->p->payload = seg->tcphdr; 801d916: 68fb ldr r3, [r7, #12] 801d918: 685b ldr r3, [r3, #4] 801d91a: 68fa ldr r2, [r7, #12] 801d91c: 6912 ldr r2, [r2, #16] 801d91e: 605a str r2, [r3, #4] seg->tcphdr->chksum = 0; 801d920: 68fb ldr r3, [r7, #12] 801d922: 691b ldr r3, [r3, #16] 801d924: 2200 movs r2, #0 801d926: 741a strb r2, [r3, #16] 801d928: 2200 movs r2, #0 801d92a: 745a strb r2, [r3, #17] #ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts); #endif LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb)); 801d92c: 68fb ldr r3, [r7, #12] 801d92e: 691a ldr r2, [r3, #16] 801d930: 68fb ldr r3, [r7, #12] 801d932: 7b1b ldrb r3, [r3, #12] 801d934: f003 0301 and.w r3, r3, #1 801d938: 2b00 cmp r3, #0 801d93a: d001 beq.n 801d940 801d93c: 2318 movs r3, #24 801d93e: e000 b.n 801d942 801d940: 2314 movs r3, #20 801d942: 4413 add r3, r2 801d944: 69fa ldr r2, [r7, #28] 801d946: 429a cmp r2, r3 801d948: d006 beq.n 801d958 801d94a: 4b10 ldr r3, [pc, #64] ; (801d98c ) 801d94c: f240 621c movw r2, #1564 ; 0x61c 801d950: 4914 ldr r1, [pc, #80] ; (801d9a4 ) 801d952: 4810 ldr r0, [pc, #64] ; (801d994 ) 801d954: f004 f818 bl 8021988 } #endif /* CHECKSUM_GEN_TCP */ TCP_STATS_INC(tcp.xmit); NETIF_SET_HINTS(netif, &(pcb->netif_hints)); err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 801d958: 68fb ldr r3, [r7, #12] 801d95a: 6858 ldr r0, [r3, #4] 801d95c: 68b9 ldr r1, [r7, #8] 801d95e: 68bb ldr r3, [r7, #8] 801d960: 1d1c adds r4, r3, #4 801d962: 68bb ldr r3, [r7, #8] 801d964: 7add ldrb r5, [r3, #11] 801d966: 68bb ldr r3, [r7, #8] 801d968: 7a9b ldrb r3, [r3, #10] 801d96a: 687a ldr r2, [r7, #4] 801d96c: 9202 str r2, [sp, #8] 801d96e: 2206 movs r2, #6 801d970: 9201 str r2, [sp, #4] 801d972: 9300 str r3, [sp, #0] 801d974: 462b mov r3, r5 801d976: 4622 mov r2, r4 801d978: f002 fc7a bl 8020270 801d97c: 4603 mov r3, r0 801d97e: 75fb strb r3, [r7, #23] seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum); seg->chksum_swapped = 1; } #endif return err; 801d980: f997 3017 ldrsb.w r3, [r7, #23] } 801d984: 4618 mov r0, r3 801d986: 3720 adds r7, #32 801d988: 46bd mov sp, r7 801d98a: bdb0 pop {r4, r5, r7, pc} 801d98c: 080257b8 .word 0x080257b8 801d990: 08025dd8 .word 0x08025dd8 801d994: 0802580c .word 0x0802580c 801d998: 08025df8 .word 0x08025df8 801d99c: 08025e18 .word 0x08025e18 801d9a0: 2401a480 .word 0x2401a480 801d9a4: 08025e3c .word 0x08025e3c 0801d9a8 : * * @param pcb the tcp_pcb for which to re-enqueue all unacked segments */ err_t tcp_rexmit_rto_prepare(struct tcp_pcb *pcb) { 801d9a8: b5b0 push {r4, r5, r7, lr} 801d9aa: b084 sub sp, #16 801d9ac: af00 add r7, sp, #0 801d9ae: 6078 str r0, [r7, #4] struct tcp_seg *seg; LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL); 801d9b0: 687b ldr r3, [r7, #4] 801d9b2: 2b00 cmp r3, #0 801d9b4: d106 bne.n 801d9c4 801d9b6: 4b36 ldr r3, [pc, #216] ; (801da90 ) 801d9b8: f240 6263 movw r2, #1635 ; 0x663 801d9bc: 4935 ldr r1, [pc, #212] ; (801da94 ) 801d9be: 4836 ldr r0, [pc, #216] ; (801da98 ) 801d9c0: f003 ffe2 bl 8021988 if (pcb->unacked == NULL) { 801d9c4: 687b ldr r3, [r7, #4] 801d9c6: 6f1b ldr r3, [r3, #112] ; 0x70 801d9c8: 2b00 cmp r3, #0 801d9ca: d102 bne.n 801d9d2 return ERR_VAL; 801d9cc: f06f 0305 mvn.w r3, #5 801d9d0: e059 b.n 801da86 /* Move all unacked segments to the head of the unsent queue. However, give up if any of the unsent pbufs are still referenced by the netif driver due to deferred transmission. No point loading the link further if it is struggling to flush its buffered writes. */ for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) { 801d9d2: 687b ldr r3, [r7, #4] 801d9d4: 6f1b ldr r3, [r3, #112] ; 0x70 801d9d6: 60fb str r3, [r7, #12] 801d9d8: e00b b.n 801d9f2 if (tcp_output_segment_busy(seg)) { 801d9da: 68f8 ldr r0, [r7, #12] 801d9dc: f7ff fee4 bl 801d7a8 801d9e0: 4603 mov r3, r0 801d9e2: 2b00 cmp r3, #0 801d9e4: d002 beq.n 801d9ec LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n")); return ERR_VAL; 801d9e6: f06f 0305 mvn.w r3, #5 801d9ea: e04c b.n 801da86 for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) { 801d9ec: 68fb ldr r3, [r7, #12] 801d9ee: 681b ldr r3, [r3, #0] 801d9f0: 60fb str r3, [r7, #12] 801d9f2: 68fb ldr r3, [r7, #12] 801d9f4: 681b ldr r3, [r3, #0] 801d9f6: 2b00 cmp r3, #0 801d9f8: d1ef bne.n 801d9da } } if (tcp_output_segment_busy(seg)) { 801d9fa: 68f8 ldr r0, [r7, #12] 801d9fc: f7ff fed4 bl 801d7a8 801da00: 4603 mov r3, r0 801da02: 2b00 cmp r3, #0 801da04: d002 beq.n 801da0c LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n")); return ERR_VAL; 801da06: f06f 0305 mvn.w r3, #5 801da0a: e03c b.n 801da86 } /* concatenate unsent queue after unacked queue */ seg->next = pcb->unsent; 801da0c: 687b ldr r3, [r7, #4] 801da0e: 6eda ldr r2, [r3, #108] ; 0x6c 801da10: 68fb ldr r3, [r7, #12] 801da12: 601a str r2, [r3, #0] #if TCP_OVERSIZE_DBGCHECK /* if last unsent changed, we need to update unsent_oversize */ if (pcb->unsent == NULL) { 801da14: 687b ldr r3, [r7, #4] 801da16: 6edb ldr r3, [r3, #108] ; 0x6c 801da18: 2b00 cmp r3, #0 801da1a: d104 bne.n 801da26 pcb->unsent_oversize = seg->oversize_left; 801da1c: 68fb ldr r3, [r7, #12] 801da1e: 895a ldrh r2, [r3, #10] 801da20: 687b ldr r3, [r7, #4] 801da22: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 } #endif /* TCP_OVERSIZE_DBGCHECK */ /* unsent queue is the concatenated queue (of unacked, unsent) */ pcb->unsent = pcb->unacked; 801da26: 687b ldr r3, [r7, #4] 801da28: 6f1a ldr r2, [r3, #112] ; 0x70 801da2a: 687b ldr r3, [r7, #4] 801da2c: 66da str r2, [r3, #108] ; 0x6c /* unacked queue is now empty */ pcb->unacked = NULL; 801da2e: 687b ldr r3, [r7, #4] 801da30: 2200 movs r2, #0 801da32: 671a str r2, [r3, #112] ; 0x70 /* Mark RTO in-progress */ tcp_set_flags(pcb, TF_RTO); 801da34: 687b ldr r3, [r7, #4] 801da36: 8b5b ldrh r3, [r3, #26] 801da38: f443 6300 orr.w r3, r3, #2048 ; 0x800 801da3c: b29a uxth r2, r3 801da3e: 687b ldr r3, [r7, #4] 801da40: 835a strh r2, [r3, #26] /* Record the next byte following retransmit */ pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); 801da42: 68fb ldr r3, [r7, #12] 801da44: 691b ldr r3, [r3, #16] 801da46: 685b ldr r3, [r3, #4] 801da48: 4618 mov r0, r3 801da4a: f7f8 fa8e bl 8015f6a 801da4e: 4604 mov r4, r0 801da50: 68fb ldr r3, [r7, #12] 801da52: 891b ldrh r3, [r3, #8] 801da54: 461d mov r5, r3 801da56: 68fb ldr r3, [r7, #12] 801da58: 691b ldr r3, [r3, #16] 801da5a: 899b ldrh r3, [r3, #12] 801da5c: b29b uxth r3, r3 801da5e: 4618 mov r0, r3 801da60: f7f8 fa6e bl 8015f40 801da64: 4603 mov r3, r0 801da66: b2db uxtb r3, r3 801da68: f003 0303 and.w r3, r3, #3 801da6c: 2b00 cmp r3, #0 801da6e: d001 beq.n 801da74 801da70: 2301 movs r3, #1 801da72: e000 b.n 801da76 801da74: 2300 movs r3, #0 801da76: 442b add r3, r5 801da78: 18e2 adds r2, r4, r3 801da7a: 687b ldr r3, [r7, #4] 801da7c: 64da str r2, [r3, #76] ; 0x4c /* Don't take any RTT measurements after retransmitting. */ pcb->rttest = 0; 801da7e: 687b ldr r3, [r7, #4] 801da80: 2200 movs r2, #0 801da82: 635a str r2, [r3, #52] ; 0x34 return ERR_OK; 801da84: 2300 movs r3, #0 } 801da86: 4618 mov r0, r3 801da88: 3710 adds r7, #16 801da8a: 46bd mov sp, r7 801da8c: bdb0 pop {r4, r5, r7, pc} 801da8e: bf00 nop 801da90: 080257b8 .word 0x080257b8 801da94: 08025e50 .word 0x08025e50 801da98: 0802580c .word 0x0802580c 0801da9c : * * @param pcb the tcp_pcb for which to re-enqueue all unacked segments */ void tcp_rexmit_rto_commit(struct tcp_pcb *pcb) { 801da9c: b580 push {r7, lr} 801da9e: b082 sub sp, #8 801daa0: af00 add r7, sp, #0 801daa2: 6078 str r0, [r7, #4] LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL); 801daa4: 687b ldr r3, [r7, #4] 801daa6: 2b00 cmp r3, #0 801daa8: d106 bne.n 801dab8 801daaa: 4b0d ldr r3, [pc, #52] ; (801dae0 ) 801daac: f44f 62d3 mov.w r2, #1688 ; 0x698 801dab0: 490c ldr r1, [pc, #48] ; (801dae4 ) 801dab2: 480d ldr r0, [pc, #52] ; (801dae8 ) 801dab4: f003 ff68 bl 8021988 /* increment number of retransmissions */ if (pcb->nrtx < 0xFF) { 801dab8: 687b ldr r3, [r7, #4] 801daba: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 801dabe: 2bff cmp r3, #255 ; 0xff 801dac0: d007 beq.n 801dad2 ++pcb->nrtx; 801dac2: 687b ldr r3, [r7, #4] 801dac4: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 801dac8: 3301 adds r3, #1 801daca: b2da uxtb r2, r3 801dacc: 687b ldr r3, [r7, #4] 801dace: f883 2042 strb.w r2, [r3, #66] ; 0x42 } /* Do the actual retransmission */ tcp_output(pcb); 801dad2: 6878 ldr r0, [r7, #4] 801dad4: f7ff fc72 bl 801d3bc } 801dad8: bf00 nop 801dada: 3708 adds r7, #8 801dadc: 46bd mov sp, r7 801dade: bd80 pop {r7, pc} 801dae0: 080257b8 .word 0x080257b8 801dae4: 08025e74 .word 0x08025e74 801dae8: 0802580c .word 0x0802580c 0801daec : * * @param pcb the tcp_pcb for which to re-enqueue all unacked segments */ void tcp_rexmit_rto(struct tcp_pcb *pcb) { 801daec: b580 push {r7, lr} 801daee: b082 sub sp, #8 801daf0: af00 add r7, sp, #0 801daf2: 6078 str r0, [r7, #4] LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL); 801daf4: 687b ldr r3, [r7, #4] 801daf6: 2b00 cmp r3, #0 801daf8: d106 bne.n 801db08 801dafa: 4b0a ldr r3, [pc, #40] ; (801db24 ) 801dafc: f240 62ad movw r2, #1709 ; 0x6ad 801db00: 4909 ldr r1, [pc, #36] ; (801db28 ) 801db02: 480a ldr r0, [pc, #40] ; (801db2c ) 801db04: f003 ff40 bl 8021988 if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) { 801db08: 6878 ldr r0, [r7, #4] 801db0a: f7ff ff4d bl 801d9a8 801db0e: 4603 mov r3, r0 801db10: 2b00 cmp r3, #0 801db12: d102 bne.n 801db1a tcp_rexmit_rto_commit(pcb); 801db14: 6878 ldr r0, [r7, #4] 801db16: f7ff ffc1 bl 801da9c } } 801db1a: bf00 nop 801db1c: 3708 adds r7, #8 801db1e: 46bd mov sp, r7 801db20: bd80 pop {r7, pc} 801db22: bf00 nop 801db24: 080257b8 .word 0x080257b8 801db28: 08025e98 .word 0x08025e98 801db2c: 0802580c .word 0x0802580c 0801db30 : * * @param pcb the tcp_pcb for which to retransmit the first unacked segment */ err_t tcp_rexmit(struct tcp_pcb *pcb) { 801db30: b590 push {r4, r7, lr} 801db32: b085 sub sp, #20 801db34: af00 add r7, sp, #0 801db36: 6078 str r0, [r7, #4] struct tcp_seg *seg; struct tcp_seg **cur_seg; LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL); 801db38: 687b ldr r3, [r7, #4] 801db3a: 2b00 cmp r3, #0 801db3c: d106 bne.n 801db4c 801db3e: 4b2f ldr r3, [pc, #188] ; (801dbfc ) 801db40: f240 62c1 movw r2, #1729 ; 0x6c1 801db44: 492e ldr r1, [pc, #184] ; (801dc00 ) 801db46: 482f ldr r0, [pc, #188] ; (801dc04 ) 801db48: f003 ff1e bl 8021988 if (pcb->unacked == NULL) { 801db4c: 687b ldr r3, [r7, #4] 801db4e: 6f1b ldr r3, [r3, #112] ; 0x70 801db50: 2b00 cmp r3, #0 801db52: d102 bne.n 801db5a return ERR_VAL; 801db54: f06f 0305 mvn.w r3, #5 801db58: e04c b.n 801dbf4 } seg = pcb->unacked; 801db5a: 687b ldr r3, [r7, #4] 801db5c: 6f1b ldr r3, [r3, #112] ; 0x70 801db5e: 60bb str r3, [r7, #8] /* Give up if the segment is still referenced by the netif driver due to deferred transmission. */ if (tcp_output_segment_busy(seg)) { 801db60: 68b8 ldr r0, [r7, #8] 801db62: f7ff fe21 bl 801d7a8 801db66: 4603 mov r3, r0 801db68: 2b00 cmp r3, #0 801db6a: d002 beq.n 801db72 LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n")); return ERR_VAL; 801db6c: f06f 0305 mvn.w r3, #5 801db70: e040 b.n 801dbf4 } /* Move the first unacked segment to the unsent queue */ /* Keep the unsent queue sorted. */ pcb->unacked = seg->next; 801db72: 68bb ldr r3, [r7, #8] 801db74: 681a ldr r2, [r3, #0] 801db76: 687b ldr r3, [r7, #4] 801db78: 671a str r2, [r3, #112] ; 0x70 cur_seg = &(pcb->unsent); 801db7a: 687b ldr r3, [r7, #4] 801db7c: 336c adds r3, #108 ; 0x6c 801db7e: 60fb str r3, [r7, #12] while (*cur_seg && 801db80: e002 b.n 801db88 TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { cur_seg = &((*cur_seg)->next ); 801db82: 68fb ldr r3, [r7, #12] 801db84: 681b ldr r3, [r3, #0] 801db86: 60fb str r3, [r7, #12] while (*cur_seg && 801db88: 68fb ldr r3, [r7, #12] 801db8a: 681b ldr r3, [r3, #0] 801db8c: 2b00 cmp r3, #0 801db8e: d011 beq.n 801dbb4 TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { 801db90: 68fb ldr r3, [r7, #12] 801db92: 681b ldr r3, [r3, #0] 801db94: 691b ldr r3, [r3, #16] 801db96: 685b ldr r3, [r3, #4] 801db98: 4618 mov r0, r3 801db9a: f7f8 f9e6 bl 8015f6a 801db9e: 4604 mov r4, r0 801dba0: 68bb ldr r3, [r7, #8] 801dba2: 691b ldr r3, [r3, #16] 801dba4: 685b ldr r3, [r3, #4] 801dba6: 4618 mov r0, r3 801dba8: f7f8 f9df bl 8015f6a 801dbac: 4603 mov r3, r0 801dbae: 1ae3 subs r3, r4, r3 while (*cur_seg && 801dbb0: 2b00 cmp r3, #0 801dbb2: dbe6 blt.n 801db82 } seg->next = *cur_seg; 801dbb4: 68fb ldr r3, [r7, #12] 801dbb6: 681a ldr r2, [r3, #0] 801dbb8: 68bb ldr r3, [r7, #8] 801dbba: 601a str r2, [r3, #0] *cur_seg = seg; 801dbbc: 68fb ldr r3, [r7, #12] 801dbbe: 68ba ldr r2, [r7, #8] 801dbc0: 601a str r2, [r3, #0] #if TCP_OVERSIZE if (seg->next == NULL) { 801dbc2: 68bb ldr r3, [r7, #8] 801dbc4: 681b ldr r3, [r3, #0] 801dbc6: 2b00 cmp r3, #0 801dbc8: d103 bne.n 801dbd2 /* the retransmitted segment is last in unsent, so reset unsent_oversize */ pcb->unsent_oversize = 0; 801dbca: 687b ldr r3, [r7, #4] 801dbcc: 2200 movs r2, #0 801dbce: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 } #endif /* TCP_OVERSIZE */ if (pcb->nrtx < 0xFF) { 801dbd2: 687b ldr r3, [r7, #4] 801dbd4: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 801dbd8: 2bff cmp r3, #255 ; 0xff 801dbda: d007 beq.n 801dbec ++pcb->nrtx; 801dbdc: 687b ldr r3, [r7, #4] 801dbde: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 801dbe2: 3301 adds r3, #1 801dbe4: b2da uxtb r2, r3 801dbe6: 687b ldr r3, [r7, #4] 801dbe8: f883 2042 strb.w r2, [r3, #66] ; 0x42 } /* Don't take any rtt measurements after retransmitting. */ pcb->rttest = 0; 801dbec: 687b ldr r3, [r7, #4] 801dbee: 2200 movs r2, #0 801dbf0: 635a str r2, [r3, #52] ; 0x34 /* Do the actual retransmission. */ MIB2_STATS_INC(mib2.tcpretranssegs); /* No need to call tcp_output: we are always called from tcp_input() and thus tcp_output directly returns. */ return ERR_OK; 801dbf2: 2300 movs r3, #0 } 801dbf4: 4618 mov r0, r3 801dbf6: 3714 adds r7, #20 801dbf8: 46bd mov sp, r7 801dbfa: bd90 pop {r4, r7, pc} 801dbfc: 080257b8 .word 0x080257b8 801dc00: 08025eb4 .word 0x08025eb4 801dc04: 0802580c .word 0x0802580c 0801dc08 : * * @param pcb the tcp_pcb for which to retransmit the first unacked segment */ void tcp_rexmit_fast(struct tcp_pcb *pcb) { 801dc08: b580 push {r7, lr} 801dc0a: b082 sub sp, #8 801dc0c: af00 add r7, sp, #0 801dc0e: 6078 str r0, [r7, #4] LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL); 801dc10: 687b ldr r3, [r7, #4] 801dc12: 2b00 cmp r3, #0 801dc14: d106 bne.n 801dc24 801dc16: 4b2a ldr r3, [pc, #168] ; (801dcc0 ) 801dc18: f240 62f9 movw r2, #1785 ; 0x6f9 801dc1c: 4929 ldr r1, [pc, #164] ; (801dcc4 ) 801dc1e: 482a ldr r0, [pc, #168] ; (801dcc8 ) 801dc20: f003 feb2 bl 8021988 if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) { 801dc24: 687b ldr r3, [r7, #4] 801dc26: 6f1b ldr r3, [r3, #112] ; 0x70 801dc28: 2b00 cmp r3, #0 801dc2a: d045 beq.n 801dcb8 801dc2c: 687b ldr r3, [r7, #4] 801dc2e: 8b5b ldrh r3, [r3, #26] 801dc30: f003 0304 and.w r3, r3, #4 801dc34: 2b00 cmp r3, #0 801dc36: d13f bne.n 801dcb8 LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %"U16_F" (%"U32_F "), fast retransmit %"U32_F"\n", (u16_t)pcb->dupacks, pcb->lastack, lwip_ntohl(pcb->unacked->tcphdr->seqno))); if (tcp_rexmit(pcb) == ERR_OK) { 801dc38: 6878 ldr r0, [r7, #4] 801dc3a: f7ff ff79 bl 801db30 801dc3e: 4603 mov r3, r0 801dc40: 2b00 cmp r3, #0 801dc42: d139 bne.n 801dcb8 /* Set ssthresh to half of the minimum of the current * cwnd and the advertised window */ pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2; 801dc44: 687b ldr r3, [r7, #4] 801dc46: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 801dc4a: 687b ldr r3, [r7, #4] 801dc4c: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 801dc50: 4293 cmp r3, r2 801dc52: bf28 it cs 801dc54: 4613 movcs r3, r2 801dc56: b29b uxth r3, r3 801dc58: 2b00 cmp r3, #0 801dc5a: da00 bge.n 801dc5e 801dc5c: 3301 adds r3, #1 801dc5e: 105b asrs r3, r3, #1 801dc60: b29a uxth r2, r3 801dc62: 687b ldr r3, [r7, #4] 801dc64: f8a3 204a strh.w r2, [r3, #74] ; 0x4a /* The minimum value for ssthresh should be 2 MSS */ if (pcb->ssthresh < (2U * pcb->mss)) { 801dc68: 687b ldr r3, [r7, #4] 801dc6a: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a 801dc6e: 461a mov r2, r3 801dc70: 687b ldr r3, [r7, #4] 801dc72: 8e5b ldrh r3, [r3, #50] ; 0x32 801dc74: 005b lsls r3, r3, #1 801dc76: 429a cmp r2, r3 801dc78: d206 bcs.n 801dc88 LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F " should be min 2 mss %"U16_F"...\n", pcb->ssthresh, (u16_t)(2 * pcb->mss))); pcb->ssthresh = 2 * pcb->mss; 801dc7a: 687b ldr r3, [r7, #4] 801dc7c: 8e5b ldrh r3, [r3, #50] ; 0x32 801dc7e: 005b lsls r3, r3, #1 801dc80: b29a uxth r2, r3 801dc82: 687b ldr r3, [r7, #4] 801dc84: f8a3 204a strh.w r2, [r3, #74] ; 0x4a } pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; 801dc88: 687b ldr r3, [r7, #4] 801dc8a: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a 801dc8e: 687b ldr r3, [r7, #4] 801dc90: 8e5b ldrh r3, [r3, #50] ; 0x32 801dc92: 4619 mov r1, r3 801dc94: 0049 lsls r1, r1, #1 801dc96: 440b add r3, r1 801dc98: b29b uxth r3, r3 801dc9a: 4413 add r3, r2 801dc9c: b29a uxth r2, r3 801dc9e: 687b ldr r3, [r7, #4] 801dca0: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 tcp_set_flags(pcb, TF_INFR); 801dca4: 687b ldr r3, [r7, #4] 801dca6: 8b5b ldrh r3, [r3, #26] 801dca8: f043 0304 orr.w r3, r3, #4 801dcac: b29a uxth r2, r3 801dcae: 687b ldr r3, [r7, #4] 801dcb0: 835a strh r2, [r3, #26] /* Reset the retransmission timer to prevent immediate rto retransmissions */ pcb->rtime = 0; 801dcb2: 687b ldr r3, [r7, #4] 801dcb4: 2200 movs r2, #0 801dcb6: 861a strh r2, [r3, #48] ; 0x30 } } } 801dcb8: bf00 nop 801dcba: 3708 adds r7, #8 801dcbc: 46bd mov sp, r7 801dcbe: bd80 pop {r7, pc} 801dcc0: 080257b8 .word 0x080257b8 801dcc4: 08025ecc .word 0x08025ecc 801dcc8: 0802580c .word 0x0802580c 0801dccc : static struct pbuf * tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen, u32_t seqno_be /* already in network byte order */, u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd) { 801dccc: b580 push {r7, lr} 801dcce: b086 sub sp, #24 801dcd0: af00 add r7, sp, #0 801dcd2: 60f8 str r0, [r7, #12] 801dcd4: 607b str r3, [r7, #4] 801dcd6: 460b mov r3, r1 801dcd8: 817b strh r3, [r7, #10] 801dcda: 4613 mov r3, r2 801dcdc: 813b strh r3, [r7, #8] struct tcp_hdr *tcphdr; struct pbuf *p; p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM); 801dcde: 897a ldrh r2, [r7, #10] 801dce0: 893b ldrh r3, [r7, #8] 801dce2: 4413 add r3, r2 801dce4: b29b uxth r3, r3 801dce6: 3314 adds r3, #20 801dce8: b29b uxth r3, r3 801dcea: f44f 7220 mov.w r2, #640 ; 0x280 801dcee: 4619 mov r1, r3 801dcf0: 2022 movs r0, #34 ; 0x22 801dcf2: f7f9 fc19 bl 8017528 801dcf6: 6178 str r0, [r7, #20] if (p != NULL) { 801dcf8: 697b ldr r3, [r7, #20] 801dcfa: 2b00 cmp r3, #0 801dcfc: d04d beq.n 801dd9a LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", 801dcfe: 897b ldrh r3, [r7, #10] 801dd00: 3313 adds r3, #19 801dd02: 697a ldr r2, [r7, #20] 801dd04: 8952 ldrh r2, [r2, #10] 801dd06: 4293 cmp r3, r2 801dd08: db06 blt.n 801dd18 801dd0a: 4b26 ldr r3, [pc, #152] ; (801dda4 ) 801dd0c: f240 7223 movw r2, #1827 ; 0x723 801dd10: 4925 ldr r1, [pc, #148] ; (801dda8 ) 801dd12: 4826 ldr r0, [pc, #152] ; (801ddac ) 801dd14: f003 fe38 bl 8021988 (p->len >= TCP_HLEN + optlen)); tcphdr = (struct tcp_hdr *)p->payload; 801dd18: 697b ldr r3, [r7, #20] 801dd1a: 685b ldr r3, [r3, #4] 801dd1c: 613b str r3, [r7, #16] tcphdr->src = lwip_htons(src_port); 801dd1e: 8c3b ldrh r3, [r7, #32] 801dd20: 4618 mov r0, r3 801dd22: f7f8 f90d bl 8015f40 801dd26: 4603 mov r3, r0 801dd28: 461a mov r2, r3 801dd2a: 693b ldr r3, [r7, #16] 801dd2c: 801a strh r2, [r3, #0] tcphdr->dest = lwip_htons(dst_port); 801dd2e: 8cbb ldrh r3, [r7, #36] ; 0x24 801dd30: 4618 mov r0, r3 801dd32: f7f8 f905 bl 8015f40 801dd36: 4603 mov r3, r0 801dd38: 461a mov r2, r3 801dd3a: 693b ldr r3, [r7, #16] 801dd3c: 805a strh r2, [r3, #2] tcphdr->seqno = seqno_be; 801dd3e: 693b ldr r3, [r7, #16] 801dd40: 687a ldr r2, [r7, #4] 801dd42: 605a str r2, [r3, #4] tcphdr->ackno = lwip_htonl(ackno); 801dd44: 68f8 ldr r0, [r7, #12] 801dd46: f7f8 f910 bl 8015f6a 801dd4a: 4602 mov r2, r0 801dd4c: 693b ldr r3, [r7, #16] 801dd4e: 609a str r2, [r3, #8] TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags); 801dd50: 897b ldrh r3, [r7, #10] 801dd52: 089b lsrs r3, r3, #2 801dd54: b29b uxth r3, r3 801dd56: 3305 adds r3, #5 801dd58: b29b uxth r3, r3 801dd5a: 031b lsls r3, r3, #12 801dd5c: b29a uxth r2, r3 801dd5e: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 801dd62: b29b uxth r3, r3 801dd64: 4313 orrs r3, r2 801dd66: b29b uxth r3, r3 801dd68: 4618 mov r0, r3 801dd6a: f7f8 f8e9 bl 8015f40 801dd6e: 4603 mov r3, r0 801dd70: 461a mov r2, r3 801dd72: 693b ldr r3, [r7, #16] 801dd74: 819a strh r2, [r3, #12] tcphdr->wnd = lwip_htons(wnd); 801dd76: 8dbb ldrh r3, [r7, #44] ; 0x2c 801dd78: 4618 mov r0, r3 801dd7a: f7f8 f8e1 bl 8015f40 801dd7e: 4603 mov r3, r0 801dd80: 461a mov r2, r3 801dd82: 693b ldr r3, [r7, #16] 801dd84: 81da strh r2, [r3, #14] tcphdr->chksum = 0; 801dd86: 693b ldr r3, [r7, #16] 801dd88: 2200 movs r2, #0 801dd8a: 741a strb r2, [r3, #16] 801dd8c: 2200 movs r2, #0 801dd8e: 745a strb r2, [r3, #17] tcphdr->urgp = 0; 801dd90: 693b ldr r3, [r7, #16] 801dd92: 2200 movs r2, #0 801dd94: 749a strb r2, [r3, #18] 801dd96: 2200 movs r2, #0 801dd98: 74da strb r2, [r3, #19] } return p; 801dd9a: 697b ldr r3, [r7, #20] } 801dd9c: 4618 mov r0, r3 801dd9e: 3718 adds r7, #24 801dda0: 46bd mov sp, r7 801dda2: bd80 pop {r7, pc} 801dda4: 080257b8 .word 0x080257b8 801dda8: 08025eec .word 0x08025eec 801ddac: 0802580c .word 0x0802580c 0801ddb0 : * @return pbuf with p->payload being the tcp_hdr */ static struct pbuf * tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen, u32_t seqno_be /* already in network byte order */) { 801ddb0: b5b0 push {r4, r5, r7, lr} 801ddb2: b08a sub sp, #40 ; 0x28 801ddb4: af04 add r7, sp, #16 801ddb6: 60f8 str r0, [r7, #12] 801ddb8: 607b str r3, [r7, #4] 801ddba: 460b mov r3, r1 801ddbc: 817b strh r3, [r7, #10] 801ddbe: 4613 mov r3, r2 801ddc0: 813b strh r3, [r7, #8] struct pbuf *p; LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL); 801ddc2: 68fb ldr r3, [r7, #12] 801ddc4: 2b00 cmp r3, #0 801ddc6: d106 bne.n 801ddd6 801ddc8: 4b15 ldr r3, [pc, #84] ; (801de20 ) 801ddca: f240 7242 movw r2, #1858 ; 0x742 801ddce: 4915 ldr r1, [pc, #84] ; (801de24 ) 801ddd0: 4815 ldr r0, [pc, #84] ; (801de28 ) 801ddd2: f003 fdd9 bl 8021988 p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen, 801ddd6: 68fb ldr r3, [r7, #12] 801ddd8: 6a58 ldr r0, [r3, #36] ; 0x24 801ddda: 68fb ldr r3, [r7, #12] 801dddc: 8adb ldrh r3, [r3, #22] 801ddde: 68fa ldr r2, [r7, #12] 801dde0: 8b12 ldrh r2, [r2, #24] 801dde2: 68f9 ldr r1, [r7, #12] 801dde4: 8d49 ldrh r1, [r1, #42] ; 0x2a 801dde6: 893d ldrh r5, [r7, #8] 801dde8: 897c ldrh r4, [r7, #10] 801ddea: 9103 str r1, [sp, #12] 801ddec: 2110 movs r1, #16 801ddee: 9102 str r1, [sp, #8] 801ddf0: 9201 str r2, [sp, #4] 801ddf2: 9300 str r3, [sp, #0] 801ddf4: 687b ldr r3, [r7, #4] 801ddf6: 462a mov r2, r5 801ddf8: 4621 mov r1, r4 801ddfa: f7ff ff67 bl 801dccc 801ddfe: 6178 str r0, [r7, #20] seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK, TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd))); if (p != NULL) { 801de00: 697b ldr r3, [r7, #20] 801de02: 2b00 cmp r3, #0 801de04: d006 beq.n 801de14 /* If we're sending a packet, update the announced right window edge */ pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; 801de06: 68fb ldr r3, [r7, #12] 801de08: 6a5b ldr r3, [r3, #36] ; 0x24 801de0a: 68fa ldr r2, [r7, #12] 801de0c: 8d52 ldrh r2, [r2, #42] ; 0x2a 801de0e: 441a add r2, r3 801de10: 68fb ldr r3, [r7, #12] 801de12: 62da str r2, [r3, #44] ; 0x2c } return p; 801de14: 697b ldr r3, [r7, #20] } 801de16: 4618 mov r0, r3 801de18: 3718 adds r7, #24 801de1a: 46bd mov sp, r7 801de1c: bdb0 pop {r4, r5, r7, pc} 801de1e: bf00 nop 801de20: 080257b8 .word 0x080257b8 801de24: 08025f1c .word 0x08025f1c 801de28: 0802580c .word 0x0802580c 0801de2c : /* Fill in options for control segments */ static void tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks) { 801de2c: b580 push {r7, lr} 801de2e: b088 sub sp, #32 801de30: af00 add r7, sp, #0 801de32: 60f8 str r0, [r7, #12] 801de34: 60b9 str r1, [r7, #8] 801de36: 4611 mov r1, r2 801de38: 461a mov r2, r3 801de3a: 460b mov r3, r1 801de3c: 71fb strb r3, [r7, #7] 801de3e: 4613 mov r3, r2 801de40: 71bb strb r3, [r7, #6] struct tcp_hdr *tcphdr; u32_t *opts; u16_t sacks_len = 0; 801de42: 2300 movs r3, #0 801de44: 83fb strh r3, [r7, #30] LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL); 801de46: 68bb ldr r3, [r7, #8] 801de48: 2b00 cmp r3, #0 801de4a: d106 bne.n 801de5a 801de4c: 4b12 ldr r3, [pc, #72] ; (801de98 ) 801de4e: f240 7256 movw r2, #1878 ; 0x756 801de52: 4912 ldr r1, [pc, #72] ; (801de9c ) 801de54: 4812 ldr r0, [pc, #72] ; (801dea0 ) 801de56: f003 fd97 bl 8021988 tcphdr = (struct tcp_hdr *)p->payload; 801de5a: 68bb ldr r3, [r7, #8] 801de5c: 685b ldr r3, [r3, #4] 801de5e: 61bb str r3, [r7, #24] opts = (u32_t *)(void *)(tcphdr + 1); 801de60: 69bb ldr r3, [r7, #24] 801de62: 3314 adds r3, #20 801de64: 617b str r3, [r7, #20] opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts); #endif LWIP_UNUSED_ARG(pcb); LWIP_UNUSED_ARG(sacks_len); LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb)); 801de66: 8bfb ldrh r3, [r7, #30] 801de68: 009b lsls r3, r3, #2 801de6a: 461a mov r2, r3 801de6c: 79fb ldrb r3, [r7, #7] 801de6e: 009b lsls r3, r3, #2 801de70: f003 0304 and.w r3, r3, #4 801de74: 4413 add r3, r2 801de76: 3314 adds r3, #20 801de78: 69ba ldr r2, [r7, #24] 801de7a: 4413 add r3, r2 801de7c: 697a ldr r2, [r7, #20] 801de7e: 429a cmp r2, r3 801de80: d006 beq.n 801de90 801de82: 4b05 ldr r3, [pc, #20] ; (801de98 ) 801de84: f240 7275 movw r2, #1909 ; 0x775 801de88: 4906 ldr r1, [pc, #24] ; (801dea4 ) 801de8a: 4805 ldr r0, [pc, #20] ; (801dea0 ) 801de8c: f003 fd7c bl 8021988 LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */ LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */ } 801de90: bf00 nop 801de92: 3720 adds r7, #32 801de94: 46bd mov sp, r7 801de96: bd80 pop {r7, pc} 801de98: 080257b8 .word 0x080257b8 801de9c: 08025f44 .word 0x08025f44 801dea0: 0802580c .word 0x0802580c 801dea4: 08025e3c .word 0x08025e3c 0801dea8 : * header checksum and calling ip_output_if while handling netif hints and stats. */ static err_t tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p, const ip_addr_t *src, const ip_addr_t *dst) { 801dea8: b580 push {r7, lr} 801deaa: b08a sub sp, #40 ; 0x28 801deac: af04 add r7, sp, #16 801deae: 60f8 str r0, [r7, #12] 801deb0: 60b9 str r1, [r7, #8] 801deb2: 607a str r2, [r7, #4] 801deb4: 603b str r3, [r7, #0] err_t err; struct netif *netif; LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL); 801deb6: 68bb ldr r3, [r7, #8] 801deb8: 2b00 cmp r3, #0 801deba: d106 bne.n 801deca 801debc: 4b1c ldr r3, [pc, #112] ; (801df30 ) 801debe: f240 7287 movw r2, #1927 ; 0x787 801dec2: 491c ldr r1, [pc, #112] ; (801df34 ) 801dec4: 481c ldr r0, [pc, #112] ; (801df38 ) 801dec6: f003 fd5f bl 8021988 netif = tcp_route(pcb, src, dst); 801deca: 683a ldr r2, [r7, #0] 801decc: 6879 ldr r1, [r7, #4] 801dece: 68f8 ldr r0, [r7, #12] 801ded0: f7fe fa7c bl 801c3cc 801ded4: 6138 str r0, [r7, #16] if (netif == NULL) { 801ded6: 693b ldr r3, [r7, #16] 801ded8: 2b00 cmp r3, #0 801deda: d102 bne.n 801dee2 err = ERR_RTE; 801dedc: 23fc movs r3, #252 ; 0xfc 801dede: 75fb strb r3, [r7, #23] 801dee0: e01c b.n 801df1c struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload; tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, src, dst); } #endif if (pcb != NULL) { 801dee2: 68fb ldr r3, [r7, #12] 801dee4: 2b00 cmp r3, #0 801dee6: d006 beq.n 801def6 NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints))); ttl = pcb->ttl; 801dee8: 68fb ldr r3, [r7, #12] 801deea: 7adb ldrb r3, [r3, #11] 801deec: 75bb strb r3, [r7, #22] tos = pcb->tos; 801deee: 68fb ldr r3, [r7, #12] 801def0: 7a9b ldrb r3, [r3, #10] 801def2: 757b strb r3, [r7, #21] 801def4: e003 b.n 801defe } else { /* Send output with hardcoded TTL/HL since we have no access to the pcb */ ttl = TCP_TTL; 801def6: 23ff movs r3, #255 ; 0xff 801def8: 75bb strb r3, [r7, #22] tos = 0; 801defa: 2300 movs r3, #0 801defc: 757b strb r3, [r7, #21] } TCP_STATS_INC(tcp.xmit); err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif); 801defe: 7dba ldrb r2, [r7, #22] 801df00: 693b ldr r3, [r7, #16] 801df02: 9302 str r3, [sp, #8] 801df04: 2306 movs r3, #6 801df06: 9301 str r3, [sp, #4] 801df08: 7d7b ldrb r3, [r7, #21] 801df0a: 9300 str r3, [sp, #0] 801df0c: 4613 mov r3, r2 801df0e: 683a ldr r2, [r7, #0] 801df10: 6879 ldr r1, [r7, #4] 801df12: 68b8 ldr r0, [r7, #8] 801df14: f002 f9ac bl 8020270 801df18: 4603 mov r3, r0 801df1a: 75fb strb r3, [r7, #23] NETIF_RESET_HINTS(netif); } pbuf_free(p); 801df1c: 68b8 ldr r0, [r7, #8] 801df1e: f7f9 fdeb bl 8017af8 return err; 801df22: f997 3017 ldrsb.w r3, [r7, #23] } 801df26: 4618 mov r0, r3 801df28: 3718 adds r7, #24 801df2a: 46bd mov sp, r7 801df2c: bd80 pop {r7, pc} 801df2e: bf00 nop 801df30: 080257b8 .word 0x080257b8 801df34: 08025f6c .word 0x08025f6c 801df38: 0802580c .word 0x0802580c 0801df3c : */ void tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno, const ip_addr_t *local_ip, const ip_addr_t *remote_ip, u16_t local_port, u16_t remote_port) { 801df3c: b590 push {r4, r7, lr} 801df3e: b08b sub sp, #44 ; 0x2c 801df40: af04 add r7, sp, #16 801df42: 60f8 str r0, [r7, #12] 801df44: 60b9 str r1, [r7, #8] 801df46: 607a str r2, [r7, #4] 801df48: 603b str r3, [r7, #0] struct pbuf *p; u16_t wnd; u8_t optlen; LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL); 801df4a: 683b ldr r3, [r7, #0] 801df4c: 2b00 cmp r3, #0 801df4e: d106 bne.n 801df5e 801df50: 4b1f ldr r3, [pc, #124] ; (801dfd0 ) 801df52: f240 72c4 movw r2, #1988 ; 0x7c4 801df56: 491f ldr r1, [pc, #124] ; (801dfd4 ) 801df58: 481f ldr r0, [pc, #124] ; (801dfd8 ) 801df5a: f003 fd15 bl 8021988 LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL); 801df5e: 6abb ldr r3, [r7, #40] ; 0x28 801df60: 2b00 cmp r3, #0 801df62: d106 bne.n 801df72 801df64: 4b1a ldr r3, [pc, #104] ; (801dfd0 ) 801df66: f240 72c5 movw r2, #1989 ; 0x7c5 801df6a: 491c ldr r1, [pc, #112] ; (801dfdc ) 801df6c: 481a ldr r0, [pc, #104] ; (801dfd8 ) 801df6e: f003 fd0b bl 8021988 optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); 801df72: 2300 movs r3, #0 801df74: 75fb strb r3, [r7, #23] #if LWIP_WND_SCALE wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF)); #else wnd = PP_HTONS(TCP_WND); 801df76: f24d 0316 movw r3, #53270 ; 0xd016 801df7a: 82bb strh r3, [r7, #20] #endif p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port, 801df7c: 7dfb ldrb r3, [r7, #23] 801df7e: b29c uxth r4, r3 801df80: 68b8 ldr r0, [r7, #8] 801df82: f7f7 fff2 bl 8015f6a 801df86: 4602 mov r2, r0 801df88: 8abb ldrh r3, [r7, #20] 801df8a: 9303 str r3, [sp, #12] 801df8c: 2314 movs r3, #20 801df8e: 9302 str r3, [sp, #8] 801df90: 8e3b ldrh r3, [r7, #48] ; 0x30 801df92: 9301 str r3, [sp, #4] 801df94: 8dbb ldrh r3, [r7, #44] ; 0x2c 801df96: 9300 str r3, [sp, #0] 801df98: 4613 mov r3, r2 801df9a: 2200 movs r2, #0 801df9c: 4621 mov r1, r4 801df9e: 6878 ldr r0, [r7, #4] 801dfa0: f7ff fe94 bl 801dccc 801dfa4: 6138 str r0, [r7, #16] remote_port, TCP_RST | TCP_ACK, wnd); if (p == NULL) { 801dfa6: 693b ldr r3, [r7, #16] 801dfa8: 2b00 cmp r3, #0 801dfaa: d00c beq.n 801dfc6 LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); return; } tcp_output_fill_options(pcb, p, 0, optlen); 801dfac: 7dfb ldrb r3, [r7, #23] 801dfae: 2200 movs r2, #0 801dfb0: 6939 ldr r1, [r7, #16] 801dfb2: 68f8 ldr r0, [r7, #12] 801dfb4: f7ff ff3a bl 801de2c MIB2_STATS_INC(mib2.tcpoutrsts); tcp_output_control_segment(pcb, p, local_ip, remote_ip); 801dfb8: 6abb ldr r3, [r7, #40] ; 0x28 801dfba: 683a ldr r2, [r7, #0] 801dfbc: 6939 ldr r1, [r7, #16] 801dfbe: 68f8 ldr r0, [r7, #12] 801dfc0: f7ff ff72 bl 801dea8 801dfc4: e000 b.n 801dfc8 return; 801dfc6: bf00 nop LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); } 801dfc8: 371c adds r7, #28 801dfca: 46bd mov sp, r7 801dfcc: bd90 pop {r4, r7, pc} 801dfce: bf00 nop 801dfd0: 080257b8 .word 0x080257b8 801dfd4: 08025f98 .word 0x08025f98 801dfd8: 0802580c .word 0x0802580c 801dfdc: 08025fb4 .word 0x08025fb4 0801dfe0 : * * @param pcb Protocol control block for the TCP connection to send the ACK */ err_t tcp_send_empty_ack(struct tcp_pcb *pcb) { 801dfe0: b590 push {r4, r7, lr} 801dfe2: b087 sub sp, #28 801dfe4: af00 add r7, sp, #0 801dfe6: 6078 str r0, [r7, #4] err_t err; struct pbuf *p; u8_t optlen, optflags = 0; 801dfe8: 2300 movs r3, #0 801dfea: 75fb strb r3, [r7, #23] u8_t num_sacks = 0; 801dfec: 2300 movs r3, #0 801dfee: 75bb strb r3, [r7, #22] LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL); 801dff0: 687b ldr r3, [r7, #4] 801dff2: 2b00 cmp r3, #0 801dff4: d106 bne.n 801e004 801dff6: 4b28 ldr r3, [pc, #160] ; (801e098 ) 801dff8: f240 72ea movw r2, #2026 ; 0x7ea 801dffc: 4927 ldr r1, [pc, #156] ; (801e09c ) 801dffe: 4828 ldr r0, [pc, #160] ; (801e0a0 ) 801e000: f003 fcc2 bl 8021988 #if LWIP_TCP_TIMESTAMPS if (pcb->flags & TF_TIMESTAMP) { optflags = TF_SEG_OPTS_TS; } #endif optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); 801e004: 7dfb ldrb r3, [r7, #23] 801e006: 009b lsls r3, r3, #2 801e008: b2db uxtb r3, r3 801e00a: f003 0304 and.w r3, r3, #4 801e00e: 757b strb r3, [r7, #21] if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) { optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */ } #endif p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt)); 801e010: 7d7b ldrb r3, [r7, #21] 801e012: b29c uxth r4, r3 801e014: 687b ldr r3, [r7, #4] 801e016: 6d1b ldr r3, [r3, #80] ; 0x50 801e018: 4618 mov r0, r3 801e01a: f7f7 ffa6 bl 8015f6a 801e01e: 4603 mov r3, r0 801e020: 2200 movs r2, #0 801e022: 4621 mov r1, r4 801e024: 6878 ldr r0, [r7, #4] 801e026: f7ff fec3 bl 801ddb0 801e02a: 6138 str r0, [r7, #16] if (p == NULL) { 801e02c: 693b ldr r3, [r7, #16] 801e02e: 2b00 cmp r3, #0 801e030: d109 bne.n 801e046 /* let tcp_fasttmr retry sending this ACK */ tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); 801e032: 687b ldr r3, [r7, #4] 801e034: 8b5b ldrh r3, [r3, #26] 801e036: f043 0303 orr.w r3, r3, #3 801e03a: b29a uxth r2, r3 801e03c: 687b ldr r3, [r7, #4] 801e03e: 835a strh r2, [r3, #26] LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); return ERR_BUF; 801e040: f06f 0301 mvn.w r3, #1 801e044: e023 b.n 801e08e } tcp_output_fill_options(pcb, p, optflags, num_sacks); 801e046: 7dbb ldrb r3, [r7, #22] 801e048: 7dfa ldrb r2, [r7, #23] 801e04a: 6939 ldr r1, [r7, #16] 801e04c: 6878 ldr r0, [r7, #4] 801e04e: f7ff feed bl 801de2c pcb->ts_lastacksent = pcb->rcv_nxt; #endif LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); 801e052: 687a ldr r2, [r7, #4] 801e054: 687b ldr r3, [r7, #4] 801e056: 3304 adds r3, #4 801e058: 6939 ldr r1, [r7, #16] 801e05a: 6878 ldr r0, [r7, #4] 801e05c: f7ff ff24 bl 801dea8 801e060: 4603 mov r3, r0 801e062: 73fb strb r3, [r7, #15] if (err != ERR_OK) { 801e064: f997 300f ldrsb.w r3, [r7, #15] 801e068: 2b00 cmp r3, #0 801e06a: d007 beq.n 801e07c /* let tcp_fasttmr retry sending this ACK */ tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); 801e06c: 687b ldr r3, [r7, #4] 801e06e: 8b5b ldrh r3, [r3, #26] 801e070: f043 0303 orr.w r3, r3, #3 801e074: b29a uxth r2, r3 801e076: 687b ldr r3, [r7, #4] 801e078: 835a strh r2, [r3, #26] 801e07a: e006 b.n 801e08a } else { /* remove ACK flags from the PCB, as we sent an empty ACK now */ tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); 801e07c: 687b ldr r3, [r7, #4] 801e07e: 8b5b ldrh r3, [r3, #26] 801e080: f023 0303 bic.w r3, r3, #3 801e084: b29a uxth r2, r3 801e086: 687b ldr r3, [r7, #4] 801e088: 835a strh r2, [r3, #26] } return err; 801e08a: f997 300f ldrsb.w r3, [r7, #15] } 801e08e: 4618 mov r0, r3 801e090: 371c adds r7, #28 801e092: 46bd mov sp, r7 801e094: bd90 pop {r4, r7, pc} 801e096: bf00 nop 801e098: 080257b8 .word 0x080257b8 801e09c: 08025fd0 .word 0x08025fd0 801e0a0: 0802580c .word 0x0802580c 0801e0a4 : * * @param pcb the tcp_pcb for which to send a keepalive packet */ err_t tcp_keepalive(struct tcp_pcb *pcb) { 801e0a4: b590 push {r4, r7, lr} 801e0a6: b085 sub sp, #20 801e0a8: af00 add r7, sp, #0 801e0aa: 6078 str r0, [r7, #4] err_t err; struct pbuf *p; u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); 801e0ac: 2300 movs r3, #0 801e0ae: 72bb strb r3, [r7, #10] LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL); 801e0b0: 687b ldr r3, [r7, #4] 801e0b2: 2b00 cmp r3, #0 801e0b4: d106 bne.n 801e0c4 801e0b6: 4b18 ldr r3, [pc, #96] ; (801e118 ) 801e0b8: f640 0224 movw r2, #2084 ; 0x824 801e0bc: 4917 ldr r1, [pc, #92] ; (801e11c ) 801e0be: 4818 ldr r0, [pc, #96] ; (801e120 ) 801e0c0: f003 fc62 bl 8021988 LWIP_DEBUGF(TCP_DEBUG, ("\n")); LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent)); p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1)); 801e0c4: 7abb ldrb r3, [r7, #10] 801e0c6: b29c uxth r4, r3 801e0c8: 687b ldr r3, [r7, #4] 801e0ca: 6d1b ldr r3, [r3, #80] ; 0x50 801e0cc: 3b01 subs r3, #1 801e0ce: 4618 mov r0, r3 801e0d0: f7f7 ff4b bl 8015f6a 801e0d4: 4603 mov r3, r0 801e0d6: 2200 movs r2, #0 801e0d8: 4621 mov r1, r4 801e0da: 6878 ldr r0, [r7, #4] 801e0dc: f7ff fe68 bl 801ddb0 801e0e0: 60f8 str r0, [r7, #12] if (p == NULL) { 801e0e2: 68fb ldr r3, [r7, #12] 801e0e4: 2b00 cmp r3, #0 801e0e6: d102 bne.n 801e0ee LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n")); return ERR_MEM; 801e0e8: f04f 33ff mov.w r3, #4294967295 801e0ec: e010 b.n 801e110 } tcp_output_fill_options(pcb, p, 0, optlen); 801e0ee: 7abb ldrb r3, [r7, #10] 801e0f0: 2200 movs r2, #0 801e0f2: 68f9 ldr r1, [r7, #12] 801e0f4: 6878 ldr r0, [r7, #4] 801e0f6: f7ff fe99 bl 801de2c err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); 801e0fa: 687a ldr r2, [r7, #4] 801e0fc: 687b ldr r3, [r7, #4] 801e0fe: 3304 adds r3, #4 801e100: 68f9 ldr r1, [r7, #12] 801e102: 6878 ldr r0, [r7, #4] 801e104: f7ff fed0 bl 801dea8 801e108: 4603 mov r3, r0 801e10a: 72fb strb r3, [r7, #11] LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n", pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err)); return err; 801e10c: f997 300b ldrsb.w r3, [r7, #11] } 801e110: 4618 mov r0, r3 801e112: 3714 adds r7, #20 801e114: 46bd mov sp, r7 801e116: bd90 pop {r4, r7, pc} 801e118: 080257b8 .word 0x080257b8 801e11c: 08025ff0 .word 0x08025ff0 801e120: 0802580c .word 0x0802580c 0801e124 : * * @param pcb the tcp_pcb for which to send a zero-window probe packet */ err_t tcp_zero_window_probe(struct tcp_pcb *pcb) { 801e124: b590 push {r4, r7, lr} 801e126: b08b sub sp, #44 ; 0x2c 801e128: af00 add r7, sp, #0 801e12a: 6078 str r0, [r7, #4] struct tcp_hdr *tcphdr; struct tcp_seg *seg; u16_t len; u8_t is_fin; u32_t snd_nxt; u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); 801e12c: 2300 movs r3, #0 801e12e: 74fb strb r3, [r7, #19] LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL); 801e130: 687b ldr r3, [r7, #4] 801e132: 2b00 cmp r3, #0 801e134: d106 bne.n 801e144 801e136: 4b4d ldr r3, [pc, #308] ; (801e26c ) 801e138: f640 024f movw r2, #2127 ; 0x84f 801e13c: 494c ldr r1, [pc, #304] ; (801e270 ) 801e13e: 484d ldr r0, [pc, #308] ; (801e274 ) 801e140: f003 fc22 bl 8021988 ("tcp_zero_window_probe: tcp_ticks %"U32_F " pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent)); /* Only consider unsent, persist timer should be off when there is data in-flight */ seg = pcb->unsent; 801e144: 687b ldr r3, [r7, #4] 801e146: 6edb ldr r3, [r3, #108] ; 0x6c 801e148: 627b str r3, [r7, #36] ; 0x24 if (seg == NULL) { 801e14a: 6a7b ldr r3, [r7, #36] ; 0x24 801e14c: 2b00 cmp r3, #0 801e14e: d101 bne.n 801e154 /* Not expected, persist timer should be off when the send buffer is empty */ return ERR_OK; 801e150: 2300 movs r3, #0 801e152: e087 b.n 801e264 /* increment probe count. NOTE: we record probe even if it fails to actually transmit due to an error. This ensures memory exhaustion/ routing problem doesn't leave a zero-window pcb as an indefinite zombie. RTO mechanism has similar behavior, see pcb->nrtx */ if (pcb->persist_probe < 0xFF) { 801e154: 687b ldr r3, [r7, #4] 801e156: f893 309a ldrb.w r3, [r3, #154] ; 0x9a 801e15a: 2bff cmp r3, #255 ; 0xff 801e15c: d007 beq.n 801e16e ++pcb->persist_probe; 801e15e: 687b ldr r3, [r7, #4] 801e160: f893 309a ldrb.w r3, [r3, #154] ; 0x9a 801e164: 3301 adds r3, #1 801e166: b2da uxtb r2, r3 801e168: 687b ldr r3, [r7, #4] 801e16a: f883 209a strb.w r2, [r3, #154] ; 0x9a } is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0); 801e16e: 6a7b ldr r3, [r7, #36] ; 0x24 801e170: 691b ldr r3, [r3, #16] 801e172: 899b ldrh r3, [r3, #12] 801e174: b29b uxth r3, r3 801e176: 4618 mov r0, r3 801e178: f7f7 fee2 bl 8015f40 801e17c: 4603 mov r3, r0 801e17e: b2db uxtb r3, r3 801e180: f003 0301 and.w r3, r3, #1 801e184: 2b00 cmp r3, #0 801e186: d005 beq.n 801e194 801e188: 6a7b ldr r3, [r7, #36] ; 0x24 801e18a: 891b ldrh r3, [r3, #8] 801e18c: 2b00 cmp r3, #0 801e18e: d101 bne.n 801e194 801e190: 2301 movs r3, #1 801e192: e000 b.n 801e196 801e194: 2300 movs r3, #0 801e196: f887 3023 strb.w r3, [r7, #35] ; 0x23 /* we want to send one seqno: either FIN or data (no options) */ len = is_fin ? 0 : 1; 801e19a: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 801e19e: 2b00 cmp r3, #0 801e1a0: bf0c ite eq 801e1a2: 2301 moveq r3, #1 801e1a4: 2300 movne r3, #0 801e1a6: b2db uxtb r3, r3 801e1a8: 843b strh r3, [r7, #32] p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno); 801e1aa: 7cfb ldrb r3, [r7, #19] 801e1ac: b299 uxth r1, r3 801e1ae: 6a7b ldr r3, [r7, #36] ; 0x24 801e1b0: 691b ldr r3, [r3, #16] 801e1b2: 685b ldr r3, [r3, #4] 801e1b4: 8c3a ldrh r2, [r7, #32] 801e1b6: 6878 ldr r0, [r7, #4] 801e1b8: f7ff fdfa bl 801ddb0 801e1bc: 61f8 str r0, [r7, #28] if (p == NULL) { 801e1be: 69fb ldr r3, [r7, #28] 801e1c0: 2b00 cmp r3, #0 801e1c2: d102 bne.n 801e1ca LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n")); return ERR_MEM; 801e1c4: f04f 33ff mov.w r3, #4294967295 801e1c8: e04c b.n 801e264 } tcphdr = (struct tcp_hdr *)p->payload; 801e1ca: 69fb ldr r3, [r7, #28] 801e1cc: 685b ldr r3, [r3, #4] 801e1ce: 61bb str r3, [r7, #24] if (is_fin) { 801e1d0: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 801e1d4: 2b00 cmp r3, #0 801e1d6: d011 beq.n 801e1fc /* FIN segment, no data */ TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN); 801e1d8: 69bb ldr r3, [r7, #24] 801e1da: 899b ldrh r3, [r3, #12] 801e1dc: b29b uxth r3, r3 801e1de: b21b sxth r3, r3 801e1e0: f423 537c bic.w r3, r3, #16128 ; 0x3f00 801e1e4: b21c sxth r4, r3 801e1e6: 2011 movs r0, #17 801e1e8: f7f7 feaa bl 8015f40 801e1ec: 4603 mov r3, r0 801e1ee: b21b sxth r3, r3 801e1f0: 4323 orrs r3, r4 801e1f2: b21b sxth r3, r3 801e1f4: b29a uxth r2, r3 801e1f6: 69bb ldr r3, [r7, #24] 801e1f8: 819a strh r2, [r3, #12] 801e1fa: e010 b.n 801e21e } else { /* Data segment, copy in one byte from the head of the unacked queue */ char *d = ((char *)p->payload + TCP_HLEN); 801e1fc: 69fb ldr r3, [r7, #28] 801e1fe: 685b ldr r3, [r3, #4] 801e200: 3314 adds r3, #20 801e202: 617b str r3, [r7, #20] /* Depending on whether the segment has already been sent (unacked) or not (unsent), seg->p->payload points to the IP header or TCP header. Ensure we copy the first TCP data byte: */ pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len); 801e204: 6a7b ldr r3, [r7, #36] ; 0x24 801e206: 6858 ldr r0, [r3, #4] 801e208: 6a7b ldr r3, [r7, #36] ; 0x24 801e20a: 685b ldr r3, [r3, #4] 801e20c: 891a ldrh r2, [r3, #8] 801e20e: 6a7b ldr r3, [r7, #36] ; 0x24 801e210: 891b ldrh r3, [r3, #8] 801e212: 1ad3 subs r3, r2, r3 801e214: b29b uxth r3, r3 801e216: 2201 movs r2, #1 801e218: 6979 ldr r1, [r7, #20] 801e21a: f7f9 fe63 bl 8017ee4 } /* The byte may be acknowledged without the window being opened. */ snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1; 801e21e: 6a7b ldr r3, [r7, #36] ; 0x24 801e220: 691b ldr r3, [r3, #16] 801e222: 685b ldr r3, [r3, #4] 801e224: 4618 mov r0, r3 801e226: f7f7 fea0 bl 8015f6a 801e22a: 4603 mov r3, r0 801e22c: 3301 adds r3, #1 801e22e: 60fb str r3, [r7, #12] if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { 801e230: 687b ldr r3, [r7, #4] 801e232: 6d1a ldr r2, [r3, #80] ; 0x50 801e234: 68fb ldr r3, [r7, #12] 801e236: 1ad3 subs r3, r2, r3 801e238: 2b00 cmp r3, #0 801e23a: da02 bge.n 801e242 pcb->snd_nxt = snd_nxt; 801e23c: 687b ldr r3, [r7, #4] 801e23e: 68fa ldr r2, [r7, #12] 801e240: 651a str r2, [r3, #80] ; 0x50 } tcp_output_fill_options(pcb, p, 0, optlen); 801e242: 7cfb ldrb r3, [r7, #19] 801e244: 2200 movs r2, #0 801e246: 69f9 ldr r1, [r7, #28] 801e248: 6878 ldr r0, [r7, #4] 801e24a: f7ff fdef bl 801de2c err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); 801e24e: 687a ldr r2, [r7, #4] 801e250: 687b ldr r3, [r7, #4] 801e252: 3304 adds r3, #4 801e254: 69f9 ldr r1, [r7, #28] 801e256: 6878 ldr r0, [r7, #4] 801e258: f7ff fe26 bl 801dea8 801e25c: 4603 mov r3, r0 801e25e: 72fb strb r3, [r7, #11] LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F " ackno %"U32_F" err %d.\n", pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err)); return err; 801e260: f997 300b ldrsb.w r3, [r7, #11] } 801e264: 4618 mov r0, r3 801e266: 372c adds r7, #44 ; 0x2c 801e268: 46bd mov sp, r7 801e26a: bd90 pop {r4, r7, pc} 801e26c: 080257b8 .word 0x080257b8 801e270: 0802600c .word 0x0802600c 801e274: 0802580c .word 0x0802580c 0801e278 : * * @param arg unused argument */ static void tcpip_tcp_timer(void *arg) { 801e278: b580 push {r7, lr} 801e27a: b082 sub sp, #8 801e27c: af00 add r7, sp, #0 801e27e: 6078 str r0, [r7, #4] LWIP_UNUSED_ARG(arg); /* call TCP timer handler */ tcp_tmr(); 801e280: f7f9 ff1e bl 80180c0 /* timer still needed? */ if (tcp_active_pcbs || tcp_tw_pcbs) { 801e284: 4b0a ldr r3, [pc, #40] ; (801e2b0 ) 801e286: 681b ldr r3, [r3, #0] 801e288: 2b00 cmp r3, #0 801e28a: d103 bne.n 801e294 801e28c: 4b09 ldr r3, [pc, #36] ; (801e2b4 ) 801e28e: 681b ldr r3, [r3, #0] 801e290: 2b00 cmp r3, #0 801e292: d005 beq.n 801e2a0 /* restart timer */ sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); 801e294: 2200 movs r2, #0 801e296: 4908 ldr r1, [pc, #32] ; (801e2b8 ) 801e298: 20fa movs r0, #250 ; 0xfa 801e29a: f000 f8f3 bl 801e484 801e29e: e003 b.n 801e2a8 } else { /* disable timer */ tcpip_tcp_timer_active = 0; 801e2a0: 4b06 ldr r3, [pc, #24] ; (801e2bc ) 801e2a2: 2200 movs r2, #0 801e2a4: 601a str r2, [r3, #0] } } 801e2a6: bf00 nop 801e2a8: bf00 nop 801e2aa: 3708 adds r7, #8 801e2ac: 46bd mov sp, r7 801e2ae: bd80 pop {r7, pc} 801e2b0: 2401a48c .word 0x2401a48c 801e2b4: 2401a490 .word 0x2401a490 801e2b8: 0801e279 .word 0x0801e279 801e2bc: 2401a4dc .word 0x2401a4dc 0801e2c0 : * the reason is to have the TCP timer only running when * there are active (or time-wait) PCBs. */ void tcp_timer_needed(void) { 801e2c0: b580 push {r7, lr} 801e2c2: af00 add r7, sp, #0 LWIP_ASSERT_CORE_LOCKED(); /* timer is off but needed again? */ if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { 801e2c4: 4b0a ldr r3, [pc, #40] ; (801e2f0 ) 801e2c6: 681b ldr r3, [r3, #0] 801e2c8: 2b00 cmp r3, #0 801e2ca: d10f bne.n 801e2ec 801e2cc: 4b09 ldr r3, [pc, #36] ; (801e2f4 ) 801e2ce: 681b ldr r3, [r3, #0] 801e2d0: 2b00 cmp r3, #0 801e2d2: d103 bne.n 801e2dc 801e2d4: 4b08 ldr r3, [pc, #32] ; (801e2f8 ) 801e2d6: 681b ldr r3, [r3, #0] 801e2d8: 2b00 cmp r3, #0 801e2da: d007 beq.n 801e2ec /* enable and start timer */ tcpip_tcp_timer_active = 1; 801e2dc: 4b04 ldr r3, [pc, #16] ; (801e2f0 ) 801e2de: 2201 movs r2, #1 801e2e0: 601a str r2, [r3, #0] sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); 801e2e2: 2200 movs r2, #0 801e2e4: 4905 ldr r1, [pc, #20] ; (801e2fc ) 801e2e6: 20fa movs r0, #250 ; 0xfa 801e2e8: f000 f8cc bl 801e484 } } 801e2ec: bf00 nop 801e2ee: bd80 pop {r7, pc} 801e2f0: 2401a4dc .word 0x2401a4dc 801e2f4: 2401a48c .word 0x2401a48c 801e2f8: 2401a490 .word 0x2401a490 801e2fc: 0801e279 .word 0x0801e279 0801e300 : #if LWIP_DEBUG_TIMERNAMES sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name) #else /* LWIP_DEBUG_TIMERNAMES */ sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg) #endif { 801e300: b580 push {r7, lr} 801e302: b086 sub sp, #24 801e304: af00 add r7, sp, #0 801e306: 60f8 str r0, [r7, #12] 801e308: 60b9 str r1, [r7, #8] 801e30a: 607a str r2, [r7, #4] struct sys_timeo *timeout, *t; timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT); 801e30c: 200a movs r0, #10 801e30e: f7f8 fbdf bl 8016ad0 801e312: 6138 str r0, [r7, #16] if (timeout == NULL) { 801e314: 693b ldr r3, [r7, #16] 801e316: 2b00 cmp r3, #0 801e318: d109 bne.n 801e32e LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL); 801e31a: 693b ldr r3, [r7, #16] 801e31c: 2b00 cmp r3, #0 801e31e: d151 bne.n 801e3c4 801e320: 4b2a ldr r3, [pc, #168] ; (801e3cc ) 801e322: 22be movs r2, #190 ; 0xbe 801e324: 492a ldr r1, [pc, #168] ; (801e3d0 ) 801e326: 482b ldr r0, [pc, #172] ; (801e3d4 ) 801e328: f003 fb2e bl 8021988 return; 801e32c: e04a b.n 801e3c4 } timeout->next = NULL; 801e32e: 693b ldr r3, [r7, #16] 801e330: 2200 movs r2, #0 801e332: 601a str r2, [r3, #0] timeout->h = handler; 801e334: 693b ldr r3, [r7, #16] 801e336: 68ba ldr r2, [r7, #8] 801e338: 609a str r2, [r3, #8] timeout->arg = arg; 801e33a: 693b ldr r3, [r7, #16] 801e33c: 687a ldr r2, [r7, #4] 801e33e: 60da str r2, [r3, #12] timeout->time = abs_time; 801e340: 693b ldr r3, [r7, #16] 801e342: 68fa ldr r2, [r7, #12] 801e344: 605a str r2, [r3, #4] timeout->handler_name = handler_name; LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n", (void *)timeout, abs_time, handler_name, (void *)arg)); #endif /* LWIP_DEBUG_TIMERNAMES */ if (next_timeout == NULL) { 801e346: 4b24 ldr r3, [pc, #144] ; (801e3d8 ) 801e348: 681b ldr r3, [r3, #0] 801e34a: 2b00 cmp r3, #0 801e34c: d103 bne.n 801e356 next_timeout = timeout; 801e34e: 4a22 ldr r2, [pc, #136] ; (801e3d8 ) 801e350: 693b ldr r3, [r7, #16] 801e352: 6013 str r3, [r2, #0] return; 801e354: e037 b.n 801e3c6 } if (TIME_LESS_THAN(timeout->time, next_timeout->time)) { 801e356: 693b ldr r3, [r7, #16] 801e358: 685a ldr r2, [r3, #4] 801e35a: 4b1f ldr r3, [pc, #124] ; (801e3d8 ) 801e35c: 681b ldr r3, [r3, #0] 801e35e: 685b ldr r3, [r3, #4] 801e360: 1ad3 subs r3, r2, r3 801e362: 0fdb lsrs r3, r3, #31 801e364: f003 0301 and.w r3, r3, #1 801e368: b2db uxtb r3, r3 801e36a: 2b00 cmp r3, #0 801e36c: d007 beq.n 801e37e timeout->next = next_timeout; 801e36e: 4b1a ldr r3, [pc, #104] ; (801e3d8 ) 801e370: 681a ldr r2, [r3, #0] 801e372: 693b ldr r3, [r7, #16] 801e374: 601a str r2, [r3, #0] next_timeout = timeout; 801e376: 4a18 ldr r2, [pc, #96] ; (801e3d8 ) 801e378: 693b ldr r3, [r7, #16] 801e37a: 6013 str r3, [r2, #0] 801e37c: e023 b.n 801e3c6 } else { for (t = next_timeout; t != NULL; t = t->next) { 801e37e: 4b16 ldr r3, [pc, #88] ; (801e3d8 ) 801e380: 681b ldr r3, [r3, #0] 801e382: 617b str r3, [r7, #20] 801e384: e01a b.n 801e3bc if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) { 801e386: 697b ldr r3, [r7, #20] 801e388: 681b ldr r3, [r3, #0] 801e38a: 2b00 cmp r3, #0 801e38c: d00b beq.n 801e3a6 801e38e: 693b ldr r3, [r7, #16] 801e390: 685a ldr r2, [r3, #4] 801e392: 697b ldr r3, [r7, #20] 801e394: 681b ldr r3, [r3, #0] 801e396: 685b ldr r3, [r3, #4] 801e398: 1ad3 subs r3, r2, r3 801e39a: 0fdb lsrs r3, r3, #31 801e39c: f003 0301 and.w r3, r3, #1 801e3a0: b2db uxtb r3, r3 801e3a2: 2b00 cmp r3, #0 801e3a4: d007 beq.n 801e3b6 timeout->next = t->next; 801e3a6: 697b ldr r3, [r7, #20] 801e3a8: 681a ldr r2, [r3, #0] 801e3aa: 693b ldr r3, [r7, #16] 801e3ac: 601a str r2, [r3, #0] t->next = timeout; 801e3ae: 697b ldr r3, [r7, #20] 801e3b0: 693a ldr r2, [r7, #16] 801e3b2: 601a str r2, [r3, #0] break; 801e3b4: e007 b.n 801e3c6 for (t = next_timeout; t != NULL; t = t->next) { 801e3b6: 697b ldr r3, [r7, #20] 801e3b8: 681b ldr r3, [r3, #0] 801e3ba: 617b str r3, [r7, #20] 801e3bc: 697b ldr r3, [r7, #20] 801e3be: 2b00 cmp r3, #0 801e3c0: d1e1 bne.n 801e386 801e3c2: e000 b.n 801e3c6 return; 801e3c4: bf00 nop } } } } 801e3c6: 3718 adds r7, #24 801e3c8: 46bd mov sp, r7 801e3ca: bd80 pop {r7, pc} 801e3cc: 08026030 .word 0x08026030 801e3d0: 08026064 .word 0x08026064 801e3d4: 080260a4 .word 0x080260a4 801e3d8: 2401a4d4 .word 0x2401a4d4 0801e3dc : #if !LWIP_TESTMODE static #endif void lwip_cyclic_timer(void *arg) { 801e3dc: b580 push {r7, lr} 801e3de: b086 sub sp, #24 801e3e0: af00 add r7, sp, #0 801e3e2: 6078 str r0, [r7, #4] u32_t now; u32_t next_timeout_time; const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg; 801e3e4: 687b ldr r3, [r7, #4] 801e3e6: 617b str r3, [r7, #20] #if LWIP_DEBUG_TIMERNAMES LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name)); #endif cyclic->handler(); 801e3e8: 697b ldr r3, [r7, #20] 801e3ea: 685b ldr r3, [r3, #4] 801e3ec: 4798 blx r3 now = sys_now(); 801e3ee: f7f1 fc97 bl 800fd20 801e3f2: 6138 str r0, [r7, #16] next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms); /* overflow handled by TIME_LESS_THAN macro */ 801e3f4: 697b ldr r3, [r7, #20] 801e3f6: 681a ldr r2, [r3, #0] 801e3f8: 4b0f ldr r3, [pc, #60] ; (801e438 ) 801e3fa: 681b ldr r3, [r3, #0] 801e3fc: 4413 add r3, r2 801e3fe: 60fb str r3, [r7, #12] if (TIME_LESS_THAN(next_timeout_time, now)) { 801e400: 68fa ldr r2, [r7, #12] 801e402: 693b ldr r3, [r7, #16] 801e404: 1ad3 subs r3, r2, r3 801e406: 0fdb lsrs r3, r3, #31 801e408: f003 0301 and.w r3, r3, #1 801e40c: b2db uxtb r3, r3 801e40e: 2b00 cmp r3, #0 801e410: d009 beq.n 801e426 /* timer would immediately expire again -> "overload" -> restart without any correction */ #if LWIP_DEBUG_TIMERNAMES sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name); #else sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg); 801e412: 697b ldr r3, [r7, #20] 801e414: 681a ldr r2, [r3, #0] 801e416: 693b ldr r3, [r7, #16] 801e418: 4413 add r3, r2 801e41a: 687a ldr r2, [r7, #4] 801e41c: 4907 ldr r1, [pc, #28] ; (801e43c ) 801e41e: 4618 mov r0, r3 801e420: f7ff ff6e bl 801e300 sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name); #else sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg); #endif } } 801e424: e004 b.n 801e430 sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg); 801e426: 687a ldr r2, [r7, #4] 801e428: 4904 ldr r1, [pc, #16] ; (801e43c ) 801e42a: 68f8 ldr r0, [r7, #12] 801e42c: f7ff ff68 bl 801e300 } 801e430: bf00 nop 801e432: 3718 adds r7, #24 801e434: 46bd mov sp, r7 801e436: bd80 pop {r7, pc} 801e438: 2401a4d8 .word 0x2401a4d8 801e43c: 0801e3dd .word 0x0801e3dd 0801e440 : /** Initialize this module */ void sys_timeouts_init(void) { 801e440: b580 push {r7, lr} 801e442: b082 sub sp, #8 801e444: af00 add r7, sp, #0 size_t i; /* tcp_tmr() at index 0 is started on demand */ for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) { 801e446: 2301 movs r3, #1 801e448: 607b str r3, [r7, #4] 801e44a: e00e b.n 801e46a /* we have to cast via size_t to get rid of const warning (this is OK as cyclic_timer() casts back to const* */ sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i])); 801e44c: 4a0b ldr r2, [pc, #44] ; (801e47c ) 801e44e: 687b ldr r3, [r7, #4] 801e450: f852 0033 ldr.w r0, [r2, r3, lsl #3] 801e454: 687b ldr r3, [r7, #4] 801e456: 00db lsls r3, r3, #3 801e458: 4a08 ldr r2, [pc, #32] ; (801e47c ) 801e45a: 4413 add r3, r2 801e45c: 461a mov r2, r3 801e45e: 4908 ldr r1, [pc, #32] ; (801e480 ) 801e460: f000 f810 bl 801e484 for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) { 801e464: 687b ldr r3, [r7, #4] 801e466: 3301 adds r3, #1 801e468: 607b str r3, [r7, #4] 801e46a: 687b ldr r3, [r7, #4] 801e46c: 2b02 cmp r3, #2 801e46e: d9ed bls.n 801e44c } } 801e470: bf00 nop 801e472: bf00 nop 801e474: 3708 adds r7, #8 801e476: 46bd mov sp, r7 801e478: bd80 pop {r7, pc} 801e47a: bf00 nop 801e47c: 08026cd4 .word 0x08026cd4 801e480: 0801e3dd .word 0x0801e3dd 0801e484 : sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name) #else /* LWIP_DEBUG_TIMERNAMES */ void sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg) #endif /* LWIP_DEBUG_TIMERNAMES */ { 801e484: b580 push {r7, lr} 801e486: b086 sub sp, #24 801e488: af00 add r7, sp, #0 801e48a: 60f8 str r0, [r7, #12] 801e48c: 60b9 str r1, [r7, #8] 801e48e: 607a str r2, [r7, #4] u32_t next_timeout_time; LWIP_ASSERT_CORE_LOCKED(); LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4)); 801e490: 68fb ldr r3, [r7, #12] 801e492: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 801e496: d306 bcc.n 801e4a6 801e498: 4b0a ldr r3, [pc, #40] ; (801e4c4 ) 801e49a: f240 1229 movw r2, #297 ; 0x129 801e49e: 490a ldr r1, [pc, #40] ; (801e4c8 ) 801e4a0: 480a ldr r0, [pc, #40] ; (801e4cc ) 801e4a2: f003 fa71 bl 8021988 next_timeout_time = (u32_t)(sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */ 801e4a6: f7f1 fc3b bl 800fd20 801e4aa: 4602 mov r2, r0 801e4ac: 68fb ldr r3, [r7, #12] 801e4ae: 4413 add r3, r2 801e4b0: 617b str r3, [r7, #20] #if LWIP_DEBUG_TIMERNAMES sys_timeout_abs(next_timeout_time, handler, arg, handler_name); #else sys_timeout_abs(next_timeout_time, handler, arg); 801e4b2: 687a ldr r2, [r7, #4] 801e4b4: 68b9 ldr r1, [r7, #8] 801e4b6: 6978 ldr r0, [r7, #20] 801e4b8: f7ff ff22 bl 801e300 #endif } 801e4bc: bf00 nop 801e4be: 3718 adds r7, #24 801e4c0: 46bd mov sp, r7 801e4c2: bd80 pop {r7, pc} 801e4c4: 08026030 .word 0x08026030 801e4c8: 080260cc .word 0x080260cc 801e4cc: 080260a4 .word 0x080260a4 0801e4d0 : * * Must be called periodically from your main loop. */ void sys_check_timeouts(void) { 801e4d0: b580 push {r7, lr} 801e4d2: b084 sub sp, #16 801e4d4: af00 add r7, sp, #0 u32_t now; LWIP_ASSERT_CORE_LOCKED(); /* Process only timers expired at the start of the function. */ now = sys_now(); 801e4d6: f7f1 fc23 bl 800fd20 801e4da: 60f8 str r0, [r7, #12] sys_timeout_handler handler; void *arg; PBUF_CHECK_FREE_OOSEQ(); tmptimeout = next_timeout; 801e4dc: 4b17 ldr r3, [pc, #92] ; (801e53c ) 801e4de: 681b ldr r3, [r3, #0] 801e4e0: 60bb str r3, [r7, #8] if (tmptimeout == NULL) { 801e4e2: 68bb ldr r3, [r7, #8] 801e4e4: 2b00 cmp r3, #0 801e4e6: d022 beq.n 801e52e return; } if (TIME_LESS_THAN(now, tmptimeout->time)) { 801e4e8: 68bb ldr r3, [r7, #8] 801e4ea: 685b ldr r3, [r3, #4] 801e4ec: 68fa ldr r2, [r7, #12] 801e4ee: 1ad3 subs r3, r2, r3 801e4f0: 0fdb lsrs r3, r3, #31 801e4f2: f003 0301 and.w r3, r3, #1 801e4f6: b2db uxtb r3, r3 801e4f8: 2b00 cmp r3, #0 801e4fa: d11a bne.n 801e532 return; } /* Timeout has expired */ next_timeout = tmptimeout->next; 801e4fc: 68bb ldr r3, [r7, #8] 801e4fe: 681b ldr r3, [r3, #0] 801e500: 4a0e ldr r2, [pc, #56] ; (801e53c ) 801e502: 6013 str r3, [r2, #0] handler = tmptimeout->h; 801e504: 68bb ldr r3, [r7, #8] 801e506: 689b ldr r3, [r3, #8] 801e508: 607b str r3, [r7, #4] arg = tmptimeout->arg; 801e50a: 68bb ldr r3, [r7, #8] 801e50c: 68db ldr r3, [r3, #12] 801e50e: 603b str r3, [r7, #0] current_timeout_due_time = tmptimeout->time; 801e510: 68bb ldr r3, [r7, #8] 801e512: 685b ldr r3, [r3, #4] 801e514: 4a0a ldr r2, [pc, #40] ; (801e540 ) 801e516: 6013 str r3, [r2, #0] if (handler != NULL) { LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n", tmptimeout->handler_name, sys_now() - tmptimeout->time, arg)); } #endif /* LWIP_DEBUG_TIMERNAMES */ memp_free(MEMP_SYS_TIMEOUT, tmptimeout); 801e518: 68b9 ldr r1, [r7, #8] 801e51a: 200a movs r0, #10 801e51c: f7f8 fb4e bl 8016bbc if (handler != NULL) { 801e520: 687b ldr r3, [r7, #4] 801e522: 2b00 cmp r3, #0 801e524: d0da beq.n 801e4dc handler(arg); 801e526: 687b ldr r3, [r7, #4] 801e528: 6838 ldr r0, [r7, #0] 801e52a: 4798 blx r3 do { 801e52c: e7d6 b.n 801e4dc return; 801e52e: bf00 nop 801e530: e000 b.n 801e534 return; 801e532: bf00 nop } LWIP_TCPIP_THREAD_ALIVE(); /* Repeat until all expired timers have been called */ } while (1); } 801e534: 3710 adds r7, #16 801e536: 46bd mov sp, r7 801e538: bd80 pop {r7, pc} 801e53a: bf00 nop 801e53c: 2401a4d4 .word 0x2401a4d4 801e540: 2401a4d8 .word 0x2401a4d8 0801e544 : /** Return the time left before the next timeout is due. If no timeouts are * enqueued, returns 0xffffffff */ u32_t sys_timeouts_sleeptime(void) { 801e544: b580 push {r7, lr} 801e546: b082 sub sp, #8 801e548: af00 add r7, sp, #0 u32_t now; LWIP_ASSERT_CORE_LOCKED(); if (next_timeout == NULL) { 801e54a: 4b16 ldr r3, [pc, #88] ; (801e5a4 ) 801e54c: 681b ldr r3, [r3, #0] 801e54e: 2b00 cmp r3, #0 801e550: d102 bne.n 801e558 return SYS_TIMEOUTS_SLEEPTIME_INFINITE; 801e552: f04f 33ff mov.w r3, #4294967295 801e556: e020 b.n 801e59a } now = sys_now(); 801e558: f7f1 fbe2 bl 800fd20 801e55c: 6078 str r0, [r7, #4] if (TIME_LESS_THAN(next_timeout->time, now)) { 801e55e: 4b11 ldr r3, [pc, #68] ; (801e5a4 ) 801e560: 681b ldr r3, [r3, #0] 801e562: 685a ldr r2, [r3, #4] 801e564: 687b ldr r3, [r7, #4] 801e566: 1ad3 subs r3, r2, r3 801e568: 0fdb lsrs r3, r3, #31 801e56a: f003 0301 and.w r3, r3, #1 801e56e: b2db uxtb r3, r3 801e570: 2b00 cmp r3, #0 801e572: d001 beq.n 801e578 return 0; 801e574: 2300 movs r3, #0 801e576: e010 b.n 801e59a } else { u32_t ret = (u32_t)(next_timeout->time - now); 801e578: 4b0a ldr r3, [pc, #40] ; (801e5a4 ) 801e57a: 681b ldr r3, [r3, #0] 801e57c: 685a ldr r2, [r3, #4] 801e57e: 687b ldr r3, [r7, #4] 801e580: 1ad3 subs r3, r2, r3 801e582: 603b str r3, [r7, #0] LWIP_ASSERT("invalid sleeptime", ret <= LWIP_MAX_TIMEOUT); 801e584: 683b ldr r3, [r7, #0] 801e586: 2b00 cmp r3, #0 801e588: da06 bge.n 801e598 801e58a: 4b07 ldr r3, [pc, #28] ; (801e5a8 ) 801e58c: f44f 72dc mov.w r2, #440 ; 0x1b8 801e590: 4906 ldr r1, [pc, #24] ; (801e5ac ) 801e592: 4807 ldr r0, [pc, #28] ; (801e5b0 ) 801e594: f003 f9f8 bl 8021988 return ret; 801e598: 683b ldr r3, [r7, #0] } } 801e59a: 4618 mov r0, r3 801e59c: 3708 adds r7, #8 801e59e: 46bd mov sp, r7 801e5a0: bd80 pop {r7, pc} 801e5a2: bf00 nop 801e5a4: 2401a4d4 .word 0x2401a4d4 801e5a8: 08026030 .word 0x08026030 801e5ac: 08026104 .word 0x08026104 801e5b0: 080260a4 .word 0x080260a4 0801e5b4 : /** * Initialize this module. */ void udp_init(void) { 801e5b4: b580 push {r7, lr} 801e5b6: af00 add r7, sp, #0 #ifdef LWIP_RAND udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND()); 801e5b8: f003 f86a bl 8021690 801e5bc: 4603 mov r3, r0 801e5be: b29b uxth r3, r3 801e5c0: f3c3 030d ubfx r3, r3, #0, #14 801e5c4: b29b uxth r3, r3 801e5c6: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000 801e5ca: b29a uxth r2, r3 801e5cc: 4b01 ldr r3, [pc, #4] ; (801e5d4 ) 801e5ce: 801a strh r2, [r3, #0] #endif /* LWIP_RAND */ } 801e5d0: bf00 nop 801e5d2: bd80 pop {r7, pc} 801e5d4: 24000044 .word 0x24000044 0801e5d8 : * * @return a new (free) local UDP port number */ static u16_t udp_new_port(void) { 801e5d8: b480 push {r7} 801e5da: b083 sub sp, #12 801e5dc: af00 add r7, sp, #0 u16_t n = 0; 801e5de: 2300 movs r3, #0 801e5e0: 80fb strh r3, [r7, #6] struct udp_pcb *pcb; again: if (udp_port++ == UDP_LOCAL_PORT_RANGE_END) { 801e5e2: 4b17 ldr r3, [pc, #92] ; (801e640 ) 801e5e4: 881b ldrh r3, [r3, #0] 801e5e6: 1c5a adds r2, r3, #1 801e5e8: b291 uxth r1, r2 801e5ea: 4a15 ldr r2, [pc, #84] ; (801e640 ) 801e5ec: 8011 strh r1, [r2, #0] 801e5ee: f64f 72ff movw r2, #65535 ; 0xffff 801e5f2: 4293 cmp r3, r2 801e5f4: d103 bne.n 801e5fe udp_port = UDP_LOCAL_PORT_RANGE_START; 801e5f6: 4b12 ldr r3, [pc, #72] ; (801e640 ) 801e5f8: f44f 4240 mov.w r2, #49152 ; 0xc000 801e5fc: 801a strh r2, [r3, #0] } /* Check all PCBs. */ for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { 801e5fe: 4b11 ldr r3, [pc, #68] ; (801e644 ) 801e600: 681b ldr r3, [r3, #0] 801e602: 603b str r3, [r7, #0] 801e604: e011 b.n 801e62a if (pcb->local_port == udp_port) { 801e606: 683b ldr r3, [r7, #0] 801e608: 8a5a ldrh r2, [r3, #18] 801e60a: 4b0d ldr r3, [pc, #52] ; (801e640 ) 801e60c: 881b ldrh r3, [r3, #0] 801e60e: 429a cmp r2, r3 801e610: d108 bne.n 801e624 if (++n > (UDP_LOCAL_PORT_RANGE_END - UDP_LOCAL_PORT_RANGE_START)) { 801e612: 88fb ldrh r3, [r7, #6] 801e614: 3301 adds r3, #1 801e616: 80fb strh r3, [r7, #6] 801e618: 88fb ldrh r3, [r7, #6] 801e61a: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 801e61e: d3e0 bcc.n 801e5e2 return 0; 801e620: 2300 movs r3, #0 801e622: e007 b.n 801e634 for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { 801e624: 683b ldr r3, [r7, #0] 801e626: 68db ldr r3, [r3, #12] 801e628: 603b str r3, [r7, #0] 801e62a: 683b ldr r3, [r7, #0] 801e62c: 2b00 cmp r3, #0 801e62e: d1ea bne.n 801e606 } goto again; } } return udp_port; 801e630: 4b03 ldr r3, [pc, #12] ; (801e640 ) 801e632: 881b ldrh r3, [r3, #0] } 801e634: 4618 mov r0, r3 801e636: 370c adds r7, #12 801e638: 46bd mov sp, r7 801e63a: f85d 7b04 ldr.w r7, [sp], #4 801e63e: 4770 bx lr 801e640: 24000044 .word 0x24000044 801e644: 2401a4e0 .word 0x2401a4e0 0801e648 : * @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4) * @return 1 on match, 0 otherwise */ static u8_t udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast) { 801e648: b580 push {r7, lr} 801e64a: b084 sub sp, #16 801e64c: af00 add r7, sp, #0 801e64e: 60f8 str r0, [r7, #12] 801e650: 60b9 str r1, [r7, #8] 801e652: 4613 mov r3, r2 801e654: 71fb strb r3, [r7, #7] LWIP_UNUSED_ARG(inp); /* in IPv6 only case */ LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */ LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL); 801e656: 68fb ldr r3, [r7, #12] 801e658: 2b00 cmp r3, #0 801e65a: d105 bne.n 801e668 801e65c: 4b27 ldr r3, [pc, #156] ; (801e6fc ) 801e65e: 2287 movs r2, #135 ; 0x87 801e660: 4927 ldr r1, [pc, #156] ; (801e700 ) 801e662: 4828 ldr r0, [pc, #160] ; (801e704 ) 801e664: f003 f990 bl 8021988 LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL); 801e668: 68bb ldr r3, [r7, #8] 801e66a: 2b00 cmp r3, #0 801e66c: d105 bne.n 801e67a 801e66e: 4b23 ldr r3, [pc, #140] ; (801e6fc ) 801e670: 2288 movs r2, #136 ; 0x88 801e672: 4925 ldr r1, [pc, #148] ; (801e708 ) 801e674: 4823 ldr r0, [pc, #140] ; (801e704 ) 801e676: f003 f987 bl 8021988 /* check if PCB is bound to specific netif */ if ((pcb->netif_idx != NETIF_NO_INDEX) && 801e67a: 68fb ldr r3, [r7, #12] 801e67c: 7a1b ldrb r3, [r3, #8] 801e67e: 2b00 cmp r3, #0 801e680: d00b beq.n 801e69a (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { 801e682: 68fb ldr r3, [r7, #12] 801e684: 7a1a ldrb r2, [r3, #8] 801e686: 4b21 ldr r3, [pc, #132] ; (801e70c ) 801e688: 685b ldr r3, [r3, #4] 801e68a: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 801e68e: 3301 adds r3, #1 801e690: b2db uxtb r3, r3 if ((pcb->netif_idx != NETIF_NO_INDEX) && 801e692: 429a cmp r2, r3 801e694: d001 beq.n 801e69a return 0; 801e696: 2300 movs r3, #0 801e698: e02b b.n 801e6f2 /* Only need to check PCB if incoming IP version matches PCB IP version */ if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) { #if LWIP_IPV4 /* Special case: IPv4 broadcast: all or broadcasts in my subnet * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */ if (broadcast != 0) { 801e69a: 79fb ldrb r3, [r7, #7] 801e69c: 2b00 cmp r3, #0 801e69e: d018 beq.n 801e6d2 #if IP_SOF_BROADCAST_RECV if (ip_get_option(pcb, SOF_BROADCAST)) #endif /* IP_SOF_BROADCAST_RECV */ { if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || 801e6a0: 68fb ldr r3, [r7, #12] 801e6a2: 2b00 cmp r3, #0 801e6a4: d013 beq.n 801e6ce 801e6a6: 68fb ldr r3, [r7, #12] 801e6a8: 681b ldr r3, [r3, #0] 801e6aa: 2b00 cmp r3, #0 801e6ac: d00f beq.n 801e6ce ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) || 801e6ae: 4b17 ldr r3, [pc, #92] ; (801e70c ) 801e6b0: 695b ldr r3, [r3, #20] if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || 801e6b2: f1b3 3fff cmp.w r3, #4294967295 801e6b6: d00a beq.n 801e6ce ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) { 801e6b8: 68fb ldr r3, [r7, #12] 801e6ba: 681a ldr r2, [r3, #0] 801e6bc: 4b13 ldr r3, [pc, #76] ; (801e70c ) 801e6be: 695b ldr r3, [r3, #20] 801e6c0: 405a eors r2, r3 801e6c2: 68bb ldr r3, [r7, #8] 801e6c4: 3308 adds r3, #8 801e6c6: 681b ldr r3, [r3, #0] 801e6c8: 4013 ands r3, r2 ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) || 801e6ca: 2b00 cmp r3, #0 801e6cc: d110 bne.n 801e6f0 return 1; 801e6ce: 2301 movs r3, #1 801e6d0: e00f b.n 801e6f2 } } } else #endif /* LWIP_IPV4 */ /* Handle IPv4 and IPv6: all or exact match */ if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { 801e6d2: 68fb ldr r3, [r7, #12] 801e6d4: 2b00 cmp r3, #0 801e6d6: d009 beq.n 801e6ec 801e6d8: 68fb ldr r3, [r7, #12] 801e6da: 681b ldr r3, [r3, #0] 801e6dc: 2b00 cmp r3, #0 801e6de: d005 beq.n 801e6ec 801e6e0: 68fb ldr r3, [r7, #12] 801e6e2: 681a ldr r2, [r3, #0] 801e6e4: 4b09 ldr r3, [pc, #36] ; (801e70c ) 801e6e6: 695b ldr r3, [r3, #20] 801e6e8: 429a cmp r2, r3 801e6ea: d101 bne.n 801e6f0 return 1; 801e6ec: 2301 movs r3, #1 801e6ee: e000 b.n 801e6f2 } } return 0; 801e6f0: 2300 movs r3, #0 } 801e6f2: 4618 mov r0, r3 801e6f4: 3710 adds r7, #16 801e6f6: 46bd mov sp, r7 801e6f8: bd80 pop {r7, pc} 801e6fa: bf00 nop 801e6fc: 08026118 .word 0x08026118 801e700: 08026148 .word 0x08026148 801e704: 0802616c .word 0x0802616c 801e708: 08026194 .word 0x08026194 801e70c: 24013980 .word 0x24013980 0801e710 : * @param inp network interface on which the datagram was received. * */ void udp_input(struct pbuf *p, struct netif *inp) { 801e710: b590 push {r4, r7, lr} 801e712: b08d sub sp, #52 ; 0x34 801e714: af02 add r7, sp, #8 801e716: 6078 str r0, [r7, #4] 801e718: 6039 str r1, [r7, #0] struct udp_hdr *udphdr; struct udp_pcb *pcb, *prev; struct udp_pcb *uncon_pcb; u16_t src, dest; u8_t broadcast; u8_t for_us = 0; 801e71a: 2300 movs r3, #0 801e71c: 77fb strb r3, [r7, #31] LWIP_UNUSED_ARG(inp); LWIP_ASSERT_CORE_LOCKED(); LWIP_ASSERT("udp_input: invalid pbuf", p != NULL); 801e71e: 687b ldr r3, [r7, #4] 801e720: 2b00 cmp r3, #0 801e722: d105 bne.n 801e730 801e724: 4b7c ldr r3, [pc, #496] ; (801e918 ) 801e726: 22cf movs r2, #207 ; 0xcf 801e728: 497c ldr r1, [pc, #496] ; (801e91c ) 801e72a: 487d ldr r0, [pc, #500] ; (801e920 ) 801e72c: f003 f92c bl 8021988 LWIP_ASSERT("udp_input: invalid netif", inp != NULL); 801e730: 683b ldr r3, [r7, #0] 801e732: 2b00 cmp r3, #0 801e734: d105 bne.n 801e742 801e736: 4b78 ldr r3, [pc, #480] ; (801e918 ) 801e738: 22d0 movs r2, #208 ; 0xd0 801e73a: 497a ldr r1, [pc, #488] ; (801e924 ) 801e73c: 4878 ldr r0, [pc, #480] ; (801e920 ) 801e73e: f003 f923 bl 8021988 PERF_START; UDP_STATS_INC(udp.recv); /* Check minimum length (UDP header) */ if (p->len < UDP_HLEN) { 801e742: 687b ldr r3, [r7, #4] 801e744: 895b ldrh r3, [r3, #10] 801e746: 2b07 cmp r3, #7 801e748: d803 bhi.n 801e752 LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); UDP_STATS_INC(udp.lenerr); UDP_STATS_INC(udp.drop); MIB2_STATS_INC(mib2.udpinerrors); pbuf_free(p); 801e74a: 6878 ldr r0, [r7, #4] 801e74c: f7f9 f9d4 bl 8017af8 goto end; 801e750: e0de b.n 801e910 } udphdr = (struct udp_hdr *)p->payload; 801e752: 687b ldr r3, [r7, #4] 801e754: 685b ldr r3, [r3, #4] 801e756: 617b str r3, [r7, #20] /* is broadcast packet ? */ broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()); 801e758: 4b73 ldr r3, [pc, #460] ; (801e928 ) 801e75a: 695b ldr r3, [r3, #20] 801e75c: 4a72 ldr r2, [pc, #456] ; (801e928 ) 801e75e: 6812 ldr r2, [r2, #0] 801e760: 4611 mov r1, r2 801e762: 4618 mov r0, r3 801e764: f001 fe5c bl 8020420 801e768: 4603 mov r3, r0 801e76a: 74fb strb r3, [r7, #19] LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); /* convert src and dest ports to host byte order */ src = lwip_ntohs(udphdr->src); 801e76c: 697b ldr r3, [r7, #20] 801e76e: 881b ldrh r3, [r3, #0] 801e770: b29b uxth r3, r3 801e772: 4618 mov r0, r3 801e774: f7f7 fbe4 bl 8015f40 801e778: 4603 mov r3, r0 801e77a: 823b strh r3, [r7, #16] dest = lwip_ntohs(udphdr->dest); 801e77c: 697b ldr r3, [r7, #20] 801e77e: 885b ldrh r3, [r3, #2] 801e780: b29b uxth r3, r3 801e782: 4618 mov r0, r3 801e784: f7f7 fbdc bl 8015f40 801e788: 4603 mov r3, r0 801e78a: 81fb strh r3, [r7, #14] ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr()); LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest))); ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr()); LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src))); pcb = NULL; 801e78c: 2300 movs r3, #0 801e78e: 623b str r3, [r7, #32] prev = NULL; 801e790: 2300 movs r3, #0 801e792: 627b str r3, [r7, #36] ; 0x24 uncon_pcb = NULL; 801e794: 2300 movs r3, #0 801e796: 61bb str r3, [r7, #24] /* Iterate through the UDP pcb list for a matching pcb. * 'Perfect match' pcbs (connected to the remote port & ip address) are * preferred. If no perfect match is found, the first unconnected pcb that * matches the local port and ip address gets the datagram. */ for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { 801e798: 4b64 ldr r3, [pc, #400] ; (801e92c ) 801e79a: 681b ldr r3, [r3, #0] 801e79c: 623b str r3, [r7, #32] 801e79e: e054 b.n 801e84a LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port)); ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip); LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port)); /* compare PCB local addr+port to UDP destination addr+port */ if ((pcb->local_port == dest) && 801e7a0: 6a3b ldr r3, [r7, #32] 801e7a2: 8a5b ldrh r3, [r3, #18] 801e7a4: 89fa ldrh r2, [r7, #14] 801e7a6: 429a cmp r2, r3 801e7a8: d14a bne.n 801e840 (udp_input_local_match(pcb, inp, broadcast) != 0)) { 801e7aa: 7cfb ldrb r3, [r7, #19] 801e7ac: 461a mov r2, r3 801e7ae: 6839 ldr r1, [r7, #0] 801e7b0: 6a38 ldr r0, [r7, #32] 801e7b2: f7ff ff49 bl 801e648 801e7b6: 4603 mov r3, r0 if ((pcb->local_port == dest) && 801e7b8: 2b00 cmp r3, #0 801e7ba: d041 beq.n 801e840 if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) { 801e7bc: 6a3b ldr r3, [r7, #32] 801e7be: 7c1b ldrb r3, [r3, #16] 801e7c0: f003 0304 and.w r3, r3, #4 801e7c4: 2b00 cmp r3, #0 801e7c6: d11d bne.n 801e804 if (uncon_pcb == NULL) { 801e7c8: 69bb ldr r3, [r7, #24] 801e7ca: 2b00 cmp r3, #0 801e7cc: d102 bne.n 801e7d4 /* the first unconnected matching PCB */ uncon_pcb = pcb; 801e7ce: 6a3b ldr r3, [r7, #32] 801e7d0: 61bb str r3, [r7, #24] 801e7d2: e017 b.n 801e804 #if LWIP_IPV4 } else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) { 801e7d4: 7cfb ldrb r3, [r7, #19] 801e7d6: 2b00 cmp r3, #0 801e7d8: d014 beq.n 801e804 801e7da: 4b53 ldr r3, [pc, #332] ; (801e928 ) 801e7dc: 695b ldr r3, [r3, #20] 801e7de: f1b3 3fff cmp.w r3, #4294967295 801e7e2: d10f bne.n 801e804 /* global broadcast address (only valid for IPv4; match was checked before) */ if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) { 801e7e4: 69bb ldr r3, [r7, #24] 801e7e6: 681a ldr r2, [r3, #0] 801e7e8: 683b ldr r3, [r7, #0] 801e7ea: 3304 adds r3, #4 801e7ec: 681b ldr r3, [r3, #0] 801e7ee: 429a cmp r2, r3 801e7f0: d008 beq.n 801e804 /* uncon_pcb does not match the input netif, check this pcb */ if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) { 801e7f2: 6a3b ldr r3, [r7, #32] 801e7f4: 681a ldr r2, [r3, #0] 801e7f6: 683b ldr r3, [r7, #0] 801e7f8: 3304 adds r3, #4 801e7fa: 681b ldr r3, [r3, #0] 801e7fc: 429a cmp r2, r3 801e7fe: d101 bne.n 801e804 /* better match */ uncon_pcb = pcb; 801e800: 6a3b ldr r3, [r7, #32] 801e802: 61bb str r3, [r7, #24] } #endif /* SO_REUSE */ } /* compare PCB remote addr+port to UDP source addr+port */ if ((pcb->remote_port == src) && 801e804: 6a3b ldr r3, [r7, #32] 801e806: 8a9b ldrh r3, [r3, #20] 801e808: 8a3a ldrh r2, [r7, #16] 801e80a: 429a cmp r2, r3 801e80c: d118 bne.n 801e840 (ip_addr_isany_val(pcb->remote_ip) || 801e80e: 6a3b ldr r3, [r7, #32] 801e810: 685b ldr r3, [r3, #4] if ((pcb->remote_port == src) && 801e812: 2b00 cmp r3, #0 801e814: d005 beq.n 801e822 ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) { 801e816: 6a3b ldr r3, [r7, #32] 801e818: 685a ldr r2, [r3, #4] 801e81a: 4b43 ldr r3, [pc, #268] ; (801e928 ) 801e81c: 691b ldr r3, [r3, #16] (ip_addr_isany_val(pcb->remote_ip) || 801e81e: 429a cmp r2, r3 801e820: d10e bne.n 801e840 /* the first fully matching PCB */ if (prev != NULL) { 801e822: 6a7b ldr r3, [r7, #36] ; 0x24 801e824: 2b00 cmp r3, #0 801e826: d014 beq.n 801e852 /* move the pcb to the front of udp_pcbs so that is found faster next time */ prev->next = pcb->next; 801e828: 6a3b ldr r3, [r7, #32] 801e82a: 68da ldr r2, [r3, #12] 801e82c: 6a7b ldr r3, [r7, #36] ; 0x24 801e82e: 60da str r2, [r3, #12] pcb->next = udp_pcbs; 801e830: 4b3e ldr r3, [pc, #248] ; (801e92c ) 801e832: 681a ldr r2, [r3, #0] 801e834: 6a3b ldr r3, [r7, #32] 801e836: 60da str r2, [r3, #12] udp_pcbs = pcb; 801e838: 4a3c ldr r2, [pc, #240] ; (801e92c ) 801e83a: 6a3b ldr r3, [r7, #32] 801e83c: 6013 str r3, [r2, #0] } else { UDP_STATS_INC(udp.cachehit); } break; 801e83e: e008 b.n 801e852 } } prev = pcb; 801e840: 6a3b ldr r3, [r7, #32] 801e842: 627b str r3, [r7, #36] ; 0x24 for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { 801e844: 6a3b ldr r3, [r7, #32] 801e846: 68db ldr r3, [r3, #12] 801e848: 623b str r3, [r7, #32] 801e84a: 6a3b ldr r3, [r7, #32] 801e84c: 2b00 cmp r3, #0 801e84e: d1a7 bne.n 801e7a0 801e850: e000 b.n 801e854 break; 801e852: bf00 nop } /* no fully matching pcb found? then look for an unconnected pcb */ if (pcb == NULL) { 801e854: 6a3b ldr r3, [r7, #32] 801e856: 2b00 cmp r3, #0 801e858: d101 bne.n 801e85e pcb = uncon_pcb; 801e85a: 69bb ldr r3, [r7, #24] 801e85c: 623b str r3, [r7, #32] } /* Check checksum if this is a match or if it was directed at us. */ if (pcb != NULL) { 801e85e: 6a3b ldr r3, [r7, #32] 801e860: 2b00 cmp r3, #0 801e862: d002 beq.n 801e86a for_us = 1; 801e864: 2301 movs r3, #1 801e866: 77fb strb r3, [r7, #31] 801e868: e00a b.n 801e880 for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0; } #endif /* LWIP_IPV6 */ #if LWIP_IPV4 if (!ip_current_is_v6()) { for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr()); 801e86a: 683b ldr r3, [r7, #0] 801e86c: 3304 adds r3, #4 801e86e: 681a ldr r2, [r3, #0] 801e870: 4b2d ldr r3, [pc, #180] ; (801e928 ) 801e872: 695b ldr r3, [r3, #20] 801e874: 429a cmp r2, r3 801e876: bf0c ite eq 801e878: 2301 moveq r3, #1 801e87a: 2300 movne r3, #0 801e87c: b2db uxtb r3, r3 801e87e: 77fb strb r3, [r7, #31] } #endif /* LWIP_IPV4 */ } if (for_us) { 801e880: 7ffb ldrb r3, [r7, #31] 801e882: 2b00 cmp r3, #0 801e884: d041 beq.n 801e90a } } } } #endif /* CHECKSUM_CHECK_UDP */ if (pbuf_remove_header(p, UDP_HLEN)) { 801e886: 2108 movs r1, #8 801e888: 6878 ldr r0, [r7, #4] 801e88a: f7f9 f8af bl 80179ec 801e88e: 4603 mov r3, r0 801e890: 2b00 cmp r3, #0 801e892: d00a beq.n 801e8aa /* Can we cope with this failing? Just assert for now */ LWIP_ASSERT("pbuf_remove_header failed\n", 0); 801e894: 4b20 ldr r3, [pc, #128] ; (801e918 ) 801e896: f44f 72b8 mov.w r2, #368 ; 0x170 801e89a: 4925 ldr r1, [pc, #148] ; (801e930 ) 801e89c: 4820 ldr r0, [pc, #128] ; (801e920 ) 801e89e: f003 f873 bl 8021988 UDP_STATS_INC(udp.drop); MIB2_STATS_INC(mib2.udpinerrors); pbuf_free(p); 801e8a2: 6878 ldr r0, [r7, #4] 801e8a4: f7f9 f928 bl 8017af8 goto end; 801e8a8: e032 b.n 801e910 } if (pcb != NULL) { 801e8aa: 6a3b ldr r3, [r7, #32] 801e8ac: 2b00 cmp r3, #0 801e8ae: d012 beq.n 801e8d6 } } } #endif /* SO_REUSE && SO_REUSE_RXTOALL */ /* callback */ if (pcb->recv != NULL) { 801e8b0: 6a3b ldr r3, [r7, #32] 801e8b2: 699b ldr r3, [r3, #24] 801e8b4: 2b00 cmp r3, #0 801e8b6: d00a beq.n 801e8ce /* now the recv function is responsible for freeing p */ pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src); 801e8b8: 6a3b ldr r3, [r7, #32] 801e8ba: 699c ldr r4, [r3, #24] 801e8bc: 6a3b ldr r3, [r7, #32] 801e8be: 69d8 ldr r0, [r3, #28] 801e8c0: 8a3b ldrh r3, [r7, #16] 801e8c2: 9300 str r3, [sp, #0] 801e8c4: 4b1b ldr r3, [pc, #108] ; (801e934 ) 801e8c6: 687a ldr r2, [r7, #4] 801e8c8: 6a39 ldr r1, [r7, #32] 801e8ca: 47a0 blx r4 } else { pbuf_free(p); } end: PERF_STOP("udp_input"); return; 801e8cc: e021 b.n 801e912 pbuf_free(p); 801e8ce: 6878 ldr r0, [r7, #4] 801e8d0: f7f9 f912 bl 8017af8 goto end; 801e8d4: e01c b.n 801e910 if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) { 801e8d6: 7cfb ldrb r3, [r7, #19] 801e8d8: 2b00 cmp r3, #0 801e8da: d112 bne.n 801e902 801e8dc: 4b12 ldr r3, [pc, #72] ; (801e928 ) 801e8de: 695b ldr r3, [r3, #20] 801e8e0: f003 03f0 and.w r3, r3, #240 ; 0xf0 801e8e4: 2be0 cmp r3, #224 ; 0xe0 801e8e6: d00c beq.n 801e902 pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN)); 801e8e8: 4b0f ldr r3, [pc, #60] ; (801e928 ) 801e8ea: 899b ldrh r3, [r3, #12] 801e8ec: 3308 adds r3, #8 801e8ee: b29b uxth r3, r3 801e8f0: b21b sxth r3, r3 801e8f2: 4619 mov r1, r3 801e8f4: 6878 ldr r0, [r7, #4] 801e8f6: f7f9 f8ec bl 8017ad2 icmp_port_unreach(ip_current_is_v6(), p); 801e8fa: 2103 movs r1, #3 801e8fc: 6878 ldr r0, [r7, #4] 801e8fe: f001 fa65 bl 801fdcc pbuf_free(p); 801e902: 6878 ldr r0, [r7, #4] 801e904: f7f9 f8f8 bl 8017af8 return; 801e908: e003 b.n 801e912 pbuf_free(p); 801e90a: 6878 ldr r0, [r7, #4] 801e90c: f7f9 f8f4 bl 8017af8 return; 801e910: bf00 nop UDP_STATS_INC(udp.drop); MIB2_STATS_INC(mib2.udpinerrors); pbuf_free(p); PERF_STOP("udp_input"); #endif /* CHECKSUM_CHECK_UDP */ } 801e912: 372c adds r7, #44 ; 0x2c 801e914: 46bd mov sp, r7 801e916: bd90 pop {r4, r7, pc} 801e918: 08026118 .word 0x08026118 801e91c: 080261bc .word 0x080261bc 801e920: 0802616c .word 0x0802616c 801e924: 080261d4 .word 0x080261d4 801e928: 24013980 .word 0x24013980 801e92c: 2401a4e0 .word 0x2401a4e0 801e930: 080261f0 .word 0x080261f0 801e934: 24013990 .word 0x24013990 0801e938 : * * @see udp_disconnect() */ err_t udp_bind(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) { 801e938: b580 push {r7, lr} 801e93a: b086 sub sp, #24 801e93c: af00 add r7, sp, #0 801e93e: 60f8 str r0, [r7, #12] 801e940: 60b9 str r1, [r7, #8] 801e942: 4613 mov r3, r2 801e944: 80fb strh r3, [r7, #6] LWIP_ASSERT_CORE_LOCKED(); #if LWIP_IPV4 /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ if (ipaddr == NULL) { 801e946: 68bb ldr r3, [r7, #8] 801e948: 2b00 cmp r3, #0 801e94a: d101 bne.n 801e950 ipaddr = IP4_ADDR_ANY; 801e94c: 4b39 ldr r3, [pc, #228] ; (801ea34 ) 801e94e: 60bb str r3, [r7, #8] } #else /* LWIP_IPV4 */ LWIP_ERROR("udp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG); #endif /* LWIP_IPV4 */ LWIP_ERROR("udp_bind: invalid pcb", pcb != NULL, return ERR_ARG); 801e950: 68fb ldr r3, [r7, #12] 801e952: 2b00 cmp r3, #0 801e954: d109 bne.n 801e96a 801e956: 4b38 ldr r3, [pc, #224] ; (801ea38 ) 801e958: f240 32b7 movw r2, #951 ; 0x3b7 801e95c: 4937 ldr r1, [pc, #220] ; (801ea3c ) 801e95e: 4838 ldr r0, [pc, #224] ; (801ea40 ) 801e960: f003 f812 bl 8021988 801e964: f06f 030f mvn.w r3, #15 801e968: e060 b.n 801ea2c LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = ")); ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE, ipaddr); LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port)); rebind = 0; 801e96a: 2300 movs r3, #0 801e96c: 74fb strb r3, [r7, #19] /* Check for double bind and rebind of the same pcb */ for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { 801e96e: 4b35 ldr r3, [pc, #212] ; (801ea44 ) 801e970: 681b ldr r3, [r3, #0] 801e972: 617b str r3, [r7, #20] 801e974: e009 b.n 801e98a /* is this UDP PCB already on active list? */ if (pcb == ipcb) { 801e976: 68fa ldr r2, [r7, #12] 801e978: 697b ldr r3, [r7, #20] 801e97a: 429a cmp r2, r3 801e97c: d102 bne.n 801e984 rebind = 1; 801e97e: 2301 movs r3, #1 801e980: 74fb strb r3, [r7, #19] break; 801e982: e005 b.n 801e990 for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { 801e984: 697b ldr r3, [r7, #20] 801e986: 68db ldr r3, [r3, #12] 801e988: 617b str r3, [r7, #20] 801e98a: 697b ldr r3, [r7, #20] 801e98c: 2b00 cmp r3, #0 801e98e: d1f2 bne.n 801e976 ipaddr = &zoned_ipaddr; } #endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ /* no port specified? */ if (port == 0) { 801e990: 88fb ldrh r3, [r7, #6] 801e992: 2b00 cmp r3, #0 801e994: d109 bne.n 801e9aa port = udp_new_port(); 801e996: f7ff fe1f bl 801e5d8 801e99a: 4603 mov r3, r0 801e99c: 80fb strh r3, [r7, #6] if (port == 0) { 801e99e: 88fb ldrh r3, [r7, #6] 801e9a0: 2b00 cmp r3, #0 801e9a2: d12c bne.n 801e9fe /* no more ports available in local range */ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); return ERR_USE; 801e9a4: f06f 0307 mvn.w r3, #7 801e9a8: e040 b.n 801ea2c } } else { for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { 801e9aa: 4b26 ldr r3, [pc, #152] ; (801ea44 ) 801e9ac: 681b ldr r3, [r3, #0] 801e9ae: 617b str r3, [r7, #20] 801e9b0: e022 b.n 801e9f8 if (pcb != ipcb) { 801e9b2: 68fa ldr r2, [r7, #12] 801e9b4: 697b ldr r3, [r7, #20] 801e9b6: 429a cmp r2, r3 801e9b8: d01b beq.n 801e9f2 if (!ip_get_option(pcb, SOF_REUSEADDR) || !ip_get_option(ipcb, SOF_REUSEADDR)) #endif /* SO_REUSE */ { /* port matches that of PCB in list and REUSEADDR not set -> reject */ if ((ipcb->local_port == port) && 801e9ba: 697b ldr r3, [r7, #20] 801e9bc: 8a5b ldrh r3, [r3, #18] 801e9be: 88fa ldrh r2, [r7, #6] 801e9c0: 429a cmp r2, r3 801e9c2: d116 bne.n 801e9f2 /* IP address matches or any IP used? */ (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) || 801e9c4: 697b ldr r3, [r7, #20] 801e9c6: 681a ldr r2, [r3, #0] 801e9c8: 68bb ldr r3, [r7, #8] 801e9ca: 681b ldr r3, [r3, #0] if ((ipcb->local_port == port) && 801e9cc: 429a cmp r2, r3 801e9ce: d00d beq.n 801e9ec (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) || 801e9d0: 68bb ldr r3, [r7, #8] 801e9d2: 2b00 cmp r3, #0 801e9d4: d00a beq.n 801e9ec 801e9d6: 68bb ldr r3, [r7, #8] 801e9d8: 681b ldr r3, [r3, #0] 801e9da: 2b00 cmp r3, #0 801e9dc: d006 beq.n 801e9ec ip_addr_isany(&ipcb->local_ip))) { 801e9de: 697b ldr r3, [r7, #20] (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) || 801e9e0: 2b00 cmp r3, #0 801e9e2: d003 beq.n 801e9ec ip_addr_isany(&ipcb->local_ip))) { 801e9e4: 697b ldr r3, [r7, #20] 801e9e6: 681b ldr r3, [r3, #0] 801e9e8: 2b00 cmp r3, #0 801e9ea: d102 bne.n 801e9f2 /* other PCB already binds to this local IP and port */ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); return ERR_USE; 801e9ec: f06f 0307 mvn.w r3, #7 801e9f0: e01c b.n 801ea2c for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { 801e9f2: 697b ldr r3, [r7, #20] 801e9f4: 68db ldr r3, [r3, #12] 801e9f6: 617b str r3, [r7, #20] 801e9f8: 697b ldr r3, [r7, #20] 801e9fa: 2b00 cmp r3, #0 801e9fc: d1d9 bne.n 801e9b2 } } } } ip_addr_set_ipaddr(&pcb->local_ip, ipaddr); 801e9fe: 68bb ldr r3, [r7, #8] 801ea00: 2b00 cmp r3, #0 801ea02: d002 beq.n 801ea0a 801ea04: 68bb ldr r3, [r7, #8] 801ea06: 681b ldr r3, [r3, #0] 801ea08: e000 b.n 801ea0c 801ea0a: 2300 movs r3, #0 801ea0c: 68fa ldr r2, [r7, #12] 801ea0e: 6013 str r3, [r2, #0] pcb->local_port = port; 801ea10: 68fb ldr r3, [r7, #12] 801ea12: 88fa ldrh r2, [r7, #6] 801ea14: 825a strh r2, [r3, #18] mib2_udp_bind(pcb); /* pcb not active yet? */ if (rebind == 0) { 801ea16: 7cfb ldrb r3, [r7, #19] 801ea18: 2b00 cmp r3, #0 801ea1a: d106 bne.n 801ea2a /* place the PCB on the active list if not already there */ pcb->next = udp_pcbs; 801ea1c: 4b09 ldr r3, [pc, #36] ; (801ea44 ) 801ea1e: 681a ldr r2, [r3, #0] 801ea20: 68fb ldr r3, [r7, #12] 801ea22: 60da str r2, [r3, #12] udp_pcbs = pcb; 801ea24: 4a07 ldr r2, [pc, #28] ; (801ea44 ) 801ea26: 68fb ldr r3, [r7, #12] 801ea28: 6013 str r3, [r2, #0] } LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_bind: bound to ")); ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, pcb->local_ip); LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->local_port)); return ERR_OK; 801ea2a: 2300 movs r3, #0 } 801ea2c: 4618 mov r0, r3 801ea2e: 3718 adds r7, #24 801ea30: 46bd mov sp, r7 801ea32: bd80 pop {r7, pc} 801ea34: 08026cec .word 0x08026cec 801ea38: 08026118 .word 0x08026118 801ea3c: 080263e0 .word 0x080263e0 801ea40: 0802616c .word 0x0802616c 801ea44: 2401a4e0 .word 0x2401a4e0 0801ea48 : * * @see udp_disconnect() */ err_t udp_connect(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) { 801ea48: b580 push {r7, lr} 801ea4a: b086 sub sp, #24 801ea4c: af00 add r7, sp, #0 801ea4e: 60f8 str r0, [r7, #12] 801ea50: 60b9 str r1, [r7, #8] 801ea52: 4613 mov r3, r2 801ea54: 80fb strh r3, [r7, #6] struct udp_pcb *ipcb; LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("udp_connect: invalid pcb", pcb != NULL, return ERR_ARG); 801ea56: 68fb ldr r3, [r7, #12] 801ea58: 2b00 cmp r3, #0 801ea5a: d109 bne.n 801ea70 801ea5c: 4b2c ldr r3, [pc, #176] ; (801eb10 ) 801ea5e: f240 4235 movw r2, #1077 ; 0x435 801ea62: 492c ldr r1, [pc, #176] ; (801eb14 ) 801ea64: 482c ldr r0, [pc, #176] ; (801eb18 ) 801ea66: f002 ff8f bl 8021988 801ea6a: f06f 030f mvn.w r3, #15 801ea6e: e04b b.n 801eb08 LWIP_ERROR("udp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG); 801ea70: 68bb ldr r3, [r7, #8] 801ea72: 2b00 cmp r3, #0 801ea74: d109 bne.n 801ea8a 801ea76: 4b26 ldr r3, [pc, #152] ; (801eb10 ) 801ea78: f240 4236 movw r2, #1078 ; 0x436 801ea7c: 4927 ldr r1, [pc, #156] ; (801eb1c ) 801ea7e: 4826 ldr r0, [pc, #152] ; (801eb18 ) 801ea80: f002 ff82 bl 8021988 801ea84: f06f 030f mvn.w r3, #15 801ea88: e03e b.n 801eb08 if (pcb->local_port == 0) { 801ea8a: 68fb ldr r3, [r7, #12] 801ea8c: 8a5b ldrh r3, [r3, #18] 801ea8e: 2b00 cmp r3, #0 801ea90: d10f bne.n 801eab2 err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); 801ea92: 68f9 ldr r1, [r7, #12] 801ea94: 68fb ldr r3, [r7, #12] 801ea96: 8a5b ldrh r3, [r3, #18] 801ea98: 461a mov r2, r3 801ea9a: 68f8 ldr r0, [r7, #12] 801ea9c: f7ff ff4c bl 801e938 801eaa0: 4603 mov r3, r0 801eaa2: 75fb strb r3, [r7, #23] if (err != ERR_OK) { 801eaa4: f997 3017 ldrsb.w r3, [r7, #23] 801eaa8: 2b00 cmp r3, #0 801eaaa: d002 beq.n 801eab2 return err; 801eaac: f997 3017 ldrsb.w r3, [r7, #23] 801eab0: e02a b.n 801eb08 } } ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr); 801eab2: 68bb ldr r3, [r7, #8] 801eab4: 2b00 cmp r3, #0 801eab6: d002 beq.n 801eabe 801eab8: 68bb ldr r3, [r7, #8] 801eaba: 681b ldr r3, [r3, #0] 801eabc: e000 b.n 801eac0 801eabe: 2300 movs r3, #0 801eac0: 68fa ldr r2, [r7, #12] 801eac2: 6053 str r3, [r2, #4] ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) { ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip)); } #endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ pcb->remote_port = port; 801eac4: 68fb ldr r3, [r7, #12] 801eac6: 88fa ldrh r2, [r7, #6] 801eac8: 829a strh r2, [r3, #20] pcb->flags |= UDP_FLAGS_CONNECTED; 801eaca: 68fb ldr r3, [r7, #12] 801eacc: 7c1b ldrb r3, [r3, #16] 801eace: f043 0304 orr.w r3, r3, #4 801ead2: b2da uxtb r2, r3 801ead4: 68fb ldr r3, [r7, #12] 801ead6: 741a strb r2, [r3, #16] ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, pcb->remote_ip); LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->remote_port)); /* Insert UDP PCB into the list of active UDP PCBs. */ for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { 801ead8: 4b11 ldr r3, [pc, #68] ; (801eb20 ) 801eada: 681b ldr r3, [r3, #0] 801eadc: 613b str r3, [r7, #16] 801eade: e008 b.n 801eaf2 if (pcb == ipcb) { 801eae0: 68fa ldr r2, [r7, #12] 801eae2: 693b ldr r3, [r7, #16] 801eae4: 429a cmp r2, r3 801eae6: d101 bne.n 801eaec /* already on the list, just return */ return ERR_OK; 801eae8: 2300 movs r3, #0 801eaea: e00d b.n 801eb08 for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { 801eaec: 693b ldr r3, [r7, #16] 801eaee: 68db ldr r3, [r3, #12] 801eaf0: 613b str r3, [r7, #16] 801eaf2: 693b ldr r3, [r7, #16] 801eaf4: 2b00 cmp r3, #0 801eaf6: d1f3 bne.n 801eae0 } } /* PCB not yet on the list, add PCB now */ pcb->next = udp_pcbs; 801eaf8: 4b09 ldr r3, [pc, #36] ; (801eb20 ) 801eafa: 681a ldr r2, [r3, #0] 801eafc: 68fb ldr r3, [r7, #12] 801eafe: 60da str r2, [r3, #12] udp_pcbs = pcb; 801eb00: 4a07 ldr r2, [pc, #28] ; (801eb20 ) 801eb02: 68fb ldr r3, [r7, #12] 801eb04: 6013 str r3, [r2, #0] return ERR_OK; 801eb06: 2300 movs r3, #0 } 801eb08: 4618 mov r0, r3 801eb0a: 3718 adds r7, #24 801eb0c: 46bd mov sp, r7 801eb0e: bd80 pop {r7, pc} 801eb10: 08026118 .word 0x08026118 801eb14: 080263f8 .word 0x080263f8 801eb18: 0802616c .word 0x0802616c 801eb1c: 08026414 .word 0x08026414 801eb20: 2401a4e0 .word 0x2401a4e0 0801eb24 : * @param recv function pointer of the callback function * @param recv_arg additional argument to pass to the callback function */ void udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg) { 801eb24: b580 push {r7, lr} 801eb26: b084 sub sp, #16 801eb28: af00 add r7, sp, #0 801eb2a: 60f8 str r0, [r7, #12] 801eb2c: 60b9 str r1, [r7, #8] 801eb2e: 607a str r2, [r7, #4] LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("udp_recv: invalid pcb", pcb != NULL, return); 801eb30: 68fb ldr r3, [r7, #12] 801eb32: 2b00 cmp r3, #0 801eb34: d107 bne.n 801eb46 801eb36: 4b08 ldr r3, [pc, #32] ; (801eb58 ) 801eb38: f240 428a movw r2, #1162 ; 0x48a 801eb3c: 4907 ldr r1, [pc, #28] ; (801eb5c ) 801eb3e: 4808 ldr r0, [pc, #32] ; (801eb60 ) 801eb40: f002 ff22 bl 8021988 801eb44: e005 b.n 801eb52 /* remember recv() callback and user data */ pcb->recv = recv; 801eb46: 68fb ldr r3, [r7, #12] 801eb48: 68ba ldr r2, [r7, #8] 801eb4a: 619a str r2, [r3, #24] pcb->recv_arg = recv_arg; 801eb4c: 68fb ldr r3, [r7, #12] 801eb4e: 687a ldr r2, [r7, #4] 801eb50: 61da str r2, [r3, #28] } 801eb52: 3710 adds r7, #16 801eb54: 46bd mov sp, r7 801eb56: bd80 pop {r7, pc} 801eb58: 08026118 .word 0x08026118 801eb5c: 0802644c .word 0x0802644c 801eb60: 0802616c .word 0x0802616c 0801eb64 : * * @see udp_new() */ void udp_remove(struct udp_pcb *pcb) { 801eb64: b580 push {r7, lr} 801eb66: b084 sub sp, #16 801eb68: af00 add r7, sp, #0 801eb6a: 6078 str r0, [r7, #4] struct udp_pcb *pcb2; LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("udp_remove: invalid pcb", pcb != NULL, return); 801eb6c: 687b ldr r3, [r7, #4] 801eb6e: 2b00 cmp r3, #0 801eb70: d107 bne.n 801eb82 801eb72: 4b19 ldr r3, [pc, #100] ; (801ebd8 ) 801eb74: f240 42a1 movw r2, #1185 ; 0x4a1 801eb78: 4918 ldr r1, [pc, #96] ; (801ebdc ) 801eb7a: 4819 ldr r0, [pc, #100] ; (801ebe0 ) 801eb7c: f002 ff04 bl 8021988 801eb80: e026 b.n 801ebd0 mib2_udp_unbind(pcb); /* pcb to be removed is first in list? */ if (udp_pcbs == pcb) { 801eb82: 4b18 ldr r3, [pc, #96] ; (801ebe4 ) 801eb84: 681b ldr r3, [r3, #0] 801eb86: 687a ldr r2, [r7, #4] 801eb88: 429a cmp r2, r3 801eb8a: d105 bne.n 801eb98 /* make list start at 2nd pcb */ udp_pcbs = udp_pcbs->next; 801eb8c: 4b15 ldr r3, [pc, #84] ; (801ebe4 ) 801eb8e: 681b ldr r3, [r3, #0] 801eb90: 68db ldr r3, [r3, #12] 801eb92: 4a14 ldr r2, [pc, #80] ; (801ebe4 ) 801eb94: 6013 str r3, [r2, #0] 801eb96: e017 b.n 801ebc8 /* pcb not 1st in list */ } else { for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { 801eb98: 4b12 ldr r3, [pc, #72] ; (801ebe4 ) 801eb9a: 681b ldr r3, [r3, #0] 801eb9c: 60fb str r3, [r7, #12] 801eb9e: e010 b.n 801ebc2 /* find pcb in udp_pcbs list */ if (pcb2->next != NULL && pcb2->next == pcb) { 801eba0: 68fb ldr r3, [r7, #12] 801eba2: 68db ldr r3, [r3, #12] 801eba4: 2b00 cmp r3, #0 801eba6: d009 beq.n 801ebbc 801eba8: 68fb ldr r3, [r7, #12] 801ebaa: 68db ldr r3, [r3, #12] 801ebac: 687a ldr r2, [r7, #4] 801ebae: 429a cmp r2, r3 801ebb0: d104 bne.n 801ebbc /* remove pcb from list */ pcb2->next = pcb->next; 801ebb2: 687b ldr r3, [r7, #4] 801ebb4: 68da ldr r2, [r3, #12] 801ebb6: 68fb ldr r3, [r7, #12] 801ebb8: 60da str r2, [r3, #12] break; 801ebba: e005 b.n 801ebc8 for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { 801ebbc: 68fb ldr r3, [r7, #12] 801ebbe: 68db ldr r3, [r3, #12] 801ebc0: 60fb str r3, [r7, #12] 801ebc2: 68fb ldr r3, [r7, #12] 801ebc4: 2b00 cmp r3, #0 801ebc6: d1eb bne.n 801eba0 } } } memp_free(MEMP_UDP_PCB, pcb); 801ebc8: 6879 ldr r1, [r7, #4] 801ebca: 2000 movs r0, #0 801ebcc: f7f7 fff6 bl 8016bbc } 801ebd0: 3710 adds r7, #16 801ebd2: 46bd mov sp, r7 801ebd4: bd80 pop {r7, pc} 801ebd6: bf00 nop 801ebd8: 08026118 .word 0x08026118 801ebdc: 08026464 .word 0x08026464 801ebe0: 0802616c .word 0x0802616c 801ebe4: 2401a4e0 .word 0x2401a4e0 0801ebe8 : * * @see udp_remove() */ struct udp_pcb * udp_new(void) { 801ebe8: b580 push {r7, lr} 801ebea: b082 sub sp, #8 801ebec: af00 add r7, sp, #0 struct udp_pcb *pcb; LWIP_ASSERT_CORE_LOCKED(); pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB); 801ebee: 2000 movs r0, #0 801ebf0: f7f7 ff6e bl 8016ad0 801ebf4: 6078 str r0, [r7, #4] /* could allocate UDP PCB? */ if (pcb != NULL) { 801ebf6: 687b ldr r3, [r7, #4] 801ebf8: 2b00 cmp r3, #0 801ebfa: d007 beq.n 801ec0c /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0 * which means checksum is generated over the whole datagram per default * (recommended as default by RFC 3828). */ /* initialize PCB to all zeroes */ memset(pcb, 0, sizeof(struct udp_pcb)); 801ebfc: 2220 movs r2, #32 801ebfe: 2100 movs r1, #0 801ec00: 6878 ldr r0, [r7, #4] 801ec02: f003 f86d bl 8021ce0 pcb->ttl = UDP_TTL; 801ec06: 687b ldr r3, [r7, #4] 801ec08: 22ff movs r2, #255 ; 0xff 801ec0a: 72da strb r2, [r3, #11] #if LWIP_MULTICAST_TX_OPTIONS udp_set_multicast_ttl(pcb, UDP_TTL); #endif /* LWIP_MULTICAST_TX_OPTIONS */ } return pcb; 801ec0c: 687b ldr r3, [r7, #4] } 801ec0e: 4618 mov r0, r3 801ec10: 3708 adds r7, #8 801ec12: 46bd mov sp, r7 801ec14: bd80 pop {r7, pc} 0801ec16 : * * @see udp_remove() */ struct udp_pcb * udp_new_ip_type(u8_t type) { 801ec16: b580 push {r7, lr} 801ec18: b084 sub sp, #16 801ec1a: af00 add r7, sp, #0 801ec1c: 4603 mov r3, r0 801ec1e: 71fb strb r3, [r7, #7] struct udp_pcb *pcb; LWIP_ASSERT_CORE_LOCKED(); pcb = udp_new(); 801ec20: f7ff ffe2 bl 801ebe8 801ec24: 60f8 str r0, [r7, #12] IP_SET_TYPE_VAL(pcb->remote_ip, type); } #else LWIP_UNUSED_ARG(type); #endif /* LWIP_IPV4 && LWIP_IPV6 */ return pcb; 801ec26: 68fb ldr r3, [r7, #12] } 801ec28: 4618 mov r0, r3 801ec2a: 3710 adds r7, #16 801ec2c: 46bd mov sp, r7 801ec2e: bd80 pop {r7, pc} 0801ec30 : * * @param old_addr IP address of the netif before change * @param new_addr IP address of the netif after change */ void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) { 801ec30: b480 push {r7} 801ec32: b085 sub sp, #20 801ec34: af00 add r7, sp, #0 801ec36: 6078 str r0, [r7, #4] 801ec38: 6039 str r1, [r7, #0] struct udp_pcb *upcb; if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) { 801ec3a: 687b ldr r3, [r7, #4] 801ec3c: 2b00 cmp r3, #0 801ec3e: d01e beq.n 801ec7e 801ec40: 687b ldr r3, [r7, #4] 801ec42: 681b ldr r3, [r3, #0] 801ec44: 2b00 cmp r3, #0 801ec46: d01a beq.n 801ec7e 801ec48: 683b ldr r3, [r7, #0] 801ec4a: 2b00 cmp r3, #0 801ec4c: d017 beq.n 801ec7e 801ec4e: 683b ldr r3, [r7, #0] 801ec50: 681b ldr r3, [r3, #0] 801ec52: 2b00 cmp r3, #0 801ec54: d013 beq.n 801ec7e for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) { 801ec56: 4b0d ldr r3, [pc, #52] ; (801ec8c ) 801ec58: 681b ldr r3, [r3, #0] 801ec5a: 60fb str r3, [r7, #12] 801ec5c: e00c b.n 801ec78 /* PCB bound to current local interface address? */ if (ip_addr_cmp(&upcb->local_ip, old_addr)) { 801ec5e: 68fb ldr r3, [r7, #12] 801ec60: 681a ldr r2, [r3, #0] 801ec62: 687b ldr r3, [r7, #4] 801ec64: 681b ldr r3, [r3, #0] 801ec66: 429a cmp r2, r3 801ec68: d103 bne.n 801ec72 /* The PCB is bound to the old ipaddr and * is set to bound to the new one instead */ ip_addr_copy(upcb->local_ip, *new_addr); 801ec6a: 683b ldr r3, [r7, #0] 801ec6c: 681a ldr r2, [r3, #0] 801ec6e: 68fb ldr r3, [r7, #12] 801ec70: 601a str r2, [r3, #0] for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) { 801ec72: 68fb ldr r3, [r7, #12] 801ec74: 68db ldr r3, [r3, #12] 801ec76: 60fb str r3, [r7, #12] 801ec78: 68fb ldr r3, [r7, #12] 801ec7a: 2b00 cmp r3, #0 801ec7c: d1ef bne.n 801ec5e } } } } 801ec7e: bf00 nop 801ec80: 3714 adds r7, #20 801ec82: 46bd mov sp, r7 801ec84: f85d 7b04 ldr.w r7, [sp], #4 801ec88: 4770 bx lr 801ec8a: bf00 nop 801ec8c: 2401a4e0 .word 0x2401a4e0 0801ec90 : #endif /* ARP_QUEUEING */ /** Clean up ARP table entries */ static void etharp_free_entry(int i) { 801ec90: b580 push {r7, lr} 801ec92: b082 sub sp, #8 801ec94: af00 add r7, sp, #0 801ec96: 6078 str r0, [r7, #4] /* remove from SNMP ARP index tree */ mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr); /* and empty packet queue */ if (arp_table[i].q != NULL) { 801ec98: 492b ldr r1, [pc, #172] ; (801ed48 ) 801ec9a: 687a ldr r2, [r7, #4] 801ec9c: 4613 mov r3, r2 801ec9e: 005b lsls r3, r3, #1 801eca0: 4413 add r3, r2 801eca2: 00db lsls r3, r3, #3 801eca4: 440b add r3, r1 801eca6: 681b ldr r3, [r3, #0] 801eca8: 2b00 cmp r3, #0 801ecaa: d013 beq.n 801ecd4 /* remove all queued packets */ LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q))); free_etharp_q(arp_table[i].q); 801ecac: 4926 ldr r1, [pc, #152] ; (801ed48 ) 801ecae: 687a ldr r2, [r7, #4] 801ecb0: 4613 mov r3, r2 801ecb2: 005b lsls r3, r3, #1 801ecb4: 4413 add r3, r2 801ecb6: 00db lsls r3, r3, #3 801ecb8: 440b add r3, r1 801ecba: 681b ldr r3, [r3, #0] 801ecbc: 4618 mov r0, r3 801ecbe: f7f8 ff1b bl 8017af8 arp_table[i].q = NULL; 801ecc2: 4921 ldr r1, [pc, #132] ; (801ed48 ) 801ecc4: 687a ldr r2, [r7, #4] 801ecc6: 4613 mov r3, r2 801ecc8: 005b lsls r3, r3, #1 801ecca: 4413 add r3, r2 801eccc: 00db lsls r3, r3, #3 801ecce: 440b add r3, r1 801ecd0: 2200 movs r2, #0 801ecd2: 601a str r2, [r3, #0] } /* recycle entry for re-use */ arp_table[i].state = ETHARP_STATE_EMPTY; 801ecd4: 491c ldr r1, [pc, #112] ; (801ed48 ) 801ecd6: 687a ldr r2, [r7, #4] 801ecd8: 4613 mov r3, r2 801ecda: 005b lsls r3, r3, #1 801ecdc: 4413 add r3, r2 801ecde: 00db lsls r3, r3, #3 801ece0: 440b add r3, r1 801ece2: 3314 adds r3, #20 801ece4: 2200 movs r2, #0 801ece6: 701a strb r2, [r3, #0] #ifdef LWIP_DEBUG /* for debugging, clean out the complete entry */ arp_table[i].ctime = 0; 801ece8: 4917 ldr r1, [pc, #92] ; (801ed48 ) 801ecea: 687a ldr r2, [r7, #4] 801ecec: 4613 mov r3, r2 801ecee: 005b lsls r3, r3, #1 801ecf0: 4413 add r3, r2 801ecf2: 00db lsls r3, r3, #3 801ecf4: 440b add r3, r1 801ecf6: 3312 adds r3, #18 801ecf8: 2200 movs r2, #0 801ecfa: 801a strh r2, [r3, #0] arp_table[i].netif = NULL; 801ecfc: 4912 ldr r1, [pc, #72] ; (801ed48 ) 801ecfe: 687a ldr r2, [r7, #4] 801ed00: 4613 mov r3, r2 801ed02: 005b lsls r3, r3, #1 801ed04: 4413 add r3, r2 801ed06: 00db lsls r3, r3, #3 801ed08: 440b add r3, r1 801ed0a: 3308 adds r3, #8 801ed0c: 2200 movs r2, #0 801ed0e: 601a str r2, [r3, #0] ip4_addr_set_zero(&arp_table[i].ipaddr); 801ed10: 490d ldr r1, [pc, #52] ; (801ed48 ) 801ed12: 687a ldr r2, [r7, #4] 801ed14: 4613 mov r3, r2 801ed16: 005b lsls r3, r3, #1 801ed18: 4413 add r3, r2 801ed1a: 00db lsls r3, r3, #3 801ed1c: 440b add r3, r1 801ed1e: 3304 adds r3, #4 801ed20: 2200 movs r2, #0 801ed22: 601a str r2, [r3, #0] arp_table[i].ethaddr = ethzero; 801ed24: 4908 ldr r1, [pc, #32] ; (801ed48 ) 801ed26: 687a ldr r2, [r7, #4] 801ed28: 4613 mov r3, r2 801ed2a: 005b lsls r3, r3, #1 801ed2c: 4413 add r3, r2 801ed2e: 00db lsls r3, r3, #3 801ed30: 440b add r3, r1 801ed32: 3308 adds r3, #8 801ed34: 4a05 ldr r2, [pc, #20] ; (801ed4c ) 801ed36: 3304 adds r3, #4 801ed38: 6810 ldr r0, [r2, #0] 801ed3a: 6018 str r0, [r3, #0] 801ed3c: 8892 ldrh r2, [r2, #4] 801ed3e: 809a strh r2, [r3, #4] #endif /* LWIP_DEBUG */ } 801ed40: bf00 nop 801ed42: 3708 adds r7, #8 801ed44: 46bd mov sp, r7 801ed46: bd80 pop {r7, pc} 801ed48: 2401a4e4 .word 0x2401a4e4 801ed4c: 08026cf8 .word 0x08026cf8 0801ed50 : * This function should be called every ARP_TMR_INTERVAL milliseconds (1 second), * in order to expire entries in the ARP table. */ void etharp_tmr(void) { 801ed50: b580 push {r7, lr} 801ed52: b082 sub sp, #8 801ed54: af00 add r7, sp, #0 int i; LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); /* remove expired entries from the ARP table */ for (i = 0; i < ARP_TABLE_SIZE; ++i) { 801ed56: 2300 movs r3, #0 801ed58: 607b str r3, [r7, #4] 801ed5a: e096 b.n 801ee8a u8_t state = arp_table[i].state; 801ed5c: 494f ldr r1, [pc, #316] ; (801ee9c ) 801ed5e: 687a ldr r2, [r7, #4] 801ed60: 4613 mov r3, r2 801ed62: 005b lsls r3, r3, #1 801ed64: 4413 add r3, r2 801ed66: 00db lsls r3, r3, #3 801ed68: 440b add r3, r1 801ed6a: 3314 adds r3, #20 801ed6c: 781b ldrb r3, [r3, #0] 801ed6e: 70fb strb r3, [r7, #3] if (state != ETHARP_STATE_EMPTY 801ed70: 78fb ldrb r3, [r7, #3] 801ed72: 2b00 cmp r3, #0 801ed74: f000 8086 beq.w 801ee84 #if ETHARP_SUPPORT_STATIC_ENTRIES && (state != ETHARP_STATE_STATIC) #endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ ) { arp_table[i].ctime++; 801ed78: 4948 ldr r1, [pc, #288] ; (801ee9c ) 801ed7a: 687a ldr r2, [r7, #4] 801ed7c: 4613 mov r3, r2 801ed7e: 005b lsls r3, r3, #1 801ed80: 4413 add r3, r2 801ed82: 00db lsls r3, r3, #3 801ed84: 440b add r3, r1 801ed86: 3312 adds r3, #18 801ed88: 881b ldrh r3, [r3, #0] 801ed8a: 3301 adds r3, #1 801ed8c: b298 uxth r0, r3 801ed8e: 4943 ldr r1, [pc, #268] ; (801ee9c ) 801ed90: 687a ldr r2, [r7, #4] 801ed92: 4613 mov r3, r2 801ed94: 005b lsls r3, r3, #1 801ed96: 4413 add r3, r2 801ed98: 00db lsls r3, r3, #3 801ed9a: 440b add r3, r1 801ed9c: 3312 adds r3, #18 801ed9e: 4602 mov r2, r0 801eda0: 801a strh r2, [r3, #0] if ((arp_table[i].ctime >= ARP_MAXAGE) || 801eda2: 493e ldr r1, [pc, #248] ; (801ee9c ) 801eda4: 687a ldr r2, [r7, #4] 801eda6: 4613 mov r3, r2 801eda8: 005b lsls r3, r3, #1 801edaa: 4413 add r3, r2 801edac: 00db lsls r3, r3, #3 801edae: 440b add r3, r1 801edb0: 3312 adds r3, #18 801edb2: 881b ldrh r3, [r3, #0] 801edb4: f5b3 7f96 cmp.w r3, #300 ; 0x12c 801edb8: d215 bcs.n 801ede6 ((arp_table[i].state == ETHARP_STATE_PENDING) && 801edba: 4938 ldr r1, [pc, #224] ; (801ee9c ) 801edbc: 687a ldr r2, [r7, #4] 801edbe: 4613 mov r3, r2 801edc0: 005b lsls r3, r3, #1 801edc2: 4413 add r3, r2 801edc4: 00db lsls r3, r3, #3 801edc6: 440b add r3, r1 801edc8: 3314 adds r3, #20 801edca: 781b ldrb r3, [r3, #0] if ((arp_table[i].ctime >= ARP_MAXAGE) || 801edcc: 2b01 cmp r3, #1 801edce: d10e bne.n 801edee (arp_table[i].ctime >= ARP_MAXPENDING))) { 801edd0: 4932 ldr r1, [pc, #200] ; (801ee9c ) 801edd2: 687a ldr r2, [r7, #4] 801edd4: 4613 mov r3, r2 801edd6: 005b lsls r3, r3, #1 801edd8: 4413 add r3, r2 801edda: 00db lsls r3, r3, #3 801eddc: 440b add r3, r1 801edde: 3312 adds r3, #18 801ede0: 881b ldrh r3, [r3, #0] ((arp_table[i].state == ETHARP_STATE_PENDING) && 801ede2: 2b04 cmp r3, #4 801ede4: d903 bls.n 801edee /* pending or stable entry has become old! */ LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n", arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i)); /* clean up entries that have just been expired */ etharp_free_entry(i); 801ede6: 6878 ldr r0, [r7, #4] 801ede8: f7ff ff52 bl 801ec90 801edec: e04a b.n 801ee84 } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) { 801edee: 492b ldr r1, [pc, #172] ; (801ee9c ) 801edf0: 687a ldr r2, [r7, #4] 801edf2: 4613 mov r3, r2 801edf4: 005b lsls r3, r3, #1 801edf6: 4413 add r3, r2 801edf8: 00db lsls r3, r3, #3 801edfa: 440b add r3, r1 801edfc: 3314 adds r3, #20 801edfe: 781b ldrb r3, [r3, #0] 801ee00: 2b03 cmp r3, #3 801ee02: d10a bne.n 801ee1a /* Don't send more than one request every 2 seconds. */ arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2; 801ee04: 4925 ldr r1, [pc, #148] ; (801ee9c ) 801ee06: 687a ldr r2, [r7, #4] 801ee08: 4613 mov r3, r2 801ee0a: 005b lsls r3, r3, #1 801ee0c: 4413 add r3, r2 801ee0e: 00db lsls r3, r3, #3 801ee10: 440b add r3, r1 801ee12: 3314 adds r3, #20 801ee14: 2204 movs r2, #4 801ee16: 701a strb r2, [r3, #0] 801ee18: e034 b.n 801ee84 } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) { 801ee1a: 4920 ldr r1, [pc, #128] ; (801ee9c ) 801ee1c: 687a ldr r2, [r7, #4] 801ee1e: 4613 mov r3, r2 801ee20: 005b lsls r3, r3, #1 801ee22: 4413 add r3, r2 801ee24: 00db lsls r3, r3, #3 801ee26: 440b add r3, r1 801ee28: 3314 adds r3, #20 801ee2a: 781b ldrb r3, [r3, #0] 801ee2c: 2b04 cmp r3, #4 801ee2e: d10a bne.n 801ee46 /* Reset state to stable, so that the next transmitted packet will re-send an ARP request. */ arp_table[i].state = ETHARP_STATE_STABLE; 801ee30: 491a ldr r1, [pc, #104] ; (801ee9c ) 801ee32: 687a ldr r2, [r7, #4] 801ee34: 4613 mov r3, r2 801ee36: 005b lsls r3, r3, #1 801ee38: 4413 add r3, r2 801ee3a: 00db lsls r3, r3, #3 801ee3c: 440b add r3, r1 801ee3e: 3314 adds r3, #20 801ee40: 2202 movs r2, #2 801ee42: 701a strb r2, [r3, #0] 801ee44: e01e b.n 801ee84 } else if (arp_table[i].state == ETHARP_STATE_PENDING) { 801ee46: 4915 ldr r1, [pc, #84] ; (801ee9c ) 801ee48: 687a ldr r2, [r7, #4] 801ee4a: 4613 mov r3, r2 801ee4c: 005b lsls r3, r3, #1 801ee4e: 4413 add r3, r2 801ee50: 00db lsls r3, r3, #3 801ee52: 440b add r3, r1 801ee54: 3314 adds r3, #20 801ee56: 781b ldrb r3, [r3, #0] 801ee58: 2b01 cmp r3, #1 801ee5a: d113 bne.n 801ee84 /* still pending, resend an ARP query */ etharp_request(arp_table[i].netif, &arp_table[i].ipaddr); 801ee5c: 490f ldr r1, [pc, #60] ; (801ee9c ) 801ee5e: 687a ldr r2, [r7, #4] 801ee60: 4613 mov r3, r2 801ee62: 005b lsls r3, r3, #1 801ee64: 4413 add r3, r2 801ee66: 00db lsls r3, r3, #3 801ee68: 440b add r3, r1 801ee6a: 3308 adds r3, #8 801ee6c: 6818 ldr r0, [r3, #0] 801ee6e: 687a ldr r2, [r7, #4] 801ee70: 4613 mov r3, r2 801ee72: 005b lsls r3, r3, #1 801ee74: 4413 add r3, r2 801ee76: 00db lsls r3, r3, #3 801ee78: 4a08 ldr r2, [pc, #32] ; (801ee9c ) 801ee7a: 4413 add r3, r2 801ee7c: 3304 adds r3, #4 801ee7e: 4619 mov r1, r3 801ee80: f000 fe6e bl 801fb60 for (i = 0; i < ARP_TABLE_SIZE; ++i) { 801ee84: 687b ldr r3, [r7, #4] 801ee86: 3301 adds r3, #1 801ee88: 607b str r3, [r7, #4] 801ee8a: 687b ldr r3, [r7, #4] 801ee8c: 2b09 cmp r3, #9 801ee8e: f77f af65 ble.w 801ed5c } } } } 801ee92: bf00 nop 801ee94: bf00 nop 801ee96: 3708 adds r7, #8 801ee98: 46bd mov sp, r7 801ee9a: bd80 pop {r7, pc} 801ee9c: 2401a4e4 .word 0x2401a4e4 0801eea0 : * @return The ARP entry index that matched or is created, ERR_MEM if no * entry is found or could be recycled. */ static s16_t etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif) { 801eea0: b580 push {r7, lr} 801eea2: b08a sub sp, #40 ; 0x28 801eea4: af00 add r7, sp, #0 801eea6: 60f8 str r0, [r7, #12] 801eea8: 460b mov r3, r1 801eeaa: 607a str r2, [r7, #4] 801eeac: 72fb strb r3, [r7, #11] s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; 801eeae: 230a movs r3, #10 801eeb0: 843b strh r3, [r7, #32] 801eeb2: 230a movs r3, #10 801eeb4: 847b strh r3, [r7, #34] ; 0x22 s16_t empty = ARP_TABLE_SIZE; 801eeb6: 230a movs r3, #10 801eeb8: 84bb strh r3, [r7, #36] ; 0x24 s16_t i = 0; 801eeba: 2300 movs r3, #0 801eebc: 84fb strh r3, [r7, #38] ; 0x26 /* oldest entry with packets on queue */ s16_t old_queue = ARP_TABLE_SIZE; 801eebe: 230a movs r3, #10 801eec0: 83fb strh r3, [r7, #30] /* its age */ u16_t age_queue = 0, age_pending = 0, age_stable = 0; 801eec2: 2300 movs r3, #0 801eec4: 83bb strh r3, [r7, #28] 801eec6: 2300 movs r3, #0 801eec8: 837b strh r3, [r7, #26] 801eeca: 2300 movs r3, #0 801eecc: 833b strh r3, [r7, #24] * 4) remember the oldest pending entry with queued packets (if any) * 5) search for a matching IP entry, either pending or stable * until 5 matches, or all entries are searched for. */ for (i = 0; i < ARP_TABLE_SIZE; ++i) { 801eece: 2300 movs r3, #0 801eed0: 84fb strh r3, [r7, #38] ; 0x26 801eed2: e0ae b.n 801f032 u8_t state = arp_table[i].state; 801eed4: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801eed8: 49a6 ldr r1, [pc, #664] ; (801f174 ) 801eeda: 4613 mov r3, r2 801eedc: 005b lsls r3, r3, #1 801eede: 4413 add r3, r2 801eee0: 00db lsls r3, r3, #3 801eee2: 440b add r3, r1 801eee4: 3314 adds r3, #20 801eee6: 781b ldrb r3, [r3, #0] 801eee8: 75fb strb r3, [r7, #23] /* no empty entry found yet and now we do find one? */ if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) { 801eeea: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24 801eeee: 2b0a cmp r3, #10 801eef0: d105 bne.n 801eefe 801eef2: 7dfb ldrb r3, [r7, #23] 801eef4: 2b00 cmp r3, #0 801eef6: d102 bne.n 801eefe LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i)); /* remember first empty entry */ empty = i; 801eef8: 8cfb ldrh r3, [r7, #38] ; 0x26 801eefa: 84bb strh r3, [r7, #36] ; 0x24 801eefc: e095 b.n 801f02a } else if (state != ETHARP_STATE_EMPTY) { 801eefe: 7dfb ldrb r3, [r7, #23] 801ef00: 2b00 cmp r3, #0 801ef02: f000 8092 beq.w 801f02a LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE", 801ef06: 7dfb ldrb r3, [r7, #23] 801ef08: 2b01 cmp r3, #1 801ef0a: d009 beq.n 801ef20 801ef0c: 7dfb ldrb r3, [r7, #23] 801ef0e: 2b01 cmp r3, #1 801ef10: d806 bhi.n 801ef20 801ef12: 4b99 ldr r3, [pc, #612] ; (801f178 ) 801ef14: f240 1223 movw r2, #291 ; 0x123 801ef18: 4998 ldr r1, [pc, #608] ; (801f17c ) 801ef1a: 4899 ldr r0, [pc, #612] ; (801f180 ) 801ef1c: f002 fd34 bl 8021988 state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE); /* if given, does IP address match IP address in ARP entry? */ if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr) 801ef20: 68fb ldr r3, [r7, #12] 801ef22: 2b00 cmp r3, #0 801ef24: d020 beq.n 801ef68 801ef26: 68fb ldr r3, [r7, #12] 801ef28: 6819 ldr r1, [r3, #0] 801ef2a: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801ef2e: 4891 ldr r0, [pc, #580] ; (801f174 ) 801ef30: 4613 mov r3, r2 801ef32: 005b lsls r3, r3, #1 801ef34: 4413 add r3, r2 801ef36: 00db lsls r3, r3, #3 801ef38: 4403 add r3, r0 801ef3a: 3304 adds r3, #4 801ef3c: 681b ldr r3, [r3, #0] 801ef3e: 4299 cmp r1, r3 801ef40: d112 bne.n 801ef68 #if ETHARP_TABLE_MATCH_NETIF && ((netif == NULL) || (netif == arp_table[i].netif)) 801ef42: 687b ldr r3, [r7, #4] 801ef44: 2b00 cmp r3, #0 801ef46: d00c beq.n 801ef62 801ef48: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801ef4c: 4989 ldr r1, [pc, #548] ; (801f174 ) 801ef4e: 4613 mov r3, r2 801ef50: 005b lsls r3, r3, #1 801ef52: 4413 add r3, r2 801ef54: 00db lsls r3, r3, #3 801ef56: 440b add r3, r1 801ef58: 3308 adds r3, #8 801ef5a: 681b ldr r3, [r3, #0] 801ef5c: 687a ldr r2, [r7, #4] 801ef5e: 429a cmp r2, r3 801ef60: d102 bne.n 801ef68 #endif /* ETHARP_TABLE_MATCH_NETIF */ ) { LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i)); /* found exact IP address match, simply bail out */ return i; 801ef62: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 801ef66: e100 b.n 801f16a } /* pending entry? */ if (state == ETHARP_STATE_PENDING) { 801ef68: 7dfb ldrb r3, [r7, #23] 801ef6a: 2b01 cmp r3, #1 801ef6c: d140 bne.n 801eff0 /* pending with queued packets? */ if (arp_table[i].q != NULL) { 801ef6e: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801ef72: 4980 ldr r1, [pc, #512] ; (801f174 ) 801ef74: 4613 mov r3, r2 801ef76: 005b lsls r3, r3, #1 801ef78: 4413 add r3, r2 801ef7a: 00db lsls r3, r3, #3 801ef7c: 440b add r3, r1 801ef7e: 681b ldr r3, [r3, #0] 801ef80: 2b00 cmp r3, #0 801ef82: d01a beq.n 801efba if (arp_table[i].ctime >= age_queue) { 801ef84: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801ef88: 497a ldr r1, [pc, #488] ; (801f174 ) 801ef8a: 4613 mov r3, r2 801ef8c: 005b lsls r3, r3, #1 801ef8e: 4413 add r3, r2 801ef90: 00db lsls r3, r3, #3 801ef92: 440b add r3, r1 801ef94: 3312 adds r3, #18 801ef96: 881b ldrh r3, [r3, #0] 801ef98: 8bba ldrh r2, [r7, #28] 801ef9a: 429a cmp r2, r3 801ef9c: d845 bhi.n 801f02a old_queue = i; 801ef9e: 8cfb ldrh r3, [r7, #38] ; 0x26 801efa0: 83fb strh r3, [r7, #30] age_queue = arp_table[i].ctime; 801efa2: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801efa6: 4973 ldr r1, [pc, #460] ; (801f174 ) 801efa8: 4613 mov r3, r2 801efaa: 005b lsls r3, r3, #1 801efac: 4413 add r3, r2 801efae: 00db lsls r3, r3, #3 801efb0: 440b add r3, r1 801efb2: 3312 adds r3, #18 801efb4: 881b ldrh r3, [r3, #0] 801efb6: 83bb strh r3, [r7, #28] 801efb8: e037 b.n 801f02a } } else /* pending without queued packets? */ { if (arp_table[i].ctime >= age_pending) { 801efba: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801efbe: 496d ldr r1, [pc, #436] ; (801f174 ) 801efc0: 4613 mov r3, r2 801efc2: 005b lsls r3, r3, #1 801efc4: 4413 add r3, r2 801efc6: 00db lsls r3, r3, #3 801efc8: 440b add r3, r1 801efca: 3312 adds r3, #18 801efcc: 881b ldrh r3, [r3, #0] 801efce: 8b7a ldrh r2, [r7, #26] 801efd0: 429a cmp r2, r3 801efd2: d82a bhi.n 801f02a old_pending = i; 801efd4: 8cfb ldrh r3, [r7, #38] ; 0x26 801efd6: 843b strh r3, [r7, #32] age_pending = arp_table[i].ctime; 801efd8: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801efdc: 4965 ldr r1, [pc, #404] ; (801f174 ) 801efde: 4613 mov r3, r2 801efe0: 005b lsls r3, r3, #1 801efe2: 4413 add r3, r2 801efe4: 00db lsls r3, r3, #3 801efe6: 440b add r3, r1 801efe8: 3312 adds r3, #18 801efea: 881b ldrh r3, [r3, #0] 801efec: 837b strh r3, [r7, #26] 801efee: e01c b.n 801f02a } } /* stable entry? */ } else if (state >= ETHARP_STATE_STABLE) { 801eff0: 7dfb ldrb r3, [r7, #23] 801eff2: 2b01 cmp r3, #1 801eff4: d919 bls.n 801f02a /* don't record old_stable for static entries since they never expire */ if (state < ETHARP_STATE_STATIC) #endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ { /* remember entry with oldest stable entry in oldest, its age in maxtime */ if (arp_table[i].ctime >= age_stable) { 801eff6: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801effa: 495e ldr r1, [pc, #376] ; (801f174 ) 801effc: 4613 mov r3, r2 801effe: 005b lsls r3, r3, #1 801f000: 4413 add r3, r2 801f002: 00db lsls r3, r3, #3 801f004: 440b add r3, r1 801f006: 3312 adds r3, #18 801f008: 881b ldrh r3, [r3, #0] 801f00a: 8b3a ldrh r2, [r7, #24] 801f00c: 429a cmp r2, r3 801f00e: d80c bhi.n 801f02a old_stable = i; 801f010: 8cfb ldrh r3, [r7, #38] ; 0x26 801f012: 847b strh r3, [r7, #34] ; 0x22 age_stable = arp_table[i].ctime; 801f014: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801f018: 4956 ldr r1, [pc, #344] ; (801f174 ) 801f01a: 4613 mov r3, r2 801f01c: 005b lsls r3, r3, #1 801f01e: 4413 add r3, r2 801f020: 00db lsls r3, r3, #3 801f022: 440b add r3, r1 801f024: 3312 adds r3, #18 801f026: 881b ldrh r3, [r3, #0] 801f028: 833b strh r3, [r7, #24] for (i = 0; i < ARP_TABLE_SIZE; ++i) { 801f02a: 8cfb ldrh r3, [r7, #38] ; 0x26 801f02c: 3301 adds r3, #1 801f02e: b29b uxth r3, r3 801f030: 84fb strh r3, [r7, #38] ; 0x26 801f032: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 801f036: 2b09 cmp r3, #9 801f038: f77f af4c ble.w 801eed4 } } /* { we have no match } => try to create a new entry */ /* don't create new entry, only search? */ if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) || 801f03c: 7afb ldrb r3, [r7, #11] 801f03e: f003 0302 and.w r3, r3, #2 801f042: 2b00 cmp r3, #0 801f044: d108 bne.n 801f058 801f046: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24 801f04a: 2b0a cmp r3, #10 801f04c: d107 bne.n 801f05e /* or no empty entry found and not allowed to recycle? */ ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) { 801f04e: 7afb ldrb r3, [r7, #11] 801f050: f003 0301 and.w r3, r3, #1 801f054: 2b00 cmp r3, #0 801f056: d102 bne.n 801f05e LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n")); return (s16_t)ERR_MEM; 801f058: f04f 33ff mov.w r3, #4294967295 801f05c: e085 b.n 801f16a * * { ETHARP_FLAG_TRY_HARD is set at this point } */ /* 1) empty entry available? */ if (empty < ARP_TABLE_SIZE) { 801f05e: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24 801f062: 2b09 cmp r3, #9 801f064: dc02 bgt.n 801f06c i = empty; 801f066: 8cbb ldrh r3, [r7, #36] ; 0x24 801f068: 84fb strh r3, [r7, #38] ; 0x26 801f06a: e039 b.n 801f0e0 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i)); } else { /* 2) found recyclable stable entry? */ if (old_stable < ARP_TABLE_SIZE) { 801f06c: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22 801f070: 2b09 cmp r3, #9 801f072: dc14 bgt.n 801f09e /* recycle oldest stable*/ i = old_stable; 801f074: 8c7b ldrh r3, [r7, #34] ; 0x22 801f076: 84fb strh r3, [r7, #38] ; 0x26 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i)); /* no queued packets should exist on stable entries */ LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL); 801f078: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801f07c: 493d ldr r1, [pc, #244] ; (801f174 ) 801f07e: 4613 mov r3, r2 801f080: 005b lsls r3, r3, #1 801f082: 4413 add r3, r2 801f084: 00db lsls r3, r3, #3 801f086: 440b add r3, r1 801f088: 681b ldr r3, [r3, #0] 801f08a: 2b00 cmp r3, #0 801f08c: d018 beq.n 801f0c0 801f08e: 4b3a ldr r3, [pc, #232] ; (801f178 ) 801f090: f240 126d movw r2, #365 ; 0x16d 801f094: 493b ldr r1, [pc, #236] ; (801f184 ) 801f096: 483a ldr r0, [pc, #232] ; (801f180 ) 801f098: f002 fc76 bl 8021988 801f09c: e010 b.n 801f0c0 /* 3) found recyclable pending entry without queued packets? */ } else if (old_pending < ARP_TABLE_SIZE) { 801f09e: f9b7 3020 ldrsh.w r3, [r7, #32] 801f0a2: 2b09 cmp r3, #9 801f0a4: dc02 bgt.n 801f0ac /* recycle oldest pending */ i = old_pending; 801f0a6: 8c3b ldrh r3, [r7, #32] 801f0a8: 84fb strh r3, [r7, #38] ; 0x26 801f0aa: e009 b.n 801f0c0 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i)); /* 4) found recyclable pending entry with queued packets? */ } else if (old_queue < ARP_TABLE_SIZE) { 801f0ac: f9b7 301e ldrsh.w r3, [r7, #30] 801f0b0: 2b09 cmp r3, #9 801f0b2: dc02 bgt.n 801f0ba /* recycle oldest pending (queued packets are free in etharp_free_entry) */ i = old_queue; 801f0b4: 8bfb ldrh r3, [r7, #30] 801f0b6: 84fb strh r3, [r7, #38] ; 0x26 801f0b8: e002 b.n 801f0c0 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q))); /* no empty or recyclable entries found */ } else { LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n")); return (s16_t)ERR_MEM; 801f0ba: f04f 33ff mov.w r3, #4294967295 801f0be: e054 b.n 801f16a } /* { empty or recyclable entry found } */ LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); 801f0c0: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 801f0c4: 2b09 cmp r3, #9 801f0c6: dd06 ble.n 801f0d6 801f0c8: 4b2b ldr r3, [pc, #172] ; (801f178 ) 801f0ca: f240 127f movw r2, #383 ; 0x17f 801f0ce: 492e ldr r1, [pc, #184] ; (801f188 ) 801f0d0: 482b ldr r0, [pc, #172] ; (801f180 ) 801f0d2: f002 fc59 bl 8021988 etharp_free_entry(i); 801f0d6: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 801f0da: 4618 mov r0, r3 801f0dc: f7ff fdd8 bl 801ec90 } LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); 801f0e0: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 801f0e4: 2b09 cmp r3, #9 801f0e6: dd06 ble.n 801f0f6 801f0e8: 4b23 ldr r3, [pc, #140] ; (801f178 ) 801f0ea: f240 1283 movw r2, #387 ; 0x183 801f0ee: 4926 ldr r1, [pc, #152] ; (801f188 ) 801f0f0: 4823 ldr r0, [pc, #140] ; (801f180 ) 801f0f2: f002 fc49 bl 8021988 LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY", 801f0f6: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801f0fa: 491e ldr r1, [pc, #120] ; (801f174 ) 801f0fc: 4613 mov r3, r2 801f0fe: 005b lsls r3, r3, #1 801f100: 4413 add r3, r2 801f102: 00db lsls r3, r3, #3 801f104: 440b add r3, r1 801f106: 3314 adds r3, #20 801f108: 781b ldrb r3, [r3, #0] 801f10a: 2b00 cmp r3, #0 801f10c: d006 beq.n 801f11c 801f10e: 4b1a ldr r3, [pc, #104] ; (801f178 ) 801f110: f44f 72c2 mov.w r2, #388 ; 0x184 801f114: 491d ldr r1, [pc, #116] ; (801f18c ) 801f116: 481a ldr r0, [pc, #104] ; (801f180 ) 801f118: f002 fc36 bl 8021988 arp_table[i].state == ETHARP_STATE_EMPTY); /* IP address given? */ if (ipaddr != NULL) { 801f11c: 68fb ldr r3, [r7, #12] 801f11e: 2b00 cmp r3, #0 801f120: d00b beq.n 801f13a /* set IP address */ ip4_addr_copy(arp_table[i].ipaddr, *ipaddr); 801f122: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801f126: 68fb ldr r3, [r7, #12] 801f128: 6819 ldr r1, [r3, #0] 801f12a: 4812 ldr r0, [pc, #72] ; (801f174 ) 801f12c: 4613 mov r3, r2 801f12e: 005b lsls r3, r3, #1 801f130: 4413 add r3, r2 801f132: 00db lsls r3, r3, #3 801f134: 4403 add r3, r0 801f136: 3304 adds r3, #4 801f138: 6019 str r1, [r3, #0] } arp_table[i].ctime = 0; 801f13a: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801f13e: 490d ldr r1, [pc, #52] ; (801f174 ) 801f140: 4613 mov r3, r2 801f142: 005b lsls r3, r3, #1 801f144: 4413 add r3, r2 801f146: 00db lsls r3, r3, #3 801f148: 440b add r3, r1 801f14a: 3312 adds r3, #18 801f14c: 2200 movs r2, #0 801f14e: 801a strh r2, [r3, #0] #if ETHARP_TABLE_MATCH_NETIF arp_table[i].netif = netif; 801f150: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 801f154: 4907 ldr r1, [pc, #28] ; (801f174 ) 801f156: 4613 mov r3, r2 801f158: 005b lsls r3, r3, #1 801f15a: 4413 add r3, r2 801f15c: 00db lsls r3, r3, #3 801f15e: 440b add r3, r1 801f160: 3308 adds r3, #8 801f162: 687a ldr r2, [r7, #4] 801f164: 601a str r2, [r3, #0] #endif /* ETHARP_TABLE_MATCH_NETIF */ return (s16_t)i; 801f166: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 } 801f16a: 4618 mov r0, r3 801f16c: 3728 adds r7, #40 ; 0x28 801f16e: 46bd mov sp, r7 801f170: bd80 pop {r7, pc} 801f172: bf00 nop 801f174: 2401a4e4 .word 0x2401a4e4 801f178: 0802647c .word 0x0802647c 801f17c: 080264b4 .word 0x080264b4 801f180: 080264f4 .word 0x080264f4 801f184: 0802651c .word 0x0802651c 801f188: 08026534 .word 0x08026534 801f18c: 08026548 .word 0x08026548 0801f190 : * * @see pbuf_free() */ static err_t etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags) { 801f190: b580 push {r7, lr} 801f192: b088 sub sp, #32 801f194: af02 add r7, sp, #8 801f196: 60f8 str r0, [r7, #12] 801f198: 60b9 str r1, [r7, #8] 801f19a: 607a str r2, [r7, #4] 801f19c: 70fb strb r3, [r7, #3] s16_t i; LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN); 801f19e: 68fb ldr r3, [r7, #12] 801f1a0: f893 302c ldrb.w r3, [r3, #44] ; 0x2c 801f1a4: 2b06 cmp r3, #6 801f1a6: d006 beq.n 801f1b6 801f1a8: 4b48 ldr r3, [pc, #288] ; (801f2cc ) 801f1aa: f240 12a9 movw r2, #425 ; 0x1a9 801f1ae: 4948 ldr r1, [pc, #288] ; (801f2d0 ) 801f1b0: 4848 ldr r0, [pc, #288] ; (801f2d4 ) 801f1b2: f002 fbe9 bl 8021988 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr), (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2], (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5])); /* non-unicast address? */ if (ip4_addr_isany(ipaddr) || 801f1b6: 68bb ldr r3, [r7, #8] 801f1b8: 2b00 cmp r3, #0 801f1ba: d012 beq.n 801f1e2 801f1bc: 68bb ldr r3, [r7, #8] 801f1be: 681b ldr r3, [r3, #0] 801f1c0: 2b00 cmp r3, #0 801f1c2: d00e beq.n 801f1e2 ip4_addr_isbroadcast(ipaddr, netif) || 801f1c4: 68bb ldr r3, [r7, #8] 801f1c6: 681b ldr r3, [r3, #0] 801f1c8: 68f9 ldr r1, [r7, #12] 801f1ca: 4618 mov r0, r3 801f1cc: f001 f928 bl 8020420 801f1d0: 4603 mov r3, r0 if (ip4_addr_isany(ipaddr) || 801f1d2: 2b00 cmp r3, #0 801f1d4: d105 bne.n 801f1e2 ip4_addr_ismulticast(ipaddr)) { 801f1d6: 68bb ldr r3, [r7, #8] 801f1d8: 681b ldr r3, [r3, #0] 801f1da: f003 03f0 and.w r3, r3, #240 ; 0xf0 ip4_addr_isbroadcast(ipaddr, netif) || 801f1de: 2be0 cmp r3, #224 ; 0xe0 801f1e0: d102 bne.n 801f1e8 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n")); return ERR_ARG; 801f1e2: f06f 030f mvn.w r3, #15 801f1e6: e06c b.n 801f2c2 } /* find or create ARP entry */ i = etharp_find_entry(ipaddr, flags, netif); 801f1e8: 78fb ldrb r3, [r7, #3] 801f1ea: 68fa ldr r2, [r7, #12] 801f1ec: 4619 mov r1, r3 801f1ee: 68b8 ldr r0, [r7, #8] 801f1f0: f7ff fe56 bl 801eea0 801f1f4: 4603 mov r3, r0 801f1f6: 82fb strh r3, [r7, #22] /* bail out if no entry could be found */ if (i < 0) { 801f1f8: f9b7 3016 ldrsh.w r3, [r7, #22] 801f1fc: 2b00 cmp r3, #0 801f1fe: da02 bge.n 801f206 return (err_t)i; 801f200: 8afb ldrh r3, [r7, #22] 801f202: b25b sxtb r3, r3 801f204: e05d b.n 801f2c2 return ERR_VAL; } else #endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ { /* mark it stable */ arp_table[i].state = ETHARP_STATE_STABLE; 801f206: f9b7 2016 ldrsh.w r2, [r7, #22] 801f20a: 4933 ldr r1, [pc, #204] ; (801f2d8 ) 801f20c: 4613 mov r3, r2 801f20e: 005b lsls r3, r3, #1 801f210: 4413 add r3, r2 801f212: 00db lsls r3, r3, #3 801f214: 440b add r3, r1 801f216: 3314 adds r3, #20 801f218: 2202 movs r2, #2 801f21a: 701a strb r2, [r3, #0] } /* record network interface */ arp_table[i].netif = netif; 801f21c: f9b7 2016 ldrsh.w r2, [r7, #22] 801f220: 492d ldr r1, [pc, #180] ; (801f2d8 ) 801f222: 4613 mov r3, r2 801f224: 005b lsls r3, r3, #1 801f226: 4413 add r3, r2 801f228: 00db lsls r3, r3, #3 801f22a: 440b add r3, r1 801f22c: 3308 adds r3, #8 801f22e: 68fa ldr r2, [r7, #12] 801f230: 601a str r2, [r3, #0] /* insert in SNMP ARP index tree */ mib2_add_arp_entry(netif, &arp_table[i].ipaddr); LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i)); /* update address */ SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN); 801f232: f9b7 2016 ldrsh.w r2, [r7, #22] 801f236: 4613 mov r3, r2 801f238: 005b lsls r3, r3, #1 801f23a: 4413 add r3, r2 801f23c: 00db lsls r3, r3, #3 801f23e: 3308 adds r3, #8 801f240: 4a25 ldr r2, [pc, #148] ; (801f2d8 ) 801f242: 4413 add r3, r2 801f244: 3304 adds r3, #4 801f246: 2206 movs r2, #6 801f248: 6879 ldr r1, [r7, #4] 801f24a: 4618 mov r0, r3 801f24c: f002 fdcb bl 8021de6 /* reset time stamp */ arp_table[i].ctime = 0; 801f250: f9b7 2016 ldrsh.w r2, [r7, #22] 801f254: 4920 ldr r1, [pc, #128] ; (801f2d8 ) 801f256: 4613 mov r3, r2 801f258: 005b lsls r3, r3, #1 801f25a: 4413 add r3, r2 801f25c: 00db lsls r3, r3, #3 801f25e: 440b add r3, r1 801f260: 3312 adds r3, #18 801f262: 2200 movs r2, #0 801f264: 801a strh r2, [r3, #0] /* get the packet pointer */ p = q->p; /* now queue entry can be freed */ memp_free(MEMP_ARP_QUEUE, q); #else /* ARP_QUEUEING */ if (arp_table[i].q != NULL) { 801f266: f9b7 2016 ldrsh.w r2, [r7, #22] 801f26a: 491b ldr r1, [pc, #108] ; (801f2d8 ) 801f26c: 4613 mov r3, r2 801f26e: 005b lsls r3, r3, #1 801f270: 4413 add r3, r2 801f272: 00db lsls r3, r3, #3 801f274: 440b add r3, r1 801f276: 681b ldr r3, [r3, #0] 801f278: 2b00 cmp r3, #0 801f27a: d021 beq.n 801f2c0 struct pbuf *p = arp_table[i].q; 801f27c: f9b7 2016 ldrsh.w r2, [r7, #22] 801f280: 4915 ldr r1, [pc, #84] ; (801f2d8 ) 801f282: 4613 mov r3, r2 801f284: 005b lsls r3, r3, #1 801f286: 4413 add r3, r2 801f288: 00db lsls r3, r3, #3 801f28a: 440b add r3, r1 801f28c: 681b ldr r3, [r3, #0] 801f28e: 613b str r3, [r7, #16] arp_table[i].q = NULL; 801f290: f9b7 2016 ldrsh.w r2, [r7, #22] 801f294: 4910 ldr r1, [pc, #64] ; (801f2d8 ) 801f296: 4613 mov r3, r2 801f298: 005b lsls r3, r3, #1 801f29a: 4413 add r3, r2 801f29c: 00db lsls r3, r3, #3 801f29e: 440b add r3, r1 801f2a0: 2200 movs r2, #0 801f2a2: 601a str r2, [r3, #0] #endif /* ARP_QUEUEING */ /* send the queued IP packet */ ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP); 801f2a4: 68fb ldr r3, [r7, #12] 801f2a6: f103 0226 add.w r2, r3, #38 ; 0x26 801f2aa: f44f 6300 mov.w r3, #2048 ; 0x800 801f2ae: 9300 str r3, [sp, #0] 801f2b0: 687b ldr r3, [r7, #4] 801f2b2: 6939 ldr r1, [r7, #16] 801f2b4: 68f8 ldr r0, [r7, #12] 801f2b6: f001 ffc1 bl 802123c /* free the queued IP packet */ pbuf_free(p); 801f2ba: 6938 ldr r0, [r7, #16] 801f2bc: f7f8 fc1c bl 8017af8 } return ERR_OK; 801f2c0: 2300 movs r3, #0 } 801f2c2: 4618 mov r0, r3 801f2c4: 3718 adds r7, #24 801f2c6: 46bd mov sp, r7 801f2c8: bd80 pop {r7, pc} 801f2ca: bf00 nop 801f2cc: 0802647c .word 0x0802647c 801f2d0: 08026574 .word 0x08026574 801f2d4: 080264f4 .word 0x080264f4 801f2d8: 2401a4e4 .word 0x2401a4e4 0801f2dc : * * @param netif points to a network interface */ void etharp_cleanup_netif(struct netif *netif) { 801f2dc: b580 push {r7, lr} 801f2de: b084 sub sp, #16 801f2e0: af00 add r7, sp, #0 801f2e2: 6078 str r0, [r7, #4] int i; for (i = 0; i < ARP_TABLE_SIZE; ++i) { 801f2e4: 2300 movs r3, #0 801f2e6: 60fb str r3, [r7, #12] 801f2e8: e01e b.n 801f328 u8_t state = arp_table[i].state; 801f2ea: 4913 ldr r1, [pc, #76] ; (801f338 ) 801f2ec: 68fa ldr r2, [r7, #12] 801f2ee: 4613 mov r3, r2 801f2f0: 005b lsls r3, r3, #1 801f2f2: 4413 add r3, r2 801f2f4: 00db lsls r3, r3, #3 801f2f6: 440b add r3, r1 801f2f8: 3314 adds r3, #20 801f2fa: 781b ldrb r3, [r3, #0] 801f2fc: 72fb strb r3, [r7, #11] if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) { 801f2fe: 7afb ldrb r3, [r7, #11] 801f300: 2b00 cmp r3, #0 801f302: d00e beq.n 801f322 801f304: 490c ldr r1, [pc, #48] ; (801f338 ) 801f306: 68fa ldr r2, [r7, #12] 801f308: 4613 mov r3, r2 801f30a: 005b lsls r3, r3, #1 801f30c: 4413 add r3, r2 801f30e: 00db lsls r3, r3, #3 801f310: 440b add r3, r1 801f312: 3308 adds r3, #8 801f314: 681b ldr r3, [r3, #0] 801f316: 687a ldr r2, [r7, #4] 801f318: 429a cmp r2, r3 801f31a: d102 bne.n 801f322 etharp_free_entry(i); 801f31c: 68f8 ldr r0, [r7, #12] 801f31e: f7ff fcb7 bl 801ec90 for (i = 0; i < ARP_TABLE_SIZE; ++i) { 801f322: 68fb ldr r3, [r7, #12] 801f324: 3301 adds r3, #1 801f326: 60fb str r3, [r7, #12] 801f328: 68fb ldr r3, [r7, #12] 801f32a: 2b09 cmp r3, #9 801f32c: dddd ble.n 801f2ea } } } 801f32e: bf00 nop 801f330: bf00 nop 801f332: 3710 adds r7, #16 801f334: 46bd mov sp, r7 801f336: bd80 pop {r7, pc} 801f338: 2401a4e4 .word 0x2401a4e4 0801f33c : * * @see pbuf_free() */ void etharp_input(struct pbuf *p, struct netif *netif) { 801f33c: b5b0 push {r4, r5, r7, lr} 801f33e: b08a sub sp, #40 ; 0x28 801f340: af04 add r7, sp, #16 801f342: 6078 str r0, [r7, #4] 801f344: 6039 str r1, [r7, #0] ip4_addr_t sipaddr, dipaddr; u8_t for_us; LWIP_ASSERT_CORE_LOCKED(); LWIP_ERROR("netif != NULL", (netif != NULL), return;); 801f346: 683b ldr r3, [r7, #0] 801f348: 2b00 cmp r3, #0 801f34a: d107 bne.n 801f35c 801f34c: 4b3d ldr r3, [pc, #244] ; (801f444 ) 801f34e: f240 228a movw r2, #650 ; 0x28a 801f352: 493d ldr r1, [pc, #244] ; (801f448 ) 801f354: 483d ldr r0, [pc, #244] ; (801f44c ) 801f356: f002 fb17 bl 8021988 801f35a: e06f b.n 801f43c hdr = (struct etharp_hdr *)p->payload; 801f35c: 687b ldr r3, [r7, #4] 801f35e: 685b ldr r3, [r3, #4] 801f360: 617b str r3, [r7, #20] /* RFC 826 "Packet Reception": */ if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) || 801f362: 697b ldr r3, [r7, #20] 801f364: 881b ldrh r3, [r3, #0] 801f366: b29b uxth r3, r3 801f368: f5b3 7f80 cmp.w r3, #256 ; 0x100 801f36c: d10c bne.n 801f388 (hdr->hwlen != ETH_HWADDR_LEN) || 801f36e: 697b ldr r3, [r7, #20] 801f370: 791b ldrb r3, [r3, #4] if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) || 801f372: 2b06 cmp r3, #6 801f374: d108 bne.n 801f388 (hdr->protolen != sizeof(ip4_addr_t)) || 801f376: 697b ldr r3, [r7, #20] 801f378: 795b ldrb r3, [r3, #5] (hdr->hwlen != ETH_HWADDR_LEN) || 801f37a: 2b04 cmp r3, #4 801f37c: d104 bne.n 801f388 (hdr->proto != PP_HTONS(ETHTYPE_IP))) { 801f37e: 697b ldr r3, [r7, #20] 801f380: 885b ldrh r3, [r3, #2] 801f382: b29b uxth r3, r3 (hdr->protolen != sizeof(ip4_addr_t)) || 801f384: 2b08 cmp r3, #8 801f386: d003 beq.n 801f390 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n", hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen)); ETHARP_STATS_INC(etharp.proterr); ETHARP_STATS_INC(etharp.drop); pbuf_free(p); 801f388: 6878 ldr r0, [r7, #4] 801f38a: f7f8 fbb5 bl 8017af8 return; 801f38e: e055 b.n 801f43c autoip_arp_reply(netif, hdr); #endif /* LWIP_AUTOIP */ /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without * structure packing (not using structure copy which breaks strict-aliasing rules). */ IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr); 801f390: 697b ldr r3, [r7, #20] 801f392: 330e adds r3, #14 801f394: 681b ldr r3, [r3, #0] 801f396: 60fb str r3, [r7, #12] IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr); 801f398: 697b ldr r3, [r7, #20] 801f39a: 3318 adds r3, #24 801f39c: 681b ldr r3, [r3, #0] 801f39e: 60bb str r3, [r7, #8] /* this interface is not configured? */ if (ip4_addr_isany_val(*netif_ip4_addr(netif))) { 801f3a0: 683b ldr r3, [r7, #0] 801f3a2: 3304 adds r3, #4 801f3a4: 681b ldr r3, [r3, #0] 801f3a6: 2b00 cmp r3, #0 801f3a8: d102 bne.n 801f3b0 for_us = 0; 801f3aa: 2300 movs r3, #0 801f3ac: 74fb strb r3, [r7, #19] 801f3ae: e009 b.n 801f3c4 } else { /* ARP packet directed to us? */ for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif)); 801f3b0: 68ba ldr r2, [r7, #8] 801f3b2: 683b ldr r3, [r7, #0] 801f3b4: 3304 adds r3, #4 801f3b6: 681b ldr r3, [r3, #0] 801f3b8: 429a cmp r2, r3 801f3ba: bf0c ite eq 801f3bc: 2301 moveq r3, #1 801f3be: 2300 movne r3, #0 801f3c0: b2db uxtb r3, r3 801f3c2: 74fb strb r3, [r7, #19] /* ARP message directed to us? -> add IP address in ARP cache; assume requester wants to talk to us, can result in directly sending the queued packets for this host. ARP message not directed to us? -> update the source IP address in the cache, if present */ etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 801f3c4: 697b ldr r3, [r7, #20] 801f3c6: f103 0208 add.w r2, r3, #8 801f3ca: 7cfb ldrb r3, [r7, #19] 801f3cc: 2b00 cmp r3, #0 801f3ce: d001 beq.n 801f3d4 801f3d0: 2301 movs r3, #1 801f3d2: e000 b.n 801f3d6 801f3d4: 2302 movs r3, #2 801f3d6: f107 010c add.w r1, r7, #12 801f3da: 6838 ldr r0, [r7, #0] 801f3dc: f7ff fed8 bl 801f190 for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY); /* now act on the message itself */ switch (hdr->opcode) { 801f3e0: 697b ldr r3, [r7, #20] 801f3e2: 88db ldrh r3, [r3, #6] 801f3e4: b29b uxth r3, r3 801f3e6: f5b3 7f80 cmp.w r3, #256 ; 0x100 801f3ea: d003 beq.n 801f3f4 801f3ec: f5b3 7f00 cmp.w r3, #512 ; 0x200 801f3f0: d01e beq.n 801f430 #endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */ break; default: LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode))); ETHARP_STATS_INC(etharp.err); break; 801f3f2: e020 b.n 801f436 if (for_us) { 801f3f4: 7cfb ldrb r3, [r7, #19] 801f3f6: 2b00 cmp r3, #0 801f3f8: d01c beq.n 801f434 (struct eth_addr *)netif->hwaddr, &hdr->shwaddr, 801f3fa: 683b ldr r3, [r7, #0] 801f3fc: f103 0026 add.w r0, r3, #38 ; 0x26 801f400: 697b ldr r3, [r7, #20] 801f402: f103 0408 add.w r4, r3, #8 (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), 801f406: 683b ldr r3, [r7, #0] 801f408: f103 0526 add.w r5, r3, #38 ; 0x26 801f40c: 683b ldr r3, [r7, #0] 801f40e: 3304 adds r3, #4 &hdr->shwaddr, &sipaddr, 801f410: 697a ldr r2, [r7, #20] 801f412: 3208 adds r2, #8 etharp_raw(netif, 801f414: 2102 movs r1, #2 801f416: 9103 str r1, [sp, #12] 801f418: f107 010c add.w r1, r7, #12 801f41c: 9102 str r1, [sp, #8] 801f41e: 9201 str r2, [sp, #4] 801f420: 9300 str r3, [sp, #0] 801f422: 462b mov r3, r5 801f424: 4622 mov r2, r4 801f426: 4601 mov r1, r0 801f428: 6838 ldr r0, [r7, #0] 801f42a: f000 faeb bl 801fa04 break; 801f42e: e001 b.n 801f434 break; 801f430: bf00 nop 801f432: e000 b.n 801f436 break; 801f434: bf00 nop } /* free ARP packet */ pbuf_free(p); 801f436: 6878 ldr r0, [r7, #4] 801f438: f7f8 fb5e bl 8017af8 } 801f43c: 3718 adds r7, #24 801f43e: 46bd mov sp, r7 801f440: bdb0 pop {r4, r5, r7, pc} 801f442: bf00 nop 801f444: 0802647c .word 0x0802647c 801f448: 080265cc .word 0x080265cc 801f44c: 080264f4 .word 0x080264f4 0801f450 : /** Just a small helper function that sends a pbuf to an ethernet address * in the arp_table specified by the index 'arp_idx'. */ static err_t etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx) { 801f450: b580 push {r7, lr} 801f452: b086 sub sp, #24 801f454: af02 add r7, sp, #8 801f456: 60f8 str r0, [r7, #12] 801f458: 60b9 str r1, [r7, #8] 801f45a: 4613 mov r3, r2 801f45c: 71fb strb r3, [r7, #7] LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE", 801f45e: 79fa ldrb r2, [r7, #7] 801f460: 4944 ldr r1, [pc, #272] ; (801f574 ) 801f462: 4613 mov r3, r2 801f464: 005b lsls r3, r3, #1 801f466: 4413 add r3, r2 801f468: 00db lsls r3, r3, #3 801f46a: 440b add r3, r1 801f46c: 3314 adds r3, #20 801f46e: 781b ldrb r3, [r3, #0] 801f470: 2b01 cmp r3, #1 801f472: d806 bhi.n 801f482 801f474: 4b40 ldr r3, [pc, #256] ; (801f578 ) 801f476: f240 22ee movw r2, #750 ; 0x2ee 801f47a: 4940 ldr r1, [pc, #256] ; (801f57c ) 801f47c: 4840 ldr r0, [pc, #256] ; (801f580 ) 801f47e: f002 fa83 bl 8021988 arp_table[arp_idx].state >= ETHARP_STATE_STABLE); /* if arp table entry is about to expire: re-request it, but only if its state is ETHARP_STATE_STABLE to prevent flooding the network with ARP requests if this address is used frequently. */ if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) { 801f482: 79fa ldrb r2, [r7, #7] 801f484: 493b ldr r1, [pc, #236] ; (801f574 ) 801f486: 4613 mov r3, r2 801f488: 005b lsls r3, r3, #1 801f48a: 4413 add r3, r2 801f48c: 00db lsls r3, r3, #3 801f48e: 440b add r3, r1 801f490: 3314 adds r3, #20 801f492: 781b ldrb r3, [r3, #0] 801f494: 2b02 cmp r3, #2 801f496: d153 bne.n 801f540 if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) { 801f498: 79fa ldrb r2, [r7, #7] 801f49a: 4936 ldr r1, [pc, #216] ; (801f574 ) 801f49c: 4613 mov r3, r2 801f49e: 005b lsls r3, r3, #1 801f4a0: 4413 add r3, r2 801f4a2: 00db lsls r3, r3, #3 801f4a4: 440b add r3, r1 801f4a6: 3312 adds r3, #18 801f4a8: 881b ldrh r3, [r3, #0] 801f4aa: f5b3 7f8e cmp.w r3, #284 ; 0x11c 801f4ae: d919 bls.n 801f4e4 /* issue a standard request using broadcast */ if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) { 801f4b0: 79fa ldrb r2, [r7, #7] 801f4b2: 4613 mov r3, r2 801f4b4: 005b lsls r3, r3, #1 801f4b6: 4413 add r3, r2 801f4b8: 00db lsls r3, r3, #3 801f4ba: 4a2e ldr r2, [pc, #184] ; (801f574 ) 801f4bc: 4413 add r3, r2 801f4be: 3304 adds r3, #4 801f4c0: 4619 mov r1, r3 801f4c2: 68f8 ldr r0, [r7, #12] 801f4c4: f000 fb4c bl 801fb60 801f4c8: 4603 mov r3, r0 801f4ca: 2b00 cmp r3, #0 801f4cc: d138 bne.n 801f540 arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1; 801f4ce: 79fa ldrb r2, [r7, #7] 801f4d0: 4928 ldr r1, [pc, #160] ; (801f574 ) 801f4d2: 4613 mov r3, r2 801f4d4: 005b lsls r3, r3, #1 801f4d6: 4413 add r3, r2 801f4d8: 00db lsls r3, r3, #3 801f4da: 440b add r3, r1 801f4dc: 3314 adds r3, #20 801f4de: 2203 movs r2, #3 801f4e0: 701a strb r2, [r3, #0] 801f4e2: e02d b.n 801f540 } } else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) { 801f4e4: 79fa ldrb r2, [r7, #7] 801f4e6: 4923 ldr r1, [pc, #140] ; (801f574 ) 801f4e8: 4613 mov r3, r2 801f4ea: 005b lsls r3, r3, #1 801f4ec: 4413 add r3, r2 801f4ee: 00db lsls r3, r3, #3 801f4f0: 440b add r3, r1 801f4f2: 3312 adds r3, #18 801f4f4: 881b ldrh r3, [r3, #0] 801f4f6: f5b3 7f87 cmp.w r3, #270 ; 0x10e 801f4fa: d321 bcc.n 801f540 /* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */ if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) { 801f4fc: 79fa ldrb r2, [r7, #7] 801f4fe: 4613 mov r3, r2 801f500: 005b lsls r3, r3, #1 801f502: 4413 add r3, r2 801f504: 00db lsls r3, r3, #3 801f506: 4a1b ldr r2, [pc, #108] ; (801f574 ) 801f508: 4413 add r3, r2 801f50a: 1d19 adds r1, r3, #4 801f50c: 79fa ldrb r2, [r7, #7] 801f50e: 4613 mov r3, r2 801f510: 005b lsls r3, r3, #1 801f512: 4413 add r3, r2 801f514: 00db lsls r3, r3, #3 801f516: 3308 adds r3, #8 801f518: 4a16 ldr r2, [pc, #88] ; (801f574 ) 801f51a: 4413 add r3, r2 801f51c: 3304 adds r3, #4 801f51e: 461a mov r2, r3 801f520: 68f8 ldr r0, [r7, #12] 801f522: f000 fafb bl 801fb1c 801f526: 4603 mov r3, r0 801f528: 2b00 cmp r3, #0 801f52a: d109 bne.n 801f540 arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1; 801f52c: 79fa ldrb r2, [r7, #7] 801f52e: 4911 ldr r1, [pc, #68] ; (801f574 ) 801f530: 4613 mov r3, r2 801f532: 005b lsls r3, r3, #1 801f534: 4413 add r3, r2 801f536: 00db lsls r3, r3, #3 801f538: 440b add r3, r1 801f53a: 3314 adds r3, #20 801f53c: 2203 movs r2, #3 801f53e: 701a strb r2, [r3, #0] } } } return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP); 801f540: 68fb ldr r3, [r7, #12] 801f542: f103 0126 add.w r1, r3, #38 ; 0x26 801f546: 79fa ldrb r2, [r7, #7] 801f548: 4613 mov r3, r2 801f54a: 005b lsls r3, r3, #1 801f54c: 4413 add r3, r2 801f54e: 00db lsls r3, r3, #3 801f550: 3308 adds r3, #8 801f552: 4a08 ldr r2, [pc, #32] ; (801f574 ) 801f554: 4413 add r3, r2 801f556: 3304 adds r3, #4 801f558: f44f 6200 mov.w r2, #2048 ; 0x800 801f55c: 9200 str r2, [sp, #0] 801f55e: 460a mov r2, r1 801f560: 68b9 ldr r1, [r7, #8] 801f562: 68f8 ldr r0, [r7, #12] 801f564: f001 fe6a bl 802123c 801f568: 4603 mov r3, r0 } 801f56a: 4618 mov r0, r3 801f56c: 3710 adds r7, #16 801f56e: 46bd mov sp, r7 801f570: bd80 pop {r7, pc} 801f572: bf00 nop 801f574: 2401a4e4 .word 0x2401a4e4 801f578: 0802647c .word 0x0802647c 801f57c: 080265ec .word 0x080265ec 801f580: 080264f4 .word 0x080264f4 0801f584 : * - ERR_RTE No route to destination (no gateway to external networks), * or the return type of either etharp_query() or ethernet_output(). */ err_t etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr) { 801f584: b580 push {r7, lr} 801f586: b08a sub sp, #40 ; 0x28 801f588: af02 add r7, sp, #8 801f58a: 60f8 str r0, [r7, #12] 801f58c: 60b9 str r1, [r7, #8] 801f58e: 607a str r2, [r7, #4] const struct eth_addr *dest; struct eth_addr mcastaddr; const ip4_addr_t *dst_addr = ipaddr; 801f590: 687b ldr r3, [r7, #4] 801f592: 61bb str r3, [r7, #24] LWIP_ASSERT_CORE_LOCKED(); LWIP_ASSERT("netif != NULL", netif != NULL); 801f594: 68fb ldr r3, [r7, #12] 801f596: 2b00 cmp r3, #0 801f598: d106 bne.n 801f5a8 801f59a: 4b73 ldr r3, [pc, #460] ; (801f768 ) 801f59c: f240 321e movw r2, #798 ; 0x31e 801f5a0: 4972 ldr r1, [pc, #456] ; (801f76c ) 801f5a2: 4873 ldr r0, [pc, #460] ; (801f770 ) 801f5a4: f002 f9f0 bl 8021988 LWIP_ASSERT("q != NULL", q != NULL); 801f5a8: 68bb ldr r3, [r7, #8] 801f5aa: 2b00 cmp r3, #0 801f5ac: d106 bne.n 801f5bc 801f5ae: 4b6e ldr r3, [pc, #440] ; (801f768 ) 801f5b0: f240 321f movw r2, #799 ; 0x31f 801f5b4: 496f ldr r1, [pc, #444] ; (801f774 ) 801f5b6: 486e ldr r0, [pc, #440] ; (801f770 ) 801f5b8: f002 f9e6 bl 8021988 LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL); 801f5bc: 687b ldr r3, [r7, #4] 801f5be: 2b00 cmp r3, #0 801f5c0: d106 bne.n 801f5d0 801f5c2: 4b69 ldr r3, [pc, #420] ; (801f768 ) 801f5c4: f44f 7248 mov.w r2, #800 ; 0x320 801f5c8: 496b ldr r1, [pc, #428] ; (801f778 ) 801f5ca: 4869 ldr r0, [pc, #420] ; (801f770 ) 801f5cc: f002 f9dc bl 8021988 /* Determine on destination hardware address. Broadcasts and multicasts * are special, other IP addresses are looked up in the ARP table. */ /* broadcast destination IP address? */ if (ip4_addr_isbroadcast(ipaddr, netif)) { 801f5d0: 687b ldr r3, [r7, #4] 801f5d2: 681b ldr r3, [r3, #0] 801f5d4: 68f9 ldr r1, [r7, #12] 801f5d6: 4618 mov r0, r3 801f5d8: f000 ff22 bl 8020420 801f5dc: 4603 mov r3, r0 801f5de: 2b00 cmp r3, #0 801f5e0: d002 beq.n 801f5e8 /* broadcast on Ethernet also */ dest = (const struct eth_addr *)ðbroadcast; 801f5e2: 4b66 ldr r3, [pc, #408] ; (801f77c ) 801f5e4: 61fb str r3, [r7, #28] 801f5e6: e0af b.n 801f748 /* multicast destination IP address? */ } else if (ip4_addr_ismulticast(ipaddr)) { 801f5e8: 687b ldr r3, [r7, #4] 801f5ea: 681b ldr r3, [r3, #0] 801f5ec: f003 03f0 and.w r3, r3, #240 ; 0xf0 801f5f0: 2be0 cmp r3, #224 ; 0xe0 801f5f2: d118 bne.n 801f626 /* Hash IP multicast address to MAC address.*/ mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0; 801f5f4: 2301 movs r3, #1 801f5f6: 743b strb r3, [r7, #16] mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1; 801f5f8: 2300 movs r3, #0 801f5fa: 747b strb r3, [r7, #17] mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2; 801f5fc: 235e movs r3, #94 ; 0x5e 801f5fe: 74bb strb r3, [r7, #18] mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; 801f600: 687b ldr r3, [r7, #4] 801f602: 3301 adds r3, #1 801f604: 781b ldrb r3, [r3, #0] 801f606: f003 037f and.w r3, r3, #127 ; 0x7f 801f60a: b2db uxtb r3, r3 801f60c: 74fb strb r3, [r7, #19] mcastaddr.addr[4] = ip4_addr3(ipaddr); 801f60e: 687b ldr r3, [r7, #4] 801f610: 3302 adds r3, #2 801f612: 781b ldrb r3, [r3, #0] 801f614: 753b strb r3, [r7, #20] mcastaddr.addr[5] = ip4_addr4(ipaddr); 801f616: 687b ldr r3, [r7, #4] 801f618: 3303 adds r3, #3 801f61a: 781b ldrb r3, [r3, #0] 801f61c: 757b strb r3, [r7, #21] /* destination Ethernet address is multicast */ dest = &mcastaddr; 801f61e: f107 0310 add.w r3, r7, #16 801f622: 61fb str r3, [r7, #28] 801f624: e090 b.n 801f748 /* unicast destination IP address? */ } else { netif_addr_idx_t i; /* outside local network? if so, this can neither be a global broadcast nor a subnet broadcast. */ if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) && 801f626: 687b ldr r3, [r7, #4] 801f628: 681a ldr r2, [r3, #0] 801f62a: 68fb ldr r3, [r7, #12] 801f62c: 3304 adds r3, #4 801f62e: 681b ldr r3, [r3, #0] 801f630: 405a eors r2, r3 801f632: 68fb ldr r3, [r7, #12] 801f634: 3308 adds r3, #8 801f636: 681b ldr r3, [r3, #0] 801f638: 4013 ands r3, r2 801f63a: 2b00 cmp r3, #0 801f63c: d012 beq.n 801f664 !ip4_addr_islinklocal(ipaddr)) { 801f63e: 687b ldr r3, [r7, #4] 801f640: 681b ldr r3, [r3, #0] 801f642: b29b uxth r3, r3 if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) && 801f644: f64f 62a9 movw r2, #65193 ; 0xfea9 801f648: 4293 cmp r3, r2 801f64a: d00b beq.n 801f664 dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr); if (dst_addr == NULL) #endif /* LWIP_HOOK_ETHARP_GET_GW */ { /* interface has default gateway? */ if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) { 801f64c: 68fb ldr r3, [r7, #12] 801f64e: 330c adds r3, #12 801f650: 681b ldr r3, [r3, #0] 801f652: 2b00 cmp r3, #0 801f654: d003 beq.n 801f65e /* send to hardware address of default gateway IP address */ dst_addr = netif_ip4_gw(netif); 801f656: 68fb ldr r3, [r7, #12] 801f658: 330c adds r3, #12 801f65a: 61bb str r3, [r7, #24] 801f65c: e002 b.n 801f664 /* no default gateway available */ } else { /* no route to destination error (default gateway missing) */ return ERR_RTE; 801f65e: f06f 0303 mvn.w r3, #3 801f662: e07d b.n 801f760 if (netif->hints != NULL) { /* per-pcb cached entry was given */ netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint; if (etharp_cached_entry < ARP_TABLE_SIZE) { #endif /* LWIP_NETIF_HWADDRHINT */ if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) && 801f664: 4b46 ldr r3, [pc, #280] ; (801f780 ) 801f666: 781b ldrb r3, [r3, #0] 801f668: 4619 mov r1, r3 801f66a: 4a46 ldr r2, [pc, #280] ; (801f784 ) 801f66c: 460b mov r3, r1 801f66e: 005b lsls r3, r3, #1 801f670: 440b add r3, r1 801f672: 00db lsls r3, r3, #3 801f674: 4413 add r3, r2 801f676: 3314 adds r3, #20 801f678: 781b ldrb r3, [r3, #0] 801f67a: 2b01 cmp r3, #1 801f67c: d925 bls.n 801f6ca #if ETHARP_TABLE_MATCH_NETIF (arp_table[etharp_cached_entry].netif == netif) && 801f67e: 4b40 ldr r3, [pc, #256] ; (801f780 ) 801f680: 781b ldrb r3, [r3, #0] 801f682: 4619 mov r1, r3 801f684: 4a3f ldr r2, [pc, #252] ; (801f784 ) 801f686: 460b mov r3, r1 801f688: 005b lsls r3, r3, #1 801f68a: 440b add r3, r1 801f68c: 00db lsls r3, r3, #3 801f68e: 4413 add r3, r2 801f690: 3308 adds r3, #8 801f692: 681b ldr r3, [r3, #0] if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) && 801f694: 68fa ldr r2, [r7, #12] 801f696: 429a cmp r2, r3 801f698: d117 bne.n 801f6ca #endif (ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) { 801f69a: 69bb ldr r3, [r7, #24] 801f69c: 681a ldr r2, [r3, #0] 801f69e: 4b38 ldr r3, [pc, #224] ; (801f780 ) 801f6a0: 781b ldrb r3, [r3, #0] 801f6a2: 4618 mov r0, r3 801f6a4: 4937 ldr r1, [pc, #220] ; (801f784 ) 801f6a6: 4603 mov r3, r0 801f6a8: 005b lsls r3, r3, #1 801f6aa: 4403 add r3, r0 801f6ac: 00db lsls r3, r3, #3 801f6ae: 440b add r3, r1 801f6b0: 3304 adds r3, #4 801f6b2: 681b ldr r3, [r3, #0] (arp_table[etharp_cached_entry].netif == netif) && 801f6b4: 429a cmp r2, r3 801f6b6: d108 bne.n 801f6ca /* the per-pcb-cached entry is stable and the right one! */ ETHARP_STATS_INC(etharp.cachehit); return etharp_output_to_arp_index(netif, q, etharp_cached_entry); 801f6b8: 4b31 ldr r3, [pc, #196] ; (801f780 ) 801f6ba: 781b ldrb r3, [r3, #0] 801f6bc: 461a mov r2, r3 801f6be: 68b9 ldr r1, [r7, #8] 801f6c0: 68f8 ldr r0, [r7, #12] 801f6c2: f7ff fec5 bl 801f450 801f6c6: 4603 mov r3, r0 801f6c8: e04a b.n 801f760 } #endif /* LWIP_NETIF_HWADDRHINT */ /* find stable entry: do this here since this is a critical path for throughput and etharp_find_entry() is kind of slow */ for (i = 0; i < ARP_TABLE_SIZE; i++) { 801f6ca: 2300 movs r3, #0 801f6cc: 75fb strb r3, [r7, #23] 801f6ce: e031 b.n 801f734 if ((arp_table[i].state >= ETHARP_STATE_STABLE) && 801f6d0: 7dfa ldrb r2, [r7, #23] 801f6d2: 492c ldr r1, [pc, #176] ; (801f784 ) 801f6d4: 4613 mov r3, r2 801f6d6: 005b lsls r3, r3, #1 801f6d8: 4413 add r3, r2 801f6da: 00db lsls r3, r3, #3 801f6dc: 440b add r3, r1 801f6de: 3314 adds r3, #20 801f6e0: 781b ldrb r3, [r3, #0] 801f6e2: 2b01 cmp r3, #1 801f6e4: d923 bls.n 801f72e #if ETHARP_TABLE_MATCH_NETIF (arp_table[i].netif == netif) && 801f6e6: 7dfa ldrb r2, [r7, #23] 801f6e8: 4926 ldr r1, [pc, #152] ; (801f784 ) 801f6ea: 4613 mov r3, r2 801f6ec: 005b lsls r3, r3, #1 801f6ee: 4413 add r3, r2 801f6f0: 00db lsls r3, r3, #3 801f6f2: 440b add r3, r1 801f6f4: 3308 adds r3, #8 801f6f6: 681b ldr r3, [r3, #0] if ((arp_table[i].state >= ETHARP_STATE_STABLE) && 801f6f8: 68fa ldr r2, [r7, #12] 801f6fa: 429a cmp r2, r3 801f6fc: d117 bne.n 801f72e #endif (ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) { 801f6fe: 69bb ldr r3, [r7, #24] 801f700: 6819 ldr r1, [r3, #0] 801f702: 7dfa ldrb r2, [r7, #23] 801f704: 481f ldr r0, [pc, #124] ; (801f784 ) 801f706: 4613 mov r3, r2 801f708: 005b lsls r3, r3, #1 801f70a: 4413 add r3, r2 801f70c: 00db lsls r3, r3, #3 801f70e: 4403 add r3, r0 801f710: 3304 adds r3, #4 801f712: 681b ldr r3, [r3, #0] (arp_table[i].netif == netif) && 801f714: 4299 cmp r1, r3 801f716: d10a bne.n 801f72e /* found an existing, stable entry */ ETHARP_SET_ADDRHINT(netif, i); 801f718: 4a19 ldr r2, [pc, #100] ; (801f780 ) 801f71a: 7dfb ldrb r3, [r7, #23] 801f71c: 7013 strb r3, [r2, #0] return etharp_output_to_arp_index(netif, q, i); 801f71e: 7dfb ldrb r3, [r7, #23] 801f720: 461a mov r2, r3 801f722: 68b9 ldr r1, [r7, #8] 801f724: 68f8 ldr r0, [r7, #12] 801f726: f7ff fe93 bl 801f450 801f72a: 4603 mov r3, r0 801f72c: e018 b.n 801f760 for (i = 0; i < ARP_TABLE_SIZE; i++) { 801f72e: 7dfb ldrb r3, [r7, #23] 801f730: 3301 adds r3, #1 801f732: 75fb strb r3, [r7, #23] 801f734: 7dfb ldrb r3, [r7, #23] 801f736: 2b09 cmp r3, #9 801f738: d9ca bls.n 801f6d0 } } /* no stable entry found, use the (slower) query function: queue on destination Ethernet address belonging to ipaddr */ return etharp_query(netif, dst_addr, q); 801f73a: 68ba ldr r2, [r7, #8] 801f73c: 69b9 ldr r1, [r7, #24] 801f73e: 68f8 ldr r0, [r7, #12] 801f740: f000 f822 bl 801f788 801f744: 4603 mov r3, r0 801f746: e00b b.n 801f760 } /* continuation for multicast/broadcast destinations */ /* obtain source Ethernet address of the given interface */ /* send packet directly on the link */ return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP); 801f748: 68fb ldr r3, [r7, #12] 801f74a: f103 0226 add.w r2, r3, #38 ; 0x26 801f74e: f44f 6300 mov.w r3, #2048 ; 0x800 801f752: 9300 str r3, [sp, #0] 801f754: 69fb ldr r3, [r7, #28] 801f756: 68b9 ldr r1, [r7, #8] 801f758: 68f8 ldr r0, [r7, #12] 801f75a: f001 fd6f bl 802123c 801f75e: 4603 mov r3, r0 } 801f760: 4618 mov r0, r3 801f762: 3720 adds r7, #32 801f764: 46bd mov sp, r7 801f766: bd80 pop {r7, pc} 801f768: 0802647c .word 0x0802647c 801f76c: 080265cc .word 0x080265cc 801f770: 080264f4 .word 0x080264f4 801f774: 0802661c .word 0x0802661c 801f778: 080265bc .word 0x080265bc 801f77c: 08026cf0 .word 0x08026cf0 801f780: 2401a5d4 .word 0x2401a5d4 801f784: 2401a4e4 .word 0x2401a4e4 0801f788 : * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. * */ err_t etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q) { 801f788: b580 push {r7, lr} 801f78a: b08c sub sp, #48 ; 0x30 801f78c: af02 add r7, sp, #8 801f78e: 60f8 str r0, [r7, #12] 801f790: 60b9 str r1, [r7, #8] 801f792: 607a str r2, [r7, #4] struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr; 801f794: 68fb ldr r3, [r7, #12] 801f796: 3326 adds r3, #38 ; 0x26 801f798: 617b str r3, [r7, #20] err_t result = ERR_MEM; 801f79a: 23ff movs r3, #255 ; 0xff 801f79c: f887 3027 strb.w r3, [r7, #39] ; 0x27 int is_new_entry = 0; 801f7a0: 2300 movs r3, #0 801f7a2: 623b str r3, [r7, #32] s16_t i_err; netif_addr_idx_t i; /* non-unicast address? */ if (ip4_addr_isbroadcast(ipaddr, netif) || 801f7a4: 68bb ldr r3, [r7, #8] 801f7a6: 681b ldr r3, [r3, #0] 801f7a8: 68f9 ldr r1, [r7, #12] 801f7aa: 4618 mov r0, r3 801f7ac: f000 fe38 bl 8020420 801f7b0: 4603 mov r3, r0 801f7b2: 2b00 cmp r3, #0 801f7b4: d10c bne.n 801f7d0 ip4_addr_ismulticast(ipaddr) || 801f7b6: 68bb ldr r3, [r7, #8] 801f7b8: 681b ldr r3, [r3, #0] 801f7ba: f003 03f0 and.w r3, r3, #240 ; 0xf0 if (ip4_addr_isbroadcast(ipaddr, netif) || 801f7be: 2be0 cmp r3, #224 ; 0xe0 801f7c0: d006 beq.n 801f7d0 ip4_addr_ismulticast(ipaddr) || 801f7c2: 68bb ldr r3, [r7, #8] 801f7c4: 2b00 cmp r3, #0 801f7c6: d003 beq.n 801f7d0 ip4_addr_isany(ipaddr)) { 801f7c8: 68bb ldr r3, [r7, #8] 801f7ca: 681b ldr r3, [r3, #0] 801f7cc: 2b00 cmp r3, #0 801f7ce: d102 bne.n 801f7d6 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); return ERR_ARG; 801f7d0: f06f 030f mvn.w r3, #15 801f7d4: e101 b.n 801f9da } /* find entry in ARP cache, ask to create entry if queueing packet */ i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif); 801f7d6: 68fa ldr r2, [r7, #12] 801f7d8: 2101 movs r1, #1 801f7da: 68b8 ldr r0, [r7, #8] 801f7dc: f7ff fb60 bl 801eea0 801f7e0: 4603 mov r3, r0 801f7e2: 827b strh r3, [r7, #18] /* could not find or create entry? */ if (i_err < 0) { 801f7e4: f9b7 3012 ldrsh.w r3, [r7, #18] 801f7e8: 2b00 cmp r3, #0 801f7ea: da02 bge.n 801f7f2 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n")); if (q) { LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n")); ETHARP_STATS_INC(etharp.memerr); } return (err_t)i_err; 801f7ec: 8a7b ldrh r3, [r7, #18] 801f7ee: b25b sxtb r3, r3 801f7f0: e0f3 b.n 801f9da } LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX); 801f7f2: 8a7b ldrh r3, [r7, #18] 801f7f4: 2b7e cmp r3, #126 ; 0x7e 801f7f6: d906 bls.n 801f806 801f7f8: 4b7a ldr r3, [pc, #488] ; (801f9e4 ) 801f7fa: f240 32c1 movw r2, #961 ; 0x3c1 801f7fe: 497a ldr r1, [pc, #488] ; (801f9e8 ) 801f800: 487a ldr r0, [pc, #488] ; (801f9ec ) 801f802: f002 f8c1 bl 8021988 i = (netif_addr_idx_t)i_err; 801f806: 8a7b ldrh r3, [r7, #18] 801f808: 747b strb r3, [r7, #17] /* mark a fresh entry as pending (we just sent a request) */ if (arp_table[i].state == ETHARP_STATE_EMPTY) { 801f80a: 7c7a ldrb r2, [r7, #17] 801f80c: 4978 ldr r1, [pc, #480] ; (801f9f0 ) 801f80e: 4613 mov r3, r2 801f810: 005b lsls r3, r3, #1 801f812: 4413 add r3, r2 801f814: 00db lsls r3, r3, #3 801f816: 440b add r3, r1 801f818: 3314 adds r3, #20 801f81a: 781b ldrb r3, [r3, #0] 801f81c: 2b00 cmp r3, #0 801f81e: d115 bne.n 801f84c is_new_entry = 1; 801f820: 2301 movs r3, #1 801f822: 623b str r3, [r7, #32] arp_table[i].state = ETHARP_STATE_PENDING; 801f824: 7c7a ldrb r2, [r7, #17] 801f826: 4972 ldr r1, [pc, #456] ; (801f9f0 ) 801f828: 4613 mov r3, r2 801f82a: 005b lsls r3, r3, #1 801f82c: 4413 add r3, r2 801f82e: 00db lsls r3, r3, #3 801f830: 440b add r3, r1 801f832: 3314 adds r3, #20 801f834: 2201 movs r2, #1 801f836: 701a strb r2, [r3, #0] /* record network interface for re-sending arp request in etharp_tmr */ arp_table[i].netif = netif; 801f838: 7c7a ldrb r2, [r7, #17] 801f83a: 496d ldr r1, [pc, #436] ; (801f9f0 ) 801f83c: 4613 mov r3, r2 801f83e: 005b lsls r3, r3, #1 801f840: 4413 add r3, r2 801f842: 00db lsls r3, r3, #3 801f844: 440b add r3, r1 801f846: 3308 adds r3, #8 801f848: 68fa ldr r2, [r7, #12] 801f84a: 601a str r2, [r3, #0] } /* { i is either a STABLE or (new or existing) PENDING entry } */ LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", 801f84c: 7c7a ldrb r2, [r7, #17] 801f84e: 4968 ldr r1, [pc, #416] ; (801f9f0 ) 801f850: 4613 mov r3, r2 801f852: 005b lsls r3, r3, #1 801f854: 4413 add r3, r2 801f856: 00db lsls r3, r3, #3 801f858: 440b add r3, r1 801f85a: 3314 adds r3, #20 801f85c: 781b ldrb r3, [r3, #0] 801f85e: 2b01 cmp r3, #1 801f860: d011 beq.n 801f886 801f862: 7c7a ldrb r2, [r7, #17] 801f864: 4962 ldr r1, [pc, #392] ; (801f9f0 ) 801f866: 4613 mov r3, r2 801f868: 005b lsls r3, r3, #1 801f86a: 4413 add r3, r2 801f86c: 00db lsls r3, r3, #3 801f86e: 440b add r3, r1 801f870: 3314 adds r3, #20 801f872: 781b ldrb r3, [r3, #0] 801f874: 2b01 cmp r3, #1 801f876: d806 bhi.n 801f886 801f878: 4b5a ldr r3, [pc, #360] ; (801f9e4 ) 801f87a: f240 32cd movw r2, #973 ; 0x3cd 801f87e: 495d ldr r1, [pc, #372] ; (801f9f4 ) 801f880: 485a ldr r0, [pc, #360] ; (801f9ec ) 801f882: f002 f881 bl 8021988 ((arp_table[i].state == ETHARP_STATE_PENDING) || (arp_table[i].state >= ETHARP_STATE_STABLE))); /* do we have a new entry? or an implicit query request? */ if (is_new_entry || (q == NULL)) { 801f886: 6a3b ldr r3, [r7, #32] 801f888: 2b00 cmp r3, #0 801f88a: d102 bne.n 801f892 801f88c: 687b ldr r3, [r7, #4] 801f88e: 2b00 cmp r3, #0 801f890: d10c bne.n 801f8ac /* try to resolve it; send out ARP request */ result = etharp_request(netif, ipaddr); 801f892: 68b9 ldr r1, [r7, #8] 801f894: 68f8 ldr r0, [r7, #12] 801f896: f000 f963 bl 801fb60 801f89a: 4603 mov r3, r0 801f89c: f887 3027 strb.w r3, [r7, #39] ; 0x27 /* ARP request couldn't be sent */ /* We don't re-send arp request in etharp_tmr, but we still queue packets, since this failure could be temporary, and the next packet calling etharp_query again could lead to sending the queued packets. */ } if (q == NULL) { 801f8a0: 687b ldr r3, [r7, #4] 801f8a2: 2b00 cmp r3, #0 801f8a4: d102 bne.n 801f8ac return result; 801f8a6: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 801f8aa: e096 b.n 801f9da } } /* packet given? */ LWIP_ASSERT("q != NULL", q != NULL); 801f8ac: 687b ldr r3, [r7, #4] 801f8ae: 2b00 cmp r3, #0 801f8b0: d106 bne.n 801f8c0 801f8b2: 4b4c ldr r3, [pc, #304] ; (801f9e4 ) 801f8b4: f240 32e1 movw r2, #993 ; 0x3e1 801f8b8: 494f ldr r1, [pc, #316] ; (801f9f8 ) 801f8ba: 484c ldr r0, [pc, #304] ; (801f9ec ) 801f8bc: f002 f864 bl 8021988 /* stable entry? */ if (arp_table[i].state >= ETHARP_STATE_STABLE) { 801f8c0: 7c7a ldrb r2, [r7, #17] 801f8c2: 494b ldr r1, [pc, #300] ; (801f9f0 ) 801f8c4: 4613 mov r3, r2 801f8c6: 005b lsls r3, r3, #1 801f8c8: 4413 add r3, r2 801f8ca: 00db lsls r3, r3, #3 801f8cc: 440b add r3, r1 801f8ce: 3314 adds r3, #20 801f8d0: 781b ldrb r3, [r3, #0] 801f8d2: 2b01 cmp r3, #1 801f8d4: d917 bls.n 801f906 /* we have a valid IP->Ethernet address mapping */ ETHARP_SET_ADDRHINT(netif, i); 801f8d6: 4a49 ldr r2, [pc, #292] ; (801f9fc ) 801f8d8: 7c7b ldrb r3, [r7, #17] 801f8da: 7013 strb r3, [r2, #0] /* send the packet */ result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP); 801f8dc: 7c7a ldrb r2, [r7, #17] 801f8de: 4613 mov r3, r2 801f8e0: 005b lsls r3, r3, #1 801f8e2: 4413 add r3, r2 801f8e4: 00db lsls r3, r3, #3 801f8e6: 3308 adds r3, #8 801f8e8: 4a41 ldr r2, [pc, #260] ; (801f9f0 ) 801f8ea: 4413 add r3, r2 801f8ec: 3304 adds r3, #4 801f8ee: f44f 6200 mov.w r2, #2048 ; 0x800 801f8f2: 9200 str r2, [sp, #0] 801f8f4: 697a ldr r2, [r7, #20] 801f8f6: 6879 ldr r1, [r7, #4] 801f8f8: 68f8 ldr r0, [r7, #12] 801f8fa: f001 fc9f bl 802123c 801f8fe: 4603 mov r3, r0 801f900: f887 3027 strb.w r3, [r7, #39] ; 0x27 801f904: e067 b.n 801f9d6 /* pending entry? (either just created or already pending */ } else if (arp_table[i].state == ETHARP_STATE_PENDING) { 801f906: 7c7a ldrb r2, [r7, #17] 801f908: 4939 ldr r1, [pc, #228] ; (801f9f0 ) 801f90a: 4613 mov r3, r2 801f90c: 005b lsls r3, r3, #1 801f90e: 4413 add r3, r2 801f910: 00db lsls r3, r3, #3 801f912: 440b add r3, r1 801f914: 3314 adds r3, #20 801f916: 781b ldrb r3, [r3, #0] 801f918: 2b01 cmp r3, #1 801f91a: d15c bne.n 801f9d6 /* entry is still pending, queue the given packet 'q' */ struct pbuf *p; int copy_needed = 0; 801f91c: 2300 movs r3, #0 801f91e: 61bb str r3, [r7, #24] /* IF q includes a pbuf that must be copied, copy the whole chain into a * new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */ p = q; 801f920: 687b ldr r3, [r7, #4] 801f922: 61fb str r3, [r7, #28] while (p) { 801f924: e01c b.n 801f960 LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0)); 801f926: 69fb ldr r3, [r7, #28] 801f928: 895a ldrh r2, [r3, #10] 801f92a: 69fb ldr r3, [r7, #28] 801f92c: 891b ldrh r3, [r3, #8] 801f92e: 429a cmp r2, r3 801f930: d10a bne.n 801f948 801f932: 69fb ldr r3, [r7, #28] 801f934: 681b ldr r3, [r3, #0] 801f936: 2b00 cmp r3, #0 801f938: d006 beq.n 801f948 801f93a: 4b2a ldr r3, [pc, #168] ; (801f9e4 ) 801f93c: f240 32f1 movw r2, #1009 ; 0x3f1 801f940: 492f ldr r1, [pc, #188] ; (801fa00 ) 801f942: 482a ldr r0, [pc, #168] ; (801f9ec ) 801f944: f002 f820 bl 8021988 if (PBUF_NEEDS_COPY(p)) { 801f948: 69fb ldr r3, [r7, #28] 801f94a: 7b1b ldrb r3, [r3, #12] 801f94c: f003 0340 and.w r3, r3, #64 ; 0x40 801f950: 2b00 cmp r3, #0 801f952: d002 beq.n 801f95a copy_needed = 1; 801f954: 2301 movs r3, #1 801f956: 61bb str r3, [r7, #24] break; 801f958: e005 b.n 801f966 } p = p->next; 801f95a: 69fb ldr r3, [r7, #28] 801f95c: 681b ldr r3, [r3, #0] 801f95e: 61fb str r3, [r7, #28] while (p) { 801f960: 69fb ldr r3, [r7, #28] 801f962: 2b00 cmp r3, #0 801f964: d1df bne.n 801f926 } if (copy_needed) { 801f966: 69bb ldr r3, [r7, #24] 801f968: 2b00 cmp r3, #0 801f96a: d007 beq.n 801f97c /* copy the whole packet into new pbufs */ p = pbuf_clone(PBUF_LINK, PBUF_RAM, q); 801f96c: 687a ldr r2, [r7, #4] 801f96e: f44f 7120 mov.w r1, #640 ; 0x280 801f972: 200e movs r0, #14 801f974: f7f8 fb28 bl 8017fc8 801f978: 61f8 str r0, [r7, #28] 801f97a: e004 b.n 801f986 } else { /* referencing the old pbuf is enough */ p = q; 801f97c: 687b ldr r3, [r7, #4] 801f97e: 61fb str r3, [r7, #28] pbuf_ref(p); 801f980: 69f8 ldr r0, [r7, #28] 801f982: f7f8 f95f bl 8017c44 } /* packet could be taken over? */ if (p != NULL) { 801f986: 69fb ldr r3, [r7, #28] 801f988: 2b00 cmp r3, #0 801f98a: d021 beq.n 801f9d0 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); result = ERR_MEM; } #else /* ARP_QUEUEING */ /* always queue one packet per ARP request only, freeing a previously queued packet */ if (arp_table[i].q != NULL) { 801f98c: 7c7a ldrb r2, [r7, #17] 801f98e: 4918 ldr r1, [pc, #96] ; (801f9f0 ) 801f990: 4613 mov r3, r2 801f992: 005b lsls r3, r3, #1 801f994: 4413 add r3, r2 801f996: 00db lsls r3, r3, #3 801f998: 440b add r3, r1 801f99a: 681b ldr r3, [r3, #0] 801f99c: 2b00 cmp r3, #0 801f99e: d00a beq.n 801f9b6 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i)); pbuf_free(arp_table[i].q); 801f9a0: 7c7a ldrb r2, [r7, #17] 801f9a2: 4913 ldr r1, [pc, #76] ; (801f9f0 ) 801f9a4: 4613 mov r3, r2 801f9a6: 005b lsls r3, r3, #1 801f9a8: 4413 add r3, r2 801f9aa: 00db lsls r3, r3, #3 801f9ac: 440b add r3, r1 801f9ae: 681b ldr r3, [r3, #0] 801f9b0: 4618 mov r0, r3 801f9b2: f7f8 f8a1 bl 8017af8 } arp_table[i].q = p; 801f9b6: 7c7a ldrb r2, [r7, #17] 801f9b8: 490d ldr r1, [pc, #52] ; (801f9f0 ) 801f9ba: 4613 mov r3, r2 801f9bc: 005b lsls r3, r3, #1 801f9be: 4413 add r3, r2 801f9c0: 00db lsls r3, r3, #3 801f9c2: 440b add r3, r1 801f9c4: 69fa ldr r2, [r7, #28] 801f9c6: 601a str r2, [r3, #0] result = ERR_OK; 801f9c8: 2300 movs r3, #0 801f9ca: f887 3027 strb.w r3, [r7, #39] ; 0x27 801f9ce: e002 b.n 801f9d6 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i)); #endif /* ARP_QUEUEING */ } else { ETHARP_STATS_INC(etharp.memerr); LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); result = ERR_MEM; 801f9d0: 23ff movs r3, #255 ; 0xff 801f9d2: f887 3027 strb.w r3, [r7, #39] ; 0x27 } } return result; 801f9d6: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 } 801f9da: 4618 mov r0, r3 801f9dc: 3728 adds r7, #40 ; 0x28 801f9de: 46bd mov sp, r7 801f9e0: bd80 pop {r7, pc} 801f9e2: bf00 nop 801f9e4: 0802647c .word 0x0802647c 801f9e8: 08026628 .word 0x08026628 801f9ec: 080264f4 .word 0x080264f4 801f9f0: 2401a4e4 .word 0x2401a4e4 801f9f4: 08026638 .word 0x08026638 801f9f8: 0802661c .word 0x0802661c 801f9fc: 2401a5d4 .word 0x2401a5d4 801fa00: 08026660 .word 0x08026660 0801fa04 : etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, const struct eth_addr *ethdst_addr, const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr, const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr, const u16_t opcode) { 801fa04: b580 push {r7, lr} 801fa06: b08a sub sp, #40 ; 0x28 801fa08: af02 add r7, sp, #8 801fa0a: 60f8 str r0, [r7, #12] 801fa0c: 60b9 str r1, [r7, #8] 801fa0e: 607a str r2, [r7, #4] 801fa10: 603b str r3, [r7, #0] struct pbuf *p; err_t result = ERR_OK; 801fa12: 2300 movs r3, #0 801fa14: 77fb strb r3, [r7, #31] struct etharp_hdr *hdr; LWIP_ASSERT("netif != NULL", netif != NULL); 801fa16: 68fb ldr r3, [r7, #12] 801fa18: 2b00 cmp r3, #0 801fa1a: d106 bne.n 801fa2a 801fa1c: 4b3a ldr r3, [pc, #232] ; (801fb08 ) 801fa1e: f240 4257 movw r2, #1111 ; 0x457 801fa22: 493a ldr r1, [pc, #232] ; (801fb0c ) 801fa24: 483a ldr r0, [pc, #232] ; (801fb10 ) 801fa26: f001 ffaf bl 8021988 /* allocate a pbuf for the outgoing ARP request packet */ p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM); 801fa2a: f44f 7220 mov.w r2, #640 ; 0x280 801fa2e: 211c movs r1, #28 801fa30: 200e movs r0, #14 801fa32: f7f7 fd79 bl 8017528 801fa36: 61b8 str r0, [r7, #24] /* could allocate a pbuf for an ARP request? */ if (p == NULL) { 801fa38: 69bb ldr r3, [r7, #24] 801fa3a: 2b00 cmp r3, #0 801fa3c: d102 bne.n 801fa44 LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("etharp_raw: could not allocate pbuf for ARP request.\n")); ETHARP_STATS_INC(etharp.memerr); return ERR_MEM; 801fa3e: f04f 33ff mov.w r3, #4294967295 801fa42: e05d b.n 801fb00 } LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr", 801fa44: 69bb ldr r3, [r7, #24] 801fa46: 895b ldrh r3, [r3, #10] 801fa48: 2b1b cmp r3, #27 801fa4a: d806 bhi.n 801fa5a 801fa4c: 4b2e ldr r3, [pc, #184] ; (801fb08 ) 801fa4e: f240 4262 movw r2, #1122 ; 0x462 801fa52: 4930 ldr r1, [pc, #192] ; (801fb14 ) 801fa54: 482e ldr r0, [pc, #184] ; (801fb10 ) 801fa56: f001 ff97 bl 8021988 (p->len >= SIZEOF_ETHARP_HDR)); hdr = (struct etharp_hdr *)p->payload; 801fa5a: 69bb ldr r3, [r7, #24] 801fa5c: 685b ldr r3, [r3, #4] 801fa5e: 617b str r3, [r7, #20] LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n")); hdr->opcode = lwip_htons(opcode); 801fa60: 8ebb ldrh r3, [r7, #52] ; 0x34 801fa62: 4618 mov r0, r3 801fa64: f7f6 fa6c bl 8015f40 801fa68: 4603 mov r3, r0 801fa6a: 461a mov r2, r3 801fa6c: 697b ldr r3, [r7, #20] 801fa6e: 80da strh r2, [r3, #6] LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!", 801fa70: 68fb ldr r3, [r7, #12] 801fa72: f893 302c ldrb.w r3, [r3, #44] ; 0x2c 801fa76: 2b06 cmp r3, #6 801fa78: d006 beq.n 801fa88 801fa7a: 4b23 ldr r3, [pc, #140] ; (801fb08 ) 801fa7c: f240 4269 movw r2, #1129 ; 0x469 801fa80: 4925 ldr r1, [pc, #148] ; (801fb18 ) 801fa82: 4823 ldr r0, [pc, #140] ; (801fb10 ) 801fa84: f001 ff80 bl 8021988 (netif->hwaddr_len == ETH_HWADDR_LEN)); /* Write the ARP MAC-Addresses */ SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN); 801fa88: 697b ldr r3, [r7, #20] 801fa8a: 3308 adds r3, #8 801fa8c: 2206 movs r2, #6 801fa8e: 6839 ldr r1, [r7, #0] 801fa90: 4618 mov r0, r3 801fa92: f002 f9a8 bl 8021de6 SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN); 801fa96: 697b ldr r3, [r7, #20] 801fa98: 3312 adds r3, #18 801fa9a: 2206 movs r2, #6 801fa9c: 6af9 ldr r1, [r7, #44] ; 0x2c 801fa9e: 4618 mov r0, r3 801faa0: f002 f9a1 bl 8021de6 /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without * structure packing. */ IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr); 801faa4: 697b ldr r3, [r7, #20] 801faa6: 330e adds r3, #14 801faa8: 6aba ldr r2, [r7, #40] ; 0x28 801faaa: 6812 ldr r2, [r2, #0] 801faac: 601a str r2, [r3, #0] IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr); 801faae: 697b ldr r3, [r7, #20] 801fab0: 3318 adds r3, #24 801fab2: 6b3a ldr r2, [r7, #48] ; 0x30 801fab4: 6812 ldr r2, [r2, #0] 801fab6: 601a str r2, [r3, #0] hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET); 801fab8: 697b ldr r3, [r7, #20] 801faba: 2200 movs r2, #0 801fabc: 701a strb r2, [r3, #0] 801fabe: 2200 movs r2, #0 801fac0: f042 0201 orr.w r2, r2, #1 801fac4: 705a strb r2, [r3, #1] hdr->proto = PP_HTONS(ETHTYPE_IP); 801fac6: 697b ldr r3, [r7, #20] 801fac8: 2200 movs r2, #0 801faca: f042 0208 orr.w r2, r2, #8 801face: 709a strb r2, [r3, #2] 801fad0: 2200 movs r2, #0 801fad2: 70da strb r2, [r3, #3] /* set hwlen and protolen */ hdr->hwlen = ETH_HWADDR_LEN; 801fad4: 697b ldr r3, [r7, #20] 801fad6: 2206 movs r2, #6 801fad8: 711a strb r2, [r3, #4] hdr->protolen = sizeof(ip4_addr_t); 801fada: 697b ldr r3, [r7, #20] 801fadc: 2204 movs r2, #4 801fade: 715a strb r2, [r3, #5] if (ip4_addr_islinklocal(ipsrc_addr)) { ethernet_output(netif, p, ethsrc_addr, ðbroadcast, ETHTYPE_ARP); } else #endif /* LWIP_AUTOIP */ { ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP); 801fae0: f640 0306 movw r3, #2054 ; 0x806 801fae4: 9300 str r3, [sp, #0] 801fae6: 687b ldr r3, [r7, #4] 801fae8: 68ba ldr r2, [r7, #8] 801faea: 69b9 ldr r1, [r7, #24] 801faec: 68f8 ldr r0, [r7, #12] 801faee: f001 fba5 bl 802123c } ETHARP_STATS_INC(etharp.xmit); /* free ARP query packet */ pbuf_free(p); 801faf2: 69b8 ldr r0, [r7, #24] 801faf4: f7f8 f800 bl 8017af8 p = NULL; 801faf8: 2300 movs r3, #0 801fafa: 61bb str r3, [r7, #24] /* could not allocate pbuf for ARP request */ return result; 801fafc: f997 301f ldrsb.w r3, [r7, #31] } 801fb00: 4618 mov r0, r3 801fb02: 3720 adds r7, #32 801fb04: 46bd mov sp, r7 801fb06: bd80 pop {r7, pc} 801fb08: 0802647c .word 0x0802647c 801fb0c: 080265cc .word 0x080265cc 801fb10: 080264f4 .word 0x080264f4 801fb14: 0802667c .word 0x0802667c 801fb18: 080266b0 .word 0x080266b0 0801fb1c : * ERR_MEM if the ARP packet couldn't be allocated * any other err_t on failure */ static err_t etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr) { 801fb1c: b580 push {r7, lr} 801fb1e: b088 sub sp, #32 801fb20: af04 add r7, sp, #16 801fb22: 60f8 str r0, [r7, #12] 801fb24: 60b9 str r1, [r7, #8] 801fb26: 607a str r2, [r7, #4] return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr, 801fb28: 68fb ldr r3, [r7, #12] 801fb2a: f103 0126 add.w r1, r3, #38 ; 0x26 (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), ðzero, 801fb2e: 68fb ldr r3, [r7, #12] 801fb30: f103 0026 add.w r0, r3, #38 ; 0x26 801fb34: 68fb ldr r3, [r7, #12] 801fb36: 3304 adds r3, #4 return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr, 801fb38: 2201 movs r2, #1 801fb3a: 9203 str r2, [sp, #12] 801fb3c: 68ba ldr r2, [r7, #8] 801fb3e: 9202 str r2, [sp, #8] 801fb40: 4a06 ldr r2, [pc, #24] ; (801fb5c ) 801fb42: 9201 str r2, [sp, #4] 801fb44: 9300 str r3, [sp, #0] 801fb46: 4603 mov r3, r0 801fb48: 687a ldr r2, [r7, #4] 801fb4a: 68f8 ldr r0, [r7, #12] 801fb4c: f7ff ff5a bl 801fa04 801fb50: 4603 mov r3, r0 ipaddr, ARP_REQUEST); } 801fb52: 4618 mov r0, r3 801fb54: 3710 adds r7, #16 801fb56: 46bd mov sp, r7 801fb58: bd80 pop {r7, pc} 801fb5a: bf00 nop 801fb5c: 08026cf8 .word 0x08026cf8 0801fb60 : * ERR_MEM if the ARP packet couldn't be allocated * any other err_t on failure */ err_t etharp_request(struct netif *netif, const ip4_addr_t *ipaddr) { 801fb60: b580 push {r7, lr} 801fb62: b082 sub sp, #8 801fb64: af00 add r7, sp, #0 801fb66: 6078 str r0, [r7, #4] 801fb68: 6039 str r1, [r7, #0] LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n")); return etharp_request_dst(netif, ipaddr, ðbroadcast); 801fb6a: 4a05 ldr r2, [pc, #20] ; (801fb80 ) 801fb6c: 6839 ldr r1, [r7, #0] 801fb6e: 6878 ldr r0, [r7, #4] 801fb70: f7ff ffd4 bl 801fb1c 801fb74: 4603 mov r3, r0 } 801fb76: 4618 mov r0, r3 801fb78: 3708 adds r7, #8 801fb7a: 46bd mov sp, r7 801fb7c: bd80 pop {r7, pc} 801fb7e: bf00 nop 801fb80: 08026cf0 .word 0x08026cf0 0801fb84 : * @param p the icmp echo request packet, p->payload pointing to the icmp header * @param inp the netif on which this packet was received */ void icmp_input(struct pbuf *p, struct netif *inp) { 801fb84: b580 push {r7, lr} 801fb86: b08e sub sp, #56 ; 0x38 801fb88: af04 add r7, sp, #16 801fb8a: 6078 str r0, [r7, #4] 801fb8c: 6039 str r1, [r7, #0] const ip4_addr_t *src; ICMP_STATS_INC(icmp.recv); MIB2_STATS_INC(mib2.icmpinmsgs); iphdr_in = ip4_current_header(); 801fb8e: 4b89 ldr r3, [pc, #548] ; (801fdb4 ) 801fb90: 689b ldr r3, [r3, #8] 801fb92: 627b str r3, [r7, #36] ; 0x24 hlen = IPH_HL_BYTES(iphdr_in); 801fb94: 6a7b ldr r3, [r7, #36] ; 0x24 801fb96: 781b ldrb r3, [r3, #0] 801fb98: f003 030f and.w r3, r3, #15 801fb9c: b2db uxtb r3, r3 801fb9e: 009b lsls r3, r3, #2 801fba0: b2db uxtb r3, r3 801fba2: 847b strh r3, [r7, #34] ; 0x22 if (hlen < IP_HLEN) { 801fba4: 8c7b ldrh r3, [r7, #34] ; 0x22 801fba6: 2b13 cmp r3, #19 801fba8: f240 80ed bls.w 801fd86 LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen)); goto lenerr; } if (p->len < sizeof(u16_t) * 2) { 801fbac: 687b ldr r3, [r7, #4] 801fbae: 895b ldrh r3, [r3, #10] 801fbb0: 2b03 cmp r3, #3 801fbb2: f240 80ea bls.w 801fd8a LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); goto lenerr; } type = *((u8_t *)p->payload); 801fbb6: 687b ldr r3, [r7, #4] 801fbb8: 685b ldr r3, [r3, #4] 801fbba: 781b ldrb r3, [r3, #0] 801fbbc: f887 3021 strb.w r3, [r7, #33] ; 0x21 #ifdef LWIP_DEBUG code = *(((u8_t *)p->payload) + 1); 801fbc0: 687b ldr r3, [r7, #4] 801fbc2: 685b ldr r3, [r3, #4] 801fbc4: 785b ldrb r3, [r3, #1] 801fbc6: f887 3020 strb.w r3, [r7, #32] /* if debug is enabled but debug statement below is somehow disabled: */ LWIP_UNUSED_ARG(code); #endif /* LWIP_DEBUG */ switch (type) { 801fbca: f897 3021 ldrb.w r3, [r7, #33] ; 0x21 801fbce: 2b00 cmp r3, #0 801fbd0: f000 80d2 beq.w 801fd78 801fbd4: 2b08 cmp r3, #8 801fbd6: f040 80d2 bne.w 801fd7e (as obviously, an echo request has been sent, too). */ MIB2_STATS_INC(mib2.icmpinechoreps); break; case ICMP_ECHO: MIB2_STATS_INC(mib2.icmpinechos); src = ip4_current_dest_addr(); 801fbda: 4b77 ldr r3, [pc, #476] ; (801fdb8 ) 801fbdc: 61fb str r3, [r7, #28] /* multicast destination address? */ if (ip4_addr_ismulticast(ip4_current_dest_addr())) { 801fbde: 4b75 ldr r3, [pc, #468] ; (801fdb4 ) 801fbe0: 695b ldr r3, [r3, #20] 801fbe2: f003 03f0 and.w r3, r3, #240 ; 0xf0 801fbe6: 2be0 cmp r3, #224 ; 0xe0 801fbe8: f000 80d6 beq.w 801fd98 LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n")); goto icmperr; #endif /* LWIP_MULTICAST_PING */ } /* broadcast destination address? */ if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) { 801fbec: 4b71 ldr r3, [pc, #452] ; (801fdb4 ) 801fbee: 695b ldr r3, [r3, #20] 801fbf0: 4a70 ldr r2, [pc, #448] ; (801fdb4 ) 801fbf2: 6812 ldr r2, [r2, #0] 801fbf4: 4611 mov r1, r2 801fbf6: 4618 mov r0, r3 801fbf8: f000 fc12 bl 8020420 801fbfc: 4603 mov r3, r0 801fbfe: 2b00 cmp r3, #0 801fc00: f040 80cc bne.w 801fd9c LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n")); goto icmperr; #endif /* LWIP_BROADCAST_PING */ } LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); if (p->tot_len < sizeof(struct icmp_echo_hdr)) { 801fc04: 687b ldr r3, [r7, #4] 801fc06: 891b ldrh r3, [r3, #8] 801fc08: 2b07 cmp r3, #7 801fc0a: f240 80c0 bls.w 801fd8e LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); goto lenerr; } #if CHECKSUM_CHECK_ICMP IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_ICMP) { if (inet_chksum_pbuf(p) != 0) { 801fc0e: 6878 ldr r0, [r7, #4] 801fc10: f7f6 fa33 bl 801607a 801fc14: 4603 mov r3, r0 801fc16: 2b00 cmp r3, #0 801fc18: d003 beq.n 801fc22 LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n")); pbuf_free(p); 801fc1a: 6878 ldr r0, [r7, #4] 801fc1c: f7f7 ff6c bl 8017af8 ICMP_STATS_INC(icmp.chkerr); MIB2_STATS_INC(mib2.icmpinerrors); return; 801fc20: e0c5 b.n 801fdae } } #endif #if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) { 801fc22: 8c7b ldrh r3, [r7, #34] ; 0x22 801fc24: 330e adds r3, #14 801fc26: 4619 mov r1, r3 801fc28: 6878 ldr r0, [r7, #4] 801fc2a: f7f7 fecf bl 80179cc 801fc2e: 4603 mov r3, r0 801fc30: 2b00 cmp r3, #0 801fc32: d04b beq.n 801fccc /* p is not big enough to contain link headers * allocate a new one and copy p into it */ struct pbuf *r; u16_t alloc_len = (u16_t)(p->tot_len + hlen); 801fc34: 687b ldr r3, [r7, #4] 801fc36: 891a ldrh r2, [r3, #8] 801fc38: 8c7b ldrh r3, [r7, #34] ; 0x22 801fc3a: 4413 add r3, r2 801fc3c: 837b strh r3, [r7, #26] if (alloc_len < p->tot_len) { 801fc3e: 687b ldr r3, [r7, #4] 801fc40: 891b ldrh r3, [r3, #8] 801fc42: 8b7a ldrh r2, [r7, #26] 801fc44: 429a cmp r2, r3 801fc46: f0c0 80ab bcc.w 801fda0 LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n")); goto icmperr; } /* allocate new packet buffer with space for link headers */ r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM); 801fc4a: 8b7b ldrh r3, [r7, #26] 801fc4c: f44f 7220 mov.w r2, #640 ; 0x280 801fc50: 4619 mov r1, r3 801fc52: 200e movs r0, #14 801fc54: f7f7 fc68 bl 8017528 801fc58: 6178 str r0, [r7, #20] if (r == NULL) { 801fc5a: 697b ldr r3, [r7, #20] 801fc5c: 2b00 cmp r3, #0 801fc5e: f000 80a1 beq.w 801fda4 LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n")); goto icmperr; } if (r->len < hlen + sizeof(struct icmp_echo_hdr)) { 801fc62: 697b ldr r3, [r7, #20] 801fc64: 895b ldrh r3, [r3, #10] 801fc66: 461a mov r2, r3 801fc68: 8c7b ldrh r3, [r7, #34] ; 0x22 801fc6a: 3308 adds r3, #8 801fc6c: 429a cmp r2, r3 801fc6e: d203 bcs.n 801fc78 LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header")); pbuf_free(r); 801fc70: 6978 ldr r0, [r7, #20] 801fc72: f7f7 ff41 bl 8017af8 goto icmperr; 801fc76: e096 b.n 801fda6 } /* copy the ip header */ MEMCPY(r->payload, iphdr_in, hlen); 801fc78: 697b ldr r3, [r7, #20] 801fc7a: 685b ldr r3, [r3, #4] 801fc7c: 8c7a ldrh r2, [r7, #34] ; 0x22 801fc7e: 6a79 ldr r1, [r7, #36] ; 0x24 801fc80: 4618 mov r0, r3 801fc82: f002 f8b0 bl 8021de6 /* switch r->payload back to icmp header (cannot fail) */ if (pbuf_remove_header(r, hlen)) { 801fc86: 8c7b ldrh r3, [r7, #34] ; 0x22 801fc88: 4619 mov r1, r3 801fc8a: 6978 ldr r0, [r7, #20] 801fc8c: f7f7 feae bl 80179ec 801fc90: 4603 mov r3, r0 801fc92: 2b00 cmp r3, #0 801fc94: d009 beq.n 801fcaa LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0); 801fc96: 4b49 ldr r3, [pc, #292] ; (801fdbc ) 801fc98: 22b6 movs r2, #182 ; 0xb6 801fc9a: 4949 ldr r1, [pc, #292] ; (801fdc0 ) 801fc9c: 4849 ldr r0, [pc, #292] ; (801fdc4 ) 801fc9e: f001 fe73 bl 8021988 pbuf_free(r); 801fca2: 6978 ldr r0, [r7, #20] 801fca4: f7f7 ff28 bl 8017af8 goto icmperr; 801fca8: e07d b.n 801fda6 } /* copy the rest of the packet without ip header */ if (pbuf_copy(r, p) != ERR_OK) { 801fcaa: 6879 ldr r1, [r7, #4] 801fcac: 6978 ldr r0, [r7, #20] 801fcae: f7f8 f847 bl 8017d40 801fcb2: 4603 mov r3, r0 801fcb4: 2b00 cmp r3, #0 801fcb6: d003 beq.n 801fcc0 LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed")); pbuf_free(r); 801fcb8: 6978 ldr r0, [r7, #20] 801fcba: f7f7 ff1d bl 8017af8 goto icmperr; 801fcbe: e072 b.n 801fda6 } /* free the original p */ pbuf_free(p); 801fcc0: 6878 ldr r0, [r7, #4] 801fcc2: f7f7 ff19 bl 8017af8 /* we now have an identical copy of p that has room for link headers */ p = r; 801fcc6: 697b ldr r3, [r7, #20] 801fcc8: 607b str r3, [r7, #4] 801fcca: e00f b.n 801fcec } else { /* restore p->payload to point to icmp header (cannot fail) */ if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) { 801fccc: 8c7b ldrh r3, [r7, #34] ; 0x22 801fcce: 330e adds r3, #14 801fcd0: 4619 mov r1, r3 801fcd2: 6878 ldr r0, [r7, #4] 801fcd4: f7f7 fe8a bl 80179ec 801fcd8: 4603 mov r3, r0 801fcda: 2b00 cmp r3, #0 801fcdc: d006 beq.n 801fcec LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0); 801fcde: 4b37 ldr r3, [pc, #220] ; (801fdbc ) 801fce0: 22c7 movs r2, #199 ; 0xc7 801fce2: 4939 ldr r1, [pc, #228] ; (801fdc8 ) 801fce4: 4837 ldr r0, [pc, #220] ; (801fdc4 ) 801fce6: f001 fe4f bl 8021988 goto icmperr; 801fcea: e05c b.n 801fda6 } #endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ /* At this point, all checks are OK. */ /* We generate an answer by switching the dest and src ip addresses, * setting the icmp type to ECHO_RESPONSE and updating the checksum. */ iecho = (struct icmp_echo_hdr *)p->payload; 801fcec: 687b ldr r3, [r7, #4] 801fcee: 685b ldr r3, [r3, #4] 801fcf0: 613b str r3, [r7, #16] if (pbuf_add_header(p, hlen)) { 801fcf2: 8c7b ldrh r3, [r7, #34] ; 0x22 801fcf4: 4619 mov r1, r3 801fcf6: 6878 ldr r0, [r7, #4] 801fcf8: f7f7 fe68 bl 80179cc 801fcfc: 4603 mov r3, r0 801fcfe: 2b00 cmp r3, #0 801fd00: d13c bne.n 801fd7c LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet")); } else { err_t ret; struct ip_hdr *iphdr = (struct ip_hdr *)p->payload; 801fd02: 687b ldr r3, [r7, #4] 801fd04: 685b ldr r3, [r3, #4] 801fd06: 60fb str r3, [r7, #12] ip4_addr_copy(iphdr->src, *src); 801fd08: 69fb ldr r3, [r7, #28] 801fd0a: 681a ldr r2, [r3, #0] 801fd0c: 68fb ldr r3, [r7, #12] 801fd0e: 60da str r2, [r3, #12] ip4_addr_copy(iphdr->dest, *ip4_current_src_addr()); 801fd10: 4b28 ldr r3, [pc, #160] ; (801fdb4 ) 801fd12: 691a ldr r2, [r3, #16] 801fd14: 68fb ldr r3, [r7, #12] 801fd16: 611a str r2, [r3, #16] ICMPH_TYPE_SET(iecho, ICMP_ER); 801fd18: 693b ldr r3, [r7, #16] 801fd1a: 2200 movs r2, #0 801fd1c: 701a strb r2, [r3, #0] #if CHECKSUM_GEN_ICMP IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_ICMP) { /* adjust the checksum */ if (iecho->chksum > PP_HTONS(0xffffU - (ICMP_ECHO << 8))) { 801fd1e: 693b ldr r3, [r7, #16] 801fd20: 885b ldrh r3, [r3, #2] 801fd22: b29b uxth r3, r3 801fd24: f64f 72f7 movw r2, #65527 ; 0xfff7 801fd28: 4293 cmp r3, r2 801fd2a: d907 bls.n 801fd3c iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS((u16_t)(ICMP_ECHO << 8)) + 1); 801fd2c: 693b ldr r3, [r7, #16] 801fd2e: 885b ldrh r3, [r3, #2] 801fd30: b29b uxth r3, r3 801fd32: 3309 adds r3, #9 801fd34: b29a uxth r2, r3 801fd36: 693b ldr r3, [r7, #16] 801fd38: 805a strh r2, [r3, #2] 801fd3a: e006 b.n 801fd4a } else { iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS(ICMP_ECHO << 8)); 801fd3c: 693b ldr r3, [r7, #16] 801fd3e: 885b ldrh r3, [r3, #2] 801fd40: b29b uxth r3, r3 801fd42: 3308 adds r3, #8 801fd44: b29a uxth r2, r3 801fd46: 693b ldr r3, [r7, #16] 801fd48: 805a strh r2, [r3, #2] #else /* CHECKSUM_GEN_ICMP */ iecho->chksum = 0; #endif /* CHECKSUM_GEN_ICMP */ /* Set the correct TTL and recalculate the header checksum. */ IPH_TTL_SET(iphdr, ICMP_TTL); 801fd4a: 68fb ldr r3, [r7, #12] 801fd4c: 22ff movs r2, #255 ; 0xff 801fd4e: 721a strb r2, [r3, #8] IPH_CHKSUM_SET(iphdr, 0); 801fd50: 68fb ldr r3, [r7, #12] 801fd52: 2200 movs r2, #0 801fd54: 729a strb r2, [r3, #10] 801fd56: 2200 movs r2, #0 801fd58: 72da strb r2, [r3, #11] MIB2_STATS_INC(mib2.icmpoutmsgs); /* increase number of echo replies attempted to send */ MIB2_STATS_INC(mib2.icmpoutechoreps); /* send an ICMP packet */ ret = ip4_output_if(p, src, LWIP_IP_HDRINCL, 801fd5a: 683b ldr r3, [r7, #0] 801fd5c: 9302 str r3, [sp, #8] 801fd5e: 2301 movs r3, #1 801fd60: 9301 str r3, [sp, #4] 801fd62: 2300 movs r3, #0 801fd64: 9300 str r3, [sp, #0] 801fd66: 23ff movs r3, #255 ; 0xff 801fd68: 2200 movs r2, #0 801fd6a: 69f9 ldr r1, [r7, #28] 801fd6c: 6878 ldr r0, [r7, #4] 801fd6e: f000 fa7f bl 8020270 801fd72: 4603 mov r3, r0 801fd74: 72fb strb r3, [r7, #11] ICMP_TTL, 0, IP_PROTO_ICMP, inp); if (ret != ERR_OK) { LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret))); } } break; 801fd76: e001 b.n 801fd7c break; 801fd78: bf00 nop 801fd7a: e000 b.n 801fd7e break; 801fd7c: bf00 nop LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", (s16_t)type, (s16_t)code)); ICMP_STATS_INC(icmp.proterr); ICMP_STATS_INC(icmp.drop); } pbuf_free(p); 801fd7e: 6878 ldr r0, [r7, #4] 801fd80: f7f7 feba bl 8017af8 return; 801fd84: e013 b.n 801fdae goto lenerr; 801fd86: bf00 nop 801fd88: e002 b.n 801fd90 goto lenerr; 801fd8a: bf00 nop 801fd8c: e000 b.n 801fd90 goto lenerr; 801fd8e: bf00 nop lenerr: pbuf_free(p); 801fd90: 6878 ldr r0, [r7, #4] 801fd92: f7f7 feb1 bl 8017af8 ICMP_STATS_INC(icmp.lenerr); MIB2_STATS_INC(mib2.icmpinerrors); return; 801fd96: e00a b.n 801fdae goto icmperr; 801fd98: bf00 nop 801fd9a: e004 b.n 801fda6 goto icmperr; 801fd9c: bf00 nop 801fd9e: e002 b.n 801fda6 goto icmperr; 801fda0: bf00 nop 801fda2: e000 b.n 801fda6 goto icmperr; 801fda4: bf00 nop #if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING icmperr: pbuf_free(p); 801fda6: 6878 ldr r0, [r7, #4] 801fda8: f7f7 fea6 bl 8017af8 ICMP_STATS_INC(icmp.err); MIB2_STATS_INC(mib2.icmpinerrors); return; 801fdac: bf00 nop #endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */ } 801fdae: 3728 adds r7, #40 ; 0x28 801fdb0: 46bd mov sp, r7 801fdb2: bd80 pop {r7, pc} 801fdb4: 24013980 .word 0x24013980 801fdb8: 24013994 .word 0x24013994 801fdbc: 080266f4 .word 0x080266f4 801fdc0: 0802672c .word 0x0802672c 801fdc4: 08026764 .word 0x08026764 801fdc8: 0802678c .word 0x0802678c 0801fdcc : * p->payload pointing to the IP header * @param t type of the 'unreachable' packet */ void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) { 801fdcc: b580 push {r7, lr} 801fdce: b082 sub sp, #8 801fdd0: af00 add r7, sp, #0 801fdd2: 6078 str r0, [r7, #4] 801fdd4: 460b mov r3, r1 801fdd6: 70fb strb r3, [r7, #3] MIB2_STATS_INC(mib2.icmpoutdestunreachs); icmp_send_response(p, ICMP_DUR, t); 801fdd8: 78fb ldrb r3, [r7, #3] 801fdda: 461a mov r2, r3 801fddc: 2103 movs r1, #3 801fdde: 6878 ldr r0, [r7, #4] 801fde0: f000 f814 bl 801fe0c } 801fde4: bf00 nop 801fde6: 3708 adds r7, #8 801fde8: 46bd mov sp, r7 801fdea: bd80 pop {r7, pc} 0801fdec : * p->payload pointing to the IP header * @param t type of the 'time exceeded' packet */ void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) { 801fdec: b580 push {r7, lr} 801fdee: b082 sub sp, #8 801fdf0: af00 add r7, sp, #0 801fdf2: 6078 str r0, [r7, #4] 801fdf4: 460b mov r3, r1 801fdf6: 70fb strb r3, [r7, #3] MIB2_STATS_INC(mib2.icmpouttimeexcds); icmp_send_response(p, ICMP_TE, t); 801fdf8: 78fb ldrb r3, [r7, #3] 801fdfa: 461a mov r2, r3 801fdfc: 210b movs r1, #11 801fdfe: 6878 ldr r0, [r7, #4] 801fe00: f000 f804 bl 801fe0c } 801fe04: bf00 nop 801fe06: 3708 adds r7, #8 801fe08: 46bd mov sp, r7 801fe0a: bd80 pop {r7, pc} 0801fe0c : * @param type Type of the ICMP header * @param code Code of the ICMP header */ static void icmp_send_response(struct pbuf *p, u8_t type, u8_t code) { 801fe0c: b580 push {r7, lr} 801fe0e: b08c sub sp, #48 ; 0x30 801fe10: af04 add r7, sp, #16 801fe12: 6078 str r0, [r7, #4] 801fe14: 460b mov r3, r1 801fe16: 70fb strb r3, [r7, #3] 801fe18: 4613 mov r3, r2 801fe1a: 70bb strb r3, [r7, #2] /* increase number of messages attempted to send */ MIB2_STATS_INC(mib2.icmpoutmsgs); /* ICMP header + IP header + 8 bytes of data */ q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE, 801fe1c: f44f 7220 mov.w r2, #640 ; 0x280 801fe20: 2124 movs r1, #36 ; 0x24 801fe22: 2022 movs r0, #34 ; 0x22 801fe24: f7f7 fb80 bl 8017528 801fe28: 61b8 str r0, [r7, #24] PBUF_RAM); if (q == NULL) { 801fe2a: 69bb ldr r3, [r7, #24] 801fe2c: 2b00 cmp r3, #0 801fe2e: d056 beq.n 801fede LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n")); MIB2_STATS_INC(mib2.icmpouterrors); return; } LWIP_ASSERT("check that first pbuf can hold icmp message", 801fe30: 69bb ldr r3, [r7, #24] 801fe32: 895b ldrh r3, [r3, #10] 801fe34: 2b23 cmp r3, #35 ; 0x23 801fe36: d806 bhi.n 801fe46 801fe38: 4b2b ldr r3, [pc, #172] ; (801fee8 ) 801fe3a: f44f 72b4 mov.w r2, #360 ; 0x168 801fe3e: 492b ldr r1, [pc, #172] ; (801feec ) 801fe40: 482b ldr r0, [pc, #172] ; (801fef0 ) 801fe42: f001 fda1 bl 8021988 (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE))); iphdr = (struct ip_hdr *)p->payload; 801fe46: 687b ldr r3, [r7, #4] 801fe48: 685b ldr r3, [r3, #4] 801fe4a: 617b str r3, [r7, #20] ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src); LWIP_DEBUGF(ICMP_DEBUG, (" to ")); ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest); LWIP_DEBUGF(ICMP_DEBUG, ("\n")); icmphdr = (struct icmp_echo_hdr *)q->payload; 801fe4c: 69bb ldr r3, [r7, #24] 801fe4e: 685b ldr r3, [r3, #4] 801fe50: 613b str r3, [r7, #16] icmphdr->type = type; 801fe52: 693b ldr r3, [r7, #16] 801fe54: 78fa ldrb r2, [r7, #3] 801fe56: 701a strb r2, [r3, #0] icmphdr->code = code; 801fe58: 693b ldr r3, [r7, #16] 801fe5a: 78ba ldrb r2, [r7, #2] 801fe5c: 705a strb r2, [r3, #1] icmphdr->id = 0; 801fe5e: 693b ldr r3, [r7, #16] 801fe60: 2200 movs r2, #0 801fe62: 711a strb r2, [r3, #4] 801fe64: 2200 movs r2, #0 801fe66: 715a strb r2, [r3, #5] icmphdr->seqno = 0; 801fe68: 693b ldr r3, [r7, #16] 801fe6a: 2200 movs r2, #0 801fe6c: 719a strb r2, [r3, #6] 801fe6e: 2200 movs r2, #0 801fe70: 71da strb r2, [r3, #7] /* copy fields from original packet */ SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload, 801fe72: 69bb ldr r3, [r7, #24] 801fe74: 685b ldr r3, [r3, #4] 801fe76: f103 0008 add.w r0, r3, #8 801fe7a: 687b ldr r3, [r7, #4] 801fe7c: 685b ldr r3, [r3, #4] 801fe7e: 221c movs r2, #28 801fe80: 4619 mov r1, r3 801fe82: f001 ffb0 bl 8021de6 IP_HLEN + ICMP_DEST_UNREACH_DATASIZE); ip4_addr_copy(iphdr_src, iphdr->src); 801fe86: 697b ldr r3, [r7, #20] 801fe88: 68db ldr r3, [r3, #12] 801fe8a: 60fb str r3, [r7, #12] ip4_addr_t iphdr_dst; ip4_addr_copy(iphdr_dst, iphdr->dest); netif = ip4_route_src(&iphdr_dst, &iphdr_src); } #else netif = ip4_route(&iphdr_src); 801fe8c: f107 030c add.w r3, r7, #12 801fe90: 4618 mov r0, r3 801fe92: f000 f82f bl 801fef4 801fe96: 61f8 str r0, [r7, #28] #endif if (netif != NULL) { 801fe98: 69fb ldr r3, [r7, #28] 801fe9a: 2b00 cmp r3, #0 801fe9c: d01b beq.n 801fed6 /* calculate checksum */ icmphdr->chksum = 0; 801fe9e: 693b ldr r3, [r7, #16] 801fea0: 2200 movs r2, #0 801fea2: 709a strb r2, [r3, #2] 801fea4: 2200 movs r2, #0 801fea6: 70da strb r2, [r3, #3] #if CHECKSUM_GEN_ICMP IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) { icmphdr->chksum = inet_chksum(icmphdr, q->len); 801fea8: 69bb ldr r3, [r7, #24] 801feaa: 895b ldrh r3, [r3, #10] 801feac: 4619 mov r1, r3 801feae: 6938 ldr r0, [r7, #16] 801feb0: f7f6 f8d1 bl 8016056 801feb4: 4603 mov r3, r0 801feb6: 461a mov r2, r3 801feb8: 693b ldr r3, [r7, #16] 801feba: 805a strh r2, [r3, #2] } #endif ICMP_STATS_INC(icmp.xmit); ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif); 801febc: f107 020c add.w r2, r7, #12 801fec0: 69fb ldr r3, [r7, #28] 801fec2: 9302 str r3, [sp, #8] 801fec4: 2301 movs r3, #1 801fec6: 9301 str r3, [sp, #4] 801fec8: 2300 movs r3, #0 801feca: 9300 str r3, [sp, #0] 801fecc: 23ff movs r3, #255 ; 0xff 801fece: 2100 movs r1, #0 801fed0: 69b8 ldr r0, [r7, #24] 801fed2: f000 f9cd bl 8020270 } pbuf_free(q); 801fed6: 69b8 ldr r0, [r7, #24] 801fed8: f7f7 fe0e bl 8017af8 801fedc: e000 b.n 801fee0 return; 801fede: bf00 nop } 801fee0: 3720 adds r7, #32 801fee2: 46bd mov sp, r7 801fee4: bd80 pop {r7, pc} 801fee6: bf00 nop 801fee8: 080266f4 .word 0x080266f4 801feec: 080267c0 .word 0x080267c0 801fef0: 08026764 .word 0x08026764 0801fef4 : * @param dest the destination IP address for which to find the route * @return the netif on which to send to reach dest */ struct netif * ip4_route(const ip4_addr_t *dest) { 801fef4: b480 push {r7} 801fef6: b085 sub sp, #20 801fef8: af00 add r7, sp, #0 801fefa: 6078 str r0, [r7, #4] /* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */ LWIP_UNUSED_ARG(dest); /* iterate through netifs */ NETIF_FOREACH(netif) { 801fefc: 4b33 ldr r3, [pc, #204] ; (801ffcc ) 801fefe: 681b ldr r3, [r3, #0] 801ff00: 60fb str r3, [r7, #12] 801ff02: e036 b.n 801ff72 /* is the netif up, does it have a link and a valid address? */ if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) { 801ff04: 68fb ldr r3, [r7, #12] 801ff06: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801ff0a: f003 0301 and.w r3, r3, #1 801ff0e: b2db uxtb r3, r3 801ff10: 2b00 cmp r3, #0 801ff12: d02b beq.n 801ff6c 801ff14: 68fb ldr r3, [r7, #12] 801ff16: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801ff1a: 089b lsrs r3, r3, #2 801ff1c: f003 0301 and.w r3, r3, #1 801ff20: b2db uxtb r3, r3 801ff22: 2b00 cmp r3, #0 801ff24: d022 beq.n 801ff6c 801ff26: 68fb ldr r3, [r7, #12] 801ff28: 3304 adds r3, #4 801ff2a: 681b ldr r3, [r3, #0] 801ff2c: 2b00 cmp r3, #0 801ff2e: d01d beq.n 801ff6c /* network mask matches? */ if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) { 801ff30: 687b ldr r3, [r7, #4] 801ff32: 681a ldr r2, [r3, #0] 801ff34: 68fb ldr r3, [r7, #12] 801ff36: 3304 adds r3, #4 801ff38: 681b ldr r3, [r3, #0] 801ff3a: 405a eors r2, r3 801ff3c: 68fb ldr r3, [r7, #12] 801ff3e: 3308 adds r3, #8 801ff40: 681b ldr r3, [r3, #0] 801ff42: 4013 ands r3, r2 801ff44: 2b00 cmp r3, #0 801ff46: d101 bne.n 801ff4c /* return netif on which to forward IP packet */ return netif; 801ff48: 68fb ldr r3, [r7, #12] 801ff4a: e038 b.n 801ffbe } /* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */ if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) { 801ff4c: 68fb ldr r3, [r7, #12] 801ff4e: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801ff52: f003 0302 and.w r3, r3, #2 801ff56: 2b00 cmp r3, #0 801ff58: d108 bne.n 801ff6c 801ff5a: 687b ldr r3, [r7, #4] 801ff5c: 681a ldr r2, [r3, #0] 801ff5e: 68fb ldr r3, [r7, #12] 801ff60: 330c adds r3, #12 801ff62: 681b ldr r3, [r3, #0] 801ff64: 429a cmp r2, r3 801ff66: d101 bne.n 801ff6c /* return netif on which to forward IP packet */ return netif; 801ff68: 68fb ldr r3, [r7, #12] 801ff6a: e028 b.n 801ffbe NETIF_FOREACH(netif) { 801ff6c: 68fb ldr r3, [r7, #12] 801ff6e: 681b ldr r3, [r3, #0] 801ff70: 60fb str r3, [r7, #12] 801ff72: 68fb ldr r3, [r7, #12] 801ff74: 2b00 cmp r3, #0 801ff76: d1c5 bne.n 801ff04 return netif; } #endif #endif /* !LWIP_SINGLE_NETIF */ if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) || 801ff78: 4b15 ldr r3, [pc, #84] ; (801ffd0 ) 801ff7a: 681b ldr r3, [r3, #0] 801ff7c: 2b00 cmp r3, #0 801ff7e: d01a beq.n 801ffb6 801ff80: 4b13 ldr r3, [pc, #76] ; (801ffd0 ) 801ff82: 681b ldr r3, [r3, #0] 801ff84: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801ff88: f003 0301 and.w r3, r3, #1 801ff8c: 2b00 cmp r3, #0 801ff8e: d012 beq.n 801ffb6 801ff90: 4b0f ldr r3, [pc, #60] ; (801ffd0 ) 801ff92: 681b ldr r3, [r3, #0] 801ff94: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801ff98: f003 0304 and.w r3, r3, #4 801ff9c: 2b00 cmp r3, #0 801ff9e: d00a beq.n 801ffb6 ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) { 801ffa0: 4b0b ldr r3, [pc, #44] ; (801ffd0 ) 801ffa2: 681b ldr r3, [r3, #0] 801ffa4: 3304 adds r3, #4 801ffa6: 681b ldr r3, [r3, #0] if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) || 801ffa8: 2b00 cmp r3, #0 801ffaa: d004 beq.n 801ffb6 ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) { 801ffac: 687b ldr r3, [r7, #4] 801ffae: 681b ldr r3, [r3, #0] 801ffb0: b2db uxtb r3, r3 801ffb2: 2b7f cmp r3, #127 ; 0x7f 801ffb4: d101 bne.n 801ffba If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */ LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); IP_STATS_INC(ip.rterr); MIB2_STATS_INC(mib2.ipoutnoroutes); return NULL; 801ffb6: 2300 movs r3, #0 801ffb8: e001 b.n 801ffbe } return netif_default; 801ffba: 4b05 ldr r3, [pc, #20] ; (801ffd0 ) 801ffbc: 681b ldr r3, [r3, #0] } 801ffbe: 4618 mov r0, r3 801ffc0: 3714 adds r7, #20 801ffc2: 46bd mov sp, r7 801ffc4: f85d 7b04 ldr.w r7, [sp], #4 801ffc8: 4770 bx lr 801ffca: bf00 nop 801ffcc: 2401a474 .word 0x2401a474 801ffd0: 2401a478 .word 0x2401a478 0801ffd4 : #endif /* IP_FORWARD */ /** Return true if the current input packet should be accepted on this netif */ static int ip4_input_accept(struct netif *netif) { 801ffd4: b580 push {r7, lr} 801ffd6: b082 sub sp, #8 801ffd8: af00 add r7, sp, #0 801ffda: 6078 str r0, [r7, #4] ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)), ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)), ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif)))); /* interface is up and configured? */ if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) { 801ffdc: 687b ldr r3, [r7, #4] 801ffde: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 801ffe2: f003 0301 and.w r3, r3, #1 801ffe6: b2db uxtb r3, r3 801ffe8: 2b00 cmp r3, #0 801ffea: d016 beq.n 802001a 801ffec: 687b ldr r3, [r7, #4] 801ffee: 3304 adds r3, #4 801fff0: 681b ldr r3, [r3, #0] 801fff2: 2b00 cmp r3, #0 801fff4: d011 beq.n 802001a /* unicast to this interface address? */ if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) || 801fff6: 4b0b ldr r3, [pc, #44] ; (8020024 ) 801fff8: 695a ldr r2, [r3, #20] 801fffa: 687b ldr r3, [r7, #4] 801fffc: 3304 adds r3, #4 801fffe: 681b ldr r3, [r3, #0] 8020000: 429a cmp r2, r3 8020002: d008 beq.n 8020016 /* or broadcast on this interface network address? */ ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) 8020004: 4b07 ldr r3, [pc, #28] ; (8020024 ) 8020006: 695b ldr r3, [r3, #20] 8020008: 6879 ldr r1, [r7, #4] 802000a: 4618 mov r0, r3 802000c: f000 fa08 bl 8020420 8020010: 4603 mov r3, r0 if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) || 8020012: 2b00 cmp r3, #0 8020014: d001 beq.n 802001a #endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */ ) { LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n", netif->name[0], netif->name[1])); /* accept on this netif */ return 1; 8020016: 2301 movs r3, #1 8020018: e000 b.n 802001c /* accept on this netif */ return 1; } #endif /* LWIP_AUTOIP */ } return 0; 802001a: 2300 movs r3, #0 } 802001c: 4618 mov r0, r3 802001e: 3708 adds r7, #8 8020020: 46bd mov sp, r7 8020022: bd80 pop {r7, pc} 8020024: 24013980 .word 0x24013980 08020028 : * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't * processed, but currently always returns ERR_OK) */ err_t ip4_input(struct pbuf *p, struct netif *inp) { 8020028: b580 push {r7, lr} 802002a: b086 sub sp, #24 802002c: af00 add r7, sp, #0 802002e: 6078 str r0, [r7, #4] 8020030: 6039 str r1, [r7, #0] IP_STATS_INC(ip.recv); MIB2_STATS_INC(mib2.ipinreceives); /* identify the IP header */ iphdr = (struct ip_hdr *)p->payload; 8020032: 687b ldr r3, [r7, #4] 8020034: 685b ldr r3, [r3, #4] 8020036: 613b str r3, [r7, #16] if (IPH_V(iphdr) != 4) { 8020038: 693b ldr r3, [r7, #16] 802003a: 781b ldrb r3, [r3, #0] 802003c: 091b lsrs r3, r3, #4 802003e: b2db uxtb r3, r3 8020040: 2b04 cmp r3, #4 8020042: d004 beq.n 802004e LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr))); ip4_debug_print(p); pbuf_free(p); 8020044: 6878 ldr r0, [r7, #4] 8020046: f7f7 fd57 bl 8017af8 IP_STATS_INC(ip.err); IP_STATS_INC(ip.drop); MIB2_STATS_INC(mib2.ipinhdrerrors); return ERR_OK; 802004a: 2300 movs r3, #0 802004c: e107 b.n 802025e return ERR_OK; } #endif /* obtain IP header length in bytes */ iphdr_hlen = IPH_HL_BYTES(iphdr); 802004e: 693b ldr r3, [r7, #16] 8020050: 781b ldrb r3, [r3, #0] 8020052: f003 030f and.w r3, r3, #15 8020056: b2db uxtb r3, r3 8020058: 009b lsls r3, r3, #2 802005a: b2db uxtb r3, r3 802005c: 81fb strh r3, [r7, #14] /* obtain ip length in bytes */ iphdr_len = lwip_ntohs(IPH_LEN(iphdr)); 802005e: 693b ldr r3, [r7, #16] 8020060: 885b ldrh r3, [r3, #2] 8020062: b29b uxth r3, r3 8020064: 4618 mov r0, r3 8020066: f7f5 ff6b bl 8015f40 802006a: 4603 mov r3, r0 802006c: 81bb strh r3, [r7, #12] /* Trim pbuf. This is especially required for packets < 60 bytes. */ if (iphdr_len < p->tot_len) { 802006e: 687b ldr r3, [r7, #4] 8020070: 891b ldrh r3, [r3, #8] 8020072: 89ba ldrh r2, [r7, #12] 8020074: 429a cmp r2, r3 8020076: d204 bcs.n 8020082 pbuf_realloc(p, iphdr_len); 8020078: 89bb ldrh r3, [r7, #12] 802007a: 4619 mov r1, r3 802007c: 6878 ldr r0, [r7, #4] 802007e: f7f7 fbb5 bl 80177ec } /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */ if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) { 8020082: 687b ldr r3, [r7, #4] 8020084: 895b ldrh r3, [r3, #10] 8020086: 89fa ldrh r2, [r7, #14] 8020088: 429a cmp r2, r3 802008a: d807 bhi.n 802009c 802008c: 687b ldr r3, [r7, #4] 802008e: 891b ldrh r3, [r3, #8] 8020090: 89ba ldrh r2, [r7, #12] 8020092: 429a cmp r2, r3 8020094: d802 bhi.n 802009c 8020096: 89fb ldrh r3, [r7, #14] 8020098: 2b13 cmp r3, #19 802009a: d804 bhi.n 80200a6 LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n", iphdr_len, p->tot_len)); } /* free (drop) packet pbufs */ pbuf_free(p); 802009c: 6878 ldr r0, [r7, #4] 802009e: f7f7 fd2b bl 8017af8 IP_STATS_INC(ip.lenerr); IP_STATS_INC(ip.drop); MIB2_STATS_INC(mib2.ipindiscards); return ERR_OK; 80200a2: 2300 movs r3, #0 80200a4: e0db b.n 802025e } } #endif /* copy IP addresses to aligned ip_addr_t */ ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest); 80200a6: 693b ldr r3, [r7, #16] 80200a8: 691b ldr r3, [r3, #16] 80200aa: 4a6f ldr r2, [pc, #444] ; (8020268 ) 80200ac: 6153 str r3, [r2, #20] ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src); 80200ae: 693b ldr r3, [r7, #16] 80200b0: 68db ldr r3, [r3, #12] 80200b2: 4a6d ldr r2, [pc, #436] ; (8020268 ) 80200b4: 6113 str r3, [r2, #16] /* match packet against an interface, i.e. is this packet for us? */ if (ip4_addr_ismulticast(ip4_current_dest_addr())) { 80200b6: 4b6c ldr r3, [pc, #432] ; (8020268 ) 80200b8: 695b ldr r3, [r3, #20] 80200ba: f003 03f0 and.w r3, r3, #240 ; 0xf0 80200be: 2be0 cmp r3, #224 ; 0xe0 80200c0: d112 bne.n 80200e8 netif = inp; } else { netif = NULL; } #else /* LWIP_IGMP */ if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) { 80200c2: 683b ldr r3, [r7, #0] 80200c4: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 80200c8: f003 0301 and.w r3, r3, #1 80200cc: b2db uxtb r3, r3 80200ce: 2b00 cmp r3, #0 80200d0: d007 beq.n 80200e2 80200d2: 683b ldr r3, [r7, #0] 80200d4: 3304 adds r3, #4 80200d6: 681b ldr r3, [r3, #0] 80200d8: 2b00 cmp r3, #0 80200da: d002 beq.n 80200e2 netif = inp; 80200dc: 683b ldr r3, [r7, #0] 80200de: 617b str r3, [r7, #20] 80200e0: e02a b.n 8020138 } else { netif = NULL; 80200e2: 2300 movs r3, #0 80200e4: 617b str r3, [r7, #20] 80200e6: e027 b.n 8020138 } #endif /* LWIP_IGMP */ } else { /* start trying with inp. if that's not acceptable, start walking the list of configured netifs. */ if (ip4_input_accept(inp)) { 80200e8: 6838 ldr r0, [r7, #0] 80200ea: f7ff ff73 bl 801ffd4 80200ee: 4603 mov r3, r0 80200f0: 2b00 cmp r3, #0 80200f2: d002 beq.n 80200fa netif = inp; 80200f4: 683b ldr r3, [r7, #0] 80200f6: 617b str r3, [r7, #20] 80200f8: e01e b.n 8020138 } else { netif = NULL; 80200fa: 2300 movs r3, #0 80200fc: 617b str r3, [r7, #20] #if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF /* Packets sent to the loopback address must not be accepted on an * interface that does not have the loopback address assigned to it, * unless a non-loopback interface is used for loopback traffic. */ if (!ip4_addr_isloopback(ip4_current_dest_addr())) 80200fe: 4b5a ldr r3, [pc, #360] ; (8020268 ) 8020100: 695b ldr r3, [r3, #20] 8020102: b2db uxtb r3, r3 8020104: 2b7f cmp r3, #127 ; 0x7f 8020106: d017 beq.n 8020138 #endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */ { #if !LWIP_SINGLE_NETIF NETIF_FOREACH(netif) { 8020108: 4b58 ldr r3, [pc, #352] ; (802026c ) 802010a: 681b ldr r3, [r3, #0] 802010c: 617b str r3, [r7, #20] 802010e: e00e b.n 802012e if (netif == inp) { 8020110: 697a ldr r2, [r7, #20] 8020112: 683b ldr r3, [r7, #0] 8020114: 429a cmp r2, r3 8020116: d006 beq.n 8020126 /* we checked that before already */ continue; } if (ip4_input_accept(netif)) { 8020118: 6978 ldr r0, [r7, #20] 802011a: f7ff ff5b bl 801ffd4 802011e: 4603 mov r3, r0 8020120: 2b00 cmp r3, #0 8020122: d108 bne.n 8020136 8020124: e000 b.n 8020128 continue; 8020126: bf00 nop NETIF_FOREACH(netif) { 8020128: 697b ldr r3, [r7, #20] 802012a: 681b ldr r3, [r3, #0] 802012c: 617b str r3, [r7, #20] 802012e: 697b ldr r3, [r7, #20] 8020130: 2b00 cmp r3, #0 8020132: d1ed bne.n 8020110 8020134: e000 b.n 8020138 break; 8020136: bf00 nop && !ip4_addr_isany_val(*ip4_current_src_addr()) #endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ ) #endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */ { if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) || 8020138: 4b4b ldr r3, [pc, #300] ; (8020268 ) 802013a: 691b ldr r3, [r3, #16] 802013c: 6839 ldr r1, [r7, #0] 802013e: 4618 mov r0, r3 8020140: f000 f96e bl 8020420 8020144: 4603 mov r3, r0 8020146: 2b00 cmp r3, #0 8020148: d105 bne.n 8020156 (ip4_addr_ismulticast(ip4_current_src_addr()))) { 802014a: 4b47 ldr r3, [pc, #284] ; (8020268 ) 802014c: 691b ldr r3, [r3, #16] 802014e: f003 03f0 and.w r3, r3, #240 ; 0xf0 if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) || 8020152: 2be0 cmp r3, #224 ; 0xe0 8020154: d104 bne.n 8020160 /* packet source is not valid */ LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n")); /* free (drop) packet pbufs */ pbuf_free(p); 8020156: 6878 ldr r0, [r7, #4] 8020158: f7f7 fcce bl 8017af8 IP_STATS_INC(ip.drop); MIB2_STATS_INC(mib2.ipinaddrerrors); MIB2_STATS_INC(mib2.ipindiscards); return ERR_OK; 802015c: 2300 movs r3, #0 802015e: e07e b.n 802025e } } /* packet not for us? */ if (netif == NULL) { 8020160: 697b ldr r3, [r7, #20] 8020162: 2b00 cmp r3, #0 8020164: d104 bne.n 8020170 { IP_STATS_INC(ip.drop); MIB2_STATS_INC(mib2.ipinaddrerrors); MIB2_STATS_INC(mib2.ipindiscards); } pbuf_free(p); 8020166: 6878 ldr r0, [r7, #4] 8020168: f7f7 fcc6 bl 8017af8 return ERR_OK; 802016c: 2300 movs r3, #0 802016e: e076 b.n 802025e } /* packet consists of multiple fragments? */ if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) { 8020170: 693b ldr r3, [r7, #16] 8020172: 88db ldrh r3, [r3, #6] 8020174: b29b uxth r3, r3 8020176: 461a mov r2, r3 8020178: f64f 733f movw r3, #65343 ; 0xff3f 802017c: 4013 ands r3, r2 802017e: 2b00 cmp r3, #0 8020180: d00b beq.n 802019a #if IP_REASSEMBLY /* packet fragment reassembly code present? */ LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n", lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8))); /* reassemble the packet*/ p = ip4_reass(p); 8020182: 6878 ldr r0, [r7, #4] 8020184: f000 fc92 bl 8020aac 8020188: 6078 str r0, [r7, #4] /* packet not fully reassembled yet? */ if (p == NULL) { 802018a: 687b ldr r3, [r7, #4] 802018c: 2b00 cmp r3, #0 802018e: d101 bne.n 8020194 return ERR_OK; 8020190: 2300 movs r3, #0 8020192: e064 b.n 802025e } iphdr = (const struct ip_hdr *)p->payload; 8020194: 687b ldr r3, [r7, #4] 8020196: 685b ldr r3, [r3, #4] 8020198: 613b str r3, [r7, #16] /* send to upper layers */ LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n")); ip4_debug_print(p); LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); ip_data.current_netif = netif; 802019a: 4a33 ldr r2, [pc, #204] ; (8020268 ) 802019c: 697b ldr r3, [r7, #20] 802019e: 6013 str r3, [r2, #0] ip_data.current_input_netif = inp; 80201a0: 4a31 ldr r2, [pc, #196] ; (8020268 ) 80201a2: 683b ldr r3, [r7, #0] 80201a4: 6053 str r3, [r2, #4] ip_data.current_ip4_header = iphdr; 80201a6: 4a30 ldr r2, [pc, #192] ; (8020268 ) 80201a8: 693b ldr r3, [r7, #16] 80201aa: 6093 str r3, [r2, #8] ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr); 80201ac: 693b ldr r3, [r7, #16] 80201ae: 781b ldrb r3, [r3, #0] 80201b0: f003 030f and.w r3, r3, #15 80201b4: b2db uxtb r3, r3 80201b6: 009b lsls r3, r3, #2 80201b8: b2db uxtb r3, r3 80201ba: b29a uxth r2, r3 80201bc: 4b2a ldr r3, [pc, #168] ; (8020268 ) 80201be: 819a strh r2, [r3, #12] /* raw input did not eat the packet? */ raw_status = raw_input(p, inp); if (raw_status != RAW_INPUT_EATEN) #endif /* LWIP_RAW */ { pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */ 80201c0: 89fb ldrh r3, [r7, #14] 80201c2: 4619 mov r1, r3 80201c4: 6878 ldr r0, [r7, #4] 80201c6: f7f7 fc11 bl 80179ec switch (IPH_PROTO(iphdr)) { 80201ca: 693b ldr r3, [r7, #16] 80201cc: 7a5b ldrb r3, [r3, #9] 80201ce: 2b11 cmp r3, #17 80201d0: d006 beq.n 80201e0 80201d2: 2b11 cmp r3, #17 80201d4: dc13 bgt.n 80201fe 80201d6: 2b01 cmp r3, #1 80201d8: d00c beq.n 80201f4 80201da: 2b06 cmp r3, #6 80201dc: d005 beq.n 80201ea 80201de: e00e b.n 80201fe case IP_PROTO_UDP: #if LWIP_UDPLITE case IP_PROTO_UDPLITE: #endif /* LWIP_UDPLITE */ MIB2_STATS_INC(mib2.ipindelivers); udp_input(p, inp); 80201e0: 6839 ldr r1, [r7, #0] 80201e2: 6878 ldr r0, [r7, #4] 80201e4: f7fe fa94 bl 801e710 break; 80201e8: e026 b.n 8020238 #endif /* LWIP_UDP */ #if LWIP_TCP case IP_PROTO_TCP: MIB2_STATS_INC(mib2.ipindelivers); tcp_input(p, inp); 80201ea: 6839 ldr r1, [r7, #0] 80201ec: 6878 ldr r0, [r7, #4] 80201ee: f7f9 fde1 bl 8019db4 break; 80201f2: e021 b.n 8020238 #endif /* LWIP_TCP */ #if LWIP_ICMP case IP_PROTO_ICMP: MIB2_STATS_INC(mib2.ipindelivers); icmp_input(p, inp); 80201f4: 6839 ldr r1, [r7, #0] 80201f6: 6878 ldr r0, [r7, #4] 80201f8: f7ff fcc4 bl 801fb84 break; 80201fc: e01c b.n 8020238 } else #endif /* LWIP_RAW */ { #if LWIP_ICMP /* send ICMP destination protocol unreachable unless is was a broadcast */ if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) && 80201fe: 4b1a ldr r3, [pc, #104] ; (8020268 ) 8020200: 695b ldr r3, [r3, #20] 8020202: 6979 ldr r1, [r7, #20] 8020204: 4618 mov r0, r3 8020206: f000 f90b bl 8020420 802020a: 4603 mov r3, r0 802020c: 2b00 cmp r3, #0 802020e: d10f bne.n 8020230 !ip4_addr_ismulticast(ip4_current_dest_addr())) { 8020210: 4b15 ldr r3, [pc, #84] ; (8020268 ) 8020212: 695b ldr r3, [r3, #20] 8020214: f003 03f0 and.w r3, r3, #240 ; 0xf0 if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) && 8020218: 2be0 cmp r3, #224 ; 0xe0 802021a: d009 beq.n 8020230 pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */ 802021c: f9b7 300e ldrsh.w r3, [r7, #14] 8020220: 4619 mov r1, r3 8020222: 6878 ldr r0, [r7, #4] 8020224: f7f7 fc55 bl 8017ad2 icmp_dest_unreach(p, ICMP_DUR_PROTO); 8020228: 2102 movs r1, #2 802022a: 6878 ldr r0, [r7, #4] 802022c: f7ff fdce bl 801fdcc IP_STATS_INC(ip.proterr); IP_STATS_INC(ip.drop); MIB2_STATS_INC(mib2.ipinunknownprotos); } pbuf_free(p); 8020230: 6878 ldr r0, [r7, #4] 8020232: f7f7 fc61 bl 8017af8 break; 8020236: bf00 nop } } /* @todo: this is not really necessary... */ ip_data.current_netif = NULL; 8020238: 4b0b ldr r3, [pc, #44] ; (8020268 ) 802023a: 2200 movs r2, #0 802023c: 601a str r2, [r3, #0] ip_data.current_input_netif = NULL; 802023e: 4b0a ldr r3, [pc, #40] ; (8020268 ) 8020240: 2200 movs r2, #0 8020242: 605a str r2, [r3, #4] ip_data.current_ip4_header = NULL; 8020244: 4b08 ldr r3, [pc, #32] ; (8020268 ) 8020246: 2200 movs r2, #0 8020248: 609a str r2, [r3, #8] ip_data.current_ip_header_tot_len = 0; 802024a: 4b07 ldr r3, [pc, #28] ; (8020268 ) 802024c: 2200 movs r2, #0 802024e: 819a strh r2, [r3, #12] ip4_addr_set_any(ip4_current_src_addr()); 8020250: 4b05 ldr r3, [pc, #20] ; (8020268 ) 8020252: 2200 movs r2, #0 8020254: 611a str r2, [r3, #16] ip4_addr_set_any(ip4_current_dest_addr()); 8020256: 4b04 ldr r3, [pc, #16] ; (8020268 ) 8020258: 2200 movs r2, #0 802025a: 615a str r2, [r3, #20] return ERR_OK; 802025c: 2300 movs r3, #0 } 802025e: 4618 mov r0, r3 8020260: 3718 adds r7, #24 8020262: 46bd mov sp, r7 8020264: bd80 pop {r7, pc} 8020266: bf00 nop 8020268: 24013980 .word 0x24013980 802026c: 2401a474 .word 0x2401a474 08020270 : */ err_t ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, u8_t ttl, u8_t tos, u8_t proto, struct netif *netif) { 8020270: b580 push {r7, lr} 8020272: b08a sub sp, #40 ; 0x28 8020274: af04 add r7, sp, #16 8020276: 60f8 str r0, [r7, #12] 8020278: 60b9 str r1, [r7, #8] 802027a: 607a str r2, [r7, #4] 802027c: 70fb strb r3, [r7, #3] ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, u16_t optlen) { #endif /* IP_OPTIONS_SEND */ const ip4_addr_t *src_used = src; 802027e: 68bb ldr r3, [r7, #8] 8020280: 617b str r3, [r7, #20] if (dest != LWIP_IP_HDRINCL) { 8020282: 687b ldr r3, [r7, #4] 8020284: 2b00 cmp r3, #0 8020286: d009 beq.n 802029c if (ip4_addr_isany(src)) { 8020288: 68bb ldr r3, [r7, #8] 802028a: 2b00 cmp r3, #0 802028c: d003 beq.n 8020296 802028e: 68bb ldr r3, [r7, #8] 8020290: 681b ldr r3, [r3, #0] 8020292: 2b00 cmp r3, #0 8020294: d102 bne.n 802029c src_used = netif_ip4_addr(netif); 8020296: 6abb ldr r3, [r7, #40] ; 0x28 8020298: 3304 adds r3, #4 802029a: 617b str r3, [r7, #20] #if IP_OPTIONS_SEND return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif, ip_options, optlen); #else /* IP_OPTIONS_SEND */ return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif); 802029c: 78fa ldrb r2, [r7, #3] 802029e: 6abb ldr r3, [r7, #40] ; 0x28 80202a0: 9302 str r3, [sp, #8] 80202a2: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 80202a6: 9301 str r3, [sp, #4] 80202a8: f897 3020 ldrb.w r3, [r7, #32] 80202ac: 9300 str r3, [sp, #0] 80202ae: 4613 mov r3, r2 80202b0: 687a ldr r2, [r7, #4] 80202b2: 6979 ldr r1, [r7, #20] 80202b4: 68f8 ldr r0, [r7, #12] 80202b6: f000 f805 bl 80202c4 80202ba: 4603 mov r3, r0 #endif /* IP_OPTIONS_SEND */ } 80202bc: 4618 mov r0, r3 80202be: 3718 adds r7, #24 80202c0: 46bd mov sp, r7 80202c2: bd80 pop {r7, pc} 080202c4 : */ err_t ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, u8_t ttl, u8_t tos, u8_t proto, struct netif *netif) { 80202c4: b580 push {r7, lr} 80202c6: b088 sub sp, #32 80202c8: af00 add r7, sp, #0 80202ca: 60f8 str r0, [r7, #12] 80202cc: 60b9 str r1, [r7, #8] 80202ce: 607a str r2, [r7, #4] 80202d0: 70fb strb r3, [r7, #3] #if CHECKSUM_GEN_IP_INLINE u32_t chk_sum = 0; #endif /* CHECKSUM_GEN_IP_INLINE */ LWIP_ASSERT_CORE_LOCKED(); LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); 80202d2: 68fb ldr r3, [r7, #12] 80202d4: 7b9b ldrb r3, [r3, #14] 80202d6: 2b01 cmp r3, #1 80202d8: d006 beq.n 80202e8 80202da: 4b4b ldr r3, [pc, #300] ; (8020408 ) 80202dc: f44f 7255 mov.w r2, #852 ; 0x354 80202e0: 494a ldr r1, [pc, #296] ; (802040c ) 80202e2: 484b ldr r0, [pc, #300] ; (8020410 ) 80202e4: f001 fb50 bl 8021988 MIB2_STATS_INC(mib2.ipoutrequests); /* Should the IP header be generated or is it already included in p? */ if (dest != LWIP_IP_HDRINCL) { 80202e8: 687b ldr r3, [r7, #4] 80202ea: 2b00 cmp r3, #0 80202ec: d060 beq.n 80203b0 u16_t ip_hlen = IP_HLEN; 80202ee: 2314 movs r3, #20 80202f0: 837b strh r3, [r7, #26] } #endif /* CHECKSUM_GEN_IP_INLINE */ } #endif /* IP_OPTIONS_SEND */ /* generate IP header */ if (pbuf_add_header(p, IP_HLEN)) { 80202f2: 2114 movs r1, #20 80202f4: 68f8 ldr r0, [r7, #12] 80202f6: f7f7 fb69 bl 80179cc 80202fa: 4603 mov r3, r0 80202fc: 2b00 cmp r3, #0 80202fe: d002 beq.n 8020306 LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n")); IP_STATS_INC(ip.err); MIB2_STATS_INC(mib2.ipoutdiscards); return ERR_BUF; 8020300: f06f 0301 mvn.w r3, #1 8020304: e07c b.n 8020400 } iphdr = (struct ip_hdr *)p->payload; 8020306: 68fb ldr r3, [r7, #12] 8020308: 685b ldr r3, [r3, #4] 802030a: 61fb str r3, [r7, #28] LWIP_ASSERT("check that first pbuf can hold struct ip_hdr", 802030c: 68fb ldr r3, [r7, #12] 802030e: 895b ldrh r3, [r3, #10] 8020310: 2b13 cmp r3, #19 8020312: d806 bhi.n 8020322 8020314: 4b3c ldr r3, [pc, #240] ; (8020408 ) 8020316: f44f 7262 mov.w r2, #904 ; 0x388 802031a: 493e ldr r1, [pc, #248] ; (8020414 ) 802031c: 483c ldr r0, [pc, #240] ; (8020410 ) 802031e: f001 fb33 bl 8021988 (p->len >= sizeof(struct ip_hdr))); IPH_TTL_SET(iphdr, ttl); 8020322: 69fb ldr r3, [r7, #28] 8020324: 78fa ldrb r2, [r7, #3] 8020326: 721a strb r2, [r3, #8] IPH_PROTO_SET(iphdr, proto); 8020328: 69fb ldr r3, [r7, #28] 802032a: f897 202c ldrb.w r2, [r7, #44] ; 0x2c 802032e: 725a strb r2, [r3, #9] #if CHECKSUM_GEN_IP_INLINE chk_sum += PP_NTOHS(proto | (ttl << 8)); #endif /* CHECKSUM_GEN_IP_INLINE */ /* dest cannot be NULL here */ ip4_addr_copy(iphdr->dest, *dest); 8020330: 687b ldr r3, [r7, #4] 8020332: 681a ldr r2, [r3, #0] 8020334: 69fb ldr r3, [r7, #28] 8020336: 611a str r2, [r3, #16] #if CHECKSUM_GEN_IP_INLINE chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF; chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16; #endif /* CHECKSUM_GEN_IP_INLINE */ IPH_VHL_SET(iphdr, 4, ip_hlen / 4); 8020338: 8b7b ldrh r3, [r7, #26] 802033a: 089b lsrs r3, r3, #2 802033c: b29b uxth r3, r3 802033e: b2db uxtb r3, r3 8020340: f043 0340 orr.w r3, r3, #64 ; 0x40 8020344: b2da uxtb r2, r3 8020346: 69fb ldr r3, [r7, #28] 8020348: 701a strb r2, [r3, #0] IPH_TOS_SET(iphdr, tos); 802034a: 69fb ldr r3, [r7, #28] 802034c: f897 2028 ldrb.w r2, [r7, #40] ; 0x28 8020350: 705a strb r2, [r3, #1] #if CHECKSUM_GEN_IP_INLINE chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8)); #endif /* CHECKSUM_GEN_IP_INLINE */ IPH_LEN_SET(iphdr, lwip_htons(p->tot_len)); 8020352: 68fb ldr r3, [r7, #12] 8020354: 891b ldrh r3, [r3, #8] 8020356: 4618 mov r0, r3 8020358: f7f5 fdf2 bl 8015f40 802035c: 4603 mov r3, r0 802035e: 461a mov r2, r3 8020360: 69fb ldr r3, [r7, #28] 8020362: 805a strh r2, [r3, #2] #if CHECKSUM_GEN_IP_INLINE chk_sum += iphdr->_len; #endif /* CHECKSUM_GEN_IP_INLINE */ IPH_OFFSET_SET(iphdr, 0); 8020364: 69fb ldr r3, [r7, #28] 8020366: 2200 movs r2, #0 8020368: 719a strb r2, [r3, #6] 802036a: 2200 movs r2, #0 802036c: 71da strb r2, [r3, #7] IPH_ID_SET(iphdr, lwip_htons(ip_id)); 802036e: 4b2a ldr r3, [pc, #168] ; (8020418 ) 8020370: 881b ldrh r3, [r3, #0] 8020372: 4618 mov r0, r3 8020374: f7f5 fde4 bl 8015f40 8020378: 4603 mov r3, r0 802037a: 461a mov r2, r3 802037c: 69fb ldr r3, [r7, #28] 802037e: 809a strh r2, [r3, #4] #if CHECKSUM_GEN_IP_INLINE chk_sum += iphdr->_id; #endif /* CHECKSUM_GEN_IP_INLINE */ ++ip_id; 8020380: 4b25 ldr r3, [pc, #148] ; (8020418 ) 8020382: 881b ldrh r3, [r3, #0] 8020384: 3301 adds r3, #1 8020386: b29a uxth r2, r3 8020388: 4b23 ldr r3, [pc, #140] ; (8020418 ) 802038a: 801a strh r2, [r3, #0] if (src == NULL) { 802038c: 68bb ldr r3, [r7, #8] 802038e: 2b00 cmp r3, #0 8020390: d104 bne.n 802039c ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4); 8020392: 4b22 ldr r3, [pc, #136] ; (802041c ) 8020394: 681a ldr r2, [r3, #0] 8020396: 69fb ldr r3, [r7, #28] 8020398: 60da str r2, [r3, #12] 802039a: e003 b.n 80203a4 } else { /* src cannot be NULL here */ ip4_addr_copy(iphdr->src, *src); 802039c: 68bb ldr r3, [r7, #8] 802039e: 681a ldr r2, [r3, #0] 80203a0: 69fb ldr r3, [r7, #28] 80203a2: 60da str r2, [r3, #12] else { IPH_CHKSUM_SET(iphdr, 0); } #endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/ #else /* CHECKSUM_GEN_IP_INLINE */ IPH_CHKSUM_SET(iphdr, 0); 80203a4: 69fb ldr r3, [r7, #28] 80203a6: 2200 movs r2, #0 80203a8: 729a strb r2, [r3, #10] 80203aa: 2200 movs r2, #0 80203ac: 72da strb r2, [r3, #11] 80203ae: e00f b.n 80203d0 } #endif /* CHECKSUM_GEN_IP */ #endif /* CHECKSUM_GEN_IP_INLINE */ } else { /* IP header already included in p */ if (p->len < IP_HLEN) { 80203b0: 68fb ldr r3, [r7, #12] 80203b2: 895b ldrh r3, [r3, #10] 80203b4: 2b13 cmp r3, #19 80203b6: d802 bhi.n 80203be LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n")); IP_STATS_INC(ip.err); MIB2_STATS_INC(mib2.ipoutdiscards); return ERR_BUF; 80203b8: f06f 0301 mvn.w r3, #1 80203bc: e020 b.n 8020400 } iphdr = (struct ip_hdr *)p->payload; 80203be: 68fb ldr r3, [r7, #12] 80203c0: 685b ldr r3, [r3, #4] 80203c2: 61fb str r3, [r7, #28] ip4_addr_copy(dest_addr, iphdr->dest); 80203c4: 69fb ldr r3, [r7, #28] 80203c6: 691b ldr r3, [r3, #16] 80203c8: 617b str r3, [r7, #20] dest = &dest_addr; 80203ca: f107 0314 add.w r3, r7, #20 80203ce: 607b str r3, [r7, #4] } #endif /* LWIP_MULTICAST_TX_OPTIONS */ #endif /* ENABLE_LOOPBACK */ #if IP_FRAG /* don't fragment if interface has mtu set to 0 [loopif] */ if (netif->mtu && (p->tot_len > netif->mtu)) { 80203d0: 6b3b ldr r3, [r7, #48] ; 0x30 80203d2: 8c9b ldrh r3, [r3, #36] ; 0x24 80203d4: 2b00 cmp r3, #0 80203d6: d00c beq.n 80203f2 80203d8: 68fb ldr r3, [r7, #12] 80203da: 891a ldrh r2, [r3, #8] 80203dc: 6b3b ldr r3, [r7, #48] ; 0x30 80203de: 8c9b ldrh r3, [r3, #36] ; 0x24 80203e0: 429a cmp r2, r3 80203e2: d906 bls.n 80203f2 return ip4_frag(p, netif, dest); 80203e4: 687a ldr r2, [r7, #4] 80203e6: 6b39 ldr r1, [r7, #48] ; 0x30 80203e8: 68f8 ldr r0, [r7, #12] 80203ea: f000 fd53 bl 8020e94 80203ee: 4603 mov r3, r0 80203f0: e006 b.n 8020400 } #endif /* IP_FRAG */ LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n")); return netif->output(netif, p, dest); 80203f2: 6b3b ldr r3, [r7, #48] ; 0x30 80203f4: 695b ldr r3, [r3, #20] 80203f6: 687a ldr r2, [r7, #4] 80203f8: 68f9 ldr r1, [r7, #12] 80203fa: 6b38 ldr r0, [r7, #48] ; 0x30 80203fc: 4798 blx r3 80203fe: 4603 mov r3, r0 } 8020400: 4618 mov r0, r3 8020402: 3720 adds r7, #32 8020404: 46bd mov sp, r7 8020406: bd80 pop {r7, pc} 8020408: 080267ec .word 0x080267ec 802040c: 08026820 .word 0x08026820 8020410: 0802682c .word 0x0802682c 8020414: 08026854 .word 0x08026854 8020418: 2401a5d6 .word 0x2401a5d6 802041c: 08026cec .word 0x08026cec 08020420 : * @param netif the network interface against which the address is checked * @return returns non-zero if the address is a broadcast address */ u8_t ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif) { 8020420: b480 push {r7} 8020422: b085 sub sp, #20 8020424: af00 add r7, sp, #0 8020426: 6078 str r0, [r7, #4] 8020428: 6039 str r1, [r7, #0] ip4_addr_t ipaddr; ip4_addr_set_u32(&ipaddr, addr); 802042a: 687b ldr r3, [r7, #4] 802042c: 60fb str r3, [r7, #12] /* all ones (broadcast) or all zeroes (old skool broadcast) */ if ((~addr == IPADDR_ANY) || 802042e: 687b ldr r3, [r7, #4] 8020430: f1b3 3fff cmp.w r3, #4294967295 8020434: d002 beq.n 802043c 8020436: 687b ldr r3, [r7, #4] 8020438: 2b00 cmp r3, #0 802043a: d101 bne.n 8020440 (addr == IPADDR_ANY)) { return 1; 802043c: 2301 movs r3, #1 802043e: e02a b.n 8020496 /* no broadcast support on this network interface? */ } else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) { 8020440: 683b ldr r3, [r7, #0] 8020442: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 8020446: f003 0302 and.w r3, r3, #2 802044a: 2b00 cmp r3, #0 802044c: d101 bne.n 8020452 /* the given address cannot be a broadcast address * nor can we check against any broadcast addresses */ return 0; 802044e: 2300 movs r3, #0 8020450: e021 b.n 8020496 /* address matches network interface address exactly? => no broadcast */ } else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) { 8020452: 683b ldr r3, [r7, #0] 8020454: 3304 adds r3, #4 8020456: 681b ldr r3, [r3, #0] 8020458: 687a ldr r2, [r7, #4] 802045a: 429a cmp r2, r3 802045c: d101 bne.n 8020462 return 0; 802045e: 2300 movs r3, #0 8020460: e019 b.n 8020496 /* on the same (sub) network... */ } else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) 8020462: 68fa ldr r2, [r7, #12] 8020464: 683b ldr r3, [r7, #0] 8020466: 3304 adds r3, #4 8020468: 681b ldr r3, [r3, #0] 802046a: 405a eors r2, r3 802046c: 683b ldr r3, [r7, #0] 802046e: 3308 adds r3, #8 8020470: 681b ldr r3, [r3, #0] 8020472: 4013 ands r3, r2 8020474: 2b00 cmp r3, #0 8020476: d10d bne.n 8020494 /* ...and host identifier bits are all ones? =>... */ && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) == 8020478: 683b ldr r3, [r7, #0] 802047a: 3308 adds r3, #8 802047c: 681b ldr r3, [r3, #0] 802047e: 43da mvns r2, r3 8020480: 687b ldr r3, [r7, #4] 8020482: 401a ands r2, r3 (IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) { 8020484: 683b ldr r3, [r7, #0] 8020486: 3308 adds r3, #8 8020488: 681b ldr r3, [r3, #0] 802048a: 43db mvns r3, r3 && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) == 802048c: 429a cmp r2, r3 802048e: d101 bne.n 8020494 /* => network broadcast address */ return 1; 8020490: 2301 movs r3, #1 8020492: e000 b.n 8020496 } else { return 0; 8020494: 2300 movs r3, #0 } } 8020496: 4618 mov r0, r3 8020498: 3714 adds r7, #20 802049a: 46bd mov sp, r7 802049c: f85d 7b04 ldr.w r7, [sp], #4 80204a0: 4770 bx lr ... 080204a4 : * * Should be called every 1000 msec (defined by IP_TMR_INTERVAL). */ void ip_reass_tmr(void) { 80204a4: b580 push {r7, lr} 80204a6: b084 sub sp, #16 80204a8: af00 add r7, sp, #0 struct ip_reassdata *r, *prev = NULL; 80204aa: 2300 movs r3, #0 80204ac: 60bb str r3, [r7, #8] r = reassdatagrams; 80204ae: 4b12 ldr r3, [pc, #72] ; (80204f8 ) 80204b0: 681b ldr r3, [r3, #0] 80204b2: 60fb str r3, [r7, #12] while (r != NULL) { 80204b4: e018 b.n 80204e8 /* Decrement the timer. Once it reaches 0, * clean up the incomplete fragment assembly */ if (r->timer > 0) { 80204b6: 68fb ldr r3, [r7, #12] 80204b8: 7fdb ldrb r3, [r3, #31] 80204ba: 2b00 cmp r3, #0 80204bc: d00b beq.n 80204d6 r->timer--; 80204be: 68fb ldr r3, [r7, #12] 80204c0: 7fdb ldrb r3, [r3, #31] 80204c2: 3b01 subs r3, #1 80204c4: b2da uxtb r2, r3 80204c6: 68fb ldr r3, [r7, #12] 80204c8: 77da strb r2, [r3, #31] LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer)); prev = r; 80204ca: 68fb ldr r3, [r7, #12] 80204cc: 60bb str r3, [r7, #8] r = r->next; 80204ce: 68fb ldr r3, [r7, #12] 80204d0: 681b ldr r3, [r3, #0] 80204d2: 60fb str r3, [r7, #12] 80204d4: e008 b.n 80204e8 } else { /* reassembly timed out */ struct ip_reassdata *tmp; LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n")); tmp = r; 80204d6: 68fb ldr r3, [r7, #12] 80204d8: 607b str r3, [r7, #4] /* get the next pointer before freeing */ r = r->next; 80204da: 68fb ldr r3, [r7, #12] 80204dc: 681b ldr r3, [r3, #0] 80204de: 60fb str r3, [r7, #12] /* free the helper struct and all enqueued pbufs */ ip_reass_free_complete_datagram(tmp, prev); 80204e0: 68b9 ldr r1, [r7, #8] 80204e2: 6878 ldr r0, [r7, #4] 80204e4: f000 f80a bl 80204fc while (r != NULL) { 80204e8: 68fb ldr r3, [r7, #12] 80204ea: 2b00 cmp r3, #0 80204ec: d1e3 bne.n 80204b6 } } } 80204ee: bf00 nop 80204f0: bf00 nop 80204f2: 3710 adds r7, #16 80204f4: 46bd mov sp, r7 80204f6: bd80 pop {r7, pc} 80204f8: 2401a5d8 .word 0x2401a5d8 080204fc : * @param prev the previous datagram in the linked list * @return the number of pbufs freed */ static int ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) { 80204fc: b580 push {r7, lr} 80204fe: b088 sub sp, #32 8020500: af00 add r7, sp, #0 8020502: 6078 str r0, [r7, #4] 8020504: 6039 str r1, [r7, #0] u16_t pbufs_freed = 0; 8020506: 2300 movs r3, #0 8020508: 83fb strh r3, [r7, #30] u16_t clen; struct pbuf *p; struct ip_reass_helper *iprh; LWIP_ASSERT("prev != ipr", prev != ipr); 802050a: 683a ldr r2, [r7, #0] 802050c: 687b ldr r3, [r7, #4] 802050e: 429a cmp r2, r3 8020510: d105 bne.n 802051e 8020512: 4b45 ldr r3, [pc, #276] ; (8020628 ) 8020514: 22ab movs r2, #171 ; 0xab 8020516: 4945 ldr r1, [pc, #276] ; (802062c ) 8020518: 4845 ldr r0, [pc, #276] ; (8020630 ) 802051a: f001 fa35 bl 8021988 if (prev != NULL) { 802051e: 683b ldr r3, [r7, #0] 8020520: 2b00 cmp r3, #0 8020522: d00a beq.n 802053a LWIP_ASSERT("prev->next == ipr", prev->next == ipr); 8020524: 683b ldr r3, [r7, #0] 8020526: 681b ldr r3, [r3, #0] 8020528: 687a ldr r2, [r7, #4] 802052a: 429a cmp r2, r3 802052c: d005 beq.n 802053a 802052e: 4b3e ldr r3, [pc, #248] ; (8020628 ) 8020530: 22ad movs r2, #173 ; 0xad 8020532: 4940 ldr r1, [pc, #256] ; (8020634 ) 8020534: 483e ldr r0, [pc, #248] ; (8020630 ) 8020536: f001 fa27 bl 8021988 } MIB2_STATS_INC(mib2.ipreasmfails); #if LWIP_ICMP iprh = (struct ip_reass_helper *)ipr->p->payload; 802053a: 687b ldr r3, [r7, #4] 802053c: 685b ldr r3, [r3, #4] 802053e: 685b ldr r3, [r3, #4] 8020540: 617b str r3, [r7, #20] if (iprh->start == 0) { 8020542: 697b ldr r3, [r7, #20] 8020544: 889b ldrh r3, [r3, #4] 8020546: b29b uxth r3, r3 8020548: 2b00 cmp r3, #0 802054a: d12a bne.n 80205a2 /* The first fragment was received, send ICMP time exceeded. */ /* First, de-queue the first pbuf from r->p. */ p = ipr->p; 802054c: 687b ldr r3, [r7, #4] 802054e: 685b ldr r3, [r3, #4] 8020550: 61bb str r3, [r7, #24] ipr->p = iprh->next_pbuf; 8020552: 697b ldr r3, [r7, #20] 8020554: 681a ldr r2, [r3, #0] 8020556: 687b ldr r3, [r7, #4] 8020558: 605a str r2, [r3, #4] /* Then, copy the original header into it. */ SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN); 802055a: 69bb ldr r3, [r7, #24] 802055c: 6858 ldr r0, [r3, #4] 802055e: 687b ldr r3, [r7, #4] 8020560: 3308 adds r3, #8 8020562: 2214 movs r2, #20 8020564: 4619 mov r1, r3 8020566: f001 fc3e bl 8021de6 icmp_time_exceeded(p, ICMP_TE_FRAG); 802056a: 2101 movs r1, #1 802056c: 69b8 ldr r0, [r7, #24] 802056e: f7ff fc3d bl 801fdec clen = pbuf_clen(p); 8020572: 69b8 ldr r0, [r7, #24] 8020574: f7f7 fb4e bl 8017c14 8020578: 4603 mov r3, r0 802057a: 827b strh r3, [r7, #18] LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); 802057c: 8bfa ldrh r2, [r7, #30] 802057e: 8a7b ldrh r3, [r7, #18] 8020580: 4413 add r3, r2 8020582: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8020586: db05 blt.n 8020594 8020588: 4b27 ldr r3, [pc, #156] ; (8020628 ) 802058a: 22bc movs r2, #188 ; 0xbc 802058c: 492a ldr r1, [pc, #168] ; (8020638 ) 802058e: 4828 ldr r0, [pc, #160] ; (8020630 ) 8020590: f001 f9fa bl 8021988 pbufs_freed = (u16_t)(pbufs_freed + clen); 8020594: 8bfa ldrh r2, [r7, #30] 8020596: 8a7b ldrh r3, [r7, #18] 8020598: 4413 add r3, r2 802059a: 83fb strh r3, [r7, #30] pbuf_free(p); 802059c: 69b8 ldr r0, [r7, #24] 802059e: f7f7 faab bl 8017af8 } #endif /* LWIP_ICMP */ /* First, free all received pbufs. The individual pbufs need to be released separately as they have not yet been chained */ p = ipr->p; 80205a2: 687b ldr r3, [r7, #4] 80205a4: 685b ldr r3, [r3, #4] 80205a6: 61bb str r3, [r7, #24] while (p != NULL) { 80205a8: e01f b.n 80205ea struct pbuf *pcur; iprh = (struct ip_reass_helper *)p->payload; 80205aa: 69bb ldr r3, [r7, #24] 80205ac: 685b ldr r3, [r3, #4] 80205ae: 617b str r3, [r7, #20] pcur = p; 80205b0: 69bb ldr r3, [r7, #24] 80205b2: 60fb str r3, [r7, #12] /* get the next pointer before freeing */ p = iprh->next_pbuf; 80205b4: 697b ldr r3, [r7, #20] 80205b6: 681b ldr r3, [r3, #0] 80205b8: 61bb str r3, [r7, #24] clen = pbuf_clen(pcur); 80205ba: 68f8 ldr r0, [r7, #12] 80205bc: f7f7 fb2a bl 8017c14 80205c0: 4603 mov r3, r0 80205c2: 827b strh r3, [r7, #18] LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); 80205c4: 8bfa ldrh r2, [r7, #30] 80205c6: 8a7b ldrh r3, [r7, #18] 80205c8: 4413 add r3, r2 80205ca: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80205ce: db05 blt.n 80205dc 80205d0: 4b15 ldr r3, [pc, #84] ; (8020628 ) 80205d2: 22cc movs r2, #204 ; 0xcc 80205d4: 4918 ldr r1, [pc, #96] ; (8020638 ) 80205d6: 4816 ldr r0, [pc, #88] ; (8020630 ) 80205d8: f001 f9d6 bl 8021988 pbufs_freed = (u16_t)(pbufs_freed + clen); 80205dc: 8bfa ldrh r2, [r7, #30] 80205de: 8a7b ldrh r3, [r7, #18] 80205e0: 4413 add r3, r2 80205e2: 83fb strh r3, [r7, #30] pbuf_free(pcur); 80205e4: 68f8 ldr r0, [r7, #12] 80205e6: f7f7 fa87 bl 8017af8 while (p != NULL) { 80205ea: 69bb ldr r3, [r7, #24] 80205ec: 2b00 cmp r3, #0 80205ee: d1dc bne.n 80205aa } /* Then, unchain the struct ip_reassdata from the list and free it. */ ip_reass_dequeue_datagram(ipr, prev); 80205f0: 6839 ldr r1, [r7, #0] 80205f2: 6878 ldr r0, [r7, #4] 80205f4: f000 f8c2 bl 802077c LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed); 80205f8: 4b10 ldr r3, [pc, #64] ; (802063c ) 80205fa: 881b ldrh r3, [r3, #0] 80205fc: 8bfa ldrh r2, [r7, #30] 80205fe: 429a cmp r2, r3 8020600: d905 bls.n 802060e 8020602: 4b09 ldr r3, [pc, #36] ; (8020628 ) 8020604: 22d2 movs r2, #210 ; 0xd2 8020606: 490e ldr r1, [pc, #56] ; (8020640 ) 8020608: 4809 ldr r0, [pc, #36] ; (8020630 ) 802060a: f001 f9bd bl 8021988 ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed); 802060e: 4b0b ldr r3, [pc, #44] ; (802063c ) 8020610: 881a ldrh r2, [r3, #0] 8020612: 8bfb ldrh r3, [r7, #30] 8020614: 1ad3 subs r3, r2, r3 8020616: b29a uxth r2, r3 8020618: 4b08 ldr r3, [pc, #32] ; (802063c ) 802061a: 801a strh r2, [r3, #0] return pbufs_freed; 802061c: 8bfb ldrh r3, [r7, #30] } 802061e: 4618 mov r0, r3 8020620: 3720 adds r7, #32 8020622: 46bd mov sp, r7 8020624: bd80 pop {r7, pc} 8020626: bf00 nop 8020628: 08026884 .word 0x08026884 802062c: 080268c0 .word 0x080268c0 8020630: 080268cc .word 0x080268cc 8020634: 080268f4 .word 0x080268f4 8020638: 08026908 .word 0x08026908 802063c: 2401a5dc .word 0x2401a5dc 8020640: 08026928 .word 0x08026928 08020644 : * (used for freeing other datagrams if not enough space) * @return the number of pbufs freed */ static int ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed) { 8020644: b580 push {r7, lr} 8020646: b08a sub sp, #40 ; 0x28 8020648: af00 add r7, sp, #0 802064a: 6078 str r0, [r7, #4] 802064c: 6039 str r1, [r7, #0] /* @todo Can't we simply remove the last datagram in the * linked list behind reassdatagrams? */ struct ip_reassdata *r, *oldest, *prev, *oldest_prev; int pbufs_freed = 0, pbufs_freed_current; 802064e: 2300 movs r3, #0 8020650: 617b str r3, [r7, #20] int other_datagrams; /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs, * but don't free the datagram that 'fraghdr' belongs to! */ do { oldest = NULL; 8020652: 2300 movs r3, #0 8020654: 623b str r3, [r7, #32] prev = NULL; 8020656: 2300 movs r3, #0 8020658: 61fb str r3, [r7, #28] oldest_prev = NULL; 802065a: 2300 movs r3, #0 802065c: 61bb str r3, [r7, #24] other_datagrams = 0; 802065e: 2300 movs r3, #0 8020660: 613b str r3, [r7, #16] r = reassdatagrams; 8020662: 4b28 ldr r3, [pc, #160] ; (8020704 ) 8020664: 681b ldr r3, [r3, #0] 8020666: 627b str r3, [r7, #36] ; 0x24 while (r != NULL) { 8020668: e030 b.n 80206cc if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) { 802066a: 6a7b ldr r3, [r7, #36] ; 0x24 802066c: 695a ldr r2, [r3, #20] 802066e: 687b ldr r3, [r7, #4] 8020670: 68db ldr r3, [r3, #12] 8020672: 429a cmp r2, r3 8020674: d10c bne.n 8020690 8020676: 6a7b ldr r3, [r7, #36] ; 0x24 8020678: 699a ldr r2, [r3, #24] 802067a: 687b ldr r3, [r7, #4] 802067c: 691b ldr r3, [r3, #16] 802067e: 429a cmp r2, r3 8020680: d106 bne.n 8020690 8020682: 6a7b ldr r3, [r7, #36] ; 0x24 8020684: 899a ldrh r2, [r3, #12] 8020686: 687b ldr r3, [r7, #4] 8020688: 889b ldrh r3, [r3, #4] 802068a: b29b uxth r3, r3 802068c: 429a cmp r2, r3 802068e: d014 beq.n 80206ba /* Not the same datagram as fraghdr */ other_datagrams++; 8020690: 693b ldr r3, [r7, #16] 8020692: 3301 adds r3, #1 8020694: 613b str r3, [r7, #16] if (oldest == NULL) { 8020696: 6a3b ldr r3, [r7, #32] 8020698: 2b00 cmp r3, #0 802069a: d104 bne.n 80206a6 oldest = r; 802069c: 6a7b ldr r3, [r7, #36] ; 0x24 802069e: 623b str r3, [r7, #32] oldest_prev = prev; 80206a0: 69fb ldr r3, [r7, #28] 80206a2: 61bb str r3, [r7, #24] 80206a4: e009 b.n 80206ba } else if (r->timer <= oldest->timer) { 80206a6: 6a7b ldr r3, [r7, #36] ; 0x24 80206a8: 7fda ldrb r2, [r3, #31] 80206aa: 6a3b ldr r3, [r7, #32] 80206ac: 7fdb ldrb r3, [r3, #31] 80206ae: 429a cmp r2, r3 80206b0: d803 bhi.n 80206ba /* older than the previous oldest */ oldest = r; 80206b2: 6a7b ldr r3, [r7, #36] ; 0x24 80206b4: 623b str r3, [r7, #32] oldest_prev = prev; 80206b6: 69fb ldr r3, [r7, #28] 80206b8: 61bb str r3, [r7, #24] } } if (r->next != NULL) { 80206ba: 6a7b ldr r3, [r7, #36] ; 0x24 80206bc: 681b ldr r3, [r3, #0] 80206be: 2b00 cmp r3, #0 80206c0: d001 beq.n 80206c6 prev = r; 80206c2: 6a7b ldr r3, [r7, #36] ; 0x24 80206c4: 61fb str r3, [r7, #28] } r = r->next; 80206c6: 6a7b ldr r3, [r7, #36] ; 0x24 80206c8: 681b ldr r3, [r3, #0] 80206ca: 627b str r3, [r7, #36] ; 0x24 while (r != NULL) { 80206cc: 6a7b ldr r3, [r7, #36] ; 0x24 80206ce: 2b00 cmp r3, #0 80206d0: d1cb bne.n 802066a } if (oldest != NULL) { 80206d2: 6a3b ldr r3, [r7, #32] 80206d4: 2b00 cmp r3, #0 80206d6: d008 beq.n 80206ea pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev); 80206d8: 69b9 ldr r1, [r7, #24] 80206da: 6a38 ldr r0, [r7, #32] 80206dc: f7ff ff0e bl 80204fc 80206e0: 60f8 str r0, [r7, #12] pbufs_freed += pbufs_freed_current; 80206e2: 697a ldr r2, [r7, #20] 80206e4: 68fb ldr r3, [r7, #12] 80206e6: 4413 add r3, r2 80206e8: 617b str r3, [r7, #20] } } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1)); 80206ea: 697a ldr r2, [r7, #20] 80206ec: 683b ldr r3, [r7, #0] 80206ee: 429a cmp r2, r3 80206f0: da02 bge.n 80206f8 80206f2: 693b ldr r3, [r7, #16] 80206f4: 2b01 cmp r3, #1 80206f6: dcac bgt.n 8020652 return pbufs_freed; 80206f8: 697b ldr r3, [r7, #20] } 80206fa: 4618 mov r0, r3 80206fc: 3728 adds r7, #40 ; 0x28 80206fe: 46bd mov sp, r7 8020700: bd80 pop {r7, pc} 8020702: bf00 nop 8020704: 2401a5d8 .word 0x2401a5d8 08020708 : * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space) * @return A pointer to the queue location into which the fragment was enqueued */ static struct ip_reassdata * ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen) { 8020708: b580 push {r7, lr} 802070a: b084 sub sp, #16 802070c: af00 add r7, sp, #0 802070e: 6078 str r0, [r7, #4] 8020710: 6039 str r1, [r7, #0] #if ! IP_REASS_FREE_OLDEST LWIP_UNUSED_ARG(clen); #endif /* No matching previous fragment found, allocate a new reassdata struct */ ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); 8020712: 2004 movs r0, #4 8020714: f7f6 f9dc bl 8016ad0 8020718: 60f8 str r0, [r7, #12] if (ipr == NULL) { 802071a: 68fb ldr r3, [r7, #12] 802071c: 2b00 cmp r3, #0 802071e: d110 bne.n 8020742 #if IP_REASS_FREE_OLDEST if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) { 8020720: 6839 ldr r1, [r7, #0] 8020722: 6878 ldr r0, [r7, #4] 8020724: f7ff ff8e bl 8020644 8020728: 4602 mov r2, r0 802072a: 683b ldr r3, [r7, #0] 802072c: 4293 cmp r3, r2 802072e: dc03 bgt.n 8020738 ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); 8020730: 2004 movs r0, #4 8020732: f7f6 f9cd bl 8016ad0 8020736: 60f8 str r0, [r7, #12] } if (ipr == NULL) 8020738: 68fb ldr r3, [r7, #12] 802073a: 2b00 cmp r3, #0 802073c: d101 bne.n 8020742 #endif /* IP_REASS_FREE_OLDEST */ { IPFRAG_STATS_INC(ip_frag.memerr); LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n")); return NULL; 802073e: 2300 movs r3, #0 8020740: e016 b.n 8020770 } } memset(ipr, 0, sizeof(struct ip_reassdata)); 8020742: 2220 movs r2, #32 8020744: 2100 movs r1, #0 8020746: 68f8 ldr r0, [r7, #12] 8020748: f001 faca bl 8021ce0 ipr->timer = IP_REASS_MAXAGE; 802074c: 68fb ldr r3, [r7, #12] 802074e: 220f movs r2, #15 8020750: 77da strb r2, [r3, #31] /* enqueue the new structure to the front of the list */ ipr->next = reassdatagrams; 8020752: 4b09 ldr r3, [pc, #36] ; (8020778 ) 8020754: 681a ldr r2, [r3, #0] 8020756: 68fb ldr r3, [r7, #12] 8020758: 601a str r2, [r3, #0] reassdatagrams = ipr; 802075a: 4a07 ldr r2, [pc, #28] ; (8020778 ) 802075c: 68fb ldr r3, [r7, #12] 802075e: 6013 str r3, [r2, #0] /* copy the ip header for later tests and input */ /* @todo: no ip options supported? */ SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN); 8020760: 68fb ldr r3, [r7, #12] 8020762: 3308 adds r3, #8 8020764: 2214 movs r2, #20 8020766: 6879 ldr r1, [r7, #4] 8020768: 4618 mov r0, r3 802076a: f001 fb3c bl 8021de6 return ipr; 802076e: 68fb ldr r3, [r7, #12] } 8020770: 4618 mov r0, r3 8020772: 3710 adds r7, #16 8020774: 46bd mov sp, r7 8020776: bd80 pop {r7, pc} 8020778: 2401a5d8 .word 0x2401a5d8 0802077c : * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs. * @param ipr points to the queue entry to dequeue */ static void ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) { 802077c: b580 push {r7, lr} 802077e: b082 sub sp, #8 8020780: af00 add r7, sp, #0 8020782: 6078 str r0, [r7, #4] 8020784: 6039 str r1, [r7, #0] /* dequeue the reass struct */ if (reassdatagrams == ipr) { 8020786: 4b10 ldr r3, [pc, #64] ; (80207c8 ) 8020788: 681b ldr r3, [r3, #0] 802078a: 687a ldr r2, [r7, #4] 802078c: 429a cmp r2, r3 802078e: d104 bne.n 802079a /* it was the first in the list */ reassdatagrams = ipr->next; 8020790: 687b ldr r3, [r7, #4] 8020792: 681b ldr r3, [r3, #0] 8020794: 4a0c ldr r2, [pc, #48] ; (80207c8 ) 8020796: 6013 str r3, [r2, #0] 8020798: e00d b.n 80207b6 } else { /* it wasn't the first, so it must have a valid 'prev' */ LWIP_ASSERT("sanity check linked list", prev != NULL); 802079a: 683b ldr r3, [r7, #0] 802079c: 2b00 cmp r3, #0 802079e: d106 bne.n 80207ae 80207a0: 4b0a ldr r3, [pc, #40] ; (80207cc ) 80207a2: f240 1245 movw r2, #325 ; 0x145 80207a6: 490a ldr r1, [pc, #40] ; (80207d0 ) 80207a8: 480a ldr r0, [pc, #40] ; (80207d4 ) 80207aa: f001 f8ed bl 8021988 prev->next = ipr->next; 80207ae: 687b ldr r3, [r7, #4] 80207b0: 681a ldr r2, [r3, #0] 80207b2: 683b ldr r3, [r7, #0] 80207b4: 601a str r2, [r3, #0] } /* now we can free the ip_reassdata struct */ memp_free(MEMP_REASSDATA, ipr); 80207b6: 6879 ldr r1, [r7, #4] 80207b8: 2004 movs r0, #4 80207ba: f7f6 f9ff bl 8016bbc } 80207be: bf00 nop 80207c0: 3708 adds r7, #8 80207c2: 46bd mov sp, r7 80207c4: bd80 pop {r7, pc} 80207c6: bf00 nop 80207c8: 2401a5d8 .word 0x2401a5d8 80207cc: 08026884 .word 0x08026884 80207d0: 0802694c .word 0x0802694c 80207d4: 080268cc .word 0x080268cc 080207d8 : * @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet) * @return see IP_REASS_VALIDATE_* defines */ static int ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last) { 80207d8: b580 push {r7, lr} 80207da: b08c sub sp, #48 ; 0x30 80207dc: af00 add r7, sp, #0 80207de: 60f8 str r0, [r7, #12] 80207e0: 60b9 str r1, [r7, #8] 80207e2: 607a str r2, [r7, #4] struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL; 80207e4: 2300 movs r3, #0 80207e6: 62bb str r3, [r7, #40] ; 0x28 struct pbuf *q; u16_t offset, len; u8_t hlen; struct ip_hdr *fraghdr; int valid = 1; 80207e8: 2301 movs r3, #1 80207ea: 623b str r3, [r7, #32] /* Extract length and fragment offset from current fragment */ fraghdr = (struct ip_hdr *)new_p->payload; 80207ec: 68bb ldr r3, [r7, #8] 80207ee: 685b ldr r3, [r3, #4] 80207f0: 61fb str r3, [r7, #28] len = lwip_ntohs(IPH_LEN(fraghdr)); 80207f2: 69fb ldr r3, [r7, #28] 80207f4: 885b ldrh r3, [r3, #2] 80207f6: b29b uxth r3, r3 80207f8: 4618 mov r0, r3 80207fa: f7f5 fba1 bl 8015f40 80207fe: 4603 mov r3, r0 8020800: 837b strh r3, [r7, #26] hlen = IPH_HL_BYTES(fraghdr); 8020802: 69fb ldr r3, [r7, #28] 8020804: 781b ldrb r3, [r3, #0] 8020806: f003 030f and.w r3, r3, #15 802080a: b2db uxtb r3, r3 802080c: 009b lsls r3, r3, #2 802080e: 767b strb r3, [r7, #25] if (hlen > len) { 8020810: 7e7b ldrb r3, [r7, #25] 8020812: b29b uxth r3, r3 8020814: 8b7a ldrh r2, [r7, #26] 8020816: 429a cmp r2, r3 8020818: d202 bcs.n 8020820 /* invalid datagram */ return IP_REASS_VALIDATE_PBUF_DROPPED; 802081a: f04f 33ff mov.w r3, #4294967295 802081e: e135 b.n 8020a8c } len = (u16_t)(len - hlen); 8020820: 7e7b ldrb r3, [r7, #25] 8020822: b29b uxth r3, r3 8020824: 8b7a ldrh r2, [r7, #26] 8020826: 1ad3 subs r3, r2, r3 8020828: 837b strh r3, [r7, #26] offset = IPH_OFFSET_BYTES(fraghdr); 802082a: 69fb ldr r3, [r7, #28] 802082c: 88db ldrh r3, [r3, #6] 802082e: b29b uxth r3, r3 8020830: 4618 mov r0, r3 8020832: f7f5 fb85 bl 8015f40 8020836: 4603 mov r3, r0 8020838: f3c3 030c ubfx r3, r3, #0, #13 802083c: b29b uxth r3, r3 802083e: 00db lsls r3, r3, #3 8020840: 82fb strh r3, [r7, #22] /* overwrite the fragment's ip header from the pbuf with our helper struct, * and setup the embedded helper structure. */ /* make sure the struct ip_reass_helper fits into the IP header */ LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN", sizeof(struct ip_reass_helper) <= IP_HLEN); iprh = (struct ip_reass_helper *)new_p->payload; 8020842: 68bb ldr r3, [r7, #8] 8020844: 685b ldr r3, [r3, #4] 8020846: 62fb str r3, [r7, #44] ; 0x2c iprh->next_pbuf = NULL; 8020848: 6afb ldr r3, [r7, #44] ; 0x2c 802084a: 2200 movs r2, #0 802084c: 701a strb r2, [r3, #0] 802084e: 2200 movs r2, #0 8020850: 705a strb r2, [r3, #1] 8020852: 2200 movs r2, #0 8020854: 709a strb r2, [r3, #2] 8020856: 2200 movs r2, #0 8020858: 70da strb r2, [r3, #3] iprh->start = offset; 802085a: 6afb ldr r3, [r7, #44] ; 0x2c 802085c: 8afa ldrh r2, [r7, #22] 802085e: 809a strh r2, [r3, #4] iprh->end = (u16_t)(offset + len); 8020860: 8afa ldrh r2, [r7, #22] 8020862: 8b7b ldrh r3, [r7, #26] 8020864: 4413 add r3, r2 8020866: b29a uxth r2, r3 8020868: 6afb ldr r3, [r7, #44] ; 0x2c 802086a: 80da strh r2, [r3, #6] if (iprh->end < offset) { 802086c: 6afb ldr r3, [r7, #44] ; 0x2c 802086e: 88db ldrh r3, [r3, #6] 8020870: b29b uxth r3, r3 8020872: 8afa ldrh r2, [r7, #22] 8020874: 429a cmp r2, r3 8020876: d902 bls.n 802087e /* u16_t overflow, cannot handle this */ return IP_REASS_VALIDATE_PBUF_DROPPED; 8020878: f04f 33ff mov.w r3, #4294967295 802087c: e106 b.n 8020a8c } /* Iterate through until we either get to the end of the list (append), * or we find one with a larger offset (insert). */ for (q = ipr->p; q != NULL;) { 802087e: 68fb ldr r3, [r7, #12] 8020880: 685b ldr r3, [r3, #4] 8020882: 627b str r3, [r7, #36] ; 0x24 8020884: e068 b.n 8020958 iprh_tmp = (struct ip_reass_helper *)q->payload; 8020886: 6a7b ldr r3, [r7, #36] ; 0x24 8020888: 685b ldr r3, [r3, #4] 802088a: 613b str r3, [r7, #16] if (iprh->start < iprh_tmp->start) { 802088c: 6afb ldr r3, [r7, #44] ; 0x2c 802088e: 889b ldrh r3, [r3, #4] 8020890: b29a uxth r2, r3 8020892: 693b ldr r3, [r7, #16] 8020894: 889b ldrh r3, [r3, #4] 8020896: b29b uxth r3, r3 8020898: 429a cmp r2, r3 802089a: d235 bcs.n 8020908 /* the new pbuf should be inserted before this */ iprh->next_pbuf = q; 802089c: 6afb ldr r3, [r7, #44] ; 0x2c 802089e: 6a7a ldr r2, [r7, #36] ; 0x24 80208a0: 601a str r2, [r3, #0] if (iprh_prev != NULL) { 80208a2: 6abb ldr r3, [r7, #40] ; 0x28 80208a4: 2b00 cmp r3, #0 80208a6: d020 beq.n 80208ea /* not the fragment with the lowest offset */ #if IP_REASS_CHECK_OVERLAP if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) { 80208a8: 6afb ldr r3, [r7, #44] ; 0x2c 80208aa: 889b ldrh r3, [r3, #4] 80208ac: b29a uxth r2, r3 80208ae: 6abb ldr r3, [r7, #40] ; 0x28 80208b0: 88db ldrh r3, [r3, #6] 80208b2: b29b uxth r3, r3 80208b4: 429a cmp r2, r3 80208b6: d307 bcc.n 80208c8 80208b8: 6afb ldr r3, [r7, #44] ; 0x2c 80208ba: 88db ldrh r3, [r3, #6] 80208bc: b29a uxth r2, r3 80208be: 693b ldr r3, [r7, #16] 80208c0: 889b ldrh r3, [r3, #4] 80208c2: b29b uxth r3, r3 80208c4: 429a cmp r2, r3 80208c6: d902 bls.n 80208ce /* fragment overlaps with previous or following, throw away */ return IP_REASS_VALIDATE_PBUF_DROPPED; 80208c8: f04f 33ff mov.w r3, #4294967295 80208cc: e0de b.n 8020a8c } #endif /* IP_REASS_CHECK_OVERLAP */ iprh_prev->next_pbuf = new_p; 80208ce: 6abb ldr r3, [r7, #40] ; 0x28 80208d0: 68ba ldr r2, [r7, #8] 80208d2: 601a str r2, [r3, #0] if (iprh_prev->end != iprh->start) { 80208d4: 6abb ldr r3, [r7, #40] ; 0x28 80208d6: 88db ldrh r3, [r3, #6] 80208d8: b29a uxth r2, r3 80208da: 6afb ldr r3, [r7, #44] ; 0x2c 80208dc: 889b ldrh r3, [r3, #4] 80208de: b29b uxth r3, r3 80208e0: 429a cmp r2, r3 80208e2: d03d beq.n 8020960 /* There is a fragment missing between the current * and the previous fragment */ valid = 0; 80208e4: 2300 movs r3, #0 80208e6: 623b str r3, [r7, #32] } #endif /* IP_REASS_CHECK_OVERLAP */ /* fragment with the lowest offset */ ipr->p = new_p; } break; 80208e8: e03a b.n 8020960 if (iprh->end > iprh_tmp->start) { 80208ea: 6afb ldr r3, [r7, #44] ; 0x2c 80208ec: 88db ldrh r3, [r3, #6] 80208ee: b29a uxth r2, r3 80208f0: 693b ldr r3, [r7, #16] 80208f2: 889b ldrh r3, [r3, #4] 80208f4: b29b uxth r3, r3 80208f6: 429a cmp r2, r3 80208f8: d902 bls.n 8020900 return IP_REASS_VALIDATE_PBUF_DROPPED; 80208fa: f04f 33ff mov.w r3, #4294967295 80208fe: e0c5 b.n 8020a8c ipr->p = new_p; 8020900: 68fb ldr r3, [r7, #12] 8020902: 68ba ldr r2, [r7, #8] 8020904: 605a str r2, [r3, #4] break; 8020906: e02b b.n 8020960 } else if (iprh->start == iprh_tmp->start) { 8020908: 6afb ldr r3, [r7, #44] ; 0x2c 802090a: 889b ldrh r3, [r3, #4] 802090c: b29a uxth r2, r3 802090e: 693b ldr r3, [r7, #16] 8020910: 889b ldrh r3, [r3, #4] 8020912: b29b uxth r3, r3 8020914: 429a cmp r2, r3 8020916: d102 bne.n 802091e /* received the same datagram twice: no need to keep the datagram */ return IP_REASS_VALIDATE_PBUF_DROPPED; 8020918: f04f 33ff mov.w r3, #4294967295 802091c: e0b6 b.n 8020a8c #if IP_REASS_CHECK_OVERLAP } else if (iprh->start < iprh_tmp->end) { 802091e: 6afb ldr r3, [r7, #44] ; 0x2c 8020920: 889b ldrh r3, [r3, #4] 8020922: b29a uxth r2, r3 8020924: 693b ldr r3, [r7, #16] 8020926: 88db ldrh r3, [r3, #6] 8020928: b29b uxth r3, r3 802092a: 429a cmp r2, r3 802092c: d202 bcs.n 8020934 /* overlap: no need to keep the new datagram */ return IP_REASS_VALIDATE_PBUF_DROPPED; 802092e: f04f 33ff mov.w r3, #4294967295 8020932: e0ab b.n 8020a8c #endif /* IP_REASS_CHECK_OVERLAP */ } else { /* Check if the fragments received so far have no holes. */ if (iprh_prev != NULL) { 8020934: 6abb ldr r3, [r7, #40] ; 0x28 8020936: 2b00 cmp r3, #0 8020938: d009 beq.n 802094e if (iprh_prev->end != iprh_tmp->start) { 802093a: 6abb ldr r3, [r7, #40] ; 0x28 802093c: 88db ldrh r3, [r3, #6] 802093e: b29a uxth r2, r3 8020940: 693b ldr r3, [r7, #16] 8020942: 889b ldrh r3, [r3, #4] 8020944: b29b uxth r3, r3 8020946: 429a cmp r2, r3 8020948: d001 beq.n 802094e /* There is a fragment missing between the current * and the previous fragment */ valid = 0; 802094a: 2300 movs r3, #0 802094c: 623b str r3, [r7, #32] } } } q = iprh_tmp->next_pbuf; 802094e: 693b ldr r3, [r7, #16] 8020950: 681b ldr r3, [r3, #0] 8020952: 627b str r3, [r7, #36] ; 0x24 iprh_prev = iprh_tmp; 8020954: 693b ldr r3, [r7, #16] 8020956: 62bb str r3, [r7, #40] ; 0x28 for (q = ipr->p; q != NULL;) { 8020958: 6a7b ldr r3, [r7, #36] ; 0x24 802095a: 2b00 cmp r3, #0 802095c: d193 bne.n 8020886 802095e: e000 b.n 8020962 break; 8020960: bf00 nop } /* If q is NULL, then we made it to the end of the list. Determine what to do now */ if (q == NULL) { 8020962: 6a7b ldr r3, [r7, #36] ; 0x24 8020964: 2b00 cmp r3, #0 8020966: d12d bne.n 80209c4 if (iprh_prev != NULL) { 8020968: 6abb ldr r3, [r7, #40] ; 0x28 802096a: 2b00 cmp r3, #0 802096c: d01c beq.n 80209a8 /* this is (for now), the fragment with the highest offset: * chain it to the last fragment */ #if IP_REASS_CHECK_OVERLAP LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start); 802096e: 6abb ldr r3, [r7, #40] ; 0x28 8020970: 88db ldrh r3, [r3, #6] 8020972: b29a uxth r2, r3 8020974: 6afb ldr r3, [r7, #44] ; 0x2c 8020976: 889b ldrh r3, [r3, #4] 8020978: b29b uxth r3, r3 802097a: 429a cmp r2, r3 802097c: d906 bls.n 802098c 802097e: 4b45 ldr r3, [pc, #276] ; (8020a94 ) 8020980: f44f 72db mov.w r2, #438 ; 0x1b6 8020984: 4944 ldr r1, [pc, #272] ; (8020a98 ) 8020986: 4845 ldr r0, [pc, #276] ; (8020a9c ) 8020988: f000 fffe bl 8021988 #endif /* IP_REASS_CHECK_OVERLAP */ iprh_prev->next_pbuf = new_p; 802098c: 6abb ldr r3, [r7, #40] ; 0x28 802098e: 68ba ldr r2, [r7, #8] 8020990: 601a str r2, [r3, #0] if (iprh_prev->end != iprh->start) { 8020992: 6abb ldr r3, [r7, #40] ; 0x28 8020994: 88db ldrh r3, [r3, #6] 8020996: b29a uxth r2, r3 8020998: 6afb ldr r3, [r7, #44] ; 0x2c 802099a: 889b ldrh r3, [r3, #4] 802099c: b29b uxth r3, r3 802099e: 429a cmp r2, r3 80209a0: d010 beq.n 80209c4 valid = 0; 80209a2: 2300 movs r3, #0 80209a4: 623b str r3, [r7, #32] 80209a6: e00d b.n 80209c4 } } else { #if IP_REASS_CHECK_OVERLAP LWIP_ASSERT("no previous fragment, this must be the first fragment!", 80209a8: 68fb ldr r3, [r7, #12] 80209aa: 685b ldr r3, [r3, #4] 80209ac: 2b00 cmp r3, #0 80209ae: d006 beq.n 80209be 80209b0: 4b38 ldr r3, [pc, #224] ; (8020a94 ) 80209b2: f44f 72df mov.w r2, #446 ; 0x1be 80209b6: 493a ldr r1, [pc, #232] ; (8020aa0 ) 80209b8: 4838 ldr r0, [pc, #224] ; (8020a9c ) 80209ba: f000 ffe5 bl 8021988 ipr->p == NULL); #endif /* IP_REASS_CHECK_OVERLAP */ /* this is the first fragment we ever received for this ip datagram */ ipr->p = new_p; 80209be: 68fb ldr r3, [r7, #12] 80209c0: 68ba ldr r2, [r7, #8] 80209c2: 605a str r2, [r3, #4] } } /* At this point, the validation part begins: */ /* If we already received the last fragment */ if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) { 80209c4: 687b ldr r3, [r7, #4] 80209c6: 2b00 cmp r3, #0 80209c8: d105 bne.n 80209d6 80209ca: 68fb ldr r3, [r7, #12] 80209cc: 7f9b ldrb r3, [r3, #30] 80209ce: f003 0301 and.w r3, r3, #1 80209d2: 2b00 cmp r3, #0 80209d4: d059 beq.n 8020a8a /* and had no holes so far */ if (valid) { 80209d6: 6a3b ldr r3, [r7, #32] 80209d8: 2b00 cmp r3, #0 80209da: d04f beq.n 8020a7c /* then check if the rest of the fragments is here */ /* Check if the queue starts with the first datagram */ if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) { 80209dc: 68fb ldr r3, [r7, #12] 80209de: 685b ldr r3, [r3, #4] 80209e0: 2b00 cmp r3, #0 80209e2: d006 beq.n 80209f2 80209e4: 68fb ldr r3, [r7, #12] 80209e6: 685b ldr r3, [r3, #4] 80209e8: 685b ldr r3, [r3, #4] 80209ea: 889b ldrh r3, [r3, #4] 80209ec: b29b uxth r3, r3 80209ee: 2b00 cmp r3, #0 80209f0: d002 beq.n 80209f8 valid = 0; 80209f2: 2300 movs r3, #0 80209f4: 623b str r3, [r7, #32] 80209f6: e041 b.n 8020a7c } else { /* and check that there are no holes after this datagram */ iprh_prev = iprh; 80209f8: 6afb ldr r3, [r7, #44] ; 0x2c 80209fa: 62bb str r3, [r7, #40] ; 0x28 q = iprh->next_pbuf; 80209fc: 6afb ldr r3, [r7, #44] ; 0x2c 80209fe: 681b ldr r3, [r3, #0] 8020a00: 627b str r3, [r7, #36] ; 0x24 while (q != NULL) { 8020a02: e012 b.n 8020a2a iprh = (struct ip_reass_helper *)q->payload; 8020a04: 6a7b ldr r3, [r7, #36] ; 0x24 8020a06: 685b ldr r3, [r3, #4] 8020a08: 62fb str r3, [r7, #44] ; 0x2c if (iprh_prev->end != iprh->start) { 8020a0a: 6abb ldr r3, [r7, #40] ; 0x28 8020a0c: 88db ldrh r3, [r3, #6] 8020a0e: b29a uxth r2, r3 8020a10: 6afb ldr r3, [r7, #44] ; 0x2c 8020a12: 889b ldrh r3, [r3, #4] 8020a14: b29b uxth r3, r3 8020a16: 429a cmp r2, r3 8020a18: d002 beq.n 8020a20 valid = 0; 8020a1a: 2300 movs r3, #0 8020a1c: 623b str r3, [r7, #32] break; 8020a1e: e007 b.n 8020a30 } iprh_prev = iprh; 8020a20: 6afb ldr r3, [r7, #44] ; 0x2c 8020a22: 62bb str r3, [r7, #40] ; 0x28 q = iprh->next_pbuf; 8020a24: 6afb ldr r3, [r7, #44] ; 0x2c 8020a26: 681b ldr r3, [r3, #0] 8020a28: 627b str r3, [r7, #36] ; 0x24 while (q != NULL) { 8020a2a: 6a7b ldr r3, [r7, #36] ; 0x24 8020a2c: 2b00 cmp r3, #0 8020a2e: d1e9 bne.n 8020a04 } /* if still valid, all fragments are received * (because to the MF==0 already arrived */ if (valid) { 8020a30: 6a3b ldr r3, [r7, #32] 8020a32: 2b00 cmp r3, #0 8020a34: d022 beq.n 8020a7c LWIP_ASSERT("sanity check", ipr->p != NULL); 8020a36: 68fb ldr r3, [r7, #12] 8020a38: 685b ldr r3, [r3, #4] 8020a3a: 2b00 cmp r3, #0 8020a3c: d106 bne.n 8020a4c 8020a3e: 4b15 ldr r3, [pc, #84] ; (8020a94 ) 8020a40: f240 12df movw r2, #479 ; 0x1df 8020a44: 4917 ldr r1, [pc, #92] ; (8020aa4 ) 8020a46: 4815 ldr r0, [pc, #84] ; (8020a9c ) 8020a48: f000 ff9e bl 8021988 LWIP_ASSERT("sanity check", 8020a4c: 68fb ldr r3, [r7, #12] 8020a4e: 685b ldr r3, [r3, #4] 8020a50: 685b ldr r3, [r3, #4] 8020a52: 6afa ldr r2, [r7, #44] ; 0x2c 8020a54: 429a cmp r2, r3 8020a56: d106 bne.n 8020a66 8020a58: 4b0e ldr r3, [pc, #56] ; (8020a94 ) 8020a5a: f44f 72f0 mov.w r2, #480 ; 0x1e0 8020a5e: 4911 ldr r1, [pc, #68] ; (8020aa4 ) 8020a60: 480e ldr r0, [pc, #56] ; (8020a9c ) 8020a62: f000 ff91 bl 8021988 ((struct ip_reass_helper *)ipr->p->payload) != iprh); LWIP_ASSERT("validate_datagram:next_pbuf!=NULL", 8020a66: 6afb ldr r3, [r7, #44] ; 0x2c 8020a68: 681b ldr r3, [r3, #0] 8020a6a: 2b00 cmp r3, #0 8020a6c: d006 beq.n 8020a7c 8020a6e: 4b09 ldr r3, [pc, #36] ; (8020a94 ) 8020a70: f44f 72f1 mov.w r2, #482 ; 0x1e2 8020a74: 490c ldr r1, [pc, #48] ; (8020aa8 ) 8020a76: 4809 ldr r0, [pc, #36] ; (8020a9c ) 8020a78: f000 ff86 bl 8021988 } } /* If valid is 0 here, there are some fragments missing in the middle * (since MF == 0 has already arrived). Such datagrams simply time out if * no more fragments are received... */ return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED; 8020a7c: 6a3b ldr r3, [r7, #32] 8020a7e: 2b00 cmp r3, #0 8020a80: bf14 ite ne 8020a82: 2301 movne r3, #1 8020a84: 2300 moveq r3, #0 8020a86: b2db uxtb r3, r3 8020a88: e000 b.n 8020a8c } /* If we come here, not all fragments were received, yet! */ return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */ 8020a8a: 2300 movs r3, #0 } 8020a8c: 4618 mov r0, r3 8020a8e: 3730 adds r7, #48 ; 0x30 8020a90: 46bd mov sp, r7 8020a92: bd80 pop {r7, pc} 8020a94: 08026884 .word 0x08026884 8020a98: 08026968 .word 0x08026968 8020a9c: 080268cc .word 0x080268cc 8020aa0: 08026988 .word 0x08026988 8020aa4: 080269c0 .word 0x080269c0 8020aa8: 080269d0 .word 0x080269d0 08020aac : * @param p points to a pbuf chain of the fragment * @return NULL if reassembly is incomplete, ? otherwise */ struct pbuf * ip4_reass(struct pbuf *p) { 8020aac: b580 push {r7, lr} 8020aae: b08e sub sp, #56 ; 0x38 8020ab0: af00 add r7, sp, #0 8020ab2: 6078 str r0, [r7, #4] int is_last; IPFRAG_STATS_INC(ip_frag.recv); MIB2_STATS_INC(mib2.ipreasmreqds); fraghdr = (struct ip_hdr *)p->payload; 8020ab4: 687b ldr r3, [r7, #4] 8020ab6: 685b ldr r3, [r3, #4] 8020ab8: 62bb str r3, [r7, #40] ; 0x28 if (IPH_HL_BYTES(fraghdr) != IP_HLEN) { 8020aba: 6abb ldr r3, [r7, #40] ; 0x28 8020abc: 781b ldrb r3, [r3, #0] 8020abe: f003 030f and.w r3, r3, #15 8020ac2: b2db uxtb r3, r3 8020ac4: 009b lsls r3, r3, #2 8020ac6: b2db uxtb r3, r3 8020ac8: 2b14 cmp r3, #20 8020aca: f040 8171 bne.w 8020db0 LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n")); IPFRAG_STATS_INC(ip_frag.err); goto nullreturn; } offset = IPH_OFFSET_BYTES(fraghdr); 8020ace: 6abb ldr r3, [r7, #40] ; 0x28 8020ad0: 88db ldrh r3, [r3, #6] 8020ad2: b29b uxth r3, r3 8020ad4: 4618 mov r0, r3 8020ad6: f7f5 fa33 bl 8015f40 8020ada: 4603 mov r3, r0 8020adc: f3c3 030c ubfx r3, r3, #0, #13 8020ae0: b29b uxth r3, r3 8020ae2: 00db lsls r3, r3, #3 8020ae4: 84fb strh r3, [r7, #38] ; 0x26 len = lwip_ntohs(IPH_LEN(fraghdr)); 8020ae6: 6abb ldr r3, [r7, #40] ; 0x28 8020ae8: 885b ldrh r3, [r3, #2] 8020aea: b29b uxth r3, r3 8020aec: 4618 mov r0, r3 8020aee: f7f5 fa27 bl 8015f40 8020af2: 4603 mov r3, r0 8020af4: 84bb strh r3, [r7, #36] ; 0x24 hlen = IPH_HL_BYTES(fraghdr); 8020af6: 6abb ldr r3, [r7, #40] ; 0x28 8020af8: 781b ldrb r3, [r3, #0] 8020afa: f003 030f and.w r3, r3, #15 8020afe: b2db uxtb r3, r3 8020b00: 009b lsls r3, r3, #2 8020b02: f887 3023 strb.w r3, [r7, #35] ; 0x23 if (hlen > len) { 8020b06: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 8020b0a: b29b uxth r3, r3 8020b0c: 8cba ldrh r2, [r7, #36] ; 0x24 8020b0e: 429a cmp r2, r3 8020b10: f0c0 8150 bcc.w 8020db4 /* invalid datagram */ goto nullreturn; } len = (u16_t)(len - hlen); 8020b14: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 8020b18: b29b uxth r3, r3 8020b1a: 8cba ldrh r2, [r7, #36] ; 0x24 8020b1c: 1ad3 subs r3, r2, r3 8020b1e: 84bb strh r3, [r7, #36] ; 0x24 /* Check if we are allowed to enqueue more datagrams. */ clen = pbuf_clen(p); 8020b20: 6878 ldr r0, [r7, #4] 8020b22: f7f7 f877 bl 8017c14 8020b26: 4603 mov r3, r0 8020b28: 843b strh r3, [r7, #32] if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) { 8020b2a: 4b8c ldr r3, [pc, #560] ; (8020d5c ) 8020b2c: 881b ldrh r3, [r3, #0] 8020b2e: 461a mov r2, r3 8020b30: 8c3b ldrh r3, [r7, #32] 8020b32: 4413 add r3, r2 8020b34: 2b0a cmp r3, #10 8020b36: dd10 ble.n 8020b5a #if IP_REASS_FREE_OLDEST if (!ip_reass_remove_oldest_datagram(fraghdr, clen) || 8020b38: 8c3b ldrh r3, [r7, #32] 8020b3a: 4619 mov r1, r3 8020b3c: 6ab8 ldr r0, [r7, #40] ; 0x28 8020b3e: f7ff fd81 bl 8020644 8020b42: 4603 mov r3, r0 8020b44: 2b00 cmp r3, #0 8020b46: f000 8137 beq.w 8020db8 ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS)) 8020b4a: 4b84 ldr r3, [pc, #528] ; (8020d5c ) 8020b4c: 881b ldrh r3, [r3, #0] 8020b4e: 461a mov r2, r3 8020b50: 8c3b ldrh r3, [r7, #32] 8020b52: 4413 add r3, r2 if (!ip_reass_remove_oldest_datagram(fraghdr, clen) || 8020b54: 2b0a cmp r3, #10 8020b56: f300 812f bgt.w 8020db8 } } /* Look for the datagram the fragment belongs to in the current datagram queue, * remembering the previous in the queue for later dequeueing. */ for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) { 8020b5a: 4b81 ldr r3, [pc, #516] ; (8020d60 ) 8020b5c: 681b ldr r3, [r3, #0] 8020b5e: 633b str r3, [r7, #48] ; 0x30 8020b60: e015 b.n 8020b8e /* Check if the incoming fragment matches the one currently present in the reassembly buffer. If so, we proceed with copying the fragment into the buffer. */ if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) { 8020b62: 6b3b ldr r3, [r7, #48] ; 0x30 8020b64: 695a ldr r2, [r3, #20] 8020b66: 6abb ldr r3, [r7, #40] ; 0x28 8020b68: 68db ldr r3, [r3, #12] 8020b6a: 429a cmp r2, r3 8020b6c: d10c bne.n 8020b88 8020b6e: 6b3b ldr r3, [r7, #48] ; 0x30 8020b70: 699a ldr r2, [r3, #24] 8020b72: 6abb ldr r3, [r7, #40] ; 0x28 8020b74: 691b ldr r3, [r3, #16] 8020b76: 429a cmp r2, r3 8020b78: d106 bne.n 8020b88 8020b7a: 6b3b ldr r3, [r7, #48] ; 0x30 8020b7c: 899a ldrh r2, [r3, #12] 8020b7e: 6abb ldr r3, [r7, #40] ; 0x28 8020b80: 889b ldrh r3, [r3, #4] 8020b82: b29b uxth r3, r3 8020b84: 429a cmp r2, r3 8020b86: d006 beq.n 8020b96 for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) { 8020b88: 6b3b ldr r3, [r7, #48] ; 0x30 8020b8a: 681b ldr r3, [r3, #0] 8020b8c: 633b str r3, [r7, #48] ; 0x30 8020b8e: 6b3b ldr r3, [r7, #48] ; 0x30 8020b90: 2b00 cmp r3, #0 8020b92: d1e6 bne.n 8020b62 8020b94: e000 b.n 8020b98 LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n", lwip_ntohs(IPH_ID(fraghdr)))); IPFRAG_STATS_INC(ip_frag.cachehit); break; 8020b96: bf00 nop } } if (ipr == NULL) { 8020b98: 6b3b ldr r3, [r7, #48] ; 0x30 8020b9a: 2b00 cmp r3, #0 8020b9c: d109 bne.n 8020bb2 /* Enqueue a new datagram into the datagram queue */ ipr = ip_reass_enqueue_new_datagram(fraghdr, clen); 8020b9e: 8c3b ldrh r3, [r7, #32] 8020ba0: 4619 mov r1, r3 8020ba2: 6ab8 ldr r0, [r7, #40] ; 0x28 8020ba4: f7ff fdb0 bl 8020708 8020ba8: 6338 str r0, [r7, #48] ; 0x30 /* Bail if unable to enqueue */ if (ipr == NULL) { 8020baa: 6b3b ldr r3, [r7, #48] ; 0x30 8020bac: 2b00 cmp r3, #0 8020bae: d11c bne.n 8020bea goto nullreturn; 8020bb0: e105 b.n 8020dbe } } else { if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && 8020bb2: 6abb ldr r3, [r7, #40] ; 0x28 8020bb4: 88db ldrh r3, [r3, #6] 8020bb6: b29b uxth r3, r3 8020bb8: 4618 mov r0, r3 8020bba: f7f5 f9c1 bl 8015f40 8020bbe: 4603 mov r3, r0 8020bc0: f3c3 030c ubfx r3, r3, #0, #13 8020bc4: 2b00 cmp r3, #0 8020bc6: d110 bne.n 8020bea ((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) { 8020bc8: 6b3b ldr r3, [r7, #48] ; 0x30 8020bca: 89db ldrh r3, [r3, #14] 8020bcc: 4618 mov r0, r3 8020bce: f7f5 f9b7 bl 8015f40 8020bd2: 4603 mov r3, r0 8020bd4: f3c3 030c ubfx r3, r3, #0, #13 if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && 8020bd8: 2b00 cmp r3, #0 8020bda: d006 beq.n 8020bea /* ipr->iphdr is not the header from the first fragment, but fraghdr is * -> copy fraghdr into ipr->iphdr since we want to have the header * of the first fragment (for ICMP time exceeded and later, for copying * all options, if supported)*/ SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN); 8020bdc: 6b3b ldr r3, [r7, #48] ; 0x30 8020bde: 3308 adds r3, #8 8020be0: 2214 movs r2, #20 8020be2: 6ab9 ldr r1, [r7, #40] ; 0x28 8020be4: 4618 mov r0, r3 8020be6: f001 f8fe bl 8021de6 /* At this point, we have either created a new entry or pointing * to an existing one */ /* check for 'no more fragments', and update queue entry*/ is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0; 8020bea: 6abb ldr r3, [r7, #40] ; 0x28 8020bec: 88db ldrh r3, [r3, #6] 8020bee: b29b uxth r3, r3 8020bf0: f003 0320 and.w r3, r3, #32 8020bf4: 2b00 cmp r3, #0 8020bf6: bf0c ite eq 8020bf8: 2301 moveq r3, #1 8020bfa: 2300 movne r3, #0 8020bfc: b2db uxtb r3, r3 8020bfe: 61fb str r3, [r7, #28] if (is_last) { 8020c00: 69fb ldr r3, [r7, #28] 8020c02: 2b00 cmp r3, #0 8020c04: d00e beq.n 8020c24 u16_t datagram_len = (u16_t)(offset + len); 8020c06: 8cfa ldrh r2, [r7, #38] ; 0x26 8020c08: 8cbb ldrh r3, [r7, #36] ; 0x24 8020c0a: 4413 add r3, r2 8020c0c: 837b strh r3, [r7, #26] if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) { 8020c0e: 8b7a ldrh r2, [r7, #26] 8020c10: 8cfb ldrh r3, [r7, #38] ; 0x26 8020c12: 429a cmp r2, r3 8020c14: f0c0 80a0 bcc.w 8020d58 8020c18: 8b7b ldrh r3, [r7, #26] 8020c1a: f64f 72eb movw r2, #65515 ; 0xffeb 8020c1e: 4293 cmp r3, r2 8020c20: f200 809a bhi.w 8020d58 goto nullreturn_ipr; } } /* find the right place to insert this pbuf */ /* @todo: trim pbufs if fragments are overlapping */ valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last); 8020c24: 69fa ldr r2, [r7, #28] 8020c26: 6879 ldr r1, [r7, #4] 8020c28: 6b38 ldr r0, [r7, #48] ; 0x30 8020c2a: f7ff fdd5 bl 80207d8 8020c2e: 6178 str r0, [r7, #20] if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) { 8020c30: 697b ldr r3, [r7, #20] 8020c32: f1b3 3fff cmp.w r3, #4294967295 8020c36: f000 809b beq.w 8020d70 /* if we come here, the pbuf has been enqueued */ /* Track the current number of pbufs current 'in-flight', in order to limit the number of fragments that may be enqueued at any one time (overflow checked by testing against IP_REASS_MAX_PBUFS) */ ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen); 8020c3a: 4b48 ldr r3, [pc, #288] ; (8020d5c ) 8020c3c: 881a ldrh r2, [r3, #0] 8020c3e: 8c3b ldrh r3, [r7, #32] 8020c40: 4413 add r3, r2 8020c42: b29a uxth r2, r3 8020c44: 4b45 ldr r3, [pc, #276] ; (8020d5c ) 8020c46: 801a strh r2, [r3, #0] if (is_last) { 8020c48: 69fb ldr r3, [r7, #28] 8020c4a: 2b00 cmp r3, #0 8020c4c: d00d beq.n 8020c6a u16_t datagram_len = (u16_t)(offset + len); 8020c4e: 8cfa ldrh r2, [r7, #38] ; 0x26 8020c50: 8cbb ldrh r3, [r7, #36] ; 0x24 8020c52: 4413 add r3, r2 8020c54: 827b strh r3, [r7, #18] ipr->datagram_len = datagram_len; 8020c56: 6b3b ldr r3, [r7, #48] ; 0x30 8020c58: 8a7a ldrh r2, [r7, #18] 8020c5a: 839a strh r2, [r3, #28] ipr->flags |= IP_REASS_FLAG_LASTFRAG; 8020c5c: 6b3b ldr r3, [r7, #48] ; 0x30 8020c5e: 7f9b ldrb r3, [r3, #30] 8020c60: f043 0301 orr.w r3, r3, #1 8020c64: b2da uxtb r2, r3 8020c66: 6b3b ldr r3, [r7, #48] ; 0x30 8020c68: 779a strb r2, [r3, #30] LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: last fragment seen, total len %"S16_F"\n", ipr->datagram_len)); } if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) { 8020c6a: 697b ldr r3, [r7, #20] 8020c6c: 2b01 cmp r3, #1 8020c6e: d171 bne.n 8020d54 struct ip_reassdata *ipr_prev; /* the totally last fragment (flag more fragments = 0) was received at least * once AND all fragments are received */ u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN); 8020c70: 6b3b ldr r3, [r7, #48] ; 0x30 8020c72: 8b9b ldrh r3, [r3, #28] 8020c74: 3314 adds r3, #20 8020c76: 823b strh r3, [r7, #16] /* save the second pbuf before copying the header over the pointer */ r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf; 8020c78: 6b3b ldr r3, [r7, #48] ; 0x30 8020c7a: 685b ldr r3, [r3, #4] 8020c7c: 685b ldr r3, [r3, #4] 8020c7e: 681b ldr r3, [r3, #0] 8020c80: 62fb str r3, [r7, #44] ; 0x2c /* copy the original ip header back to the first pbuf */ fraghdr = (struct ip_hdr *)(ipr->p->payload); 8020c82: 6b3b ldr r3, [r7, #48] ; 0x30 8020c84: 685b ldr r3, [r3, #4] 8020c86: 685b ldr r3, [r3, #4] 8020c88: 62bb str r3, [r7, #40] ; 0x28 SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN); 8020c8a: 6b3b ldr r3, [r7, #48] ; 0x30 8020c8c: 3308 adds r3, #8 8020c8e: 2214 movs r2, #20 8020c90: 4619 mov r1, r3 8020c92: 6ab8 ldr r0, [r7, #40] ; 0x28 8020c94: f001 f8a7 bl 8021de6 IPH_LEN_SET(fraghdr, lwip_htons(datagram_len)); 8020c98: 8a3b ldrh r3, [r7, #16] 8020c9a: 4618 mov r0, r3 8020c9c: f7f5 f950 bl 8015f40 8020ca0: 4603 mov r3, r0 8020ca2: 461a mov r2, r3 8020ca4: 6abb ldr r3, [r7, #40] ; 0x28 8020ca6: 805a strh r2, [r3, #2] IPH_OFFSET_SET(fraghdr, 0); 8020ca8: 6abb ldr r3, [r7, #40] ; 0x28 8020caa: 2200 movs r2, #0 8020cac: 719a strb r2, [r3, #6] 8020cae: 2200 movs r2, #0 8020cb0: 71da strb r2, [r3, #7] IPH_CHKSUM_SET(fraghdr, 0); 8020cb2: 6abb ldr r3, [r7, #40] ; 0x28 8020cb4: 2200 movs r2, #0 8020cb6: 729a strb r2, [r3, #10] 8020cb8: 2200 movs r2, #0 8020cba: 72da strb r2, [r3, #11] IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) { IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN)); } #endif /* CHECKSUM_GEN_IP */ p = ipr->p; 8020cbc: 6b3b ldr r3, [r7, #48] ; 0x30 8020cbe: 685b ldr r3, [r3, #4] 8020cc0: 607b str r3, [r7, #4] /* chain together the pbufs contained within the reass_data list. */ while (r != NULL) { 8020cc2: e00d b.n 8020ce0 iprh = (struct ip_reass_helper *)r->payload; 8020cc4: 6afb ldr r3, [r7, #44] ; 0x2c 8020cc6: 685b ldr r3, [r3, #4] 8020cc8: 60fb str r3, [r7, #12] /* hide the ip header for every succeeding fragment */ pbuf_remove_header(r, IP_HLEN); 8020cca: 2114 movs r1, #20 8020ccc: 6af8 ldr r0, [r7, #44] ; 0x2c 8020cce: f7f6 fe8d bl 80179ec pbuf_cat(p, r); 8020cd2: 6af9 ldr r1, [r7, #44] ; 0x2c 8020cd4: 6878 ldr r0, [r7, #4] 8020cd6: f7f6 ffdd bl 8017c94 r = iprh->next_pbuf; 8020cda: 68fb ldr r3, [r7, #12] 8020cdc: 681b ldr r3, [r3, #0] 8020cde: 62fb str r3, [r7, #44] ; 0x2c while (r != NULL) { 8020ce0: 6afb ldr r3, [r7, #44] ; 0x2c 8020ce2: 2b00 cmp r3, #0 8020ce4: d1ee bne.n 8020cc4 } /* find the previous entry in the linked list */ if (ipr == reassdatagrams) { 8020ce6: 4b1e ldr r3, [pc, #120] ; (8020d60 ) 8020ce8: 681b ldr r3, [r3, #0] 8020cea: 6b3a ldr r2, [r7, #48] ; 0x30 8020cec: 429a cmp r2, r3 8020cee: d102 bne.n 8020cf6 ipr_prev = NULL; 8020cf0: 2300 movs r3, #0 8020cf2: 637b str r3, [r7, #52] ; 0x34 8020cf4: e010 b.n 8020d18 } else { for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { 8020cf6: 4b1a ldr r3, [pc, #104] ; (8020d60 ) 8020cf8: 681b ldr r3, [r3, #0] 8020cfa: 637b str r3, [r7, #52] ; 0x34 8020cfc: e007 b.n 8020d0e if (ipr_prev->next == ipr) { 8020cfe: 6b7b ldr r3, [r7, #52] ; 0x34 8020d00: 681b ldr r3, [r3, #0] 8020d02: 6b3a ldr r2, [r7, #48] ; 0x30 8020d04: 429a cmp r2, r3 8020d06: d006 beq.n 8020d16 for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { 8020d08: 6b7b ldr r3, [r7, #52] ; 0x34 8020d0a: 681b ldr r3, [r3, #0] 8020d0c: 637b str r3, [r7, #52] ; 0x34 8020d0e: 6b7b ldr r3, [r7, #52] ; 0x34 8020d10: 2b00 cmp r3, #0 8020d12: d1f4 bne.n 8020cfe 8020d14: e000 b.n 8020d18 break; 8020d16: bf00 nop } } } /* release the sources allocate for the fragment queue entry */ ip_reass_dequeue_datagram(ipr, ipr_prev); 8020d18: 6b79 ldr r1, [r7, #52] ; 0x34 8020d1a: 6b38 ldr r0, [r7, #48] ; 0x30 8020d1c: f7ff fd2e bl 802077c /* and adjust the number of pbufs currently queued for reassembly. */ clen = pbuf_clen(p); 8020d20: 6878 ldr r0, [r7, #4] 8020d22: f7f6 ff77 bl 8017c14 8020d26: 4603 mov r3, r0 8020d28: 843b strh r3, [r7, #32] LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen); 8020d2a: 4b0c ldr r3, [pc, #48] ; (8020d5c ) 8020d2c: 881b ldrh r3, [r3, #0] 8020d2e: 8c3a ldrh r2, [r7, #32] 8020d30: 429a cmp r2, r3 8020d32: d906 bls.n 8020d42 8020d34: 4b0b ldr r3, [pc, #44] ; (8020d64 ) 8020d36: f240 229b movw r2, #667 ; 0x29b 8020d3a: 490b ldr r1, [pc, #44] ; (8020d68 ) 8020d3c: 480b ldr r0, [pc, #44] ; (8020d6c ) 8020d3e: f000 fe23 bl 8021988 ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen); 8020d42: 4b06 ldr r3, [pc, #24] ; (8020d5c ) 8020d44: 881a ldrh r2, [r3, #0] 8020d46: 8c3b ldrh r3, [r7, #32] 8020d48: 1ad3 subs r3, r2, r3 8020d4a: b29a uxth r2, r3 8020d4c: 4b03 ldr r3, [pc, #12] ; (8020d5c ) 8020d4e: 801a strh r2, [r3, #0] MIB2_STATS_INC(mib2.ipreasmoks); /* Return the pbuf chain */ return p; 8020d50: 687b ldr r3, [r7, #4] 8020d52: e038 b.n 8020dc6 } /* the datagram is not (yet?) reassembled completely */ LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount)); return NULL; 8020d54: 2300 movs r3, #0 8020d56: e036 b.n 8020dc6 goto nullreturn_ipr; 8020d58: bf00 nop 8020d5a: e00a b.n 8020d72 8020d5c: 2401a5dc .word 0x2401a5dc 8020d60: 2401a5d8 .word 0x2401a5d8 8020d64: 08026884 .word 0x08026884 8020d68: 080269f4 .word 0x080269f4 8020d6c: 080268cc .word 0x080268cc goto nullreturn_ipr; 8020d70: bf00 nop nullreturn_ipr: LWIP_ASSERT("ipr != NULL", ipr != NULL); 8020d72: 6b3b ldr r3, [r7, #48] ; 0x30 8020d74: 2b00 cmp r3, #0 8020d76: d106 bne.n 8020d86 8020d78: 4b15 ldr r3, [pc, #84] ; (8020dd0 ) 8020d7a: f44f 722a mov.w r2, #680 ; 0x2a8 8020d7e: 4915 ldr r1, [pc, #84] ; (8020dd4 ) 8020d80: 4815 ldr r0, [pc, #84] ; (8020dd8 ) 8020d82: f000 fe01 bl 8021988 if (ipr->p == NULL) { 8020d86: 6b3b ldr r3, [r7, #48] ; 0x30 8020d88: 685b ldr r3, [r3, #4] 8020d8a: 2b00 cmp r3, #0 8020d8c: d116 bne.n 8020dbc /* dropped pbuf after creating a new datagram entry: remove the entry, too */ LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams); 8020d8e: 4b13 ldr r3, [pc, #76] ; (8020ddc ) 8020d90: 681b ldr r3, [r3, #0] 8020d92: 6b3a ldr r2, [r7, #48] ; 0x30 8020d94: 429a cmp r2, r3 8020d96: d006 beq.n 8020da6 8020d98: 4b0d ldr r3, [pc, #52] ; (8020dd0 ) 8020d9a: f240 22ab movw r2, #683 ; 0x2ab 8020d9e: 4910 ldr r1, [pc, #64] ; (8020de0 ) 8020da0: 480d ldr r0, [pc, #52] ; (8020dd8 ) 8020da2: f000 fdf1 bl 8021988 ip_reass_dequeue_datagram(ipr, NULL); 8020da6: 2100 movs r1, #0 8020da8: 6b38 ldr r0, [r7, #48] ; 0x30 8020daa: f7ff fce7 bl 802077c 8020dae: e006 b.n 8020dbe goto nullreturn; 8020db0: bf00 nop 8020db2: e004 b.n 8020dbe goto nullreturn; 8020db4: bf00 nop 8020db6: e002 b.n 8020dbe goto nullreturn; 8020db8: bf00 nop 8020dba: e000 b.n 8020dbe } nullreturn: 8020dbc: bf00 nop LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n")); IPFRAG_STATS_INC(ip_frag.drop); pbuf_free(p); 8020dbe: 6878 ldr r0, [r7, #4] 8020dc0: f7f6 fe9a bl 8017af8 return NULL; 8020dc4: 2300 movs r3, #0 } 8020dc6: 4618 mov r0, r3 8020dc8: 3738 adds r7, #56 ; 0x38 8020dca: 46bd mov sp, r7 8020dcc: bd80 pop {r7, pc} 8020dce: bf00 nop 8020dd0: 08026884 .word 0x08026884 8020dd4: 08026a10 .word 0x08026a10 8020dd8: 080268cc .word 0x080268cc 8020ddc: 2401a5d8 .word 0x2401a5d8 8020de0: 08026a1c .word 0x08026a1c 08020de4 : #if IP_FRAG #if !LWIP_NETIF_TX_SINGLE_PBUF /** Allocate a new struct pbuf_custom_ref */ static struct pbuf_custom_ref * ip_frag_alloc_pbuf_custom_ref(void) { 8020de4: b580 push {r7, lr} 8020de6: af00 add r7, sp, #0 return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF); 8020de8: 2005 movs r0, #5 8020dea: f7f5 fe71 bl 8016ad0 8020dee: 4603 mov r3, r0 } 8020df0: 4618 mov r0, r3 8020df2: bd80 pop {r7, pc} 08020df4 : /** Free a struct pbuf_custom_ref */ static void ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p) { 8020df4: b580 push {r7, lr} 8020df6: b082 sub sp, #8 8020df8: af00 add r7, sp, #0 8020dfa: 6078 str r0, [r7, #4] LWIP_ASSERT("p != NULL", p != NULL); 8020dfc: 687b ldr r3, [r7, #4] 8020dfe: 2b00 cmp r3, #0 8020e00: d106 bne.n 8020e10 8020e02: 4b07 ldr r3, [pc, #28] ; (8020e20 ) 8020e04: f44f 7231 mov.w r2, #708 ; 0x2c4 8020e08: 4906 ldr r1, [pc, #24] ; (8020e24 ) 8020e0a: 4807 ldr r0, [pc, #28] ; (8020e28 ) 8020e0c: f000 fdbc bl 8021988 memp_free(MEMP_FRAG_PBUF, p); 8020e10: 6879 ldr r1, [r7, #4] 8020e12: 2005 movs r0, #5 8020e14: f7f5 fed2 bl 8016bbc } 8020e18: bf00 nop 8020e1a: 3708 adds r7, #8 8020e1c: 46bd mov sp, r7 8020e1e: bd80 pop {r7, pc} 8020e20: 08026884 .word 0x08026884 8020e24: 08026a3c .word 0x08026a3c 8020e28: 080268cc .word 0x080268cc 08020e2c : /** Free-callback function to free a 'struct pbuf_custom_ref', called by * pbuf_free. */ static void ipfrag_free_pbuf_custom(struct pbuf *p) { 8020e2c: b580 push {r7, lr} 8020e2e: b084 sub sp, #16 8020e30: af00 add r7, sp, #0 8020e32: 6078 str r0, [r7, #4] struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p; 8020e34: 687b ldr r3, [r7, #4] 8020e36: 60fb str r3, [r7, #12] LWIP_ASSERT("pcr != NULL", pcr != NULL); 8020e38: 68fb ldr r3, [r7, #12] 8020e3a: 2b00 cmp r3, #0 8020e3c: d106 bne.n 8020e4c 8020e3e: 4b11 ldr r3, [pc, #68] ; (8020e84 ) 8020e40: f240 22ce movw r2, #718 ; 0x2ce 8020e44: 4910 ldr r1, [pc, #64] ; (8020e88 ) 8020e46: 4811 ldr r0, [pc, #68] ; (8020e8c ) 8020e48: f000 fd9e bl 8021988 LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p); 8020e4c: 68fa ldr r2, [r7, #12] 8020e4e: 687b ldr r3, [r7, #4] 8020e50: 429a cmp r2, r3 8020e52: d006 beq.n 8020e62 8020e54: 4b0b ldr r3, [pc, #44] ; (8020e84 ) 8020e56: f240 22cf movw r2, #719 ; 0x2cf 8020e5a: 490d ldr r1, [pc, #52] ; (8020e90 ) 8020e5c: 480b ldr r0, [pc, #44] ; (8020e8c ) 8020e5e: f000 fd93 bl 8021988 if (pcr->original != NULL) { 8020e62: 68fb ldr r3, [r7, #12] 8020e64: 695b ldr r3, [r3, #20] 8020e66: 2b00 cmp r3, #0 8020e68: d004 beq.n 8020e74 pbuf_free(pcr->original); 8020e6a: 68fb ldr r3, [r7, #12] 8020e6c: 695b ldr r3, [r3, #20] 8020e6e: 4618 mov r0, r3 8020e70: f7f6 fe42 bl 8017af8 } ip_frag_free_pbuf_custom_ref(pcr); 8020e74: 68f8 ldr r0, [r7, #12] 8020e76: f7ff ffbd bl 8020df4 } 8020e7a: bf00 nop 8020e7c: 3710 adds r7, #16 8020e7e: 46bd mov sp, r7 8020e80: bd80 pop {r7, pc} 8020e82: bf00 nop 8020e84: 08026884 .word 0x08026884 8020e88: 08026a48 .word 0x08026a48 8020e8c: 080268cc .word 0x080268cc 8020e90: 08026a54 .word 0x08026a54 08020e94 : * * @return ERR_OK if sent successfully, err_t otherwise */ err_t ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest) { 8020e94: b580 push {r7, lr} 8020e96: b094 sub sp, #80 ; 0x50 8020e98: af02 add r7, sp, #8 8020e9a: 60f8 str r0, [r7, #12] 8020e9c: 60b9 str r1, [r7, #8] 8020e9e: 607a str r2, [r7, #4] struct pbuf *rambuf; #if !LWIP_NETIF_TX_SINGLE_PBUF struct pbuf *newpbuf; u16_t newpbuflen = 0; 8020ea0: 2300 movs r3, #0 8020ea2: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 u16_t left_to_copy; #endif struct ip_hdr *original_iphdr; struct ip_hdr *iphdr; const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8); 8020ea6: 68bb ldr r3, [r7, #8] 8020ea8: 8c9b ldrh r3, [r3, #36] ; 0x24 8020eaa: 3b14 subs r3, #20 8020eac: 2b00 cmp r3, #0 8020eae: da00 bge.n 8020eb2 8020eb0: 3307 adds r3, #7 8020eb2: 10db asrs r3, r3, #3 8020eb4: 877b strh r3, [r7, #58] ; 0x3a u16_t left, fragsize; u16_t ofo; int last; u16_t poff = IP_HLEN; 8020eb6: 2314 movs r3, #20 8020eb8: 87fb strh r3, [r7, #62] ; 0x3e u16_t tmp; int mf_set; original_iphdr = (struct ip_hdr *)p->payload; 8020eba: 68fb ldr r3, [r7, #12] 8020ebc: 685b ldr r3, [r3, #4] 8020ebe: 637b str r3, [r7, #52] ; 0x34 iphdr = original_iphdr; 8020ec0: 6b7b ldr r3, [r7, #52] ; 0x34 8020ec2: 633b str r3, [r7, #48] ; 0x30 if (IPH_HL_BYTES(iphdr) != IP_HLEN) { 8020ec4: 6b3b ldr r3, [r7, #48] ; 0x30 8020ec6: 781b ldrb r3, [r3, #0] 8020ec8: f003 030f and.w r3, r3, #15 8020ecc: b2db uxtb r3, r3 8020ece: 009b lsls r3, r3, #2 8020ed0: b2db uxtb r3, r3 8020ed2: 2b14 cmp r3, #20 8020ed4: d002 beq.n 8020edc /* ip4_frag() does not support IP options */ return ERR_VAL; 8020ed6: f06f 0305 mvn.w r3, #5 8020eda: e110 b.n 80210fe } LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL); 8020edc: 68fb ldr r3, [r7, #12] 8020ede: 895b ldrh r3, [r3, #10] 8020ee0: 2b13 cmp r3, #19 8020ee2: d809 bhi.n 8020ef8 8020ee4: 4b88 ldr r3, [pc, #544] ; (8021108 ) 8020ee6: f44f 723f mov.w r2, #764 ; 0x2fc 8020eea: 4988 ldr r1, [pc, #544] ; (802110c ) 8020eec: 4888 ldr r0, [pc, #544] ; (8021110 ) 8020eee: f000 fd4b bl 8021988 8020ef2: f06f 0305 mvn.w r3, #5 8020ef6: e102 b.n 80210fe /* Save original offset */ tmp = lwip_ntohs(IPH_OFFSET(iphdr)); 8020ef8: 6b3b ldr r3, [r7, #48] ; 0x30 8020efa: 88db ldrh r3, [r3, #6] 8020efc: b29b uxth r3, r3 8020efe: 4618 mov r0, r3 8020f00: f7f5 f81e bl 8015f40 8020f04: 4603 mov r3, r0 8020f06: 87bb strh r3, [r7, #60] ; 0x3c ofo = tmp & IP_OFFMASK; 8020f08: 8fbb ldrh r3, [r7, #60] ; 0x3c 8020f0a: f3c3 030c ubfx r3, r3, #0, #13 8020f0e: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 /* already fragmented? if so, the last fragment we create must have MF, too */ mf_set = tmp & IP_MF; 8020f12: 8fbb ldrh r3, [r7, #60] ; 0x3c 8020f14: f403 5300 and.w r3, r3, #8192 ; 0x2000 8020f18: 62fb str r3, [r7, #44] ; 0x2c left = (u16_t)(p->tot_len - IP_HLEN); 8020f1a: 68fb ldr r3, [r7, #12] 8020f1c: 891b ldrh r3, [r3, #8] 8020f1e: 3b14 subs r3, #20 8020f20: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 while (left) { 8020f24: e0e1 b.n 80210ea /* Fill this fragment */ fragsize = LWIP_MIN(left, (u16_t)(nfb * 8)); 8020f26: 8f7b ldrh r3, [r7, #58] ; 0x3a 8020f28: 00db lsls r3, r3, #3 8020f2a: b29b uxth r3, r3 8020f2c: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 8020f30: 4293 cmp r3, r2 8020f32: bf28 it cs 8020f34: 4613 movcs r3, r2 8020f36: 857b strh r3, [r7, #42] ; 0x2a /* When not using a static buffer, create a chain of pbufs. * The first will be a PBUF_RAM holding the link and IP header. * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged, * but limited to the size of an mtu. */ rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM); 8020f38: f44f 7220 mov.w r2, #640 ; 0x280 8020f3c: 2114 movs r1, #20 8020f3e: 200e movs r0, #14 8020f40: f7f6 faf2 bl 8017528 8020f44: 6278 str r0, [r7, #36] ; 0x24 if (rambuf == NULL) { 8020f46: 6a7b ldr r3, [r7, #36] ; 0x24 8020f48: 2b00 cmp r3, #0 8020f4a: f000 80d5 beq.w 80210f8 goto memerr; } LWIP_ASSERT("this needs a pbuf in one piece!", 8020f4e: 6a7b ldr r3, [r7, #36] ; 0x24 8020f50: 895b ldrh r3, [r3, #10] 8020f52: 2b13 cmp r3, #19 8020f54: d806 bhi.n 8020f64 8020f56: 4b6c ldr r3, [pc, #432] ; (8021108 ) 8020f58: f44f 7249 mov.w r2, #804 ; 0x324 8020f5c: 496d ldr r1, [pc, #436] ; (8021114 ) 8020f5e: 486c ldr r0, [pc, #432] ; (8021110 ) 8020f60: f000 fd12 bl 8021988 (rambuf->len >= (IP_HLEN))); SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN); 8020f64: 6a7b ldr r3, [r7, #36] ; 0x24 8020f66: 685b ldr r3, [r3, #4] 8020f68: 2214 movs r2, #20 8020f6a: 6b79 ldr r1, [r7, #52] ; 0x34 8020f6c: 4618 mov r0, r3 8020f6e: f000 ff3a bl 8021de6 iphdr = (struct ip_hdr *)rambuf->payload; 8020f72: 6a7b ldr r3, [r7, #36] ; 0x24 8020f74: 685b ldr r3, [r3, #4] 8020f76: 633b str r3, [r7, #48] ; 0x30 left_to_copy = fragsize; 8020f78: 8d7b ldrh r3, [r7, #42] ; 0x2a 8020f7a: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 while (left_to_copy) { 8020f7e: e064 b.n 802104a struct pbuf_custom_ref *pcr; u16_t plen = (u16_t)(p->len - poff); 8020f80: 68fb ldr r3, [r7, #12] 8020f82: 895a ldrh r2, [r3, #10] 8020f84: 8ffb ldrh r3, [r7, #62] ; 0x3e 8020f86: 1ad3 subs r3, r2, r3 8020f88: 83fb strh r3, [r7, #30] LWIP_ASSERT("p->len >= poff", p->len >= poff); 8020f8a: 68fb ldr r3, [r7, #12] 8020f8c: 895b ldrh r3, [r3, #10] 8020f8e: 8ffa ldrh r2, [r7, #62] ; 0x3e 8020f90: 429a cmp r2, r3 8020f92: d906 bls.n 8020fa2 8020f94: 4b5c ldr r3, [pc, #368] ; (8021108 ) 8020f96: f240 322d movw r2, #813 ; 0x32d 8020f9a: 495f ldr r1, [pc, #380] ; (8021118 ) 8020f9c: 485c ldr r0, [pc, #368] ; (8021110 ) 8020f9e: f000 fcf3 bl 8021988 newpbuflen = LWIP_MIN(left_to_copy, plen); 8020fa2: 8bfa ldrh r2, [r7, #30] 8020fa4: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 8020fa8: 4293 cmp r3, r2 8020faa: bf28 it cs 8020fac: 4613 movcs r3, r2 8020fae: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 /* Is this pbuf already empty? */ if (!newpbuflen) { 8020fb2: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 8020fb6: 2b00 cmp r3, #0 8020fb8: d105 bne.n 8020fc6 poff = 0; 8020fba: 2300 movs r3, #0 8020fbc: 87fb strh r3, [r7, #62] ; 0x3e p = p->next; 8020fbe: 68fb ldr r3, [r7, #12] 8020fc0: 681b ldr r3, [r3, #0] 8020fc2: 60fb str r3, [r7, #12] continue; 8020fc4: e041 b.n 802104a } pcr = ip_frag_alloc_pbuf_custom_ref(); 8020fc6: f7ff ff0d bl 8020de4 8020fca: 61b8 str r0, [r7, #24] if (pcr == NULL) { 8020fcc: 69bb ldr r3, [r7, #24] 8020fce: 2b00 cmp r3, #0 8020fd0: d103 bne.n 8020fda pbuf_free(rambuf); 8020fd2: 6a78 ldr r0, [r7, #36] ; 0x24 8020fd4: f7f6 fd90 bl 8017af8 goto memerr; 8020fd8: e08f b.n 80210fa } /* Mirror this pbuf, although we might not need all of it. */ newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, 8020fda: 69b8 ldr r0, [r7, #24] (u8_t *)p->payload + poff, newpbuflen); 8020fdc: 68fb ldr r3, [r7, #12] 8020fde: 685a ldr r2, [r3, #4] newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, 8020fe0: 8ffb ldrh r3, [r7, #62] ; 0x3e 8020fe2: 4413 add r3, r2 8020fe4: f8b7 1046 ldrh.w r1, [r7, #70] ; 0x46 8020fe8: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46 8020fec: 9201 str r2, [sp, #4] 8020fee: 9300 str r3, [sp, #0] 8020ff0: 4603 mov r3, r0 8020ff2: 2241 movs r2, #65 ; 0x41 8020ff4: 2000 movs r0, #0 8020ff6: f7f6 fbc5 bl 8017784 8020ffa: 6178 str r0, [r7, #20] if (newpbuf == NULL) { 8020ffc: 697b ldr r3, [r7, #20] 8020ffe: 2b00 cmp r3, #0 8021000: d106 bne.n 8021010 ip_frag_free_pbuf_custom_ref(pcr); 8021002: 69b8 ldr r0, [r7, #24] 8021004: f7ff fef6 bl 8020df4 pbuf_free(rambuf); 8021008: 6a78 ldr r0, [r7, #36] ; 0x24 802100a: f7f6 fd75 bl 8017af8 goto memerr; 802100e: e074 b.n 80210fa } pbuf_ref(p); 8021010: 68f8 ldr r0, [r7, #12] 8021012: f7f6 fe17 bl 8017c44 pcr->original = p; 8021016: 69bb ldr r3, [r7, #24] 8021018: 68fa ldr r2, [r7, #12] 802101a: 615a str r2, [r3, #20] pcr->pc.custom_free_function = ipfrag_free_pbuf_custom; 802101c: 69bb ldr r3, [r7, #24] 802101e: 4a3f ldr r2, [pc, #252] ; (802111c ) 8021020: 611a str r2, [r3, #16] /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain * so that it is removed when pbuf_dechain is later called on rambuf. */ pbuf_cat(rambuf, newpbuf); 8021022: 6979 ldr r1, [r7, #20] 8021024: 6a78 ldr r0, [r7, #36] ; 0x24 8021026: f7f6 fe35 bl 8017c94 left_to_copy = (u16_t)(left_to_copy - newpbuflen); 802102a: f8b7 2044 ldrh.w r2, [r7, #68] ; 0x44 802102e: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 8021032: 1ad3 subs r3, r2, r3 8021034: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 if (left_to_copy) { 8021038: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 802103c: 2b00 cmp r3, #0 802103e: d004 beq.n 802104a poff = 0; 8021040: 2300 movs r3, #0 8021042: 87fb strh r3, [r7, #62] ; 0x3e p = p->next; 8021044: 68fb ldr r3, [r7, #12] 8021046: 681b ldr r3, [r3, #0] 8021048: 60fb str r3, [r7, #12] while (left_to_copy) { 802104a: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 802104e: 2b00 cmp r3, #0 8021050: d196 bne.n 8020f80 } } poff = (u16_t)(poff + newpbuflen); 8021052: 8ffa ldrh r2, [r7, #62] ; 0x3e 8021054: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 8021058: 4413 add r3, r2 802105a: 87fb strh r3, [r7, #62] ; 0x3e #endif /* LWIP_NETIF_TX_SINGLE_PBUF */ /* Correct header */ last = (left <= netif->mtu - IP_HLEN); 802105c: 68bb ldr r3, [r7, #8] 802105e: 8c9b ldrh r3, [r3, #36] ; 0x24 8021060: f1a3 0213 sub.w r2, r3, #19 8021064: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 8021068: 429a cmp r2, r3 802106a: bfcc ite gt 802106c: 2301 movgt r3, #1 802106e: 2300 movle r3, #0 8021070: b2db uxtb r3, r3 8021072: 623b str r3, [r7, #32] /* Set new offset and MF flag */ tmp = (IP_OFFMASK & (ofo)); 8021074: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 8021078: f3c3 030c ubfx r3, r3, #0, #13 802107c: 87bb strh r3, [r7, #60] ; 0x3c if (!last || mf_set) { 802107e: 6a3b ldr r3, [r7, #32] 8021080: 2b00 cmp r3, #0 8021082: d002 beq.n 802108a 8021084: 6afb ldr r3, [r7, #44] ; 0x2c 8021086: 2b00 cmp r3, #0 8021088: d003 beq.n 8021092 /* the last fragment has MF set if the input frame had it */ tmp = tmp | IP_MF; 802108a: 8fbb ldrh r3, [r7, #60] ; 0x3c 802108c: f443 5300 orr.w r3, r3, #8192 ; 0x2000 8021090: 87bb strh r3, [r7, #60] ; 0x3c } IPH_OFFSET_SET(iphdr, lwip_htons(tmp)); 8021092: 8fbb ldrh r3, [r7, #60] ; 0x3c 8021094: 4618 mov r0, r3 8021096: f7f4 ff53 bl 8015f40 802109a: 4603 mov r3, r0 802109c: 461a mov r2, r3 802109e: 6b3b ldr r3, [r7, #48] ; 0x30 80210a0: 80da strh r2, [r3, #6] IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN))); 80210a2: 8d7b ldrh r3, [r7, #42] ; 0x2a 80210a4: 3314 adds r3, #20 80210a6: b29b uxth r3, r3 80210a8: 4618 mov r0, r3 80210aa: f7f4 ff49 bl 8015f40 80210ae: 4603 mov r3, r0 80210b0: 461a mov r2, r3 80210b2: 6b3b ldr r3, [r7, #48] ; 0x30 80210b4: 805a strh r2, [r3, #2] IPH_CHKSUM_SET(iphdr, 0); 80210b6: 6b3b ldr r3, [r7, #48] ; 0x30 80210b8: 2200 movs r2, #0 80210ba: 729a strb r2, [r3, #10] 80210bc: 2200 movs r2, #0 80210be: 72da strb r2, [r3, #11] #endif /* CHECKSUM_GEN_IP */ /* No need for separate header pbuf - we allowed room for it in rambuf * when allocated. */ netif->output(netif, rambuf, dest); 80210c0: 68bb ldr r3, [r7, #8] 80210c2: 695b ldr r3, [r3, #20] 80210c4: 687a ldr r2, [r7, #4] 80210c6: 6a79 ldr r1, [r7, #36] ; 0x24 80210c8: 68b8 ldr r0, [r7, #8] 80210ca: 4798 blx r3 * recreate it next time round the loop. If we're lucky the hardware * will have already sent the packet, the free will really free, and * there will be zero memory penalty. */ pbuf_free(rambuf); 80210cc: 6a78 ldr r0, [r7, #36] ; 0x24 80210ce: f7f6 fd13 bl 8017af8 left = (u16_t)(left - fragsize); 80210d2: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 80210d6: 8d7b ldrh r3, [r7, #42] ; 0x2a 80210d8: 1ad3 subs r3, r2, r3 80210da: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 ofo = (u16_t)(ofo + nfb); 80210de: f8b7 2040 ldrh.w r2, [r7, #64] ; 0x40 80210e2: 8f7b ldrh r3, [r7, #58] ; 0x3a 80210e4: 4413 add r3, r2 80210e6: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 while (left) { 80210ea: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 80210ee: 2b00 cmp r3, #0 80210f0: f47f af19 bne.w 8020f26 } MIB2_STATS_INC(mib2.ipfragoks); return ERR_OK; 80210f4: 2300 movs r3, #0 80210f6: e002 b.n 80210fe goto memerr; 80210f8: bf00 nop memerr: MIB2_STATS_INC(mib2.ipfragfails); return ERR_MEM; 80210fa: f04f 33ff mov.w r3, #4294967295 } 80210fe: 4618 mov r0, r3 8021100: 3748 adds r7, #72 ; 0x48 8021102: 46bd mov sp, r7 8021104: bd80 pop {r7, pc} 8021106: bf00 nop 8021108: 08026884 .word 0x08026884 802110c: 08026a60 .word 0x08026a60 8021110: 080268cc .word 0x080268cc 8021114: 08026a7c .word 0x08026a7c 8021118: 08026a9c .word 0x08026a9c 802111c: 08020e2d .word 0x08020e2d 08021120 : * @see ETHARP_SUPPORT_VLAN * @see LWIP_HOOK_VLAN_CHECK */ err_t ethernet_input(struct pbuf *p, struct netif *netif) { 8021120: b580 push {r7, lr} 8021122: b086 sub sp, #24 8021124: af00 add r7, sp, #0 8021126: 6078 str r0, [r7, #4] 8021128: 6039 str r1, [r7, #0] struct eth_hdr *ethhdr; u16_t type; #if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6 u16_t next_hdr_offset = SIZEOF_ETH_HDR; 802112a: 230e movs r3, #14 802112c: 82fb strh r3, [r7, #22] #endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */ LWIP_ASSERT_CORE_LOCKED(); if (p->len <= SIZEOF_ETH_HDR) { 802112e: 687b ldr r3, [r7, #4] 8021130: 895b ldrh r3, [r3, #10] 8021132: 2b0e cmp r3, #14 8021134: d96e bls.n 8021214 ETHARP_STATS_INC(etharp.drop); MIB2_STATS_NETIF_INC(netif, ifinerrors); goto free_and_return; } if (p->if_idx == NETIF_NO_INDEX) { 8021136: 687b ldr r3, [r7, #4] 8021138: 7bdb ldrb r3, [r3, #15] 802113a: 2b00 cmp r3, #0 802113c: d106 bne.n 802114c p->if_idx = netif_get_index(netif); 802113e: 683b ldr r3, [r7, #0] 8021140: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 8021144: 3301 adds r3, #1 8021146: b2da uxtb r2, r3 8021148: 687b ldr r3, [r7, #4] 802114a: 73da strb r2, [r3, #15] } /* points to packet payload, which starts with an Ethernet header */ ethhdr = (struct eth_hdr *)p->payload; 802114c: 687b ldr r3, [r7, #4] 802114e: 685b ldr r3, [r3, #4] 8021150: 613b str r3, [r7, #16] (unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5], (unsigned char)ethhdr->src.addr[0], (unsigned char)ethhdr->src.addr[1], (unsigned char)ethhdr->src.addr[2], (unsigned char)ethhdr->src.addr[3], (unsigned char)ethhdr->src.addr[4], (unsigned char)ethhdr->src.addr[5], lwip_htons(ethhdr->type))); type = ethhdr->type; 8021152: 693b ldr r3, [r7, #16] 8021154: 7b1a ldrb r2, [r3, #12] 8021156: 7b5b ldrb r3, [r3, #13] 8021158: 021b lsls r3, r3, #8 802115a: 4313 orrs r3, r2 802115c: 81fb strh r3, [r7, #14] #if LWIP_ARP_FILTER_NETIF netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type)); #endif /* LWIP_ARP_FILTER_NETIF*/ if (ethhdr->dest.addr[0] & 1) { 802115e: 693b ldr r3, [r7, #16] 8021160: 781b ldrb r3, [r3, #0] 8021162: f003 0301 and.w r3, r3, #1 8021166: 2b00 cmp r3, #0 8021168: d023 beq.n 80211b2 /* this might be a multicast or broadcast packet */ if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) { 802116a: 693b ldr r3, [r7, #16] 802116c: 781b ldrb r3, [r3, #0] 802116e: 2b01 cmp r3, #1 8021170: d10f bne.n 8021192 #if LWIP_IPV4 if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) && 8021172: 693b ldr r3, [r7, #16] 8021174: 785b ldrb r3, [r3, #1] 8021176: 2b00 cmp r3, #0 8021178: d11b bne.n 80211b2 (ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) { 802117a: 693b ldr r3, [r7, #16] 802117c: 789b ldrb r3, [r3, #2] if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) && 802117e: 2b5e cmp r3, #94 ; 0x5e 8021180: d117 bne.n 80211b2 /* mark the pbuf as link-layer multicast */ p->flags |= PBUF_FLAG_LLMCAST; 8021182: 687b ldr r3, [r7, #4] 8021184: 7b5b ldrb r3, [r3, #13] 8021186: f043 0310 orr.w r3, r3, #16 802118a: b2da uxtb r2, r3 802118c: 687b ldr r3, [r7, #4] 802118e: 735a strb r2, [r3, #13] 8021190: e00f b.n 80211b2 (ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) { /* mark the pbuf as link-layer multicast */ p->flags |= PBUF_FLAG_LLMCAST; } #endif /* LWIP_IPV6 */ else if (eth_addr_cmp(ðhdr->dest, ðbroadcast)) { 8021192: 693b ldr r3, [r7, #16] 8021194: 2206 movs r2, #6 8021196: 4928 ldr r1, [pc, #160] ; (8021238 ) 8021198: 4618 mov r0, r3 802119a: f000 fd77 bl 8021c8c 802119e: 4603 mov r3, r0 80211a0: 2b00 cmp r3, #0 80211a2: d106 bne.n 80211b2 /* mark the pbuf as link-layer broadcast */ p->flags |= PBUF_FLAG_LLBCAST; 80211a4: 687b ldr r3, [r7, #4] 80211a6: 7b5b ldrb r3, [r3, #13] 80211a8: f043 0308 orr.w r3, r3, #8 80211ac: b2da uxtb r2, r3 80211ae: 687b ldr r3, [r7, #4] 80211b0: 735a strb r2, [r3, #13] } } switch (type) { 80211b2: 89fb ldrh r3, [r7, #14] 80211b4: 2b08 cmp r3, #8 80211b6: d003 beq.n 80211c0 80211b8: f5b3 6fc1 cmp.w r3, #1544 ; 0x608 80211bc: d014 beq.n 80211e8 } #endif ETHARP_STATS_INC(etharp.proterr); ETHARP_STATS_INC(etharp.drop); MIB2_STATS_NETIF_INC(netif, ifinunknownprotos); goto free_and_return; 80211be: e032 b.n 8021226 if (!(netif->flags & NETIF_FLAG_ETHARP)) { 80211c0: 683b ldr r3, [r7, #0] 80211c2: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 80211c6: f003 0308 and.w r3, r3, #8 80211ca: 2b00 cmp r3, #0 80211cc: d024 beq.n 8021218 if (pbuf_remove_header(p, next_hdr_offset)) { 80211ce: 8afb ldrh r3, [r7, #22] 80211d0: 4619 mov r1, r3 80211d2: 6878 ldr r0, [r7, #4] 80211d4: f7f6 fc0a bl 80179ec 80211d8: 4603 mov r3, r0 80211da: 2b00 cmp r3, #0 80211dc: d11e bne.n 802121c ip4_input(p, netif); 80211de: 6839 ldr r1, [r7, #0] 80211e0: 6878 ldr r0, [r7, #4] 80211e2: f7fe ff21 bl 8020028 break; 80211e6: e013 b.n 8021210 if (!(netif->flags & NETIF_FLAG_ETHARP)) { 80211e8: 683b ldr r3, [r7, #0] 80211ea: f893 302d ldrb.w r3, [r3, #45] ; 0x2d 80211ee: f003 0308 and.w r3, r3, #8 80211f2: 2b00 cmp r3, #0 80211f4: d014 beq.n 8021220 if (pbuf_remove_header(p, next_hdr_offset)) { 80211f6: 8afb ldrh r3, [r7, #22] 80211f8: 4619 mov r1, r3 80211fa: 6878 ldr r0, [r7, #4] 80211fc: f7f6 fbf6 bl 80179ec 8021200: 4603 mov r3, r0 8021202: 2b00 cmp r3, #0 8021204: d10e bne.n 8021224 etharp_input(p, netif); 8021206: 6839 ldr r1, [r7, #0] 8021208: 6878 ldr r0, [r7, #4] 802120a: f7fe f897 bl 801f33c break; 802120e: bf00 nop } /* This means the pbuf is freed or consumed, so the caller doesn't have to free it again */ return ERR_OK; 8021210: 2300 movs r3, #0 8021212: e00c b.n 802122e goto free_and_return; 8021214: bf00 nop 8021216: e006 b.n 8021226 goto free_and_return; 8021218: bf00 nop 802121a: e004 b.n 8021226 goto free_and_return; 802121c: bf00 nop 802121e: e002 b.n 8021226 goto free_and_return; 8021220: bf00 nop 8021222: e000 b.n 8021226 goto free_and_return; 8021224: bf00 nop free_and_return: pbuf_free(p); 8021226: 6878 ldr r0, [r7, #4] 8021228: f7f6 fc66 bl 8017af8 return ERR_OK; 802122c: 2300 movs r3, #0 } 802122e: 4618 mov r0, r3 8021230: 3718 adds r7, #24 8021232: 46bd mov sp, r7 8021234: bd80 pop {r7, pc} 8021236: bf00 nop 8021238: 08026cf0 .word 0x08026cf0 0802123c : * @return ERR_OK if the packet was sent, any other err_t on failure */ err_t ethernet_output(struct netif * netif, struct pbuf * p, const struct eth_addr * src, const struct eth_addr * dst, u16_t eth_type) { 802123c: b580 push {r7, lr} 802123e: b086 sub sp, #24 8021240: af00 add r7, sp, #0 8021242: 60f8 str r0, [r7, #12] 8021244: 60b9 str r1, [r7, #8] 8021246: 607a str r2, [r7, #4] 8021248: 603b str r3, [r7, #0] struct eth_hdr *ethhdr; u16_t eth_type_be = lwip_htons(eth_type); 802124a: 8c3b ldrh r3, [r7, #32] 802124c: 4618 mov r0, r3 802124e: f7f4 fe77 bl 8015f40 8021252: 4603 mov r3, r0 8021254: 82fb strh r3, [r7, #22] eth_type_be = PP_HTONS(ETHTYPE_VLAN); } else #endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */ { if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) { 8021256: 210e movs r1, #14 8021258: 68b8 ldr r0, [r7, #8] 802125a: f7f6 fbb7 bl 80179cc 802125e: 4603 mov r3, r0 8021260: 2b00 cmp r3, #0 8021262: d125 bne.n 80212b0 } } LWIP_ASSERT_CORE_LOCKED(); ethhdr = (struct eth_hdr *)p->payload; 8021264: 68bb ldr r3, [r7, #8] 8021266: 685b ldr r3, [r3, #4] 8021268: 613b str r3, [r7, #16] ethhdr->type = eth_type_be; 802126a: 693b ldr r3, [r7, #16] 802126c: 8afa ldrh r2, [r7, #22] 802126e: 819a strh r2, [r3, #12] SMEMCPY(ðhdr->dest, dst, ETH_HWADDR_LEN); 8021270: 693b ldr r3, [r7, #16] 8021272: 2206 movs r2, #6 8021274: 6839 ldr r1, [r7, #0] 8021276: 4618 mov r0, r3 8021278: f000 fdb5 bl 8021de6 SMEMCPY(ðhdr->src, src, ETH_HWADDR_LEN); 802127c: 693b ldr r3, [r7, #16] 802127e: 3306 adds r3, #6 8021280: 2206 movs r2, #6 8021282: 6879 ldr r1, [r7, #4] 8021284: 4618 mov r0, r3 8021286: f000 fdae bl 8021de6 LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!", 802128a: 68fb ldr r3, [r7, #12] 802128c: f893 302c ldrb.w r3, [r3, #44] ; 0x2c 8021290: 2b06 cmp r3, #6 8021292: d006 beq.n 80212a2 8021294: 4b0a ldr r3, [pc, #40] ; (80212c0 ) 8021296: f44f 7299 mov.w r2, #306 ; 0x132 802129a: 490a ldr r1, [pc, #40] ; (80212c4 ) 802129c: 480a ldr r0, [pc, #40] ; (80212c8 ) 802129e: f000 fb73 bl 8021988 (netif->hwaddr_len == ETH_HWADDR_LEN)); LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("ethernet_output: sending packet %p\n", (void *)p)); /* send the packet */ return netif->linkoutput(netif, p); 80212a2: 68fb ldr r3, [r7, #12] 80212a4: 699b ldr r3, [r3, #24] 80212a6: 68b9 ldr r1, [r7, #8] 80212a8: 68f8 ldr r0, [r7, #12] 80212aa: 4798 blx r3 80212ac: 4603 mov r3, r0 80212ae: e002 b.n 80212b6 goto pbuf_header_failed; 80212b0: bf00 nop pbuf_header_failed: LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("ethernet_output: could not allocate room for header.\n")); LINK_STATS_INC(link.lenerr); return ERR_BUF; 80212b2: f06f 0301 mvn.w r3, #1 } 80212b6: 4618 mov r0, r3 80212b8: 3718 adds r7, #24 80212ba: 46bd mov sp, r7 80212bc: bd80 pop {r7, pc} 80212be: bf00 nop 80212c0: 08026aac .word 0x08026aac 80212c4: 08026ae4 .word 0x08026ae4 80212c8: 08026b18 .word 0x08026b18 080212cc : #endif /*-----------------------------------------------------------------------------------*/ // Creates an empty mailbox. err_t sys_mbox_new(sys_mbox_t *mbox, int size) { 80212cc: b580 push {r7, lr} 80212ce: b086 sub sp, #24 80212d0: af00 add r7, sp, #0 80212d2: 6078 str r0, [r7, #4] 80212d4: 6039 str r1, [r7, #0] #if (osCMSIS < 0x20000U) osMessageQDef(QUEUE, size, void *); 80212d6: 683b ldr r3, [r7, #0] 80212d8: 60bb str r3, [r7, #8] 80212da: 2304 movs r3, #4 80212dc: 60fb str r3, [r7, #12] 80212de: 2300 movs r3, #0 80212e0: 613b str r3, [r7, #16] 80212e2: 2300 movs r3, #0 80212e4: 617b str r3, [r7, #20] *mbox = osMessageCreate(osMessageQ(QUEUE), NULL); 80212e6: f107 0308 add.w r3, r7, #8 80212ea: 2100 movs r1, #0 80212ec: 4618 mov r0, r3 80212ee: f7ef f9c0 bl 8010672 80212f2: 4602 mov r2, r0 80212f4: 687b ldr r3, [r7, #4] 80212f6: 601a str r2, [r3, #0] if(lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used) { lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used; } #endif /* SYS_STATS */ if(*mbox == NULL) 80212f8: 687b ldr r3, [r7, #4] 80212fa: 681b ldr r3, [r3, #0] 80212fc: 2b00 cmp r3, #0 80212fe: d102 bne.n 8021306 return ERR_MEM; 8021300: f04f 33ff mov.w r3, #4294967295 8021304: e000 b.n 8021308 return ERR_OK; 8021306: 2300 movs r3, #0 } 8021308: 4618 mov r0, r3 802130a: 3718 adds r7, #24 802130c: 46bd mov sp, r7 802130e: bd80 pop {r7, pc} 08021310 : Deallocates a mailbox. If there are messages still present in the mailbox when the mailbox is deallocated, it is an indication of a programming error in lwIP and the developer should be notified. */ void sys_mbox_free(sys_mbox_t *mbox) { 8021310: b580 push {r7, lr} 8021312: b082 sub sp, #8 8021314: af00 add r7, sp, #0 8021316: 6078 str r0, [r7, #4] #if (osCMSIS < 0x20000U) if(osMessageWaiting(*mbox)) 8021318: 687b ldr r3, [r7, #4] 802131a: 681b ldr r3, [r3, #0] 802131c: 4618 mov r0, r3 802131e: f7ef fa85 bl 801082c lwip_stats.sys.mbox.err++; #endif /* SYS_STATS */ } #if (osCMSIS < 0x20000U) osMessageDelete(*mbox); 8021322: 687b ldr r3, [r7, #4] 8021324: 681b ldr r3, [r3, #0] 8021326: 4618 mov r0, r3 8021328: f7ef fa96 bl 8010858 osMessageQueueDelete(*mbox); #endif #if SYS_STATS --lwip_stats.sys.mbox.used; #endif /* SYS_STATS */ } 802132c: bf00 nop 802132e: 3708 adds r7, #8 8021330: 46bd mov sp, r7 8021332: bd80 pop {r7, pc} 08021334 : /*-----------------------------------------------------------------------------------*/ // Try to post the "msg" to the mailbox. err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) { 8021334: b580 push {r7, lr} 8021336: b084 sub sp, #16 8021338: af00 add r7, sp, #0 802133a: 6078 str r0, [r7, #4] 802133c: 6039 str r1, [r7, #0] err_t result; #if (osCMSIS < 0x20000U) if(osMessagePut(*mbox, (uint32_t)msg, 0) == osOK) 802133e: 687b ldr r3, [r7, #4] 8021340: 681b ldr r3, [r3, #0] 8021342: 6839 ldr r1, [r7, #0] 8021344: 2200 movs r2, #0 8021346: 4618 mov r0, r3 8021348: f7ef f9bc bl 80106c4 802134c: 4603 mov r3, r0 802134e: 2b00 cmp r3, #0 8021350: d102 bne.n 8021358 #else if(osMessageQueuePut(*mbox, &msg, 0, 0) == osOK) #endif { result = ERR_OK; 8021352: 2300 movs r3, #0 8021354: 73fb strb r3, [r7, #15] 8021356: e001 b.n 802135c } else { // could not post, queue must be full result = ERR_MEM; 8021358: 23ff movs r3, #255 ; 0xff 802135a: 73fb strb r3, [r7, #15] #if SYS_STATS lwip_stats.sys.mbox.err++; #endif /* SYS_STATS */ } return result; 802135c: f997 300f ldrsb.w r3, [r7, #15] } 8021360: 4618 mov r0, r3 8021362: 3710 adds r7, #16 8021364: 46bd mov sp, r7 8021366: bd80 pop {r7, pc} 08021368 : Note that a function with a similar name, sys_mbox_fetch(), is implemented by lwIP. */ u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) { 8021368: b580 push {r7, lr} 802136a: b08c sub sp, #48 ; 0x30 802136c: af00 add r7, sp, #0 802136e: 61f8 str r0, [r7, #28] 8021370: 61b9 str r1, [r7, #24] 8021372: 617a str r2, [r7, #20] #if (osCMSIS < 0x20000U) osEvent event; uint32_t starttime = osKernelSysTick(); 8021374: f7ee ffa8 bl 80102c8 8021378: 62f8 str r0, [r7, #44] ; 0x2c #else osStatus_t status; uint32_t starttime = osKernelGetTickCount(); #endif if(timeout != 0) 802137a: 697b ldr r3, [r7, #20] 802137c: 2b00 cmp r3, #0 802137e: d017 beq.n 80213b0 { #if (osCMSIS < 0x20000U) event = osMessageGet (*mbox, timeout); 8021380: 69fb ldr r3, [r7, #28] 8021382: 6819 ldr r1, [r3, #0] 8021384: f107 0320 add.w r3, r7, #32 8021388: 697a ldr r2, [r7, #20] 802138a: 4618 mov r0, r3 802138c: f7ef f9da bl 8010744 if(event.status == osEventMessage) 8021390: 6a3b ldr r3, [r7, #32] 8021392: 2b10 cmp r3, #16 8021394: d109 bne.n 80213aa { *msg = (void *)event.value.v; 8021396: 6a7b ldr r3, [r7, #36] ; 0x24 8021398: 461a mov r2, r3 802139a: 69bb ldr r3, [r7, #24] 802139c: 601a str r2, [r3, #0] return (osKernelSysTick() - starttime); 802139e: f7ee ff93 bl 80102c8 80213a2: 4602 mov r2, r0 80213a4: 6afb ldr r3, [r7, #44] ; 0x2c 80213a6: 1ad3 subs r3, r2, r3 80213a8: e019 b.n 80213de return (osKernelGetTickCount() - starttime); } #endif else { return SYS_ARCH_TIMEOUT; 80213aa: f04f 33ff mov.w r3, #4294967295 80213ae: e016 b.n 80213de } } else { #if (osCMSIS < 0x20000U) event = osMessageGet (*mbox, osWaitForever); 80213b0: 69fb ldr r3, [r7, #28] 80213b2: 6819 ldr r1, [r3, #0] 80213b4: 463b mov r3, r7 80213b6: f04f 32ff mov.w r2, #4294967295 80213ba: 4618 mov r0, r3 80213bc: f7ef f9c2 bl 8010744 80213c0: f107 0320 add.w r3, r7, #32 80213c4: 463a mov r2, r7 80213c6: ca07 ldmia r2, {r0, r1, r2} 80213c8: e883 0007 stmia.w r3, {r0, r1, r2} *msg = (void *)event.value.v; 80213cc: 6a7b ldr r3, [r7, #36] ; 0x24 80213ce: 461a mov r2, r3 80213d0: 69bb ldr r3, [r7, #24] 80213d2: 601a str r2, [r3, #0] return (osKernelSysTick() - starttime); 80213d4: f7ee ff78 bl 80102c8 80213d8: 4602 mov r2, r0 80213da: 6afb ldr r3, [r7, #44] ; 0x2c 80213dc: 1ad3 subs r3, r2, r3 #else osMessageQueueGet(*mbox, msg, 0, osWaitForever ); return (osKernelGetTickCount() - starttime); #endif } } 80213de: 4618 mov r0, r3 80213e0: 3730 adds r7, #48 ; 0x30 80213e2: 46bd mov sp, r7 80213e4: bd80 pop {r7, pc} 080213e6 : /* Similar to sys_arch_mbox_fetch, but if message is not ready immediately, we'll return with SYS_MBOX_EMPTY. On success, 0 is returned. */ u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) { 80213e6: b580 push {r7, lr} 80213e8: b086 sub sp, #24 80213ea: af00 add r7, sp, #0 80213ec: 6078 str r0, [r7, #4] 80213ee: 6039 str r1, [r7, #0] #if (osCMSIS < 0x20000U) osEvent event; event = osMessageGet (*mbox, 0); 80213f0: 687b ldr r3, [r7, #4] 80213f2: 6819 ldr r1, [r3, #0] 80213f4: f107 030c add.w r3, r7, #12 80213f8: 2200 movs r2, #0 80213fa: 4618 mov r0, r3 80213fc: f7ef f9a2 bl 8010744 if(event.status == osEventMessage) 8021400: 68fb ldr r3, [r7, #12] 8021402: 2b10 cmp r3, #16 8021404: d105 bne.n 8021412 { *msg = (void *)event.value.v; 8021406: 693b ldr r3, [r7, #16] 8021408: 461a mov r2, r3 802140a: 683b ldr r3, [r7, #0] 802140c: 601a str r2, [r3, #0] #else if (osMessageQueueGet(*mbox, msg, 0, 0) == osOK) { #endif return ERR_OK; 802140e: 2300 movs r3, #0 8021410: e001 b.n 8021416 } else { return SYS_MBOX_EMPTY; 8021412: f04f 33ff mov.w r3, #4294967295 } } 8021416: 4618 mov r0, r3 8021418: 3718 adds r7, #24 802141a: 46bd mov sp, r7 802141c: bd80 pop {r7, pc} 0802141e : /*----------------------------------------------------------------------------------*/ int sys_mbox_valid(sys_mbox_t *mbox) { 802141e: b480 push {r7} 8021420: b083 sub sp, #12 8021422: af00 add r7, sp, #0 8021424: 6078 str r0, [r7, #4] if (*mbox == SYS_MBOX_NULL) 8021426: 687b ldr r3, [r7, #4] 8021428: 681b ldr r3, [r3, #0] 802142a: 2b00 cmp r3, #0 802142c: d101 bne.n 8021432 return 0; 802142e: 2300 movs r3, #0 8021430: e000 b.n 8021434 else return 1; 8021432: 2301 movs r3, #1 } 8021434: 4618 mov r0, r3 8021436: 370c adds r7, #12 8021438: 46bd mov sp, r7 802143a: f85d 7b04 ldr.w r7, [sp], #4 802143e: 4770 bx lr 08021440 : /*-----------------------------------------------------------------------------------*/ void sys_mbox_set_invalid(sys_mbox_t *mbox) { 8021440: b480 push {r7} 8021442: b083 sub sp, #12 8021444: af00 add r7, sp, #0 8021446: 6078 str r0, [r7, #4] *mbox = SYS_MBOX_NULL; 8021448: 687b ldr r3, [r7, #4] 802144a: 2200 movs r2, #0 802144c: 601a str r2, [r3, #0] } 802144e: bf00 nop 8021450: 370c adds r7, #12 8021452: 46bd mov sp, r7 8021454: f85d 7b04 ldr.w r7, [sp], #4 8021458: 4770 bx lr 0802145a : /*-----------------------------------------------------------------------------------*/ // Creates a new semaphore. The "count" argument specifies // the initial state of the semaphore. err_t sys_sem_new(sys_sem_t *sem, u8_t count) { 802145a: b580 push {r7, lr} 802145c: b084 sub sp, #16 802145e: af00 add r7, sp, #0 8021460: 6078 str r0, [r7, #4] 8021462: 460b mov r3, r1 8021464: 70fb strb r3, [r7, #3] #if (osCMSIS < 0x20000U) osSemaphoreDef(SEM); 8021466: 2300 movs r3, #0 8021468: 60bb str r3, [r7, #8] 802146a: 2300 movs r3, #0 802146c: 60fb str r3, [r7, #12] *sem = osSemaphoreCreate (osSemaphore(SEM), 1); 802146e: f107 0308 add.w r3, r7, #8 8021472: 2101 movs r1, #1 8021474: 4618 mov r0, r3 8021476: f7ef f833 bl 80104e0 802147a: 4602 mov r2, r0 802147c: 687b ldr r3, [r7, #4] 802147e: 601a str r2, [r3, #0] #else *sem = osSemaphoreNew(UINT16_MAX, count, NULL); #endif if(*sem == NULL) 8021480: 687b ldr r3, [r7, #4] 8021482: 681b ldr r3, [r3, #0] 8021484: 2b00 cmp r3, #0 8021486: d102 bne.n 802148e { #if SYS_STATS ++lwip_stats.sys.sem.err; #endif /* SYS_STATS */ return ERR_MEM; 8021488: f04f 33ff mov.w r3, #4294967295 802148c: e009 b.n 80214a2 } if(count == 0) // Means it can't be taken 802148e: 78fb ldrb r3, [r7, #3] 8021490: 2b00 cmp r3, #0 8021492: d105 bne.n 80214a0 { #if (osCMSIS < 0x20000U) osSemaphoreWait(*sem, 0); 8021494: 687b ldr r3, [r7, #4] 8021496: 681b ldr r3, [r3, #0] 8021498: 2100 movs r1, #0 802149a: 4618 mov r0, r3 802149c: f7ef f852 bl 8010544 if (lwip_stats.sys.sem.max < lwip_stats.sys.sem.used) { lwip_stats.sys.sem.max = lwip_stats.sys.sem.used; } #endif /* SYS_STATS */ return ERR_OK; 80214a0: 2300 movs r3, #0 } 80214a2: 4618 mov r0, r3 80214a4: 3710 adds r7, #16 80214a6: 46bd mov sp, r7 80214a8: bd80 pop {r7, pc} 080214aa : Notice that lwIP implements a function with a similar name, sys_sem_wait(), that uses the sys_arch_sem_wait() function. */ u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) { 80214aa: b580 push {r7, lr} 80214ac: b084 sub sp, #16 80214ae: af00 add r7, sp, #0 80214b0: 6078 str r0, [r7, #4] 80214b2: 6039 str r1, [r7, #0] #if (osCMSIS < 0x20000U) uint32_t starttime = osKernelSysTick(); 80214b4: f7ee ff08 bl 80102c8 80214b8: 60f8 str r0, [r7, #12] #else uint32_t starttime = osKernelGetTickCount(); #endif if(timeout != 0) 80214ba: 683b ldr r3, [r7, #0] 80214bc: 2b00 cmp r3, #0 80214be: d011 beq.n 80214e4 { #if (osCMSIS < 0x20000U) if(osSemaphoreWait (*sem, timeout) == osOK) 80214c0: 687b ldr r3, [r7, #4] 80214c2: 681b ldr r3, [r3, #0] 80214c4: 6839 ldr r1, [r7, #0] 80214c6: 4618 mov r0, r3 80214c8: f7ef f83c bl 8010544 80214cc: 4603 mov r3, r0 80214ce: 2b00 cmp r3, #0 80214d0: d105 bne.n 80214de { return (osKernelSysTick() - starttime); 80214d2: f7ee fef9 bl 80102c8 80214d6: 4602 mov r2, r0 80214d8: 68fb ldr r3, [r7, #12] 80214da: 1ad3 subs r3, r2, r3 80214dc: e012 b.n 8021504 return (osKernelGetTickCount() - starttime); #endif } else { return SYS_ARCH_TIMEOUT; 80214de: f04f 33ff mov.w r3, #4294967295 80214e2: e00f b.n 8021504 } } else { #if (osCMSIS < 0x20000U) while(osSemaphoreWait (*sem, osWaitForever) != osOK); 80214e4: bf00 nop 80214e6: 687b ldr r3, [r7, #4] 80214e8: 681b ldr r3, [r3, #0] 80214ea: f04f 31ff mov.w r1, #4294967295 80214ee: 4618 mov r0, r3 80214f0: f7ef f828 bl 8010544 80214f4: 4603 mov r3, r0 80214f6: 2b00 cmp r3, #0 80214f8: d1f5 bne.n 80214e6 return (osKernelSysTick() - starttime); 80214fa: f7ee fee5 bl 80102c8 80214fe: 4602 mov r2, r0 8021500: 68fb ldr r3, [r7, #12] 8021502: 1ad3 subs r3, r2, r3 #else while(osSemaphoreAcquire(*sem, osWaitForever) != osOK); return (osKernelGetTickCount() - starttime); #endif } } 8021504: 4618 mov r0, r3 8021506: 3710 adds r7, #16 8021508: 46bd mov sp, r7 802150a: bd80 pop {r7, pc} 0802150c : /*-----------------------------------------------------------------------------------*/ // Signals a semaphore void sys_sem_signal(sys_sem_t *sem) { 802150c: b580 push {r7, lr} 802150e: b082 sub sp, #8 8021510: af00 add r7, sp, #0 8021512: 6078 str r0, [r7, #4] osSemaphoreRelease(*sem); 8021514: 687b ldr r3, [r7, #4] 8021516: 681b ldr r3, [r3, #0] 8021518: 4618 mov r0, r3 802151a: f7ef f861 bl 80105e0 } 802151e: bf00 nop 8021520: 3708 adds r7, #8 8021522: 46bd mov sp, r7 8021524: bd80 pop {r7, pc} 08021526 : /*-----------------------------------------------------------------------------------*/ // Deallocates a semaphore void sys_sem_free(sys_sem_t *sem) { 8021526: b580 push {r7, lr} 8021528: b082 sub sp, #8 802152a: af00 add r7, sp, #0 802152c: 6078 str r0, [r7, #4] #if SYS_STATS --lwip_stats.sys.sem.used; #endif /* SYS_STATS */ osSemaphoreDelete(*sem); 802152e: 687b ldr r3, [r7, #4] 8021530: 681b ldr r3, [r3, #0] 8021532: 4618 mov r0, r3 8021534: f7ef f88a bl 801064c } 8021538: bf00 nop 802153a: 3708 adds r7, #8 802153c: 46bd mov sp, r7 802153e: bd80 pop {r7, pc} 08021540 : /*-----------------------------------------------------------------------------------*/ int sys_sem_valid(sys_sem_t *sem) { 8021540: b480 push {r7} 8021542: b083 sub sp, #12 8021544: af00 add r7, sp, #0 8021546: 6078 str r0, [r7, #4] if (*sem == SYS_SEM_NULL) 8021548: 687b ldr r3, [r7, #4] 802154a: 681b ldr r3, [r3, #0] 802154c: 2b00 cmp r3, #0 802154e: d101 bne.n 8021554 return 0; 8021550: 2300 movs r3, #0 8021552: e000 b.n 8021556 else return 1; 8021554: 2301 movs r3, #1 } 8021556: 4618 mov r0, r3 8021558: 370c adds r7, #12 802155a: 46bd mov sp, r7 802155c: f85d 7b04 ldr.w r7, [sp], #4 8021560: 4770 bx lr 08021562 : /*-----------------------------------------------------------------------------------*/ void sys_sem_set_invalid(sys_sem_t *sem) { 8021562: b480 push {r7} 8021564: b083 sub sp, #12 8021566: af00 add r7, sp, #0 8021568: 6078 str r0, [r7, #4] *sem = SYS_SEM_NULL; 802156a: 687b ldr r3, [r7, #4] 802156c: 2200 movs r2, #0 802156e: 601a str r2, [r3, #0] } 8021570: bf00 nop 8021572: 370c adds r7, #12 8021574: 46bd mov sp, r7 8021576: f85d 7b04 ldr.w r7, [sp], #4 802157a: 4770 bx lr 0802157c : #else osMutexId_t lwip_sys_mutex; #endif // Initialize sys arch void sys_init(void) { 802157c: b580 push {r7, lr} 802157e: af00 add r7, sp, #0 #if (osCMSIS < 0x20000U) lwip_sys_mutex = osMutexCreate(osMutex(lwip_sys_mutex)); 8021580: 4803 ldr r0, [pc, #12] ; (8021590 ) 8021582: f7ee ff11 bl 80103a8 8021586: 4603 mov r3, r0 8021588: 4a02 ldr r2, [pc, #8] ; (8021594 ) 802158a: 6013 str r3, [r2, #0] #else lwip_sys_mutex = osMutexNew(NULL); #endif } 802158c: bf00 nop 802158e: bd80 pop {r7, pc} 8021590: 08026d00 .word 0x08026d00 8021594: 2401a5e4 .word 0x2401a5e4 08021598 : /* Mutexes*/ /*-----------------------------------------------------------------------------------*/ /*-----------------------------------------------------------------------------------*/ #if LWIP_COMPAT_MUTEX == 0 /* Create a new mutex*/ err_t sys_mutex_new(sys_mutex_t *mutex) { 8021598: b580 push {r7, lr} 802159a: b084 sub sp, #16 802159c: af00 add r7, sp, #0 802159e: 6078 str r0, [r7, #4] #if (osCMSIS < 0x20000U) osMutexDef(MUTEX); 80215a0: 2300 movs r3, #0 80215a2: 60bb str r3, [r7, #8] 80215a4: 2300 movs r3, #0 80215a6: 60fb str r3, [r7, #12] *mutex = osMutexCreate(osMutex(MUTEX)); 80215a8: f107 0308 add.w r3, r7, #8 80215ac: 4618 mov r0, r3 80215ae: f7ee fefb bl 80103a8 80215b2: 4602 mov r2, r0 80215b4: 687b ldr r3, [r7, #4] 80215b6: 601a str r2, [r3, #0] #else *mutex = osMutexNew(NULL); #endif if(*mutex == NULL) 80215b8: 687b ldr r3, [r7, #4] 80215ba: 681b ldr r3, [r3, #0] 80215bc: 2b00 cmp r3, #0 80215be: d102 bne.n 80215c6 { #if SYS_STATS ++lwip_stats.sys.mutex.err; #endif /* SYS_STATS */ return ERR_MEM; 80215c0: f04f 33ff mov.w r3, #4294967295 80215c4: e000 b.n 80215c8 ++lwip_stats.sys.mutex.used; if (lwip_stats.sys.mutex.max < lwip_stats.sys.mutex.used) { lwip_stats.sys.mutex.max = lwip_stats.sys.mutex.used; } #endif /* SYS_STATS */ return ERR_OK; 80215c6: 2300 movs r3, #0 } 80215c8: 4618 mov r0, r3 80215ca: 3710 adds r7, #16 80215cc: 46bd mov sp, r7 80215ce: bd80 pop {r7, pc} 080215d0 : osMutexDelete(*mutex); } /*-----------------------------------------------------------------------------------*/ /* Lock a mutex*/ void sys_mutex_lock(sys_mutex_t *mutex) { 80215d0: b580 push {r7, lr} 80215d2: b082 sub sp, #8 80215d4: af00 add r7, sp, #0 80215d6: 6078 str r0, [r7, #4] #if (osCMSIS < 0x20000U) osMutexWait(*mutex, osWaitForever); 80215d8: 687b ldr r3, [r7, #4] 80215da: 681b ldr r3, [r3, #0] 80215dc: f04f 31ff mov.w r1, #4294967295 80215e0: 4618 mov r0, r3 80215e2: f7ee fef9 bl 80103d8 #else osMutexAcquire(*mutex, osWaitForever); #endif } 80215e6: bf00 nop 80215e8: 3708 adds r7, #8 80215ea: 46bd mov sp, r7 80215ec: bd80 pop {r7, pc} 080215ee : /*-----------------------------------------------------------------------------------*/ /* Unlock a mutex*/ void sys_mutex_unlock(sys_mutex_t *mutex) { 80215ee: b580 push {r7, lr} 80215f0: b082 sub sp, #8 80215f2: af00 add r7, sp, #0 80215f4: 6078 str r0, [r7, #4] osMutexRelease(*mutex); 80215f6: 687b ldr r3, [r7, #4] 80215f8: 681b ldr r3, [r3, #0] 80215fa: 4618 mov r0, r3 80215fc: f7ee ff3a bl 8010474 } 8021600: bf00 nop 8021602: 3708 adds r7, #8 8021604: 46bd mov sp, r7 8021606: bd80 pop {r7, pc} 08021608 : function "thread()". The "arg" argument will be passed as an argument to the thread() function. The id of the new thread is returned. Both the id and the priority are system dependent. */ sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread , void *arg, int stacksize, int prio) { 8021608: b580 push {r7, lr} 802160a: b08c sub sp, #48 ; 0x30 802160c: af00 add r7, sp, #0 802160e: 60f8 str r0, [r7, #12] 8021610: 60b9 str r1, [r7, #8] 8021612: 607a str r2, [r7, #4] 8021614: 603b str r3, [r7, #0] #if (osCMSIS < 0x20000U) const osThreadDef_t os_thread_def = { (char *)name, (os_pthread)thread, (osPriority)prio, 0, stacksize}; 8021616: f107 0314 add.w r3, r7, #20 802161a: 2200 movs r2, #0 802161c: 601a str r2, [r3, #0] 802161e: 605a str r2, [r3, #4] 8021620: 609a str r2, [r3, #8] 8021622: 60da str r2, [r3, #12] 8021624: 611a str r2, [r3, #16] 8021626: 615a str r2, [r3, #20] 8021628: 619a str r2, [r3, #24] 802162a: 68fb ldr r3, [r7, #12] 802162c: 617b str r3, [r7, #20] 802162e: 68bb ldr r3, [r7, #8] 8021630: 61bb str r3, [r7, #24] 8021632: 6bbb ldr r3, [r7, #56] ; 0x38 8021634: b21b sxth r3, r3 8021636: 83bb strh r3, [r7, #28] 8021638: 683b ldr r3, [r7, #0] 802163a: 627b str r3, [r7, #36] ; 0x24 return osThreadCreate(&os_thread_def, arg); 802163c: f107 0314 add.w r3, r7, #20 8021640: 6879 ldr r1, [r7, #4] 8021642: 4618 mov r0, r3 8021644: f7ee fe50 bl 80102e8 8021648: 4603 mov r3, r0 .stack_size = stacksize, .priority = (osPriority_t)prio, }; return osThreadNew(thread, arg, &attributes); #endif } 802164a: 4618 mov r0, r3 802164c: 3730 adds r7, #48 ; 0x30 802164e: 46bd mov sp, r7 8021650: bd80 pop {r7, pc} ... 08021654 : Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS API is available */ sys_prot_t sys_arch_protect(void) { 8021654: b580 push {r7, lr} 8021656: af00 add r7, sp, #0 #if (osCMSIS < 0x20000U) osMutexWait(lwip_sys_mutex, osWaitForever); 8021658: 4b04 ldr r3, [pc, #16] ; (802166c ) 802165a: 681b ldr r3, [r3, #0] 802165c: f04f 31ff mov.w r1, #4294967295 8021660: 4618 mov r0, r3 8021662: f7ee feb9 bl 80103d8 #else osMutexAcquire(lwip_sys_mutex, osWaitForever); #endif return (sys_prot_t)1; 8021666: 2301 movs r3, #1 } 8021668: 4618 mov r0, r3 802166a: bd80 pop {r7, pc} 802166c: 2401a5e4 .word 0x2401a5e4 08021670 : Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS API is available */ void sys_arch_unprotect(sys_prot_t pval) { 8021670: b580 push {r7, lr} 8021672: b082 sub sp, #8 8021674: af00 add r7, sp, #0 8021676: 6078 str r0, [r7, #4] ( void ) pval; osMutexRelease(lwip_sys_mutex); 8021678: 4b04 ldr r3, [pc, #16] ; (802168c ) 802167a: 681b ldr r3, [r3, #0] 802167c: 4618 mov r0, r3 802167e: f7ee fef9 bl 8010474 } 8021682: bf00 nop 8021684: 3708 adds r7, #8 8021686: 46bd mov sp, r7 8021688: bd80 pop {r7, pc} 802168a: bf00 nop 802168c: 2401a5e4 .word 0x2401a5e4 08021690 : 8021690: 4b16 ldr r3, [pc, #88] ; (80216ec ) 8021692: b510 push {r4, lr} 8021694: 681c ldr r4, [r3, #0] 8021696: 6b23 ldr r3, [r4, #48] ; 0x30 8021698: b9b3 cbnz r3, 80216c8 802169a: 2018 movs r0, #24 802169c: f000 fc1c bl 8021ed8 80216a0: 4602 mov r2, r0 80216a2: 6320 str r0, [r4, #48] ; 0x30 80216a4: b920 cbnz r0, 80216b0 80216a6: 4b12 ldr r3, [pc, #72] ; (80216f0 ) 80216a8: 4812 ldr r0, [pc, #72] ; (80216f4 ) 80216aa: 2152 movs r1, #82 ; 0x52 80216ac: f000 fbaa bl 8021e04 <__assert_func> 80216b0: 4911 ldr r1, [pc, #68] ; (80216f8 ) 80216b2: 4b12 ldr r3, [pc, #72] ; (80216fc ) 80216b4: e9c0 1300 strd r1, r3, [r0] 80216b8: 4b11 ldr r3, [pc, #68] ; (8021700 ) 80216ba: 6083 str r3, [r0, #8] 80216bc: 230b movs r3, #11 80216be: 8183 strh r3, [r0, #12] 80216c0: 2100 movs r1, #0 80216c2: 2001 movs r0, #1 80216c4: e9c2 0104 strd r0, r1, [r2, #16] 80216c8: 6b21 ldr r1, [r4, #48] ; 0x30 80216ca: 480e ldr r0, [pc, #56] ; (8021704 ) 80216cc: 690b ldr r3, [r1, #16] 80216ce: 694c ldr r4, [r1, #20] 80216d0: 4a0d ldr r2, [pc, #52] ; (8021708 ) 80216d2: 4358 muls r0, r3 80216d4: fb02 0004 mla r0, r2, r4, r0 80216d8: fba3 3202 umull r3, r2, r3, r2 80216dc: 3301 adds r3, #1 80216de: eb40 0002 adc.w r0, r0, r2 80216e2: e9c1 3004 strd r3, r0, [r1, #16] 80216e6: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 80216ea: bd10 pop {r4, pc} 80216ec: 240000a0 .word 0x240000a0 80216f0: 08026d08 .word 0x08026d08 80216f4: 08026d1f .word 0x08026d1f 80216f8: abcd330e .word 0xabcd330e 80216fc: e66d1234 .word 0xe66d1234 8021700: 0005deec .word 0x0005deec 8021704: 5851f42d .word 0x5851f42d 8021708: 4c957f2d .word 0x4c957f2d 0802170c <_strtoul_l.constprop.0>: 802170c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 8021710: 4f36 ldr r7, [pc, #216] ; (80217ec <_strtoul_l.constprop.0+0xe0>) 8021712: 4686 mov lr, r0 8021714: 460d mov r5, r1 8021716: 4628 mov r0, r5 8021718: f815 4b01 ldrb.w r4, [r5], #1 802171c: 5d3e ldrb r6, [r7, r4] 802171e: f016 0608 ands.w r6, r6, #8 8021722: d1f8 bne.n 8021716 <_strtoul_l.constprop.0+0xa> 8021724: 2c2d cmp r4, #45 ; 0x2d 8021726: d130 bne.n 802178a <_strtoul_l.constprop.0+0x7e> 8021728: 782c ldrb r4, [r5, #0] 802172a: 2601 movs r6, #1 802172c: 1c85 adds r5, r0, #2 802172e: 2b00 cmp r3, #0 8021730: d057 beq.n 80217e2 <_strtoul_l.constprop.0+0xd6> 8021732: 2b10 cmp r3, #16 8021734: d109 bne.n 802174a <_strtoul_l.constprop.0+0x3e> 8021736: 2c30 cmp r4, #48 ; 0x30 8021738: d107 bne.n 802174a <_strtoul_l.constprop.0+0x3e> 802173a: 7828 ldrb r0, [r5, #0] 802173c: f000 00df and.w r0, r0, #223 ; 0xdf 8021740: 2858 cmp r0, #88 ; 0x58 8021742: d149 bne.n 80217d8 <_strtoul_l.constprop.0+0xcc> 8021744: 786c ldrb r4, [r5, #1] 8021746: 2310 movs r3, #16 8021748: 3502 adds r5, #2 802174a: f04f 38ff mov.w r8, #4294967295 802174e: 2700 movs r7, #0 8021750: fbb8 f8f3 udiv r8, r8, r3 8021754: fb03 f908 mul.w r9, r3, r8 8021758: ea6f 0909 mvn.w r9, r9 802175c: 4638 mov r0, r7 802175e: f1a4 0c30 sub.w ip, r4, #48 ; 0x30 8021762: f1bc 0f09 cmp.w ip, #9 8021766: d815 bhi.n 8021794 <_strtoul_l.constprop.0+0x88> 8021768: 4664 mov r4, ip 802176a: 42a3 cmp r3, r4 802176c: dd23 ble.n 80217b6 <_strtoul_l.constprop.0+0xaa> 802176e: f1b7 3fff cmp.w r7, #4294967295 8021772: d007 beq.n 8021784 <_strtoul_l.constprop.0+0x78> 8021774: 4580 cmp r8, r0 8021776: d31b bcc.n 80217b0 <_strtoul_l.constprop.0+0xa4> 8021778: d101 bne.n 802177e <_strtoul_l.constprop.0+0x72> 802177a: 45a1 cmp r9, r4 802177c: db18 blt.n 80217b0 <_strtoul_l.constprop.0+0xa4> 802177e: fb00 4003 mla r0, r0, r3, r4 8021782: 2701 movs r7, #1 8021784: f815 4b01 ldrb.w r4, [r5], #1 8021788: e7e9 b.n 802175e <_strtoul_l.constprop.0+0x52> 802178a: 2c2b cmp r4, #43 ; 0x2b 802178c: bf04 itt eq 802178e: 782c ldrbeq r4, [r5, #0] 8021790: 1c85 addeq r5, r0, #2 8021792: e7cc b.n 802172e <_strtoul_l.constprop.0+0x22> 8021794: f1a4 0c41 sub.w ip, r4, #65 ; 0x41 8021798: f1bc 0f19 cmp.w ip, #25 802179c: d801 bhi.n 80217a2 <_strtoul_l.constprop.0+0x96> 802179e: 3c37 subs r4, #55 ; 0x37 80217a0: e7e3 b.n 802176a <_strtoul_l.constprop.0+0x5e> 80217a2: f1a4 0c61 sub.w ip, r4, #97 ; 0x61 80217a6: f1bc 0f19 cmp.w ip, #25 80217aa: d804 bhi.n 80217b6 <_strtoul_l.constprop.0+0xaa> 80217ac: 3c57 subs r4, #87 ; 0x57 80217ae: e7dc b.n 802176a <_strtoul_l.constprop.0+0x5e> 80217b0: f04f 37ff mov.w r7, #4294967295 80217b4: e7e6 b.n 8021784 <_strtoul_l.constprop.0+0x78> 80217b6: 1c7b adds r3, r7, #1 80217b8: d106 bne.n 80217c8 <_strtoul_l.constprop.0+0xbc> 80217ba: 2322 movs r3, #34 ; 0x22 80217bc: f8ce 3000 str.w r3, [lr] 80217c0: 4638 mov r0, r7 80217c2: b932 cbnz r2, 80217d2 <_strtoul_l.constprop.0+0xc6> 80217c4: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 80217c8: b106 cbz r6, 80217cc <_strtoul_l.constprop.0+0xc0> 80217ca: 4240 negs r0, r0 80217cc: 2a00 cmp r2, #0 80217ce: d0f9 beq.n 80217c4 <_strtoul_l.constprop.0+0xb8> 80217d0: b107 cbz r7, 80217d4 <_strtoul_l.constprop.0+0xc8> 80217d2: 1e69 subs r1, r5, #1 80217d4: 6011 str r1, [r2, #0] 80217d6: e7f5 b.n 80217c4 <_strtoul_l.constprop.0+0xb8> 80217d8: 2430 movs r4, #48 ; 0x30 80217da: 2b00 cmp r3, #0 80217dc: d1b5 bne.n 802174a <_strtoul_l.constprop.0+0x3e> 80217de: 2308 movs r3, #8 80217e0: e7b3 b.n 802174a <_strtoul_l.constprop.0+0x3e> 80217e2: 2c30 cmp r4, #48 ; 0x30 80217e4: d0a9 beq.n 802173a <_strtoul_l.constprop.0+0x2e> 80217e6: 230a movs r3, #10 80217e8: e7af b.n 802174a <_strtoul_l.constprop.0+0x3e> 80217ea: bf00 nop 80217ec: 08026d78 .word 0x08026d78 080217f0 : 80217f0: 4613 mov r3, r2 80217f2: 460a mov r2, r1 80217f4: 4601 mov r1, r0 80217f6: 4802 ldr r0, [pc, #8] ; (8021800 ) 80217f8: 6800 ldr r0, [r0, #0] 80217fa: f7ff bf87 b.w 802170c <_strtoul_l.constprop.0> 80217fe: bf00 nop 8021800: 240000a0 .word 0x240000a0 08021804 : 8021804: 2300 movs r3, #0 8021806: b510 push {r4, lr} 8021808: 4604 mov r4, r0 802180a: e9c0 3300 strd r3, r3, [r0] 802180e: e9c0 3304 strd r3, r3, [r0, #16] 8021812: 6083 str r3, [r0, #8] 8021814: 8181 strh r1, [r0, #12] 8021816: 6643 str r3, [r0, #100] ; 0x64 8021818: 81c2 strh r2, [r0, #14] 802181a: 6183 str r3, [r0, #24] 802181c: 4619 mov r1, r3 802181e: 2208 movs r2, #8 8021820: 305c adds r0, #92 ; 0x5c 8021822: f000 fa5d bl 8021ce0 8021826: 4b0d ldr r3, [pc, #52] ; (802185c ) 8021828: 6263 str r3, [r4, #36] ; 0x24 802182a: 4b0d ldr r3, [pc, #52] ; (8021860 ) 802182c: 62a3 str r3, [r4, #40] ; 0x28 802182e: 4b0d ldr r3, [pc, #52] ; (8021864 ) 8021830: 62e3 str r3, [r4, #44] ; 0x2c 8021832: 4b0d ldr r3, [pc, #52] ; (8021868 ) 8021834: 6323 str r3, [r4, #48] ; 0x30 8021836: 4b0d ldr r3, [pc, #52] ; (802186c ) 8021838: 6224 str r4, [r4, #32] 802183a: 429c cmp r4, r3 802183c: d006 beq.n 802184c 802183e: f103 0268 add.w r2, r3, #104 ; 0x68 8021842: 4294 cmp r4, r2 8021844: d002 beq.n 802184c 8021846: 33d0 adds r3, #208 ; 0xd0 8021848: 429c cmp r4, r3 802184a: d105 bne.n 8021858 802184c: f104 0058 add.w r0, r4, #88 ; 0x58 8021850: e8bd 4010 ldmia.w sp!, {r4, lr} 8021854: f000 bac4 b.w 8021de0 <__retarget_lock_init_recursive> 8021858: bd10 pop {r4, pc} 802185a: bf00 nop 802185c: 08021add .word 0x08021add 8021860: 08021aff .word 0x08021aff 8021864: 08021b37 .word 0x08021b37 8021868: 08021b5b .word 0x08021b5b 802186c: 2401a5e8 .word 0x2401a5e8 08021870 : 8021870: 4a02 ldr r2, [pc, #8] ; (802187c ) 8021872: 4903 ldr r1, [pc, #12] ; (8021880 ) 8021874: 4803 ldr r0, [pc, #12] ; (8021884 ) 8021876: f000 b869 b.w 802194c <_fwalk_sglue> 802187a: bf00 nop 802187c: 24000048 .word 0x24000048 8021880: 080229a5 .word 0x080229a5 8021884: 24000054 .word 0x24000054 08021888 : 8021888: 6841 ldr r1, [r0, #4] 802188a: 4b0c ldr r3, [pc, #48] ; (80218bc ) 802188c: 4299 cmp r1, r3 802188e: b510 push {r4, lr} 8021890: 4604 mov r4, r0 8021892: d001 beq.n 8021898 8021894: f001 f886 bl 80229a4 <_fflush_r> 8021898: 68a1 ldr r1, [r4, #8] 802189a: 4b09 ldr r3, [pc, #36] ; (80218c0 ) 802189c: 4299 cmp r1, r3 802189e: d002 beq.n 80218a6 80218a0: 4620 mov r0, r4 80218a2: f001 f87f bl 80229a4 <_fflush_r> 80218a6: 68e1 ldr r1, [r4, #12] 80218a8: 4b06 ldr r3, [pc, #24] ; (80218c4 ) 80218aa: 4299 cmp r1, r3 80218ac: d004 beq.n 80218b8 80218ae: 4620 mov r0, r4 80218b0: e8bd 4010 ldmia.w sp!, {r4, lr} 80218b4: f001 b876 b.w 80229a4 <_fflush_r> 80218b8: bd10 pop {r4, pc} 80218ba: bf00 nop 80218bc: 2401a5e8 .word 0x2401a5e8 80218c0: 2401a650 .word 0x2401a650 80218c4: 2401a6b8 .word 0x2401a6b8 080218c8 : 80218c8: b510 push {r4, lr} 80218ca: 4b0b ldr r3, [pc, #44] ; (80218f8 ) 80218cc: 4c0b ldr r4, [pc, #44] ; (80218fc ) 80218ce: 4a0c ldr r2, [pc, #48] ; (8021900 ) 80218d0: 601a str r2, [r3, #0] 80218d2: 4620 mov r0, r4 80218d4: 2200 movs r2, #0 80218d6: 2104 movs r1, #4 80218d8: f7ff ff94 bl 8021804 80218dc: f104 0068 add.w r0, r4, #104 ; 0x68 80218e0: 2201 movs r2, #1 80218e2: 2109 movs r1, #9 80218e4: f7ff ff8e bl 8021804 80218e8: f104 00d0 add.w r0, r4, #208 ; 0xd0 80218ec: 2202 movs r2, #2 80218ee: e8bd 4010 ldmia.w sp!, {r4, lr} 80218f2: 2112 movs r1, #18 80218f4: f7ff bf86 b.w 8021804 80218f8: 2401a720 .word 0x2401a720 80218fc: 2401a5e8 .word 0x2401a5e8 8021900: 08021871 .word 0x08021871 08021904 <__sfp_lock_acquire>: 8021904: 4801 ldr r0, [pc, #4] ; (802190c <__sfp_lock_acquire+0x8>) 8021906: f000 ba6c b.w 8021de2 <__retarget_lock_acquire_recursive> 802190a: bf00 nop 802190c: 2401a725 .word 0x2401a725 08021910 <__sfp_lock_release>: 8021910: 4801 ldr r0, [pc, #4] ; (8021918 <__sfp_lock_release+0x8>) 8021912: f000 ba67 b.w 8021de4 <__retarget_lock_release_recursive> 8021916: bf00 nop 8021918: 2401a725 .word 0x2401a725 0802191c <__sinit>: 802191c: b510 push {r4, lr} 802191e: 4604 mov r4, r0 8021920: f7ff fff0 bl 8021904 <__sfp_lock_acquire> 8021924: 6a23 ldr r3, [r4, #32] 8021926: b11b cbz r3, 8021930 <__sinit+0x14> 8021928: e8bd 4010 ldmia.w sp!, {r4, lr} 802192c: f7ff bff0 b.w 8021910 <__sfp_lock_release> 8021930: 4b04 ldr r3, [pc, #16] ; (8021944 <__sinit+0x28>) 8021932: 6223 str r3, [r4, #32] 8021934: 4b04 ldr r3, [pc, #16] ; (8021948 <__sinit+0x2c>) 8021936: 681b ldr r3, [r3, #0] 8021938: 2b00 cmp r3, #0 802193a: d1f5 bne.n 8021928 <__sinit+0xc> 802193c: f7ff ffc4 bl 80218c8 8021940: e7f2 b.n 8021928 <__sinit+0xc> 8021942: bf00 nop 8021944: 08021889 .word 0x08021889 8021948: 2401a720 .word 0x2401a720 0802194c <_fwalk_sglue>: 802194c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8021950: 4607 mov r7, r0 8021952: 4688 mov r8, r1 8021954: 4614 mov r4, r2 8021956: 2600 movs r6, #0 8021958: e9d4 9501 ldrd r9, r5, [r4, #4] 802195c: f1b9 0901 subs.w r9, r9, #1 8021960: d505 bpl.n 802196e <_fwalk_sglue+0x22> 8021962: 6824 ldr r4, [r4, #0] 8021964: 2c00 cmp r4, #0 8021966: d1f7 bne.n 8021958 <_fwalk_sglue+0xc> 8021968: 4630 mov r0, r6 802196a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 802196e: 89ab ldrh r3, [r5, #12] 8021970: 2b01 cmp r3, #1 8021972: d907 bls.n 8021984 <_fwalk_sglue+0x38> 8021974: f9b5 300e ldrsh.w r3, [r5, #14] 8021978: 3301 adds r3, #1 802197a: d003 beq.n 8021984 <_fwalk_sglue+0x38> 802197c: 4629 mov r1, r5 802197e: 4638 mov r0, r7 8021980: 47c0 blx r8 8021982: 4306 orrs r6, r0 8021984: 3568 adds r5, #104 ; 0x68 8021986: e7e9 b.n 802195c <_fwalk_sglue+0x10> 08021988 : 8021988: b40f push {r0, r1, r2, r3} 802198a: b507 push {r0, r1, r2, lr} 802198c: 4906 ldr r1, [pc, #24] ; (80219a8 ) 802198e: ab04 add r3, sp, #16 8021990: 6808 ldr r0, [r1, #0] 8021992: f853 2b04 ldr.w r2, [r3], #4 8021996: 6881 ldr r1, [r0, #8] 8021998: 9301 str r3, [sp, #4] 802199a: f000 fcd3 bl 8022344 <_vfiprintf_r> 802199e: b003 add sp, #12 80219a0: f85d eb04 ldr.w lr, [sp], #4 80219a4: b004 add sp, #16 80219a6: 4770 bx lr 80219a8: 240000a0 .word 0x240000a0 080219ac : 80219ac: 4b02 ldr r3, [pc, #8] ; (80219b8 ) 80219ae: 4601 mov r1, r0 80219b0: 6818 ldr r0, [r3, #0] 80219b2: 6882 ldr r2, [r0, #8] 80219b4: f001 b892 b.w 8022adc <_putc_r> 80219b8: 240000a0 .word 0x240000a0 080219bc <_puts_r>: 80219bc: 6a03 ldr r3, [r0, #32] 80219be: b570 push {r4, r5, r6, lr} 80219c0: 6884 ldr r4, [r0, #8] 80219c2: 4605 mov r5, r0 80219c4: 460e mov r6, r1 80219c6: b90b cbnz r3, 80219cc <_puts_r+0x10> 80219c8: f7ff ffa8 bl 802191c <__sinit> 80219cc: 6e63 ldr r3, [r4, #100] ; 0x64 80219ce: 07db lsls r3, r3, #31 80219d0: d405 bmi.n 80219de <_puts_r+0x22> 80219d2: 89a3 ldrh r3, [r4, #12] 80219d4: 0598 lsls r0, r3, #22 80219d6: d402 bmi.n 80219de <_puts_r+0x22> 80219d8: 6da0 ldr r0, [r4, #88] ; 0x58 80219da: f000 fa02 bl 8021de2 <__retarget_lock_acquire_recursive> 80219de: 89a3 ldrh r3, [r4, #12] 80219e0: 0719 lsls r1, r3, #28 80219e2: d513 bpl.n 8021a0c <_puts_r+0x50> 80219e4: 6923 ldr r3, [r4, #16] 80219e6: b18b cbz r3, 8021a0c <_puts_r+0x50> 80219e8: 3e01 subs r6, #1 80219ea: 68a3 ldr r3, [r4, #8] 80219ec: f816 1f01 ldrb.w r1, [r6, #1]! 80219f0: 3b01 subs r3, #1 80219f2: 60a3 str r3, [r4, #8] 80219f4: b9e9 cbnz r1, 8021a32 <_puts_r+0x76> 80219f6: 2b00 cmp r3, #0 80219f8: da2e bge.n 8021a58 <_puts_r+0x9c> 80219fa: 4622 mov r2, r4 80219fc: 210a movs r1, #10 80219fe: 4628 mov r0, r5 8021a00: f000 f8af bl 8021b62 <__swbuf_r> 8021a04: 3001 adds r0, #1 8021a06: d007 beq.n 8021a18 <_puts_r+0x5c> 8021a08: 250a movs r5, #10 8021a0a: e007 b.n 8021a1c <_puts_r+0x60> 8021a0c: 4621 mov r1, r4 8021a0e: 4628 mov r0, r5 8021a10: f000 f8e4 bl 8021bdc <__swsetup_r> 8021a14: 2800 cmp r0, #0 8021a16: d0e7 beq.n 80219e8 <_puts_r+0x2c> 8021a18: f04f 35ff mov.w r5, #4294967295 8021a1c: 6e63 ldr r3, [r4, #100] ; 0x64 8021a1e: 07da lsls r2, r3, #31 8021a20: d405 bmi.n 8021a2e <_puts_r+0x72> 8021a22: 89a3 ldrh r3, [r4, #12] 8021a24: 059b lsls r3, r3, #22 8021a26: d402 bmi.n 8021a2e <_puts_r+0x72> 8021a28: 6da0 ldr r0, [r4, #88] ; 0x58 8021a2a: f000 f9db bl 8021de4 <__retarget_lock_release_recursive> 8021a2e: 4628 mov r0, r5 8021a30: bd70 pop {r4, r5, r6, pc} 8021a32: 2b00 cmp r3, #0 8021a34: da04 bge.n 8021a40 <_puts_r+0x84> 8021a36: 69a2 ldr r2, [r4, #24] 8021a38: 429a cmp r2, r3 8021a3a: dc06 bgt.n 8021a4a <_puts_r+0x8e> 8021a3c: 290a cmp r1, #10 8021a3e: d004 beq.n 8021a4a <_puts_r+0x8e> 8021a40: 6823 ldr r3, [r4, #0] 8021a42: 1c5a adds r2, r3, #1 8021a44: 6022 str r2, [r4, #0] 8021a46: 7019 strb r1, [r3, #0] 8021a48: e7cf b.n 80219ea <_puts_r+0x2e> 8021a4a: 4622 mov r2, r4 8021a4c: 4628 mov r0, r5 8021a4e: f000 f888 bl 8021b62 <__swbuf_r> 8021a52: 3001 adds r0, #1 8021a54: d1c9 bne.n 80219ea <_puts_r+0x2e> 8021a56: e7df b.n 8021a18 <_puts_r+0x5c> 8021a58: 6823 ldr r3, [r4, #0] 8021a5a: 250a movs r5, #10 8021a5c: 1c5a adds r2, r3, #1 8021a5e: 6022 str r2, [r4, #0] 8021a60: 701d strb r5, [r3, #0] 8021a62: e7db b.n 8021a1c <_puts_r+0x60> 08021a64 : 8021a64: 4b02 ldr r3, [pc, #8] ; (8021a70 ) 8021a66: 4601 mov r1, r0 8021a68: 6818 ldr r0, [r3, #0] 8021a6a: f7ff bfa7 b.w 80219bc <_puts_r> 8021a6e: bf00 nop 8021a70: 240000a0 .word 0x240000a0 08021a74 : 8021a74: b40c push {r2, r3} 8021a76: b530 push {r4, r5, lr} 8021a78: 4b17 ldr r3, [pc, #92] ; (8021ad8 ) 8021a7a: 1e0c subs r4, r1, #0 8021a7c: 681d ldr r5, [r3, #0] 8021a7e: b09d sub sp, #116 ; 0x74 8021a80: da08 bge.n 8021a94 8021a82: 238b movs r3, #139 ; 0x8b 8021a84: 602b str r3, [r5, #0] 8021a86: f04f 30ff mov.w r0, #4294967295 8021a8a: b01d add sp, #116 ; 0x74 8021a8c: e8bd 4030 ldmia.w sp!, {r4, r5, lr} 8021a90: b002 add sp, #8 8021a92: 4770 bx lr 8021a94: f44f 7302 mov.w r3, #520 ; 0x208 8021a98: f8ad 3014 strh.w r3, [sp, #20] 8021a9c: bf14 ite ne 8021a9e: f104 33ff addne.w r3, r4, #4294967295 8021aa2: 4623 moveq r3, r4 8021aa4: 9304 str r3, [sp, #16] 8021aa6: 9307 str r3, [sp, #28] 8021aa8: f64f 73ff movw r3, #65535 ; 0xffff 8021aac: 9002 str r0, [sp, #8] 8021aae: 9006 str r0, [sp, #24] 8021ab0: f8ad 3016 strh.w r3, [sp, #22] 8021ab4: 9a20 ldr r2, [sp, #128] ; 0x80 8021ab6: ab21 add r3, sp, #132 ; 0x84 8021ab8: a902 add r1, sp, #8 8021aba: 4628 mov r0, r5 8021abc: 9301 str r3, [sp, #4] 8021abe: f000 fb19 bl 80220f4 <_svfiprintf_r> 8021ac2: 1c43 adds r3, r0, #1 8021ac4: bfbc itt lt 8021ac6: 238b movlt r3, #139 ; 0x8b 8021ac8: 602b strlt r3, [r5, #0] 8021aca: 2c00 cmp r4, #0 8021acc: d0dd beq.n 8021a8a 8021ace: 9b02 ldr r3, [sp, #8] 8021ad0: 2200 movs r2, #0 8021ad2: 701a strb r2, [r3, #0] 8021ad4: e7d9 b.n 8021a8a 8021ad6: bf00 nop 8021ad8: 240000a0 .word 0x240000a0 08021adc <__sread>: 8021adc: b510 push {r4, lr} 8021ade: 460c mov r4, r1 8021ae0: f9b1 100e ldrsh.w r1, [r1, #14] 8021ae4: f000 f934 bl 8021d50 <_read_r> 8021ae8: 2800 cmp r0, #0 8021aea: bfab itete ge 8021aec: 6d63 ldrge r3, [r4, #84] ; 0x54 8021aee: 89a3 ldrhlt r3, [r4, #12] 8021af0: 181b addge r3, r3, r0 8021af2: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 8021af6: bfac ite ge 8021af8: 6563 strge r3, [r4, #84] ; 0x54 8021afa: 81a3 strhlt r3, [r4, #12] 8021afc: bd10 pop {r4, pc} 08021afe <__swrite>: 8021afe: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8021b02: 461f mov r7, r3 8021b04: 898b ldrh r3, [r1, #12] 8021b06: 05db lsls r3, r3, #23 8021b08: 4605 mov r5, r0 8021b0a: 460c mov r4, r1 8021b0c: 4616 mov r6, r2 8021b0e: d505 bpl.n 8021b1c <__swrite+0x1e> 8021b10: f9b1 100e ldrsh.w r1, [r1, #14] 8021b14: 2302 movs r3, #2 8021b16: 2200 movs r2, #0 8021b18: f000 f908 bl 8021d2c <_lseek_r> 8021b1c: 89a3 ldrh r3, [r4, #12] 8021b1e: f9b4 100e ldrsh.w r1, [r4, #14] 8021b22: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8021b26: 81a3 strh r3, [r4, #12] 8021b28: 4632 mov r2, r6 8021b2a: 463b mov r3, r7 8021b2c: 4628 mov r0, r5 8021b2e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8021b32: f000 b91f b.w 8021d74 <_write_r> 08021b36 <__sseek>: 8021b36: b510 push {r4, lr} 8021b38: 460c mov r4, r1 8021b3a: f9b1 100e ldrsh.w r1, [r1, #14] 8021b3e: f000 f8f5 bl 8021d2c <_lseek_r> 8021b42: 1c43 adds r3, r0, #1 8021b44: 89a3 ldrh r3, [r4, #12] 8021b46: bf15 itete ne 8021b48: 6560 strne r0, [r4, #84] ; 0x54 8021b4a: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 8021b4e: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 8021b52: 81a3 strheq r3, [r4, #12] 8021b54: bf18 it ne 8021b56: 81a3 strhne r3, [r4, #12] 8021b58: bd10 pop {r4, pc} 08021b5a <__sclose>: 8021b5a: f9b1 100e ldrsh.w r1, [r1, #14] 8021b5e: f000 b8d5 b.w 8021d0c <_close_r> 08021b62 <__swbuf_r>: 8021b62: b5f8 push {r3, r4, r5, r6, r7, lr} 8021b64: 460e mov r6, r1 8021b66: 4614 mov r4, r2 8021b68: 4605 mov r5, r0 8021b6a: b118 cbz r0, 8021b74 <__swbuf_r+0x12> 8021b6c: 6a03 ldr r3, [r0, #32] 8021b6e: b90b cbnz r3, 8021b74 <__swbuf_r+0x12> 8021b70: f7ff fed4 bl 802191c <__sinit> 8021b74: 69a3 ldr r3, [r4, #24] 8021b76: 60a3 str r3, [r4, #8] 8021b78: 89a3 ldrh r3, [r4, #12] 8021b7a: 071a lsls r2, r3, #28 8021b7c: d525 bpl.n 8021bca <__swbuf_r+0x68> 8021b7e: 6923 ldr r3, [r4, #16] 8021b80: b31b cbz r3, 8021bca <__swbuf_r+0x68> 8021b82: 6823 ldr r3, [r4, #0] 8021b84: 6922 ldr r2, [r4, #16] 8021b86: 1a98 subs r0, r3, r2 8021b88: 6963 ldr r3, [r4, #20] 8021b8a: b2f6 uxtb r6, r6 8021b8c: 4283 cmp r3, r0 8021b8e: 4637 mov r7, r6 8021b90: dc04 bgt.n 8021b9c <__swbuf_r+0x3a> 8021b92: 4621 mov r1, r4 8021b94: 4628 mov r0, r5 8021b96: f000 ff05 bl 80229a4 <_fflush_r> 8021b9a: b9e0 cbnz r0, 8021bd6 <__swbuf_r+0x74> 8021b9c: 68a3 ldr r3, [r4, #8] 8021b9e: 3b01 subs r3, #1 8021ba0: 60a3 str r3, [r4, #8] 8021ba2: 6823 ldr r3, [r4, #0] 8021ba4: 1c5a adds r2, r3, #1 8021ba6: 6022 str r2, [r4, #0] 8021ba8: 701e strb r6, [r3, #0] 8021baa: 6962 ldr r2, [r4, #20] 8021bac: 1c43 adds r3, r0, #1 8021bae: 429a cmp r2, r3 8021bb0: d004 beq.n 8021bbc <__swbuf_r+0x5a> 8021bb2: 89a3 ldrh r3, [r4, #12] 8021bb4: 07db lsls r3, r3, #31 8021bb6: d506 bpl.n 8021bc6 <__swbuf_r+0x64> 8021bb8: 2e0a cmp r6, #10 8021bba: d104 bne.n 8021bc6 <__swbuf_r+0x64> 8021bbc: 4621 mov r1, r4 8021bbe: 4628 mov r0, r5 8021bc0: f000 fef0 bl 80229a4 <_fflush_r> 8021bc4: b938 cbnz r0, 8021bd6 <__swbuf_r+0x74> 8021bc6: 4638 mov r0, r7 8021bc8: bdf8 pop {r3, r4, r5, r6, r7, pc} 8021bca: 4621 mov r1, r4 8021bcc: 4628 mov r0, r5 8021bce: f000 f805 bl 8021bdc <__swsetup_r> 8021bd2: 2800 cmp r0, #0 8021bd4: d0d5 beq.n 8021b82 <__swbuf_r+0x20> 8021bd6: f04f 37ff mov.w r7, #4294967295 8021bda: e7f4 b.n 8021bc6 <__swbuf_r+0x64> 08021bdc <__swsetup_r>: 8021bdc: b538 push {r3, r4, r5, lr} 8021bde: 4b2a ldr r3, [pc, #168] ; (8021c88 <__swsetup_r+0xac>) 8021be0: 4605 mov r5, r0 8021be2: 6818 ldr r0, [r3, #0] 8021be4: 460c mov r4, r1 8021be6: b118 cbz r0, 8021bf0 <__swsetup_r+0x14> 8021be8: 6a03 ldr r3, [r0, #32] 8021bea: b90b cbnz r3, 8021bf0 <__swsetup_r+0x14> 8021bec: f7ff fe96 bl 802191c <__sinit> 8021bf0: 89a3 ldrh r3, [r4, #12] 8021bf2: f9b4 200c ldrsh.w r2, [r4, #12] 8021bf6: 0718 lsls r0, r3, #28 8021bf8: d422 bmi.n 8021c40 <__swsetup_r+0x64> 8021bfa: 06d9 lsls r1, r3, #27 8021bfc: d407 bmi.n 8021c0e <__swsetup_r+0x32> 8021bfe: 2309 movs r3, #9 8021c00: 602b str r3, [r5, #0] 8021c02: f042 0340 orr.w r3, r2, #64 ; 0x40 8021c06: 81a3 strh r3, [r4, #12] 8021c08: f04f 30ff mov.w r0, #4294967295 8021c0c: e034 b.n 8021c78 <__swsetup_r+0x9c> 8021c0e: 0758 lsls r0, r3, #29 8021c10: d512 bpl.n 8021c38 <__swsetup_r+0x5c> 8021c12: 6b61 ldr r1, [r4, #52] ; 0x34 8021c14: b141 cbz r1, 8021c28 <__swsetup_r+0x4c> 8021c16: f104 0344 add.w r3, r4, #68 ; 0x44 8021c1a: 4299 cmp r1, r3 8021c1c: d002 beq.n 8021c24 <__swsetup_r+0x48> 8021c1e: 4628 mov r0, r5 8021c20: f000 f90e bl 8021e40 <_free_r> 8021c24: 2300 movs r3, #0 8021c26: 6363 str r3, [r4, #52] ; 0x34 8021c28: 89a3 ldrh r3, [r4, #12] 8021c2a: f023 0324 bic.w r3, r3, #36 ; 0x24 8021c2e: 81a3 strh r3, [r4, #12] 8021c30: 2300 movs r3, #0 8021c32: 6063 str r3, [r4, #4] 8021c34: 6923 ldr r3, [r4, #16] 8021c36: 6023 str r3, [r4, #0] 8021c38: 89a3 ldrh r3, [r4, #12] 8021c3a: f043 0308 orr.w r3, r3, #8 8021c3e: 81a3 strh r3, [r4, #12] 8021c40: 6923 ldr r3, [r4, #16] 8021c42: b94b cbnz r3, 8021c58 <__swsetup_r+0x7c> 8021c44: 89a3 ldrh r3, [r4, #12] 8021c46: f403 7320 and.w r3, r3, #640 ; 0x280 8021c4a: f5b3 7f00 cmp.w r3, #512 ; 0x200 8021c4e: d003 beq.n 8021c58 <__swsetup_r+0x7c> 8021c50: 4621 mov r1, r4 8021c52: 4628 mov r0, r5 8021c54: f000 ff06 bl 8022a64 <__smakebuf_r> 8021c58: 89a0 ldrh r0, [r4, #12] 8021c5a: f9b4 200c ldrsh.w r2, [r4, #12] 8021c5e: f010 0301 ands.w r3, r0, #1 8021c62: d00a beq.n 8021c7a <__swsetup_r+0x9e> 8021c64: 2300 movs r3, #0 8021c66: 60a3 str r3, [r4, #8] 8021c68: 6963 ldr r3, [r4, #20] 8021c6a: 425b negs r3, r3 8021c6c: 61a3 str r3, [r4, #24] 8021c6e: 6923 ldr r3, [r4, #16] 8021c70: b943 cbnz r3, 8021c84 <__swsetup_r+0xa8> 8021c72: f010 0080 ands.w r0, r0, #128 ; 0x80 8021c76: d1c4 bne.n 8021c02 <__swsetup_r+0x26> 8021c78: bd38 pop {r3, r4, r5, pc} 8021c7a: 0781 lsls r1, r0, #30 8021c7c: bf58 it pl 8021c7e: 6963 ldrpl r3, [r4, #20] 8021c80: 60a3 str r3, [r4, #8] 8021c82: e7f4 b.n 8021c6e <__swsetup_r+0x92> 8021c84: 2000 movs r0, #0 8021c86: e7f7 b.n 8021c78 <__swsetup_r+0x9c> 8021c88: 240000a0 .word 0x240000a0 08021c8c : 8021c8c: b510 push {r4, lr} 8021c8e: 3901 subs r1, #1 8021c90: 4402 add r2, r0 8021c92: 4290 cmp r0, r2 8021c94: d101 bne.n 8021c9a 8021c96: 2000 movs r0, #0 8021c98: e005 b.n 8021ca6 8021c9a: 7803 ldrb r3, [r0, #0] 8021c9c: f811 4f01 ldrb.w r4, [r1, #1]! 8021ca0: 42a3 cmp r3, r4 8021ca2: d001 beq.n 8021ca8 8021ca4: 1b18 subs r0, r3, r4 8021ca6: bd10 pop {r4, pc} 8021ca8: 3001 adds r0, #1 8021caa: e7f2 b.n 8021c92 08021cac : 8021cac: 4288 cmp r0, r1 8021cae: b510 push {r4, lr} 8021cb0: eb01 0402 add.w r4, r1, r2 8021cb4: d902 bls.n 8021cbc 8021cb6: 4284 cmp r4, r0 8021cb8: 4623 mov r3, r4 8021cba: d807 bhi.n 8021ccc 8021cbc: 1e43 subs r3, r0, #1 8021cbe: 42a1 cmp r1, r4 8021cc0: d008 beq.n 8021cd4 8021cc2: f811 2b01 ldrb.w r2, [r1], #1 8021cc6: f803 2f01 strb.w r2, [r3, #1]! 8021cca: e7f8 b.n 8021cbe 8021ccc: 4402 add r2, r0 8021cce: 4601 mov r1, r0 8021cd0: 428a cmp r2, r1 8021cd2: d100 bne.n 8021cd6 8021cd4: bd10 pop {r4, pc} 8021cd6: f813 4d01 ldrb.w r4, [r3, #-1]! 8021cda: f802 4d01 strb.w r4, [r2, #-1]! 8021cde: e7f7 b.n 8021cd0 08021ce0 : 8021ce0: 4402 add r2, r0 8021ce2: 4603 mov r3, r0 8021ce4: 4293 cmp r3, r2 8021ce6: d100 bne.n 8021cea 8021ce8: 4770 bx lr 8021cea: f803 1b01 strb.w r1, [r3], #1 8021cee: e7f9 b.n 8021ce4 08021cf0 : 8021cf0: b2c9 uxtb r1, r1 8021cf2: 4603 mov r3, r0 8021cf4: f810 2b01 ldrb.w r2, [r0], #1 8021cf8: b11a cbz r2, 8021d02 8021cfa: 428a cmp r2, r1 8021cfc: d1f9 bne.n 8021cf2 8021cfe: 4618 mov r0, r3 8021d00: 4770 bx lr 8021d02: 2900 cmp r1, #0 8021d04: bf18 it ne 8021d06: 2300 movne r3, #0 8021d08: e7f9 b.n 8021cfe ... 08021d0c <_close_r>: 8021d0c: b538 push {r3, r4, r5, lr} 8021d0e: 4d06 ldr r5, [pc, #24] ; (8021d28 <_close_r+0x1c>) 8021d10: 2300 movs r3, #0 8021d12: 4604 mov r4, r0 8021d14: 4608 mov r0, r1 8021d16: 602b str r3, [r5, #0] 8021d18: f7e0 f855 bl 8001dc6 <_close> 8021d1c: 1c43 adds r3, r0, #1 8021d1e: d102 bne.n 8021d26 <_close_r+0x1a> 8021d20: 682b ldr r3, [r5, #0] 8021d22: b103 cbz r3, 8021d26 <_close_r+0x1a> 8021d24: 6023 str r3, [r4, #0] 8021d26: bd38 pop {r3, r4, r5, pc} 8021d28: 2401a5e0 .word 0x2401a5e0 08021d2c <_lseek_r>: 8021d2c: b538 push {r3, r4, r5, lr} 8021d2e: 4d07 ldr r5, [pc, #28] ; (8021d4c <_lseek_r+0x20>) 8021d30: 4604 mov r4, r0 8021d32: 4608 mov r0, r1 8021d34: 4611 mov r1, r2 8021d36: 2200 movs r2, #0 8021d38: 602a str r2, [r5, #0] 8021d3a: 461a mov r2, r3 8021d3c: f7e0 f86a bl 8001e14 <_lseek> 8021d40: 1c43 adds r3, r0, #1 8021d42: d102 bne.n 8021d4a <_lseek_r+0x1e> 8021d44: 682b ldr r3, [r5, #0] 8021d46: b103 cbz r3, 8021d4a <_lseek_r+0x1e> 8021d48: 6023 str r3, [r4, #0] 8021d4a: bd38 pop {r3, r4, r5, pc} 8021d4c: 2401a5e0 .word 0x2401a5e0 08021d50 <_read_r>: 8021d50: b538 push {r3, r4, r5, lr} 8021d52: 4d07 ldr r5, [pc, #28] ; (8021d70 <_read_r+0x20>) 8021d54: 4604 mov r4, r0 8021d56: 4608 mov r0, r1 8021d58: 4611 mov r1, r2 8021d5a: 2200 movs r2, #0 8021d5c: 602a str r2, [r5, #0] 8021d5e: 461a mov r2, r3 8021d60: f7e0 f814 bl 8001d8c <_read> 8021d64: 1c43 adds r3, r0, #1 8021d66: d102 bne.n 8021d6e <_read_r+0x1e> 8021d68: 682b ldr r3, [r5, #0] 8021d6a: b103 cbz r3, 8021d6e <_read_r+0x1e> 8021d6c: 6023 str r3, [r4, #0] 8021d6e: bd38 pop {r3, r4, r5, pc} 8021d70: 2401a5e0 .word 0x2401a5e0 08021d74 <_write_r>: 8021d74: b538 push {r3, r4, r5, lr} 8021d76: 4d07 ldr r5, [pc, #28] ; (8021d94 <_write_r+0x20>) 8021d78: 4604 mov r4, r0 8021d7a: 4608 mov r0, r1 8021d7c: 4611 mov r1, r2 8021d7e: 2200 movs r2, #0 8021d80: 602a str r2, [r5, #0] 8021d82: 461a mov r2, r3 8021d84: f7de fd11 bl 80007aa <_write> 8021d88: 1c43 adds r3, r0, #1 8021d8a: d102 bne.n 8021d92 <_write_r+0x1e> 8021d8c: 682b ldr r3, [r5, #0] 8021d8e: b103 cbz r3, 8021d92 <_write_r+0x1e> 8021d90: 6023 str r3, [r4, #0] 8021d92: bd38 pop {r3, r4, r5, pc} 8021d94: 2401a5e0 .word 0x2401a5e0 08021d98 <__libc_init_array>: 8021d98: b570 push {r4, r5, r6, lr} 8021d9a: 4d0d ldr r5, [pc, #52] ; (8021dd0 <__libc_init_array+0x38>) 8021d9c: 4c0d ldr r4, [pc, #52] ; (8021dd4 <__libc_init_array+0x3c>) 8021d9e: 1b64 subs r4, r4, r5 8021da0: 10a4 asrs r4, r4, #2 8021da2: 2600 movs r6, #0 8021da4: 42a6 cmp r6, r4 8021da6: d109 bne.n 8021dbc <__libc_init_array+0x24> 8021da8: 4d0b ldr r5, [pc, #44] ; (8021dd8 <__libc_init_array+0x40>) 8021daa: 4c0c ldr r4, [pc, #48] ; (8021ddc <__libc_init_array+0x44>) 8021dac: f000 ff7e bl 8022cac <_init> 8021db0: 1b64 subs r4, r4, r5 8021db2: 10a4 asrs r4, r4, #2 8021db4: 2600 movs r6, #0 8021db6: 42a6 cmp r6, r4 8021db8: d105 bne.n 8021dc6 <__libc_init_array+0x2e> 8021dba: bd70 pop {r4, r5, r6, pc} 8021dbc: f855 3b04 ldr.w r3, [r5], #4 8021dc0: 4798 blx r3 8021dc2: 3601 adds r6, #1 8021dc4: e7ee b.n 8021da4 <__libc_init_array+0xc> 8021dc6: f855 3b04 ldr.w r3, [r5], #4 8021dca: 4798 blx r3 8021dcc: 3601 adds r6, #1 8021dce: e7f2 b.n 8021db6 <__libc_init_array+0x1e> 8021dd0: 08026ef0 .word 0x08026ef0 8021dd4: 08026ef0 .word 0x08026ef0 8021dd8: 08026ef0 .word 0x08026ef0 8021ddc: 08026ef4 .word 0x08026ef4 08021de0 <__retarget_lock_init_recursive>: 8021de0: 4770 bx lr 08021de2 <__retarget_lock_acquire_recursive>: 8021de2: 4770 bx lr 08021de4 <__retarget_lock_release_recursive>: 8021de4: 4770 bx lr 08021de6 : 8021de6: 440a add r2, r1 8021de8: 4291 cmp r1, r2 8021dea: f100 33ff add.w r3, r0, #4294967295 8021dee: d100 bne.n 8021df2 8021df0: 4770 bx lr 8021df2: b510 push {r4, lr} 8021df4: f811 4b01 ldrb.w r4, [r1], #1 8021df8: f803 4f01 strb.w r4, [r3, #1]! 8021dfc: 4291 cmp r1, r2 8021dfe: d1f9 bne.n 8021df4 8021e00: bd10 pop {r4, pc} ... 08021e04 <__assert_func>: 8021e04: b51f push {r0, r1, r2, r3, r4, lr} 8021e06: 4614 mov r4, r2 8021e08: 461a mov r2, r3 8021e0a: 4b09 ldr r3, [pc, #36] ; (8021e30 <__assert_func+0x2c>) 8021e0c: 681b ldr r3, [r3, #0] 8021e0e: 4605 mov r5, r0 8021e10: 68d8 ldr r0, [r3, #12] 8021e12: b14c cbz r4, 8021e28 <__assert_func+0x24> 8021e14: 4b07 ldr r3, [pc, #28] ; (8021e34 <__assert_func+0x30>) 8021e16: 9100 str r1, [sp, #0] 8021e18: e9cd 3401 strd r3, r4, [sp, #4] 8021e1c: 4906 ldr r1, [pc, #24] ; (8021e38 <__assert_func+0x34>) 8021e1e: 462b mov r3, r5 8021e20: f000 fde8 bl 80229f4 8021e24: f000 fec0 bl 8022ba8 8021e28: 4b04 ldr r3, [pc, #16] ; (8021e3c <__assert_func+0x38>) 8021e2a: 461c mov r4, r3 8021e2c: e7f3 b.n 8021e16 <__assert_func+0x12> 8021e2e: bf00 nop 8021e30: 240000a0 .word 0x240000a0 8021e34: 08026e78 .word 0x08026e78 8021e38: 08026e85 .word 0x08026e85 8021e3c: 08026eb3 .word 0x08026eb3 08021e40 <_free_r>: 8021e40: b537 push {r0, r1, r2, r4, r5, lr} 8021e42: 2900 cmp r1, #0 8021e44: d044 beq.n 8021ed0 <_free_r+0x90> 8021e46: f851 3c04 ldr.w r3, [r1, #-4] 8021e4a: 9001 str r0, [sp, #4] 8021e4c: 2b00 cmp r3, #0 8021e4e: f1a1 0404 sub.w r4, r1, #4 8021e52: bfb8 it lt 8021e54: 18e4 addlt r4, r4, r3 8021e56: f000 f8e7 bl 8022028 <__malloc_lock> 8021e5a: 4a1e ldr r2, [pc, #120] ; (8021ed4 <_free_r+0x94>) 8021e5c: 9801 ldr r0, [sp, #4] 8021e5e: 6813 ldr r3, [r2, #0] 8021e60: b933 cbnz r3, 8021e70 <_free_r+0x30> 8021e62: 6063 str r3, [r4, #4] 8021e64: 6014 str r4, [r2, #0] 8021e66: b003 add sp, #12 8021e68: e8bd 4030 ldmia.w sp!, {r4, r5, lr} 8021e6c: f000 b8e2 b.w 8022034 <__malloc_unlock> 8021e70: 42a3 cmp r3, r4 8021e72: d908 bls.n 8021e86 <_free_r+0x46> 8021e74: 6825 ldr r5, [r4, #0] 8021e76: 1961 adds r1, r4, r5 8021e78: 428b cmp r3, r1 8021e7a: bf01 itttt eq 8021e7c: 6819 ldreq r1, [r3, #0] 8021e7e: 685b ldreq r3, [r3, #4] 8021e80: 1949 addeq r1, r1, r5 8021e82: 6021 streq r1, [r4, #0] 8021e84: e7ed b.n 8021e62 <_free_r+0x22> 8021e86: 461a mov r2, r3 8021e88: 685b ldr r3, [r3, #4] 8021e8a: b10b cbz r3, 8021e90 <_free_r+0x50> 8021e8c: 42a3 cmp r3, r4 8021e8e: d9fa bls.n 8021e86 <_free_r+0x46> 8021e90: 6811 ldr r1, [r2, #0] 8021e92: 1855 adds r5, r2, r1 8021e94: 42a5 cmp r5, r4 8021e96: d10b bne.n 8021eb0 <_free_r+0x70> 8021e98: 6824 ldr r4, [r4, #0] 8021e9a: 4421 add r1, r4 8021e9c: 1854 adds r4, r2, r1 8021e9e: 42a3 cmp r3, r4 8021ea0: 6011 str r1, [r2, #0] 8021ea2: d1e0 bne.n 8021e66 <_free_r+0x26> 8021ea4: 681c ldr r4, [r3, #0] 8021ea6: 685b ldr r3, [r3, #4] 8021ea8: 6053 str r3, [r2, #4] 8021eaa: 440c add r4, r1 8021eac: 6014 str r4, [r2, #0] 8021eae: e7da b.n 8021e66 <_free_r+0x26> 8021eb0: d902 bls.n 8021eb8 <_free_r+0x78> 8021eb2: 230c movs r3, #12 8021eb4: 6003 str r3, [r0, #0] 8021eb6: e7d6 b.n 8021e66 <_free_r+0x26> 8021eb8: 6825 ldr r5, [r4, #0] 8021eba: 1961 adds r1, r4, r5 8021ebc: 428b cmp r3, r1 8021ebe: bf04 itt eq 8021ec0: 6819 ldreq r1, [r3, #0] 8021ec2: 685b ldreq r3, [r3, #4] 8021ec4: 6063 str r3, [r4, #4] 8021ec6: bf04 itt eq 8021ec8: 1949 addeq r1, r1, r5 8021eca: 6021 streq r1, [r4, #0] 8021ecc: 6054 str r4, [r2, #4] 8021ece: e7ca b.n 8021e66 <_free_r+0x26> 8021ed0: b003 add sp, #12 8021ed2: bd30 pop {r4, r5, pc} 8021ed4: 2401a728 .word 0x2401a728 08021ed8 : 8021ed8: 4b02 ldr r3, [pc, #8] ; (8021ee4 ) 8021eda: 4601 mov r1, r0 8021edc: 6818 ldr r0, [r3, #0] 8021ede: f000 b823 b.w 8021f28 <_malloc_r> 8021ee2: bf00 nop 8021ee4: 240000a0 .word 0x240000a0 08021ee8 : 8021ee8: b570 push {r4, r5, r6, lr} 8021eea: 4e0e ldr r6, [pc, #56] ; (8021f24 ) 8021eec: 460c mov r4, r1 8021eee: 6831 ldr r1, [r6, #0] 8021ef0: 4605 mov r5, r0 8021ef2: b911 cbnz r1, 8021efa 8021ef4: f000 fe48 bl 8022b88 <_sbrk_r> 8021ef8: 6030 str r0, [r6, #0] 8021efa: 4621 mov r1, r4 8021efc: 4628 mov r0, r5 8021efe: f000 fe43 bl 8022b88 <_sbrk_r> 8021f02: 1c43 adds r3, r0, #1 8021f04: d00a beq.n 8021f1c 8021f06: 1cc4 adds r4, r0, #3 8021f08: f024 0403 bic.w r4, r4, #3 8021f0c: 42a0 cmp r0, r4 8021f0e: d007 beq.n 8021f20 8021f10: 1a21 subs r1, r4, r0 8021f12: 4628 mov r0, r5 8021f14: f000 fe38 bl 8022b88 <_sbrk_r> 8021f18: 3001 adds r0, #1 8021f1a: d101 bne.n 8021f20 8021f1c: f04f 34ff mov.w r4, #4294967295 8021f20: 4620 mov r0, r4 8021f22: bd70 pop {r4, r5, r6, pc} 8021f24: 2401a72c .word 0x2401a72c 08021f28 <_malloc_r>: 8021f28: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8021f2c: 1ccd adds r5, r1, #3 8021f2e: f025 0503 bic.w r5, r5, #3 8021f32: 3508 adds r5, #8 8021f34: 2d0c cmp r5, #12 8021f36: bf38 it cc 8021f38: 250c movcc r5, #12 8021f3a: 2d00 cmp r5, #0 8021f3c: 4607 mov r7, r0 8021f3e: db01 blt.n 8021f44 <_malloc_r+0x1c> 8021f40: 42a9 cmp r1, r5 8021f42: d905 bls.n 8021f50 <_malloc_r+0x28> 8021f44: 230c movs r3, #12 8021f46: 603b str r3, [r7, #0] 8021f48: 2600 movs r6, #0 8021f4a: 4630 mov r0, r6 8021f4c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8021f50: f8df 80d0 ldr.w r8, [pc, #208] ; 8022024 <_malloc_r+0xfc> 8021f54: f000 f868 bl 8022028 <__malloc_lock> 8021f58: f8d8 3000 ldr.w r3, [r8] 8021f5c: 461c mov r4, r3 8021f5e: bb5c cbnz r4, 8021fb8 <_malloc_r+0x90> 8021f60: 4629 mov r1, r5 8021f62: 4638 mov r0, r7 8021f64: f7ff ffc0 bl 8021ee8 8021f68: 1c43 adds r3, r0, #1 8021f6a: 4604 mov r4, r0 8021f6c: d155 bne.n 802201a <_malloc_r+0xf2> 8021f6e: f8d8 4000 ldr.w r4, [r8] 8021f72: 4626 mov r6, r4 8021f74: 2e00 cmp r6, #0 8021f76: d145 bne.n 8022004 <_malloc_r+0xdc> 8021f78: 2c00 cmp r4, #0 8021f7a: d048 beq.n 802200e <_malloc_r+0xe6> 8021f7c: 6823 ldr r3, [r4, #0] 8021f7e: 4631 mov r1, r6 8021f80: 4638 mov r0, r7 8021f82: eb04 0903 add.w r9, r4, r3 8021f86: f000 fdff bl 8022b88 <_sbrk_r> 8021f8a: 4581 cmp r9, r0 8021f8c: d13f bne.n 802200e <_malloc_r+0xe6> 8021f8e: 6821 ldr r1, [r4, #0] 8021f90: 1a6d subs r5, r5, r1 8021f92: 4629 mov r1, r5 8021f94: 4638 mov r0, r7 8021f96: f7ff ffa7 bl 8021ee8 8021f9a: 3001 adds r0, #1 8021f9c: d037 beq.n 802200e <_malloc_r+0xe6> 8021f9e: 6823 ldr r3, [r4, #0] 8021fa0: 442b add r3, r5 8021fa2: 6023 str r3, [r4, #0] 8021fa4: f8d8 3000 ldr.w r3, [r8] 8021fa8: 2b00 cmp r3, #0 8021faa: d038 beq.n 802201e <_malloc_r+0xf6> 8021fac: 685a ldr r2, [r3, #4] 8021fae: 42a2 cmp r2, r4 8021fb0: d12b bne.n 802200a <_malloc_r+0xe2> 8021fb2: 2200 movs r2, #0 8021fb4: 605a str r2, [r3, #4] 8021fb6: e00f b.n 8021fd8 <_malloc_r+0xb0> 8021fb8: 6822 ldr r2, [r4, #0] 8021fba: 1b52 subs r2, r2, r5 8021fbc: d41f bmi.n 8021ffe <_malloc_r+0xd6> 8021fbe: 2a0b cmp r2, #11 8021fc0: d917 bls.n 8021ff2 <_malloc_r+0xca> 8021fc2: 1961 adds r1, r4, r5 8021fc4: 42a3 cmp r3, r4 8021fc6: 6025 str r5, [r4, #0] 8021fc8: bf18 it ne 8021fca: 6059 strne r1, [r3, #4] 8021fcc: 6863 ldr r3, [r4, #4] 8021fce: bf08 it eq 8021fd0: f8c8 1000 streq.w r1, [r8] 8021fd4: 5162 str r2, [r4, r5] 8021fd6: 604b str r3, [r1, #4] 8021fd8: 4638 mov r0, r7 8021fda: f104 060b add.w r6, r4, #11 8021fde: f000 f829 bl 8022034 <__malloc_unlock> 8021fe2: f026 0607 bic.w r6, r6, #7 8021fe6: 1d23 adds r3, r4, #4 8021fe8: 1af2 subs r2, r6, r3 8021fea: d0ae beq.n 8021f4a <_malloc_r+0x22> 8021fec: 1b9b subs r3, r3, r6 8021fee: 50a3 str r3, [r4, r2] 8021ff0: e7ab b.n 8021f4a <_malloc_r+0x22> 8021ff2: 42a3 cmp r3, r4 8021ff4: 6862 ldr r2, [r4, #4] 8021ff6: d1dd bne.n 8021fb4 <_malloc_r+0x8c> 8021ff8: f8c8 2000 str.w r2, [r8] 8021ffc: e7ec b.n 8021fd8 <_malloc_r+0xb0> 8021ffe: 4623 mov r3, r4 8022000: 6864 ldr r4, [r4, #4] 8022002: e7ac b.n 8021f5e <_malloc_r+0x36> 8022004: 4634 mov r4, r6 8022006: 6876 ldr r6, [r6, #4] 8022008: e7b4 b.n 8021f74 <_malloc_r+0x4c> 802200a: 4613 mov r3, r2 802200c: e7cc b.n 8021fa8 <_malloc_r+0x80> 802200e: 230c movs r3, #12 8022010: 603b str r3, [r7, #0] 8022012: 4638 mov r0, r7 8022014: f000 f80e bl 8022034 <__malloc_unlock> 8022018: e797 b.n 8021f4a <_malloc_r+0x22> 802201a: 6025 str r5, [r4, #0] 802201c: e7dc b.n 8021fd8 <_malloc_r+0xb0> 802201e: 605b str r3, [r3, #4] 8022020: deff udf #255 ; 0xff 8022022: bf00 nop 8022024: 2401a728 .word 0x2401a728 08022028 <__malloc_lock>: 8022028: 4801 ldr r0, [pc, #4] ; (8022030 <__malloc_lock+0x8>) 802202a: f7ff beda b.w 8021de2 <__retarget_lock_acquire_recursive> 802202e: bf00 nop 8022030: 2401a724 .word 0x2401a724 08022034 <__malloc_unlock>: 8022034: 4801 ldr r0, [pc, #4] ; (802203c <__malloc_unlock+0x8>) 8022036: f7ff bed5 b.w 8021de4 <__retarget_lock_release_recursive> 802203a: bf00 nop 802203c: 2401a724 .word 0x2401a724 08022040 <__ssputs_r>: 8022040: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8022044: 688e ldr r6, [r1, #8] 8022046: 461f mov r7, r3 8022048: 42be cmp r6, r7 802204a: 680b ldr r3, [r1, #0] 802204c: 4682 mov sl, r0 802204e: 460c mov r4, r1 8022050: 4690 mov r8, r2 8022052: d82c bhi.n 80220ae <__ssputs_r+0x6e> 8022054: 898a ldrh r2, [r1, #12] 8022056: f412 6f90 tst.w r2, #1152 ; 0x480 802205a: d026 beq.n 80220aa <__ssputs_r+0x6a> 802205c: 6965 ldr r5, [r4, #20] 802205e: 6909 ldr r1, [r1, #16] 8022060: eb05 0545 add.w r5, r5, r5, lsl #1 8022064: eba3 0901 sub.w r9, r3, r1 8022068: eb05 75d5 add.w r5, r5, r5, lsr #31 802206c: 1c7b adds r3, r7, #1 802206e: 444b add r3, r9 8022070: 106d asrs r5, r5, #1 8022072: 429d cmp r5, r3 8022074: bf38 it cc 8022076: 461d movcc r5, r3 8022078: 0553 lsls r3, r2, #21 802207a: d527 bpl.n 80220cc <__ssputs_r+0x8c> 802207c: 4629 mov r1, r5 802207e: f7ff ff53 bl 8021f28 <_malloc_r> 8022082: 4606 mov r6, r0 8022084: b360 cbz r0, 80220e0 <__ssputs_r+0xa0> 8022086: 6921 ldr r1, [r4, #16] 8022088: 464a mov r2, r9 802208a: f7ff feac bl 8021de6 802208e: 89a3 ldrh r3, [r4, #12] 8022090: f423 6390 bic.w r3, r3, #1152 ; 0x480 8022094: f043 0380 orr.w r3, r3, #128 ; 0x80 8022098: 81a3 strh r3, [r4, #12] 802209a: 6126 str r6, [r4, #16] 802209c: 6165 str r5, [r4, #20] 802209e: 444e add r6, r9 80220a0: eba5 0509 sub.w r5, r5, r9 80220a4: 6026 str r6, [r4, #0] 80220a6: 60a5 str r5, [r4, #8] 80220a8: 463e mov r6, r7 80220aa: 42be cmp r6, r7 80220ac: d900 bls.n 80220b0 <__ssputs_r+0x70> 80220ae: 463e mov r6, r7 80220b0: 6820 ldr r0, [r4, #0] 80220b2: 4632 mov r2, r6 80220b4: 4641 mov r1, r8 80220b6: f7ff fdf9 bl 8021cac 80220ba: 68a3 ldr r3, [r4, #8] 80220bc: 1b9b subs r3, r3, r6 80220be: 60a3 str r3, [r4, #8] 80220c0: 6823 ldr r3, [r4, #0] 80220c2: 4433 add r3, r6 80220c4: 6023 str r3, [r4, #0] 80220c6: 2000 movs r0, #0 80220c8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80220cc: 462a mov r2, r5 80220ce: f000 fd72 bl 8022bb6 <_realloc_r> 80220d2: 4606 mov r6, r0 80220d4: 2800 cmp r0, #0 80220d6: d1e0 bne.n 802209a <__ssputs_r+0x5a> 80220d8: 6921 ldr r1, [r4, #16] 80220da: 4650 mov r0, sl 80220dc: f7ff feb0 bl 8021e40 <_free_r> 80220e0: 230c movs r3, #12 80220e2: f8ca 3000 str.w r3, [sl] 80220e6: 89a3 ldrh r3, [r4, #12] 80220e8: f043 0340 orr.w r3, r3, #64 ; 0x40 80220ec: 81a3 strh r3, [r4, #12] 80220ee: f04f 30ff mov.w r0, #4294967295 80220f2: e7e9 b.n 80220c8 <__ssputs_r+0x88> 080220f4 <_svfiprintf_r>: 80220f4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80220f8: 4698 mov r8, r3 80220fa: 898b ldrh r3, [r1, #12] 80220fc: 061b lsls r3, r3, #24 80220fe: b09d sub sp, #116 ; 0x74 8022100: 4607 mov r7, r0 8022102: 460d mov r5, r1 8022104: 4614 mov r4, r2 8022106: d50e bpl.n 8022126 <_svfiprintf_r+0x32> 8022108: 690b ldr r3, [r1, #16] 802210a: b963 cbnz r3, 8022126 <_svfiprintf_r+0x32> 802210c: 2140 movs r1, #64 ; 0x40 802210e: f7ff ff0b bl 8021f28 <_malloc_r> 8022112: 6028 str r0, [r5, #0] 8022114: 6128 str r0, [r5, #16] 8022116: b920 cbnz r0, 8022122 <_svfiprintf_r+0x2e> 8022118: 230c movs r3, #12 802211a: 603b str r3, [r7, #0] 802211c: f04f 30ff mov.w r0, #4294967295 8022120: e0d0 b.n 80222c4 <_svfiprintf_r+0x1d0> 8022122: 2340 movs r3, #64 ; 0x40 8022124: 616b str r3, [r5, #20] 8022126: 2300 movs r3, #0 8022128: 9309 str r3, [sp, #36] ; 0x24 802212a: 2320 movs r3, #32 802212c: f88d 3029 strb.w r3, [sp, #41] ; 0x29 8022130: f8cd 800c str.w r8, [sp, #12] 8022134: 2330 movs r3, #48 ; 0x30 8022136: f8df 81a4 ldr.w r8, [pc, #420] ; 80222dc <_svfiprintf_r+0x1e8> 802213a: f88d 302a strb.w r3, [sp, #42] ; 0x2a 802213e: f04f 0901 mov.w r9, #1 8022142: 4623 mov r3, r4 8022144: 469a mov sl, r3 8022146: f813 2b01 ldrb.w r2, [r3], #1 802214a: b10a cbz r2, 8022150 <_svfiprintf_r+0x5c> 802214c: 2a25 cmp r2, #37 ; 0x25 802214e: d1f9 bne.n 8022144 <_svfiprintf_r+0x50> 8022150: ebba 0b04 subs.w fp, sl, r4 8022154: d00b beq.n 802216e <_svfiprintf_r+0x7a> 8022156: 465b mov r3, fp 8022158: 4622 mov r2, r4 802215a: 4629 mov r1, r5 802215c: 4638 mov r0, r7 802215e: f7ff ff6f bl 8022040 <__ssputs_r> 8022162: 3001 adds r0, #1 8022164: f000 80a9 beq.w 80222ba <_svfiprintf_r+0x1c6> 8022168: 9a09 ldr r2, [sp, #36] ; 0x24 802216a: 445a add r2, fp 802216c: 9209 str r2, [sp, #36] ; 0x24 802216e: f89a 3000 ldrb.w r3, [sl] 8022172: 2b00 cmp r3, #0 8022174: f000 80a1 beq.w 80222ba <_svfiprintf_r+0x1c6> 8022178: 2300 movs r3, #0 802217a: f04f 32ff mov.w r2, #4294967295 802217e: e9cd 2305 strd r2, r3, [sp, #20] 8022182: f10a 0a01 add.w sl, sl, #1 8022186: 9304 str r3, [sp, #16] 8022188: 9307 str r3, [sp, #28] 802218a: f88d 3053 strb.w r3, [sp, #83] ; 0x53 802218e: 931a str r3, [sp, #104] ; 0x68 8022190: 4654 mov r4, sl 8022192: 2205 movs r2, #5 8022194: f814 1b01 ldrb.w r1, [r4], #1 8022198: 4850 ldr r0, [pc, #320] ; (80222dc <_svfiprintf_r+0x1e8>) 802219a: f7de f8d1 bl 8000340 802219e: 9a04 ldr r2, [sp, #16] 80221a0: b9d8 cbnz r0, 80221da <_svfiprintf_r+0xe6> 80221a2: 06d0 lsls r0, r2, #27 80221a4: bf44 itt mi 80221a6: 2320 movmi r3, #32 80221a8: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 80221ac: 0711 lsls r1, r2, #28 80221ae: bf44 itt mi 80221b0: 232b movmi r3, #43 ; 0x2b 80221b2: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 80221b6: f89a 3000 ldrb.w r3, [sl] 80221ba: 2b2a cmp r3, #42 ; 0x2a 80221bc: d015 beq.n 80221ea <_svfiprintf_r+0xf6> 80221be: 9a07 ldr r2, [sp, #28] 80221c0: 4654 mov r4, sl 80221c2: 2000 movs r0, #0 80221c4: f04f 0c0a mov.w ip, #10 80221c8: 4621 mov r1, r4 80221ca: f811 3b01 ldrb.w r3, [r1], #1 80221ce: 3b30 subs r3, #48 ; 0x30 80221d0: 2b09 cmp r3, #9 80221d2: d94d bls.n 8022270 <_svfiprintf_r+0x17c> 80221d4: b1b0 cbz r0, 8022204 <_svfiprintf_r+0x110> 80221d6: 9207 str r2, [sp, #28] 80221d8: e014 b.n 8022204 <_svfiprintf_r+0x110> 80221da: eba0 0308 sub.w r3, r0, r8 80221de: fa09 f303 lsl.w r3, r9, r3 80221e2: 4313 orrs r3, r2 80221e4: 9304 str r3, [sp, #16] 80221e6: 46a2 mov sl, r4 80221e8: e7d2 b.n 8022190 <_svfiprintf_r+0x9c> 80221ea: 9b03 ldr r3, [sp, #12] 80221ec: 1d19 adds r1, r3, #4 80221ee: 681b ldr r3, [r3, #0] 80221f0: 9103 str r1, [sp, #12] 80221f2: 2b00 cmp r3, #0 80221f4: bfbb ittet lt 80221f6: 425b neglt r3, r3 80221f8: f042 0202 orrlt.w r2, r2, #2 80221fc: 9307 strge r3, [sp, #28] 80221fe: 9307 strlt r3, [sp, #28] 8022200: bfb8 it lt 8022202: 9204 strlt r2, [sp, #16] 8022204: 7823 ldrb r3, [r4, #0] 8022206: 2b2e cmp r3, #46 ; 0x2e 8022208: d10c bne.n 8022224 <_svfiprintf_r+0x130> 802220a: 7863 ldrb r3, [r4, #1] 802220c: 2b2a cmp r3, #42 ; 0x2a 802220e: d134 bne.n 802227a <_svfiprintf_r+0x186> 8022210: 9b03 ldr r3, [sp, #12] 8022212: 1d1a adds r2, r3, #4 8022214: 681b ldr r3, [r3, #0] 8022216: 9203 str r2, [sp, #12] 8022218: 2b00 cmp r3, #0 802221a: bfb8 it lt 802221c: f04f 33ff movlt.w r3, #4294967295 8022220: 3402 adds r4, #2 8022222: 9305 str r3, [sp, #20] 8022224: f8df a0c4 ldr.w sl, [pc, #196] ; 80222ec <_svfiprintf_r+0x1f8> 8022228: 7821 ldrb r1, [r4, #0] 802222a: 2203 movs r2, #3 802222c: 4650 mov r0, sl 802222e: f7de f887 bl 8000340 8022232: b138 cbz r0, 8022244 <_svfiprintf_r+0x150> 8022234: 9b04 ldr r3, [sp, #16] 8022236: eba0 000a sub.w r0, r0, sl 802223a: 2240 movs r2, #64 ; 0x40 802223c: 4082 lsls r2, r0 802223e: 4313 orrs r3, r2 8022240: 3401 adds r4, #1 8022242: 9304 str r3, [sp, #16] 8022244: f814 1b01 ldrb.w r1, [r4], #1 8022248: 4825 ldr r0, [pc, #148] ; (80222e0 <_svfiprintf_r+0x1ec>) 802224a: f88d 1028 strb.w r1, [sp, #40] ; 0x28 802224e: 2206 movs r2, #6 8022250: f7de f876 bl 8000340 8022254: 2800 cmp r0, #0 8022256: d038 beq.n 80222ca <_svfiprintf_r+0x1d6> 8022258: 4b22 ldr r3, [pc, #136] ; (80222e4 <_svfiprintf_r+0x1f0>) 802225a: bb1b cbnz r3, 80222a4 <_svfiprintf_r+0x1b0> 802225c: 9b03 ldr r3, [sp, #12] 802225e: 3307 adds r3, #7 8022260: f023 0307 bic.w r3, r3, #7 8022264: 3308 adds r3, #8 8022266: 9303 str r3, [sp, #12] 8022268: 9b09 ldr r3, [sp, #36] ; 0x24 802226a: 4433 add r3, r6 802226c: 9309 str r3, [sp, #36] ; 0x24 802226e: e768 b.n 8022142 <_svfiprintf_r+0x4e> 8022270: fb0c 3202 mla r2, ip, r2, r3 8022274: 460c mov r4, r1 8022276: 2001 movs r0, #1 8022278: e7a6 b.n 80221c8 <_svfiprintf_r+0xd4> 802227a: 2300 movs r3, #0 802227c: 3401 adds r4, #1 802227e: 9305 str r3, [sp, #20] 8022280: 4619 mov r1, r3 8022282: f04f 0c0a mov.w ip, #10 8022286: 4620 mov r0, r4 8022288: f810 2b01 ldrb.w r2, [r0], #1 802228c: 3a30 subs r2, #48 ; 0x30 802228e: 2a09 cmp r2, #9 8022290: d903 bls.n 802229a <_svfiprintf_r+0x1a6> 8022292: 2b00 cmp r3, #0 8022294: d0c6 beq.n 8022224 <_svfiprintf_r+0x130> 8022296: 9105 str r1, [sp, #20] 8022298: e7c4 b.n 8022224 <_svfiprintf_r+0x130> 802229a: fb0c 2101 mla r1, ip, r1, r2 802229e: 4604 mov r4, r0 80222a0: 2301 movs r3, #1 80222a2: e7f0 b.n 8022286 <_svfiprintf_r+0x192> 80222a4: ab03 add r3, sp, #12 80222a6: 9300 str r3, [sp, #0] 80222a8: 462a mov r2, r5 80222aa: 4b0f ldr r3, [pc, #60] ; (80222e8 <_svfiprintf_r+0x1f4>) 80222ac: a904 add r1, sp, #16 80222ae: 4638 mov r0, r7 80222b0: f3af 8000 nop.w 80222b4: 1c42 adds r2, r0, #1 80222b6: 4606 mov r6, r0 80222b8: d1d6 bne.n 8022268 <_svfiprintf_r+0x174> 80222ba: 89ab ldrh r3, [r5, #12] 80222bc: 065b lsls r3, r3, #25 80222be: f53f af2d bmi.w 802211c <_svfiprintf_r+0x28> 80222c2: 9809 ldr r0, [sp, #36] ; 0x24 80222c4: b01d add sp, #116 ; 0x74 80222c6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80222ca: ab03 add r3, sp, #12 80222cc: 9300 str r3, [sp, #0] 80222ce: 462a mov r2, r5 80222d0: 4b05 ldr r3, [pc, #20] ; (80222e8 <_svfiprintf_r+0x1f4>) 80222d2: a904 add r1, sp, #16 80222d4: 4638 mov r0, r7 80222d6: f000 f9bd bl 8022654 <_printf_i> 80222da: e7eb b.n 80222b4 <_svfiprintf_r+0x1c0> 80222dc: 08026eb4 .word 0x08026eb4 80222e0: 08026ebe .word 0x08026ebe 80222e4: 00000000 .word 0x00000000 80222e8: 08022041 .word 0x08022041 80222ec: 08026eba .word 0x08026eba 080222f0 <__sfputc_r>: 80222f0: 6893 ldr r3, [r2, #8] 80222f2: 3b01 subs r3, #1 80222f4: 2b00 cmp r3, #0 80222f6: b410 push {r4} 80222f8: 6093 str r3, [r2, #8] 80222fa: da08 bge.n 802230e <__sfputc_r+0x1e> 80222fc: 6994 ldr r4, [r2, #24] 80222fe: 42a3 cmp r3, r4 8022300: db01 blt.n 8022306 <__sfputc_r+0x16> 8022302: 290a cmp r1, #10 8022304: d103 bne.n 802230e <__sfputc_r+0x1e> 8022306: f85d 4b04 ldr.w r4, [sp], #4 802230a: f7ff bc2a b.w 8021b62 <__swbuf_r> 802230e: 6813 ldr r3, [r2, #0] 8022310: 1c58 adds r0, r3, #1 8022312: 6010 str r0, [r2, #0] 8022314: 7019 strb r1, [r3, #0] 8022316: 4608 mov r0, r1 8022318: f85d 4b04 ldr.w r4, [sp], #4 802231c: 4770 bx lr 0802231e <__sfputs_r>: 802231e: b5f8 push {r3, r4, r5, r6, r7, lr} 8022320: 4606 mov r6, r0 8022322: 460f mov r7, r1 8022324: 4614 mov r4, r2 8022326: 18d5 adds r5, r2, r3 8022328: 42ac cmp r4, r5 802232a: d101 bne.n 8022330 <__sfputs_r+0x12> 802232c: 2000 movs r0, #0 802232e: e007 b.n 8022340 <__sfputs_r+0x22> 8022330: f814 1b01 ldrb.w r1, [r4], #1 8022334: 463a mov r2, r7 8022336: 4630 mov r0, r6 8022338: f7ff ffda bl 80222f0 <__sfputc_r> 802233c: 1c43 adds r3, r0, #1 802233e: d1f3 bne.n 8022328 <__sfputs_r+0xa> 8022340: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08022344 <_vfiprintf_r>: 8022344: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8022348: 460d mov r5, r1 802234a: b09d sub sp, #116 ; 0x74 802234c: 4614 mov r4, r2 802234e: 4698 mov r8, r3 8022350: 4606 mov r6, r0 8022352: b118 cbz r0, 802235c <_vfiprintf_r+0x18> 8022354: 6a03 ldr r3, [r0, #32] 8022356: b90b cbnz r3, 802235c <_vfiprintf_r+0x18> 8022358: f7ff fae0 bl 802191c <__sinit> 802235c: 6e6b ldr r3, [r5, #100] ; 0x64 802235e: 07d9 lsls r1, r3, #31 8022360: d405 bmi.n 802236e <_vfiprintf_r+0x2a> 8022362: 89ab ldrh r3, [r5, #12] 8022364: 059a lsls r2, r3, #22 8022366: d402 bmi.n 802236e <_vfiprintf_r+0x2a> 8022368: 6da8 ldr r0, [r5, #88] ; 0x58 802236a: f7ff fd3a bl 8021de2 <__retarget_lock_acquire_recursive> 802236e: 89ab ldrh r3, [r5, #12] 8022370: 071b lsls r3, r3, #28 8022372: d501 bpl.n 8022378 <_vfiprintf_r+0x34> 8022374: 692b ldr r3, [r5, #16] 8022376: b99b cbnz r3, 80223a0 <_vfiprintf_r+0x5c> 8022378: 4629 mov r1, r5 802237a: 4630 mov r0, r6 802237c: f7ff fc2e bl 8021bdc <__swsetup_r> 8022380: b170 cbz r0, 80223a0 <_vfiprintf_r+0x5c> 8022382: 6e6b ldr r3, [r5, #100] ; 0x64 8022384: 07dc lsls r4, r3, #31 8022386: d504 bpl.n 8022392 <_vfiprintf_r+0x4e> 8022388: f04f 30ff mov.w r0, #4294967295 802238c: b01d add sp, #116 ; 0x74 802238e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8022392: 89ab ldrh r3, [r5, #12] 8022394: 0598 lsls r0, r3, #22 8022396: d4f7 bmi.n 8022388 <_vfiprintf_r+0x44> 8022398: 6da8 ldr r0, [r5, #88] ; 0x58 802239a: f7ff fd23 bl 8021de4 <__retarget_lock_release_recursive> 802239e: e7f3 b.n 8022388 <_vfiprintf_r+0x44> 80223a0: 2300 movs r3, #0 80223a2: 9309 str r3, [sp, #36] ; 0x24 80223a4: 2320 movs r3, #32 80223a6: f88d 3029 strb.w r3, [sp, #41] ; 0x29 80223aa: f8cd 800c str.w r8, [sp, #12] 80223ae: 2330 movs r3, #48 ; 0x30 80223b0: f8df 81b0 ldr.w r8, [pc, #432] ; 8022564 <_vfiprintf_r+0x220> 80223b4: f88d 302a strb.w r3, [sp, #42] ; 0x2a 80223b8: f04f 0901 mov.w r9, #1 80223bc: 4623 mov r3, r4 80223be: 469a mov sl, r3 80223c0: f813 2b01 ldrb.w r2, [r3], #1 80223c4: b10a cbz r2, 80223ca <_vfiprintf_r+0x86> 80223c6: 2a25 cmp r2, #37 ; 0x25 80223c8: d1f9 bne.n 80223be <_vfiprintf_r+0x7a> 80223ca: ebba 0b04 subs.w fp, sl, r4 80223ce: d00b beq.n 80223e8 <_vfiprintf_r+0xa4> 80223d0: 465b mov r3, fp 80223d2: 4622 mov r2, r4 80223d4: 4629 mov r1, r5 80223d6: 4630 mov r0, r6 80223d8: f7ff ffa1 bl 802231e <__sfputs_r> 80223dc: 3001 adds r0, #1 80223de: f000 80a9 beq.w 8022534 <_vfiprintf_r+0x1f0> 80223e2: 9a09 ldr r2, [sp, #36] ; 0x24 80223e4: 445a add r2, fp 80223e6: 9209 str r2, [sp, #36] ; 0x24 80223e8: f89a 3000 ldrb.w r3, [sl] 80223ec: 2b00 cmp r3, #0 80223ee: f000 80a1 beq.w 8022534 <_vfiprintf_r+0x1f0> 80223f2: 2300 movs r3, #0 80223f4: f04f 32ff mov.w r2, #4294967295 80223f8: e9cd 2305 strd r2, r3, [sp, #20] 80223fc: f10a 0a01 add.w sl, sl, #1 8022400: 9304 str r3, [sp, #16] 8022402: 9307 str r3, [sp, #28] 8022404: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8022408: 931a str r3, [sp, #104] ; 0x68 802240a: 4654 mov r4, sl 802240c: 2205 movs r2, #5 802240e: f814 1b01 ldrb.w r1, [r4], #1 8022412: 4854 ldr r0, [pc, #336] ; (8022564 <_vfiprintf_r+0x220>) 8022414: f7dd ff94 bl 8000340 8022418: 9a04 ldr r2, [sp, #16] 802241a: b9d8 cbnz r0, 8022454 <_vfiprintf_r+0x110> 802241c: 06d1 lsls r1, r2, #27 802241e: bf44 itt mi 8022420: 2320 movmi r3, #32 8022422: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8022426: 0713 lsls r3, r2, #28 8022428: bf44 itt mi 802242a: 232b movmi r3, #43 ; 0x2b 802242c: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8022430: f89a 3000 ldrb.w r3, [sl] 8022434: 2b2a cmp r3, #42 ; 0x2a 8022436: d015 beq.n 8022464 <_vfiprintf_r+0x120> 8022438: 9a07 ldr r2, [sp, #28] 802243a: 4654 mov r4, sl 802243c: 2000 movs r0, #0 802243e: f04f 0c0a mov.w ip, #10 8022442: 4621 mov r1, r4 8022444: f811 3b01 ldrb.w r3, [r1], #1 8022448: 3b30 subs r3, #48 ; 0x30 802244a: 2b09 cmp r3, #9 802244c: d94d bls.n 80224ea <_vfiprintf_r+0x1a6> 802244e: b1b0 cbz r0, 802247e <_vfiprintf_r+0x13a> 8022450: 9207 str r2, [sp, #28] 8022452: e014 b.n 802247e <_vfiprintf_r+0x13a> 8022454: eba0 0308 sub.w r3, r0, r8 8022458: fa09 f303 lsl.w r3, r9, r3 802245c: 4313 orrs r3, r2 802245e: 9304 str r3, [sp, #16] 8022460: 46a2 mov sl, r4 8022462: e7d2 b.n 802240a <_vfiprintf_r+0xc6> 8022464: 9b03 ldr r3, [sp, #12] 8022466: 1d19 adds r1, r3, #4 8022468: 681b ldr r3, [r3, #0] 802246a: 9103 str r1, [sp, #12] 802246c: 2b00 cmp r3, #0 802246e: bfbb ittet lt 8022470: 425b neglt r3, r3 8022472: f042 0202 orrlt.w r2, r2, #2 8022476: 9307 strge r3, [sp, #28] 8022478: 9307 strlt r3, [sp, #28] 802247a: bfb8 it lt 802247c: 9204 strlt r2, [sp, #16] 802247e: 7823 ldrb r3, [r4, #0] 8022480: 2b2e cmp r3, #46 ; 0x2e 8022482: d10c bne.n 802249e <_vfiprintf_r+0x15a> 8022484: 7863 ldrb r3, [r4, #1] 8022486: 2b2a cmp r3, #42 ; 0x2a 8022488: d134 bne.n 80224f4 <_vfiprintf_r+0x1b0> 802248a: 9b03 ldr r3, [sp, #12] 802248c: 1d1a adds r2, r3, #4 802248e: 681b ldr r3, [r3, #0] 8022490: 9203 str r2, [sp, #12] 8022492: 2b00 cmp r3, #0 8022494: bfb8 it lt 8022496: f04f 33ff movlt.w r3, #4294967295 802249a: 3402 adds r4, #2 802249c: 9305 str r3, [sp, #20] 802249e: f8df a0d4 ldr.w sl, [pc, #212] ; 8022574 <_vfiprintf_r+0x230> 80224a2: 7821 ldrb r1, [r4, #0] 80224a4: 2203 movs r2, #3 80224a6: 4650 mov r0, sl 80224a8: f7dd ff4a bl 8000340 80224ac: b138 cbz r0, 80224be <_vfiprintf_r+0x17a> 80224ae: 9b04 ldr r3, [sp, #16] 80224b0: eba0 000a sub.w r0, r0, sl 80224b4: 2240 movs r2, #64 ; 0x40 80224b6: 4082 lsls r2, r0 80224b8: 4313 orrs r3, r2 80224ba: 3401 adds r4, #1 80224bc: 9304 str r3, [sp, #16] 80224be: f814 1b01 ldrb.w r1, [r4], #1 80224c2: 4829 ldr r0, [pc, #164] ; (8022568 <_vfiprintf_r+0x224>) 80224c4: f88d 1028 strb.w r1, [sp, #40] ; 0x28 80224c8: 2206 movs r2, #6 80224ca: f7dd ff39 bl 8000340 80224ce: 2800 cmp r0, #0 80224d0: d03f beq.n 8022552 <_vfiprintf_r+0x20e> 80224d2: 4b26 ldr r3, [pc, #152] ; (802256c <_vfiprintf_r+0x228>) 80224d4: bb1b cbnz r3, 802251e <_vfiprintf_r+0x1da> 80224d6: 9b03 ldr r3, [sp, #12] 80224d8: 3307 adds r3, #7 80224da: f023 0307 bic.w r3, r3, #7 80224de: 3308 adds r3, #8 80224e0: 9303 str r3, [sp, #12] 80224e2: 9b09 ldr r3, [sp, #36] ; 0x24 80224e4: 443b add r3, r7 80224e6: 9309 str r3, [sp, #36] ; 0x24 80224e8: e768 b.n 80223bc <_vfiprintf_r+0x78> 80224ea: fb0c 3202 mla r2, ip, r2, r3 80224ee: 460c mov r4, r1 80224f0: 2001 movs r0, #1 80224f2: e7a6 b.n 8022442 <_vfiprintf_r+0xfe> 80224f4: 2300 movs r3, #0 80224f6: 3401 adds r4, #1 80224f8: 9305 str r3, [sp, #20] 80224fa: 4619 mov r1, r3 80224fc: f04f 0c0a mov.w ip, #10 8022500: 4620 mov r0, r4 8022502: f810 2b01 ldrb.w r2, [r0], #1 8022506: 3a30 subs r2, #48 ; 0x30 8022508: 2a09 cmp r2, #9 802250a: d903 bls.n 8022514 <_vfiprintf_r+0x1d0> 802250c: 2b00 cmp r3, #0 802250e: d0c6 beq.n 802249e <_vfiprintf_r+0x15a> 8022510: 9105 str r1, [sp, #20] 8022512: e7c4 b.n 802249e <_vfiprintf_r+0x15a> 8022514: fb0c 2101 mla r1, ip, r1, r2 8022518: 4604 mov r4, r0 802251a: 2301 movs r3, #1 802251c: e7f0 b.n 8022500 <_vfiprintf_r+0x1bc> 802251e: ab03 add r3, sp, #12 8022520: 9300 str r3, [sp, #0] 8022522: 462a mov r2, r5 8022524: 4b12 ldr r3, [pc, #72] ; (8022570 <_vfiprintf_r+0x22c>) 8022526: a904 add r1, sp, #16 8022528: 4630 mov r0, r6 802252a: f3af 8000 nop.w 802252e: 4607 mov r7, r0 8022530: 1c78 adds r0, r7, #1 8022532: d1d6 bne.n 80224e2 <_vfiprintf_r+0x19e> 8022534: 6e6b ldr r3, [r5, #100] ; 0x64 8022536: 07d9 lsls r1, r3, #31 8022538: d405 bmi.n 8022546 <_vfiprintf_r+0x202> 802253a: 89ab ldrh r3, [r5, #12] 802253c: 059a lsls r2, r3, #22 802253e: d402 bmi.n 8022546 <_vfiprintf_r+0x202> 8022540: 6da8 ldr r0, [r5, #88] ; 0x58 8022542: f7ff fc4f bl 8021de4 <__retarget_lock_release_recursive> 8022546: 89ab ldrh r3, [r5, #12] 8022548: 065b lsls r3, r3, #25 802254a: f53f af1d bmi.w 8022388 <_vfiprintf_r+0x44> 802254e: 9809 ldr r0, [sp, #36] ; 0x24 8022550: e71c b.n 802238c <_vfiprintf_r+0x48> 8022552: ab03 add r3, sp, #12 8022554: 9300 str r3, [sp, #0] 8022556: 462a mov r2, r5 8022558: 4b05 ldr r3, [pc, #20] ; (8022570 <_vfiprintf_r+0x22c>) 802255a: a904 add r1, sp, #16 802255c: 4630 mov r0, r6 802255e: f000 f879 bl 8022654 <_printf_i> 8022562: e7e4 b.n 802252e <_vfiprintf_r+0x1ea> 8022564: 08026eb4 .word 0x08026eb4 8022568: 08026ebe .word 0x08026ebe 802256c: 00000000 .word 0x00000000 8022570: 0802231f .word 0x0802231f 8022574: 08026eba .word 0x08026eba 08022578 <_printf_common>: 8022578: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 802257c: 4616 mov r6, r2 802257e: 4699 mov r9, r3 8022580: 688a ldr r2, [r1, #8] 8022582: 690b ldr r3, [r1, #16] 8022584: f8dd 8020 ldr.w r8, [sp, #32] 8022588: 4293 cmp r3, r2 802258a: bfb8 it lt 802258c: 4613 movlt r3, r2 802258e: 6033 str r3, [r6, #0] 8022590: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8022594: 4607 mov r7, r0 8022596: 460c mov r4, r1 8022598: b10a cbz r2, 802259e <_printf_common+0x26> 802259a: 3301 adds r3, #1 802259c: 6033 str r3, [r6, #0] 802259e: 6823 ldr r3, [r4, #0] 80225a0: 0699 lsls r1, r3, #26 80225a2: bf42 ittt mi 80225a4: 6833 ldrmi r3, [r6, #0] 80225a6: 3302 addmi r3, #2 80225a8: 6033 strmi r3, [r6, #0] 80225aa: 6825 ldr r5, [r4, #0] 80225ac: f015 0506 ands.w r5, r5, #6 80225b0: d106 bne.n 80225c0 <_printf_common+0x48> 80225b2: f104 0a19 add.w sl, r4, #25 80225b6: 68e3 ldr r3, [r4, #12] 80225b8: 6832 ldr r2, [r6, #0] 80225ba: 1a9b subs r3, r3, r2 80225bc: 42ab cmp r3, r5 80225be: dc26 bgt.n 802260e <_printf_common+0x96> 80225c0: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 80225c4: 1e13 subs r3, r2, #0 80225c6: 6822 ldr r2, [r4, #0] 80225c8: bf18 it ne 80225ca: 2301 movne r3, #1 80225cc: 0692 lsls r2, r2, #26 80225ce: d42b bmi.n 8022628 <_printf_common+0xb0> 80225d0: f104 0243 add.w r2, r4, #67 ; 0x43 80225d4: 4649 mov r1, r9 80225d6: 4638 mov r0, r7 80225d8: 47c0 blx r8 80225da: 3001 adds r0, #1 80225dc: d01e beq.n 802261c <_printf_common+0xa4> 80225de: 6823 ldr r3, [r4, #0] 80225e0: 6922 ldr r2, [r4, #16] 80225e2: f003 0306 and.w r3, r3, #6 80225e6: 2b04 cmp r3, #4 80225e8: bf02 ittt eq 80225ea: 68e5 ldreq r5, [r4, #12] 80225ec: 6833 ldreq r3, [r6, #0] 80225ee: 1aed subeq r5, r5, r3 80225f0: 68a3 ldr r3, [r4, #8] 80225f2: bf0c ite eq 80225f4: ea25 75e5 biceq.w r5, r5, r5, asr #31 80225f8: 2500 movne r5, #0 80225fa: 4293 cmp r3, r2 80225fc: bfc4 itt gt 80225fe: 1a9b subgt r3, r3, r2 8022600: 18ed addgt r5, r5, r3 8022602: 2600 movs r6, #0 8022604: 341a adds r4, #26 8022606: 42b5 cmp r5, r6 8022608: d11a bne.n 8022640 <_printf_common+0xc8> 802260a: 2000 movs r0, #0 802260c: e008 b.n 8022620 <_printf_common+0xa8> 802260e: 2301 movs r3, #1 8022610: 4652 mov r2, sl 8022612: 4649 mov r1, r9 8022614: 4638 mov r0, r7 8022616: 47c0 blx r8 8022618: 3001 adds r0, #1 802261a: d103 bne.n 8022624 <_printf_common+0xac> 802261c: f04f 30ff mov.w r0, #4294967295 8022620: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8022624: 3501 adds r5, #1 8022626: e7c6 b.n 80225b6 <_printf_common+0x3e> 8022628: 18e1 adds r1, r4, r3 802262a: 1c5a adds r2, r3, #1 802262c: 2030 movs r0, #48 ; 0x30 802262e: f881 0043 strb.w r0, [r1, #67] ; 0x43 8022632: 4422 add r2, r4 8022634: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 8022638: f882 1043 strb.w r1, [r2, #67] ; 0x43 802263c: 3302 adds r3, #2 802263e: e7c7 b.n 80225d0 <_printf_common+0x58> 8022640: 2301 movs r3, #1 8022642: 4622 mov r2, r4 8022644: 4649 mov r1, r9 8022646: 4638 mov r0, r7 8022648: 47c0 blx r8 802264a: 3001 adds r0, #1 802264c: d0e6 beq.n 802261c <_printf_common+0xa4> 802264e: 3601 adds r6, #1 8022650: e7d9 b.n 8022606 <_printf_common+0x8e> ... 08022654 <_printf_i>: 8022654: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8022658: 7e0f ldrb r7, [r1, #24] 802265a: 9d0c ldr r5, [sp, #48] ; 0x30 802265c: 2f78 cmp r7, #120 ; 0x78 802265e: 4691 mov r9, r2 8022660: 4680 mov r8, r0 8022662: 460c mov r4, r1 8022664: 469a mov sl, r3 8022666: f101 0243 add.w r2, r1, #67 ; 0x43 802266a: d807 bhi.n 802267c <_printf_i+0x28> 802266c: 2f62 cmp r7, #98 ; 0x62 802266e: d80a bhi.n 8022686 <_printf_i+0x32> 8022670: 2f00 cmp r7, #0 8022672: f000 80d4 beq.w 802281e <_printf_i+0x1ca> 8022676: 2f58 cmp r7, #88 ; 0x58 8022678: f000 80c0 beq.w 80227fc <_printf_i+0x1a8> 802267c: f104 0542 add.w r5, r4, #66 ; 0x42 8022680: f884 7042 strb.w r7, [r4, #66] ; 0x42 8022684: e03a b.n 80226fc <_printf_i+0xa8> 8022686: f1a7 0363 sub.w r3, r7, #99 ; 0x63 802268a: 2b15 cmp r3, #21 802268c: d8f6 bhi.n 802267c <_printf_i+0x28> 802268e: a101 add r1, pc, #4 ; (adr r1, 8022694 <_printf_i+0x40>) 8022690: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8022694: 080226ed .word 0x080226ed 8022698: 08022701 .word 0x08022701 802269c: 0802267d .word 0x0802267d 80226a0: 0802267d .word 0x0802267d 80226a4: 0802267d .word 0x0802267d 80226a8: 0802267d .word 0x0802267d 80226ac: 08022701 .word 0x08022701 80226b0: 0802267d .word 0x0802267d 80226b4: 0802267d .word 0x0802267d 80226b8: 0802267d .word 0x0802267d 80226bc: 0802267d .word 0x0802267d 80226c0: 08022805 .word 0x08022805 80226c4: 0802272d .word 0x0802272d 80226c8: 080227bf .word 0x080227bf 80226cc: 0802267d .word 0x0802267d 80226d0: 0802267d .word 0x0802267d 80226d4: 08022827 .word 0x08022827 80226d8: 0802267d .word 0x0802267d 80226dc: 0802272d .word 0x0802272d 80226e0: 0802267d .word 0x0802267d 80226e4: 0802267d .word 0x0802267d 80226e8: 080227c7 .word 0x080227c7 80226ec: 682b ldr r3, [r5, #0] 80226ee: 1d1a adds r2, r3, #4 80226f0: 681b ldr r3, [r3, #0] 80226f2: 602a str r2, [r5, #0] 80226f4: f104 0542 add.w r5, r4, #66 ; 0x42 80226f8: f884 3042 strb.w r3, [r4, #66] ; 0x42 80226fc: 2301 movs r3, #1 80226fe: e09f b.n 8022840 <_printf_i+0x1ec> 8022700: 6820 ldr r0, [r4, #0] 8022702: 682b ldr r3, [r5, #0] 8022704: 0607 lsls r7, r0, #24 8022706: f103 0104 add.w r1, r3, #4 802270a: 6029 str r1, [r5, #0] 802270c: d501 bpl.n 8022712 <_printf_i+0xbe> 802270e: 681e ldr r6, [r3, #0] 8022710: e003 b.n 802271a <_printf_i+0xc6> 8022712: 0646 lsls r6, r0, #25 8022714: d5fb bpl.n 802270e <_printf_i+0xba> 8022716: f9b3 6000 ldrsh.w r6, [r3] 802271a: 2e00 cmp r6, #0 802271c: da03 bge.n 8022726 <_printf_i+0xd2> 802271e: 232d movs r3, #45 ; 0x2d 8022720: 4276 negs r6, r6 8022722: f884 3043 strb.w r3, [r4, #67] ; 0x43 8022726: 485a ldr r0, [pc, #360] ; (8022890 <_printf_i+0x23c>) 8022728: 230a movs r3, #10 802272a: e012 b.n 8022752 <_printf_i+0xfe> 802272c: 682b ldr r3, [r5, #0] 802272e: 6820 ldr r0, [r4, #0] 8022730: 1d19 adds r1, r3, #4 8022732: 6029 str r1, [r5, #0] 8022734: 0605 lsls r5, r0, #24 8022736: d501 bpl.n 802273c <_printf_i+0xe8> 8022738: 681e ldr r6, [r3, #0] 802273a: e002 b.n 8022742 <_printf_i+0xee> 802273c: 0641 lsls r1, r0, #25 802273e: d5fb bpl.n 8022738 <_printf_i+0xe4> 8022740: 881e ldrh r6, [r3, #0] 8022742: 4853 ldr r0, [pc, #332] ; (8022890 <_printf_i+0x23c>) 8022744: 2f6f cmp r7, #111 ; 0x6f 8022746: bf0c ite eq 8022748: 2308 moveq r3, #8 802274a: 230a movne r3, #10 802274c: 2100 movs r1, #0 802274e: f884 1043 strb.w r1, [r4, #67] ; 0x43 8022752: 6865 ldr r5, [r4, #4] 8022754: 60a5 str r5, [r4, #8] 8022756: 2d00 cmp r5, #0 8022758: bfa2 ittt ge 802275a: 6821 ldrge r1, [r4, #0] 802275c: f021 0104 bicge.w r1, r1, #4 8022760: 6021 strge r1, [r4, #0] 8022762: b90e cbnz r6, 8022768 <_printf_i+0x114> 8022764: 2d00 cmp r5, #0 8022766: d04b beq.n 8022800 <_printf_i+0x1ac> 8022768: 4615 mov r5, r2 802276a: fbb6 f1f3 udiv r1, r6, r3 802276e: fb03 6711 mls r7, r3, r1, r6 8022772: 5dc7 ldrb r7, [r0, r7] 8022774: f805 7d01 strb.w r7, [r5, #-1]! 8022778: 4637 mov r7, r6 802277a: 42bb cmp r3, r7 802277c: 460e mov r6, r1 802277e: d9f4 bls.n 802276a <_printf_i+0x116> 8022780: 2b08 cmp r3, #8 8022782: d10b bne.n 802279c <_printf_i+0x148> 8022784: 6823 ldr r3, [r4, #0] 8022786: 07de lsls r6, r3, #31 8022788: d508 bpl.n 802279c <_printf_i+0x148> 802278a: 6923 ldr r3, [r4, #16] 802278c: 6861 ldr r1, [r4, #4] 802278e: 4299 cmp r1, r3 8022790: bfde ittt le 8022792: 2330 movle r3, #48 ; 0x30 8022794: f805 3c01 strble.w r3, [r5, #-1] 8022798: f105 35ff addle.w r5, r5, #4294967295 802279c: 1b52 subs r2, r2, r5 802279e: 6122 str r2, [r4, #16] 80227a0: f8cd a000 str.w sl, [sp] 80227a4: 464b mov r3, r9 80227a6: aa03 add r2, sp, #12 80227a8: 4621 mov r1, r4 80227aa: 4640 mov r0, r8 80227ac: f7ff fee4 bl 8022578 <_printf_common> 80227b0: 3001 adds r0, #1 80227b2: d14a bne.n 802284a <_printf_i+0x1f6> 80227b4: f04f 30ff mov.w r0, #4294967295 80227b8: b004 add sp, #16 80227ba: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80227be: 6823 ldr r3, [r4, #0] 80227c0: f043 0320 orr.w r3, r3, #32 80227c4: 6023 str r3, [r4, #0] 80227c6: 4833 ldr r0, [pc, #204] ; (8022894 <_printf_i+0x240>) 80227c8: 2778 movs r7, #120 ; 0x78 80227ca: f884 7045 strb.w r7, [r4, #69] ; 0x45 80227ce: 6823 ldr r3, [r4, #0] 80227d0: 6829 ldr r1, [r5, #0] 80227d2: 061f lsls r7, r3, #24 80227d4: f851 6b04 ldr.w r6, [r1], #4 80227d8: d402 bmi.n 80227e0 <_printf_i+0x18c> 80227da: 065f lsls r7, r3, #25 80227dc: bf48 it mi 80227de: b2b6 uxthmi r6, r6 80227e0: 07df lsls r7, r3, #31 80227e2: bf48 it mi 80227e4: f043 0320 orrmi.w r3, r3, #32 80227e8: 6029 str r1, [r5, #0] 80227ea: bf48 it mi 80227ec: 6023 strmi r3, [r4, #0] 80227ee: b91e cbnz r6, 80227f8 <_printf_i+0x1a4> 80227f0: 6823 ldr r3, [r4, #0] 80227f2: f023 0320 bic.w r3, r3, #32 80227f6: 6023 str r3, [r4, #0] 80227f8: 2310 movs r3, #16 80227fa: e7a7 b.n 802274c <_printf_i+0xf8> 80227fc: 4824 ldr r0, [pc, #144] ; (8022890 <_printf_i+0x23c>) 80227fe: e7e4 b.n 80227ca <_printf_i+0x176> 8022800: 4615 mov r5, r2 8022802: e7bd b.n 8022780 <_printf_i+0x12c> 8022804: 682b ldr r3, [r5, #0] 8022806: 6826 ldr r6, [r4, #0] 8022808: 6961 ldr r1, [r4, #20] 802280a: 1d18 adds r0, r3, #4 802280c: 6028 str r0, [r5, #0] 802280e: 0635 lsls r5, r6, #24 8022810: 681b ldr r3, [r3, #0] 8022812: d501 bpl.n 8022818 <_printf_i+0x1c4> 8022814: 6019 str r1, [r3, #0] 8022816: e002 b.n 802281e <_printf_i+0x1ca> 8022818: 0670 lsls r0, r6, #25 802281a: d5fb bpl.n 8022814 <_printf_i+0x1c0> 802281c: 8019 strh r1, [r3, #0] 802281e: 2300 movs r3, #0 8022820: 6123 str r3, [r4, #16] 8022822: 4615 mov r5, r2 8022824: e7bc b.n 80227a0 <_printf_i+0x14c> 8022826: 682b ldr r3, [r5, #0] 8022828: 1d1a adds r2, r3, #4 802282a: 602a str r2, [r5, #0] 802282c: 681d ldr r5, [r3, #0] 802282e: 6862 ldr r2, [r4, #4] 8022830: 2100 movs r1, #0 8022832: 4628 mov r0, r5 8022834: f7dd fd84 bl 8000340 8022838: b108 cbz r0, 802283e <_printf_i+0x1ea> 802283a: 1b40 subs r0, r0, r5 802283c: 6060 str r0, [r4, #4] 802283e: 6863 ldr r3, [r4, #4] 8022840: 6123 str r3, [r4, #16] 8022842: 2300 movs r3, #0 8022844: f884 3043 strb.w r3, [r4, #67] ; 0x43 8022848: e7aa b.n 80227a0 <_printf_i+0x14c> 802284a: 6923 ldr r3, [r4, #16] 802284c: 462a mov r2, r5 802284e: 4649 mov r1, r9 8022850: 4640 mov r0, r8 8022852: 47d0 blx sl 8022854: 3001 adds r0, #1 8022856: d0ad beq.n 80227b4 <_printf_i+0x160> 8022858: 6823 ldr r3, [r4, #0] 802285a: 079b lsls r3, r3, #30 802285c: d413 bmi.n 8022886 <_printf_i+0x232> 802285e: 68e0 ldr r0, [r4, #12] 8022860: 9b03 ldr r3, [sp, #12] 8022862: 4298 cmp r0, r3 8022864: bfb8 it lt 8022866: 4618 movlt r0, r3 8022868: e7a6 b.n 80227b8 <_printf_i+0x164> 802286a: 2301 movs r3, #1 802286c: 4632 mov r2, r6 802286e: 4649 mov r1, r9 8022870: 4640 mov r0, r8 8022872: 47d0 blx sl 8022874: 3001 adds r0, #1 8022876: d09d beq.n 80227b4 <_printf_i+0x160> 8022878: 3501 adds r5, #1 802287a: 68e3 ldr r3, [r4, #12] 802287c: 9903 ldr r1, [sp, #12] 802287e: 1a5b subs r3, r3, r1 8022880: 42ab cmp r3, r5 8022882: dcf2 bgt.n 802286a <_printf_i+0x216> 8022884: e7eb b.n 802285e <_printf_i+0x20a> 8022886: 2500 movs r5, #0 8022888: f104 0619 add.w r6, r4, #25 802288c: e7f5 b.n 802287a <_printf_i+0x226> 802288e: bf00 nop 8022890: 08026ec5 .word 0x08026ec5 8022894: 08026ed6 .word 0x08026ed6 08022898 <__sflush_r>: 8022898: 898a ldrh r2, [r1, #12] 802289a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 802289e: 4605 mov r5, r0 80228a0: 0710 lsls r0, r2, #28 80228a2: 460c mov r4, r1 80228a4: d458 bmi.n 8022958 <__sflush_r+0xc0> 80228a6: 684b ldr r3, [r1, #4] 80228a8: 2b00 cmp r3, #0 80228aa: dc05 bgt.n 80228b8 <__sflush_r+0x20> 80228ac: 6c0b ldr r3, [r1, #64] ; 0x40 80228ae: 2b00 cmp r3, #0 80228b0: dc02 bgt.n 80228b8 <__sflush_r+0x20> 80228b2: 2000 movs r0, #0 80228b4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80228b8: 6ae6 ldr r6, [r4, #44] ; 0x2c 80228ba: 2e00 cmp r6, #0 80228bc: d0f9 beq.n 80228b2 <__sflush_r+0x1a> 80228be: 2300 movs r3, #0 80228c0: f412 5280 ands.w r2, r2, #4096 ; 0x1000 80228c4: 682f ldr r7, [r5, #0] 80228c6: 6a21 ldr r1, [r4, #32] 80228c8: 602b str r3, [r5, #0] 80228ca: d032 beq.n 8022932 <__sflush_r+0x9a> 80228cc: 6d60 ldr r0, [r4, #84] ; 0x54 80228ce: 89a3 ldrh r3, [r4, #12] 80228d0: 075a lsls r2, r3, #29 80228d2: d505 bpl.n 80228e0 <__sflush_r+0x48> 80228d4: 6863 ldr r3, [r4, #4] 80228d6: 1ac0 subs r0, r0, r3 80228d8: 6b63 ldr r3, [r4, #52] ; 0x34 80228da: b10b cbz r3, 80228e0 <__sflush_r+0x48> 80228dc: 6c23 ldr r3, [r4, #64] ; 0x40 80228de: 1ac0 subs r0, r0, r3 80228e0: 2300 movs r3, #0 80228e2: 4602 mov r2, r0 80228e4: 6ae6 ldr r6, [r4, #44] ; 0x2c 80228e6: 6a21 ldr r1, [r4, #32] 80228e8: 4628 mov r0, r5 80228ea: 47b0 blx r6 80228ec: 1c43 adds r3, r0, #1 80228ee: 89a3 ldrh r3, [r4, #12] 80228f0: d106 bne.n 8022900 <__sflush_r+0x68> 80228f2: 6829 ldr r1, [r5, #0] 80228f4: 291d cmp r1, #29 80228f6: d82b bhi.n 8022950 <__sflush_r+0xb8> 80228f8: 4a29 ldr r2, [pc, #164] ; (80229a0 <__sflush_r+0x108>) 80228fa: 410a asrs r2, r1 80228fc: 07d6 lsls r6, r2, #31 80228fe: d427 bmi.n 8022950 <__sflush_r+0xb8> 8022900: 2200 movs r2, #0 8022902: 6062 str r2, [r4, #4] 8022904: 04d9 lsls r1, r3, #19 8022906: 6922 ldr r2, [r4, #16] 8022908: 6022 str r2, [r4, #0] 802290a: d504 bpl.n 8022916 <__sflush_r+0x7e> 802290c: 1c42 adds r2, r0, #1 802290e: d101 bne.n 8022914 <__sflush_r+0x7c> 8022910: 682b ldr r3, [r5, #0] 8022912: b903 cbnz r3, 8022916 <__sflush_r+0x7e> 8022914: 6560 str r0, [r4, #84] ; 0x54 8022916: 6b61 ldr r1, [r4, #52] ; 0x34 8022918: 602f str r7, [r5, #0] 802291a: 2900 cmp r1, #0 802291c: d0c9 beq.n 80228b2 <__sflush_r+0x1a> 802291e: f104 0344 add.w r3, r4, #68 ; 0x44 8022922: 4299 cmp r1, r3 8022924: d002 beq.n 802292c <__sflush_r+0x94> 8022926: 4628 mov r0, r5 8022928: f7ff fa8a bl 8021e40 <_free_r> 802292c: 2000 movs r0, #0 802292e: 6360 str r0, [r4, #52] ; 0x34 8022930: e7c0 b.n 80228b4 <__sflush_r+0x1c> 8022932: 2301 movs r3, #1 8022934: 4628 mov r0, r5 8022936: 47b0 blx r6 8022938: 1c41 adds r1, r0, #1 802293a: d1c8 bne.n 80228ce <__sflush_r+0x36> 802293c: 682b ldr r3, [r5, #0] 802293e: 2b00 cmp r3, #0 8022940: d0c5 beq.n 80228ce <__sflush_r+0x36> 8022942: 2b1d cmp r3, #29 8022944: d001 beq.n 802294a <__sflush_r+0xb2> 8022946: 2b16 cmp r3, #22 8022948: d101 bne.n 802294e <__sflush_r+0xb6> 802294a: 602f str r7, [r5, #0] 802294c: e7b1 b.n 80228b2 <__sflush_r+0x1a> 802294e: 89a3 ldrh r3, [r4, #12] 8022950: f043 0340 orr.w r3, r3, #64 ; 0x40 8022954: 81a3 strh r3, [r4, #12] 8022956: e7ad b.n 80228b4 <__sflush_r+0x1c> 8022958: 690f ldr r7, [r1, #16] 802295a: 2f00 cmp r7, #0 802295c: d0a9 beq.n 80228b2 <__sflush_r+0x1a> 802295e: 0793 lsls r3, r2, #30 8022960: 680e ldr r6, [r1, #0] 8022962: bf08 it eq 8022964: 694b ldreq r3, [r1, #20] 8022966: 600f str r7, [r1, #0] 8022968: bf18 it ne 802296a: 2300 movne r3, #0 802296c: eba6 0807 sub.w r8, r6, r7 8022970: 608b str r3, [r1, #8] 8022972: f1b8 0f00 cmp.w r8, #0 8022976: dd9c ble.n 80228b2 <__sflush_r+0x1a> 8022978: 6a21 ldr r1, [r4, #32] 802297a: 6aa6 ldr r6, [r4, #40] ; 0x28 802297c: 4643 mov r3, r8 802297e: 463a mov r2, r7 8022980: 4628 mov r0, r5 8022982: 47b0 blx r6 8022984: 2800 cmp r0, #0 8022986: dc06 bgt.n 8022996 <__sflush_r+0xfe> 8022988: 89a3 ldrh r3, [r4, #12] 802298a: f043 0340 orr.w r3, r3, #64 ; 0x40 802298e: 81a3 strh r3, [r4, #12] 8022990: f04f 30ff mov.w r0, #4294967295 8022994: e78e b.n 80228b4 <__sflush_r+0x1c> 8022996: 4407 add r7, r0 8022998: eba8 0800 sub.w r8, r8, r0 802299c: e7e9 b.n 8022972 <__sflush_r+0xda> 802299e: bf00 nop 80229a0: dfbffffe .word 0xdfbffffe 080229a4 <_fflush_r>: 80229a4: b538 push {r3, r4, r5, lr} 80229a6: 690b ldr r3, [r1, #16] 80229a8: 4605 mov r5, r0 80229aa: 460c mov r4, r1 80229ac: b913 cbnz r3, 80229b4 <_fflush_r+0x10> 80229ae: 2500 movs r5, #0 80229b0: 4628 mov r0, r5 80229b2: bd38 pop {r3, r4, r5, pc} 80229b4: b118 cbz r0, 80229be <_fflush_r+0x1a> 80229b6: 6a03 ldr r3, [r0, #32] 80229b8: b90b cbnz r3, 80229be <_fflush_r+0x1a> 80229ba: f7fe ffaf bl 802191c <__sinit> 80229be: f9b4 300c ldrsh.w r3, [r4, #12] 80229c2: 2b00 cmp r3, #0 80229c4: d0f3 beq.n 80229ae <_fflush_r+0xa> 80229c6: 6e62 ldr r2, [r4, #100] ; 0x64 80229c8: 07d0 lsls r0, r2, #31 80229ca: d404 bmi.n 80229d6 <_fflush_r+0x32> 80229cc: 0599 lsls r1, r3, #22 80229ce: d402 bmi.n 80229d6 <_fflush_r+0x32> 80229d0: 6da0 ldr r0, [r4, #88] ; 0x58 80229d2: f7ff fa06 bl 8021de2 <__retarget_lock_acquire_recursive> 80229d6: 4628 mov r0, r5 80229d8: 4621 mov r1, r4 80229da: f7ff ff5d bl 8022898 <__sflush_r> 80229de: 6e63 ldr r3, [r4, #100] ; 0x64 80229e0: 07da lsls r2, r3, #31 80229e2: 4605 mov r5, r0 80229e4: d4e4 bmi.n 80229b0 <_fflush_r+0xc> 80229e6: 89a3 ldrh r3, [r4, #12] 80229e8: 059b lsls r3, r3, #22 80229ea: d4e1 bmi.n 80229b0 <_fflush_r+0xc> 80229ec: 6da0 ldr r0, [r4, #88] ; 0x58 80229ee: f7ff f9f9 bl 8021de4 <__retarget_lock_release_recursive> 80229f2: e7dd b.n 80229b0 <_fflush_r+0xc> 080229f4 : 80229f4: b40e push {r1, r2, r3} 80229f6: b503 push {r0, r1, lr} 80229f8: 4601 mov r1, r0 80229fa: ab03 add r3, sp, #12 80229fc: 4805 ldr r0, [pc, #20] ; (8022a14 ) 80229fe: f853 2b04 ldr.w r2, [r3], #4 8022a02: 6800 ldr r0, [r0, #0] 8022a04: 9301 str r3, [sp, #4] 8022a06: f7ff fc9d bl 8022344 <_vfiprintf_r> 8022a0a: b002 add sp, #8 8022a0c: f85d eb04 ldr.w lr, [sp], #4 8022a10: b003 add sp, #12 8022a12: 4770 bx lr 8022a14: 240000a0 .word 0x240000a0 08022a18 <__swhatbuf_r>: 8022a18: b570 push {r4, r5, r6, lr} 8022a1a: 460c mov r4, r1 8022a1c: f9b1 100e ldrsh.w r1, [r1, #14] 8022a20: 2900 cmp r1, #0 8022a22: b096 sub sp, #88 ; 0x58 8022a24: 4615 mov r5, r2 8022a26: 461e mov r6, r3 8022a28: da0d bge.n 8022a46 <__swhatbuf_r+0x2e> 8022a2a: 89a3 ldrh r3, [r4, #12] 8022a2c: f013 0f80 tst.w r3, #128 ; 0x80 8022a30: f04f 0100 mov.w r1, #0 8022a34: bf0c ite eq 8022a36: f44f 6380 moveq.w r3, #1024 ; 0x400 8022a3a: 2340 movne r3, #64 ; 0x40 8022a3c: 2000 movs r0, #0 8022a3e: 6031 str r1, [r6, #0] 8022a40: 602b str r3, [r5, #0] 8022a42: b016 add sp, #88 ; 0x58 8022a44: bd70 pop {r4, r5, r6, pc} 8022a46: 466a mov r2, sp 8022a48: f000 f87c bl 8022b44 <_fstat_r> 8022a4c: 2800 cmp r0, #0 8022a4e: dbec blt.n 8022a2a <__swhatbuf_r+0x12> 8022a50: 9901 ldr r1, [sp, #4] 8022a52: f401 4170 and.w r1, r1, #61440 ; 0xf000 8022a56: f5a1 5300 sub.w r3, r1, #8192 ; 0x2000 8022a5a: 4259 negs r1, r3 8022a5c: 4159 adcs r1, r3 8022a5e: f44f 6380 mov.w r3, #1024 ; 0x400 8022a62: e7eb b.n 8022a3c <__swhatbuf_r+0x24> 08022a64 <__smakebuf_r>: 8022a64: 898b ldrh r3, [r1, #12] 8022a66: b573 push {r0, r1, r4, r5, r6, lr} 8022a68: 079d lsls r5, r3, #30 8022a6a: 4606 mov r6, r0 8022a6c: 460c mov r4, r1 8022a6e: d507 bpl.n 8022a80 <__smakebuf_r+0x1c> 8022a70: f104 0347 add.w r3, r4, #71 ; 0x47 8022a74: 6023 str r3, [r4, #0] 8022a76: 6123 str r3, [r4, #16] 8022a78: 2301 movs r3, #1 8022a7a: 6163 str r3, [r4, #20] 8022a7c: b002 add sp, #8 8022a7e: bd70 pop {r4, r5, r6, pc} 8022a80: ab01 add r3, sp, #4 8022a82: 466a mov r2, sp 8022a84: f7ff ffc8 bl 8022a18 <__swhatbuf_r> 8022a88: 9900 ldr r1, [sp, #0] 8022a8a: 4605 mov r5, r0 8022a8c: 4630 mov r0, r6 8022a8e: f7ff fa4b bl 8021f28 <_malloc_r> 8022a92: b948 cbnz r0, 8022aa8 <__smakebuf_r+0x44> 8022a94: f9b4 300c ldrsh.w r3, [r4, #12] 8022a98: 059a lsls r2, r3, #22 8022a9a: d4ef bmi.n 8022a7c <__smakebuf_r+0x18> 8022a9c: f023 0303 bic.w r3, r3, #3 8022aa0: f043 0302 orr.w r3, r3, #2 8022aa4: 81a3 strh r3, [r4, #12] 8022aa6: e7e3 b.n 8022a70 <__smakebuf_r+0xc> 8022aa8: 89a3 ldrh r3, [r4, #12] 8022aaa: 6020 str r0, [r4, #0] 8022aac: f043 0380 orr.w r3, r3, #128 ; 0x80 8022ab0: 81a3 strh r3, [r4, #12] 8022ab2: 9b00 ldr r3, [sp, #0] 8022ab4: 6163 str r3, [r4, #20] 8022ab6: 9b01 ldr r3, [sp, #4] 8022ab8: 6120 str r0, [r4, #16] 8022aba: b15b cbz r3, 8022ad4 <__smakebuf_r+0x70> 8022abc: f9b4 100e ldrsh.w r1, [r4, #14] 8022ac0: 4630 mov r0, r6 8022ac2: f000 f851 bl 8022b68 <_isatty_r> 8022ac6: b128 cbz r0, 8022ad4 <__smakebuf_r+0x70> 8022ac8: 89a3 ldrh r3, [r4, #12] 8022aca: f023 0303 bic.w r3, r3, #3 8022ace: f043 0301 orr.w r3, r3, #1 8022ad2: 81a3 strh r3, [r4, #12] 8022ad4: 89a3 ldrh r3, [r4, #12] 8022ad6: 431d orrs r5, r3 8022ad8: 81a5 strh r5, [r4, #12] 8022ada: e7cf b.n 8022a7c <__smakebuf_r+0x18> 08022adc <_putc_r>: 8022adc: b570 push {r4, r5, r6, lr} 8022ade: 460d mov r5, r1 8022ae0: 4614 mov r4, r2 8022ae2: 4606 mov r6, r0 8022ae4: b118 cbz r0, 8022aee <_putc_r+0x12> 8022ae6: 6a03 ldr r3, [r0, #32] 8022ae8: b90b cbnz r3, 8022aee <_putc_r+0x12> 8022aea: f7fe ff17 bl 802191c <__sinit> 8022aee: 6e63 ldr r3, [r4, #100] ; 0x64 8022af0: 07d8 lsls r0, r3, #31 8022af2: d405 bmi.n 8022b00 <_putc_r+0x24> 8022af4: 89a3 ldrh r3, [r4, #12] 8022af6: 0599 lsls r1, r3, #22 8022af8: d402 bmi.n 8022b00 <_putc_r+0x24> 8022afa: 6da0 ldr r0, [r4, #88] ; 0x58 8022afc: f7ff f971 bl 8021de2 <__retarget_lock_acquire_recursive> 8022b00: 68a3 ldr r3, [r4, #8] 8022b02: 3b01 subs r3, #1 8022b04: 2b00 cmp r3, #0 8022b06: 60a3 str r3, [r4, #8] 8022b08: da05 bge.n 8022b16 <_putc_r+0x3a> 8022b0a: 69a2 ldr r2, [r4, #24] 8022b0c: 4293 cmp r3, r2 8022b0e: db12 blt.n 8022b36 <_putc_r+0x5a> 8022b10: b2eb uxtb r3, r5 8022b12: 2b0a cmp r3, #10 8022b14: d00f beq.n 8022b36 <_putc_r+0x5a> 8022b16: 6823 ldr r3, [r4, #0] 8022b18: 1c5a adds r2, r3, #1 8022b1a: 6022 str r2, [r4, #0] 8022b1c: 701d strb r5, [r3, #0] 8022b1e: b2ed uxtb r5, r5 8022b20: 6e63 ldr r3, [r4, #100] ; 0x64 8022b22: 07da lsls r2, r3, #31 8022b24: d405 bmi.n 8022b32 <_putc_r+0x56> 8022b26: 89a3 ldrh r3, [r4, #12] 8022b28: 059b lsls r3, r3, #22 8022b2a: d402 bmi.n 8022b32 <_putc_r+0x56> 8022b2c: 6da0 ldr r0, [r4, #88] ; 0x58 8022b2e: f7ff f959 bl 8021de4 <__retarget_lock_release_recursive> 8022b32: 4628 mov r0, r5 8022b34: bd70 pop {r4, r5, r6, pc} 8022b36: 4629 mov r1, r5 8022b38: 4622 mov r2, r4 8022b3a: 4630 mov r0, r6 8022b3c: f7ff f811 bl 8021b62 <__swbuf_r> 8022b40: 4605 mov r5, r0 8022b42: e7ed b.n 8022b20 <_putc_r+0x44> 08022b44 <_fstat_r>: 8022b44: b538 push {r3, r4, r5, lr} 8022b46: 4d07 ldr r5, [pc, #28] ; (8022b64 <_fstat_r+0x20>) 8022b48: 2300 movs r3, #0 8022b4a: 4604 mov r4, r0 8022b4c: 4608 mov r0, r1 8022b4e: 4611 mov r1, r2 8022b50: 602b str r3, [r5, #0] 8022b52: f7df f944 bl 8001dde <_fstat> 8022b56: 1c43 adds r3, r0, #1 8022b58: d102 bne.n 8022b60 <_fstat_r+0x1c> 8022b5a: 682b ldr r3, [r5, #0] 8022b5c: b103 cbz r3, 8022b60 <_fstat_r+0x1c> 8022b5e: 6023 str r3, [r4, #0] 8022b60: bd38 pop {r3, r4, r5, pc} 8022b62: bf00 nop 8022b64: 2401a5e0 .word 0x2401a5e0 08022b68 <_isatty_r>: 8022b68: b538 push {r3, r4, r5, lr} 8022b6a: 4d06 ldr r5, [pc, #24] ; (8022b84 <_isatty_r+0x1c>) 8022b6c: 2300 movs r3, #0 8022b6e: 4604 mov r4, r0 8022b70: 4608 mov r0, r1 8022b72: 602b str r3, [r5, #0] 8022b74: f7df f943 bl 8001dfe <_isatty> 8022b78: 1c43 adds r3, r0, #1 8022b7a: d102 bne.n 8022b82 <_isatty_r+0x1a> 8022b7c: 682b ldr r3, [r5, #0] 8022b7e: b103 cbz r3, 8022b82 <_isatty_r+0x1a> 8022b80: 6023 str r3, [r4, #0] 8022b82: bd38 pop {r3, r4, r5, pc} 8022b84: 2401a5e0 .word 0x2401a5e0 08022b88 <_sbrk_r>: 8022b88: b538 push {r3, r4, r5, lr} 8022b8a: 4d06 ldr r5, [pc, #24] ; (8022ba4 <_sbrk_r+0x1c>) 8022b8c: 2300 movs r3, #0 8022b8e: 4604 mov r4, r0 8022b90: 4608 mov r0, r1 8022b92: 602b str r3, [r5, #0] 8022b94: f7df f94c bl 8001e30 <_sbrk> 8022b98: 1c43 adds r3, r0, #1 8022b9a: d102 bne.n 8022ba2 <_sbrk_r+0x1a> 8022b9c: 682b ldr r3, [r5, #0] 8022b9e: b103 cbz r3, 8022ba2 <_sbrk_r+0x1a> 8022ba0: 6023 str r3, [r4, #0] 8022ba2: bd38 pop {r3, r4, r5, pc} 8022ba4: 2401a5e0 .word 0x2401a5e0 08022ba8 : 8022ba8: b508 push {r3, lr} 8022baa: 2006 movs r0, #6 8022bac: f000 f85a bl 8022c64 8022bb0: 2001 movs r0, #1 8022bb2: f7df f8e1 bl 8001d78 <_exit> 08022bb6 <_realloc_r>: 8022bb6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8022bba: 4680 mov r8, r0 8022bbc: 4614 mov r4, r2 8022bbe: 460e mov r6, r1 8022bc0: b921 cbnz r1, 8022bcc <_realloc_r+0x16> 8022bc2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8022bc6: 4611 mov r1, r2 8022bc8: f7ff b9ae b.w 8021f28 <_malloc_r> 8022bcc: b92a cbnz r2, 8022bda <_realloc_r+0x24> 8022bce: f7ff f937 bl 8021e40 <_free_r> 8022bd2: 4625 mov r5, r4 8022bd4: 4628 mov r0, r5 8022bd6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8022bda: f000 f85f bl 8022c9c <_malloc_usable_size_r> 8022bde: 4284 cmp r4, r0 8022be0: 4607 mov r7, r0 8022be2: d802 bhi.n 8022bea <_realloc_r+0x34> 8022be4: ebb4 0f50 cmp.w r4, r0, lsr #1 8022be8: d812 bhi.n 8022c10 <_realloc_r+0x5a> 8022bea: 4621 mov r1, r4 8022bec: 4640 mov r0, r8 8022bee: f7ff f99b bl 8021f28 <_malloc_r> 8022bf2: 4605 mov r5, r0 8022bf4: 2800 cmp r0, #0 8022bf6: d0ed beq.n 8022bd4 <_realloc_r+0x1e> 8022bf8: 42bc cmp r4, r7 8022bfa: 4622 mov r2, r4 8022bfc: 4631 mov r1, r6 8022bfe: bf28 it cs 8022c00: 463a movcs r2, r7 8022c02: f7ff f8f0 bl 8021de6 8022c06: 4631 mov r1, r6 8022c08: 4640 mov r0, r8 8022c0a: f7ff f919 bl 8021e40 <_free_r> 8022c0e: e7e1 b.n 8022bd4 <_realloc_r+0x1e> 8022c10: 4635 mov r5, r6 8022c12: e7df b.n 8022bd4 <_realloc_r+0x1e> 08022c14 <_raise_r>: 8022c14: 291f cmp r1, #31 8022c16: b538 push {r3, r4, r5, lr} 8022c18: 4604 mov r4, r0 8022c1a: 460d mov r5, r1 8022c1c: d904 bls.n 8022c28 <_raise_r+0x14> 8022c1e: 2316 movs r3, #22 8022c20: 6003 str r3, [r0, #0] 8022c22: f04f 30ff mov.w r0, #4294967295 8022c26: bd38 pop {r3, r4, r5, pc} 8022c28: 6bc2 ldr r2, [r0, #60] ; 0x3c 8022c2a: b112 cbz r2, 8022c32 <_raise_r+0x1e> 8022c2c: f852 3021 ldr.w r3, [r2, r1, lsl #2] 8022c30: b94b cbnz r3, 8022c46 <_raise_r+0x32> 8022c32: 4620 mov r0, r4 8022c34: f000 f830 bl 8022c98 <_getpid_r> 8022c38: 462a mov r2, r5 8022c3a: 4601 mov r1, r0 8022c3c: 4620 mov r0, r4 8022c3e: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8022c42: f000 b817 b.w 8022c74 <_kill_r> 8022c46: 2b01 cmp r3, #1 8022c48: d00a beq.n 8022c60 <_raise_r+0x4c> 8022c4a: 1c59 adds r1, r3, #1 8022c4c: d103 bne.n 8022c56 <_raise_r+0x42> 8022c4e: 2316 movs r3, #22 8022c50: 6003 str r3, [r0, #0] 8022c52: 2001 movs r0, #1 8022c54: e7e7 b.n 8022c26 <_raise_r+0x12> 8022c56: 2400 movs r4, #0 8022c58: f842 4025 str.w r4, [r2, r5, lsl #2] 8022c5c: 4628 mov r0, r5 8022c5e: 4798 blx r3 8022c60: 2000 movs r0, #0 8022c62: e7e0 b.n 8022c26 <_raise_r+0x12> 08022c64 : 8022c64: 4b02 ldr r3, [pc, #8] ; (8022c70 ) 8022c66: 4601 mov r1, r0 8022c68: 6818 ldr r0, [r3, #0] 8022c6a: f7ff bfd3 b.w 8022c14 <_raise_r> 8022c6e: bf00 nop 8022c70: 240000a0 .word 0x240000a0 08022c74 <_kill_r>: 8022c74: b538 push {r3, r4, r5, lr} 8022c76: 4d07 ldr r5, [pc, #28] ; (8022c94 <_kill_r+0x20>) 8022c78: 2300 movs r3, #0 8022c7a: 4604 mov r4, r0 8022c7c: 4608 mov r0, r1 8022c7e: 4611 mov r1, r2 8022c80: 602b str r3, [r5, #0] 8022c82: f7df f867 bl 8001d54 <_kill> 8022c86: 1c43 adds r3, r0, #1 8022c88: d102 bne.n 8022c90 <_kill_r+0x1c> 8022c8a: 682b ldr r3, [r5, #0] 8022c8c: b103 cbz r3, 8022c90 <_kill_r+0x1c> 8022c8e: 6023 str r3, [r4, #0] 8022c90: bd38 pop {r3, r4, r5, pc} 8022c92: bf00 nop 8022c94: 2401a5e0 .word 0x2401a5e0 08022c98 <_getpid_r>: 8022c98: f7df b854 b.w 8001d44 <_getpid> 08022c9c <_malloc_usable_size_r>: 8022c9c: f851 3c04 ldr.w r3, [r1, #-4] 8022ca0: 1f18 subs r0, r3, #4 8022ca2: 2b00 cmp r3, #0 8022ca4: bfbc itt lt 8022ca6: 580b ldrlt r3, [r1, r0] 8022ca8: 18c0 addlt r0, r0, r3 8022caa: 4770 bx lr 08022cac <_init>: 8022cac: b5f8 push {r3, r4, r5, r6, r7, lr} 8022cae: bf00 nop 8022cb0: bcf8 pop {r3, r4, r5, r6, r7} 8022cb2: bc08 pop {r3} 8022cb4: 469e mov lr, r3 8022cb6: 4770 bx lr 08022cb8 <_fini>: 8022cb8: b5f8 push {r3, r4, r5, r6, r7, lr} 8022cba: bf00 nop 8022cbc: bcf8 pop {r3, r4, r5, r6, r7} 8022cbe: bc08 pop {r3} 8022cc0: 469e mov lr, r3 8022cc2: 4770 bx lr