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SeungJu Lim 2024-02-29 17:13:44 +09:00
parent 531862a0f9
commit f794e86f5c
1016 changed files with 789 additions and 502600 deletions
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240
.cproject
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@ -1,240 +0,0 @@
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org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"}
org.eclipse.cdt.codan.internal.checkers.BlacklistProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.BlacklistProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function or method is blacklisted\\")",blacklist\=>()}
org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"C-Style cast instead of C++ cast\\")",checkMacro\=>true}
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false}
org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"}
org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true}
org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"}
org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"}
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Direct float comparison\\")"}
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"}
org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"}
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"}
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"}
org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Avoid magic numbers\\")",checkArray\=>true,checkOperatorParen\=>true,exceptions\=>(1,0,-1,2,1.0,0.0,-1.0)}
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"}
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"}
org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false}
org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"}
org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"}
org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Multiple variable declaration\\")"}
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.NoDiscardProblem=Warning
org.eclipse.cdt.codan.internal.checkers.NoDiscardProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return value not evaluated\\")",macro\=>true}
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"}
org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"}
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"}
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"}
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"}
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"}
org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Miss copy constructor or assignment operator\\")",onlynew\=>false}
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Static variable in header file\\")"}
org.eclipse.cdt.codan.internal.checkers.StructuredBindingDeclarationProblem=Error
org.eclipse.cdt.codan.internal.checkers.StructuredBindingDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid structured binding declaration\\")"}
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false}
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false}
org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol shadowing\\")",paramFuncParameters\=>true}
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true}
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true}
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")}
org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"}
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error
org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"}

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147
Core/Inc/FreeRTOSConfig.h
View File

@ -1,147 +0,0 @@
/* USER CODE BEGIN Header */
/*
* FreeRTOS Kernel V10.3.1
* Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* USER CODE END Header */
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* These parameters and more are described within the 'configuration' section of the
* FreeRTOS API documentation available on the FreeRTOS.org web site.
*
* See http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* Section where include file can be added */
/* USER CODE END Includes */
/* Ensure definitions are only used by the compiler, and not by the assembler. */
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif
#define configENABLE_FPU 0
#define configENABLE_MPU 0
#define configUSE_PREEMPTION 1
#define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES ( 7 )
#define configMINIMAL_STACK_SIZE ((uint16_t)256)
#define configTOTAL_HEAP_SIZE ((size_t)30720)
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_16_BIT_TICKS 0
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
/* Defaults to size_t for backward compatibility, but can be changed
if lengths will always be less than the number of bytes in a size_t. */
#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH 512
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 1
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
/* USER CODE BEGIN 1 */
#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
#define INCLUDE_uxTaskGetStackHighWaterMark 1 // To check stack usage of task
/* USER CODE END 1 */
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick,
to prevent overwriting SysTick_Handler defined within STM32Cube HAL */
#define xPortSysTickHandler SysTick_Handler
/* USER CODE BEGIN Defines */
/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
/* USER CODE END Defines */
#endif /* FREERTOS_CONFIG_H */

83
Core/Inc/main.h
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define mLED_Pin GPIO_PIN_15
#define mLED_GPIO_Port GPIOA
#define SD_LED_Pin GPIO_PIN_10
#define SD_LED_GPIO_Port GPIOE
#define sdDetect_Pin GPIO_PIN_15
#define sdDetect_GPIO_Port GPIOB
#define VIN_IG_Pin GPIO_PIN_11
#define VIN_IG_GPIO_Port GPIOE
#define VIN_ON_Pin GPIO_PIN_12
#define VIN_ON_GPIO_Port GPIOE
#define PICO_EN_Pin GPIO_PIN_9
#define PICO_EN_GPIO_Port GPIOE
#define VIN_1_4_Pin GPIO_PIN_13
#define VIN_1_4_GPIO_Port GPIOE
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */

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Core/Inc/stm32h7xx_hal_conf.h
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_CONF_H
#define STM32H7xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
#define HAL_FDCAN_MODULE_ENABLED
/* #define HAL_FMAC_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_COMP_MODULE_ENABLED */
/* #define HAL_CORDIC_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */
/* #define HAL_DCMI_MODULE_ENABLED */
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_OTFDEC_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
/* #define HAL_SDRAM_MODULE_ENABLED */
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_HRTIM_MODULE_ENABLED */
/* #define HAL_HSEM_MODULE_ENABLED */
/* #define HAL_GFXMMU_MODULE_ENABLED */
/* #define HAL_JPEG_MODULE_ENABLED */
/* #define HAL_OPAMP_MODULE_ENABLED */
/* #define HAL_OSPI_MODULE_ENABLED */
/* #define HAL_OSPI_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_RAMECC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
/* #define HAL_MMC_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */
/* #define HAL_SPI_MODULE_ENABLED */
/* #define HAL_SWPMI_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
/* #define HAL_PCD_MODULE_ENABLED */
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
/* #define HAL_JPEG_MODULE_ENABLED */
/* #define HAL_MDIOS_MODULE_ENABLED */
/* #define HAL_PSSI_MODULE_ENABLED */
/* #define HAL_DTS_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_MDMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_HSEM_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal oscillator (CSI) default value.
* This value is the default CSI value after Reset.
*/
#if !defined (CSI_VALUE)
#define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
#if !defined (LSI_VALUE)
#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */
#define USE_RTOS 0
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */
#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
/* ########################### Ethernet Configuration ######################### */
#define ETH_TX_DESC_CNT 4U /* number of Ethernet Tx DMA descriptors */
#define ETH_RX_DESC_CNT 4U /* number of Ethernet Rx DMA descriptors */
#define ETH_MAC_ADDR0 (0x02UL)
#define ETH_MAC_ADDR1 (0x00UL)
#define ETH_MAC_ADDR2 (0x00UL)
#define ETH_MAC_ADDR3 (0x00UL)
#define ETH_MAC_ADDR4 (0x00UL)
#define ETH_MAC_ADDR5 (0x00UL)
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32h7xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32h7xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32h7xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_MDMA_MODULE_ENABLED
#include "stm32h7xx_hal_mdma.h"
#endif /* HAL_MDMA_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32h7xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32h7xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32h7xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32h7xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32h7xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_DTS_MODULE_ENABLED
#include "stm32h7xx_hal_dts.h"
#endif /* HAL_DTS_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32h7xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
#include "stm32h7xx_hal_eth_legacy.h"
#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32h7xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32h7xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32h7xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_FDCAN_MODULE_ENABLED
#include "stm32h7xx_hal_fdcan.h"
#endif /* HAL_FDCAN_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32h7xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32h7xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CORDIC_MODULE_ENABLED
#include "stm32h7xx_hal_cordic.h"
#endif /* HAL_CORDIC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32h7xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32h7xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32h7xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32h7xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_GFXMMU_MODULE_ENABLED
#include "stm32h7xx_hal_gfxmmu.h"
#endif /* HAL_GFXMMU_MODULE_ENABLED */
#ifdef HAL_FMAC_MODULE_ENABLED
#include "stm32h7xx_hal_fmac.h"
#endif /* HAL_FMAC_MODULE_ENABLED */
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32h7xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
#ifdef HAL_HSEM_MODULE_ENABLED
#include "stm32h7xx_hal_hsem.h"
#endif /* HAL_HSEM_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32h7xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32h7xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32h7xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32h7xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32h7xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32h7xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_JPEG_MODULE_ENABLED
#include "stm32h7xx_hal_jpeg.h"
#endif /* HAL_JPEG_MODULE_ENABLED */
#ifdef HAL_MDIOS_MODULE_ENABLED
#include "stm32h7xx_hal_mdios.h"
#endif /* HAL_MDIOS_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32h7xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32h7xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32h7xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32h7xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_OSPI_MODULE_ENABLED
#include "stm32h7xx_hal_ospi.h"
#endif /* HAL_OSPI_MODULE_ENABLED */
#ifdef HAL_OTFDEC_MODULE_ENABLED
#include "stm32h7xx_hal_otfdec.h"
#endif /* HAL_OTFDEC_MODULE_ENABLED */
#ifdef HAL_PSSI_MODULE_ENABLED
#include "stm32h7xx_hal_pssi.h"
#endif /* HAL_PSSI_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32h7xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32h7xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RAMECC_MODULE_ENABLED
#include "stm32h7xx_hal_ramecc.h"
#endif /* HAL_RAMECC_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32h7xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32h7xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32h7xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32h7xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32h7xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32h7xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32h7xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
#ifdef HAL_SWPMI_MODULE_ENABLED
#include "stm32h7xx_hal_swpmi.h"
#endif /* HAL_SWPMI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32h7xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32h7xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32h7xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32h7xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32h7xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32h7xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32h7xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32h7xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32h7xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7xx_HAL_CONF_H */

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Core/Inc/stm32h7xx_it.h
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@ -1,71 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_IT_H
#define __STM32H7xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void DebugMon_Handler(void);
void DMA1_Stream0_IRQHandler(void);
void FDCAN1_IT0_IRQHandler(void);
void FDCAN2_IT0_IRQHandler(void);
void SDMMC1_IRQHandler(void);
void TIM6_DAC_IRQHandler(void);
void ETH_IRQHandler(void);
void MDMA_IRQHandler(void);
void FDCAN3_IT0_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_IT_H */

102
Core/Src/freertos.c
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@ -1,102 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : freertos.c
* Description : Code for freertos applications
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "FreeRTOS.h"
#include "task.h"
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN Variables */
/* USER CODE END Variables */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN FunctionPrototypes */
/* USER CODE END FunctionPrototypes */
/* GetIdleTaskMemory prototype (linked to static allocation support) */
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
/* GetTimerTaskMemory prototype (linked to static allocation support) */
void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
/* Hook prototypes */
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);
/* USER CODE BEGIN 4 */
__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
{
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
called if a stack overflow is detected. */
}
/* USER CODE END 4 */
/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
static StaticTask_t xIdleTaskTCBBuffer;
static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
{
*ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
*ppxIdleTaskStackBuffer = &xIdleStack[0];
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
/* place for user code */
}
/* USER CODE END GET_IDLE_TASK_MEMORY */
/* USER CODE BEGIN GET_TIMER_TASK_MEMORY */
static StaticTask_t xTimerTaskTCBBuffer;
static StackType_t xTimerStack[configTIMER_TASK_STACK_DEPTH];
void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
{
*ppxTimerTaskTCBBuffer = &xTimerTaskTCBBuffer;
*ppxTimerTaskStackBuffer = &xTimerStack[0];
*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
/* place for user code */
}
/* USER CODE END GET_TIMER_TASK_MEMORY */
/* Private application code --------------------------------------------------*/
/* USER CODE BEGIN Application */
/* USER CODE END Application */

958
Core/Src/main.c
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@ -1,958 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "cmsis_os.h"
#include "fatfs.h"
#include "lwip.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include <stdio.h>
#include <string.h>
#include "lwip/api.h"
#include "lwftpc.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
FDCAN_HandleTypeDef hfdcan1;
FDCAN_HandleTypeDef hfdcan2;
FDCAN_HandleTypeDef hfdcan3;
SD_HandleTypeDef hsd1;
TIM_HandleTypeDef htim3;
UART_HandleTypeDef huart4;
UART_HandleTypeDef huart7;
UART_HandleTypeDef huart8;
DMA_HandleTypeDef hdma_uart8_rx;
MDMA_HandleTypeDef hmdma_mdma_channel0_sdmmc1_end_data_0;
osThreadId defaultTaskHandle;
uint32_t defaultTaskBuffer[ 4096 ];
osStaticThreadDef_t defaultTaskControlBlock;
osThreadId debugTaskHandle;
uint32_t debugTaskBuffer[ 2048 ];
osStaticThreadDef_t debugTaskControlBlock;
/* USER CODE BEGIN PV */
#define FTPSemaphore 0
static lwftp_session_t s;
sys_sem_t ftpsem;
uint8_t CLI_IP[4] = { 192, 168, 0, 120 }; // client addr
uint8_t SVR_IP[4] = { 192, 168, 0, 100 }; // server addr
u16_t SVR_PORT = 21;
char *USER = "anonymous";
char *PASS = "email@example.com";
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MPU_Config(void);
static void MX_GPIO_Init(void);
static void MX_DMA_Init(void);
static void MX_MDMA_Init(void);
static void MX_FDCAN3_Init(void);
static void MX_SDMMC1_SD_Init(void);
static void MX_TIM3_Init(void);
static void MX_UART4_Init(void);
static void MX_UART7_Init(void);
static void MX_FDCAN1_Init(void);
static void MX_FDCAN2_Init(void);
static void MX_UART8_Init(void);
void StartDefaultTask(void const * argument);
void StartDebugTask(void const * argument);
/* USER CODE BEGIN PFP */
// Function to send the data to the server
void lwftp_init(void);
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
int _write(int32_t file, uint8_t *ptr, int32_t len) {
for (int32_t i = 0; i < len; ++i)
ITM_SendChar(*ptr++);
return len;
}
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MPU Configuration--------------------------------------------------------*/
MPU_Config();
/* Enable the CPU Cache */
/* Enable I-Cache---------------------------------------------------------*/
SCB_EnableICache();
/* Enable D-Cache---------------------------------------------------------*/
SCB_EnableDCache();
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_DMA_Init();
MX_MDMA_Init();
MX_FDCAN3_Init();
MX_SDMMC1_SD_Init();
MX_TIM3_Init();
MX_UART4_Init();
MX_UART7_Init();
MX_FDCAN1_Init();
MX_FDCAN2_Init();
MX_FATFS_Init();
MX_UART8_Init();
/* USER CODE BEGIN 2 */
#define RTOS_MODE 1
#if RTOS_MODE
/* USER CODE END 2 */
/* USER CODE BEGIN RTOS_MUTEX */
/* add mutexes, ... */
/* USER CODE END RTOS_MUTEX */
/* USER CODE BEGIN RTOS_SEMAPHORES */
/* add semaphores, ... */
/* USER CODE END RTOS_SEMAPHORES */
/* USER CODE BEGIN RTOS_TIMERS */
/* start timers, add new ones, ... */
/* USER CODE END RTOS_TIMERS */
/* USER CODE BEGIN RTOS_QUEUES */
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* definition and creation of defaultTask */
osThreadStaticDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 4096, defaultTaskBuffer, &defaultTaskControlBlock);
defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
/* definition and creation of debugTask */
osThreadStaticDef(debugTask, StartDebugTask, osPriorityNormal, 0, 2048, debugTaskBuffer, &debugTaskControlBlock);
debugTaskHandle = osThreadCreate(osThread(debugTask), NULL);
/* USER CODE BEGIN RTOS_THREADS */
/* add threads, ... */
/* USER CODE END RTOS_THREADS */
/* Start scheduler */
osKernelStart();
/* We should never get here as control is now taken by the scheduler */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
#else
MX_LWIP_Init();
while (1) {
MX_LWIP_Process();
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
#endif
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Supply configuration update enable
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 5;
RCC_OscInitStruct.PLL.PLLN = 96;
RCC_OscInitStruct.PLL.PLLP = 1;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief FDCAN1 Initialization Function
* @param None
* @retval None
*/
static void MX_FDCAN1_Init(void)
{
/* USER CODE BEGIN FDCAN1_Init 0 */
/* USER CODE END FDCAN1_Init 0 */
/* USER CODE BEGIN FDCAN1_Init 1 */
/* USER CODE END FDCAN1_Init 1 */
hfdcan1.Instance = FDCAN1;
hfdcan1.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
hfdcan1.Init.AutoRetransmission = DISABLE;
hfdcan1.Init.TransmitPause = DISABLE;
hfdcan1.Init.ProtocolException = DISABLE;
hfdcan1.Init.NominalPrescaler = 6;
hfdcan1.Init.NominalSyncJumpWidth = 4;
hfdcan1.Init.NominalTimeSeg1 = 29;
hfdcan1.Init.NominalTimeSeg2 = 10;
hfdcan1.Init.DataPrescaler = 4;
hfdcan1.Init.DataSyncJumpWidth = 4;
hfdcan1.Init.DataTimeSeg1 = 11;
hfdcan1.Init.DataTimeSeg2 = 3;
hfdcan1.Init.MessageRAMOffset = 0;
hfdcan1.Init.StdFiltersNbr = 0;
hfdcan1.Init.ExtFiltersNbr = 0;
hfdcan1.Init.RxFifo0ElmtsNbr = 8;
hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
hfdcan1.Init.RxFifo1ElmtsNbr = 0;
hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
hfdcan1.Init.RxBuffersNbr = 0;
hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
hfdcan1.Init.TxEventsNbr = 8;
hfdcan1.Init.TxBuffersNbr = 0;
hfdcan1.Init.TxFifoQueueElmtsNbr = 8;
hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN FDCAN1_Init 2 */
/* USER CODE END FDCAN1_Init 2 */
}
/**
* @brief FDCAN2 Initialization Function
* @param None
* @retval None
*/
static void MX_FDCAN2_Init(void)
{
/* USER CODE BEGIN FDCAN2_Init 0 */
/* USER CODE END FDCAN2_Init 0 */
/* USER CODE BEGIN FDCAN2_Init 1 */
/* USER CODE END FDCAN2_Init 1 */
hfdcan2.Instance = FDCAN2;
hfdcan2.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
hfdcan2.Init.AutoRetransmission = DISABLE;
hfdcan2.Init.TransmitPause = DISABLE;
hfdcan2.Init.ProtocolException = DISABLE;
hfdcan2.Init.NominalPrescaler = 6;
hfdcan2.Init.NominalSyncJumpWidth = 4;
hfdcan2.Init.NominalTimeSeg1 = 29;
hfdcan2.Init.NominalTimeSeg2 = 10;
hfdcan2.Init.DataPrescaler = 4;
hfdcan2.Init.DataSyncJumpWidth = 4;
hfdcan2.Init.DataTimeSeg1 = 11;
hfdcan2.Init.DataTimeSeg2 = 3;
hfdcan2.Init.MessageRAMOffset = 512;
hfdcan2.Init.StdFiltersNbr = 0;
hfdcan2.Init.ExtFiltersNbr = 0;
hfdcan2.Init.RxFifo0ElmtsNbr = 8;
hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
hfdcan2.Init.RxFifo1ElmtsNbr = 0;
hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
hfdcan2.Init.RxBuffersNbr = 0;
hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
hfdcan2.Init.TxEventsNbr = 8;
hfdcan2.Init.TxBuffersNbr = 0;
hfdcan2.Init.TxFifoQueueElmtsNbr = 8;
hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN FDCAN2_Init 2 */
/* USER CODE END FDCAN2_Init 2 */
}
/**
* @brief FDCAN3 Initialization Function
* @param None
* @retval None
*/
static void MX_FDCAN3_Init(void)
{
/* USER CODE BEGIN FDCAN3_Init 0 */
/* USER CODE END FDCAN3_Init 0 */
/* USER CODE BEGIN FDCAN3_Init 1 */
/* USER CODE END FDCAN3_Init 1 */
hfdcan3.Instance = FDCAN3;
hfdcan3.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
hfdcan3.Init.Mode = FDCAN_MODE_NORMAL;
hfdcan3.Init.AutoRetransmission = DISABLE;
hfdcan3.Init.TransmitPause = DISABLE;
hfdcan3.Init.ProtocolException = DISABLE;
hfdcan3.Init.NominalPrescaler = 6;
hfdcan3.Init.NominalSyncJumpWidth = 4;
hfdcan3.Init.NominalTimeSeg1 = 29;
hfdcan3.Init.NominalTimeSeg2 = 10;
hfdcan3.Init.DataPrescaler = 4;
hfdcan3.Init.DataSyncJumpWidth = 4;
hfdcan3.Init.DataTimeSeg1 = 11;
hfdcan3.Init.DataTimeSeg2 = 3;
hfdcan3.Init.MessageRAMOffset = 1024;
hfdcan3.Init.StdFiltersNbr = 0;
hfdcan3.Init.ExtFiltersNbr = 0;
hfdcan3.Init.RxFifo0ElmtsNbr = 8;
hfdcan3.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
hfdcan3.Init.RxFifo1ElmtsNbr = 0;
hfdcan3.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
hfdcan3.Init.RxBuffersNbr = 0;
hfdcan3.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
hfdcan3.Init.TxEventsNbr = 8;
hfdcan3.Init.TxBuffersNbr = 0;
hfdcan3.Init.TxFifoQueueElmtsNbr = 8;
hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
hfdcan3.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN FDCAN3_Init 2 */
/* USER CODE END FDCAN3_Init 2 */
}
/**
* @brief SDMMC1 Initialization Function
* @param None
* @retval None
*/
static void MX_SDMMC1_SD_Init(void)
{
/* USER CODE BEGIN SDMMC1_Init 0 */
/* USER CODE END SDMMC1_Init 0 */
/* USER CODE BEGIN SDMMC1_Init 1 */
/* USER CODE END SDMMC1_Init 1 */
hsd1.Instance = SDMMC1;
hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE;
hsd1.Init.ClockDiv = 1;
/* USER CODE BEGIN SDMMC1_Init 2 */
/* USER CODE END SDMMC1_Init 2 */
}
/**
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
htim3.Init.Prescaler = 119;
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
htim3.Init.Period = 65535;
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
{
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
}
/**
* @brief UART4 Initialization Function
* @param None
* @retval None
*/
static void MX_UART4_Init(void)
{
/* USER CODE BEGIN UART4_Init 0 */
/* USER CODE END UART4_Init 0 */
/* USER CODE BEGIN UART4_Init 1 */
/* USER CODE END UART4_Init 1 */
huart4.Instance = UART4;
huart4.Init.BaudRate = 9600;
huart4.Init.WordLength = UART_WORDLENGTH_8B;
huart4.Init.StopBits = UART_STOPBITS_1;
huart4.Init.Parity = UART_PARITY_NONE;
huart4.Init.Mode = UART_MODE_TX_RX;
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1;
huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart4) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN UART4_Init 2 */
/* USER CODE END UART4_Init 2 */
}
/**
* @brief UART7 Initialization Function
* @param None
* @retval None
*/
static void MX_UART7_Init(void)
{
/* USER CODE BEGIN UART7_Init 0 */
/* USER CODE END UART7_Init 0 */
/* USER CODE BEGIN UART7_Init 1 */
/* USER CODE END UART7_Init 1 */
huart7.Instance = UART7;
huart7.Init.BaudRate = 115200;
huart7.Init.WordLength = UART_WORDLENGTH_8B;
huart7.Init.StopBits = UART_STOPBITS_1;
huart7.Init.Parity = UART_PARITY_NONE;
huart7.Init.Mode = UART_MODE_TX_RX;
huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart7.Init.OverSampling = UART_OVERSAMPLING_16;
huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart7.Init.ClockPrescaler = UART_PRESCALER_DIV1;
huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart7) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart7, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart7, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&huart7) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN UART7_Init 2 */
/* USER CODE END UART7_Init 2 */
}
/**
* @brief UART8 Initialization Function
* @param None
* @retval None
*/
static void MX_UART8_Init(void)
{
/* USER CODE BEGIN UART8_Init 0 */
/* USER CODE END UART8_Init 0 */
/* USER CODE BEGIN UART8_Init 1 */
/* USER CODE END UART8_Init 1 */
huart8.Instance = UART8;
huart8.Init.BaudRate = 115200;
huart8.Init.WordLength = UART_WORDLENGTH_8B;
huart8.Init.StopBits = UART_STOPBITS_1;
huart8.Init.Parity = UART_PARITY_NONE;
huart8.Init.Mode = UART_MODE_TX_RX;
huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart8.Init.OverSampling = UART_OVERSAMPLING_16;
huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1;
huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN UART8_Init 2 */
/* USER CODE END UART8_Init 2 */
}
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
/* DMA interrupt init */
/* DMA1_Stream0_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
}
/**
* Enable MDMA controller clock
* Configure MDMA for global transfers
* hmdma_mdma_channel0_sdmmc1_end_data_0
*/
static void MX_MDMA_Init(void)
{
/* MDMA controller clock enable */
__HAL_RCC_MDMA_CLK_ENABLE();
/* Local variables */
/* Configure MDMA channel MDMA_Channel0 */
/* Configure MDMA request hmdma_mdma_channel0_sdmmc1_end_data_0 on MDMA_Channel0 */
hmdma_mdma_channel0_sdmmc1_end_data_0.Instance = MDMA_Channel0;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Request = MDMA_REQUEST_SDMMC1_END_DATA;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.TransferTriggerMode = MDMA_BUFFER_TRANSFER;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Priority = MDMA_PRIORITY_LOW;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.Endianness = MDMA_LITTLE_ENDIANNESS_PRESERVE;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceInc = MDMA_SRC_INC_BYTE;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestinationInc = MDMA_DEST_INC_BYTE;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceDataSize = MDMA_SRC_DATASIZE_BYTE;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestDataSize = MDMA_DEST_DATASIZE_BYTE;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DataAlignment = MDMA_DATAALIGN_PACKENABLE;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.BufferTransferLength = 1;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceBurst = MDMA_SOURCE_BURST_SINGLE;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestBurst = MDMA_DEST_BURST_SINGLE;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.SourceBlockAddressOffset = 0;
hmdma_mdma_channel0_sdmmc1_end_data_0.Init.DestBlockAddressOffset = 0;
if (HAL_MDMA_Init(&hmdma_mdma_channel0_sdmmc1_end_data_0) != HAL_OK)
{
Error_Handler();
}
/* Configure post request address and data masks */
if (HAL_MDMA_ConfigPostRequestMask(&hmdma_mdma_channel0_sdmmc1_end_data_0, 0, 0) != HAL_OK)
{
Error_Handler();
}
/* MDMA interrupt initialization */
/* MDMA_IRQn interrupt configuration */
HAL_NVIC_SetPriority(MDMA_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(MDMA_IRQn);
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(mLED_GPIO_Port, mLED_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, SD_LED_Pin|VIN_ON_Pin|PICO_EN_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin : mLED_Pin */
GPIO_InitStruct.Pin = mLED_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(mLED_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : SD_LED_Pin VIN_ON_Pin PICO_EN_Pin */
GPIO_InitStruct.Pin = SD_LED_Pin|VIN_ON_Pin|PICO_EN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pin : sdDetect_Pin */
GPIO_InitStruct.Pin = sdDetect_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(sdDetect_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : VIN_IG_Pin VIN_1_4_Pin */
GPIO_InitStruct.Pin = VIN_IG_Pin|VIN_1_4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
/* USER CODE BEGIN 4 */
void lwftp_init(void) {
IP4_ADDR(&s.cli_ip, CLI_IP[0], CLI_IP[1], CLI_IP[2], CLI_IP[3]);
IP4_ADDR(&s.svr_ip, SVR_IP[0], SVR_IP[1], SVR_IP[2], SVR_IP[3]);
s.svr_port = SVR_PORT;
s.user = USER;
s.pass = PASS;
printf("\n>> lwftp: cli ip: %d.%d.%d.%d\r\n", CLI_IP[0], CLI_IP[1], CLI_IP[2], CLI_IP[3]);
printf(">> lwftp: svr ip: %d.%d.%d.%d\r\n", SVR_IP[0], SVR_IP[1], SVR_IP[2], SVR_IP[3]);
printf(">> lwftp: svr port: %d\r\n", s.svr_port);
printf(">> lwftp: username: %s\r\n", s.user);
printf(">> lwftp: password: %s\r\n\n", s.pass);
#if FTPSemaphore
sys_sem_new(&ftpsem, 0); // the semaphore would prevent simultaneous access to lwftp_send
#endif
/* Thread for Control connection*/
sys_thread_new("lwftp_ctrl_thread", lwftp_ctrl_thread, (void*) &s,
DEFAULT_THREAD_STACKSIZE, osPriorityNormal);
/* Thread for Data connection*/
sys_thread_new("lwftp_data_thread", lwftp_data_thread, (void*) &s,
DEFAULT_THREAD_STACKSIZE, osPriorityNormal);
}
/* USER CODE END 4 */
/* USER CODE BEGIN Header_StartDefaultTask */
/**
* @brief Function implementing the defaultTask thread.
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_StartDefaultTask */
void StartDefaultTask(void const * argument)
{
/* init code for LWIP */
MX_LWIP_Init();
/* USER CODE BEGIN 5 */
printf("[INFO] Remaining stack size of task: %ld\r\n",
uxTaskGetStackHighWaterMark(NULL));
lwftp_init();
osDelay(5000); // run code aft 5s
err_t err;
// err = lwftp_list(&s);
// err = lwftp_store(&s, "foobar.txt", "TESTTESTTESTTESTTESTTESTTEST\r\n");
err = lwftp_retrieve(&s, "ftp_test_1.txt");
printf("%d\r\n",err);
/* Infinite loop */
for (;;) {
osDelay(1);
}
/* USER CODE END 5 */
}
/* USER CODE BEGIN Header_StartDebugTask */
/**
* @brief Function implementing the debugTask thread.
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_StartDebugTask */
void StartDebugTask(void const * argument)
{
/* USER CODE BEGIN StartDebugTask */
/* Infinite loop */
for(;;)
{
osDelay(1);
}
/* USER CODE END StartDebugTask */
}
/* MPU Configuration */
void MPU_Config(void)
{
MPU_Region_InitTypeDef MPU_InitStruct = {0};
/* Disables the MPU */
HAL_MPU_Disable();
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.BaseAddress = 0x0;
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
MPU_InitStruct.SubRegionDisable = 0x87;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
MPU_InitStruct.BaseAddress = 0x30000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
MPU_InitStruct.SubRegionDisable = 0x0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Number = MPU_REGION_NUMBER2;
MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Number = MPU_REGION_NUMBER3;
MPU_InitStruct.BaseAddress = 0x24000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Enables the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
/**
* @brief Period elapsed callback in non blocking mode
* @note This function is called when TIM6 interrupt took place, inside
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM6) {
HAL_IncTick();
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1) {
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

645
Core/Src/stm32h7xx_hal_msp.c
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@ -1,645 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_hal_msp.c
* @brief This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern DMA_HandleTypeDef hdma_uart8_rx;
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0;
/**
* @brief FDCAN MSP Initialization
* This function configures the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hfdcan->Instance==FDCAN1)
{
/* USER CODE BEGIN FDCAN1_MspInit 0 */
/* USER CODE END FDCAN1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
HAL_RCC_FDCAN_CLK_ENABLED++;
if(HAL_RCC_FDCAN_CLK_ENABLED==1){
__HAL_RCC_FDCAN_CLK_ENABLE();
}
__HAL_RCC_GPIOB_CLK_ENABLE();
/**FDCAN1 GPIO Configuration
PB9 ------> FDCAN1_TX
PB8 ------> FDCAN1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* FDCAN1 interrupt Init */
HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
/* USER CODE BEGIN FDCAN1_MspInit 1 */
/* USER CODE END FDCAN1_MspInit 1 */
}
else if(hfdcan->Instance==FDCAN2)
{
/* USER CODE BEGIN FDCAN2_MspInit 0 */
/* USER CODE END FDCAN2_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
HAL_RCC_FDCAN_CLK_ENABLED++;
if(HAL_RCC_FDCAN_CLK_ENABLED==1){
__HAL_RCC_FDCAN_CLK_ENABLE();
}
__HAL_RCC_GPIOB_CLK_ENABLE();
/**FDCAN2 GPIO Configuration
PB6 ------> FDCAN2_TX
PB5 ------> FDCAN2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* FDCAN2 interrupt Init */
HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
/* USER CODE BEGIN FDCAN2_MspInit 1 */
/* USER CODE END FDCAN2_MspInit 1 */
}
else if(hfdcan->Instance==FDCAN3)
{
/* USER CODE BEGIN FDCAN3_MspInit 0 */
/* USER CODE END FDCAN3_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
HAL_RCC_FDCAN_CLK_ENABLED++;
if(HAL_RCC_FDCAN_CLK_ENABLED==1){
__HAL_RCC_FDCAN_CLK_ENABLE();
}
__HAL_RCC_GPIOD_CLK_ENABLE();
/**FDCAN3 GPIO Configuration
PD13 ------> FDCAN3_TX
PD12 ------> FDCAN3_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF5_FDCAN3;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* FDCAN3 interrupt Init */
HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn);
/* USER CODE BEGIN FDCAN3_MspInit 1 */
/* USER CODE END FDCAN3_MspInit 1 */
}
}
/**
* @brief FDCAN MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
{
if(hfdcan->Instance==FDCAN1)
{
/* USER CODE BEGIN FDCAN1_MspDeInit 0 */
/* USER CODE END FDCAN1_MspDeInit 0 */
/* Peripheral clock disable */
HAL_RCC_FDCAN_CLK_ENABLED--;
if(HAL_RCC_FDCAN_CLK_ENABLED==0){
__HAL_RCC_FDCAN_CLK_DISABLE();
}
/**FDCAN1 GPIO Configuration
PB9 ------> FDCAN1_TX
PB8 ------> FDCAN1_RX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9|GPIO_PIN_8);
/* FDCAN1 interrupt DeInit */
HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn);
/* USER CODE BEGIN FDCAN1_MspDeInit 1 */
/* USER CODE END FDCAN1_MspDeInit 1 */
}
else if(hfdcan->Instance==FDCAN2)
{
/* USER CODE BEGIN FDCAN2_MspDeInit 0 */
/* USER CODE END FDCAN2_MspDeInit 0 */
/* Peripheral clock disable */
HAL_RCC_FDCAN_CLK_ENABLED--;
if(HAL_RCC_FDCAN_CLK_ENABLED==0){
__HAL_RCC_FDCAN_CLK_DISABLE();
}
/**FDCAN2 GPIO Configuration
PB6 ------> FDCAN2_TX
PB5 ------> FDCAN2_RX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_5);
/* FDCAN2 interrupt DeInit */
HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn);
/* USER CODE BEGIN FDCAN2_MspDeInit 1 */
/* USER CODE END FDCAN2_MspDeInit 1 */
}
else if(hfdcan->Instance==FDCAN3)
{
/* USER CODE BEGIN FDCAN3_MspDeInit 0 */
/* USER CODE END FDCAN3_MspDeInit 0 */
/* Peripheral clock disable */
HAL_RCC_FDCAN_CLK_ENABLED--;
if(HAL_RCC_FDCAN_CLK_ENABLED==0){
__HAL_RCC_FDCAN_CLK_DISABLE();
}
/**FDCAN3 GPIO Configuration
PD13 ------> FDCAN3_TX
PD12 ------> FDCAN3_RX
*/
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_13|GPIO_PIN_12);
/* FDCAN3 interrupt DeInit */
HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn);
/* USER CODE BEGIN FDCAN3_MspDeInit 1 */
/* USER CODE END FDCAN3_MspDeInit 1 */
}
}
/**
* @brief SD MSP Initialization
* This function configures the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hsd->Instance==SDMMC1)
{
/* USER CODE BEGIN SDMMC1_MspInit 0 */
/* USER CODE END SDMMC1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC;
PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_SDMMC1_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
/**SDMMC1 GPIO Configuration
PD2 ------> SDMMC1_CMD
PC11 ------> SDMMC1_D3
PC10 ------> SDMMC1_D2
PC12 ------> SDMMC1_CK
PC9 ------> SDMMC1_D1
PC8 ------> SDMMC1_D0
*/
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_9
|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* SDMMC1 interrupt Init */
HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
/* USER CODE BEGIN SDMMC1_MspInit 1 */
/* USER CODE END SDMMC1_MspInit 1 */
}
}
/**
* @brief SD MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
{
if(hsd->Instance==SDMMC1)
{
/* USER CODE BEGIN SDMMC1_MspDeInit 0 */
/* USER CODE END SDMMC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SDMMC1_CLK_DISABLE();
/**SDMMC1 GPIO Configuration
PD2 ------> SDMMC1_CMD
PC11 ------> SDMMC1_D3
PC10 ------> SDMMC1_D2
PC12 ------> SDMMC1_CK
PC9 ------> SDMMC1_D1
PC8 ------> SDMMC1_D0
*/
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_9
|GPIO_PIN_8);
/* SDMMC1 interrupt DeInit */
HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
/* USER CODE BEGIN SDMMC1_MspDeInit 1 */
/* USER CODE END SDMMC1_MspDeInit 1 */
}
}
/**
* @brief TIM_Base MSP Initialization
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
if(htim_base->Instance==TIM3)
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
/**
* @brief TIM_Base MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
{
if(htim_base->Instance==TIM3)
{
/* USER CODE BEGIN TIM3_MspDeInit 0 */
/* USER CODE END TIM3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_TIM3_CLK_DISABLE();
/* USER CODE BEGIN TIM3_MspDeInit 1 */
/* USER CODE END TIM3_MspDeInit 1 */
}
}
/**
* @brief UART MSP Initialization
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(huart->Instance==UART4)
{
/* USER CODE BEGIN UART4_MspInit 0 */
/* USER CODE END UART4_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4;
PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_UART4_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**UART4 GPIO Configuration
PD0 ------> UART4_RX
PD1 ------> UART4_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* USER CODE BEGIN UART4_MspInit 1 */
/* USER CODE END UART4_MspInit 1 */
}
else if(huart->Instance==UART7)
{
/* USER CODE BEGIN UART7_MspInit 0 */
/* USER CODE END UART7_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART7;
PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_UART7_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
/**UART7 GPIO Configuration
PE7 ------> UART7_RX
PE8 ------> UART7_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF7_UART7;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/* USER CODE BEGIN UART7_MspInit 1 */
/* USER CODE END UART7_MspInit 1 */
}
else if(huart->Instance==UART8)
{
/* USER CODE BEGIN UART8_MspInit 0 */
/* USER CODE END UART8_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8;
PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_UART8_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
/**UART8 GPIO Configuration
PE1 ------> UART8_TX
PE0 ------> UART8_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF8_UART8;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/* UART8 DMA Init */
/* UART8_RX Init */
hdma_uart8_rx.Instance = DMA1_Stream0;
hdma_uart8_rx.Init.Request = DMA_REQUEST_UART8_RX;
hdma_uart8_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_uart8_rx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_uart8_rx.Init.MemInc = DMA_MINC_ENABLE;
hdma_uart8_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_uart8_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_uart8_rx.Init.Mode = DMA_CIRCULAR;
hdma_uart8_rx.Init.Priority = DMA_PRIORITY_LOW;
hdma_uart8_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_uart8_rx) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(huart,hdmarx,hdma_uart8_rx);
/* USER CODE BEGIN UART8_MspInit 1 */
/* USER CODE END UART8_MspInit 1 */
}
}
/**
* @brief UART MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
if(huart->Instance==UART4)
{
/* USER CODE BEGIN UART4_MspDeInit 0 */
/* USER CODE END UART4_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_UART4_CLK_DISABLE();
/**UART4 GPIO Configuration
PD0 ------> UART4_RX
PD1 ------> UART4_TX
*/
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1);
/* USER CODE BEGIN UART4_MspDeInit 1 */
/* USER CODE END UART4_MspDeInit 1 */
}
else if(huart->Instance==UART7)
{
/* USER CODE BEGIN UART7_MspDeInit 0 */
/* USER CODE END UART7_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_UART7_CLK_DISABLE();
/**UART7 GPIO Configuration
PE7 ------> UART7_RX
PE8 ------> UART7_TX
*/
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8);
/* USER CODE BEGIN UART7_MspDeInit 1 */
/* USER CODE END UART7_MspDeInit 1 */
}
else if(huart->Instance==UART8)
{
/* USER CODE BEGIN UART8_MspDeInit 0 */
/* USER CODE END UART8_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_UART8_CLK_DISABLE();
/**UART8 GPIO Configuration
PE1 ------> UART8_TX
PE0 ------> UART8_RX
*/
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0);
/* UART8 DMA DeInit */
HAL_DMA_DeInit(huart->hdmarx);
/* USER CODE BEGIN UART8_MspDeInit 1 */
/* USER CODE END UART8_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

131
Core/Src/stm32h7xx_hal_timebase_tim.c
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@ -1,131 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_hal_timebase_tim.c
* @brief HAL time base based on the hardware TIM.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
#include "stm32h7xx_hal_tim.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
TIM_HandleTypeDef htim6;
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @brief This function configures the TIM6 as a time base source.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock, uwAPB1Prescaler;
uint32_t uwPrescalerValue;
uint32_t pFLatency;
/*Configure the TIM6 IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
uwTickPrio = TickPriority;
}
else
{
return HAL_ERROR;
}
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
/* Get APB1 prescaler */
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
/* Compute TIM6 clock */
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
{
uwTimclock = HAL_RCC_GetPCLK1Freq();
}
else
{
uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
}
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
/* Initialize TIM6 */
htim6.Instance = TIM6;
/* Initialize TIMx peripheral as follow:
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim6.Init.Period = (1000000U / 1000U) - 1U;
htim6.Init.Prescaler = uwPrescalerValue;
htim6.Init.ClockDivision = 0;
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim6);
}
/* Return function status */
return HAL_ERROR;
}
/**
* @brief Suspend Tick increment.
* @note Disable the tick increment by disabling TIM6 update interrupt.
* @param None
* @retval None
*/
void HAL_SuspendTick(void)
{
/* Disable TIM6 update Interrupt */
__HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE);
}
/**
* @brief Resume Tick increment.
* @note Enable the tick increment by Enabling TIM6 update interrupt.
* @param None
* @retval None
*/
void HAL_ResumeTick(void)
{
/* Enable TIM6 Update interrupt */
__HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE);
}

283
Core/Src/stm32h7xx_it.c
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@ -1,283 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32h7xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern ETH_HandleTypeDef heth;
extern FDCAN_HandleTypeDef hfdcan1;
extern FDCAN_HandleTypeDef hfdcan2;
extern FDCAN_HandleTypeDef hfdcan3;
extern MDMA_HandleTypeDef hmdma_mdma_channel0_sdmmc1_end_data_0;
extern SD_HandleTypeDef hsd1;
extern DMA_HandleTypeDef hdma_uart8_rx;
extern TIM_HandleTypeDef htim6;
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/******************************************************************************/
/* STM32H7xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32h7xx.s). */
/******************************************************************************/
/**
* @brief This function handles DMA1 stream0 global interrupt.
*/
void DMA1_Stream0_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
/* USER CODE END DMA1_Stream0_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_uart8_rx);
/* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
/* USER CODE END DMA1_Stream0_IRQn 1 */
}
/**
* @brief This function handles FDCAN1 interrupt 0.
*/
void FDCAN1_IT0_IRQHandler(void)
{
/* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */
/* USER CODE END FDCAN1_IT0_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan1);
/* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
/* USER CODE END FDCAN1_IT0_IRQn 1 */
}
/**
* @brief This function handles FDCAN2 interrupt 0.
*/
void FDCAN2_IT0_IRQHandler(void)
{
/* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */
/* USER CODE END FDCAN2_IT0_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan2);
/* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */
/* USER CODE END FDCAN2_IT0_IRQn 1 */
}
/**
* @brief This function handles SDMMC1 global interrupt.
*/
void SDMMC1_IRQHandler(void)
{
/* USER CODE BEGIN SDMMC1_IRQn 0 */
/* USER CODE END SDMMC1_IRQn 0 */
HAL_SD_IRQHandler(&hsd1);
/* USER CODE BEGIN SDMMC1_IRQn 1 */
/* USER CODE END SDMMC1_IRQn 1 */
}
/**
* @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_TIM_IRQHandler(&htim6);
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
/* USER CODE END TIM6_DAC_IRQn 1 */
}
/**
* @brief This function handles Ethernet global interrupt.
*/
void ETH_IRQHandler(void)
{
/* USER CODE BEGIN ETH_IRQn 0 */
/* USER CODE END ETH_IRQn 0 */
HAL_ETH_IRQHandler(&heth);
/* USER CODE BEGIN ETH_IRQn 1 */
/* USER CODE END ETH_IRQn 1 */
}
/**
* @brief This function handles MDMA global interrupt.
*/
void MDMA_IRQHandler(void)
{
/* USER CODE BEGIN MDMA_IRQn 0 */
/* USER CODE END MDMA_IRQn 0 */
HAL_MDMA_IRQHandler(&hmdma_mdma_channel0_sdmmc1_end_data_0);
/* USER CODE BEGIN MDMA_IRQn 1 */
/* USER CODE END MDMA_IRQn 1 */
}
/**
* @brief This function handles FDCAN3 interrupt 0.
*/
void FDCAN3_IT0_IRQHandler(void)
{
/* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */
/* USER CODE END FDCAN3_IT0_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan3);
/* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */
/* USER CODE END FDCAN3_IT0_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

176
Core/Src/syscalls.c
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@ -1,176 +0,0 @@
/**
******************************************************************************
* @file syscalls.c
* @author Auto-generated by STM32CubeIDE
* @brief STM32CubeIDE Minimal System calls file
*
* For more information about which c-functions
* need which of these lowlevel functions
* please consult the Newlib libc-manual
******************************************************************************
* @attention
*
* Copyright (c) 2020-2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes */
#include <sys/stat.h>
#include <stdlib.h>
#include <errno.h>
#include <stdio.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <sys/times.h>
/* Variables */
extern int __io_putchar(int ch) __attribute__((weak));
extern int __io_getchar(void) __attribute__((weak));
char *__env[1] = { 0 };
char **environ = __env;
/* Functions */
void initialise_monitor_handles()
{
}
int _getpid(void)
{
return 1;
}
int _kill(int pid, int sig)
{
(void)pid;
(void)sig;
errno = EINVAL;
return -1;
}
void _exit (int status)
{
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
*ptr++ = __io_getchar();
}
return len;
}
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
__io_putchar(*ptr++);
}
return len;
}
int _close(int file)
{
(void)file;
return -1;
}
int _fstat(int file, struct stat *st)
{
(void)file;
st->st_mode = S_IFCHR;
return 0;
}
int _isatty(int file)
{
(void)file;
return 1;
}
int _lseek(int file, int ptr, int dir)
{
(void)file;
(void)ptr;
(void)dir;
return 0;
}
int _open(char *path, int flags, ...)
{
(void)path;
(void)flags;
/* Pretend like we always fail */
return -1;
}
int _wait(int *status)
{
(void)status;
errno = ECHILD;
return -1;
}
int _unlink(char *name)
{
(void)name;
errno = ENOENT;
return -1;
}
int _times(struct tms *buf)
{
(void)buf;
return -1;
}
int _stat(char *file, struct stat *st)
{
(void)file;
st->st_mode = S_IFCHR;
return 0;
}
int _link(char *old, char *new)
{
(void)old;
(void)new;
errno = EMLINK;
return -1;
}
int _fork(void)
{
errno = EAGAIN;
return -1;
}
int _execve(char *name, char **argv, char **env)
{
(void)name;
(void)argv;
(void)env;
errno = ENOMEM;
return -1;
}

79
Core/Src/sysmem.c
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@ -1,79 +0,0 @@
/**
******************************************************************************
* @file sysmem.c
* @author Generated by STM32CubeIDE
* @brief STM32CubeIDE System Memory calls file
*
* For more information about which C functions
* need which of these lowlevel functions
* please consult the newlib libc manual
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes */
#include <errno.h>
#include <stdint.h>
/**
* Pointer to the current high watermark of the heap usage
*/
static uint8_t *__sbrk_heap_end = NULL;
/**
* @brief _sbrk() allocates memory to the newlib heap and is used by malloc
* and others from the C library
*
* @verbatim
* ############################################################################
* # .data # .bss # newlib heap # MSP stack #
* # # # # Reserved by _Min_Stack_Size #
* ############################################################################
* ^-- RAM start ^-- _end _estack, RAM end --^
* @endverbatim
*
* This implementation starts allocating at the '_end' linker symbol
* The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
* The implementation considers '_estack' linker symbol to be RAM end
* NOTE: If the MSP stack, at any point during execution, grows larger than the
* reserved size, please increase the '_Min_Stack_Size'.
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
const uint8_t *max_heap = (uint8_t *)stack_limit;
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
{
__sbrk_heap_end = &_end;
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
{
errno = ENOMEM;
return (void *)-1;
}
prev_heap_end = __sbrk_heap_end;
__sbrk_heap_end += incr;
return (void *)prev_heap_end;
}

450
Core/Src/system_stm32h7xx.c
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/**
******************************************************************************
* @file system_stm32h7xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32h7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock, it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32h7xx_system
* @{
*/
/** @addtogroup STM32H7xx_System_Private_Includes
* @{
*/
#include "stm32h7xx.h"
#include <math.h>
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (CSI_VALUE)
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
/* #define DATA_IN_D2_SRAM */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
#if defined(DUAL_CORE) && defined(CORE_CM4)
/*!< Uncomment the following line if you need to relocate your vector Table
in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#endif /* VECT_TAB_SRAM */
#else
/*!< Uncomment the following line if you need to relocate your vector Table
in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#endif /* VECT_TAB_SRAM */
#endif /* DUAL_CORE && CORE_CM4 */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 64000000;
uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting and vector table location
* configuration.
* @param None
* @retval None
*/
void SystemInit (void)
{
#if defined (DATA_IN_D2_SRAM)
__IO uint32_t tmpreg;
#endif /* DATA_IN_D2_SRAM */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Increasing the CPU frequency */
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Set HSION bit */
RCC->CR |= RCC_CR_HSION;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
#if defined(D3_SRAM_BASE)
/* Reset D1CFGR register */
RCC->D1CFGR = 0x00000000;
/* Reset D2CFGR register */
RCC->D2CFGR = 0x00000000;
/* Reset D3CFGR register */
RCC->D3CFGR = 0x00000000;
#else
/* Reset CDCFGR1 register */
RCC->CDCFGR1 = 0x00000000;
/* Reset CDCFGR2 register */
RCC->CDCFGR2 = 0x00000000;
/* Reset SRDCFGR register */
RCC->SRDCFGR = 0x00000000;
#endif
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x02020200;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x01FF0000;
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x01010280;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x01010280;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x01010280;
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */
RCC->CIER = 0x00000000;
#if (STM32H7_DEV_ID == 0x450UL)
/* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
#endif /* STM32H7_DEV_ID */
#if defined(DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
#else
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#endif /* RCC_AHB2ENR_D2SRAM3EN */
tmpreg = RCC->AHB2ENR;
(void) tmpreg;
#endif /* DATA_IN_D2_SRAM */
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */
#else
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
*/
FMC_Bank1_R->BTCR[0] = 0x000030D2;
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */
#endif /*DUAL_CORE && CORE_CM4*/
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock , it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
*
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 64 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
uint32_t common_system_clock;
float_t fracn1, pllvco;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
common_system_clock = CSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
common_system_clock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
if (pllm != 0U)
{
switch (pllsource)
{
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
default:
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
}
else
{
common_system_clock = 0U;
}
break;
default:
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
}
/* Compute SystemClock frequency --------------------------------------------------*/
#if defined (RCC_D1CFGR_D1CPRE)
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

756
Core/Startup/startup_stm32h723vghx.s
View File

@ -1,756 +0,0 @@
/**
******************************************************************************
* @file startup_stm32h723xx.s
* @author MCD Application Team
* @brief STM32H723xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word 0 /* Reserved */
.word OCTOSPI1_IRQHandler /* OCTOSPI1 */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word 0 /* Reserved */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word 0 /* Reserved */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word 0 /* Reserved */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word 0 /* Reserved */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word 0 /* Reserved */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
.word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
.word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word FMAC_IRQHandler /* FMAC Interrupt */
.word CORDIC_IRQHandler /* CORDIC Interrupt */
.word UART9_IRQHandler /* UART9 Interrupt */
.word USART10_IRQHandler /* UART10 Interrupt */
.word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */
.word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */
.word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */
.word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */
.word TIM23_IRQHandler /* TIM23 global interrupt */
.word TIM24_IRQHandler /* TIM24 global interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_PSSI_IRQHandler
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak OCTOSPI1_IRQHandler
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak DTS_IRQHandler
.thumb_set DTS_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
.weak OCTOSPI2_IRQHandler
.thumb_set OCTOSPI2_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak UART9_IRQHandler
.thumb_set UART9_IRQHandler,Default_Handler
.weak USART10_IRQHandler
.thumb_set USART10_IRQHandler,Default_Handler
.weak I2C5_EV_IRQHandler
.thumb_set I2C5_EV_IRQHandler,Default_Handler
.weak I2C5_ER_IRQHandler
.thumb_set I2C5_ER_IRQHandler,Default_Handler
.weak FDCAN3_IT0_IRQHandler
.thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
.weak FDCAN3_IT1_IRQHandler
.thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
.weak TIM23_IRQHandler
.thumb_set TIM23_IRQHandler,Default_Handler
.weak TIM24_IRQHandler
.thumb_set TIM24_IRQHandler,Default_Handler

3
Debug/Core/Src/freertos.cyclo
View File

@ -1,3 +0,0 @@
../Core/Src/freertos.c:65:13:vApplicationStackOverflowHook 1
../Core/Src/freertos.c:77:6:vApplicationGetIdleTaskMemory 1
../Core/Src/freertos.c:90:6:vApplicationGetTimerTaskMemory 1

98
Debug/Core/Src/freertos.d
View File

@ -1,98 +0,0 @@
Core/Src/freertos.o: ../Core/Src/freertos.c \
../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
../Core/Inc/FreeRTOSConfig.h \
../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
../Core/Inc/stm32h7xx_hal_conf.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
../Drivers/CMSIS/Include/core_cm7.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv7.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
../Core/Inc/FreeRTOSConfig.h:
../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
../Core/Inc/main.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
../Core/Inc/stm32h7xx_hal_conf.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
../Drivers/CMSIS/Include/core_cm7.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv7.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:

BIN
Debug/Core/Src/freertos.o
View File

Binary file not shown.

3
Debug/Core/Src/freertos.su
View File

@ -1,3 +0,0 @@
../Core/Src/freertos.c:65:13:vApplicationStackOverflowHook 16 static
../Core/Src/freertos.c:77:6:vApplicationGetIdleTaskMemory 24 static
../Core/Src/freertos.c:90:6:vApplicationGetTimerTaskMemory 24 static

21
Debug/Core/Src/main.cyclo
View File

@ -1,21 +0,0 @@
../Drivers/CMSIS/Include/core_cm7.h:2660:26:ITM_SendChar 4
../Core/Src/main.c:107:5:_write 2
../Core/Src/main.c:118:5:main 5
../Core/Src/main.c:221:6:SystemClock_Config 4
../Core/Src/main.c:280:13:MX_FDCAN1_Init 2
../Core/Src/main.c:333:13:MX_FDCAN2_Init 2
../Core/Src/main.c:386:13:MX_FDCAN3_Init 2
../Core/Src/main.c:439:13:MX_SDMMC1_SD_Init 1
../Core/Src/main.c:466:13:MX_TIM3_Init 4
../Core/Src/main.c:511:13:MX_UART4_Init 5
../Core/Src/main.c:559:13:MX_UART7_Init 5
../Core/Src/main.c:607:13:MX_UART8_Init 5
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../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:

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Debug/Core/Src/stm32h7xx_hal_msp.su
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@ -1,9 +0,0 @@
../Core/Src/stm32h7xx_hal_msp.c:65:6:HAL_MspInit 16 static
../Core/Src/stm32h7xx_hal_msp.c:90:6:HAL_FDCAN_MspInit 248 static
../Core/Src/stm32h7xx_hal_msp.c:223:6:HAL_FDCAN_MspDeInit 16 static
../Core/Src/stm32h7xx_hal_msp.c:303:6:HAL_SD_MspInit 240 static
../Core/Src/stm32h7xx_hal_msp.c:366:6:HAL_SD_MspDeInit 16 static
../Core/Src/stm32h7xx_hal_msp.c:404:6:HAL_TIM_Base_MspInit 24 static
../Core/Src/stm32h7xx_hal_msp.c:426:6:HAL_TIM_Base_MspDeInit 16 static
../Core/Src/stm32h7xx_hal_msp.c:448:6:HAL_UART_MspInit 248 static
../Core/Src/stm32h7xx_hal_msp.c:582:6:HAL_UART_MspDeInit 16 static

3
Debug/Core/Src/stm32h7xx_hal_timebase_tim.cyclo
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@ -1,3 +0,0 @@
../Core/Src/stm32h7xx_hal_timebase_tim.c:41:19:HAL_InitTick 4
../Core/Src/stm32h7xx_hal_timebase_tim.c:114:6:HAL_SuspendTick 1
../Core/Src/stm32h7xx_hal_timebase_tim.c:126:6:HAL_ResumeTick 1

80
Debug/Core/Src/stm32h7xx_hal_timebase_tim.d
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@ -1,80 +0,0 @@
Core/Src/stm32h7xx_hal_timebase_tim.o: \
../Core/Src/stm32h7xx_hal_timebase_tim.c \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
../Core/Inc/stm32h7xx_hal_conf.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
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../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
../Drivers/CMSIS/Include/core_cm7.h \
../Drivers/CMSIS/Include/cmsis_version.h \
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../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
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../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv7.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:

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Debug/Core/Src/stm32h7xx_hal_timebase_tim.su
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@ -1,3 +0,0 @@
../Core/Src/stm32h7xx_hal_timebase_tim.c:41:19:HAL_InitTick 72 static
../Core/Src/stm32h7xx_hal_timebase_tim.c:114:6:HAL_SuspendTick 4 static
../Core/Src/stm32h7xx_hal_timebase_tim.c:126:6:HAL_ResumeTick 4 static

14
Debug/Core/Src/stm32h7xx_it.cyclo
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@ -1,14 +0,0 @@
../Core/Src/stm32h7xx_it.c:77:6:NMI_Handler 1
../Core/Src/stm32h7xx_it.c:92:6:HardFault_Handler 1
../Core/Src/stm32h7xx_it.c:107:6:MemManage_Handler 1
../Core/Src/stm32h7xx_it.c:122:6:BusFault_Handler 1
../Core/Src/stm32h7xx_it.c:137:6:UsageFault_Handler 1
../Core/Src/stm32h7xx_it.c:152:6:DebugMon_Handler 1
../Core/Src/stm32h7xx_it.c:172:6:DMA1_Stream0_IRQHandler 1
../Core/Src/stm32h7xx_it.c:186:6:FDCAN1_IT0_IRQHandler 1
../Core/Src/stm32h7xx_it.c:200:6:FDCAN2_IT0_IRQHandler 1
../Core/Src/stm32h7xx_it.c:214:6:SDMMC1_IRQHandler 1
../Core/Src/stm32h7xx_it.c:228:6:TIM6_DAC_IRQHandler 1
../Core/Src/stm32h7xx_it.c:242:6:ETH_IRQHandler 1
../Core/Src/stm32h7xx_it.c:256:6:MDMA_IRQHandler 1
../Core/Src/stm32h7xx_it.c:270:6:FDCAN3_IT0_IRQHandler 1

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@ -1,82 +0,0 @@
Core/Src/stm32h7xx_it.o: ../Core/Src/stm32h7xx_it.c ../Core/Inc/main.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
../Core/Inc/stm32h7xx_hal_conf.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
../Drivers/CMSIS/Include/core_cm7.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv7.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
../Core/Inc/stm32h7xx_it.h
../Core/Inc/main.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
../Core/Inc/stm32h7xx_hal_conf.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
../Drivers/CMSIS/Include/core_cm7.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv7.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
../Core/Inc/stm32h7xx_it.h:

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Debug/Core/Src/stm32h7xx_it.su
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@ -1,14 +0,0 @@
../Core/Src/stm32h7xx_it.c:77:6:NMI_Handler 4 static
../Core/Src/stm32h7xx_it.c:92:6:HardFault_Handler 4 static
../Core/Src/stm32h7xx_it.c:107:6:MemManage_Handler 4 static
../Core/Src/stm32h7xx_it.c:122:6:BusFault_Handler 4 static
../Core/Src/stm32h7xx_it.c:137:6:UsageFault_Handler 4 static
../Core/Src/stm32h7xx_it.c:152:6:DebugMon_Handler 4 static
../Core/Src/stm32h7xx_it.c:172:6:DMA1_Stream0_IRQHandler 8 static
../Core/Src/stm32h7xx_it.c:186:6:FDCAN1_IT0_IRQHandler 8 static
../Core/Src/stm32h7xx_it.c:200:6:FDCAN2_IT0_IRQHandler 8 static
../Core/Src/stm32h7xx_it.c:214:6:SDMMC1_IRQHandler 8 static
../Core/Src/stm32h7xx_it.c:228:6:TIM6_DAC_IRQHandler 8 static
../Core/Src/stm32h7xx_it.c:242:6:ETH_IRQHandler 8 static
../Core/Src/stm32h7xx_it.c:256:6:MDMA_IRQHandler 8 static
../Core/Src/stm32h7xx_it.c:270:6:FDCAN3_IT0_IRQHandler 8 static

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@ -1,48 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (11.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../Core/Src/freertos.c \
../Core/Src/main.c \
../Core/Src/stm32h7xx_hal_msp.c \
../Core/Src/stm32h7xx_hal_timebase_tim.c \
../Core/Src/stm32h7xx_it.c \
../Core/Src/syscalls.c \
../Core/Src/sysmem.c \
../Core/Src/system_stm32h7xx.c
OBJS += \
./Core/Src/freertos.o \
./Core/Src/main.o \
./Core/Src/stm32h7xx_hal_msp.o \
./Core/Src/stm32h7xx_hal_timebase_tim.o \
./Core/Src/stm32h7xx_it.o \
./Core/Src/syscalls.o \
./Core/Src/sysmem.o \
./Core/Src/system_stm32h7xx.o
C_DEPS += \
./Core/Src/freertos.d \
./Core/Src/main.d \
./Core/Src/stm32h7xx_hal_msp.d \
./Core/Src/stm32h7xx_hal_timebase_tim.d \
./Core/Src/stm32h7xx_it.d \
./Core/Src/syscalls.d \
./Core/Src/sysmem.d \
./Core/Src/system_stm32h7xx.d
# Each subdirectory must supply rules for building sources it contributes
Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk
arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
clean: clean-Core-2f-Src
clean-Core-2f-Src:
-$(RM) ./Core/Src/freertos.cyclo ./Core/Src/freertos.d ./Core/Src/freertos.o ./Core/Src/freertos.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32h7xx_hal_msp.cyclo ./Core/Src/stm32h7xx_hal_msp.d ./Core/Src/stm32h7xx_hal_msp.o ./Core/Src/stm32h7xx_hal_msp.su ./Core/Src/stm32h7xx_hal_timebase_tim.cyclo ./Core/Src/stm32h7xx_hal_timebase_tim.d ./Core/Src/stm32h7xx_hal_timebase_tim.o ./Core/Src/stm32h7xx_hal_timebase_tim.su ./Core/Src/stm32h7xx_it.cyclo ./Core/Src/stm32h7xx_it.d ./Core/Src/stm32h7xx_it.o ./Core/Src/stm32h7xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32h7xx.cyclo ./Core/Src/system_stm32h7xx.d ./Core/Src/system_stm32h7xx.o ./Core/Src/system_stm32h7xx.su
.PHONY: clean-Core-2f-Src

18
Debug/Core/Src/syscalls.cyclo
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@ -1,18 +0,0 @@
../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1
../Core/Src/syscalls.c:48:5:_getpid 1
../Core/Src/syscalls.c:53:5:_kill 1
../Core/Src/syscalls.c:61:6:_exit 1
../Core/Src/syscalls.c:67:27:_read 2
../Core/Src/syscalls.c:80:27:_write 2
../Core/Src/syscalls.c:92:5:_close 1
../Core/Src/syscalls.c:99:5:_fstat 1
../Core/Src/syscalls.c:106:5:_isatty 1
../Core/Src/syscalls.c:112:5:_lseek 1
../Core/Src/syscalls.c:120:5:_open 1
../Core/Src/syscalls.c:128:5:_wait 1
../Core/Src/syscalls.c:135:5:_unlink 1
../Core/Src/syscalls.c:142:5:_times 1
../Core/Src/syscalls.c:148:5:_stat 1
../Core/Src/syscalls.c:155:5:_link 1
../Core/Src/syscalls.c:163:5:_fork 1
../Core/Src/syscalls.c:169:5:_execve 1

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Debug/Core/Src/syscalls.d
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@ -1,94 +0,0 @@
Core/Src/syscalls.o: ../Core/Src/syscalls.c \
../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \
../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \
../LWIP/Target/lwipopts.h ../Core/Inc/main.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
../Core/Inc/stm32h7xx_hal_conf.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
../Drivers/CMSIS/Include/core_cm7.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv7.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
../Middlewares/Third_Party/LwIP/system/arch/cc.h \
../Middlewares/Third_Party/LwIP/system/arch/cpu.h
../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h:
../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
../LWIP/Target/lwipopts.h:
../Core/Inc/main.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
../Core/Inc/stm32h7xx_hal_conf.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
../Drivers/CMSIS/Include/core_cm7.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv7.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
../Middlewares/Third_Party/LwIP/system/arch/cc.h:
../Middlewares/Third_Party/LwIP/system/arch/cpu.h:

BIN
Debug/Core/Src/syscalls.o
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Binary file not shown.

18
Debug/Core/Src/syscalls.su
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@ -1,18 +0,0 @@
../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static
../Core/Src/syscalls.c:48:5:_getpid 4 static
../Core/Src/syscalls.c:53:5:_kill 16 static
../Core/Src/syscalls.c:61:6:_exit 16 static
../Core/Src/syscalls.c:67:27:_read 32 static
../Core/Src/syscalls.c:80:27:_write 32 static
../Core/Src/syscalls.c:92:5:_close 16 static
../Core/Src/syscalls.c:99:5:_fstat 16 static
../Core/Src/syscalls.c:106:5:_isatty 16 static
../Core/Src/syscalls.c:112:5:_lseek 24 static
../Core/Src/syscalls.c:120:5:_open 12 static
../Core/Src/syscalls.c:128:5:_wait 16 static
../Core/Src/syscalls.c:135:5:_unlink 16 static
../Core/Src/syscalls.c:142:5:_times 16 static
../Core/Src/syscalls.c:148:5:_stat 16 static
../Core/Src/syscalls.c:155:5:_link 16 static
../Core/Src/syscalls.c:163:5:_fork 4 static
../Core/Src/syscalls.c:169:5:_execve 24 static

1
Debug/Core/Src/sysmem.cyclo
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../Core/Src/sysmem.c:53:7:_sbrk 3

94
Debug/Core/Src/sysmem.d
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@ -1,94 +0,0 @@
Core/Src/sysmem.o: ../Core/Src/sysmem.c \
../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \
../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \
../LWIP/Target/lwipopts.h ../Core/Inc/main.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
../Core/Inc/stm32h7xx_hal_conf.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
../Drivers/CMSIS/Include/core_cm7.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv7.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \
../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \
../Middlewares/Third_Party/LwIP/system/arch/cc.h \
../Middlewares/Third_Party/LwIP/system/arch/cpu.h
../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h:
../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h:
../LWIP/Target/lwipopts.h:
../Core/Inc/main.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
../Core/Inc/stm32h7xx_hal_conf.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
../Drivers/CMSIS/Include/core_cm7.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv7.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h:
../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h:
../Middlewares/Third_Party/LwIP/system/arch/cc.h:
../Middlewares/Third_Party/LwIP/system/arch/cpu.h:

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Debug/Core/Src/sysmem.o
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Debug/Core/Src/sysmem.su
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@ -1 +0,0 @@
../Core/Src/sysmem.c:53:7:_sbrk 32 static

2
Debug/Core/Src/system_stm32h7xx.cyclo
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@ -1,2 +0,0 @@
../Core/Src/system_stm32h7xx.c:175:6:SystemInit 3
../Core/Src/system_stm32h7xx.c:340:6:SystemCoreClockUpdate 10

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@ -1,79 +0,0 @@
Core/Src/system_stm32h7xx.o: ../Core/Src/system_stm32h7xx.c \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
../Drivers/CMSIS/Include/core_cm7.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv7.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
../Core/Inc/stm32h7xx_hal_conf.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h:
../Drivers/CMSIS/Include/core_cm7.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv7.h:
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
../Core/Inc/stm32h7xx_hal_conf.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:

BIN
Debug/Core/Src/system_stm32h7xx.o
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2
Debug/Core/Src/system_stm32h7xx.su
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@ -1,2 +0,0 @@
../Core/Src/system_stm32h7xx.c:175:6:SystemInit 16 static
../Core/Src/system_stm32h7xx.c:340:6:SystemCoreClockUpdate 48 static

2
Debug/Core/Startup/startup_stm32h723vghx.d
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@ -1,2 +0,0 @@
Core/Startup/startup_stm32h723vghx.o: \
../Core/Startup/startup_stm32h723vghx.s

BIN
Debug/Core/Startup/startup_stm32h723vghx.o
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27
Debug/Core/Startup/subdir.mk
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@ -1,27 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (11.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
S_SRCS += \
../Core/Startup/startup_stm32h723vghx.s
OBJS += \
./Core/Startup/startup_stm32h723vghx.o
S_DEPS += \
./Core/Startup/startup_stm32h723vghx.d
# Each subdirectory must supply rules for building sources it contributes
Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk
arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -DDEBUG -c -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
clean: clean-Core-2f-Startup
clean-Core-2f-Startup:
-$(RM) ./Core/Startup/startup_stm32h723vghx.d ./Core/Startup/startup_stm32h723vghx.o
.PHONY: clean-Core-2f-Startup

14
Debug/Drivers/BSP/Components/lan8742/lan8742.cyclo
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@ -1,14 +0,0 @@
../Drivers/BSP/Components/lan8742/lan8742.c:63:10:LAN8742_RegisterBusIO 5
../Drivers/BSP/Components/lan8742/lan8742.c:88:10:LAN8742_Init 15
../Drivers/BSP/Components/lan8742/lan8742.c:188:9:LAN8742_DeInit 4
../Drivers/BSP/Components/lan8742/lan8742.c:213:9:LAN8742_DisablePowerDownMode 3
../Drivers/BSP/Components/lan8742/lan8742.c:243:9:LAN8742_EnablePowerDownMode 3
../Drivers/BSP/Components/lan8742/lan8742.c:273:9:LAN8742_StartAutoNego 3
../Drivers/BSP/Components/lan8742/lan8742.c:309:9:LAN8742_GetLinkState 15
../Drivers/BSP/Components/lan8742/lan8742.c:401:9:LAN8742_SetLinkState 7
../Drivers/BSP/Components/lan8742/lan8742.c:453:9:LAN8742_EnableLoopbackMode 3
../Drivers/BSP/Components/lan8742/lan8742.c:483:9:LAN8742_DisableLoopbackMode 3
../Drivers/BSP/Components/lan8742/lan8742.c:523:9:LAN8742_EnableIT 3
../Drivers/BSP/Components/lan8742/lan8742.c:563:9:LAN8742_DisableIT 3
../Drivers/BSP/Components/lan8742/lan8742.c:602:10:LAN8742_ClearIT 2
../Drivers/BSP/Components/lan8742/lan8742.c:632:9:LAN8742_GetITStatus 2

4
Debug/Drivers/BSP/Components/lan8742/lan8742.d
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@ -1,4 +0,0 @@
Drivers/BSP/Components/lan8742/lan8742.o: \
../Drivers/BSP/Components/lan8742/lan8742.c \
../Drivers/BSP/Components/lan8742/lan8742.h
../Drivers/BSP/Components/lan8742/lan8742.h:

BIN
Debug/Drivers/BSP/Components/lan8742/lan8742.o
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14
Debug/Drivers/BSP/Components/lan8742/lan8742.su
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@ -1,14 +0,0 @@
../Drivers/BSP/Components/lan8742/lan8742.c:63:10:LAN8742_RegisterBusIO 16 static
../Drivers/BSP/Components/lan8742/lan8742.c:88:10:LAN8742_Init 32 static
../Drivers/BSP/Components/lan8742/lan8742.c:188:9:LAN8742_DeInit 16 static
../Drivers/BSP/Components/lan8742/lan8742.c:213:9:LAN8742_DisablePowerDownMode 24 static
../Drivers/BSP/Components/lan8742/lan8742.c:243:9:LAN8742_EnablePowerDownMode 24 static
../Drivers/BSP/Components/lan8742/lan8742.c:273:9:LAN8742_StartAutoNego 24 static
../Drivers/BSP/Components/lan8742/lan8742.c:309:9:LAN8742_GetLinkState 24 static
../Drivers/BSP/Components/lan8742/lan8742.c:401:9:LAN8742_SetLinkState 24 static
../Drivers/BSP/Components/lan8742/lan8742.c:453:9:LAN8742_EnableLoopbackMode 24 static
../Drivers/BSP/Components/lan8742/lan8742.c:483:9:LAN8742_DisableLoopbackMode 24 static
../Drivers/BSP/Components/lan8742/lan8742.c:523:9:LAN8742_EnableIT 24 static
../Drivers/BSP/Components/lan8742/lan8742.c:563:9:LAN8742_DisableIT 24 static
../Drivers/BSP/Components/lan8742/lan8742.c:602:10:LAN8742_ClearIT 24 static
../Drivers/BSP/Components/lan8742/lan8742.c:632:9:LAN8742_GetITStatus 24 static

27
Debug/Drivers/BSP/Components/lan8742/subdir.mk
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@ -1,27 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (11.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../Drivers/BSP/Components/lan8742/lan8742.c
OBJS += \
./Drivers/BSP/Components/lan8742/lan8742.o
C_DEPS += \
./Drivers/BSP/Components/lan8742/lan8742.d
# Each subdirectory must supply rules for building sources it contributes
Drivers/BSP/Components/lan8742/%.o Drivers/BSP/Components/lan8742/%.su Drivers/BSP/Components/lan8742/%.cyclo: ../Drivers/BSP/Components/lan8742/%.c Drivers/BSP/Components/lan8742/subdir.mk
arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../FATFS/Target -I../FATFS/App -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Middlewares/Third_Party/FatFs/src -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I"C:/_NoSleep/STM32/TBD_TaxiBoard/LWFTPC" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
clean: clean-Drivers-2f-BSP-2f-Components-2f-lan8742
clean-Drivers-2f-BSP-2f-Components-2f-lan8742:
-$(RM) ./Drivers/BSP/Components/lan8742/lan8742.cyclo ./Drivers/BSP/Components/lan8742/lan8742.d ./Drivers/BSP/Components/lan8742/lan8742.o ./Drivers/BSP/Components/lan8742/lan8742.su
.PHONY: clean-Drivers-2f-BSP-2f-Components-2f-lan8742

54
Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo
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@ -1,54 +0,0 @@
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:134:19:HAL_Init 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:187:19:HAL_DeInit 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:228:13:HAL_MspInit 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:239:13:HAL_MspDeInit 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:262:26:HAL_InitTick 4
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:327:13:HAL_IncTick 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:338:17:HAL_GetTick 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:347:10:HAL_GetTickPrio 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:356:19:HAL_SetTickFreq 3
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:388:21:HAL_GetTickFreq 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:404:13:HAL_Delay 3
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:430:13:HAL_SuspendTick 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:446:13:HAL_ResumeTick 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:456:10:HAL_GetHalVersion 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:465:10:HAL_GetREVID 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:474:10:HAL_GetDEVID 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:483:10:HAL_GetUIDw0 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:492:10:HAL_GetUIDw1 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:501:10:HAL_GetUIDw2 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:520:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:536:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:548:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:560:19:HAL_SYSCFG_EnableVREFBUF 3
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:586:6:HAL_SYSCFG_DisableVREFBUF 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:600:6:HAL_SYSCFG_ETHInterfaceSelect 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:630:6:HAL_SYSCFG_AnalogSwitchConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:648:6:HAL_SYSCFG_EnableBOOST 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:660:6:HAL_SYSCFG_DisableBOOST 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:676:6:HAL_SYSCFG_CM7BootAddConfig 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:775:6:HAL_EnableCompensationCell 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:786:6:HAL_DisableCompensationCell 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:799:6:HAL_SYSCFG_EnableIOSpeedOptimize 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:815:6:HAL_SYSCFG_DisableIOSpeedOptimize 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:832:6:HAL_SYSCFG_CompensationCodeSelect 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:849:6:HAL_SYSCFG_CompensationCodeConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:883:6:HAL_SYSCFG_ADC2ALT_Rout0Config 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:898:6:HAL_SYSCFG_ADC2ALT_Rout1Config 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:911:6:HAL_DBGMCU_EnableDBGSleepMode 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:920:6:HAL_DBGMCU_DisableDBGSleepMode 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:930:6:HAL_DBGMCU_EnableDBGStopMode 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:939:6:HAL_DBGMCU_DisableDBGStopMode 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:948:6:HAL_DBGMCU_EnableDBGStandbyMode 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:957:6:HAL_DBGMCU_DisableDBGStandbyMode 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1023:6:HAL_EnableDomain3DBGStopMode 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1032:6:HAL_DisableDomain3DBGStopMode 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1043:6:HAL_EnableDomain3DBGStandbyMode 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1052:6:HAL_DisableDomain3DBGStandbyMode 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1064:6:HAL_SetFMCMemorySwappingConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1076:10:HAL_GetFMCMemorySwappingConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1093:6:HAL_EXTI_EdgeConfig 3
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1119:6:HAL_EXTI_GenerateSWInterrupt 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1134:6:HAL_EXTI_D1_ClearFlag 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1169:6:HAL_EXTI_D1_EventInputConfig 5
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1263:6:HAL_EXTI_D3_EventInputConfig 3

80
Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d
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@ -1,80 +0,0 @@
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o: \
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
../Core/Inc/stm32h7xx_hal_conf.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \
../Drivers/CMSIS/Include/core_cm7.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv7.h \
../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
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../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1085:19:FLASH_OB_WaitForLastOperation 24 static
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1124:19:FLASH_CRC_WaitForLastOperation 24 static

30
Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo
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@ -1,30 +0,0 @@
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:176:19:HAL_FLASHEx_Erase 11
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:293:19:HAL_FLASHEx_Erase_IT 8
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:414:19:HAL_FLASHEx_OBProgram 14
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:557:6:HAL_FLASHEx_OBGetConfig 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:625:19:HAL_FLASHEx_Unlock_Bank1 3
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:647:19:HAL_FLASHEx_Lock_Bank1 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:700:19:HAL_FLASHEx_ComputeCRC 6
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:848:13:FLASH_MassErase 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:925:6:FLASH_Erase_Sector 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:982:13:FLASH_OB_EnableWRP 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1017:13:FLASH_OB_DisableWRP 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1056:13:FLASH_OB_GetWRP 3
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1102:13:FLASH_OB_RDPConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1119:17:FLASH_OB_GetRDP 3
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1175:13:FLASH_OB_UserConfig 11
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1363:17:FLASH_OB_GetUser 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1397:13:FLASH_OB_PCROPConfig 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1446:13:FLASH_OB_GetPCROP 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1482:13:FLASH_OB_BOR_LevelConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1499:17:FLASH_OB_GetBOR 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1514:13:FLASH_OB_BootAddConfig 3
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1552:13:FLASH_OB_GetBootAdd 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1636:13:FLASH_OB_SecureAreaConfig 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1678:13:FLASH_OB_GetSecureArea 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1711:13:FLASH_CRC_AddSector 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1743:13:FLASH_CRC_SelectAddress 2
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1804:13:FLASH_OB_SharedRAM_Config 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1818:17:FLASH_OB_SharedRAM_GetConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1831:13:FLASH_OB_CPUFreq_BoostConfig 1
../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1845:17:FLASH_OB_CPUFreq_GetBoost 1

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